Recording medium, signal recording apparatus thereof, and signal reproducing apparatus thereof

Abstract: A recording medium having a SYNC (synchronous code) for synchronizing with data and a DCC (DC cancel code) for suppressing a DC component of a wave form of a signal recorded on the recording medium, the SYNC and the CDD being adjacently recorded on the recording medium. Both the SYNC and DCC are patterns that are not present in a data portion. A signal recording apparatus, comprising a DSV calculating means (42) for calculating a DSV of a signal wave form recorded on the recording medium (D), a cancel code generating means (43) for generating a cancel code for suppressing a DC component of the signal wave form corresponding to the DSV calculated by the DSV calculating means, and a recording means (44,45,46) for connecting a synchronous code and record data to the cancel code generated by the cancel code generating means and recording the cancel code, the synchronous code, and the record data on the recording medium so that the cancel code and the synchronous code are adjacently disposed, the synchronous code being adapted for synchronizing with data.

Description: The present invention relates to a recording medium such as an optical disc, a signal recording apparatus thereof, and a signal reproducing apparatus thereof. When digital data is highly densely recorded on a recording medium such as an optical disc, the digital data should be modulated with a large value of the minimum code inversion length Tmin so as to record as much data in a limited bit length as possible. To do that, in recent years, as a modulation system with a large value of the minimum code inversion length Tmin, 4-9 modulation system has been proposed. The 4-9 modulation system is described in for example Japanese Patent Application No. 5-76692. The 4-9 modulation system converts 4-bit data into 9-bit data. In the 4-9 modulation system, the minimum code inversion length Tmin is 4T (where T is a bit length) and the maximum code inversion length Tmax is 18T. Fig. 9 is a schematic diagram showing the construction of a code conversion table for the 4-9 modulation system. In Fig. 9, Dn is a value of which an input binary data sequence is divided by every four bits and represented in hexadecimal (HEX) notation. T n is a binary bit pattern in which the input D n is converted into 9 bits and at least three "0s" are present between two bit "1s". Due to the relation between D n and D n+1 , two or three T n patterns are provided. Depending on the value of D n+1 , the pattern of T n is determined. When D n = 5, T n is either "000000100" or "000010001". When D n+1 is 6, 7, 8, D, or F, T n is "000010001". Otherwise, T n is "000000100". When T n is "000000100", depending on D n+1 , D n+2 also corresponds to the table of case (1). As a practical example, when D is 5, 6, or 7, "000010001", "000000000", or "100001000" can be obtained, respectively. When data is recorded on the recording medium, the resultant 4-9 modulation code is modulated corresponding to NRZI (Non-Return to Zero Inverted) technique. On the other hand, when data is reproduced from the recording medium, a synchronous code should be regularly recorded on the recording medium so as to read data, byte by byte. The synchronous code is hereinafter referred to as SYNC. The SYNC is a predetermined pattern that is not present in data portion. In the 4-9 modulation system or the like, the signal that has been modulated corresponding to the NRZI technique contains a DC component. To suppress the DC component, a DC cancel code (DCC) is added to the data portion. Fig. 10 shows the construction of a sector of a conventional optical disc. Fig. 11 shows the construction of a data portion of Fig. 10. As shown in these drawings, each sector is composed of an address portion 1 and a DATA/ECC portion 2. The SYNCs 3 and the DCCs 4 are regularly placed in at least the DATA/ECC portion 2. The DATA/ECC portion 2 is composed of a plurality of blocks, each of which has a predetermined bit length. Fig. 12 shows the relation of positions of the SYNC 3 and the DCC 4 of Fig. 11. As shown in Fig. 12, data is placed between the SYNC 3 and the DCC 4. The signal length of the SYNC 3 is 36 bits. The signal length of the DCC 4 is 9 bits. Although the DCC 4 is an essential code for suppressing the DC component of the wave form of a signal recorded on the disc, the data recording area of the DATA/ECC portion 2 is correspondingly decreased, thereby obstructing the high dense recording of the recording medium. The prior art document "The Art of Digital Audio", J. Watkinson, Focal Press, revised reprint, 1989, pages 471-490, discloses a CD data block with a synchronous pattern and 3 packaging bits for suppressing a DC component. The synchronous pattern and the 3 packaging bits are recorded adjacently in the DC data block. The synchronous pattern of the CD block has a bit length of 22 T and the packaging has a bit length of 3 T. The block length of one block of the data blocks is 17 T. The further prior art document Patent Abstracts of Japan, Vol. 12, No. 162 (E-609) & JP62272726 describes an encoding circuit which provides two kinds of synchronous signals in advance and selects one of the two kinds of synchronous signals for each line to decrease a DC component. The two synchronous signals of figure 6 of this document differ only in their second bit, as is also the case in figure 5 of the present application. The present invention provides a recording medium, a signal recording method, a signal reproducing method and a signal reproducing apparatus according to claims 1 to 4. Fig. 1 is a schematic diagram showing the construction of a DATA/ECC portion in a sector format of an optical disc according to an embodiment of the present invention; Fig. 2 is a schematic diagram showing the relation of the positions of a SYNC and a DCC in the DATA/ECC portion of Fig. 1; Fig. 3 is a schematic diagram showing patterns of the SYNC and the DCC; Fig. 4 is a block diagram showing the construction of a signal recording apparatus according to the present invention; Fig. 5 is a schematic diagram for explaining a calculating method of DSV and a determining method of DCC for two types of DCC values (a and b); Fig. 6 is a block diagram showing the construction of a signal reproducing apparatus according to the present invention; Fig. 7 is a block diagram showing the construction of a SYNC detecting circuit; Fig. 8 is a block diagram showing the construction of a synchronous pattern detecting portion according to another embodiment of the present invention; Fig. 9 is a schematic diagram showing the construction of a code conversion table for 4-9 modulation system; Fig. 10 is a schematic diagram showing the construction of a sector of a conventional optical disc; Fig. 11 is a schematic diagram showing the construction of a data portion of Fig. 10; and Fig. 12 is a schematic diagram showing the relation of the positions of a SYNC and a DCC of Fig. 11 and signal lengths thereof. Next, with reference to the accompanying drawings, embodiments of the present invention will be described. Fig. 1 is a schematic diagram showing the construction of a DATA/ECC portion in a sector format of an optical disc according to an embodiment of the present invention. Fig. 2 is a schematic diagram showing the relation of the positions of a SYNC (synchronous code) and a DCC (DC cancel code) in the DATA/ECC portion of Fig. 1 and signal lengths thereof. As shown in Figs. 1 and 2, at the beginning of each frame of the DATA/ECC portion, the SYNC 13 and the DCC 14 are adjacently disposed. In other words, at the beginning of the frame, the DCC 14 is disposed. The DCC 14 is followed by the SYNC 13. The signal length of the SYNC 13 is 27 bits. The signal length of the DCC 14 is 9 bits. Thus, the total signal length of the SYNC 13 and the DCC 14 is 36 bits. Fig. 3 is a schematic diagram showing patterns of the SYNC 13 and the DCC 14. Referring to Fig. 3, in the "*" portion, the value of "0" or "1" is placed. The SYNC 13 and the DCC 14 are represented with predetermined patterns that are not present in the data portion, namely the 4-9 modulation code. Thus, a continuous pattern composed of the SYNC 13 and the DCC 14 can be treated as a single SYNC pattern. In this example, as a pattern that is not present in the data portion, a pattern with the code inversion lengths for 17T, 4T, 4T and 6T is used. Thus, in the optical disc according to this embodiment, since the continuous pattern composed of (SYNC 13 + DCC 14) can be treated as a single SYNC pattern, the signal length of the SYNC 13 can be reduced for the signal length of the DCC 14, thereby improving the recording density without deteriorating the function of the DCC 14. Next, a signal recording apparatus that records the continuous pattern composed of the SYNC 13 and the DCC 14 will be described. Fig. 4 is a block diagram showing the construction of a signal recording apparatus according to the present invention. Referring to Fig. 4, the signal recording apparatus comprises a data modulating portion 41, a DSV calculating portion 42, a DCC determining portion 43, a sector composing portion 44, an NRZI modulating portion 45, and a signal recording portion 46. The data modulating portion 41 performs the 4-9 modulation for the input data and supplies a 4-9 modulation signal to the DSV calculating portion 42 and the sector composing portion 44. The DSV calculating portion 42 calculates a DSV (Digital Sum Value) corresponding to the input 4-9 modulation signal and supplies the DSV to the DCC determining portion 43. The DSV is obtained, block by block (for example, as blocks of D1 to D10, D11 to D20, and D21 to D30 of Fig. 1). Whenever the DSV is obtained, the DCC is determined. For example, as shown in Fig. 5, now assume that two DCC values ("010001000" and "000001000") are used so as to calculate DSVs for these values. Thereafter, the absolute values of the DSVs are compared and the DCC with the smaller absolute value is determined as the DCC 14 to be recorded. The sector composing portion 44 adds the determined DCC 14 to the record data along with the SYNC 13. Thereby the sector format shown in Fig. 1 is composed. Thereafter, the NRZI modulating portion 45 performs the NRZI modulation for the 4-9 modulation signal composed of the DCC 14, the SYNC 13, and the record data. The signal recording portion 46 records the 4-9 modulation signal on a recording medium (optical disc) D. Next, a signal reproducing apparatus that reproduces a signal from the recording medium will be described. Fig. 6 is a block diagram showing the construction of the signal reproducing apparatus. Referring to Fig. 6, the signal reproducing apparatus comprises a signal reading portion 61, an NRZI demodulating portion 62, a sector decomposing portion 63, a synchronous code extracting portion 64, a data synchronizing portion 65, and a data demodulating portion 66. The signal reading portion 61 reads a signal that has been recorded on a recording medium D and supplies the signal to the NRZI demodulating portion 62. The NRZI demodulating portion 62 performs NRZI demodulation for the read signal and supplies the demodulation signal that is a 4-9 modulation signal to the sector decomposing portion 63. The sector decomposing portion 63 extracts a data portion from the 4-9 modulation signal that composes the sector format and supplies the data portion to the data demodulating portion 66. The synchronous code extracting portion 64 extracts DCC 14 + SYNC 13 from the 4-9 modulation signal and supplies them to the data synchronizing portion 65. The data synchronizing portion 65 includes a SYNC detecting circuit. The SYNC detecting circuit detects a significant SYNC pattern necessary for synchronizing with data from DCC 14 + SYNC 13. The SYNC detecting circuit will be described later in more detail. The data synchronizing portion 65 generates a data extracting timing for the data demodulating portion 66 corresponding to the detected result of the SYNC pattern so that the data demodulating portion 66 performs the 4-9 demodulation for the data, byte by byte. Thus, reproduced data is output. Fig. 7 is a schematic diagram showing a construction of the SYNC detecting circuit. The SYNC detecting circuit comprises a shift register and some logic gates. In other words, the SYNC detecting circuit inputs serial data that has been NRZI demodulated whenever a bit clock takes place. When the input pattern accords with the above-described SYNC pattern, the SYNC detecting circuit outputs a SYNC detection signal. Tables 1 and 2 show pairs (a) to (j') of the significant SYNC pattern and detected bit sequences. The upper row of each pair represents the significant SYNC pattern composed of 36 bits of DCC + SYNC. The lower row of each pair represents part of the significant SYNC pattern. For example, the lower row of the pair (a) represents that 26 bits other than the high order five bits and the low order five bits of the significant SYNC pattern composed of 36 bits of DCC + SYNC are detected bits of the significant SYNC pattern. The 26-bit pattern is the minimum required number of bits for pattern comparison since the first bit is an inversion point of the value of the DCC and the last bit is the start bit of a sequence of 6T of the pattern of sequences of 17T, 4T, 4T, and 6T (that are not present in the data portion). The lower row of the pair (j') represents that all bits of DCC + SYNC are detected bits of the significant SYNC pattern. In other words, a bit sequence as the significant SYNC pattern can be selected from the minimum bit number of the lower row of the pair (a) in Table 1 to all the bits of DCC + SYNC of the lower row of the pair (j') of Table 2. In this embodiment, the DCC 14 is disposed at the first block of frames that contain the SYNC 13. In addition, the DCC 14 is disposed at the beginning of each block. Conventionally, the DCC is added so as to suppress the DC component when a signal is recorded. Thus, when data is reproduced, the DCC is not necessary. According to the present invention, since the DCC 14 is disposed at the beginning of each block along with the first block, the DCC 14 can be used as auxiliary information that allows data to be synchronized between each SYNC 13. Thus, even if the SYNC 13 cannot be detected due to a burst error and thereby data cannot be synchronized, with the DCC 14 of each block, the data can be synchronized. Consequently, the synchronism restoring time can be more shortened than the case that data is synchronized with only the SYNC pattern. When the synchronism restoring time is shortened, the amount of data that is processed can be increased and the reliability of the data can be improved. When only the SYNC pattern is used, an incorrectable error may take place. However, when data is synchronized using the DCC 14 of each block, the probability of which the error is corrected is increased. The situation that the error cannot be corrected is remarkably reduced, thereby reducing the load applied to the error correcting side. In the embodiment, a significant SYNC pattern contained in the continuous pattern of SYNC 13 + DCC 14 is detected so as to synchronize with data. However, as shown in Fig. 8, not only the SYNC pattern, but a pattern of the DCC 14 may be detected so as to synchronize with data. In Fig. 8, reference numeral 81 is a SYNC pattern detecting portion. As with the above-described SYNC detecting circuit, the SYNC pattern detecting portion 81 detects a significant SYNC pattern contained in the continuous pattern of SYNC 13 + DCC 14 and supplies the detected signal to an AND gate 82. Reference numeral 83 is a DCC pattern detecting portion that detects only a pattern of the DCC 14 and outputs the detected signal to the AND gate 82. Thus, in this construction, only when both the patterns of the SYNC 13 and the DCC 14 are detected, the SYNC is detected. Consequently, the accuracy of detecting the SYNC is raised and thereby the reliability of synchronism of data can be improved. In the first embodiment, the SYNC pattern contains a sequence of a code inversion length for 17T. However, the SYNC pattern may contain a sequence of a code inversion length for 18T. In the first embodiment, the 4-9 modulation system is used. However, as long as the sector format contains the SYNC 13 and the DCC 14, a variety of modulation systems such as another RLL (Run Length Limited) modulation system may be applied to the present invention. In the first embodiment, the DCC 14 is disposed at the beginning of each frame and followed by the SYNC 13. However, the SYNC 13 may be disposed at the beginning of each frame and followed by the DCC 14.

Claims: A recording medium being divided in a plurality of frames, each frame containing a plurality of rows, comprising; a code sequence which has a first code and a second code, the first code being adapted for suppressing a DC component of a signal wave form recorded on that recording medium, the second code being adapted for synchronizing data, the first code and the second code being adjacently recorded at the beginning of a first row of each frame, characterized in that : the first code is recorded at the beginning of each other row of the frames without the second code. A signal recording method for the recording medium as set forth in claim 1, for recording a code sequence which has a first code and a second code, the first code being adapted for suppressing a DC component of a signal wave form recorded on that recording medium, the second code being adapted for synchronizing data, the first code and the second code being adjacently recorded at the beginning of a first row of each frame, characterized in that : the first code is recorded at the beginning of each other row of the frames without the second code. A signal reproducing method for reproducing data from the recording medium as set forth in claim 1, the recording medium comprising a code sequence which has a first code and a second code, the first code being adapted for suppressing a DC component of a signal wave form recorded on that recording medium, the second code being adapted for synchronizing data, the first code and the second code being adjacently recorded at the beginning of a first row of each frame, characterized in that : the first code is recorded at the beginning of each other row of the frames without the second code. A signal reproducing apparatus for reproducing data from the recording medium as set forth in claim 1, the recording medium comprising a code sequence which has a first code and a second code, the first code being adapted for suppressing a DC component of a signal wave form recorded on that recording medium, the second code being adapted for synchronizing data, the first code and the second code being adjacently recorded at the beginning of a first row of each frame, characterized in that : the first code is recorded at the beginning of each other row of the frames without the second code.

Inventors: NABESHIMA DAIKI, OZAKI NAOKI, NABESHIMA, DAIKI, OZAKI, NAOKI, NABESHIMA, DAIKI, C/O INT. PROP. DIV. K.K. TOSHIBA, OZAKI, NAOKI, C/O INT. PROP. DIV. K.K. TOSHIBA
Applicants: TOSHIBA AVE KK, TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA, TOSHIBA AVE CO., LTD
Application year: 1995
Main classification: G11B20
IPC codes: G11B20, G11B7, G11B27, H03M5