Vertical MOS semiconductor device

Abstract: To reduce the mutual interference between a main cell portion (6) and a sensing cell portion (7) for detecting the current flowing through the main cell portion (6) of a vertical MOS semiconductor device and to improve the accuracy and reliability of the overcurrent detection, well regions (17, 18) of (p) type are formed between the main (6) and sensing (7) cell portions to capture the minority carriers. The breakdown of the gate oxide film (11) caused by the open emitter electrode (M, 15) of the sensing cell portion (7) is prevented by forming the (p) type well regions (17, 18) with ring shapes, spacing the (p) type well regions (17, 18) by 5 to 20µm, and by adjusting the isolation withstand voltage between the main and sensing cell portions (6, 7) to below the withstand voltage of the gate oxide film (11). The spike noise voltage is avoided by reducing the overlapping area of the detecting and gate electrodes so as to reduce the capacitance between the detecting (15) and gate (12) electrodes.

Description: The present invention relates to power semiconductor devices, and particularly concerns semiconductors having a MOS gate such as are conventionally used in inverters etc. Insulated gate bipolar transistors (hereinafter referred to as "IGBT") and power MOS field effect transistors (hereinafter referred to as "MOSFET") are voltage driven semiconductor switching elements, and are used widely in power electronics by virtue of their low on-voltage and high switching speed. When a fault such as a surge current at the start of a motor, a load short-circuit, an arm short-circuit, etc. occurs, the switching elements such as IGBTs etc. in the inverter are subjected to a high voltage and large current. The characteristics for evaluating the switching elements in relation to such a heavy electrical burden include the breakdown withstand capability called "short-circuit withstand capability". Although a protecting circuit for detecting short-circuit faults and for interrupting the power supply is conventionally incorporated in inverters and the like, it takes 10 to 20µsec for the protecting circuit to operate after detecting an overcurrent. Therefore, the IGBTs are required not to break down during this period. To meet this requirement, an overcurrent protecting means has been adopted recently in high performance IGBT modules in addition to the above described protecting circuit. The overcurrent protecting means detects the overcurrent quickly, and limits and suppresses the IGBT current to below the short-circuit withstand capability of the IGBTs by controlling the gates of the IGBTs based on the overcurrent detection signal before the protecting circuit interrupts the power supply. Figure 6 is a circuit diagram showing an example of an overcurrent protecting circuit for the IGBTs (cf. Japanese Laid Open Patent Application number H02-66975). In Figure 6, the reference numeral 1 designates a main element (main IGBT) and 2 designates a subsidiary element for current detection (an IGBT different from the main IGBT) connected in parallel to the main element 1. A current detecting resistor 3 R S is connected in series with the subsidiary element 2, and a switching element 4 (a MOSFET is shown in the Figure) is connected to the gate driver circuits of the elements 1 and 2. The switching element 4 turns on or off in correspondence to the voltage across the resistor 3. When the overcurrent caused by a load circuit fault etc. flows through the elements 1 and 2 to boost the voltage across the resistor 3 above the threshold voltage of the switching element 4, the switching element 4 is turned on to lower the gate voltages of the main and subsidiary elements 1 and 2 and thus limits the main current flowing through the main element 1. By setting the resistance of the resistor 3 and the threshold voltage of the switching element 4 respectively at appropriate values, the main current flowing through the main element 1 to be protected is limited to a value within the short-circuit withstand capability. Figure 7 is a graph showing a main current I D and a voltage V D across the main element 1 at a power supply voltage of 400 V while the protecting circuit of Figure 6 acts to limit an overcurrent caused by a load short-circuit fault. In Figure 7, the main element 1 is an IGBT (ratings: 600V, 100A) externally connected to the above described ' protecting circuit. As can be seen from Figure 7, the main current I D of the IGBT is limited in several µsec to about 250A corresponding to the short-circuit withstand capability set with respect to the rated current of 100A. In the above described overcurrent protecting circuit including an IGBT as the subsidiary detecting element 2 and constructed as an external circuit to the IGBT to be protected as the main element 1, it is difficult to secure proportionality between the operations of the elements 1 and 2 because of temperature differences between the chips on which the elements 1 and 2 are individually mounted. To overcome this problem, it has been proposed to form the elements 1 and 2 in a common chip. For example, US Patent 4,783,690 addresses the problem of the temperature difference between the elements 1 and 2 by assigning some of the cells constituting a main MOSFET to the role of sensing cells for overcurrent detection, and by leading an electrode for the overcurrent detection out from the sensing cells. However, the following problems have been left unsolved by the structure proposed by US Patent 4,783,690: (1) Since a current leaks through a parasitic lateral MOSFET caused between the main and the sensing cell portions, the actual ratio of the main current and the current for overcurrent detection deviates from the designed value. (2) Since the main cells and the sensing cell portions are adjoining, a leakage current is caused by minority carriers between the main and sensing cell portions, for example, in the application of the MOSFET to a parasitic diode, an IGBT, etc. to which the minority carriers commit. This leakage current further causes deviation of the actual ratio of the main current and the current for overcurrent detection from the designed value. To overcome these problems, a method has been proposed in European Patent Application number 95301349.7 for reducing the leakage current by expanding the spacing between the main and the sensing cell portions. Figure 8 is a sectional view showing a part of an exemplary IGBT device according to the above identified European Patent Application. In Figure 8, a (p) type base region 9 is formed selectively on the surface of an (n) type base layer 8. An (n) type emitter region 10 is formed in the surface of the (p) type base region 9. A gate electrode 12 connected to a gate terminal G is fixed via a gate oxide film 11 to the surface of that portion of the (p) type base region 9 extending between the (n) type base layer 8 and the (n) type emitter region 10. An emitter electrode is fixed via an insulating film 20 to the surface of the device. The emitter electrode is divided into a main emitter electrode 14 for a main cell portion 6 and a sensing emitter electrode 15 for a sensing cell portion 7. The main emitter electrode 14 is connected to a terminal E and the sensing emitter electrode 15 is connected to a terminal M. A collector electrode 16 connected to a terminal C is fixed to the back surface of a semiconductor substrate 19. The main cell portion 6 and the sensing cell portion 7, describing more strictly the nearest parts of adjacent channel regions 13 and 13 of the main and sensing cell portions 6 and 7, are spaced by a spacing L of 100µm or more. This distance is long enough to prevent mutual interference between the main and sensing cell portions 6 and 7. Further, a (p) type well 17, to which the emitter electrode 14 of the main cell portion 6 is fixed, is formed between the main and sensing cell portions 6 and 7 to capture the minority carriers (holes). However, it has been revealed, through research and development of the device proposed in the European Patent Application number 95301349.7, that the pertinent problems still remain unsolved, in that: (1) The leakage current through the parasitic lateral MOSFET between the main and the sensing cell portions still causes some deviation of the actual ratio of the main current and the current for overcurrent detection from the designed value. (2) The adjoining main and sensing cell portions cause leakage current by minority carriers between the main and sensing cell portions, for example, in the application of the MOSFET to a parasitic diode, an IGBT, etc. to which the minority carriers commits. This leakage current further causes deviation of the actual ratio of the main current and the current for overcurrent detection from the designed value. In addition, the following problems should not be neglected. (3) When the main and sensing cell portions are simply spaced wide apart to prevent the leakage current, the wide spacing renders a considerable area of the chip unusable and thus increases the cost of the device. (4) In MOS semiconductor devices having a main cell portion and a sensing cell portion, the sensing cell portion may be broken down by the disconnection of the current detecting resistor when a high voltage is applied between the source and drain or between the collector and emitter when the device is in the off state. This breakdown will be explained with reference to Figures 9(a) and 9(b). Figure 9(a) is a circuit diagram showing an equivalent circuit of the IGBT having the main cell portion 6 and the sensing cell portion 7. In Figure 9(a), a high voltage is applied between the collector C and emitter E of the IGBT, and the emitter terminal M of the sensing cell 7 is in the open state. Figure 9(b) is a sectional view of a part of the IGBT in which the main cell portion 6 and the sensing cell portion 7 adjoin one another. In Figures 9(a) and 9(b), the voltage between the collector and the emitter (between the terminals C and E, and between the terminals C and M) of the main cell portion 6 and the sensing cell portion 7 is determined by the collector potential when the junction leakage currents I rE and I rM flow. Since the emitter electrode E of the main cell portion is grounded while the emitter electrode M of the sensing cell portion is open, the potential of the emitter electrode E rises gradually. In response to this potential rise, the voltage between the emitter terminal M and the gate terminal G of the sensing cell portion rises. When the voltage between the terminals M and G greatly exceeds the withstand voltage of the gate oxide film 11, the gate oxide film 11 is finally broken down in the region indicated by the circle B in Figure 9(b). (5) In MOS semiconductor devices having a main cell portion and a sensing cell portion, a spike noise voltage occasionally occurs across the current detecting resistor at the instant when the MOS semiconductor device is turned on. This spike noise voltage will now be explained with reference to Figures 10(a) and 10(b). Figure 10(b) is a circuit diagram showing an equivalent circuit of the IGBT which is connected to a load and turned on and off. In Figure 10(b), a resistor R S for detecting a current I C is connected between the emitter terminals M and E of the sensing and main cell portions 7 and 6. The current I C is measured by detecting a voltage V S across the resistor R S . Figure 10(a) is a graph of voltage and current against time showing the wave form of the gate voltage V G , the current I C , and the detecting voltage V S during the operation of the circuit of Figure 10(b). Though the voltage V S should be proportional to the current I C , a spike noise is caused on the voltage V S at the turning-on of the IGBT. The spike noise is caused by the capacitance C GM between the gate electrode G and the emitter terminal M of the sensing cell portion 7. In response to the rapid rise of the gate voltage V G at the turning-on of the IGBT, a displacement current i GM flows through the capacitor C GM . i GM = C GM .dV G /dt The current j GM causes the voltage V S expressed by equation 2 across the resistor R S . V S =i GM .R S = C GM .R S .dV G /dt That is, the voltage is caused in proportion to the capacitance C GM between the gate electrode G and the emitter electrode M of the sensing cell portion 7 and the rising rate of the gate voltage V G . In view of the foregoing, the object of the present invention is to provide a MOS semiconductor device having a current detecting function which facilitates maintaining the ratio between the main and detecting currents at a constant value, preventing the breakdown at the open terminal or at the turning-on of the device, and protecting the device from the overcurrent stably in combination with an overcurrent protecting circuit. European Patent Application 0 557 126 discloses a power semiconductor device. A large sense voltage is produced by the semiconductor device. The semiconductor device, utilizing current mirror techniques, is comprised of a power MOSFET having a plurality of power cells and a plurality os sense cells formed in a semiconductor epitaxial layer. The large sense voltage is provided by isolating and separating the plurality of power cells from the plurality of sense cells by at least the thickness of the semiconductor epitaxial layer . Isolation can be provided by forming a plurality of inactive cells or an elongated cell between the plurality of power cells and the plurality of sense cells. In addition, high voltage capabilities can be maintained by including a partially active region adjacent the plurality of power cells to provide for good termination. DE 41 09 183 (corresponding to US 5,097,302) discloses a power MOS-type semiconductor device with a current detection terminal, a first number of main MOSFET elements are connected to one another in parallel, and a second number of detection MOSFET elements are similarly connected to one another. First and second terminals of the main and detection MOSFET elements are commonly connected. A third terminal of one of the detection MOSFET elements is used as the current detection terminal. The current or voltage measured at this detection terminal is substantially proportional to the ratio of the first number to the second number. To this end, the parasitic resistance in the device is increased so as to inhibit a leak current from flowing therethrough. Moreover, the ON resistance of each of the detection MOSFET elements is designed to be lower than that of a main MOSFET element by an amount which is a function of the first number and the detection resistance connected to the current detection terminal. Patent Abstracts of Japan vol. 018, No. 066 (E-1501), 3 February 1994 and JP 05 283705 A (NIPPONDENSO CO LTD), 29 October 1993 discloses a power DMOS semiconductor device with which the current detection accuracy of DMOS at a detection part can be improved remarkably without extension of a manufacturing process. This is achieved by providing a ring-shaped well region which is formed on the surface of a semiconductor substrate by doping the impurities for a well region, is formed independent of the main well region and the sub-well region wherein the sub-well region is surrounded by the above-mentioned ring-shaped well region through a prescribed interval thus relaxing the electric field on the surface of the substrate. The ring-shaped aperture, which is formed into the shape surrounding the sub-well region by patterning gate electrodes, serves as the mask for formation of the ring-shaped well region when the impurities for well region are doped for formation of the main well region and the sub-well region. As a result, the irregularity in width of a part of the semiconductor substrate between the ring-shaped well region and the sub-well region can be prevented. Patent Abstracts of Japan vol.018, No. 213 (E-1538), 15 April 1994 and JP 06 013618 A (NIPPONDENSO CO LTD), 21 January 1994 provides a semiconductor device in which the reach-through breakdown voltage of elements in a detection part is increased as compared with a main current part. This is achieved in this semiconductor device by each element being composed of, for example, the cells of DMOS, IGBT and BPT, and one part acts as a detection part and the rest acts as a main current part. These detection part and main current part is provided with a high concentration substrate having a first conductivity type low concentration layer as common electrode in which a second conductivity type main well region and a sub-well region are formed on the surface part of the layer. A first conductivity type surface electrode region which makes the other electrode of the main current part is formed on the surface part of a main well region, and a first conductivity type surface electrode region which makes the other electrode of the detection part is formed on the surface part of the sub-well region. The sub-well region is formed more shallowly than the main well region in accordance with, for example, the narrowing of the width of open grooves of a mask, so that reach-through is brought about first in the main the current part in which the distance between the well region and the substrate is shorter and then is brought about in the detection part in which the distance is longer. None of the earlier disclosures referred to above refer to a problem which arises in MOS semiconductor devices which have a main cell portion and a sensing cell portion and in which the sensing cell portion may break down by the disconnection of the current detecting resistor when a high voltage is applied between the source and drain or between the collector and emitter when the device is in the off state. This problem is explained with reference to Figures 9(a) and 9(b) on page 4 and page 5 and the present invention provides a construction for overcoming this problem. According to the present invention a vertical MOS semiconductor device which comprises a main cell portion having a number of switching cells; a sensing cell portion for detecting a current of the main cell portion, each of the cell portions further comprising a semiconductor layer of a first conductivity type, a base region of a second conductivity type formed selectively on a first surface of the semiconductor layer, an emitter region of the first conductivity type formed selectively in the surface of the base region, a gate electrode formed on the portion of the base region extending between the semiconductor layer and the emitter region and connected thereto via a gate oxide film, and an emitter electrode contacting in common with the surfaces of the base region and the emitter region; and a first well region of the second conductivity type formed between the main and sensing cell portions, the first well region being connected with the emitter electrode of the sensing cell portion and characterised in that the insulation withstand voltage between the emitter electrodes of the main and sensing cell portions is preferably lower than the withstand voltage of the gate insulating film. It is preferable to shape the first well region as a ring. It is preferable to dispose an second well region of the second conductivity type between the main and sensing cell portions, the second well region being connected with the emitter electrode of the main cell portion. It is preferable to space the neighbouring first and second wells apart by a distance of from 5 to 20µm. The leakage current caused between the main and sensing cell portions by the minority carriers is greatly reduced by the disposition of the first and the second well regions of the second conductivity type between the main and sensing cell portions, since the first well region connected to the sensing cell portion captures the minority carriers diffusing from the sensing cell portion to the main cell portion and the second well region connected to the main cell portion captures the minority carriers diffusing from the main cell portion to the sensing cell portion. By shaping the first and the second well regions as rings, the efficiency with which the minority carriers are captured is improved. By shortening the spacing between the main and sensing cell portions, the chip area is reduced. By setting the isolation withstand voltage between the main and sensing cell portions at a value lower than the insulation breakdown withstand voltage of the gate insulating film, insulation breakdown of the gate oxide film is not caused, since the junction leakage current I rM flows from the source electrode of the sensing cell to the emitter electrode of the main cell to stop the potential rise of the emitter terminal M of the sensing cell as soon as the voltage between the emitter electrode terminal M and the gate electrode terminal G of the sensing cell portion, explained with reference to Figure 9(b), reaches the isolation withstand voltage between the emitter electrode terminals M and E of the sensing and main cell portions before the voltage between the emitter electrode terminal M and the gate electrode terminal G reaches the insulation breakdown withstand voltage of the gate oxide film. By setting the spacing between the first and second well regions, on which the isolation withstand voltage between the main and sensing cell portions greatly depends, at 20/µm or less, the isolation withstand voltage may be kept low, preferably at a value of about 20 V. The present invention will be explained hereinafter with reference to the accompanying drawings, which illustrate the preferred embodiments of the present invention. In the Figures: Figure 1 is a sectional view showing a first embodiment of an IGBT according to the present invention; Figure 2 is a top plan view of the first embodiment of the present invention; Figure 3 is a sectional view showing a second embodiment of an IGBT according to the present invention; Figure 4 is a top plan view of the second embodiment of the present invention; Figure 5(a) is a top plan view of a part of a third embodiment of an IGBT according to present invention; Figure 5(b) is a sectional view taken along the line A-A' of Figure 5(a) showing an upper part of the third embodiment; Figure 5(c) is a sectional view taken along the line B-B' of Figure 5(a) showing an upper part of the third embodiment; Figure 6 is a circuit diagram showing an exemplary overcurrent protecting circuit for IGBTs; Figure 7 is a graph showing a main current and a voltage V D across the main element 1 while the protecting circuit of Figure 6 is limiting an overcurrent; Figure 8 is a sectional view showing a part of an exemplary IGBT device according to the related application; Figure 9(a) is a circuit diagram showing an equivalent circuit of the IGBT having a sensing cell, the source electrode-terminal of which is open; Figure 9(b) is a sectional view of a part of the IGBT showing a breakdown point of the IGBT of Figure 9(a); Figure 10(a) is a graph for explaining the spike noise in the detected voltage V S ; and Figure 10(b) is a circuit diagram showing an equivalent circuit of the IGBT for explaining the cause of the spike noise in the detected voltage V S . Referring now to the drawings, Figure 1 is a sectional view showing a first embodiment of an IGBT according to the present invention. In Figure 1, the boundary region between the main cell portion 6 and the sensing cell portion 7 for current detection is shown. In Figure 1, very many cells are integrated in parallel connection with each other as the switching units on a semiconductor substrate 5. The main cell portion 6 is illustrated on the right hand side of the Figure, and the sensing cell portion on the left hand side. In Figure 1, a (p) type base region 9 is formed selectively in the surface of an (n) type base layer 8. An (n) type emitter region 10 is formed in the surface of the (p) type base region 9. A gate electrode 12 is fixed via a gate oxide film 11 to the surface of a channel region 13 formed in the surface layer in the portion of the (p) type base region 9 extending between the (n) type base layer 8 and the (n) type emitter region 10. An emitter electrode 14, 15 which contacts commonly with the surfaces of the (n) type emitter region 10 and the (p) type base region 9 is fixed to the surface of the device. The emitter electrode is divided into a main emitter electrode 14 for the main cell portion 6 and a sensing emitter electrode 15 for a sensing cell portion 7. A collector electrode 16 is fixed to the back surface of the semiconductor substrate 5. The main cell portion 6 and the sensing cell portion 7, describing more strictly the nearest channel regions 13 and 13 of the main and sensing cell portions 6 and 7, are spaced by a distance L of 100µm or more, to prevent mutual interference between the main and sensing cell portions 6 and 7 considering the diffusion length of the electrons supplied from the MOSFET and the minority carriers injected from a (p) type collector layer 19 to the (n) type base layer 8. A (p) type well 17 connected to the main emitter electrode 14 of the main cell portion and a (p) type well 18 connected to the sensing emitter electrode 15 of the sensing cell portion are formed between the main and sensing cell portions 6 and 7, to capture the minority carriers (holes in this example). The wells 17 and 18 are spaced by a distance L W of 20µm or less. The spacing L W is determined as follows: when the specific resistance of the (n) type base layer 8 is 50Ωcm, the width of the depletion layer expanding under the applied voltage of 20 V is 20µm. If the spacing L W is set at 20µm or less, the junction leakage current I rM of the sensing cell portion flows to the main cell side at the applied voltage of more than 20 V. Therefore, the potential of the sensing emitter electrode 15 is not boosted any more, and the gate oxide film 11 is prevented from breakdown. If the spacing L W is to narrow, the separation effect between the main and sensing cell portions 6 and 7 is insufficient. Thus, 5 to 20µm is appropriate for the spacing L W . Figure 2 is a top plan view of the first embodiment of the present invention in which the gate oxide film 11, the main and sensing emitter electrodes 14, 15 and their upper structure of Figure 1 are omitted. In Figure 2, the sensing cell portion 7 occupies the lower left part of the Figure. The (p) type well 18 for capturing the minority carriers is formed in a ring shape surrounding the sensing cell portion 7. The main cell portion 6 is located on the upper and right hand sides of the Figure. In the structure described above, (p) type well 18, electrically contacted with the sensing emitter electrode 15 captures minority carriers diffusing out from the sensing cell portion 7 to the main cell portion 6, and (p) type well 17, electrically contacted with the main emitter electrode 14 captures the minority carriers diffusing from the main cell portion 6 toward the sensing cell portion 7. Thus, the above described structure facilitates reducing greatly the leakage current between the main and sensing cell portions 6 and 7 caused by minority carriers. In association with this leakage current reduction, the spacing between the main and sensing cell portions 6 and 7 may be shortened to reduce the overall chip area. The efficiency with which the minority carriers are captured is improved by surrounding the sensing cell portion 7 with the ring shaped (p) type wells 17 and 18. Figure 3 is a sectional view showing the second embodiment of an IGBT according to the present invention. In Figure 3, the boundary region between the main cell portion 6 and the sensing cell portion 7 for current detection is shown. The main cell portion 6 is shown on the right hand side of the Figure and the sensing cell portion 7 on the left hand side. In Figure 3, a (p) type base region 9 is formed selectively in the surface of an (n) type base layer 8. An (n) type emitter region 10 is formed in the surface of the (p) type base region 9. A gate electrode 12, a main emitter electrode 14, a sensing emitter electrode 15, and a collector electrode 16 are disposed in the same manner as in the first embodiment of Figure 1. However, the (p) type well 17 for capturing the minority carriers (in this case, holes) is connected with the (p) type base region 9 of the main cell portion 6 and the (p) type well 18 is connected with the (p) type base region 9 of the sensing cell portion 7. The spacing between the main and sensing cell portions 6 and 7 is measured between the nearest neighbouring channel regions 13 and 13. The main and sensing cell portions 6 and 7 are spaced by a distance L of 100µm or more, thus preventing any mutual interference of the main and sensing cell portions 6 and 7 considering the diffusion length of the electrons supplied from the MOSFET and the minority carriers injected from the (p) type collector layer 19 to the base layer 8. Between the main and sensing cell portions, the spacing L W between the (p) type well 17, connected to the main emitter electrode 14 of the main cell portion, for capturing the minority carriers (in this case, holes) and the (p) type well 18, connected to the sensing emitter electrode 15 of the sensing cell portion, is set at 20µm or less. Figure 4 is a top plan view of the second embodiment of the present invention in which the gate oxide film 11, the emitter electrodes 14, 15 and their upper structure of Figure 3 are omitted. In Figure 4, the sensing cell portion 7 occupies the lower left part of the Figure, and the main cell portion 6 the other part. In the structure described above in Figure 3, the (p) type well 18, in electrical contact with the sensing emitter electrode 15 of the sensing cell portion, captures the minority carriers diffusing from the sensing cell portion 7 toward the main cell portion 6, and (p) type well 17, in electrical contact with the main emitter electrode 14 of the main cell portion, captures the minority carriers diffusing from the main cell portion 6 toward the sensing cell portion 7. Thus, the structure described in Figure 3 facilitates reducing greatly the leakage current between the main and sensing cell portions 6 and 7 caused by the minority carriers. In correspondence with this leakage current reduction, the spacing between the main and sensing cell portions 6 and 7 may be shortened to reduce the chip area. Further, as in the previous embodiment, the efficiency with which the minority carriers are captured is improved by completely surrounding the sensing cell portion 7 with the ring shaped (p) type wells 17 and 18. In the embodiments of Figures 1 and 3, the spacing between the (p) type well 17, connected to the main emitter electrode 14 of the main cell portion, and the (p) type well 18, connected with the sensing emitter electrode 15 of the sensing cell portion, is short enough for the depletion layer to spread from the sensing cell portion 7 to the main cell portion 6 to avoid the breakdown of the gate insulation film 10 even when a voltage is applied to the collector electrode 16 under the open state of the emitter electrode 15 of the sensing cell portion. Figure 5(a) is a top plan view of a part of the third embodiment of an IGBT according to present invention. Figure 5(b) is sectional view taken along the line A-A' of Figure 5(a) showing an upper part of the third embodiment. Figure 5(c) is a sectional view taken along the line B-B' of Figure 5(a) showing an upper part of the third embodiment. In Figure 5(a), the sensing cell portion 7 occupies the lower left part of the Figure, and the main cell portion 6 is located on the upper and right hand sides of the Figure. In Figure 5(a), a gate electrode 12 is shown by the broken line hatching, an emitter electrode 15 of the sensing cell portion by the narrowly spaced solid line hatching, and an emitter electrode 14 of the main cell portion by the widely spaced solid line hatching. In the separating region by which sensing cell portion 7 and the main cell portion 6 are spaced, the gate electrode 12 is not formed under the extension of the emitter electrode 15 as shown in Figure 5(b). This allows the overlapping area of the electrodes 12 and 15 to be reduced as much as possible. Since the sensing cell portion 7 is formed with an island shape so as to be surrounded by the wells 17, 18 for capturing the minority carriers, the gate electrode should be connected to some point in the sensing cell portion 7. The gate electrode 12 is thus extended, as shown in Figure 5(c), over the separating region while the extension of the emitter electrode 15 of the sensing cell portion 7 is shortened at that part of the separating region, as seen in the B-B' section, so as to reduce the overlapping area of the electrodes 12 and 15. Thus, the capacitance C GM between the gate electrode 12 and the emitter electrode 15 is reduced. Therefore, the spike noise voltage which the displacement current causes across the current detecting resistor at the turning-on of the IGBT is reduced. Though the present invention has been explained by way of examples of the IGBT, it is emphasised that the present invention is applicable to all vertical MOS semiconductor devices such as MOSFETs, MOS control thyristors (MCT), etc. As explained above, the present invention facilitates maintaining the ratio of the main and detecting currents at a constant value under any circumstance. The present invention also facilitates avoiding the breakdown of the device in the open state of the emitter electrode of the sensing cell portion or at the instant of turning-on the device.

Claims: A vertical MOS semiconductor device comprising a main cell portion (6) having a number of switching cells, a sensing cell portion (7) for detecting a current of the main cell portion (7), each of the cell portions further comprising a semiconductor layer (5) of a first conductivity type, a base region (9) of a second conductivity type formed selectively on a first surface of the semiconductor layer (5), an emitter region (10) of a first conductivity type formed selectively in the surface of the base region (9), a gate electrode (12) fixed via a gate oxide film (11) to that portion of the base region (9) extending between the semiconductor layer (5) and the emitter region (10), and an emitter electrode (14,15) contacting in common with the surfaces of the base region (9) and the emitter region (10), and a first well region (17) of the second conductivity type formed between the main cell (6) and sensing cell portions (7), the first well region (17) being connected with the emitter electrode (14) of the sensing cell portion (7) characterised in that the insulation withstand voltage between the emitter electrodes of the main cell (6) and sensing cell portion (7) is lower than the withstand voltage of the gate oxide film (11). A vertical MOS semiconductor device as claimed in claim 1, characterised in that the first well region (12) is shaped as a ring. A vertical MOS semiconductor device as claimed in claim 1 or claim 2, characterised in that a second well region (18) of the second conductivity type formed between the main cell (6) and sensing cell portions (7), the second well region (18) of the second conductivity type being connected with the emitter electrode (14) of the main cell portion (6). A vertical MOS semiconductor device as claimed in claim 3, characterised in that the second well region (18) is shaped as a ring. A vertical MOS semiconductor device as claimed in claim 3, characterised in that the first well region (17) and the second well region (18) are connected with the base region (9) of the respective cell portion. A vertical MOS semiconductor device as claimed in claim 3, characterised in that the spacing between the neighbouring first (17) and second (18) wells is from 5 to 20µm.

Inventors: FUJIHIRA TATSUHIKO, MOMOTA SEIJI, OBINATA SHIGEYUKI, OTSUKI MASAHITO, YAMAZAKI TOMOYUKI, FUJIHIRA, TATSUHIKO, MOMOTA, SEIJI, OBINATA, SHIGEYUKI, OTSUKI, MASAHITO, YAMAZAKI, TOMOYUKI
Applicants: FUJI ELECTRIC CO LTD, FUJI ELECTRIC CO. LTD.
Application year: 1995
Main classification: H01L29
IPC codes: H01L27, H01L29, H01L21