CMOS integrated circuit for fast propagation of a signal edge

Abstract: A fast propagation technique for use in CMOS circuits, whereby faster signal transition at an information carrying edge of a propagating signal is achieved at a cost of slower signal transition at the opposite edge. The technique of the present invention skews a size ratio of P-channel pull-up to N-channel pull-down transistors in the CMOS circuit to obtain much faster transition at one (rising or falling) edge

Description: BACKGROUND OF THE INVENTION This invention relates to a fast propagation circuit for use in a CMOS circuit. A typical CMOS inverter includes a P-channel (PMOS) pull-up transistor and an N-channel (NMOS) pull-down transistor. Because PMOS is inherently weaker than NMOS, the size (i.e., channel width) of the PMOS pull-up transistor is usually made approximately 1.5 times larger than the NMOS pull-down transistor in order to minimize signal propagation time through a cascaded pair of inverter stages. A conventional CMOS inverter chain having PMOS channels that are about 1.25 to 2.5 times as wide as the corresponding NMOS channels is known from US 4 496 857. Signal propagation delay time for a CMOS gate increases linearly with the fanout F of that gate. The fanout F for a given stage is defined by the ratio of the size of the load device (i.e., stage being driven) divided by the size of the driver stage. The larger the size of the transistors in a CMOS inverter, the faster the output can switch any given capacitive load. To drive a very large load with minimum delay, normal CMOS logic conventionally uses a chain of serially connected inverters that progressively grow in size, each stage having a fanout F of about three. Designing with a fanout of either lower or higher than three increases the delay to achieve a given required total fanout. At lower fanout per stage, too many stages are required, while at higher fanout per stage the delay per stage becomes excessive. Propagation delay time continues to be a critical design factor. In some synchronous circuit applications it is possible to appreciably increase the signal propagation speed by using a technique known as post charge logic. As fully described in U.S. 4 985 643 and EP-A-0 347 759, post charge logic achieves much higher speed than that obtainable with normal CMOS logic circuits, and somewhat higher speed than that obtainable by the technique of the present invention. However, post charge logic has several limitations. It requires numerous feedback reset paths causing circuit layout problems. It also requires a reset time interval after each active pulse, before another pulse can be propagated. This limits the duty cycle on any pulse to 50% or less, which can be a severe limitation for many circuits including memory circuits. With a duty cycle limited to 50%, only one half of a cycle is available to develop a signal from a memory cell during a read cycle, or to force new data into a memory cell during a write cycle. Thus, there remains a need to reduce propagation delay times in CMOS logic circuits without the limitations of post charge logic. Known from US 5 061 864 is a CMOS amplifier circuit comprising a first and a second sequence of serially coupled inverters for the first and the second edge of an input signal, respectively. The sequences are coupled in parallel and form a split path for the input signal, each path responding to one logic level. Each inverter comprises a P-channel pull-up transistor and an N-channel pull-down transistor. The channel size of corresponding P- and N-channel transistors in the first and second sequence are ratioed to obtain fast propagation of the first and the second signal edge, respectively. SUMMARY OF THE INVENTION The invention is defined in claim 1. The present invention offers a fast propagation technique for those CMOS circuits where input information can change only at known specific times (i.e., with a known minimum time between changes). The technique can be employed in, for example, synchronous circuits where a repetitive timing event such as a clock input dictates when new information is available. Broadly, the circuit of the present invention has a normal or standby voltage at each node which is interrupted by an information carrying pulse. The information carrying pulse is generated near the circuit input as a narrow (short duration) pulse. To propagate this pulse through the various levels of logic in the circuit with as little propagation delay as possible, the various logic stages use transistor sizes with skewed ratios. The skewing of transistor sizes in a CMOS gate achieves faster switching in one direction (information carrying leading edge) at the cost of slower switching in the other direction (reset to normal or standby voltage). Faster leading edge transitions results in faster propagation of information through the signal path. As the pulse propagates through the signal path, the slower second edge causes the pulse width to grow. With each stage of skewed logic, the pulse width increases. There is, however, an upper limit to the width of the propagating pulse equal to the minimum cycle time of the circuit. That is, the pulse must be cleared early enough to avoid any interference with a subsequent information carrying edge. The number of skewed logic stages through which the pulse propagates must therefore be limited. Accordingly, a narrow pulse may be allowed to propagate and grow in width through several early stages of the circuit, and then restart as a second narrow pulse that continues to propagate through the later stages of the circuit as it grows in width. In a preferred embodiment, the fast propagation circuit comprises a plurality of serially coupled logic stages with a first logic stage in which the channel size of the N-channel pull-down transistor is larger than the channel size of the P-channel pull-up transistor and with a second logic stage in which the channel size of the P-channel pull-up transistor is larger than the channel size of the N-channel pull-down transistor. A better understanding of the nature and advantages of the fast propagation technique of the present invention may be had by referring to the detailed descriptions and diagrams below. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A and 1B show a prior art inverter chain and an inverter chain having skewed logic according to the present invention, respectively; Figure 2 is a timing diagram for the inverter chains of Figure 1, illustrating the speed of skewed logic; Figure 3 shows one simple embodiment of a CMOS circuit using skewed logic according to the present invention; and Figure 4 shows complementary data paths fore skewed logic technique, not forming part of the present invention. DESCRIPTION OF SPECIFIC EMBODIMENTS Figures 1A and 1B show two CMOS inverter chains 100 and 102, respectively, each driving an effective capacitive load 104 of equal value. Inverter chain 100 is a typical prior art buffering circuit with a chain of six serially connected CMOS inverters 106, 108, 110, 112, 114, and 116 having transistor sizes adjusted for minimum propagation delay for both the rising and the falling edge of the input signal 200. The width of each transistor is shown in Figures 1A and 1B in parentheses with PMOS transistor 106P being 3µ wide and NMOS transistor 106N being 2µ wide. In this example, the size of each inverter grows by a factor of three, starting from a PMOS/NMOS channel width ratio of 3/2 for inverter 106 to 729/486 for the last inverter 116. Defining the fanout for each individual transistor as the ratio of the sum of the transistor sizes (channel widths) of the load (i.e., total width of transistor gates being driven) divided by the size of the driver transistor yields a fanout Fp of 5 (5 = [9+6]/3 = [27+18]/9 = [81+54]/27 = etc.) for the PMOS transistors 106P, 108P, 110P, etc., and a fanout Fn of 7.5 (7.5 = [9+6]/2 = [27+18]/6 = [81+54]/18 = etc.) for the NMOS transistors 106N, 108N, 110N, etc. With equal fanout conditions, each pair of stages (one with a rising edge and one with a falling edge) exhibits the same amount of propagation delay as every other pair. Referring to Figure 1B, inverter chain 102 includes four serially connected CMOS inverters 118, 120, 122, and 124, all designed with skewed transistor sizes. In this example, it is assumed that information is carried by the rising edge of the input signal. Therefore transistor sizes have been skewed to speed up the propagation through the inverter chain resulting from the rising edge of the input signal. The first inverter 118 has an NMOS transistor with a size, for example, four times that of the PMOS transistor, resulting in a much faster falling transition on node 118OUT than rising transition. To achieve high speed for the fast (information carrying) path of inverter chain 102, the fanout Fn of NMOS transistor 118N is chosen to be 7.5, the same value as used for transistor 106N in Figure 1A. The sum of channel widths for the load transistors 120P and 120N is thus designed to be 7.5 times larger than the 4µ channel width of the driver transistor 118N, for a total channel width for transistors 120P and 120N of 30µ. To speed up the rise time of the signal at the output of inverter 120, PMOS transistor 120P is made much larger than NMOS transistor 120N. In the example shown, PMOS/NMOS transistor sizes for inverter 120 is set at 25/5. This speeds up the rise time of the signal at the output of inverter 120 at the cost of slower fall time, while maintaining a total of 30 microns for the transistor channel sizes. The same analysis applies in choosing the transistor channel widths for the two final inverters 122 and 124. In the example shown in Figure 1B, PMOS/NMOS channel width sizes of inverters 122 and 124 are 15/110 and 750/75, respectively. The Fp for inverter 120 is 125/25 = 5, and the Fn for inverter 122 is 825/110 = 7.5. To compare the performance of each inverter chain, assume that each consecutive pair of inverters in inverter chain 100 exhibits a propagation delay of, for example, 1 nsec. Given the same fanout for the fast path (i.e., rising edge of input) for the two inverter chains 100 and 102, the delay per pair of stages in inverter chain 102 is actually smaller than that of inverter chain 100. As the input signal 200 makes a transition from low to high, the gate to source voltage of PMOS transistors 106P and 118P of inverters 106 and 118, respectively, decreases while the gate to source voltage of NMOS transistors 106N and 118N increases. The NMOS transistors thus start to turn on and the PMOS transistors start to turn off, pulling the inverter outputs down toward ground. Initially, however, in pulling the outputs down toward ground, the NMOS transistors must fight the PMOS transistors that are not yet completely OFF. During this period, relatively strong NMOS 118N fights a much weaker PMOS 118P, as compared to NMOS 106N that fights a comparably strong PMOS 106P. Given the same capacitive fanout Fn=7.5 for the NMOS transistors, the signal 118OUT at the output of inverter 118 will therefore drop to ground faster than the signal 106OUT at the output of inverter 106. That is, for a rising input, skewed inverter 118 exhibits less delay than normal inverter 106. Similarly, when the outputs of the first inverters 106 and 118 in either chain switch low, they turn on PMOS transistors 108P and 120P and turn off NMOS transistors 108N and 120N in the following stages, respectively. Again, small NMOS transistor 120N offers little opposition to large PMOS transistor 120P, while NMOS transistor 108N initially offers substantial opposition to PMOS transistor 108P. Given the same capacitive fanout of Fp=5 for the PMOS transistors, signal 120OUT at the output of inverter 120 will therefore rise to VDD faster than signal 108OUT at the output of inverter 108. Accordingly, the average delay per pair of stages for skewed inverter chain 102 for a rising input is less than that of inverter chain 100, possibly 0.9 nsec. The total delay for inverter chain 100 is therefore equal to 3ns (six stages of 0.5 nsec. delay each), while the total delay for a rising input for skewed inverter chain 102 is 1.8ns (four stages of 0.45 nsec. delay each). Note that PMOS transistor 124P in final inverter 124 in inverter chain 102 is even stronger than PMOS transistor 116P in final inverter 116 in inverter chain 100. Therefore, inverter chain 102 with two less stages is capable of driving even a larger load, much faster than possible with inverter chain 100. The delay for a rising input for the skewed logic is only about 60% that of normal logic for the same total fanout. The significant increase in the speed through circuit 120 at the rising edge of the input signal, however, is realized at the expense of substantially increased delay at the falling edge of the input signal. The prior art signal path 100 exhibits equal delay for either rising or falling inputs. But signal path 102 according to the present invention is very slow in propagating a falling edge on its input. When the input switches low, PMOS transistor 118P is very slow to switch node 118OUT high for two reasons. First, PMOS transistor 118P has a very high fanout of [25+5)/1 = 30. Such large fanout by itself makes PMOS transistor 118P very slow. Secondly, NMOS transistor 118N continues to successfully fight PMOS transistor 118P until input 200 reaches a low enough voltage to turn off NMOS transistor 118N. Thus, node 118OUT switches high after a negative transition on the input at a considerably slower rate than does node 106OUT in circuit 100. Similarly, NMOS transistor 120N of stage 120 is very slow to pull node 120OUT low. Thus, as shown in Figure 2, the skewed logic of circuit 102 is faster than the prior art circuit 100 on the leading (rising) edge of the input, but much slower than the prior art circuit 100 on the trailing (falling) edge of the input signal. The increased delay at the trailing edge, however, has absolutely no adverse consequences on the operation of the circuit of the present invention. That is so because the pulse is terminated before the next information carrying leading edge of a pulse occurs. Due to the slower second edge, however, the width of the pulse grows by a considerable amount as the pulse propagates through each stage of the skewed inverter chain. As shown in Figure 2, the positive pulse on node 124OUT is wider than the negative pulse on node 122OUT which in tum is wider than the positive pulse on node 120OUT, etc. The width of the pulse can be permitted to grow significantly without incurring any penalties, but the circuit must be designed to ensure that, even in the last stage of logic, the pulse terminates before the next information carrying edge occurs. To ensure such timely termination, the skewed logic technique of the present invention is applicable in those circuits where the information carrying edge of the signal does not occur at random times, but is limited to occurring only with known minimum time intervals between initiation of new information carrying pulse edges. This ensures that one data carrying pulse terminates before arrival of a new data carrying pulse. For proper operation of the circuit, the designer must limit the pulse width of the signal propagating though the signal path. This can be achieved by generating a very narrow pulse at the information carrying edge of the signal using, for example, a simple one-shot circuit. Instead of the original input signal, the narrow pulse is entered into the skewed logic. As the narrow pulse propagates through the skewed logic path, its pulse width grows. When the pulse width of the signal reaches critical size (less than the minimum cycle time), the signal may once again be put through a one-shot circuit to generate a second narrow pulse which continues to propagate through additional stages of skewed logic. This regeneration of a narrow pulse can be performed as often as deemed desirable. Figure 3 provides a simple example of skewed logic according to the present invention. An input signal 300 is applied to the input of a one-shot circuit 302. The output 304 of one-shot circuit 302 is a narrow negative pulse at the rising edge of the input signal. This signal propagates through several stages of skewed logic 306. In this example, the PMOS/NMOS size ratios are skewed to minimize delay through the circuit on the falling edge of the signal on node 304. The narrow pulse grows in width as it propagates through each stage of skewed logic 306. When the pulse width approaches the minimum cycle time of the input signal (i.e., time between initiation of new information carrying pulses), a second one-shot circuit 308 receives the signal at its input to generate a second narrow pulse at its output 310. This process continues until the signal reaches the output. It is to be understood that many of the skewed inverters 306 may be NAND, NOR or other logic gates in a typical application. The skewed logic technique of the present invention requires that data be represented by pulses on complementary or mutually exclusive data lines as opposed to voltage levels. That is, data is not transmitted through a single wire using voltage levels to distinguish between a logic "0" and a logic "1." Instead, at least two mutually exclusive wires are required such that a pulse on the true wire represents a logic "1" while a mutually exclusive pulse on the inverse wire represents a logic "0." For example, in the case of a predecoder or final decoder output in a random access memory circuit, a pulse exists on a selected one of N outputs to the exclusion of a pulse on any other output. Each pulse is allowed to propagate through a separate skewed logic path. Separate data paths are illustrated by the exemplary circuit shown in Figure 4. An input signal and its inverse are applied respectively to the inputs of two pulse generators 800 and 802. The outputs of pulse generators 800 and 802 each go through several stages of skewed logic, 804 and 806 respectively, similar to the five inverters in block 306 of Figure 3. The output of the true path 804 drives the gate of a PMOS pull-up transistor 808 through an inverter, while the output of the inverse path 806 drives the gate of an NMOS pull-down transistor 810 directly. The drains of PMOS transistor 808 and NMOS transistor 810 connect together to form a single output wire. A rising edge at the input results in a negative pulse at the output of one-shot 800 whose leading edge rapidly propagates through skewed logic 804 and arrives as a much wider negative pulse at the gate of PMOS transistor 808, while the gate of NMOS transistor 810 remains at logic low. This causes PMOS transistor 808 to pull output node OUT up to VDD with little total delay. A falling edge at the input results in a negative pulse at the output of one-shot 802 whose leading edge rapidly propagates through skewed logic 806 and arrives as a much wider positive pulse at the gate of NMOS transistor 810, while the gate of PMOS transistor 808 remains at logic high. This causes the output node OUT to be pulled low to ground. In some applications a small latch may be required on the output wire to indefinitely hold the data represented by the most recently received pulse. Thus, a speed advantage of the skewed logic technique can be realized in both directions of an input signal, on a single output wire but with two separate signal paths. This example also illustrates the requirement of a minimum time interval between the occurrence of two information carrying edges. That is, a negative transition at IN cannot be permitted to follow too closely after a positive transition, or vice versa. A very narrow pulse generated at the output of one-shot 800 grows to a substantially wider pulse at the gate of PMOS transistor 808. If a subsequent negative transition at IN occurred early enough such that NMOS transistor 810 turns on before PMOS transistor 808 turns off, the output is very slow to fall, if it falls at all, and the circuit consumes excessive power. Thus, it is critical to the skewed logic technique of the present invention that the information carrying edge of the signal does not occur at random times. There must be sufficient time allowed between information carrying pulses to allow the previous information carrying edge to have already terminated before arrival of a new, possibly opposite, information carrying edge. A good example of an application circuit for the skewed logic technique of the present invention is a dynamic or static synchronous random access memory circuit. The design of synchronous memory circuits is based on a master clock signal. A dynamic random access memory (DRAM) cycle, such as Write or Read is initiated at the rising edge (arbitrary choice) of the clock input signal. The column addresses supplied to synchronous DRAMs are sampled on (or latched by) the rising edge of the periodic clock, and cannot change internally between clocks. A synchronous DRAM does not support a Read/Modify/Write cycle which would require maintaining column decode signal selected for a possible Write cycle after a Read operation. A single known operation (e.g., read or write) allows the use of a pulse rather than a level on the final column decode output. This combined with the periodic change in internal address allows the use of skewed logic. Thus, the speed benefits of skewed logic are realized while simultaneously achieving a wider pulse than is possible with post charge logic for read or write on the column select output. In conclusion, the present invention provides a fast propagation technique for CMOS circuits. By skewing the transistor sizes of the CMOS circuit, the technique of the present invention speeds up the information carrying edge of the propagating signal at the cost of slower opposite edge. This speeds up the access time of the circuit compared to that possible using normal (unskewed) logic stages. The technique can be employed in those CMOS circuits where information can not change at random times, but instead changes only at known specific times. A good example of an application for the technique of the present invention is a CMOS synchronous DRAM or SRAM circuit where access time is one of the most critical design considerations.

Claims: A fast propagation circuit for use in a complementary metal oxide semiconductor (CMOS) circuit wherein information carrying edges of data occur according to a clock signal, said fast propagation circuit comprising: a first pulse generator (302) for generating at an output (304) a narrow first pulse on a first information carrying edge, and no pulse on the opposite edge, of the data; a logic circuit (306) having a plurality of serially coupled logic stages with an input receiving the narrow first pulse, each logic stage having a P-channel pull-up transistor and an N-channel pull-down transistor, the P-channel and N-channel transistors having channel sizes ratioed to obtain fast signal transition for a first edge of the narrow first pulse and slow signal transition for a second opposite edge of the narrow first pulse, wherein the slow signal transition causes the pulse width of the narrow first pulse to grow progressively to a wider pulse at the output of the logic circuit; and a second pulse generator (308) coupled to receive the wider pulse, the second pulse generator (308) generating from the wider pulse a narrow second pulse on the first information carrying edge of the data, before a subsequent second information carrying edge of the data occurs. The fast propagation circuit of claim 1 wherein: in a first logic stage of said plurality of serially coupled logic stages, the channel size of the N-channel pull-down transistor is larger than the channel size of the P-channel pull-up transistor; and in a second logic stage of said plurality of serially coupled logic stages, the channel size of the P-channel pull-up transistor is larger than the channel size of the N-channel pull-down transistor. The fast propagation circuit of claim 2 wherein: the first logic stage is coupled to the input of the logic circuit (306); and the second logic stage is coupled to the output of the first logic stage. The fast propagation circuit of claim 2 wherein: the second logic stage is coupled to the input of the logic circuit (306); and the first logic stage is coupled to the output of the second logic stage. The fast propagation circuit of any one of claims 1 to 4 wherein each logic stage comprises a CMOS inverter. The fast propagation circuit of any one of claims 1 to 4 wherein each logic stage comprises a CMOS NAND gate. The fast propagation circuit of any one of claims 1 to 4 wherein each logic stage comprises a CMOS NOR gate.

Inventors: PROEBSTING ROBERT J, PROEBSTING, ROBERT J.
Applicants: HYUNDAI ELECTRONICS AMERICA, HYUNDAI ELECTRONICS AMERICA, INC.
Application year: 1995
Main classification: H03K19
IPC codes: H03K17, H03K19, G11C7, G11C11