BiCMOS push-pull type logic apparatus with voltage clamp circuit and clamp releasing circuit

Abstract: In a push-pull type logic apparatus including a push-pull buffer (1) formed by two bipolar transistors (11, 12), a control circuit (2) for turning ON one of the bipolar transistors and turning OFF the other, and a voltage clamp circuit (3) for clamping the voltage of the base of at least one of the bipolar transistors, a clamp releasing circuit (42, 43) is provided for releasing the clamp operation of the voltage clamp ciucuit when the corresponding bipolar transistor is turned ON. Also, a MOS transistor (44) is connected between the collector and emitter of the corresponding bipolar transistor and is turned ON when the corresponding bipolar transistor is turned ON.

Description: BACKGROUND OF THE INVENTION Filed of the Invention The present invention relates to a bipolar complementary metal oxide semiconductor (BiCMOS) push-pull type logic apparatus incorporating a voltage clamp circuit. Description of the Related Art A prior art BiCMOS push-pull type logic apparatus such as an inverter includes a push-pull buffer formed by two NPN type transistors, and a CMOS control circuit for controlling the bases of the NPN type transistors in response to an input voltage. That is, one of the NPN type transistors is turned ON, while the other is turned OFF, and accordingly, an output voltage of the push-pull buffer is changed in accordance with the input voltage. This will be explained later in detail. In the above-described prior art BiCMOS push-pull type logic apparatus, however, before each of the NPN type transistors is turned ON, the voltage at the base thereof remains at a ground level. Therefore, in order to turn ON each of the NPN type transistors, first, a parasitic capacitance thereof has to be charged, which reduces the operation speed. In this case, the driving power of the CMOS control circuit is made large so as to increase the operation speed. In order to compensate for the reduction of the operation speed, the inventor has already proposed that a voltage clamp circuit is provided at the base of each of the NPN transistors, to clamp the voltage at the base of each of the NPN transistors before turning ON the NPN transistors (see Japanese Patent Application No. 5-237620 filed on September 24, 1993 and published as Kokai No. HEI7-95045 on April 7, 1995). This will be explained later in detail. In the above-proposed BiCMOS push-pull type logic apparatus, however, the output voltage swing is so small that it is impossible to operate the logic opparatus under a low power supply voltage system. SUMMARY OF THE INVENTION It is an object of the present invention to provide a push-pull type logic apparatus incorporating a voltage clamp circuit and having a large output voltage swing. According to the present invention, in a push-pull type logic apparatus including a push-pull buffer formed by two bipolar transistors, a control circuit for turning ON one of the bipolar transistors and turning OFF the other, and a voltage clamp circuit for clamping the voltage of the base of at least one of the bipolar transistors, a clamp releasing circuit is provided for releasing the clamp operation of the voltage clamp circuit when the corresponding bipolar transistor is turned ON. Also, a MOS transistor is connected between the collector and emitter of the corresponding bipolar transistor and is turned ON when the corresponding bipolar transistor is turned ON. Thus, the output voltage swing can be increased. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description as set forth below, in comparison with the prior art, with reference to the accompanying drawings, wherein: Fig. 1 is a circuit diagram illustrating a prior art BiCMOS push-pull type logic apparatus; Figs. 2A, 2B, 2C and 2D are timing diagrams for explaining the operation of the apparatus of Fig. 1; Fig. 3 is a circuit diagram illustrating a prior art BiCMOS push-pull type logic apparatus; Figs. 4A, 4B, 4C and 4D are timing diagrams for explaining the operation of the apparatus of Fig. 3; Fig. 5 is a circuit diagram illustrating a first embodiment of the BiCMOS push-pull type logic apparatus according to the present invention; Figs. 6A, 6B, 6C, 6D and 6E are timing diagrams for explaining the operation of the apparatus of Fig. 5; Figs. 7A, 7B and 7C are circuit diagrams illustrating modifications of the apparatus of Fig. 5; Fig. 8 is a circuit diagram illustrating another modification of the apparatus of Fig. 5; Fig. 9 a circuit diagram illustrating a second embodiment of the BiCMOS push-pull type logic apparatus according to the present invention; Fig. 10 is a circuit diagram illustrating a NAND logic apparatus to which the first embodiment of the present invention is applied; Fig. 11 is a circuit diagram illustrating a NOR logic apparatus to which the first embodiment of the present invention is applied; and Fig. 12 is a circuit diagram illustrating a flip-flop logic apparatus to which the first embodiment of the present invention is applied. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before the description of the preferred embodiments, a prior art BiCMOS push-pull type logic apparatus and a proposed BiCMOS push-pull type logic apparatus will be explained with reference to Figs. 1 and 2, and Figs. 3A, 3B and 3C. In Fig. 1, which illustrates a prior art BiCMOS push-pull type logic apparatus, a push-pull buffer 1 formed by NPN type transistors 11 and 12 is connected between a high power supply voltage terminal V CC and a low power supply terminal GND. In more detail, a collector of the NPN type transistor 11 is connected to the high power supply terminal V CC , and an emitter of the NPN type transistor 11 is connected to an output terminal OUT. Also, a collector of the NPN type transistor 2 is connected to the output terminal OUT, and an emitter of the NPN type transistor 12 is connected to the low power supply terminal GND. A control circuit 2 receives an input voltage at an input terminal IN to control bases of the NPN type transistors 11 and 12. The control circuit 2 includes a P-channel MOS transistor 21, an N-channel MOS transistor 22, an N-channel MOS transistor 23, and a resistor 24. That is, the P-channel MOS transistor 21 supplies a current to the base of the NPN type transistor 11, to turn ON the NPN type transistor 11, while the N-channel transistor 22 absorbs a current from the base of the NPN type transistor 11, to turn OFF the NPN type transistor 11. Similarly, the N-channel MOS transistor 23 supplies a current to the base of the NPN type transistor 12, to turn ON the NPN type transistor 12, while the resistor 24 absorbs a current from the base of the NPN type transistor 12, to turn OFF the NPN type transistor 12. The operation of the apparatus of Fig. 1 is explained next with reference to Figs. 2A, 2B, 2C and 2D. At time t 1 , when the voltage at the input terminal IN is changed from low (= 0V) to high (= V CC ), as shown in Fig. 2A, the MOS transistors 21 and 22 are turned OFF and ON, respectively, so that the voltage at the output terminal OUT is decreased with the reduction of the voltage at a node N 1 , i.e., the base of the NPN type transistor 11, as shown in Figs. 2B and 2D. In this case, the difference in potential between the base of the NPN type transistor 11 and the output terminal OUT is a forward voltage V F of the PN junction of the NPN type transistor 11. Simultaneously, the MOS transistor 23 is turned ON to charge the base parasitic capacitance of the NPN type transistor 12, so that the voltage at a node N 2 , i.e., the base of the NPN type transistor 12 rises at V F , as shown in Fig. 2C. As a result, as shown in Fig. 2D, the voltage at the output terminal OUT is remarkably reduced at OV. At time t 2 , when the voltage at the input terminal IN is changed from high to low, as shown in Fig. 2A, the MOS transistors 21 and 22 are turned ON and OFF, respectively, to charge the base parasitic capacitance of the NPN type transistor 11. As a result, when the voltage at the node N 1 reaches VF as shown in Fig. 2B, the NPN transistor 11 is turned ON, so that the voltage at the output terminal OUT is increased with the increase of the voltage at the base of the NPN type transistor 11, as shown in Fig. 2D. Also, in this case, the difference in potential between the base of the NPN type transistor 11 and the output terminal OUT is the forward voltage VF of the PN junction of the NPN type transistor 11. Simultaneously, the MOS transistor 23 is turned OFF to cut off the base current of the NPN transistor 12. As a result, the charges at the node N 2 are discharged through the resistor 24 as shown in Fig. 2C, so that the voltage at the node N 2 , i.e., the base of the NPN type transistor 12 falls to 0V, as shown in Fig. 2C. As a result, the voltage at the output terminal OUT is remarkably increased at V CC - V F , as shown in Fig. 2D. Thus, in the logic apparatus of Fig. 1, since a charging operation is performed upon the base of the NPN transistor 12 or 11 each time after the voltage at the input terminal IN is changed from low to high or vice versa. This reduces the operation speed. In Fig. 3, which illustrates a proposed BiCMOS push-pull type logic apparatus (see Japanese Patent Application No. 5-237620 and European Patent Application 0 645 890), a voltage clamp circuit 3 is added to the elements of the apparatus of Fig. 1, to clamp the voltage at the node N 2 at V F . The voltage clamp circuit 3 includes resistors 31, 32 and 33, and an NPN type transistor 34. Note that the resistor 24 of Fig. 1 is not provided. In the voltage clamp circuit 3, in a steady mode, a current flowing through the NPN type transistor 34 is determined by the resistor 31. For example, the value of the resistor 31 is set so as to satisfy that this current is less than 100 µA. In this case, since a base current of the NPN type transistor 34 is a few µA, the voltage reduction of the resistor 32, whose value is a few kΩ, is negligible. Therefore, the base voltage of the NPN type transistor 12 is substantially clamped at that of the NPN transistor 34. Also, when the voltage at the input terminal IN is high, the MOS transistor 22 is turned ON, so that the base voltage of the NPN type transistor 11 is substantially clamped at that of the NPN type transistor 34. Also, the voltage clamp circuit 3 has a higher impedance than an impedance of the base and emitter of the NPN type transistor 12. That is, when the voltage at the input terminal IN is high, so that the MOS transistors 22 and 23 are turned ON, the ON currents therefrom are shunt into both the NPN type transistors 12 and 34. In this case, the resistors 32 and 33 restrict the currents from being supplied to the NPN type transistor 34. The operation of the apparatus of Fig. 3 is explained next with reference to Figs. 4A, 4B, 4C and 4D. At time t 1 , when the voltage at the input terminal IN is changed from low to high, as shown in Fig. 4A, the MOS transistors 21 and 22 are turned OFF and ON, respectively, so that the voltage at the output terminal OUT is decreased with the reduction of the voltage at the node N 1 , i.e., of the NPN type transistor 11, as shown in Figs. 4B and 4D. In this case, the difference in potential between the base of the NPN type transistor 11 and the output terminal OUT is the forward voltage V F of the PN junction of the NPN type transistor 11. Simultaneously, the MOS transistor 23 is turned ON. In this case, however, the base parasitic capacitance of the NPN type transistor 12, is already charged. In other word, the voltage at the node N 2 , i.e., the base of the NPN type transistor 12 is fixed at V F , as show in Fig. 4C. As a result, as shown in Fig. 4D, since it is unnecessary to charge the base of the NPN type transistor 12, the voltage at the output terminl OUT is remarkably reduced at V F . At time t 2 , when the voltage at the input terminal IN is changed from high to low, as shown in Fig. 4A, the MOS transistors 21 and 22 are turned ON and OFF, respectively, to charge the base parasitic capacitance of the NPN type transistor 11. As a result, when the voltage at the node N 1 reaches 2V F as shown in Fig. 4B, the NPN transistor 11 is turned ON, so that the voltage at the output terminal OUT is increased with the increase of the voltage at the base of the NPN type transistor 11, as shown in Fig. 4D. Also, in this case, the difference in potential between the base of the NPN type transistor 11 and the output terminal OUT is the forward voltage V F of the PN junction of the NPN type transistor 11. Simultaneously, the MOS transistor 23 is turned OFF to cut off the base current of the NPN transistor 12. In this case, however, the voltage at the node N 2 is clamped at V F as shown in Fig. 4C. As a result, the voltage at the output terminal OUT is increased to V CC - V F as shown in Fig. 4D. In the logic apparatus of Fig. 3, however, when the voltage at the input terminal IN is high, the voltage at the output terminal OUT cannot be 0V due to the presence of the voltage clamp circuit 3. Since the voltage clamp circuit 3 clamps the voltage at the node N 2 at V F , the voltage at the output terminal OUT should be about V F above the ground voltage GND, to avoid the saturation of the NPN transistor 12. As a result, the output voltage swing (= V CC -2V F ) is smaller than that (= V CC - VF) of the apparatus of Fig. 1. In order to obtain an output voltage swing of 0.5V, if V F = 0.8V, then a minimum value of the power supply voltage V CC is 2.1V, which is not suitable for a low power supply voltage system. In Fig. 5, which illustrates a first embodiment of the present invention, a CMOS inveter 41, P-channel MOS transistors 42 and 43, and N-channel MOS transistors 44 and 45 are added to the elements of Fig. 3. In this case, the MOS transistor 43 also serves as the resistor 31 of Fig. 3, and therefore, the resistor 31 of Fig.3 is not provided in Fig. 5. Also, the MOS transistor 23 is connected via the MOS transistor 42 to the power supply terminal V CC . The CMOS inverter 41 is formed by a P-channel MOS transistor and an N-channel MOS transistor (not shown). When the voltage at the output terminal OUT is low, the voltage at a node N 3 , i.e., the output of the CMOS inverter 41 is high (= V CC ), while when the voltage at the output terminal OUT is high, the voltage at the node N 3 is low (=0V). The MOS transistors 42 and 43 are used for releasing the voltage clamp circuit 3 when the voltage at the node N 3 is high. Also, the MOS transistor 44 is used for clamping the voltage at the node N 1 at the ground level GND when the voltage at the node N 3 is high. Further, the MOS transistor 45 is used for clamping the voltage at the output terminal OUT at the ground level GND when the voltage at the node N 3 is high. The operation of the apparatus of Fig. 5 is explained next with reference to Figs. 6A, 6B, 6C, 6D and 6E. Before time t 1 , the voltage at the output terminal OUT is high (= V CC - V F ) as shown in Fig. 6E, and therefore, the voltage at the node N 3 is low (= 0V), as shown in Fig. 6D. As a result, the MOS transistors 42 and 43 are turned ON, and the MOS transistors 44 and 45 are turned OFF. At time t 1 , when the voltage at the input terminal IN is changed from low to high, as shown in Fig. 6A, the MOS transistors 21 and 22 are turned OFF and ON, respectively, so that the voltage at the output terminal OUT is decreased with the reduction of the voltage at the node N 1 , i.e., the base of the NPN type transistor 11, as shown in Figs. 6B and 6E. In this case, the difference in potential between the base of the NPN type transistor 11 and the output terminal OUT is the forward voltage V F of the PN junction of the NPN type transistor 11. Simultaneously, the MOS transistor 23 is turned ON. In this case, however, the base parasitic capacitance of the NPN type transistor 12, is already charged, in other word, the voltage at the node N 2 , i.e., the base of the NPN type transistor 12 is fixed at V F , as shown in Fig. 6C. As a result, as shown in Fig. 6E, since it is uunecessary to charge the base of the NPN type transistor 12, the voltage at the output terminl OUT is remarkably reduced. On the other hand, when the voltage at the output terminal OUT is reduced as shown in Fig. 6E, the voltage at the output terminal OUT is increased as shown in Fig. 6D. As a result, the MOS transistors 42 and 43 are turned OFF, so that the operation of the clamp circuit 3 is inhibited. Simultaneously, the MOS transistor 44 is turned ON, so that the NPN type transistors 12 and 34 are completely turned OFF. Thus, the saturation of the NPN type transistor 12 is dissolved. Further, although the turning OFF of the NPN type transistor 12 seems to put the output terminal OUT in a floating state, since the MOS transistor 45 is turned ON, the voltage at the output terminal OUT is surely reduced to OV. At time t 2 , when the voltage at the input terminal IN is changed from high to low, as shown in Fig. 6A, the MOS transistors 21 and 22 are turned ON and OFF, respectively, to charge the base parasitic capacitance of the NPN type transistor 11. As a result, when the voltage at the node N 1 reaches V F as shown in Fig. 6B, the NPN transistor 11 is turned ON, so that the voltage at the output terminal OUT is increased with the increase of the voltage at the base of the NPN type transistor 11, as shown in Fig. 6E. Also, in this case, the difference in potential between the base of the NPN type transistor 11 and the output terminal OUT is the forward voltage V F of the PN junction of the NPN type transistor 11. In this case, the MOS transistors 42 and 43 are turned ON; however, the MOS transistor 23 is turned OFF to cut off the base current of the NPN transistor 12. Therefore, the voltage at the node N 2 is clamped at V F as shown in Fig. 4C. In this case, note that a current of about 50 µA flows through each of the NPN type transistors 12 and 34. As a result, the voltage at the output terminal OUT is increased to V CC - V F as shown in Fig. 6E. Thus, in the logic apparatus of Fig. 5, when the voltage at the input terminal IN is high, the voltage at the output terminal OUT can be 0V since the voltage clamp circuit 3 is released. As a result, the output voltage swing (=V CC - V F ) is the same as that of the apparatus of Fig. 1. In order to obtain an output voltage swing of 0.5V, if V F = 0.8V, then a minimum value of the power supply voltage V CC is 1.3V, which is sufficiently suitable for a low power supply voltage system. In Figs. 7A, 7B and 7C, the voltage clamp circuit 3 of Fig. 5 is modified. In Fig. 7A, the resistor 33 of Fig. 5 is omitted, and in Fig. 7B, the resistor 32 is omitted. Also, in Fig. 7C, a capacitor 35 is added. That is, at least one of the resistors 32 and 33 has only to be present, so as to increase an impedance in view of the node N 2 . In Fig. 8, which illustrates a modification of the apparatus of Fig. 5, the resistors 32 and 33 of Fig. 5 are replaced by ON state N-channel MOS transistors 32' and 33', respectively, thus increasing the integration of the apparatus of Fig. 8 as compared with that of Fig. 5. In Fig. 9, which illustrates a second embodiment of the present invention, another voltage clamp circuit 5 formed by resistors 51, 52 and 53, and an NPN type transistor 54 is added to the elements of Fig. 5. In Fig. 5, the voltage clamp circuit 3 can clamp the base voltage of the NPN type transistor 11 at the voltage V F in addition to the base voltage of the NPN type transistor 12. Conversely, in Fig. 9, the voltage clamp circuit 3 clamps the base voltage of the NPN type transistor 12 at the voltage V F , while the voltage clamp circuit 5 clamps the base voltage of the NPN type transistor 11 at GND + V F . That is, since the collector of the NPN type transistor 11 is connected to the power supply terminal V CC , the NPN type transistor 11 cannot be operated in a saturated state. Therefore, when the base voltage of the NPN type transistor 11 is clamped at GND + V F , the NPN type transistor 11 can be rapidly turned ON when the voltage at the input terminal IN is low. Fig. 10 is a circuit diagram illustrating a NAND logic apparatus to which the first embodiment as illustrated in Fig. 8 is applied. That is, a CMOS control circuit 2' includes P-channel MOS transistors 21 and 21' in parallel between the power supply terminal V CC and the node N 1 , N-channel MOS transistors 22 and 22' in series between the nodes N 1 and N 2 , and N-channel MOS transistors 23 and 23' in series between the MOS transistor 42 and the node N 2 . The MOS transistors 21 to 23 are controlled by a voltage at an input terminal IN 1 , and the MOS transistors 21' and 23' are controlled by a voltage at an input terminal IN 2 . Fig. 11 is a circuit diagram illustrating a NOR logic apparatus to which the first embodiment as illustrated in Fig. 8 is applied. That is, a CMOS control circuit 2" includes P-channel MOS transistors 21 and 21' in series between the power supply terminal V CC and the node N 1 , N-channel MOS transistors 22 and 22' in parallel between the nodes N 1 and N 2 , and N-channel MOS transistors 23 and 23' in parallel between the MOS transistor 42 and the node N 2 . Also, the MOS transistors. 21 to 23 are controlled by a voltage at an input terminal IN 1 , and the MOS transistors 21' and 23' are controlled by a voltage at an input terminal IN 2 . In Fig. 12, which illustrates a D type flip-flop, the first embodiment as illustrated in Fig. 5, 7A, 7B, 7C or 8, or the second embodiment as illustrated in Fig. 9 can be applied to a CMOS inverter 1201. In the above-described embodiments, although the bipolar transistors are of an NPN type, it is possible to use bipolar transistors of a PNP type. As explained hereinbefore, according to the present invention, since the voltage clamp circuit is released in accordance with the voltage at the output terminal, the output voltage swing can be increased.

Claims: A push-pull type logic apparatus comprising: a high power supply terminal (V CC ); a low power supply terminal (GND); an input terminal (IN); an output terminal (OUT); first, second and third nodes (N 1 , N 2 , N 3 ) ; a first NPN type transistor (11) having a collector connected to said high power supply terminal, an emitter connected to said output terminal, and a base connected to said first node (N 1 ); a second NPN type transistor (12) having a collector connected to said output terminal, an emitter connected to said low power supply terminal, and a base connected to said second node (N 2 ); a first P-channel MOS transistor (21) connected between said high power supply terminal and said first node (N 1 ) and having a gate connected to said input terminal; a first N-channel MOS transistor (22) connected between said first node (N 1 ) and said second node (N 2 ) and having a gate connected to said input terminal; a voltage detecting circuit (41) having an input connected to said output terminal and an output connected to said third node (N 3 ); a second P-channel MOS transistor (42) having a source connected to said high power supply terminal, a drain, and a gate connected to said third node (N 3 ); a second N-channel MOS transistor (23) connected between the drain of said second P-channel MOS transistor and said second node (N 2 ) and having a gate connected to said input terminal; a third P-channel MOS transistor (43) having a source connected to said high power supply terminal a drain connected to said third node (N 3 ), and a gate connected to said third node (N 3 ); and a voltage clamp circuit (3) connected between said second node (N 2 ) and said low power supply terminal. An apparatus as set forth in claim 1, wherein said voltage detecting circuit comprises a CMOS inverter. An apparatus as set forth in claim 1, wherein said voltage clamp circuit comprises: a first resistor means (32, 32') connected to said second node (N 2 ); and a third NPN transistor (34) having a collector connected to said second node (N 2 ), an emitter connected to said low power supply terminal, and a base connected to said first resistor means (32, 32'). An apparatus as set forth in claim 3, wherein said first resistor means (32, 32') comprises an ON-state MOS transistor. An apparatus as set forth in claim 3, wherein said voltage clamp circuit further comprises a second resistor means (33, 33') connected between said second node (N 2 ) and the collector of said third NPN type transistor (34). An apparatus as set forth in claim 5, wherein said second resistor means (32, 32') comprises an ON-state MOS transistor. An apparatus as set forth in claim 3, wherein said voltage clamp circuit further comprises a capacitor (35) connected between the base of said third NPN type transistor (34) and said low power supply terminal. An apparatus as set forth in claim 1, wherein said voltage clamp circuit comprises: a resistor means (33, 33') connected to said second node; and a third NPN transistor (34) having a collector connected to said resistor means, an emitter connected to said low power supply terminal, and a base connected to said second node. An apparatus as set forth in claim 8, wherein said resistor means comprises an ON-state MOS transistor. An apparatus as set forth in claim 8, wherein said voltage clamp circuit further comprises a capacitor (35) connected between the base of said third NPN type transistor (34) and said low power supply terminal. An apparatus as set forth in claim 1, further comprising a third N-channel MOS transistor (44) connected between said second node and said low power supply terminal and having a gate connected to said third node (N 3 ) An apparatus as set forth in claim 1, further comprising a fourth N-channel MOS transistor (45) connected between said output terminal and said low power supply terminal and having a gate connected to said third node (N 3 ). A apparatus as set forth in claim 1, further comprising a fourth node N 4 , said first N-channel MOS transistor (22) being connected to said fourth node instead of said second node; and a second voltage clamp circuit (5) connected to said fourth node and to said high and low power supply terminals (Figure 9). An apparatus as set forth in claim 13, wherein said additional voltage clamp circuit comprises: a third resistor means (51) connected between said high power supply terminal and said fourth node; a fourth NPN type transistor (54) having a collector, a base, and an emitter connected to said low power supply terminal; a fourth resistor means (52) connected between said fourth node and the base of said fourth NPN type transistor; and a fifth resistor means (53) connected between said fourth node and the collector of said fourth NPN type transistor.

Inventors: OKAMURA HITOSHI, OKAMURA, HITOSHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1995
Main classification: H03K19
IPC codes: H03K19, H03K17