Fuzzy processor with improved architecture

Abstract: A fuzzy processor with improved architecture, comprising a fuzzy rule processor (1), an internal fuzzy instructions memory, and an internal knowledge base memory, characterized in that it comprises an arithmetic-logic unit (2), a control unit (3) adapted to execute non-fuzzy instructions that are typical of conventional microprocessors, and an internal memory (5) comprising the non-fuzzy instructions.

Description: The present invention relates to a fuzzy processor with improved architecture. It is known that there are various kinds of fuzzy processors. An example of a classic fuzzy processor is the MB94110 processor by Fujitsu, comprising a block that performs fuzzy instructions. Another example is the SAE81C99 processor by Siemens, which can also load various knowledge bases from an external memory, although this is not possible conditionally or concurrently with normal fuzzy processing. Accordingly, known fuzzy processors only process fuzzy instructions and cannot integrate fuzzy control with the processing of classic instructions such as shift, rotate, compare, or arithmetic/logic instructions, and also have no signals such as interrupt, stack, etcetera. Accordingly, it is not possible to perform any kind of arithmetic/logic processing on the inputs and on the outputs of the fuzzy controller. All known fuzzy control units furthermore perform control by processing the fuzzy instructions sequentially, with no possibility of jumping from one instruction to another. Another characteristic of known fuzzy processors is that they process a fixed number of inputs and of fuzzy rules. A certain number of membership functions is associated with each fuzzy input, and the set of these functions is termed knowledge base. Both the set of fuzzy rules and the knowledge base remain unchanged throughout processing. IEEE MICRO, vol. 13, n.5, XP000397922 KAZUO NAKAMURA ET AL "Fuzzy inference and fuzzy inference processor" discloses a fuzzy processor comprising a fuzzy rule processor with an arithmetic-logic unit, and a control unit adapted to execute non-fuzzy instructions. ELEKTRONIK, vol. 41, n.17, 18 August 1992, XP000310952 ROSSMAN J "Der Realismus kehrt ein" also discloses a fuzzy processor comprising an arithmetic-logic unit. Accordingly, the aim of the present invention is to provide a fuzzy processor with improved architecture that is more versatile than known fuzzy processors. Within the scope of the above aim, an object of the present invention is to provide a fuzzy .processor with improved architecture that is capable of handling inputs and outputs. Another object of the present invention is to provide a fuzzy processor with improved architecture capable of loading various knowledge bases or sets of fuzzy rules from outside during normal operation. Another object of the present invention is to provide a fuzzy processor with improved architecture capable of changing the knowledge base or the set of fuzzy rules to be processed during normal processing, conditionally or unconditionally, the conditions occurring on the inputs or on the outputs. Another object of the present invention is to provide a fuzzy processor with improved architecture capable of performing arithmetic/logic processing of the inputs and outputs of the fuzzy controller, of processing non-fuzzy instructions, and of handling interrupt signals. Another object of the present invention is to provide a fuzzy processor with improved architecture capable of performing conditional or unconditional jumps within fuzzy instructions. Another object of the present invention is to provide a processor that is highly reliable, relatively easy to manufacture, and at competitive costs. This aim, these objects, and others which will become apparent hereinafter are achieved by a fuzzy processor as defined in the appended claim 1. The characteristics and advantages of the invention will become apparent from the description cf a preferred but not exclusive embodiment thereof, illustrated only by way of non-limitative example in the accompanying drawings, wherein the only figure is a block diagram of the fuzzy processor with improved architecture according to the present invention. Since known fuzzy processors only process fuzzy instructions and cannot integrate fuzzy control with the processing of classic instructions such as shift, rotate, compare, or of arithmetic-logic instructions, and also have no signals such as interrupt, stack, etcetera. The fuzzy processor according to the present invention is provided with an arithmetic/logic unit (ALU), with a direct memory access control unit (DMA), with a timer, with an interrupt handler, with interfaces for the buses, and other components. The fuzzy instructions are integrated with non-fuzzy instructions, such as arithmetic/logic instructions, shift, rotate, etcetera, according to a definable hierarchy, that is to say, all the instructions that also allow non-fuzzy processing of input and/or output data. Furthermore, the fuzzy control unit according to the present invention can use internal registers of the chip as inputs of the fuzzy section and can also use them as buffer registers for the output of the fuzzy section, and preprocessings on the inputs and postprocessings on the outputs can be performed in these registers. It is stressed that although adders, subtracters, multipliers, and dividers are already present in the classic architecture of a fuzzy control unit and are used for fuzzification and defuzzification, the present invention proposes the concept of arithmetic/logic processing of the inputs and of the outputs, the execution of non-fuzzy instructions, and the handling of interrupt signals; these functions can be performed by using appropriately modified existing blocks or specifically designed circuitry. In particular, input and output processing can be performed almost entirely by existing blocks. In this manner it is possible to integrate fuzzy control with non-fuzzy instructions that accordingly allow to flexibly handle the system to be controlled, and it is furthermore possible to control more complex systems. It is possible to preprocess the inputs of the fuzzy section with arithmetic/logic operations, so as to create new inputs of the fuzzy section as incremental ratios of the input, remove or add an offset, perform digital filterings on the inputs, etcetera. It is also possible to postprocess the outputs of the fuzzy section to adapt them to the outside world, for example by removing or adding an offset, clipping below a maximum value, etcetera. By means of the interrupt signals it is possible, if required, to interrupt control to perform emergency, control, or system management operations by means of non-fuzzy instructions. As mentioned, another problem of known fuzzy control units is that they perform control by processing the fuzzy instructions sequentially, without being able to jump from one fuzzy instruction to another. The fuzzy processor according to the present invention proposes the insertion, among fuzzy rules, of the conditional or unconditional jump instructions, in which the optional condition will have to occur on the inputs or on the outputs. This allows to instantly adapt the fuzzy control to particular changes in the system to be controlled, and therefore to jump within the rules to be processed according to the inputs or outputs obtained. As mentioned above, all known fuzzy control units process a fixed number of inputs and of fuzzy rules. A certain number of membership functions is associated with each input. The set of membership functions is termed knowledge base. Both the set of rules and the knowledge base are invariant throughout processing. Accordingly, the processor according to the present invention is able to change the knowledge base and/or the set of fuzzy rules during normal processing. This is performed by means of a buffer memory, where the next knowledge base and/or set of fuzzy rules to be processed is loaded during normal operation, so that the base or set can be swapped by virtue of an instruction for conditional or unconditional swapping of the rule set or of the knowledge base. The conditions can be imposed on the inputs or on the outputs. This allows adaptive control and furthermore, by associating different inputs with the various knowledge bases, it is possible to process a larger number of inputs and thus to perform more simply the time-sharing control of a plurality of systems. Indeed, this allows to process an infinite number of fuzzy rules. To summarize, the characteristics that are innovative with respect to known fuzzy processors are the possibility of loading from outside the fuzzy rule memory and the knowledge base memory (the membership functions) concurrently (and transparently) with respect to instruction processing; the possibility of processing both fuzzy rules and non-fuzzy instructions (shift, rotate, arithmetic/logic operations, etcetera); the possibility of conditional or unconditional jumps within the set of fuzzy rules that is being processed; and finally, the possibility of conditionally or unconditionally swapping the knowledge base or the set of rules to be processed. The block diagram of the innovative architecture of the fuzzy processor according to the present invention is shown in the only figure. The reference numeral 1 designates the classic fuzzy rule processor, which executes fuzzy rules. An arithmetic/logic unit (ALU) 2 has been included in the processor according to the present invention to perform the arithmetic/logic processing of the inputs and of the outputs. A control unit 3 is furthermore connected to the ALU 2 and is adapted to perform non-fuzzy instructions. An interrupt handler 4 is located inside the control unit 3. The control unit 3 is furthermore connected directly to the fuzzy rule processor 1. The control unit 3 and the ALU 2 are connected to internal registers 17, which are in turn connected to a data memory 18 that acts as a buffer for the internal registers 17. The control unit 3 is also connected to the data memory 18. The internal registers 17, the data memory 18, the ALU 2, and the fuzzy rule processor 1 are connected to a data bus 19. More specifically, the data bus 19 is connected to the ALU 2 by means of two lines, a direct one and a line that passes through a multiplexer 20 which performs a selection so that the second input of the ALU 2 arrives from the data bus or from the control unit 3. An external control line IF/MC 21 is connected to the control unit 3 and sends a signal externally if the processor is executing fuzzy or non-fuzzy instructions. A conventional timer 22 is furthermore connected to the control unit 3 and has its own output line 23. The interrupt signals are sent to the control unit 3 and to the interrupt handler 4 located therein by means of an interrupt line 24. The reset signals are sent to the control unit by means of a reset line 25. The clock signal is sent to the control unit 3 by means of a clock line 26. A data input control unit 27 is furthermore connected to the data bus 19 and to the control unit 3. The control unit 27 is connected to the outside by means of a handshake line 28, an input data line 29, and an input number selection line 30 for selecting an input among the multiple available inputs. A data output control unit 31 is furthermore likewise connected to the data bus 19 and to the control unit 3. Said control unit is connected to the outside by means of a handshake line 32, an output data line 33, and an output number selection line 34 for externally indicating which among the plurality of available outputs is on the output data line 33. The processor according to the present invention is furthermore provided with an internal RAM memory 5 directly connected to the fuzzy rule processor 1 and to the control unit 3. The RAM memory 5 furthermore internally comprises, besides other components, a microcode memory (MCM) 6. Said microcode memory 6 stores all the non-fuzzy instructions and is directly connected to the control unit 3, so that said instructions are executed by said control unit. The internal RAM memory 5 furthermore includes a fuzzy instruction memory 7 (IFM) that is conveniently divided into two parts, IFM 1 and IFM2. Said fuzzy instruction memory 7 comprises all the fuzzy instructions that must be executed by the fuzzy rule processor 1 to which the memory 7 is directly connected. The choice of having two separate memories for fuzzy instructions and non-fuzzy instructions is due to the different bit sizes of the two kinds of instructions. The internal RAM memory 5 furthermore comprises a knowledge base memory 8 that is conveniently divided into two parts ADM1 and AMD2 (Antecedent Data Memory) and is directly connected to the fuzzy rule processor 1. An external memory 9 is furthermore associated with the processor according to the present invention and can advantageously be an internal one; it comprises an external knowledge base memory 10, an external fuzzy rule memory 11, and an external microcode memory 12. The external knowledge base memory 10 is divided into multiple banks, each of which contains a knowledge base, from bank 1 to bank i, and the external fuzzy rule memory 11 is also divided into multiple banks, each bank containing a different set of rules, from bank 1 to bank n. The external memory 9, with its respective internal memories 10, 11, and 12, is connected to the internal RAM memory 5 by means of a direct memory access control unit (DMA) 13 and a demultiplexer 14. The memories 10, 11, and 12 are connected to the DMA 13 by means of a data line 15, whereas the DMA 13 is connected to the external memory by means of a memory address line 16. The DMA allows us to load knowledge bases and sets of fuzzy instructions in the corresponding buffer memories concurrently with normal processing. The operation of the fuzzy processor according to the present invention is as follows. The arithmetic/logic unit 2 performs the arithmetic/logic processing, whereas the non-fuzzy instructions are performed by the control unit 3. The non-fuzzy instructions reside in the microcode memory 6 and are performed directly by the control unit 3, whereas the fuzzy rules are stored in the fuzzy instruction memory 7, and the task of processing the fuzzy rules is assigned to the fuzzy rule processor 1. The control unit 3 can order the execution of a certain number n of fuzzy instructions processed by the fuzzy processor 1 and then resume control. Interrupts are requested by means of the interrupt line 24 and performed by the interrupt handler 4 located inside the control unit 3. After resetting the processor, by means of a signal sent over the reset line 25, execution of the instructions starts from address 0 of the microcode memory 6 and continues to process the non-fuzzy instructions until it encounters the instruction that orders the execution of a number n of fuzzy rules from a given memory address IFM 5. The n fuzzy rules are executed by the fuzzy rule processor 1 by taking them from the fuzzy instruction memory 7; then the execution of non-fuzzy instructions resumes. The non-fuzzy instructions also include the instruction ordering processing of the fuzzy instructions in a continuous cycle (as in classic fuzzy control units) and can be interrupted only by an intervening interrupt. The fuzzy rules can process the inputs taken directly from the outside by means of the data input control unit 27 or the inputs residing in the internal registers 17, which in this case may have been preprocessed by the control unit 3. The outputs of the fuzzy rule processor 1 can furthermore be sent immediately outside by means of the data output control unit 31 or placed in the internal registers 17, so that they can be postprocessed by the control unit 3 before being sent outside the processor. In order to perform conditional jumps inside fuzzy rules, a jump instruction has been inserted among the fuzzy instructions contained in the fuzzy instruction memory 7; as an alternative, this can be done by means of the fuzzy control unit. The possibility of changing the knowledge base or the set of fuzzy rules to be processed during normal processing is provided by means of the DMA 13, which transparently loads from the external memory 9 the new knowledge base and/or the set of rules to be processed. The internal knowledge base memory 8 and the internal fuzzy instruction memory 7 inside the internal RAM memory 5 are duplicated in memories ADM1-ADM2 and IFM1-IFM2 respectively, since while the fuzzy rule processor 1 processes rules residing in one of the fuzzy instruction memories IFM by using the knowledge base that resides in a knowledge base memory ADM, the DMA 13 can load the other memories (by taking the data from the external memory 9), and therefore the instruction for swapping the knowledge base or the set of fuzzy rules to be processed simply swaps the internal memories to be processed. This last instruction can be conditional or unconditional, and the conditions to be verified may occur on the inputs and on the outputs of the fuzzy rule processor 1 or also on the non-fuzzy processing value. From the above description it is evident that the present invention fully achieves the intended aim and objects. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: A fuzzy processor, comprising a fuzzy rule processor (1), an internal memory (5) comprising a fuzzy instruction memory (7) and an internal knowledge base memory (8), an arithmetic/logic unit (2), and a control unit (3) adapted to execute non-fuzzy instructions that are typical of conventional microprocessors and fuzzy instructions, characterized in that said internal memory (5) further comprising an internal microcode memory (6) for storing non-fuzzy instructions, and in that it further comprises an external memory (9) comprising an external knowledge base memory (10), an external fuzzy instruction memory (11), and an external non-fuzzy instruction memory (12), said control unit having direct memory access and being adapted to transparently swap data between said external memories (10, 11, 12) and said internal memories (6, 7, 8). The fuzzy processor according to claim 1, characterized in that said control unit (3) internally comprises an interrupt handler ((4). The fuzzy processor according to claim 1, characterized in that said internal knowledge base memory (8) and said internal fuzzy instruction memory (7) are both composed of a first and of a second parts (ADM1, ADM2; IFM1, IFM2). The fuzzy processor according to claim 1, characterized in that it comprises internal registers (17) associated with said control unit (3) and said arithmetic/logic unit (2). The fuzzy processor according to claim 4, characterized in that it comprises a data memory (18) associated with said internal registers (17). The fuzzy processor according to claim 1, characterized in that it comprises a data input unit (27) and a data output unit (31). The fuzzy processor according to. claim 1, characterized in that said internal fuzzy instruction memory (7) comprises at least one jump instruction. The fuzzy processor according to claim 7, characterized in that said at least one jump instruction is a conditional jump instruction. The fuzzy processor according to claim 1, characterized in that it comprises a clock associated with said control unit (3). The fuzzy processor according to one or more of the preceding claims, characterized in that it comprises a data bus (19) connected to said control unit (3), to said fuzzy rule processor (1), to said arithmetic/logic unit (2), to said data input unit (27), to said data output unit (31), and to said internal registers (17). The fuzzy processor according to one or more of the preceding claims, characterized in that it processes an unlimited number of inputs and/or fuzzy rules and/or performs time-sharing control of a plurality of processes and/or adaptive control. The fuzzy processor according to claim 7, characterized in that said at least one jump instruction is a unconditional jump instruction.

Inventors: CATANIA VINCENZO, GIACALONE BIAGIO, PAPPALARDO FRANCESCO, PELOS ENRICO, CATANIA, VINCENZO, GIACALONE, BIAGIO, PAPPALARDO, FRANCESCO, PELOS, ENRICO
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO - CORIMME
Application year: 1995
Main classification: G06F7
IPC codes: G06F9, G06N7