Circuit for automatically regulating the gain of a differential amplifier

Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

Description: The present invention relates to a circuit for automatically regulating the gain of a differential amplifier as defined in the preamble to Claim 1. In many applications it is necessary to amplify a signal of variable amplitude in a manner such that the level of the amplifier signal is substantially constant. For this purpose, amplifiers with gains which can be regulated according to the level of the output signal by means of a suitable feedback loop are used. A circuit for automatically regulating the gain of a differential amplifier is known from WO-A-9 319 466. A further example of a known circuit for automatically regulating the gain of a differential amplifier is shown schematically in Figure 1. A differential amplifier, indicated VGA, with variable gain, receives a signal, for example, a sinusoidal signal, between its two inputs, indicated v+ and v-, and produces, between its outputs out+ and out-, a signal which is amplified in comparison with the input signal to an extent which depends upon a signal applied to a control terminal thereof, indicated CTR. The outputs of the amplifier are connected to a full-wave rectifier, indicated FWR, which produces, at its output OUTfwr, a signal which is composed of a succession of unidirectional half-waves corresponding to the half-waves of the output signal of the amplifier VGA, relative to a constant voltage present at a terminal indicated REFfwr. A comparator COMP has a non-inverting input IN+ connected to the output OUTfwr of the rectifier and an inverting input IN- connected to a reference generator Gref. The latter is formed by a current generator Ir and by a resistor Rr connected in series between a supply voltage terminal Vdd and the reference terminal REFfwr of the rectifier. The voltage applied to the input IN- of the comparator COMP is given by the sum of the reference voltage at the terminal REFfwr and the voltage drop Ir·Rr, where the current Ir and the resistance Rr are indicated by the same symbols as the corresponding components. The output of the comparator COMP is connected to a circuit of the so-called charge-pump type constituted by a storage circuit Str, by a buffer amplifier A and by a cell RC formed by a capacitor C and by a resistor R. The storage circuit Str is constituted by a capacitor Ca and by two current generators I and a·I, where a is a fraction of 1, connected in series with one another between the pole Vdd of the supply and earth by means of an electronic switch SW. The electronic switch SW is controlled by the output of the comparator COMP. The capacitor C has one terminal connected to earth and the other connected to the resistor R and to a voltage/current convertor V/I, the output of which is connected to the control terminal CTR of the amplifier VGA. The operation of the circuit will now be considered. If the output OUTfwr of the rectifier is less than the voltage applied to the inverting input of the comparator COMP, the switch SW is open. The capacitor Ca is charged by the current a·I so that the current supplied to the capacitor C of the cell RC through the buffer A increases and the capacitor C is charged, causing the current at the control terminal CTR, and hence the gain of the differential amplifier, to increase. If the output OUTfwr of the rectifier is equal to or greater than the voltage at the inverting input of the comparator COMP, the switch SW closes so that the capacitor Ca discharges with a current I-a·I and the voltage applied to the cell RC decreases causing the regulating current, and hence the gain of the amplifier VGA, to decrease. In steady state operation, the peak-peak amplitude of the output signal of the amplifier VGA stabilizes at a constant value determined by the voltage of the reference generator Gref. The known circuit described above operates satisfactorily as long as the input signal of the amplifier VGA is symmetrical, that is, is constituted by positive and negative half-waves of the same amplitude. If, however, the input signal is asymmetrical the gain is determined exclusively by the half-wave of greater amplitude. This may constitute a problem if the signal contains binary data which have to be interpreted as logic levels 1 or 0 according to whether the amplitude is above or below a predetermined value. The problem is even more serious when the asymmetry is variable over time, since the peak-peak amplitude determined by the reference value of the generator Gref may become inadequate for correct reading of the data associated with the half-waves of lower amplitude. A situation of this type may occur when the input signal of the differential amplifier VGA comes from a magnetoresistive head for reading memories on magnetic media (for example "hard disks"). The object of the present invention is to propose a circuit for automatically regulating the gain of a differential amplifier which operates satisfactorily even when an asymmetrical signal is to be amplified. This object is achieved by the circuit defined and characterized in general in Claim 1. The invention will be understood better from the following detailed description of an embodiment thereof given by way of example with reference to the appended drawings, in which: Figure 1, which has already been described, is a diagram showing the concept of a known circuit for automatically regulating the gain of a differential amplifier, Figure 2 is a diagram showing the concept of a device which incorporates an automatic gain-regulating circuit according to the invention, Figure 3 is a partial block diagram and a partial circuit diagram of the regulating circuit according to the invention, and Figure 4 is a simplified circuit diagram of a double half-wave rectifier usable in the circuit of Figure 3. Figure 2, in which elements identical to those of the circuit of Figure 1 are indicated by the same reference symbols, shows a circuit according to the invention used to produce a signal of constant amplitude from the output signal of a magnetoresistive reading head, indicated RH, of a magnetic-disc data-recording unit. The signal produced by the head, which is a normally asymmetrical alternating voltage and may have a peak-peak amplitude variable of, for example, between 10 and 20 µV, is amplified in a voltage amplifier VA, for example, with a gain of 1000, and is then applied to the differential inputs of a differential amplifier with variable gain VGA. The output of the latter amplifier is regulated, as will be described below, and is applied, through a low-pass filter LP, to a threshold detector circuit THD which extracts from the signal the digital data content corresponding to that recorded on the disc for use in a data-processing system, not shown. In order to regulate the gain, the output of the differential amplifier VGA is connected to the inputs in+, in- of a double half-wave rectifier, indicated DHWR, with the function of detecting the levels of the half-waves of the signal. This rectifier supplies the positive half-waves of the input voltage signal at one output OUT1 and the rectified negative half-waves of the same signal at another output OUT2, relative to a fixed reference voltage available at a terminal REF. This fixed voltage is selected so as to be equal to the voltage present at the output terminals OUT1 and OUT2 when the difference between the voltages present at the inputs in+ and in- is equal to zero. Two comparators COMP1 and COMP2 have respective first inputs IN+1 and IN+2 connected to the respective rectifier outputs OUT1 and OUT2, and respective second inputs IN-1 and IN-2 connected to reference generators Gref1 and Gref2, respectively. Each of these two reference generators generates a reference voltage depending on a signal which is applied to a suitable terminal a1, a2, respectively, and which varies in dependence on the degree of asymmetry of the input signal of the amplifier VGA. The outputs of the comparators COMP1 and COMP2 are connected to signal-processing means which comprise two storage circuits each connected downstream to a buffer amplifier and to a resistor similar to those of the circuit of Figure 1. It should be noted that the components similar to those of Figure 1 are indicated by the same reference symbols with the addition of a "1" or a "2". The outputs of the buffer amplifiers A1 and A2 are connected, by means of respective resistors R1 and R2, to a circuit node N to which a terminal of a capacitor C is also connected, its other terminal being connected to earth. The resistors R1, R2 and the capacitor C together constitute a cell RC similar to the cell RC of the circuit of Figure 1. By way of indication, in a fully-integrated embodiment of the circuit, the capacitances of the two capacitors Ca may be about 10 pF and that of the capacitor C 10-20 pF. The operation of the circuit of Figure 2 will now be considered. If both of the outputs OUT1 and OUT2 of the rectifier DHWR are below the reference voltages applied to the terminals IN-1 and IN-2 of the comparators COMP1 and COMP2, respectively, the switches SW1 and SW2 are open and the capacitors Ca1 and Ca2 are charged by the currents a·I1 and a·I2 (where a is again a fraction of 1). The capacitor C is supplied with a current which is given by the sum of the currents output by the amplifiers A1 and A2 so that it is charged causing the current at the regulation terminal CTR, and hence the gain of the differential amplifier VGA, to increase. If one output OUT1 or OUT2 of the rectifier DHWR is equal to or greater than the reference voltage at the inverting input of the respective comparator COMP1 or COMP2, the respective switch SW1 or SW2 closes so that the respective capacitor Ca1 or Ca2 discharges until a current I1-a·I1 or I2-a·I2 , thus interrupting its contribution to the charging of the capacitor C. In steady state operation, the charge in the capacitor C, and hence the regulating current at the terminal CRT, is a function of the voltages Vc1 and Vc2 present at the outputs of the storage circuits Str1 and Str2. Since these voltages depend on the charges of the capacitors Ca1 and Ca2 which in turn depend on the states of the switches Sw1 and Sw2, the signal for regulating the amplifier VGA depends on the durations of the output signals of the two comparators COMP1 and COMP2. Clearly, in summary, the gain of the amplifier VGA is regulated with account being taken of the independent contributions of the positive and negative half-waves so that the peak-peak amplitude of the output signal of the amplifier VGA stabilizes, in steady state operation, at a constant value which depends upon the reference voltages supplied to the comparators by the reference generators Gref1 and Gref2. As stated above, these are regulated in dependence on the asymmetry of the input signal of the amplifier VGA by means of a suitable regulation of the reference generators by means of signals applied to the terminals a1 and a2. A circuit for automatically regulating the reference voltages applied to the comparators is shown in Figure 3, in which elements identical to those of Figure 2 are indicated by the same reference symbols. This circuit, which is enclosed by a broken line and generally indicated Gref, performs the function of a reference-voltage generator which was performed by the blocks Gref1 and Gref2 in Figure 2. As can be seen, it is a differential amplifier constituted by two N-channel MOS transistors, indicated M1 and M2 with their source terminals connected, each through a resistor Rs, to a generator of a constant current Io, connected to earth, and with their drain terminals connected to the positive pole Vdd of the supply by means of respective current mirrors CM1 and CM2. The output branches of the current mirrors are connected to the terminal REF of the rectifier DHWR by means of load resistors Rl1, Rl2. The gate terminals of the transistors M1 and M2 constitute two inputs of the amplifier Gref and are connected to the outputs Vc1 and Vc2 of the storage circuits Str 1 and Str2. The points at which the resistors Rl1 and Rl2 are connected to the circuit branches of the current mirrors constitute the outputs of the amplifier Gref and are connected to the inputs IN-2 and IN-1 of the two comparators COMP2 and COMP1, respectively. The voltages Vref2 and Vref1 applied to these inputs are formed by the sum of the reference voltage at the terminal REF and of the drops in the resistors Rl1 and Rl2. The voltages Vref1 and Vref2 will tend to vary in a manner such that, in steady state operation, the average of the amplitudes of the peaks of the half-waves at the terminals OUT1 and OUT2 is equal to (Io/2)·Rl where Io is the current of the generator indicated by the same symbol and Rl is the resistance of the resistors Rl1 and Rl2. The gain of the differential amplifier VGA is thus determined completely automatically on the basis of the amplitudes of both of the half-waves of the output signal of the amplifier . More particularly, in steady state operation, the output voltages of the storage circuits Str1 and Str2 have saw-toothed waveforms the leading edges of which have gradients of a·I1/C1 and a·I2/C2 , respectively, and the trailing edges of which have gradients of (I1-a·I1)/C1 and (I2-a·I2)/C2 , respectively. If the signal is not symmetrical, the leading and trailing edges of the two waveforms have different durations. The resistors R1 and R2 provide, at the node N, a voltage which, in steady state operation, is the average value of the voltages produced by the storage circuits Str1 and Str2 smoothed by the capacitor C which acts as a low-pass filter. The voltage present at the node N is converted into a current by the converter V/I and is applied to the differential amplifier VGA through its control terminal CTR. The resistors R1 and R2 may be of adjustable type for precise calibration of the circuit. The circuit diagram of a known double half-wave rectifier, is shown in Figure 4. As can be seen, it is constituted by a differential amplifier DIF and by a circuit portion for producing, at the terminal REF, a reference voltage, the value of which is equal to the voltage at each of the outputs OUT1 and OUT2 when the difference between the voltages at the inputs in+ and in- is zero. Although a single embodiment of the invention has been described and illustrated, clearly many variations and modifications are possible within the scope of the same inventive concept which is defined in claim 1. For example, digital circuits (adding/subtracting counters, registers) could be used as means for processing the signal output by the comparators instead of the analog circuits described.

Claims: A circuit for automatically regulating the gain of a differential amplifier (VGA), comprising: means for detecting the level of the output signal of the amplifier, and comparison and processing means for supplying a regulating signal at a control terminal (CTR) for regulating the gain of the amplifier if the level detected by the detector means deviates from a predetermined value, characterized in that the detector means comprise a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce, at first and second outputs (OUT1, OUT2), respectively, first and second quantities dependent on the amplitudes of the positive and negative half-waves of the output signal of the amplifier, respectively, relative to a predetermined reference level (REF), and the comparison and processing means comprise first and second comparators (COMP1, COMP2) each having a signal input (IN+1, IN+2) connected to the first and second output (OUT1, OUT2) of the rectifier (DHWR), respectively, and a reference input (IN-1, IN-2) connected to means (Gref1, Gref2, Gref) for generating reference levels in order to produce respective output signals when the first and second quantities are greater than the reference levels applied to the respective reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) connected to the outputs of the first and second comparators (COMP1, COMP2) for generating the aforementioned regulating signal in dependence on the durations of the output signals of the two comparators. A circuit according to Claim 1, in which the processing means comprise first and second charge-storage circuits (Str1, Str2) connected to the outputs of the first and second comparators (COMP1, COMP2), respectively, in order to produce respective voltages (Vc1, Vc2) depending on the durations of the output signals of the respective comparators, means (R1, R2) for finding the average value of the voltages produced by the charge-storage circuits, and low-pass filter means (C) connected between the means for finding the average value (R1, R2) and the control terminal (CRT) of the differential amplifier (VGA). A circuit according to Claim 2, in which the means for finding the average value comprise two resistors (R1, R2) each connected to an output of a storage circuit (Str1, Str2) and to a common circuit node (N), and the low-pass filter means comprise a capacitor (C) connected to the common circuit node (N). A circuit according to Claim 3, in which a buffer amplifier (A1, A2) is provided between each storage circuit (Str1, Str2) and the respective resistor (R1, R2). A circuit according to any one of the preceding claims, in which the means (Gref) for generating reference levels are connected to the outputs (Vc1, Vc2) of the first and second charge-storage circuits (Str1, Str2) in order to produce two reference levels dependent on the voltages present at these outputs. A circuit according to Claim 5, in which the means for generating reference levels comprise a differential circuit (Gref) having one of its inputs connected to the first storage circuit (Str1) and another input connected to the second storage circuit (Str2) and each of its outputs connected to one of the reference inputs (IN-1, IN-2) of the comparators (COMP1, COMP2).

Inventors: BRUCCOLERI MELCHIORRE, DEMICHELI DAVIDE, DEMICHELI MARCO, PATTI GIUSEPPE, BRUCCOLERI, MELCHIORRE, DEMICHELI, DAVIDE, DEMICHELI, MARCO, PATTI, GIUSEPPE
Applicants: CONS RIC MICROELETTRONICA, ST MICROELECTRONICS SRL, CO.RI.M.ME., STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: H03G1
IPC codes: H03G3, H03G1, G11B5