Interface circuit

Abstract: An interface circuit comprising a digital to analog converter which comprises a register for receiving and holding each bit of a digital signal, a capacitive coupling for integrating total bits held in the register with weighting, an inverted amplifier circuit for receiving an output of the capacitive coupling and for outputting an analog output voltage, and a feedback capacitance for connecting an outputs of the inverted amplifier circuit to an input of the inverted amplifier circuit, an analog signal line to which the analog output voltage is connected, and an analog to digital converter which comprises a plurality thresholding circuits with stepwise thresholds to which the analog signal line is commonly inputted, each the thresholding circuit receiving outputs of the thresholding circuits of higher threshold with weighting so that the thresholding circuits repeatedly change the outputs from high level to low level or from low level to high level.

Description: Such an interface circuit is described in US-A-4,654,815. This reference describes an analog signal conditioning and digitizing integrated circuit, which comprises a multiplying digital-to-analog converter (MDAC) and an analog-to-digital converter (ADC). The MDAC includes a gain capacitor array, an offset capacitor array, an operational amplifier, a buffer, control logic, a feedback capacitor and other means. The ADC includes a serial shift register, a successive approximation register, a comparator and a capacitor array among other means. A conversion is accomplished by successively switching the isolated plate of each capacitor of the capacitor array between analog ground and a reference voltage. Following each switch the voltage on the common plate of the capacitor array is compared to the output of the output correction circuit. The result of the comparison is used to either reset or leave set the switches connected to the most recently switched (tested) capacitor. The ADC is sequenced by shifting a bit through the shift register. The compare operation is done by the comparator and the test or reset operation are both done by the successive approximation register. The inventors of the present invention have proposed an interface circuit for converting signals from binary to multi-level signals as well as from multi-level to binary signals in JP-04 301740. This circuit converts a binary signal in a device into a multi-level signal and transmits it to another device. The multi-level signal is converted by the interface circuit into a binary signal again in the latter device. This circuit has the problem that a divider circuit is used consisting of a plurality of resistors connected in series. The circuit consumes rather a lot of electrical power. It is the object of the present invention to provide an interface circuit which comprises an improved analog-to-digital converter. This object is achieved by an interface circuit according to claim 1. Preferred embodiments of the invention are the subject matters of the dependent claims. The advantage of the interface circuit's analog-to-digital converter is that it does not require a clock and can therefore perform a faster digitization. Figure 1 is the first embodiment of an interface circuit according to the present invention, Figure 2 is a quantizing circuit in Figure 1, Figure 3 is a refresh circuit of the same embodiment, Figure 4 is the second embodiment of the present invention, and Figure 5 is a block diagram showing another embodiment of the refresh circuit. Hereinafter an embodiment of an interface circuit according to the present invention is described with referring to the attached drawings. Figure 1 shows an interface circuit for converting a binary output DD from a digital device D1 into an analog signal and for transmitting the analog signal to another digital device D2. The circuit has a register R1 for holding an output of D1. R1 has parallel input and parallel output terminals. A register of serial input and parallel output, such as shift register, can be used as the register R1. An output of register R1 is inputted to a capacitive coupling CP1 and weighted addition is performed here. Capacitive coupling CP1 consists of parallelly connected capacitances C11, C12, C13 and C14 and performs a weighting of each bits of digital data DD by C11, C12, C13 and C14 corresponding to binary weight of each bit. The capacity ratio is set to be C11:C12:C13:C14 = 8:4:2:1. An output of capacitive coupling CP1 is inputted to an inverting amplifier INV1 consisting of 3 stages CMOS inverters I1, I2 and I3, and INV1 has a large gain given by a multiplication of open gains of 3 inverters stages. An output of INV1 is connected to its input through a electricity saving switch SW1 and a feedback capacitance CF1, and an output V1 of INV1 has a value in the following formula (2) determined by a ratio of CP1 and CF1 provided that SW1 is closed. Here, CF1 is defined in formula 3, and V1 is a normalized value. CF1 = C11+C12+C13+C14 The output V1 of the inverted amplifier INV1 is transmitted to device D2 through an analog signal line ASL, and is binarized by a quantizing circuit Q 1 in a front stage of D2. The output of the quantizing circuit Q 1 is inputted to the device D2 after being held in a register R2 similar to the register R1. A voltage driven type D/A converting circuit DA is realized by R1, CP1, INV1 and CF1. In Figure 2, the quantizing circuit Q1 is composed of 4 stages thresholding circuits Th1, Th2, Th3 and Th4 from the lowest threshold to the highest threshold, which generate outputs Q1d, Q1c, Q1b and Q1a, respectively. The output of each thresholding circuit is inputted to lower thresholding circuits. The lowest thresholding circuit Th1 has a capacitive coupling CP21 for receiving V1, Q1a, Q1b and Q1c and inverting amplifier INV24 connected to CP21. The output Q1d is generated as an output of inverting amplifier INV24. CP21 is composed of capacitances C231, C232, C233, C234, C235 and C236, to which V1, Q1a, Q1b, Q1c, a the voltage of the electrical source Vd and the ground are connected, respectively. The voltage of the electrical source Vd is inputted for controlling a threshold of INV31 and the voltage of the ground is inputted for controlling the total capacity of CP21. Thresholding circuit Th2 of the 2nd threshold from the bottom has a capacitive coupling CP22 for receiving V1, Q1a, Q1b, the voltage of the electrical source Vd and the ground and inverted amplifier INV23 connected to CP22. The output Q1c is generated as an output of the inverted amplifier INV23. CP22 is composed of capacitances C221, C222, C223, C224 and C225, to which V1, Q1a, Q1b, the voltage of the electrical source Vd and the ground are connected, respectively. The voltage of the electrical source Vd is inputted for controlling the threshold of INV23 and the voltage of the ground is inputted for controlling the total capacity of CP22. Thresholding circuit Th3 of the third thresholding circuit from the bottom has capacitive coupling CP23 for receiving Q1a, the voltage of the electrical source Vd and the ground and an inverted amplifier INV22 connected to an output of CP23. The output Q1b is generated as an output of inverted amplifier INV22. CP23 is composed of capacitances C211, C212, C213 and C214, to which V1, Q1a, the voltage of the electrical source and the ground are connected, respectively. The voltage of the electrical source is inputted for controlling a threshold value of INV22 and the voltage of the ground is inputted for controlling the total capacity of CP23. Thresholding circuit Th4 of the highest threshold has an inverted amplifier INV21 for receiving the voltage V1, and the output Q1a is generated as an output of INV21. Table 1 shows capacities of capacitances CP21, CP22 and CP23, and Table 2 shows outputs Q1a, Q1b, Q1c and Q1d corresponding to input voltage V1. Cu in Table 1 is a unit capacity as a common unit of capacitances in a LSI, which may be the smallest capacity formed in LSI or rather small capacity easily formed in the LSI. In Table 2, a voltage Va represents a voltage value of (Vd/16). Capacitive Coupling Capacitance Capacity CP21 C231 16Cu C232 8Cu C233 4Cu C234 2Cu C235 Cu C236 Cu CP22 C221 8Cu × 2 C222 4Cu × 2 C223 2Cu × 2 C224 Cu × 2 C225 Cu × 2 CP23 C221 4Cu × 4 C212 2Cu × 4 C213 Cu × 4 C214 Cu × 4 Input Voltage Output Voltage In Q1d Q1c Q1b Q1a 0≦Vin<Va Vd Vd Vd Vd Va≦Vin<2Va 0 Vd Vd Vd 2Va≦Vin<3Va Vd 0 Vd Vd 3Va≦Vin<4Va 0 0 Vd Vd 4Va≦Vin<5Va Vd Vd 0 Vd 5Va≦Vin<6Va 0 Vd 0 Vd 6Va≦Vin<7Va Vd 0 0 Vd 7Va≦Vin<8Va 0 0 0 Vd 8Va≦Vin<9Va Vd Vd Vd 0 9Va≦Vin<10Va 0 Vd Vd 0 10Va≦Vin<11Va Vd 0 Vd 0 11Va≦Vin<12Va 0 0 Vd 0 12Va≦Vin<13Va Vd Vd 0 0 13Va≦Vin<14Va 0 Vd 0 0 14Va≦Vin<15Va Vd 0 0 0 15Va≦Vin<16Va 0 0 0 0 The quantizing circuit generates digital output Q1a, Q1b, Qlc and Q1d, this means that a voltage driven type A/D converting circuit AD is realized. A refresh circuit Q2 is connected between INV1 and Q1, which compensates the linearity and stability of the input of the quantizing circuit Q1. In Figure 3, the refresh circuit includes a quantizing circuit similar to Q1 following to Q2, and a capacitive coupling CP3 for receiving the outputs of Q1 and a inverting amplifier INV3 connected to an output of CP3. An output of INV3 is connected through a feedback capacitance Cf3 to its input, similar to the circuit of INV1. The power saving switch (Figure 1) makes the feedback system of inverting amplifier INV1 invalid so that the nMOS or pMOS of the INV1 is in the cut-off area of their operation area. In the cut-off area, no electrical current occurs through the nMOS or pMOS, so the INV1 does not generate electrical current and the consumed power can be ignored. Figure 4 shows the second embodiment for both A/D and D/A converting. This embodiment includes a pair of combination circuits ADDA 1 and ADDA2, each of which is a combination circuit of the above circuits AD and DA. ADDA1 and ADDA2 are connected to opposite ends of the analog signal line ASL, respectively. Outputs of circuit DA and inputs of circuit AD are connected to a multiplexer MUX for alternatively connecting AD or DA to the ASL. ADDA1 and ADDA2 are connected in reverse, that is, AD of ADDA1 is connected to ASL when DA of ADDA2 is connected to ASL, and DA of ADDA1 is connected to ASL when AD of ADDA2 is connected to ASL. This embodiment enables bi-directional conversion of A/D and D/A. Figure 5 shows a refresh circuit of bi-directional conversion in which switches SW51 and SW52 are connected to opposite terminals of input and output of the refresh circuit Q2 mentioned above. The switch SW51 1 selects lines from the left or from the right in Figure 5 to be inputted to Q2, and SW52 selects lines left or right to be inputted to Q2. SW51 and SW52 are interlocked so that the connections of the input from the left and the output to the right or the input from the right and the output to the left are alternatively settled. This bi-directional refresh circuit expands usages of the interface circuit above. As mentioned above, an interface circuit according to the present invention integrates digital signals by means of a capacitive coupling so as to convert them into an analog signals, while an analog signal is binarized by means of quantizing circuit consisting of a plurality of thresholding circuits, so that a voltage driven type analog/digital and digital/analog converters are realized and the electric power consumption is saved in the voltage driven type, not the current driven type .

Claims: An interface circuit comprising: a digital to analog converter (DA) which comprises: a register (R1) for receiving and holding each bit of a digital signal; a capacitive coupling (CP1) for integrating all bits held in said register (R1) with weighting; an inverting amplifier circuit (INV1) for receiving an output of said capacitive coupling (CP1) and for outputting an analog output voltage (V1); and a feedback capacitance (CF1) for connecting an output of said inverted amplifier circuit to an input of said inverting amplifier circuit (INV1); an analog signal line (ASL) to which said analog output voltage is connected; and an analog to digital converter (AD) characterized in that said analog to digital converter (AD) comprises a plurality thresholding circuits (Th1, Th2, Th3, Th4) with stepwise thresholds, each said thresholding circuit receiving said analog signal line (ASL) and weighted outputs of more significant thresholding circuits so that said thresholding circuits repeatedly change said outputs from high level to low level or from low level to high level. An interface circuit as claimed in claim 1 further comprising: said analog signal line is alternatively connected either to said analog output voltage or an input of said analog to digital converter (AD); and a switching means (MUX) for connecting either an output of said digital to analog converter or said input of said analog to digital converter (AD) to said analog signal line. An interface circuit as claimed in claims 1 or 2, further comprising a refresh circuit (fig. 5) which comprises: a direction switching means (SW51, SW52) for switching input/output direction along the signal transmitting direction of said analog signal line (ASL); a plurality of thresholding circuits (Th1, Th2, Th3, Th4) of stepwise thresholds to all of which an output of said direction switching means (SW51) is inputted, each said thresholding circuit received weighted outputs of more significant thresholding circuits so that said thresholding circuits repeatedly change said outputs from high level to low level or from low level to high level; a capacitive coupling (CP3) to which said outputs of said thresholding circuits are input; an inverting amplifier circuit (INV3) to which an output of said capacitive coupling (CP3) is input; and a feedback capacitance (Cf3) for connecting an output of said inverting amplifier circuit (INV3) to an input of said inverting amplifier circuit (INV3). An interface circuit as claimed in claims 1 or 2, further comprising a power saving switch (SW1; SW2) for opening a circuit connecting said input and output of said inverting amplifier circuit (INV1, INV3).

Inventors: MOTOHASHI KAZUNORI, SHOU GUOLIANG, TAKATORI SUNAO, YAMAMOTO MAKOTO, MOTOHASHI, KAZUNORI, SHOU, GUOLIANG, TAKATORI, SUNAO, YAMAMOTO, MAKOTO, Motohashi, Kazunori, c/o Yozan Inc., Shou, Guoliang, c/o YOZAN Inc., TAKATORI, SUNAO, C/O YOZAN INC., YAMAMOTO, MAKOTO, C/O YOZAN INC.
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1995
Main classification: G06J1
IPC codes: G06J1, H03M1