D flip-flop having asynchronous data loading

Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

Description: This invention relates to logic networks of the sequential type, and particularly to bistable circuits -- more commonly referred to as flip-flops in the pertinent literature -- of the D type, conventionally comprised of two cascaded bistable circuits, namely a master and a slave circuit. Flip-flops of the D type are used to provide a delay in the transmission of data; the propagation of such data from the master section to the slave section only being allowed on the occurrence of a given clock signal. However, there are applications in which storage elements of the synchronous type, but capable of performing an asynchronous data loading function as well, must be used. Examples of such applications are the parallel-to-serial converter and the counter with asynchronous data preloading. A prior technical solution consists of adding a suitable external logic to a D-type flip-flop having "preset" and "set" capabilities, e.g. as in the counters sold under selling code HCC/HCF40192B by this Applicant. Another prior solution, suitable for use in a wide range of applications and being of greatly simplified design circuit-wise, is disclosed in US-A-4,970,407. A flip-flop of the D type is proposed therein which inherently performs the asynchronous data storage function. Accordingly, the storage element can be a compact one requiring less area of integration on the silicon and effectively avoiding possible problems from the presence of a complementary external logic. Shown in Figure 1 of the drawings is a circuit diagram for such a flip-flop which directly permits of asynchronous data loading. The technical problem underlying this invention is to provide a flip-flop of the D type which also performs the asynchronous data loading function and affords improved control capabilities over prior solutions. This technical problem is solved by a flip-flop as outlined above and defined in the characterizing part of the appended claims to this specification. The features and advantages of a flip-flop of the D type according to the invention will be apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. In the drawings: Figure 1 shows a prior art (US-A-4 970 407) circuit diagram for a flip-flop of the D type having an asynchronous data loading function; Figure 2 shows a diagram, partly in block form, of a flip-flop of the D type having an asynchronous data loading function, according to the invention; and Figure 3 shows a circuit diagram for a possible implementation of same. Shown in Figure 2 is a circuit diagram of a flip-flop of the D type, according to the invention, which uses a master/slave configuration for data storage. It therefore comprises a first (master) flip-flop for storing the input data and a second (slave) flip-flop supplying the output signal. Both flip-flops include transmission gating inputs TGI1 and TGI2, respectively, and interface and selection circuits MUX1 and MUX2, respectively, each having a first input terminal connected to a respective transmission gating input. The two flip-flops further include respective logic gates ND1 and ND2, of the NAND type as shown in the Figure, each having an input terminal connected to the output terminal of the respective interface and selection circuit, the latter being in the form of a multiplexer consisting, for example, of a double buffer tristate with an inverting output and having an output terminal which forms an output terminal of the respective flip-flop. In accordance with the invention, each of the two logic gates has an input terminal CLEAR which allows the flip-flop comprising it to be driven to a predetermined state by a special active signal, which may be a simple pulse. In each of the flip-flops, a transmission gate TG1 and TG2, respectively, is negative feedback-connected between the output terminal of the flip-flop and the first input terminal of the interface and selection circuit. Connected to a second input terminal of each of the two interface and selection circuits MUX1 and MUX2, through a common inverter circuit INV1, is an asynchronous data input terminal AS_DATA. A second output terminal Q of the D-type flip-flop is provided, additionally to that formed directly by the output terminal NQ of the slave flip-flop, by connecting an inverter circuit INV2 to a circuit node thereof. In accordance with the invention, the transmission gating input TGI1 of the master flip-flop is of the inverting type, in order to regenerate the signal applied to the input terminal D of the D-type flip-flop. The transmission gating input TGI1 can be a buffer tristate with a high-impedance separating and uncoupling function. All the transmission gates and interface/selection circuits are driven by clock signals. In an implementation with CMOS technology of a D-type flip-flop according to the invention, e.g. as illustrated by the circuit diagram in Figure 3, the clock signal is split into two signals fi and Nfi; fi being in phase with the clock, and Nfi in phase opposition therewith. Likewise, the asynchronous load signal is split into ld and Nld (the loading becoming active on the high logic level). The operation of the flip-flop in the instance of a positive edge triggered clock signal will be considered. The negative edge triggering function is obtained by exchanging Nfi for fi. It is likewise possible to obtain the asynchronous data loading on a different logic level from that under consideration by exchanging Nld for ld. Let us consider now normal operation as a flip-flop of the D type, the assumption being that the load signal is always at a logic low. When fi is at a low logic level (so that Nfi will be at a logic high), the data present at D are accepted by the master flip-flop. For example, if D=1, upon fi becoming low DD=0 will appear at the input terminal of the slave flip-flop, but this level has no effect on the slave because with fi low, the transmission gate TGI2 is disabled, so that the previously stored value will still be output. Since DD is also the slave flip-flop input, upon fi becoming high, the data present at the transmission gate TGI2 will be transferred to the slave output, so that Q=1. To summarize, when fi is low, the data present at the input terminal D is read by the master but cannot be passed on to the slave. As the clock signal is restored to its logic high, thereby disabling the gating input, the data stored in the master is read by the slave flip-flop and will appear at the outputs Q and NQ. On the other hand, when a master/slave flip-flop must be allowed to have asynchronous direct inputs, these should be connected to both the master and the slave, so as to "bypass" the clock signal (fi, Nfi). The load signal enables storage, into both the master and slave flip-flops, of the data which appears asynchronously at the input AS_DATA. When the load signal is at its logic low, the flip-flop operates normally as a positive edge triggered D. As ld becomes high, the multiplexers formed by the gates TI1-TI2 and TI3-TI4 will carry to the nodes P and N the logic value present at the input AS_DATA. The asynchronous input is left unheeded upon the signal ld being restored to its logic low; in this case, the asynchronous data is still held at the output by one of the two feedback loops of the master and the slave, according to the value of fi. The master and slave inputs become active once again, so that the new data will be sampled at the first useful edge of the clock signal. Furthermore, the circuit arrangement including the two logic gates ND1 and ND2 allows the low logic level to be forced asynchronously out by the application of a special low active signal to the terminals CLEAR of the gates. Inverters may be placed on the outputs Q and NQ of the flip-flop in order to output regenerated signals having high driving capabilities. This also allows the value of the data stored into the feedback loop of the slave to be saved, since the output is electrically isolated against noise from downstream circuitry of the flip-flop. It should be understood that modifications or substitutions may be made unto the embodiment described, in ways well known to the skilled ones in the art. For example, the NAND logic gates could be replaced with other logic circuits to suit specific implementations of the other feedback loops of the bistable circuits.

Claims: A logic network of the sequential type, having at least first (D) and second (AS_DATA) signal input terminals and an output terminal (NQ) and comprising an input bistable circuit (MASTER) and an output bistable circuit (SLAVE), connected in series with each other between the first input and the output terminal of the network, the input bistable circuit including an interface and selection circuit (MUX1) which has a first input terminal connected to the first input terminal of the network (D) through an input gate (TGI1) for the transmission of signals, and a second input terminal coupled to the second input terminal (AS_DATA) of the network, the output bistable circuit including a second interface and selection circuit (MUX2) which has a first input terminal coupled to an output node (DD) of the input bistable circuit through a second gate (TGI2) for the transmission of input signals, and a second input terminal coupled to the second input terminal (AS_DATA) of the network, characterized in that the input bistable circuit (MASTER) comprises a first logic gate circuit (ND1) having a first input terminal connected to an output terminal of the first interface and selection circuit (MUX1), a second input terminal (CLEAR) for control signals and an output terminal connected to an output node (DD) of said input bistable circuit, and comprises a first feedback transmission gate (TG1) connected between the output terminal of said first logic gate circuit (ND1) and the first input terminal of the first interface and selection circuit (MUX1), and in that the output bistable circuit (SLAVE) comprises a second logic gate circuit (ND2) having a first input terminal connected to an output terminal of the second interface and selection circuit (MUX2), a second input terminal (CLEAR) for control signals and a network output terminal (NQ), and comprises a second feedback transmission gate (TG2) connected between the output terminal of said second logic gate circuit (ND2) and the first input terminal of the second interface and selection circuit (MUX2). A logic network according to Claim 1, characterized in that the first input gate (TG1) for the transmission of signals is a circuit having a high-impedance separating function. A logic network according to either Claim 1 or 2, characterized in that the first and second logic gate circuits (ND1,ND2) are of the NAND type. A logic network according to any of Claims 1, 2 and 3, characterized in that the first and second input gates (TGI1,TGI2) for the transmission of signals, and the first and second feedback transmission gates, are controlled by clock signals as synchronized in a predetermined manner. A logic network according to any of Claims 1, 2, 3 and 4, characterized in that the first and second interface and selection circuits (MUX1,MUX2) are effective to transfer, in an asynchronous manner, signals applied to the second input terminal of the network. A logic network according to any of Claims 1, 2, 3, 4, and 5, characterized in that the first and second logic gate circuits (ND1,ND2) are adapted to receive control signals in an asynchronous manner. A logic network according to Claim 6, characterized in that it is integrated monolithically with CMOS technology. Counter devices, characterized in that they comprise at least one logic network as claimed in any of CLaims 1, 2, 3, 4, 5, 6 and 7. A parallel-to-serial converter device, characterized in that it comprises at least one logic network as claimed in any of Claims 1, 2, 3, 4, 5, 6 and 7.

Inventors: FUCILI GIONA, GOLA ALBERTO, PAPILLO LORENZO, PASQUINO ANDREA, ROSSI ANNAMARIA, FUCILI, GIONA, GOLA, ALBERTO, PAPILLO, LORENZO, PASQUINO, ANDREA, ROSSI, ANNAMARIA
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: H03K3
IPC codes: H03K3