Receive signal level detection system

Abstract: A superheterodyne receiver (100) is provided in which first (107) and second envelope detectors (111) having a function of regulating the gain and offset voltage are used to detect receive signal levels from first (IF1) and second intermediate frequency signals (IF2). These receive signal levels are compensated with respect to a phase difference through a phase difference compensating circuit (113). The compensated signals are then summed by an adder (114) to provide a receive signal level detection output.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to improvements of a receive signal level detection system applicable to a superheterodyne receiver. Description of the Related Art Fig. 8 shows a receive signal detection system according to the prior art. In Fig. 8, a radio frequency signal received by an antenn 101 is converted into an intermediate frequency signal in a receiver 502. The intermediate frequency signal is then detected by an envelope detector 503. The envelope detector 503 can ascertain the amplitude of the converted intermediate frequency signal received thereby, resulting in detection of the receive signal level. The receive signal detection system of the related art has such a receive signal input level to level detection output characteristic as shown in Fig. 9. In this figure, the abscissa axis shows receive signal input levels while the ordinate axis represents receive signal level detection outputs. As shown, the output level increases proportional to increase of the input level when the receive signal input level is equal to or lower than a predetermined value. Therefore, such a linear region can be used to detect a receive signal level corresponding to each of the receive signal input levels. Thus, the state of the radio channel can be judged. In the receive signal detection system of the related art, however, the input/output characteristic of the envelope detector 503, that is, the receive signal input level at which the linearity of the receive signal input level to receive signal level detection output characteristic can be maintained is restricted. As shown in Fig. 9, the output level will be saturated if the receive signal input level exceeds the predetermined value, instead of increasing in proportion to increase of the input level. As the receive signal input level increases, the nonlinearity region (saturated region) of the input/output characteristic in the envelope detector 503 may be used to detect the receive signal level. As a result, the detection of receive signal level can not be properly carried out, resulting in increase of errors. EP-A-0 639 901 (published on 22.02.1995), which is a document falling under Article 54(3) EPC, discloses techniques which enable the dynamic range for detecting the field strength of a received signal to expand such that a variety of controls can be highly accurately performed. A part from a first signal path for amplifying a received signal and transmitting the amplified signal to a demodulator, a second signal path is provided such that a detection signal extracted from the first and second signal paths is used to detect the field strength of the received signal. The first signal path is composed of circuits which give priority to the communication quality, while the second signal path is composed of circuits which give priority to the width of the dynamic range. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a receive signal detection system which can properly detect a receive signal input level even in the saturated region of the related art, resulting in enlargement of a region to be detected. To this end, the present invention provides a receive signal detection system suitable for use in a superheterodyne receiver, comprising the features of claim 1. In one aspect of the present invention, the combining means comprises means for compensating a phase difference between the first and second receive signal levels at a point in time, and means for summing the first and second receive signal levels compensated with respect to the phase difference. In another aspect of the present invention, each of said first and second detection means include a function of regulating the detection output so that a receive signal input level to level detection output characteristic obtained by combining the outputs of the first and second detection means has a smooth linearity. In still another aspect of the present invention, said means for compensating the phase difference includes a delay line. In a further aspect of the present invention, the combining means is in the form of a CPU for performing the phase difference compensation and addition. In such an arrangement, if the receive signal input level is so high that the input/output characteristic of the second envelope detection means will be saturated, the detection of the receive signal level can be made over an increased range to be detected through the linear input/output characteristic of the first envelope detection means. Since the combining means has means for compensating the phase difference, the addition can be carried out without a phase difference between the first and second receive signal levels. Since each of the first and second detection means include the function of regulating the detection outputs, the receive signal input level to detection output characteristic obtained by combining the outputs of the first and second detection means can have a smooth linearity. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of one embodiment of an receive signal detection system constructed in accordance with the present invention. Fig. 2 is a graph illustrating a receive signal input level to detection output characteristic in the first intermediate frequency signal of the receive signal detection system according to the present invention. Fig. 3 is a graph illustrating a receive signal input level to detection output characteristic in the second intermediate frequency signal of the receive signal detection system according to the present invention. Fig. 4 is a graph illustrating a receive signal input level to detection output characteristic obtained by combining the graphs of Figs. 2 and 3. Fig. 5 is a block diagram of the second embodiment of a receive signal detection system constructed in accordance with the present invention. Fig. 6 is a block diagram of the third embodiment of a receive signal detection system constructed in accordance with the present invention. Fig. 7 is a flow chart illustrating an operation in the detection level combining circuit of the third embodiment. Fig. 8 is a block diagram of a receive signal detection system constructed in accordance with the related art. Fig. 9 illustrates a receive signal input level to detection output characteristic in the receive signal detection system of the related art. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some preferred embodiments of the present invention will be described with reference to the drawings. First Embodiment Fig. 1 shows the first embodiment of a receive signal detection system constructed according to the present invention. A double superheterodyne receiver 100 shown in Fig. 1 comprises an antenna 101, a high frequency amplifier 102 for amplifying a signal received by the antenna 101 and a band-pass filter 103 for limiting the band. The receiver 100 also comprises a mixer 104 and another band-pass filter 105 which generate a first intermediate frequency signal (IF1) that is in turn amplified by an intermediate frequency amplifier 106. The output of the intermediate frequency amplifier 106 is inputted into the first envelope detector 107 and the mixer 108. The output of the mixer 108 is then inputted into a band-pass filter 109 which in turn outputs a second intermediate frequency signal (IF2). The second intermediate frequency signal is amplified by a limiter amplifier 110 and then inputted into a second envelope detector 111 and a demodulating unit 115. The gain of the intermediate frequency amplifier 106 is set to be relatively low. Thus, the output of the intermediate frequency amplifier 106 is very weak and does not clearly exhibit linearity with a low receive signal input level. However, the output thereof will exhibit remarkable linearity as the receive signal input level increases. When the output of the intermediate frequency amplifier 106 is detected by a first envelope detector 107 and if the receive signal input level is relatively high, the receive signal input level to detection output characteristic will have linearity. A receive signal input level to level detection output characteristic or input/output characteristic in the first intermediate frequency signal of the first envelope detector 107 is shown in Fig. 2. As shown in Fig. 2, the input/output characteristic will have linearity when the receive signal input level exceeds a predetermined value E 2 +Δ. The first envelope detector 107 has a function of regulating the gain and offset voltage, that is, the gradient of the straight line and the movement thereof in the direction of the ordinate axis which shows the input/output characteristic of Fig. 2. Thus, the first envelope detector 107 forms the first detection means of the present invention. On the other hand, the gain of the limiter amplifier 110 is set to be higher than that of the intermediate frequency amplifier 106. The output level of the limiter amplifier 110 may be saturated by the higher receive signal input level. Thus, the output of the second envelope detector 111 for detecting the output signal of the limiter amplifier 110 may also be saturated by the higher receive signal input level. An input/output characteristic in the second intermediate frequency signal of the second envelope detector 111 is shown in Fig. 3. As shown, the input/output characteristic has linearity until the receive signal input level reaches the predetermined value E 2 . However, the linearity will be degraded when the receive signal input level exceeds the value E 2 . The output level of the second envelope detector 111 will be saturated when the receive signal input level exceeds E 2 +Δ. The second envelope detector 111 also has a function of regulating the gain and offset voltage and forms the second detection means of the present invention. As shown in Figs. 2 and 3, the receive signal level detection output corresponding to the first intermediate frequency signal has linearity if the receive signal input level is higher than E 2 +Δ. The receive signal level detection output corresponding to the second intermediate frequency signal also has linearity when the receive signal input level is lower than E 2 . Therefore, this embodiment uses a detection level combining circuit 112 to combine these detection levels such that the receive signal level detection characteristic will have linearity over a widened receive signal level range. The detection level combining circuit 112 forms the combining means of the present invention. There is a phase difference between the outputs of the first and second envelope detectors 107, 111. The detection level combining circuit 112 comprises a phase difference compensating circuit 113 which compensates such a phase difference before the detection outputs are summed by an adder 114. Thus, the detection outputs can be summed without any phase difference therebetween. When the detection outputs are summed by the adder 114, the gain and offset voltage regulating function in the first and second envelope detector 107, 111 can regulate the gain and offset voltage. Therefore, the gradient of the straight lines showing the receive signal level detection characteristic (those of Figs. 2 and 3) as well as the positions thereof in the direction of the ordinate axis can be regulated. Thus, the combined receive signal level detection characteristic can be a smooth straight line. Fig. 4 shows a receive signal input level to detection output characteristic thus obtained. As will be apparent from Fig. 4, the receive signal level detection output characteristic has linearity over an increased receive signal input level range. As described, this embodiment can properly detect the receive signal level by combining the detection output levels of the first and second envelope detectors even if the receive signal input level is so high that the receive signal level detection will be saturated as in the related art. Therefore, a receive signal detection system can be provided which can detect the receive signal level over an increased range. Second Embodiment Referring to Fig. 5, there is shown the second embodiment of the present invention which uses a delay line 300 in place of the phase difference compensating circuit 113 in the detection level combining circuit 112 described with respect to the first embodiment. The detection level combining circuit 112 comprises terminals 301 and 302 which are respectively connected to the first and second envelope detectors 107, 111 as described with respect to the first embodiment. As described in the first embodiment, there is a phase difference between the detection outputs from the terminals 301 and 302. In the second embodiment, thus, the delay line 300 delays the phase of the detection output from the first envelope detector 107 by a given period to match the phases of the detection outputs from the first and second envelope detectors with each other. In such a manner, the phase difference between the detection outputs can be compensated before they are summed by the adder 114. Third Embodiment Referring next to Fig. 6, there is shown the third embodiment of the present invention which comprises a central processing unit (CPU) 400 for performing the functions of the phase difference compensating circuit 113 and adder 114 in the detection level combining circuit 112. The detection level combining circuit 112 comprises terminals 401 and 402 which are respectively connected to the first and second envelope detectors 107, 111, as in the second embodiment. CPU 400 converts the detection outputs into binary numbers which are in turn subjected to the phase difference compensation and addition. Such an operation is shown in the flow chart of Fig. 7. In Fig. 7, detection levels x(n) and y(n), which are the detection outputs of the first and second envelope detectors 107, 111, are inputted into the detection level combining circuit 112 through the terminals 401 and 402. The alphabet n represents the period of the detection level (S1). The detection levels x(n) and y(n) are then sampled and converted into binary numbers X(n) and Y(n) by an A/D converter (not shown), these binary numbers being then stored in a memory (S2). Subsequently, a sampled value X(n-m) before m periods corresponding to the difference of phase between the detection levels x(n) and y(n) is fetched from the memory with respect to X(n) corresponding to the output of the first envelope detector 107. X(n-m) and Y(n) are binary numbers corresponding to the detection levels of the same phase (S3). Finally, these binary numbers X(n-m) and Y(n) are summed to provide a binary number Z(n) corresponding to the receive signal level detection output. Namely, Z(n)=X(n-m)+Y(n). Such a binary number Z(n) is used to judge the receive signal level (S4). According to the third embodiment, the phase difference compensation and addition of the detection outputs can be carried out using software through the CPU 400. This can simplify the circuit structure.

Claims: A receive signal detection system suitable for use in a superheterodyne receiver (100), comprising: first detection (107) means adapted to detect a first receive signal level through a high or intermediate frequency amplifier (106) amplifying a radio or a first intermediate frequency signal (IF1); second detection means (111) adapted to detect a second receive signal level through a limiter amplifier (110) amplifying a second intermediate frequency signal (IF2) converted from said radio or said first intermediate frequency signal (IF1); and means (112) adapted to combine the first and second receive signal levels to generate a receive signal level detecting output having a linear detecting characteristic in either of an input level in which the detection characteristic of the first receive signal level has linearity or another input level in which the detection characteristic of the second receive signal level has linearity. A receive signal detection system as defined in daim 1, wherein the first detection (107) means also outputs a signal level having a linear receive signal input level to level detection output characteristic when the receive signal input level exceeds a predetermined value; and the second detection means (111) also outputs a signal level having a linear receive signal input level to level detection output characteristic when the receive signal input level is equal to or lower than the predetermined value. A receive signal detection system as defined in any one of claims 1 to 2, wherein said combining means (112) comprises means (113, 300, 400) for compensating a phase difference between the first and second receive signal levels at a point in time, and a detection level combining circuit which comprises means (114, 400) for summing the first and second receive signal levels compensated with respect to the phase difference. A receive signal detection system as defined in any one of claims 1 to 3, wherein each of said first (107) and second detection means (111) include a function of regulating the detection output so that a receive signal input level to level detection output characteristic obtained by combining the outputs of the first and second detection means has a smooth linearity. A receive signal detection system as defined in any one of claims 1 to 4, wherein said means for compensating the phase difference includes a delay line (300). A receive signal detection system as defined in any one of claims 1 to 5, wherein the combining means (112) is in the form of CPU (400) for performing the phase difference compensation and addition.

Inventors: KASHIWAGI TAKASHI, TOMOE NAOHITO, KASHIWAGI, TAKASHI, TOMOE, NAOHITO, KASHIWAGI, TAKASHI, C/O MITSUBISHI DENKI K. K., TOMOE, NAOHITO, C/O MITSUBISHI DENKI K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1995
Main classification: H04B17
IPC codes: H04B1, G01R29, H04B17