A system and method for implementing fast high addressability error diffusion process

Abstract: A method and system implements a high addressability characteristic into an error diffusion process. A grey level value representing a pixel is received. The grey level value is interpolated to generate subpixel grey level values which correspond to a second resolution. A threshold circuit thresholds the interpolated grey level value. In parallel to the interpolation circuit and threshold circuit is an error circuit which generates a plurality of possible error values. One of the plurality of possible error values is selected based on the number of subpixels exceeding a threshold value. A portion of the selected error value is then diffused to adjacent pixels on a next scanline.

Description: The present invention is directed to the architecture of an error diffusion process. More specifically, the present invention is related to the architecture of a high addressability error diffusion process which allows the reduction of a multi-level grey signal to be carried out in the time constraints of an image rendering system. Error diffusion is a well known method of processing grey scale images on a binary output device. One of the key ingredients in error diffusion is a requirement to propagate or diffuse the error which is generated by reducing (binarizing) the grey level value of a grey scale image. Recently, improved features have been added to the typical error diffusion method. Specifically, it has been proposed to utilize high addressability error diffusion. A brief description of high addressability error diffusion will follow. In explaining the high addressability error diffusion process, it is assumed that the input grey level at pixel location i and pixel location i+1 is represented by V i and V i+1 , respectively. The pixel values are assumed to be 8 bit integers wherein, for the sake of explanation, 0 denotes white and 255 denotes black. The rendering error, at a resolution lower than the addressability resolution, that passes from upstream pixels to the downstream pixel location is denoted by e i . It is noted that a feature of high addressability involves interpolation between pixels, the creation of subpixels. This interpolation impacts the high addressability error diffusion process. More specifically, depending on the way the interpolation is done, distinct outputs can be obtained utilizing a high addressability error diffusion process. One such method of interpolation is as follows. Figures 1-7 illustrate the computational steps required to perform high addressability error diffusion using a particular interpolation scheme. Initially, as illustrated in Figure 1, the pixel value V i and V i+1 are obtained. The actual pixel values are graphically illustrated in Figure 1, wherein the pixel value V i represents the pixel value at the subpixel position 0 and the pixel value V i+1 represents the pixel value at the N subpixel. In Figure 1, the pixel values range from 0 to 255 utilizing a conventional eight bit dataword to represent the multi-level grey value of the image data to be process. It is noted that any range can be utilized to represent the grey level value of the image data; for example, 0 to 511, to 127, etc. After obtaining the initial pixel values of V i and V i+1 , a diffused error component e i (the accumulated error from previous pixel binarization processes) is added to the pixel values V i and V i+1 . It is noted that the error component e i consists of two components, e FIFO and e FB , where e FIFO is the summed error component stored in a line buffer and e FB is the feedback error component. The adding of the error component e i is illustrated graphically in Figure 2. After adding the diffused error component, the interpolated subpixel values are computed, as illustrated in Figure 3. For example, the interpolated subpixel values are B n = P0 i + n (P1 i -P0 i )/N for n = 0 to N-1, where N is the selected high addressability characteristic. It is noted that the value P0 i is equal to V i + e i and P1 i is equal to V i+1 + e i . After computing the interpolated subpixel values, each interpolated subpixel value is compared to a threshold level. In the example illustrated in Figure 4, the threshold value is 128. It is noted that this threshold value can be any value within the range of the image data depending upon the desired results. In this example, each subpixel which has a value greater than or equal to 128 is set ON. Next, the desired output (P0 i +P1 i )/2 is computed. This computing of the desired output is graphically illustrated in Figure 5. After computing the desired output, the actual output is computed. In this example, the actual output is equal to n*255/N where n is the number of subpixels that have been turned ON as the result of the comparison illustrated in Figure 4. A graphical representation of the computed actual output is shown in Figure 6. Once the desired output and the actual output have been computed, the error diffusion method computes the error to be propagated downstream. This error is computed as the desired output minus the actual output. A graphical representation of this computation is shown in Figure 7. As illustrated in Figure 7, the error is calculated to be e i+1 = (P0 i + P1 i )/2 - (n*255/N). In this instance, the error e i+1 represents the error from the present binarization process. As in all conventional error diffusion processes, the error from the binarization process is distributed to downstream pixels. The distributing of the error e i+1 to downstream pixels is illustrated in Figure 8. In this example, the distribution of error utilizes a set of error diffusion coefficients which allow fast processing by simple bit shifting. Figure 8 illustrates the coefficients associated with each pixel location. An example of the exact coefficients are discussed in U.S. Patent Application, Serial No. 08/167,758, published as US-A-5,353,127. To more readily understand the high addressability error diffusion method, a more detailed description is disclosed in EP-A-696132, corresponding to U.S. application, Serial No. 08/285,326, filed concurrently herewith. Although the above enhancement significantly improves the print quality of the images rendered via error diffusion, this improvement tends to make the computations more complex in terms of hardware design and time consuming. One of the most important drawbacks of this high addressability error diffusion improvement has been the time needed to make the complex computations. Although the computations can be implemented in a software environment, the time needed to produce binarized image data for rendering is too long to readily implement such a solution in mid-speed to high-speed printing or image rendering devices. More specifically, the exact correspondence between the high, addressability error diffusion computations in software to that which is implemented in hardware is different due to the speed requirements imposed by a system's throughput specification. Therefore, it is desirable to design an unique hardware implementation of the high addressability error diffusion method to meet the time constraints of the present day image rendering devices. A first aspect of the present invention provides a method of generating an error from a threshold process, comprising the steps of: (a) thresholding a plurality of interpolated subpixel values associated with a grey level value of an associated pixel; (b) generating a plurality of possible error values in parallel with the thresholding carried out by said step (a); and (c) selecting one of the plurality of possible error values based on the number of interpolated subpixel values exceeding a threshold value determined in said step (a). The method preferably further comprises the step of screening the grey level value with a predetermined screen prior to the execution of said step (b). A second aspect of the present invention provides a system for generating an error from a threshold process, comprising: threshold means for thesholding a plurality of subpixel values associated with a grey level value of an associated pixel and for determining a number of subpixel values which exceed a threshold value; error means, operatively connected in parallel with said threshold means, for generating a plurality of possible error values; and selecting means, operatively connected to said error means and said threshold means, for selecting one of the plurality of possible error values based on the number of subpixel values exceeding a threshold value determined by said threshold means. The system preferably further comprises: screening means for screening the grey level value with a predetermined screen prior to conversion by said conversion means. A third aspect of the invention provides a printing system for rendering marks on a receiving medium, comprising: receiving means for receiving a grey level signal corresponding to a pixel having a first resolution; interpolation means for converting the grey level signal to a second resolution, the second resolution being higher than the first resolution; binarization means for binarizing the converted grey level signal so as to output a binary signal and for determining a number of subpixels which exceed a threshold value; error means, operatively connected in parallel with said interpolation means and said binarization means, for generating a plurality of possible error values; and selecting means, operatively connected to said error means and said binarization means, for selecting one of the plurality of possible error values based on the number of subpixels exceeding a threshold value determined by said binarization means; diffusing means for diffusing the selected error value to grey level signals corresponding to pixels adjacent to the pixel being binarized; and rendering means for converting the binary signal into a mark on the receiving medium. Further objects and advantages of the present invention will become apparent from the following descriptions of the various embodiments in conjunction with the drawings, wherein: Figure 1 shows a graphical representation of obtaining boundary subpixel values; Figure 2 shows a graphical representation of modifying the obtained boundary subpixel values with an error component; Figure 3 shows a graphical representation of interpolating subpixel values between the modified boundary subpixel values; Figure 4 shows a graphical representation of comparing the interpolated subpixel values with a threshold value; Figure 5 shows a graphical representation of computing a desired output value; Figure 6 shows a graphical representation of computing an actual output value; Figure 7 shows a graphical representation of computing an error value to be propagated to downstream pixels; Figure 8 shows a graphical representation illustrating actual distribution of the error in a typical error distribution routine; Figure 9 shows a block diagram illustrating an embodiment implementing a high addressability error diffusion process; Figure 10 shows a graphical representation illustrating a decoding process illustrated in Figure 9; Figure 11 shows a graphical representation of the preferred embodiment of the present invention illustrating the obtaining boundary subpixel values in parallel with the computing a desired output value; Figure 12 shows a graphical representation of the preferred embodiment of the present invention illustrating of interpolating subpixel values between the obtained boundary subpixel values in parallel with the modifying of the desired output value with an error component; Figure 13 shows a graphical representation of the preferred embodiment of the present invention illustrating of modifying the subpixel values between the obtained boundary subpixel values with an error component; Figure 14 shows a graphical representation of the preferred embodiment of the present invention illustrating the calculation of a plurality of partial possible error values; Figure 15 shows a graphical representation of further modifying the modified subpixel values of Figure 13 with another error component; Figure 16 shows a graphical representation of the preferred embodiment of the present invention illustrating the calculation of a plurality of complete possible error values; Figure 17 shows a graphical representation of thresholding the further modified subpixel values; Figure 18 shows a graphical representation of determining of number of subpixels exceeding or equal to a threshold value; Figure 19 shows a graphical representation of selecting one of the plurality of possible complete error values; Figure 20 is a block diagram illustrating implementation of the processes illustrated in Figures 11-19; and Figure 21 is a block diagram illustrating circuitry implementation of the processes illustrated in Figures 11-19. As discussed above, the hardware implementation of the high addressability error diffusion must meet the time restraints of the throughput specifications of the image rendering device utilizing the high addressability error diffusion method. More specifically, to be implemented in present day image rendering devices, the error computation must be completed in one clock cycle, since half of the error is diffused to the next pixel in the fast scan direction. The error which is diffused downward in the slow scan direction is summed and stored in a buffer. This portion of the error is part of the distributed error component required for binarizing pixels on the next scanline. This summing, however, can be performed several cycles later, since this error component is not needed until the following scanline. If there were no constraints set on the time allowed to process the subpixel and the corresponding error or if present day microprocessors were fast enough to meet the time constraints of present day imaging devices, the hardware required to achieve high addressability error diffusion would be fairly straight forward. In this situation, the number of subpixels to be set ON could be determined by simply calculating the intersection of the line containing the points P0 i and P1 i and 128. The error to be distributed downstream would then be calculated based upon the number of subpixels which are turned ON. A block diagram of this hardware implementation is illustrated in Figure 9. In Figure 9, the input video signal is split and latched in latch 101 so as to produce the pixel value V0 i and V1 i . V0 i represents the latched input video signal V1 i , in other words, V0 i represents the pixel value just proceeding the pixel value V1 i in the same same scanline. The pixel value V0 i is fed into an adder 103 with the error component e i . Moreover, the error component e i is fed into an adder 105 along with the input video signal V1 i . The adder 103 produces an output signal P0 i which is fed into a 2-complements circuit 107 to produce negative P0 i . Negative P0 i is fed into an adder 109 along with the value P1 i to produce the value of P1 i -P0 i . Negative P0 i is also fed into adder 111 which is summed with the threshold value. In this example, the threshold value is 128. The sum from adder 111 is fed into multiplier 115 so that the value (128 - P0 i ) can be multiplied by the high addressability characteristic value N. The resulting product is then divided by the sum from adder 109 by a divider circuit 117. The resulting quotient is represented by n and fed into a decoder 119. The actual function of decoder 119 is graphically illustrated in Figure 10. More specifically, the decoder 119, as illustrated in Figure 10, determines the intersection of the P0 i /P1 i line and the value 128. From the determination of this intersection, the decoder 119 determines the number of subpixels n which are turned ON. The results from decoder 119 are fed as binarized output to a print engine and also to a multiplier 121. Multiplier 121 multiplies the output from decoder 119 with the value (-255/N). The product of multiplier 121 is added to a sum generated by an adder 113 in adder 123. Adder 113 adds the values P0 i and P1 i to produce the value P1 i + P0 i . The results of adder 123 represents the error component e i+1 which is fed into a simple bit shifting circuit 125 to produce various error values that will be utilized in the distribution process. The error values generated by the bit shifting circuit 125 are fed into an error distribution circuit 127, wherein half the error Err B is distributed to the next pixel in the same scanline and the other half of the error Err A is distributed to various pixels in the next scanline according to the weighting coefficients established in the error distribution circuit 127. Again, this hardware implementation of the high addressability error diffusion assumes that there are no time constraints, that there are no system's throughput specification requiring clock cycles exceeding 50 megahertz, or that the system has a microprocessor capable of operating at an instruction per second rate greater than 100 Mips (million instructions per second). However, as noted above, typical image rendering devices have clock cycles which exceed 50 megahertz and require all image processing of a single pixel to be completed within approximately 20 nanoseconds of time to operate in realtime; i.e., within the throughput specifications of mid-volume to high volume printing systems. To meet the time constraints imposed by present day rendering devices, the present invention decomposes the computation of the high addressability error diffusion method into two categories. The first category includes all computations which can be performed on the interpolated video signal including all possible subpixel error calculations outside or prior to entering a feedback path, and the second category is calculations which include the remaining computations that must be performed within one clock cycle (i.e., inside the feedback path). To realize this decomposition, the diffused error value is broken into two components, one component being the sum error which is stored and readily available in the FIFO buffer, namely e FIFO , and the other is the fast scan feedback error component, e FB , passed from binarizing of the neighbor pixel immediately preceding the pixel being processed in the fast scan direction. With respect to these two categories, Figures 11-14 represent the computations which can be performed prior to entering the feedback loop, while Figures 15-19 are the computations which are performed within one clock cycle or within the feedback loop. Moreover, it is noted that some of these computations are performed in parallel. The parallel computations will be discussed with respect to Figures 11-19. Figure 11 illustrates two such parallel computations which are carried out in the present invention. More specifically, Figure 11 illustrates that the pixel values V i and V i+1 are obtained in parallel to the beginning of the computation of the desired output for a single subpixel wherein the desired output is computed without including the diffused error components e FIFO or e FB . After these parallel computations are completed, the preferred embodiment of the present invention computes the interpolated subpixel values in the same way as illustrated in Figure 3. However, in parallel with this computation of the interpolated subpixel values, the desired output is continued to be computed by adding the error component e FIFO . This, is graphically represented in Figure 12. Next, the error component e FIFO is added to the pixel values V i , and V i+1 and the interpolated subpixels as illustrated in Figure 13. At the same time (in parallel thereto), all possible actual subpixel outputs are subtracted from the desired output without including the diffused error component e FB . In other words, N possible actual subpixel outputs are subtracted from the desired output computed in Figure 12 to produce N possible error outputs e p (the desired output minus the actual output is equal to the error e p ). The computations illustrated in Figure 13 are carried out in parallel with the computations illustrated in Figure 14. It is further noted that the computations illustrated in Figures 11-14 are implemented outside the feedback loop. Within the feedback loop, the computations are illustrated by Figures 15-19. Initially, within the feedback path, the error component e FB is added to the pixel values V i , V i+1 , and the various interpolated subpixel values as illustrated in Figure 15. At the same time that the feedback error component e FB is being added in Figure 15, the error component e FB is added to all possible subpixel desired outputs as illustrated in Figure 16. In other words, the error component e FB is individually added to all N error results (e p ) stemming from the calculations illustrated by Figure 14. After completing these parallel computations, the next step includes the computations illustrated in Figures 17, 18, and 19. In this next step, each interpolated subpixel value is compared to a threshold value of 128, and the subpixels having a value greater than or equal to the threshold value are turned ON. This process is graphically illustrated in Figure 17 and 18 wherein Figure 17 shows the comparison of the interpolated subpixel values with the threshold values, and Figure 18 shows the turning ON of the subpixels which have a value greater than or equal to the threshold value. Since all the possible error values were made simultaneously available as a result of the computations illustrated in Figure 16, the error to be propagated downstream can now be immediately selected; i.e., via a multiplexer, based upon the number of subpixels which are turned ON. In other words, Figure 19 illustrates the properly selected error value from the various simultaneously available error values produced by the computations illustrated in Figure 16. The selected error value is then distributed to downstream pixels utilizing any conventional error diffusion technique. In the preferred embodiment of the present invention, the error is distributed to downstream pixels utilizing the error diffusion coefficients discussed above. Figure 20 illustrates a functional block diagram of the parallel pipeline high addressability error diffusion circuit of the preferred embodiment of the present invention. In Figure 20, the input video signal is fed into an error calculation circuit 1 and a video modification circuit 3. The error components e FIFO (Err B ) and e FB (Err A ) are also fed into the error calculation circuit 1. The error calculation circuit calculates all the various possible error values that can result from the presently occurring binarization process. The selection of the proper error to be output by the error calculation circuit 1 is based upon the received error selection signal which will be discussed in more detail below. The selected error value from the error calculation circuit 1 is fed into a coefficient matrix circuit 5 which distributes the error based upon a set of weighting coefficients. The coefficient matrix circuit 5 splits the error values into the two components e FIFO (Err B ) and e FB (Err A ). As noted before, the feedback error, Err A , is fed back to the video modification circuit 3 and the error calculation circuit 1 from the coefficient matrix circuit 5. The video modification circuit 3 also receives the Err B from buffer 9. The video modification circuit 3 produces the interpolated subpixel values for the high addressability error diffusion method wherein the interpolated subpixel values are fed into the binarization circuit 7 along with a threshold value. In the preferred embodiment of the present invention, the threshold value is 128. However, it is noted that this threshold value can be any value. The binarization circuit 7 binarizes the inputted video data so as to output binarized image data for the utilization by an image rendering device. The binarization circuit 7 also produces the error selection signal which is utilized by the error calculation circuit 1 to choose the correct error value to be fed to the coefficient matrix circuit 5. This error selection signal represents the number of interpolated subpixels which are turned ON during the binarization process. Thus, the error calculation circuit 1 may include a multiplexer to make this selection. As illustrated in Figure 20, the error calculation circuit 1 is in parallel with the video modification circuit and the binarization circuit. Moreover, the high addressability error diffusion architecture of the present invention is implemented on an ASIC, thereby enabling hardware implementation so that the image data can be binarized within the time constraints and throughput specifications of a high speed image rendering device. Figure 21 illustrates a detail block diagram of the circuit of the preferred embodiment of the present invention. As illustrated in Figure 21, many of the computations, as previously described with respect to Figures 11-19, are carried out in parallel. Pixel values V i and V i+1 are obtained by the utilization of a latch 205 which latches the video signal so that two adjacent fast scan pixels are available for processing. The pixel values V i and V i+1 are summed in adder 206 and the sum is divided in half by divider 207. The result from divider 207 is fed into adder 208 with the error term e FIFO . The sum represents the desired output to the printer. In parallel to the above described process, an actual output generation circuit 200 produces all possible outputs to the printer based on the high addressability characteristic. It is noted that these values are negative since an adder is used for substraction operations. If the high addressability characteristic is N, N possible actual outputs will be generated. Also in parallel to the above described process, a subpixel circuit generated all the interpolated subpixels based on the pixel values V i and V i+1 . Next, the error component e FIFO is added to each of the interpolated subpixels by adder 210. At the same time (in parallel thereto), each possible actual outputs (negative values) is individually added to the desired output by adder 201. In other words, N possible actual subpixel outputs are subtracted from the desired output to produce N possible error outputs. In adders 211 and 202, a feedback error term e FB is added to each summation from adders 210 and 201, respectively. These computations are carried out in parallel. After completing these parallel computations, each interpolated subpixel from adder 211 is compared to a threshold value in threshold circuit 212. The subpixels having a value greater than or equal to the threshold value are turned ON. Threshold circuit outputs a number representing the number of sub pixels turned ON. This information is fed into a decode logic circuit which produces a binary therefrom to be sent to a printer. Moreover, the error terms from adder 202 are fed into a multiplexer 203 which chooses which error term to propagate to down stream pixels. The error term is selected based on a control signal received from the decode logic circuit 213. The selected error term is fed into a distribution circuit 204 which produces the next feedback error and the error to be stored in a buffer for utilization in the processing of the next scanline. The present invention is also applicable to an image processing system which combines screening with high addressability error diffusion. A full description of the screening and high addressability error diffusion process is disclosed in EP-A-696131, corresponding to U.S. Patent Application, Serial Number 08/285,328, filed concurrently herewith. In describing the present invention, the terms pixel and subpixel have been utilized. These terms may refer to an electrical (or optical, if fiber optics are used) signal which represent the physically measureable optical properties at a physically definable area on a receiving medium. The receiving medium can be any tangible document, photoreceptor, or marking material transfer medium. Moreover, the terms pixel and subpixel may refer to an electrical (or optical, if fiber optics are used) signal which represent the physically measureable optical properties at a physically definable area on a display medium. A plurality of the physically definable areas for both situations represent the physically measureable optical properties of the entire physical image to be rendered by either a material marking device, electrical or magnetic marking device, or optical display device. Lastly, the term pixel may refer to an electrical (or optical, if fiber optics are used) signal which represents physical optical property data generated from a single photosensor cell when scanning a physical image so as to convert the physical optical properties of the physical image to an electronic or electrical representation. In other words, in this situation, a pixel is an electrical (or optical) representation of the physical optical properties of a physical image measured at a physically definable area on an optical sensor. The preferred embodiment of the present invention has been described with respect to a printing system; however, this error diffusion architecture is readily implemented in a display system. Moreover, by implementing the high addressability error diffusion architecture of the present invention on an ASIC, thereby enabling the placement of the high addressability error diffusion process can be located in a scanner, stand alone electronic subsystem, printer, or display device. Moreover, the present invention has been described with respect to a video range of 0 to 255. However, it is contemplated by the present invention that the video range can be any suitable range to describe the grey level of the pixel being processed. Furthermore, the present invention is readily applicable to any rendering system, not necessarily a binary output device. It is contemplated that the concepts of the present invention are readily applicable to a four level output terminal or higher. Lastly, the present invention has been described with respect to a monochrome or black/white environment. However, the concepts of the present invention are readily applicable to a color environment. Namely, the high addressability error diffusion architecture of the present invention can be replicate three times and placed in parallel to each other so that each color space value representing a color pixel can be individually processed.

Claims: A method of generating an error from a threshold process, comprising the steps of: (a) thresholding a plurality of interpolated subpixel values (B 0 , B 1 , ...B n ) associated with a grey level value (V i ) of an associated pixel; (b) generating a plurality of possible error values in parallel with the thresholding carried out by said step (a); and (c) selecting one of the plurality of possible error values (e i ) based on the number of interpolated subpixel values exceeding a threshold value determined in said step (a). The method as claimed in claim 1, further comprising the step of: (d) diffusing the selected error value (e i ) to grey level values of pixels adjacent to the pixel being thresholded. The method as claimed in claim 1 or claim 2, further comprising the step of: screening the grey level (V i ) value with a predetermined screen prior to the execution of said step (a). A method according to any of the preceding claims, step (a) further comprising the steps of: (a1) receiving the grey level value (V i ) representing the pixel, the grey level value having a first resolution; (a2) converting the grey level value of a pixel to predetermined number of interpolated subpixel values (B 0 , B 1 ,...B n ); (a3) thresholding the interpolated subpixel values. The method as claimed in claim 4, wherein said step (a2) comprises the substeps of: (a2i) computing a first grey level value (V i ) ; and (a2ii) computing a second grey level value (V i+1 ). A system for generating an error from a threshold process, comprising: threshold means (212) for thesholding a plurality of subpixel values (B 0 ,B 1 ,...B n ) associated with a grey level value (V i ) of an associated pixel and for determining a number of subpixel values which exceed a threshold value; error means (201,202), operatively connected in parallel with said threshold means, for generating a plurality of possible error values; and selecting means (203, 213), operatively connected to said error means and said threshold means, for selecting one of the plurality of possible error values (e i ) based on the number of subpixel values exceeding a threshold value determined by said threshold means. The system as claimed in claim 6, further comprising: diffusing means (204) for diffusing the selected error (e i ) value to grey level values of pixels adjacent to the pixel being thresholded, and preferably further comprising: screening means for screening the grey level value (V i ) with a predetermined screen prior to thresholding by said threshold means. The system of claim 6 or claim 7, the threshold means including: input means for receiving the grey level value representing the pixel; and high addressability means for converting the grey level value of the pixel to a predetermined number of subpixel values. The system as claimed in claim 8, wherein said high addressability means computes a first grey level value (V i ) and a second grey level value (V i+1 ). A printing system for rendering marks on a receiving medium, comprising: receiving means for receiving a grey level signal corresponding to a pixel having a first resolution; interpolation means for converting the grey level signal to a second resolution, the second resolution being higher than the first resolution; binarization means for binarizing the converted grey level signal so as to output a binary signal and for determining a number of subpixels which exceed a threshold value; error means, operatively connected in parallel with said interpolation means and said binarization means, for generating a plurality of possible error values; and selecting means, operatively connected to said error means and said binarization means, for selecting one of the plurality of possible error values based on the number of subpixels exceeding a threshold value determined by said binarization means; diffusing means for diffusing the selected error value to grey level signals corresponding to pixels adjacent to the pixel being binarized; and rendering means for converting the binary signal into a mark on the receiving medium.

Inventors: METCALFE DAVID J, SHIAU JENG-NAN, WILLIAMS LEON C, METCALFE, DAVID J., SHIAU, JENG-NAN, WILLIAMS, LEON C.
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1995
Main classification: H04N1
IPC codes: H04N1