Parallel programming method of memory words and corresponding circuit

Abstract: A method for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices comprising at least one matrix of floating gate memory cells with corresponding drain terminals heading columns or bit lines of the matrix which are supplied during the single word programming stage with a drain voltage which is boosted with respect to a supply voltage (Vcc). During the parallel programming stage the supply voltage is used as a drain voltage. Switching is provided between the drain supply using the boosted drain voltage and the supply voltage (Vcc) during the transient between single word programming and parallel programming.

Description: Field of application This invention relates to a method for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices comprising at least one matrix of floating gate memory cells with corresponding drain terminals heading columns or bit lines in the matrix, the said drain terminals being provided during the programming stage with a drain voltage which is boosted in comparison with the supply voltage. The invention also relates to a circuit for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices of the type comprising a drain voltage regulator provided with a voltage booster device to supply the columns or bit lines of a matrix of floating gate memory cells in which the corresponding drain terminals head the said columns. As is well known, non-volatile memory devices which are integrated on semiconductors and which are electrically programmable comprise matrices of memory cells each of which comprises a floating gate MOS transistor. Each transistor comprises a drain region and a source region, provided on the semiconductor substrate and separated by a channel region. A floating gate is provided above the substrate and separated from the latter by a thin layer of gate oxide. A control gate is capacitatively coupled to the floating gate by means of a dielectric layer and metal electrodes are provided to form the drain, source and control gate in order that predetermined voltages can be applied to the memory cell. The matrix of cells is organised in lines, called word lines, and columns, called bit lines. The cells belonging to the same word line have a common electrical line which controls the corresponding control gates, while the cells which belong to the same bit line have their drain terminals in common. The amount of charge present in the floating gate can be varied by applying suitable voltages to the terminals of the cell. The operation by means of which charge is stored in the floating gate is called "programming". Each individual cell is programmed by hot electron injection and allows electrons to be trapped in the floating gate when approximately 12 V is applied to the control gate while the source terminal is connected to earth and the drain terminal is held at a drain voltage of approximately 5.5 V. During the programming stage each cell absorbs a current of approximately 400 µA from the drain. Thus a memory word consisting of one byte, that is an array of eight cells, requires a current of at least 3.2 mA. Prior art It is known that the cells of non-volatile memories, in particular those of the FLASH type, require accurate control of the drain voltage applied to the bit line during the programming stage. The optimum range for the drain voltage is generally rather small and typically lies between 5 and 6 V, and is preferably 5.5 V. The drain voltage is slightly higher than the supply voltage and it is therefore desirable that it should be generated by means of a so-called charge pump. For example a known technical arrangement described in US patent no. 5,263,000 provides that the drain voltage be provided by means of a voltage booster device fed by the dc supply voltage of 5V. The value of the voltage provided by the voltage booster device is an optimum when the memory is programmed for an individual byte. There are however other programming stages in which it is necessary to be able to programme a number of bytes in parallel, for example four or eight bytes. A typical example of this need occurs when testing the memory matrix. In fact, to reduce the duration of the test it is very important to be able to perform screening by programming several bytes in parallel. The patent publications WO-A-83 01146 of MOTOROLA, INC. and US-A-5 357 463 by KINNEY disclose such parallel programming of bytes. We have seen however that each byte takes up a current of at least 3.2 mA during the programming stage. Therefore the simultaneous programming of four bytes requires at least 12.8 mA, while the programming of eight bytes requires the provision of at least 25.6 mA. Unfortunately the current provided by the voltage booster device is proportional to the value of the capacitance incorporated within it. Thus in order to be able to deliver 25.6 mA at a voltage of 5.5 V it will be necessary to provide a voltage booster device having quite a substantial circuit size. This would compromise the reliability of the voltage booster device and would greatly reduce the ratio between the circuit area occupied by the voltage booster device and the overall area of the memory. Substantially, parallel programming sets the problem of how to provide a voltage booster device of small dimensions which is nevertheless capable of delivering a relatively high current. The technical problem underlying this invention is that of devising a method of parallel programming and a corresponding circuit which makes it possible to satisfy the current requirement of the memory cells with maximum reliability while maintaining the ratio between the area occupied by the voltage booster device and the matrix of cells as high as possible, thus overcoming the limitations of the current arrangements provided by the known art. Summary of the invention The concept underlying this invention is that of maintaining the structure of the voltage booster device designed for the programming of individual bytes and using the supply voltage Vcc as the supply to the drain during the parallel programming stage. On the basis of this concept the technical problem is solved by a method of the type indicated above and defined in the characterising part of claim 1 appended hereto. The technical problem is also resolved by a circuit for implementing the said method as defined by claims 5. The features and advantages of the method and circuit according to the invention will be apparent from the following description of an embodiment given by way of a non-restrictive illustration with reference to the appended drawing. Brief description of the drawing The single figure shows a diagrammatical view of a programming circuit constructed in accordance with this invention. Detailed description With reference to these figures, 1 indicates as a whole and diagrammatically a programming circuit for electrically programmable and cancellable non-volatile memory cells, for example cells of the FLASH type. Circuit 1 is designed in particular, but not exclusively, for a single power supply memory 2 connected to a dc supply reference voltage of 5 V. Circuit 1 is associated with a voltage regulator 3 incorporating a charge pump. More particularly, voltage regulator 3 comprises a voltage booster device 4, that is a charge pump circuit fed by the supply voltage Vcc. The magnitude of the voltage generated at the output from the voltage booster device depends on the supply voltage Vcc and the current which has to be provided; the latter depends on the number of bits which have to be programmed (from 0 to 8). Memory 2 is organised as a matrix of cells arranged in lines, called word lines, and columns called bit lines. The cells belonging to the same word line WL have in common an electrical line which controls the corresponding control gates, while the cells belonging to the same bit line have their drain terminals in common. In the figure matrix 2 is illustrated diagrammatically by way of example with an associated column decoder 5 fed by an output 6 from voltage regulator 3. Advantageously, according to the invention, a connection is also provided between supply reference voltage Vcc and decoder 5. This connection makes it possible to transfer the supply voltage Vcc to the drain terminals of the memory cells at predetermined times, and in particular during the parallel programming stage. A transistor M1 of the N-channel MOS type, with the drain terminal connected to the supply reference voltage Vcc and the source terminal connected to decoder 5 is inserted in this connection. The gate terminal of transistor M1 is connected to the output of an enabling circuit 7 comprising a first 8 and a second 9 complementary pair of MOS transistors. Each pair 8, 9 comprises the sequence of a P-channel transistor and an N-channel transistor inserted between a voltage pole Vpcy and a second reference voltage, for example a signal earth GND. The voltage Vpcy is provided by an output 11 from a second voltage booster device 10 fed by the 5 V supply voltage Vcc. A cross connection is provided between the gate terminal of the P-channel transistor of first pair 8 and the interconnection node between the transistors of the second pair 9. Similarly a cross connection is provided between the gate terminal of the P-transistor of the second pair 9 and the interconnection node between the transistors of the first pair 8. The gate terminal of the N-channel transistor of complementary second pair 9 receives an enabling voltage signal indicated by the term par-prog. This signal is also applied to an input 12 in the second voltage booster device 10 and to the gate terminal of the N-channel transistor of the other complementary pair 8 via an inverter 13. Advantageously the par-prog signal is also applied to an input of regulator 3 and decoder 5. The structure of the circuit according to the invention is particularly simple and easy to understand. The parallel programming stage is initiated by the output front of the par-prog signal which enables switching of the supply to the drain terminals of matrix cells 2. During the stage of single byte programming the par-prog signal has a low logic value and the voltage for the bit lines of matrix 2 is provided by regulator 3 which operates normally according to specification. During this stage transistor M1 is inactive and disconnects decoder 5 from supply Vcc. Transistor M1 operates essentially as a pass-gate. The method according to the invention therefore provides that voltage booster device 4 remains active during the single byte programming stage; in the meanwhile supply voltage Vcc is used as a supply for the drain during parallel programming. When it is necessary to activate the parallel programming of a number of bytes, the drain voltage is provided directly from the supply Vcc, which has no problems in providing all the current which the cells require. The supply voltage Vcc is transferred to the drain terminals of the memory cells by means of transistor M1 which is suitably dimensioned for this purpose. The gate terminal of this transistor M1 is boosted to the value of voltage Vpcy by means of enabling circuit 7. The par-prog signal activates the N-Channel transistor of second complementary pair 9 which makes it possible for voltage Vpcy to be applied to the gate of transistor M1. The increased voltage Vpcy is already available in the circuitry associated with memory matrix 2, and therefore its use to enable transistor M1 is advantageous in order to reduce the voltage drop in that transistor. The invention solves the technical problem and provides many advantages. Among these, the most important is due to the fact that use of only N-Channel transistor M1 as a pass-gate makes a P-Channel type switch between the output 6 of the regulator and the supply reference voltage Vcc superfluous. This makes it possible to reduce the size of the circuit area; in addition to this, the conductivity of the N-Channel pass-gate is greater than that of any P-Channel switch. These and other advantages make it possible to make a series of modifications and variants to the invention which nevertheless fall within the scope of the following claims.

Claims: A method for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices comprising at least a matrix of memory cells with a floating gate with corresponding drain terminals heading columns or bit lines of the matrix, said drain terminals being supplied during the programming stage with a drain voltage which is increased with respect to a supply voltage (Vcc), characterised in that during the parallel programming stage this supply voltage is used as a drain voltage. A method according to claim 1, characterised in that a switch is provided between the drain supply voltage and the supply voltage during the transient between single word programming and parallel programming. A method according to claim 1, characterised in that a connection is provided between a supply reference voltage and a column decoding circuit portion of said matrix with an inserted pass-gate. A method according to claim 3, characterised in that said pass-gate is an N-Channel MOS transistor with a gate terminal subject to a parallel programming enabling circuit. A circuit (1) for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices (2), of the type comprising a drain voltage regulator (3) provided with a voltage booster device (4) to supply the columns or bit lines of a floating gate memory cell matrix in which the corresponding drain terminals head the said columns, characterised in that it comprises a connection which is normally open between a supply reference voltage (Vcc) and a decoder (5) for said columns and a switch (M1) which is subject to a closing enabling signal to supply the supply voltage (Vcc) to the said drain terminals during parallel programming of the said memory words. A circuit according to claim 5, characterised in that said switch (M1) is a pass-gate. A circuit according to claim 6, characterised in that said pass-gate is an N-Channel MOS transistor. A circuit according to claim 5, characterised in that said switch (M1) is subject to an enabling circuit (7) comprising at least one complementary pair (8) of MOS transistors inserted between a first boosted reference voltage (Vpcy) and a second reference voltage (GND). A circuit according to claim 5, characterised in that said switch is a MOS transistor to the gate terminal of which said enabling signal is applied. A circuit according to claim 6, characterised in that said enabling signal transfers a voltage (Vpcy) which is boosted with respect to said supply voltage (Vcc) to said terminal.

Inventors: SALI MAURO, SCHIPPERS STEFAN, TASSAN CASER FABIO, SALI, MAURO, SCHIPPERS, STEFAN, TASSAN CASER, FABIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: G11C16
IPC codes: G11C29, G11C16, G11C17