Phase lock detector

Abstract: A phase lock detector for a digital phase locked loop frequency synthesiser in which phase errors, represented by phase error pulses of a duration equal to the relative time displacement of synthesised and reference waveforms in the phase locked loop, are compared with a predetermined time interval representing the maximum phase error acceptable in a phase-lock condition. A favourable result of the comparison may be required to persist for a predetermined time before a phase-lock indication is given, to avoid jitter or flicker of that indication in a near-lock situation.

Description: The present invention relates to a phase lock detector for a digital phase locked loop frequency synthesiser. Often in phase locked loop arrangements it is necessary to provide a signal indicating whether "lock" has in fact been achieved, this signal being made available, say, on an output terminal of the arrangement or as a specified bit in a serial data word clocked from the arrangement. In either case some means for generating this signal is required. Determination of whether lock has been achieved may be based on an assessment of whether the phase error indicated by the phase detector of the phase locked loop is sufficiently small, by using a counter to compare a time interval representing the phase error with a predetermined time interval, "in lock" being indicated when the phase error interval is shorter than the predetermined time interval. Such an arrangement is described for example in EP-A-0 012 899. A first problem with this approach is that the required predetermined time interval is much shorter than any reference interval normally available. For example, in a typical phase locked loop arrangement for television tuner applications, the interval required may be of the order of 100ns, while the highest reference frequency available may be 4MHz, defining a 250ns period. A second problem is how to maintain stability of the lock signal produced, so that when the phase locked loop arrangement is close to lock, the "in lock" signal does not flicker on and off. According to one aspect of the present invention a phase lock detector arrangement for a digital phase locked loop frequency synthesiser comprises a counter means which is used to measure a time interval which represents a phase error between an event in a synthesised waveform and a corresponding event in a reference waveform, and means responsive to a predetermined count state of said counter means to give a large-error indication, wherein phase lock is taken to be established if said phase error time interval is less than a predetermined value, is characterised in that the detector arrangement comprises an oscillator responsive to the occurrence of said event in one of said synthesised and reference waveforms to commence oscillating and to the occurrence of said event in the other of said synthesised and reference waveforms to stop oscillating, said counter means being arranged to count output cycles of said oscillator. Preferably the occurence of said event in the other of said synthesised and reference waveforms is arranged to reset the counter means. The absence of said large-error indication for more than a predetermined time may be taken to indicate phase lock. A second counter means may be provided to determine said predetermined time, said second counter means being arranged to be reset upon the occurrence of said large-error indication. A phase lock detector for a digital phase locked loop frequency synthesiser will now be described by way of example with reference to the accompanying drawing, which shows the detector schematically. Referring to the drawing, phase error signals between synthesised and reference waveforms from a phase locked loop frequency synthesiser (not shown), which waveforms may be effectively of two-state form, at inputs 1 and 2 are applied inverted to an And gate 3 to derive a single phase error pulse signal on path 4 which commences when one of the waveforms changes state in a given sense and terminates when the other waveform changes state in the same sense. The phase error pulse signal is applied to an input of an And gate 5 forming part of a ring oscillator 6 and to the "set" inputs of a two-bit counter 7. In the absence of a phase error pulse the ring counter 6 is disabled and the counter 7 is held in a predetermined state, such as 1,1. At the commencement of a phase error pulse the ring oscillator is enabled, its period being, say, 60ns, and the counter 7 is released to begin counting output cycles of the oscillator 6. If the phase error pulse if longer than 180ns, that is, three cycles of the oscillator 6, so that the count state of the counter reaches 1,0, an And gate 8 provides a large-error output on path 9. If, however, the phase error pulse is shorter than 180ns the oscillator 6 is disabled, the counter 7 is set again, and no output is provided on path 9, this condition, if persisting, indicating the required phase-lock state. The path 9 is connected to the "set" inputs of a two-bit counter 10 and a bistable circuit 11, setting them or holding them in their respective reset states whenever a large-error output signal is provided by the And gate 8. When the large-error signal on the path 9 ceases the counter 10 and the bistable circuit 11 are enabled, and the counter 10 starts to count signals at half the frequency of a reference signal applied to an input 12. After four periods of this half reference frequency, which may define an interval of the order of a millisecond, the bistable circuit 11 is switched to its "reset" state (logic 'O') and an indication is given on an output path 13 that phase lock has been achieved. At the same time the counter 10 is disabled by way of an And gate 14, so that the phase lock indication is maintained until a large-error signal occurs again on path 9. If a large-error is detected before the count state of the counter 10 has reset the bistable circuit 11, the counter 10 and bistable circuit 11 will be set again, forcing the count to start again. The phase lock indication on output 13 will therefore be given only if an interval of four or more periods of the half reference frequency, i.e. one millisecond or more, occurs without large error signals on the path 9, to avoid any jitter or flicker that may occur when close to lock. The period of the oscillator 6 may be adjusted by varying either the power or the number of the buffer stages in the ring.

Claims: A phase lock detector arrangement for a digital phase locked loop frequency synthesiser comprising a counter means (7) which is used to measure a time interval which represents a phase error between an event in a synthesised waveform and a corresponding event in a reference waveform, and means (8) responsive to a predetermined count state of said counter means (7) to give a large-error indication, wherein phase lock is taken to be established if said phase error time interval is less than a predetermined value, characterised in that the detector arrangement further comprises an oscillator (6) responsive to the occurrence of said event in one of said synthesised and reference waveforms to commence oscillating and to the occurrence of said event in the other of said synthesised and reference waveforms to stop oscillating, said counter means (7) being arranged to count output cycles of said oscillator (6). A phase lock detector arrangement in accordance with Claim 1 wherein the occurence of said event in the other of said synthesised and reference waveforms is arranged to reset the counter means (7). A phase lock detector arrangement in accordance with Claim 1 or Claim 2 wherein the absence of a large-error indication for more than a predetermined time is taken to indicate phase-lock, and there is provided a second counter means (10) which is arranged to determine said predetermined time and which is arranged to be reset upon the occurrence of a large-error indication.

Inventors: MUDD MARK STEPHEN JOHN, MUDD, MARK STEPHEN JOHN
Applicants: PLESSEY SEMICONDUCTORS LTD, PLESSEY SEMICONDUCTORS LIMITED
Application year: 1995
Main classification: H03L7
IPC codes: H03L7