Semiconductor memory device

Abstract: A semiconductor memory device includes first and second MOS transistors connecting a pair of data lines with a specific potential supplying node (14). A power transmitting circuit (13, 15, 16) couples the specific potential supplying node (14) with a power supply circuit (5) of an equalizing potential (HVcc) after said first and second switching elements are made conductive. The power transmitting circuit (13) isolates the specific potential supplying node (14) from the power supply circuit (5) when the equalization begins. As an alternative to the power transmitting circuit, a supplying circuit (5, 8, 9, 17, 18) may be connected to supply a precharge potential to the specific potential supplying node (14) when the equalization begins, and supply an equalizing potential to the specific potential supplying node (14) when the switching elements are both turned on.

Description: The present invention relates to a semiconductor memory device, such as a dynamic random access memory (hereinafter referred to as DRAM), and in particular to a memory device which includes a precharge and equalization circuit for quickly bringing a pair of data lines to a fixed potential. An example of a conventional equalizing circuit is shown in US-A-5,036,492. The equalizing circuit is formed of two transistors provided between a pair of bit lines connected to a precharge circuit for supplying a predetermined potential. The two transistors have their sources connected respectively to the data lines, their drains connected with each other, and their gates to which complementary equalizing signals are supplied. A bleeder current device is also connected to the drains. With such a configuration, the two transistors are concurrently activated, by means of the complementary equalizing signals, to set the bit lines to the same potential. The bleeder current device absorbs or supplies current so that the potentials on the bit lines do not depart from the set potential. The above-described equalizing circuit requires a precharge circuit, and two control signals are required to control the precharge circuit and the equalizing circuit, so that the control over operation is complicated, and it is difficult to increase the overall operation speed of the device. US-A-4,494,221 discloses a bit line precharging and equilibrating circuit, in which a transistor is coupled to the common node of a pair of precharge/equalizing transistors to establish a momentary reduction of the potential at the common node, so as to expedite the conduction of the precharge/equalizing transistors. The transistor circuit is configured so that its source is coupled to the common node and its gate and drain are coupled to the same voltage source (Vcc). JP-A-58 035 795 and Patent Abstracts of Japan, vol. 7, no. 117 (P- 198), 21 May 1983 discloses another type of bit line precharge and equalizing circuit. In accordance with the invention, there is provided a semiconductor memory device comprising a pair of data lines for transferring complementary signals, an equalizing circuit having a first MOS transistor connected between one of said pair of data lines and a specific potential supplying node, and a second MOS transistor connected between the other of said pair of data lines and the specific potential supplying node, said first and second MOS transistors being made conductive in accordance with a first control signal to electrically connect said pair of data lines together, and a power transmitting circuit for connecting said specific potential supplying node with a power supply circuit arranged to provide an equalizing potential (HVcc), said power transmitting circuit being configured to cause the potential of said specific potential supplying node to be varied at least for a period after one of said first and second MOS transistors becomes conductive and before the other of said first and second MOS transistors becomes conductive, so as to expedite the conduction of said other of said first and second MOS transistors, characterised in that said power transmitting circuit is operable to isolate said specific potential supplying node from said power supply circuit at least for a period after one of said first and second MOS transistors becomes conductive and before the other of said first and second MOS transistors has become conductive, and to connect said specific potential supplying node with said power supply circuit after both of said first and second MOS transistors are made conductive. The first and second switching elements of said equalizing circuit may comprise MOS transistors having their gate electrodes connected to receive said control signal. With the above arrangement, the specific potential supplying node is isolated from the equalizing potential power supply circuit when one of the switching elements is conductive and the other switching element is not yet conductive, at the same time when the equalization begins, i.e., when the control signal changes from the inactive state to the active state. As the potential of the control signal line varies (from the inactive state toward the active state) one of the switching elements (first switching element) connected to one of the data lines is turned on, so that the potential of the specific potential supplying node is varied toward the potential of the above-mentioned one of the data lines. When the potential of the control signal becomes sufficient, the switching element (second switching element) connected to the other data line is made conductive. It take less time for the potential of the control signal to become sufficient to turn on the second switching element because of the variation of the specific potential supplying node toward the above-mentioned one of the data lines, than if the specific potential supplying node is fixed at the equalizing potential. Thus, the two switching elements are made conductive in a shorter time, than if the specific potential supplying node is not isolated from the equalizing power supply circuit. Assume that the switching elements are N-channel MOS transistors. As the potential of the control signal line rises (above a threshold of the MOS transistor) one of the MOS transistors (first MOS transistor) connected to one of the data lines which has transferred the signal of a lower potential level is made conductive to draw the charge from the specific potential supplying node, so that the potential of the specific potential supplying node is lowered. Because of the potential drop of the specific potential supplying node, the MOS transistor (second MOS transistor) connected to the data line having a higher potential is made conductive when the potential of the control signal becomes sufficient. The potential sufficient to turn on the second MOS transistor is the sum of the threshold of the transistor and the potential of the specific potential supplying node, which is lower than if the specific potential supplying node is fixed at the equalizing potential. Accordingly, the MOS transistor are made conductive in a shorter time, than if the specific potential supplying node is not isolated from the equalizing power supply circuit. Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram showing a precharge and equalization circuit according to the invention; and Figure 2 is a waveform diagram showing the operation of the circuit of Figure 1. In the various figures of the drawings, identical reference numerals denote identical or corresponding elements or components. Fig. 1 is a circuit diagram of a precharge and equalization circuit according to the present invention. The precharge and equalization circuit shown in Figure 1 comprises an equalizing circuit 10, which is disposed between a pair of data lines 1 and 2 connected to an amplifier 3, such as a sense amplifier, via switches 4. The equalizing circuit 10 comprises a pair of switching elements, in the form of N-channel MOS transistors 11 and 12 having their drains connected to the data lines 1 and 2, respectively, their sources both connected to a specific potential supplying node 14, and their gates connected to a control signal line 6. The precharge and equalization circuit further comprises a power transmitting circuit which is formed of an N-channel MOS transistor 13 having a gate connected to a second control signal SE. The drain of the transistor 13 is connected to the specific potential supplying node 14, and the source of the transistor 13 is connected to an equalizing potential power supply circuit 5 supplying an equalizing potential HVcc (Vcc/2). The second control signal SE makes the MOS transistor 13 non-conductive while the control signal 6 changes from the inactive state to the active state, and making the MOS transistor 13 conductive after the first and second switching elements 11 and 12 are made conductive. The data lines 1 and 2 are driven by the amplifier 3 via the switches 4 to transfer complementary information (Vcc level or the GND (ground) level). For reading data from a memory cell not shown, the switch 4 is turned on to drive the pair of data lines 1 and 2 by means of the amplifier 3 for the purpose of information transfer. They are assumed to be set at the Vcc level and the GND level, respectively. The control line 6 is at the Low level (GND level), so that the transistors 11 and 12 are off, and the control signal SE is at the High level, and the transistor 13 is on, and the potential of a node 14, which is the specific potential supplying node, is at HVcc. After the information transfer is completed, the switches 4 are turned off to isolate the amplifier 3 from the data lines 1 and 2, and the control signal SE is brought to the Low level to turn off the transistor 13, and the potential of the control line 6 is raised to the High level to commence the equalizing operation, in preparation for the next cycle of data transfer operation. When the potential of the control line 6 exceeds the threshold potential Vth of the transistor 12, the transistor 12 is turned on, and the potential level of the node 14 is lowered. This is because the node 14 is isolated from the power supply circuit 5, and the parasitic capacitance of the node 14 is small compared with the data line 2 at the GND level, so that the charge is drawn from the node 14. Because of the lowering of the potential level of the node 14, the gate voltage of the transistor 11 becomes sufficient, i.e., exceeds the threshold, also denoted by Vth, of the MOS transistor 11, and the transistor 11 is turned on. As a result, the potential level of the data line 1 is lowered. Thereafter, the control signal SE is raised to the High level at a predetermined timing, the node 14 is connected to the power supply circuit 5, to equalize the potentials of the data lines 1 and 2 to HVcc. Because the potential of the node 14 is lowered before the transistor 11 turns on, it takes less time for the MOS transistor 11 to turn on, than if the potential of the node 14 is fixed at the equalizing potential HVcc. If the potential of the node 14 is fixed at HVcc, the MOS transistor 11 is not turned on until the potential on the control line 6 exceeds HVcc + Vth (Vth being the threshold of the MOS transistor 11). Accordingly, the MOS transistors 11 and 12 are turned on in a shorter time than if the node 14 is not isolated from the equalizing potential power supply circuit 5. The pair of data lines are quickly equalized by means of a relatively simple configuration. Moreover, the number of transistors connected to the control line 6 is two per pair of data lines, so that delay in the rise of the data lines due to the parasitism of gate capacitances can be avoided. Furthermore, increase in the power consumption in the equalizing circuit is small. The invention is not limited to the embodiment lescribed above. The switching elements may be all formed of transistors. If the transistors are all of the same channel type, fabrication of the device is simpler. The inventive concept described in connection with FIG. 1 can also be applied to a situation where the switching elements of the equalizing circuit are formed of P-channel MOS transistors. In such a case, the control signal is at a high level when it is in an active state, and is at a low level when it is in an inactive state. As the potential of the control signal line is lowered (below a threshold of the MOS transistor) one of the MOS transistors (first MOS transistor) connected to one of the data lines which has transferred the signal of a higher potential level is made conductive, so that the potential of the specific potential supplying node is raised. Because of the potential increase in the specific potential supplying node, the MOS transistor (second MOS transistor) connected to the data line having a lower potential is made conductive when the potential of the control signal becomes sufficiently low. The potential sufficiently low to turn on the second MOS transistor is the sum of the threshold of the transistor and the potential of the specific potential supplying node, which is higher than if the specific potential supplying node is fixed at the equalizing potential. Accordingly, the MOS transistors are made conductive in a shorter time, than if the specific potential supplying node is not isolated from the equalizing power supply circuit.

Claims: A semiconductor memory device comprising: a pair of data lines (1,2) for transferring complementary signals; an equalizing circuit (10) having a first MOS transistor (11) connected between one (1) of said pair of data lines and a specific potential supplying node (14), and a second MOS transistor (12) connected between the other (2) of said pair of data lines and the specific potential supplying node (14), said first and second MOS transistors (11,12) being made conductive in accordance with a first control signal (6) to electrically connect said pair of data lines (1,2) together; and a power transmitting circuit (13) for connecting said specific potential supplying node (14) with a power supply circuit (5) arranged to provide an equalizing potential (HVcc); said power transmitting circuit (13) being configured to cause the potential of said specific potential supplying node (14) to be varied at least for a period after one of said first and second MOS transistors becomes conductive and before the other of said first and second MOS transistors becomes conductive, so as to expedite the conduction of said other of said first and second MOS transistors; characterised in that said power transmitting circuit (13) is operable to isolate said specific potential supplying node (14) from said power supply circuit (5) at least for a period after one of said first and second MOS transistors becomes conductive and before the other of said first and second MOS transistors has become conductive, and to connect said specific potential supplying node (14) with said power supply circuit (5) after both of said first and second MOS transistors are made conductive. A semiconductor memory device according to claim 1, wherein said first control signal is in an active state to make the first and second MOS transistors conductive, and in an inactive state to make the first and second MOS transistors non-conductive; and said power transmitting circuit comprises a third MOS transistor (13) having a first electrode connected to said specific potential supplying node (14), a second electrode connected to said power supply circuit (5), and a gate electrode to which a second control signal (SE) is applied; said second control signal (SE) making said third MOS transistor non-conductive while said first control signal changes from the inactive state to the active state, and making said third MOS transistor conductive after both of said first and second MOS transistors have been made conductive. A semiconductor memory device according to claim 1 or 2, wherein said first and second MOS transistors (11,12) of said equalizing circuit have their gate electrodes connected to receive said control signal.

Inventors: TANABE TETSUYA, TANAKA YASUHIRO, TANABE, TETSUYA, TANAKA, YASUHIRO, TANABE, TETSUYA, C/O OKI ELECTRIC IND. CO. LTD., TANAKA, YASUHIRO, C/O OKI ELECTRIC IND. CO. LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1995
Main classification: G11C7
IPC codes: G11C11, G11C7