Emulation of direct memory access

Abstract: A method and means are provided for simulating a direct memory access (DMA) function to access memory in a host computer having a DMA controller for the purpose of enabling the transfer of data between the host memory and a computer accessory data handling device not capable of DMA operation that can be operably connected to the host including determining the location in the host memory for data to be transferred from the host memory to the accessory data handling device or from the accessory data handling device to the host memory by reading the memory address contents of the DMA controller. Data is read data from the host memory at the address specified in the DMA controller and written to the accessory data handling device or read from the accessory data handling device and written to the host memory at the address specified by the DMA controller, respectively. The host computer is informed that a DMA operation corresponding to the data transfer has been completed when the data transfer required has been completed.

Description: Field of the Invention The present invention relates to the field of computer systems using DMA controllers for direct memory access and more particularly to interface or accessory cards (otherwise referred to as accessory data handling devices) not capable of direct memory access. Background of the Invention When the IBM Personal Computer (IBM is a registered trademark of IBM Corporation), now known as the IBM PC, was introduced it included a central processing unit (CPU) a random access memory (RAM) and a DMA controller which served the function of allowing direct memory access to the RAM memory without the necessity of using the CPU to control the memory access, thus freeing up the CPU for other processing activities. This improved efficiency over previous computers. The direct memory access (DMA) capability of the IBM PC was carried over to the IBM Personal Computer AT and the IBM PS/2 designs (AT, PS/2 and Micro Channel are trademarks of IBM Corporation) and in fact has been carried over to many PC's in the industry including ISA architecture computers. ISA (Industry Standard Architecture) is based on AT computer architecture. Figure 1 is a block diagram of an ISA computer illustrating the major components thereof. U.S. Patent 4,658,350 issued April 14, 1987 and assigned to International Business Machines Corporation, may be referred to for a teaching of DMA architecture. Additionally, a description of DMA can be found in section 11 of "Computer System Architecture" by M. Morris Mano (Prentice Hall, 1993). As a result of the common use of DMA architecture, software that runs on PC computers is frequently designed to take advantage of the direct memory access capabilities, by initiating DMA operations for transfers of data between the host RAM memory and peripherals operating with the host system. This applies to both read operations in which data is read from the host RAM memory and write operations in which data is written to the host RAM memory. Referring to Figure 1, the typical software application that uses DMA first sets up the DMA controller 3 of the host PC 4 by writing to the DMA controller 3 the starting address of the location where data is to be written to or read from in the host RAM memory 2, the amount of data to be transferred, and the type of operation to be performed, i.e. read or write. In the case of a transfer of data from the host RAM memory 2 to an accessory card connected to the host by the ISA bus 5 and X bus 6, the application initiates DMA operation as follows: to transfer data from the host to the card; I The application sends a command to the card to start DMA operation; II The card then activates the DMA request line which is present in the host as part of the X bus 6; III The DMA controller returns an acknowledge signal on the host DMA acknowledge line (which is also part of the X bus 6); IV The data is transferred from the RAM memory 2 of the host 4 to the card 10, under control of the DMA controller 3, which issues a read command on the read/write line (which is part of the X bus 6) of the host causing data to be transferred from the RAM memory 2 along the data bus (which is contained in the X bus 6 and ISA bus 5) of the host 4 to the adapter card. In the case of a transfer of data from the accessory card to the host, in which the data is made available on the adapter card, either from data processing that has been carried on by the card, or from data that has been provided externally to the card; I the card activates the DMA request line to request the services of the DMA controller in transferring the data; II the DMA controller sends a DMA acknowledge signal back to the card III the card then transfers the data onto the host data bus under control of the DMA controller which writes the data to the RAM memory of the host at the address specified by the DMA controller. This works well if the card is DMA compatible, but if the accessory card is not adapted to connect to the DMA controller or is not DMA compatible, the accessory card will not be compatible with applications that use DMA. IBM Technical Disclosure Bulletin vol.33, no. 6A, Nov.1990 at pages 495-497 describes the "transparent addition of DMA support to existing parallel port ABIOS interface". This shows transfers under either DMA or programmed I/O interface control, depending on pointers from the device drivers. US-A-5113500 (Talbott et al) describes software emulation of I/O commands between two different types of computer. However, there is still a need for a system which will permit a non-DMA accessory card to function compatibly with applications which require DMA operation for successful operation while running on the host. A number of different standards have been accepted for PC accessory boards. One of these standards, the PCMCIA standard, does not permit DMA transfers as no electrical connections are provided for these accessory cards to the host DMA request or acknowledge lines. PCMCIA cards are proving to be more popular in the computer industry because of their size advantage and use in laptops or notebook computers. Accordingly it would be useful in the case of the PCMCIA cards to provide a method and means to make them operable or compatible with the DMA operations of a host computer. Summary of the Invention This invention provides a method and means for enabling an accessory which is not capable in itself of DMA operation to operate in a host system having DMA compatibility with application software running that makes use of or requires DMA operation compatibility. According to one aspect, the invention provides a method of processing data in a computer system comprising a host computer and an accessory data processing device connected to said host computer, the host computer having a central processor, a memory and a direct memory access (DMA) controller for controlling transfer of data between the memory and DMA compatible accessory devices in response to a DMA transfer initiation command from an application program running in said host computer, wherein said first mentioned accessory device is not DMA compatible, the method comprising the steps of: trapping said DMA transfer command in a buffer of said non-DMA compatible accessory device; generating in response thereto an interrupt from said non compatible accessory device to said host computer; in response to said interrupt, starting an emulation program, the emulation program controlling said commanded transfer of data between said non-compatible accessory device and the host computer memory and concurrently simulating to said host computer and DMA controller the signals which would be expected from a DMA compatible accessory device if it were participating in said data transfer; said data transfer step comprising: determining the location in said host memory for data to be transferred from said host memory to said non-DMA compatible accessory device or from said accessory device to said host memory; and for a data transfer from host memory to said accessory device, reading data from said host memory and writing it to said accessory device; or for a data transfer from accessory device to host memory, reading data from said accessory device and writing it to said host memory, respectively; and said simulating step comprises informing said host computer that a DMA operation corresponding to said data transfer has been completed. One embodiment of the invention preferably accomplishes reading the memory address contents of the DMA controller to determine the starting address of the location in the host memory for the data, and the maximum amount of data to be transferred. Advantageously the method of the invention may include updating the address information in the DMA controller as data is transferred between host and accessory card to maintain the currency of the DMA controller information corresponding to information that would be present if an actual DMA access of the memory had taken place. The method of the invention may advantageously include, updating the information in the DMA controller to indicate the end of a DMA operation when the data transfer has been completed. The method of the invention may also include, in the determination of the starting address, the calculating of an address compensation factor for determining the correct starting address if the DMA controller of the host free runs when it is unmasked. According to a second aspect, the invention provides a host computer system comprising a central processor, a memory and a direct memory access (DMA) controller for controlling transfer of data between the memory and a DMA-compatible accessory data processing device in response to a DMA transfer initiation command from an application program running in said host computer system, said host system being capable of receiving a non-DMA compatible accessory data processing device arranged to generate an interrupt to said host system upon receipt of a DMA transfer initiation command, the system further including an emulation computer program and means for starting said emulation program in response to such an interrupt from a non-DMA compatible accessory device, the emulation program comprising means for controlling said commanded transfer of data between said non-compatible accessory device and said memory and means for simulating to said host computer and said DMA controller, concurrently with said transfer, the signals which would be expected from a DMA-compatible device if it were participating in said data transfer; said means for controlling said commanded transfer including means for determining the location in said memory for data to be transferred from said memory to said non-DMA compatible accessory device or from said accessory device to said host memory; and means for reading data from said memory at the address specified in said DMA controller for said data and for writing said data to said accessory device and for reading data from said accessory device and writing it to said memory at the address specified by said DMA controller, respectively; and said simulating means including means for informing said host computer that a DMA operation corresponding to said data transfer has been completed. According to a third aspect, the invention provides a computer program for use in a host computer system which system comprises a control processor, a memory and a direct memory access controller for controlling transfer of data between the memory and a DMA compatible accessory data processing device in response to a DMA transfer initiation command from an application program running in said host computer system, said host system being capable of receiving a non-DMA compatible accessory data processing device arranged to generate an interrupt to said host system upon receipt of a DMA transfer initiation command, said program being started in response to such an interrupt from a non-DMA compatible accessory device; wherein said program comprises: means for controlling said commanded transfer of data between said non-compatible accessory device and said memory and means for simulating to said host computer and said DMA controller, concurrently with said transfer, the signals which would be expected from a DMA-compatible device if it were participating in said data transfer; said means for controlling said commanded transfer including means for determining the location in said memory for data to be transferred from said memory to said non-DMA compatible accessory device or from said accessory device to said host memory; and means for reading data from said memory at the address specified in said DMA controller for said data and for writing said data to said accessory device and for reading data from said accessory device and writing it to said memory at the address specified by said DMA controller, respectively; and said simulating means including means for informing said host computer that a DMA operation corresponding to said data transfer has been completed. The emulation program is preferably a terminate and stay resident program (TSR), which is operable on the host to emulate DMA operations when called upon by an application running on the host or on the accessory card or when called upon by the accessory card to access the RAM memory on the host controlled by the host's DMA controller. In the case of the transfer of data from the host RAM memory to the accessory card, the application running on the host sets up the host's DMA controller by providing it with the starting address, data quantity and provides to the accessory card the exact amount of data to be transferred and the type of operation (read or write), in this illustration, a read instruction, to perform the necessary operation. For transfer from the host to the accessory card the application program sends a command to the card to start the DMA read operation. In one optional implementation the accessory card activates an interrupt to the host (ie. to its CPU 1) to stop it from performing other processing tasks. The TSR program is activated, which then identifies that a DMA operation has been requested. The TSR reads the contents of the DMA controller to obtain the starting address, and the maximum amount of data to be transferred. The TSR also reads the exact amount of data to be transferred and whether it is to be a read or write operation. It then reads data, preferably in blocks, from the host RAM memory and writes the data to the appropriate memory of the accessory card. After TSR has completed its operation the TSR can end the interrupt, if an interrupt has been requested, of the host CPU. In the case of the transfer of data in the other direction, ie. from the card to the host, for instance, where data has been generated by the card, or received by the card, for instance by external input for transfer to the host, the card notifies the host that a data transfer is required. It can do this by generating an interrupt to the CPU; after which the TSR is activated and identifies that a data transfer is required from the card to the memory. The TSR reads the contents of the DMA controller to obtain the start address and maximum byte count of data to be transferred. (Note that the DMA controller was set up previously by the application program with the start address of the data, and the maximum byte count of data to be transferred). The TSR reads from the card the exact amount of data to be transferred and whether it is a read or write operation. The TSR reads data from the card and writes the data to the RAM memory of the host. After writing has been completed the interrupt request is ended. This process is repeated until all data has been transferred. Brief Description of the Drawings Figure 1 is a block diagram of an ISA computer illustrating the major components thereof. Figure 2 is a simplified diagram of a PCMCIA sound card made in accordance with the invention herein. Figure 3 is a flow chart of an embodiment of the method of the invention. Detailed Description of Preferred Embodiments of the Invention The following is a step-by-step illustration of an embodiment of the invention (using a TSR in accordance with the invention) for transfer of data between the host 4 and accessary card 10; (1) The (software) application running in the host 4 sets up the DMA controller 3 using the current address register of the DMA controller 3 and the page address register of the host 4 (the DMA and page registers are well known and need not be described further) with the starting address in memory 2 of where the data is to be read from; and the maximum amount of data to be transferred using the DMA count register, (2) The host (software) application sends a command to the accessory card to start DMA operation and informing it of the amount of data to be transferred and that the operation to be performed is a write operation to the card; (the information is stored in a buffer or memory on the card) (3) The card responds sending an interrupt to the host activating the TSR ; (4) The TSR reads from the DMA controller the start address and reads from the card (from a buffer or memory on the card) the byte count (amount of data to be transferred) and the control information required (a write instruction). The TSR keeps track of the information read from the DMA controller for subsequent operations. (5) the accessory card interrupts the host for the subsequent transfer of data required; (6) The TSR reads data from the host; (7) The TSR writes data to the accessory card; (8) End of interrupts (EOI) is signalled by the TSR to the host. (9) Steps 5 to 8 are repeated until the number of bytes transferred is equal to the number of bytes read from the DMA controller originally thus confirming that the total amount of data desired has been transferred. The DMA controller addressing information is updated as the data is transferred to keep the DMA controller information current. (10) The TSR updates the DMA controller (eg. inserting -1) to signal the end of the DMA operation, or informs the host application that the DMA operation has been completed. A transfer of information from the accessory card to the host can be accomplished in a similar manner, but opposite in direction as follows: (1) The (software) application running in the host 4 sets up the DMA controller using (ie. employing) the current address register of the DMA controller and the page address register of the host 4 with the starting address in memory of where the data is to be written to host memory 2; the maximum amount of data to be transferred using the DMA count register; (2) The host (software) application sends a command to the accessory card to start DMA operation and informing it of the amount of data to be transferred and that the operation to be performed is a write operation; (3) The card responds sending an interrupt to the host activating the TSR ; (4) The TSR reads from the DMA controller the start address, the maximum byte count of data to be transferred and reads from the accessory card the exact amount of data to be transferred and the control information required (in this case, that it is a read instruction). The TSR keeps track of the information read from the DMA controller for subsequent operations. (5) the accessory card interrupts the host for the subsequent transfer of data required; (6) The TSR reads data from the card (for instance from a card buffer or a data port); (7) The TSR writes data to host memory; (8) End of interrupts (EOI) is signalled by the TSR to the host. (9) Steps 5 to 8 are repeated until the number of bytes transferred is equal to the number of bytes read from the DMA controller originally thus confirming that the total amount of data desired has been transferred. The DMA controller addressing information is updated as the data is transferred to keep the DMA controller information current. (10) The TSR updates the DMA controller (eg. inserting -1) to signal the end of the DMA operation, or informs the host application that the DMA operation has been completed. In one implementation of the invention which is preferable, the accessory card contains a data buffer for accumulating data to be transferred to compensate for differences in processing availability or speed of host 4 and the accessory card. For a further understanding of the invention herein reference should be made to the flow diagram of Figure 3 which illustrates a particular mode of the invention as applied to a PCMCIA accessory card, such as that depicted in Figure 2, which incorporates a buffer or trap. The following is a description of the application of a specific embodiment of the invention to a PCMCIA audio card that is depicted in Figure 2, which is adapted to respond to the same instructions used for Soundblaster™ ISA compatible audio cards. Many audio cards on the market emulate the functions of a Soundblaster card and respond to the same instructions. ISA compatible cards are generally capable of use with DMA and software applications using DMA, whereas PCMCIA cards are not; restricting, up until now, the applications they can be used with. The pseudocode depicted and discussed below is a specific embodiment of the invention herein adapted for use with PCMCIA audio cards in accordance with Figure 2 to emulate DMA functions so that a host application calling for Soundblaster (SB hereinafter) audio functions using DMA will operate successfully. In this particular embodiment of the invention, when the host application requires a DMA transfer, it sets up the DMA controller to prepare for DMA data transfer (Step A). The host application initiates a DMA operation by writing to the accessory card 10 (Step B). Upon the host access that indicates a DMA initiation by the host 4, the accessory card traps the information in trap 20 (under control of interface controller 50) and interrupts the host (Step C). On an interrupt to the host, the TSR will be executed and reads the interrupt status register 60 on the accessory card 10 to identify the source of interrupt (Step D). If the source is determined to be a trap of a DMA initiation (Step E), the TSR reads the information from the DMA controller 3 (Step F) and trap 20. The information read from the DMA controller 3 includes the starting memory location of the DMA transfer and the maximum requested size of the block of data in memory to be transferred, as discussed previously. The information from the trap 20 includes the exact size of the data to be transferred and whether it is to be read or write operation. On a data transfer from the host to the card, the TSR reads the block of data from the host memory 2 (Step G) and writes the block of data to internal memory 70 on the accessory card (Step H). The TSR then initiates the internal logic (interface controller 50) on the accessory card to begin data transfer on the accessory card (Step I). The TSR then issues an end of interrupt (Step J) and exits the routine. In this particular example, the accessory card will interrupt the host upon completion of the internal data transfer (Step K). Upon this next interrupt, the TSR will be executed at Step D. If the TSR determines in Step E that the interrupt does not represent a trap, it will query whether the system is in a auto DMA mode. If the system is not in the auto DMA mode (Step L), the TSR updates the DMA controller to signal the completion of the DMA operation (Step M) and issues an end of interrupt to end its execution (Step N). The auto DMA mode is characterized by the immediate restarting of the DMA sequence once it is completed. It is used in sound cards to keep a continuous flow of sound. If the TSR determines in Step L that the system is in auto DMA mode; for a transfer of data from the host 4 to the accessory card, the TSR reads a data block from the host memory 2(Step O) and writes the data block to the internal memory 70 of the accessory card (Step P). It then updates the DMA controller 3 to signal the completion of a DMA cycle (Step Q) and initiates the internal logic (interface controller 50) on the card to begin data transfer on the accessory card (Step R). It then issues an end of interrupt and exits the routine (Step S). In this particular example, the accessory card will interrupt the host upon completion of the internal data transfer (Step K). Upon this next interrupt, the TSR will be executed at Step D. The TSR program embodiment of the invention described below is used to (1) Move data from a host memory 2 to the PCMCIA audio card 10 and (2) to simulate to the host application program (or game) that a true hardware DMA operation actually occurred as requested by the application. The object of DMA emulation, is to allow SB applications to run as if there really were hardware DMA available to them. In this embodiment, DMA emulation is triggered by specific SB commands that are trapped in trap 20 of card 10. DMA emulation in accordance with the invention finds the physical host address of data and length of a transfer, moves data, and simulates DMA progress or completion. This TSR program interfaces with the Intel® 8237 (and follow-on) DMA controllers produced by Intel which are normally used in ISA computers and others. It is assumed that the reader is familiar with the registers and function of these controllers. The TSR program also interfaces with the system page register which is essentially standardized on PC's and ISA computers. Following is the pseudocode used by the TSR software to perform DMA emulation. I Initialization for DMA emulation: Clear the auto-DMA state flag. Invalidate the DMA controller by writing -1 to the current address register. This value is later checked to assure that the DMA controller was actually set prior to the start of a transfer. If it is not, it is assumed that the DMA channel is MASKED at the time the transfer was requested, and the transfer is NOT emulated. II Trigger command that would start a DMA on a SB Audio Card: (this could be a trap of a play-data SB command for example) MASK the DMA controller's channel to stop the channel in case it is running. (for host computers where the DMA default setting is Active.) (a) IF the command is to start an auto-DMA session (the byte length of a transfer BLOCK is passed in command data, and the Maximum allowable number of DMA bytes that can be transferred is stored in the DMA controller's word-count register. The Maximum allowable number of DMA bytes is an integral number of BLOCKS). THEN Set the auto-DMA state flag. Read the DMA controller's word-count register and save it. Read the DMA controller's current-address register and save it. Go to START_DMA ENDIF (b) IF the command is a single byte input transfer (used for card detection in some host computers) THEN CALL GET_DMA_STATE to get the physical address of the input buffer Complement the data byte at the physical address. This simulates an input DMA (from card to host) because the data changed in the input buffer. The game uses this to verify DMA is functioning.Invalidate the DMA controller by writing -1 to the current count register.Simulate End-of-Transfer (terminal count - (TC)) by issuing a single byte block mode physical DMA transfer.Simulate a SB interrupt by calling the SB interrupt chain. This allows the games's end-of-transfer interrupt handler to run. ENDIF the command is a single byte input transfer (used for card detection) (c) IF the command is to start a data output transfer (the byte length of the transfer is passed as command data) THEN START_DMA: CALL GET_DMA_STATE to get the physical address of the input buffer where the application put the data it wants to play eg. host memory 2 Copy the data from the PC buffer AT the physical address FOR the commanded length of the transfer to the card's data-cache if present - or an I/O port.Instruct the DSP or other sound generating device on the audio card to start playing the data, which will result in a (DSP) end-of-transfer interrupt (device dependent). ENDIF the command is to start a data output transfer. III DSP End-Of-Transfer Interrupt handler: (this interrupt is sent whenever the DSP or other sound generating device, for instance, finishes playing all of the sound data that was cached in the data-cache or memory of the card) (a) IF the system is in auto-DMA state THEN Simulate a SB interrupt by calling the SB interrupt chain. This allows the games's end-of-transfer interrupt handler to run.IF the DMA controller's Word-Count is equal to zero THEN UPDATE the physical DMA controller registers as follows: 1) Current-Address = Original DMA address (saved above) 2) Word-Count = Original DMA Word-Count (saved above) ELSE UPDATE the physical DMA controller registers as follows: 1) Current-Address = Current-Address plus auto-DMA command length 2) Word-Count = Word-Count minus auto-DMA BLOCK size ENDIF the Word-Count is equal to zero Go to START_DMA ENDIF the system is in auto-DMA state (b) IF the system is NOT in auto-DMA state THEN (the transfer is completed) Invalidate the DMA controller by writing -1 to the current count register.Simulate End-of-Transfer (terminal count - (TC)) by issuing a single byte block mode physical DMA transfer. (this is useful where DMA is active without an accessory card contacting the DMA control line as is the case in some ISA computer)Simulate a SB interrupt by calling the SB interrupt chain. This allows the games's end-of-transfer interrupt handler to run. ENDIF the system is NOT in auto-DMA state Return from Interrupt. The following subroutine is used in the above pseudocode illustration: IV GET_DMA_STATE subroutine: Read the DMA controller's current address register IF the current address is -1 THEN Flag transfer cannot be done because the controller was never written to, and is assumed to be MASKED. RETURN because of the error condition ENDIF (i) DMA address adjustment: This is used in cases where the DMA controller actually starts running when the game application unmasks it. Some computers default state for DMA-Request is ACTIVE when no real hardware is plugged in to pull the DMA-Request signal to the inactive state. This can have the effect of making the DMA controller free running, whenever it is unmasked. When it starts running, then both the current address and current count registers change, so the following adjustment is applied to try to recover the base address of the DMA requested).IF the DMA controller reached TC (Terminal count (the Maximum of bytes that can be transferred)) (it ran all of the DMA) THEN ADJUST the DMA controller as follows: 1) Current Address = Current Address minus the transfer size that was sent in the SB command. 2) Current Count = Current Count plus the transfer size that was sent in the SB command. ELSE (partial or NO DMA progress made) ADJUST the DMA controller as follows: 1) Current Address = Current Address minus (command transfer size minus DMA's current count register) 2) Current Count = Current Count plus (command transfer size minus DMA's current count register) ENDIF the DMA controller reached TC (it ran all of the DMA) (ii) construct the DMA physical address: Read the DMA controller's current address registerRead the system's page register (this indicates which 64K page of PC memory the DMA controller is pointing to)Construct the physical address (page=segment, current address=offset) Read the DMA controller's current word count registerRETURN with the DMA physical address and the DMA count register END of GET_DMA_STATE subroutine.

Claims: A method of processing data in a computer system comprising a host computer (4) and an accessory data processing device (10) connected to said host computer, the host computer having a central processor (1), a memory (2) and a direct memory access (DMA) controller (3) for controlling transfer of data between the memory and DMA compatible accessory devices in response to a DMA transfer initiation command from an application program running in said host computer, wherein said first mentioned accessory device (10) is not DMA compatible, the method comprising the steps of: trapping said DMA transfer initiation command in a buffer (20) of said non-compatible accessory device; generating in response thereto an interrupt from said non-compatible accessory device to said host computer; in response to said interrupt, starting an emulation program, the emulation program controlling said commanded transfer of data between said non-DMA compatible accessory device and the host computer memory and concurrently simulating to said host computer and DMA controller the signals which would be expected from a DMA compatible accessory device if it were participating in said data transfer; said data transfer step comprising: determining the location in said host memory for data to be transferred from said host memory to said non-DMA compatible accessory device or from said accessory device to said host memory; and for a data transfer from host memory to said accessory device, reading data from said host memory and writing it to said accessory device (10); or for a data transfer from accessory device to host memory, reading data from said accessory device and writing it to said host memory, respectively; and said simulating step comprises informing said host computer that a DMA operation corresponding to said data transfer has been completed. The method of claim 1 in which said location in said host memory is determined by reading memory address information from said DMA controller including reading the starting address of the location in host memory for said data and the maximum amount of data to be transferred. The method of claim 2 in which the memory address information in said DMA controller is updated as data is transferred between host and accessory device to maintain the currency of said DMA controller information corresponding to information that would be present if an actual DMA access of said memory had taken place. The method of either claim 2 or claim 3 in which the information in said DMA controller is updated to indicate the end of a DMA operation when said data transfer has been completed. The method of any one of claims 2 to 4 in which the determination of said starting address includes calculating an address compensation factor for determining the correct starting address if said DMA controller of said host free runs when it is unmasked. The method of any preceding claim including the further step that the emulation program analyses interrupts from said accessory device to determine whether they are DMA transfer initiation commands before controlling said commanded transfer. The method of claim 6 in which said transfer of data takes place in blocks, one block at a time, each block transfer being followed by a further interrupt from said accessory device to said host computer, the emulation program, upon determining that said interrupt is not a DMA transfer initiation command, controlling the transfer of the next block of data. A host computer system (4) comprising: a central processor (1); a memory (2); a direct memory access (DMA) controller (3) for controlling transfer of data between the memory and a DMA compatible accessory data processing device in response to a DMA transfer initiation command from an application program running in said host computer system, said host system being capable of receiving a non-DMA compatible accessory data processing device arranged to generate an interrupt to said host system upon receipt of a DMA transfer initiation command; an emulation computer program; and means for starting said emulation program in response to such an interrupt from a non-DMA compatible accessory device; the emulation program comprising: means for controlling said commanded transfer of data between said non-compatible accessory device and said memory and means for simulating to said host computer and said DMA controller, concurrently with said transfer, the signals which would be expected from a DMA-compatible device if it were participating in said data transfer; said means for controlling said commanded transfer including: means for determining the location in said memory for data to be transferred from said memory to said non-DMA compatible accessory device or from said accessory device to said host memory; and means for reading data from said memory at the address specified in said DMA controller for said data and for writing said data to said accessory device and for reading data from said accessory device and writing it to said memory at the address specified by said DMA controller, respectively; and said simulating means including means for informing said host computer that a DMA operation corresponding to said data transfer has been completed. A system as claimed in claim 8 in which said means for determining the location in said memory does so by reading memory address information from said DMA controller comprising means for reading the starting address of the location in memory for said data and the maximum amount of data to be transferred. A system as claimed in either claim 8 or claim 9 in which said emulation process includes means for updating said memory address information in said DMA controller as data is transferred between host and accessory to maintain the currency of said DMA controller information corresponding to information that would be present if an actual DMA access of said memory had taken place. A system as claimed in any one of claims 8 to 10 in which said emulation program further includes means for updating information in said DMA controller to indicate the end of a simulated DMA operation when said data transfer has been completed. A system as claimed in claim 9 in which said means for the determination of said starting address includes means for calculating an address compensation factor for determining the correct starting address if said DMA controller of said host free runs when it is unmasked. A system as claimed in any one of claims 8 to 12 in which the emulation program includes means for analyzing the interrupts from said accessory device to determine whether they are DMA transfer initiation commands before controlling said commanded transfer. A system as claimed in any one of claims 8 to 13 which is capable of receiving a non-DMA compatible accessory data processing device lacking DMA request and DMA acknowledge connections. A system as claimed in claim 14 which is capable of receiving a PCMCIA device. A computer program to be run on a host computer system (4) which system comprises a control processor (1), a memory (2) and a direct memory access controller (3) for controlling transfer of data between the memory and a DMA compatible accessory data processing device in response to a DMA transfer initiation command from an application program running in said host computer system, said host system being capable of receiving a non-DMA compatible accessory data processing device arranged to generate an interrupt to said host system upon receipt of a DMA transfer initiation command, said program being started in response to such an interrupt from a non-DMA compatible accessory device; wherein said program comprises: means for controlling said commanded transfer of data between said non-compatible accessory device and said memory and means for simulating to said host computer and said DMA controller, concurrently with said transfer, the signals which would be expected from a DMA-compatible device if it were participating in said data transfer; said means for controlling said commanded transfer including means for determining the location in said memory for data to be transferred from said memory to said non-DMA compatible accessory device or from said accessory device to said host memory; and means for reading data from said memory at the address specified in said DMA controller for said data and for writing said data to said accessory device and for reading data from said accessory device and writing it to said memory at the address specified by said DMA controller, respectively; and said simulating means including means for informing said host computer that a DMA operation corresponding to said data transfer has been completed.

Inventors: DEVINS ROBERT J, HON STEPHEN, KAM PATRICK, KELLER EMORY D, DEVINS, ROBERT J., HON, STEPHEN, KAM, PATRICK, KELLER, EMORY D.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1995
Main classification: G06F13
IPC codes: G06F13, G06F9