Charge pump circuit with improved features

Abstract: A charge pump circuit (100) comprising a plurality of voltage boost stages (20 i ) that are mutually parallel-connected between a supply line (21) and an output line (22), wherein each one of the stages comprises first (25 i ) and second (28 i ) charge storage means in which, respectively, a first terminal is connected to a charge and discharge node (31 i , 29 i ) and a second terminal is connected to a boost node (27 i , 27 i+1 ) to switch between a first charge step and a second step for transferring the charge to the output line (22); an inverter (23 i ), in which an input node is connected to the boost node (27 i ) related to the first charge storage means (25 i ) and an output node is connected to the boost node (27 i+1 ) related to the second charge storage means (28 i ); a first charge transfer diode (30 i ), which is connected between the charge and discharge node (31 i ) related to the first charge storage means (25 i ) and the output line (22); a second charge transfer diode (32 i ), which is connected between the charge and discharge node (29 i ) related to the second charge storage means (28 i ) and the output line (22); the circuit having the particularity that each one of the stages (20 i ) comprises an additional diode (35 i ) that is connected between the charge and discharge node (31 i ) related to the first charge storage means (25 i ) and the output line (22), the additional diode discharging the first charge storage means when the potential of the output line is lower than the potential, minus the threshold of the additional diode, of the charge and discharge node related to the first charge storage means.

Description: The present invention relates to a charge pump circuit with improved features. Charge pump circuits for generating a voltage of a given level (known as boost voltage) starting from a supply voltage that is at a lower level in order to supply a load arranged downstream of the charge pump circuit and requiring a supply voltage higher than the one directly available from the supply line, are known in the art. Charge pump circuits are based on the principle of alternating two separate steps: the first one includes charging a capacitor, and the second one includes raising the level of one terminal of the capacitor and connecting the other terminal to an output to achieve a voltage level that is higher than the power supply. A first solution, aimed at achieving a boost voltage higher than the supply voltage, is shown in figure 1, which illustrates the complete charge pump circuit, constituted by a plurality of identical stages that are shown in detail in figure 2. Figure 1 thus shows the parallel connection of an odd number of voltage boost stages, designated by the reference numeral 2 i , between a power supply line 1 and a voltage boost line 9. Each stage shown in figure 2 comprises: a boost capacitor 3, in which the terminals form a first node 4 and a second node 5; an output diode 6, interposed between the second node 5 and the boost line 7; a charge transistor 8, interposed between the supply line 1 and the second node 5; a biasing diode 9, interposed between the supply line 1 and a node 10 formed by the gate terminal of the charge transistor 8; and an inverter 11, interposed between nodes 4 of two adjacent stages 2 i , except for the last stage, which is formed by a branch comprising an AND gate 12 followed by a NOR gate 13. The inverters 11 and the NOR circuit 13 constitute a loop oscillator with an odd number of inversion cycles. The above described charge pump circuit, of the type known as "single-stage", has the purpose of raising the voltage on the boost line 7 to a value that is twice the supply voltage V DD minus a threshold value V T caused by the drop across the diodes 6; in other words, a voltage equal to 2V DD -V T is obtained. This value is purely theoretical, that is to say, it can be attained asymptotically in maximum efficiency conditions and if no current is absorbed. If a steady-state voltage value varying between 4.5 and 5 volts is required starting from a supply voltage of 3 volts, and if the capacitance of the load to be driven has a modest value, the behavior of a "single-stage" pump is fully sufficient for the purpose. On the contrary, if the capacitances downstream of the pump circuit are high, for example in the case of large memories (16-megabit memories with hierarchical decoders), and if high current consumptions occur, the asymptotic level that is possible with a "single-stage" pump can no longer be attained, or long time periods are required to attain it. Furthermore, with a pump of this type it is necessary to use capacitors having a very large value to allow the pump to deliver the required current. Efficient transfer of charge to the boost line in fact occurs if the capacitance values of the circuit are greater than the capacitance value connected to the boost line: since this last capacitance value is already intrinsically high, this means that the capacitance values of the pump circuit must be even higher, with a consequent increase in parasitic effects, in network size, and in consumption. It should also be noted that since the maximum value that can be reached in theory by the voltage with a single-stage pump is 2V DD -V T , it is evident that when dealing with supply voltages on the order of 3 V, the loss of a threshold voltage (approximately 1 V) on a 3 V value is significant. Accordingly, there is an interest in recovering the threshold voltage lost due to the drop across the diode 6. One solution to the above mentioned problems might be the use of a so-called "two-stage" pump, in which the attainable asymptotic voltage value is 3V DD -2V T . A general diagram of such a pump is shown in figure 3, whereas figure 4 is a detail view of a single stage of the pump of figure 3. The same reference numerals used in figures 1 and 2 are used, for identical components, in figures 3 and 4, and said components are not described further. The difference between the stage shown in figure 4 and the stage of figure 2 resides in the presence of a first charge transfer diode 14 and of a second charge transfer diode 15. Reference is made to EP-A-0666571 for a detailed description of the pump circuit of figure 1 and of the pump circuit of figure 3. The voltage produced by the latter circuit is 3V DD -2V T . The drawback of a circuit of this so-called "two-stage" type is the fact that although it assuredly attains a higher voltage level than the pump shown in figure 1 (in which the asymptotic value is 2V DD -V T ) and is more efficient at that level, it has a higher overall impedance. Indeed, by increasing the number of stages, the voltage increases due to the contribution of each stage, but at the same time there is a power loss too, that is to say, it is no longer possible to generate the same current. If one seeks to raise the voltage but at the same time to drive considerable loads, this solution is not adapted, since the circuit is unable to deliver high maximum current values. Therefore there is a disadvantage in the initial step, since the boosting of the boost line is slowed down, and there is a disadvantage in the long term, since the circuit is unable to deliver the required current although it achieves the desired voltage. The principal aim of the present invention is therefore to provide a charge pump circuit that overcomes the drawbacks mentioned above, allowing to continuously achieve a high voltage level (boost voltage) in a short time and with maximum efficiency. Within the scope of this aim, an object of the present invention is to provide a charge pump circuit that allows to deliver maximum power during startup and in the initial step. Another object of the present invention is to provide a charge pump circuit that is more efficient from the point of view of overall impedance and therefore has a better current delivery capability. Another object of the present invention is to provide a charge pump circuit having a low capacitance with respect to known solutions. Another object of the present invention is to provide a charge pump circuit usable to drive large loads that require considerable current absorption. Another object of the present invention is to provide a charge pump circuit that is highly reliable and relatively easy to manufacture at competitive costs. This aim, these objects, and others which will become apparent hereinafter are achieved by a charge pump circuit that comprises a plurality of voltage boost stages that are mutually parallel-connected between a supply line and an output line, wherein each one of said stages comprises: first and second charge storage means in which, respectively, a first terminal is connected to a charge and discharge node and a second terminal is connected to a boost node to switch between a first charge step and a second step for transferring said charge to said output line; an inverter, in which an input node is connected to the boost node that is related to said first charge storage means and an output node is connected to the boost node that is related to said second charge storage means; a first charge transfer diode, which is connected between said charge and discharge node related to said first charge storage means and the charge and discharge node (29i) related to the second charge storage means (28i); a second charge transfer diode, which is connected between said charge and discharge node related to said second charge storage means and said output line; characterized in that each one of said stages comprises an additional diode connected between said charge and discharge node related to said first charge storage means and said output line, said additional diode discharging said first charge storage means when the potential of said output line is lower than the potential, minus the threshold of said additional diode, of said charge and discharge node related to said first charge storage means. Further characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the circuit according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a circuit diagram of a charge pump circuit with a plurality of stages of a first known type; figure 2 is a detail circuit diagram of one of the stages of the charge pump shown in figure 1; figure 3 is a circuit diagram of a second known type of multiple-stage charge pump circuit; figure 4 is a detail view of the circuit diagram of one of the stages of the charge pump shown in figure 3; figure 5 is a circuit diagram of a charge pump circuit according to the invention; figure 6 is a detail view of the circuit diagram of one of the stages of the charge pump circuit according to the invention, shown in figure 5; figure 7 is a chart comparing the voltage levels obtainable with a known single-stage charge pump circuit and with a pump circuit according to the invention, shown respectively in figures 1 and 5; figure 8 is a chart comparing the voltage levels obtainable with the known circuit solutions of figures 1 and 3 and with the charge pump according to the invention; and figure 9 is a chart comparing the current level that can be produced as a function of time by the two known charge pump circuits of figures 1 and 3 and by the charge pump circuit according to the invention. Figures 1-4 are diagrams of two known and previously described solutions of a charge pump circuit. With reference to figures 5 and 6, the charge pump circuit according to the invention, generally designated by the reference numeral 100, comprises a series of stages 20 1 , 20 2 ,... 20 n (where n is an odd number) that are mutually parallel-connected between a supply line 21 at the voltage V DD and an output line 22 (boost line); a loop oscillator, constituted by a plurality of mutually identical inverters 23 and by a flip-flop circuit 24, is connected to said output line. A capacitor 200 is connected to the boost line 22 and indicates the capacitive load to be driven by means of the charge pump circuit 100. The configuration of a stage 20 i is shown in detail in figure 6. The stage 20 i comprises first change storage means, advantageously constituted by a bootstrap capacitor 25 i , the terminals whereof constitute a first node 31 i and a second node 27 i . Each inverter 23 i is connected between an input node, which corresponds to the second node 27 i , and an output node 27 i+1 . The output node 27 i+1 coincides with the input node of the inverter 23 i+1 of a successive stage, whereas the input node 27 i coincides with the output node of the inverter 23 i-1 of a preceding stage. Second charge storage means, which advantageously comprise a second capacitor 28 i , have a first terminal connected between the output node 27 i+1 and a second terminal forming a node 29 i . A first charge transfer diode 30 i is connected between the nodes 31 i and 29 i . A second charge transfer diode 32 i is connected between the node 40 i and the node 41 i on the boost line 22. Advantageously, the first diode 30 i and the second diode 32 i include native N-channel MOS transistors, that is to say, transistors having a low threshold and in which the drain and gate terminals are shorted together. A third biasing diode 33 i , conveniently constituted by a native N-channel MOS transistor, has its drain terminal connected to the supply line 21 and its source terminal connected to the gate terminal of the first transistor 30 i . A fourth biasing diode 34 i , advantageously constituted by a native N-channel MOS transistor, has its drain terminal connected to the supply line 21 and its source terminal connected to the circuit branch that includes the node 29 i , the capacitor 28 i , and the node 27 i+1 . The gate terminal of the transistor 32 i is connected to the above mentioned circuit branch and therefore to the source terminal of the transistor 34 i . The gate terminals of the transistors 33 i and 34 i are connected to each other and to the supply line 21. A fifth transistor 35 i is connected, by means of its gate terminal, to the circuit branch that connects the node 27 i to the node 31 i , forming a node 26 i . The source terminal of the transistor 35 i is connected to the boost line 22, whereas its drain terminal is connected to the source terminal of the transistor 33 i . The transistor 35 i is also advantageously provided as a native N-channel MOS transistor. A sixth transistor 36 i is connected to the supply line 21 by means of its drain terminal and to the supply line 21, at the voltage V DD , by means of its source terminal. A node 37 i is formed between the source terminal of the transistor 34 i and the node 29 i , and the gate terminal of a transistor 36 i+1 belonging to a successive stage 20 i+1 is connected to said node 37 i . Likewise, the gate terminal of the transistor 36 i is connected to a node 37 i-1 belonging to a preceding stage 20 i-1 . Figure 5 shows the parallel connection of an odd number of stages 20 i and the connection of the last stage 20 n , in which the source terminal of the transistor 34 n is connected to the gate terminal of the transistor 36 2 of the second stage 20 2 . The source terminal of the transistor 34 n-1 belonging to the penultimate stage 20 n-1 is instead connected to the gate terminal of the transistor 36 1 belonging to the first stage 20 1 . Likewise, the source terminal of the transistor 34 i of a generic stage 20 i is instead connected to the gate terminal of the transistor 36 i+2 of a stage 20 i+2 . The mutually connected gate terminals of the transistors 33 i and 34 i are connected, for each stage, to a control line 40 for enabling the pump circuit. Said line 40 allows to disconnect the transistors 33 i and 34 i from the power supply V DD if one wishes to leave the level of the boost line 22 unchanged, so as to then set the boost line to the ground level if required. The output node 27 i+1 of the penultimate stage 20 n-1 is connected, by means of a line 41, to the gate terminal of a transistor 43 belonging to a first pair of transistors 42 and 43 that are included in the flip-flop 24. The output node 27 i+1 of the last stage 20 n is instead connected, by means of a line 46, to the gate terminal of a transistor 45 belonging to a second pair of transistors 44 and 45. As regards the first pair of transistors, the gate terminal of the transistor 42 is connected to a line 60 for regulating the pump circuit 100 and the source terminal of said transistor is connected to the drain terminal of the transistor 43. The source terminal of the transistor 43 is connected to the ground and the drain terminal of the transistor 42 is connected to a node 47 of a latch circuit 50. Said flip-flop circuit 24 has the purpose of interrupting the operation of the charge pump circuit, freezing the last propagation that is occurring in the loop oscillator constituted by the inverters 23 i . As regards the second pair of transistors 44 and 45, the gate terminal of the transistor 44 is connected to the regulator line 60 of the pump circuit 100, the drain terminal of said transistor is connected to the source terminal of the transistor 44, and the source terminal is connected to the ground. The drain terminal of the transistor 44 is instead connected to a circuit branch connecting a second node 48 of the latch circuit 24 to the input node of an inverter 23, the output whereof is connected to the input node 27 1 of the first stage 20 1 of the charge pump circuit 100. Advantageously, the latch circuit comprises two pairs of MOS transistors. The first pair is formed by transistors 51 and 52, and the second pair is formed by transistors 53 and 54. The gate terminal of the transistor 53 is connected to the gate terminal of the transistor 54, and both gates are connected to the node 47. The gate terminal of the transistor 51 is connected to the gate terminal of the transistor 52, and both are connected to the node 48. The drain terminals of the transistors 51 and 53 are connected to the supply voltage V DD ; the source terminals of said transistors 51 and 53 are respectively connected to the drain terminals of the transistors 52 and 54; finally, the source terminals of the transistors 52 and 54 are connected to the ground. With reference to figures 5 and 6, the operation of the charge pump circuit 100 according to the invention is as follows. Assume that a generic node 27 i is low; in this case, the capacitor 25 i begins to be precharged at the supply voltage V DD by means of the transistor 36 i , which has, from the preceding stage 27 i-1 , a voltage higher than V DD at its gate terminal, thus allowing the node 29 i to be connected to the supply V DD by means of the transistor 36 i . Then, when the node 27 i goes high, a further boosting by a voltage V DD occurs and the node 31 i reaches the level 2V DD . The capacitor 25 i could therefore transfer onto the boost line 22 a charge equal to 2V DD -V T , that is to say, a charge reduced by a threshold voltage V T of the transistor 35 i if the level of the line 22 is lower than 2V DD -V T . If the level present on the boost line is sufficiently lower than 2V DD -V T , then the capacitor 25 i discharges onto said boost line 22. Instead, when the level of the boost line approximates or equals the charge level 2V DD -V T , the charge of the node 31 i discharges onto the node 40 i (whose maximum possible level in this step is V DD ), which thus has the same charge as the node 29 i . The step for the discharge of the capacitor 25 i is followed by the step for precharging the capacitor 28 i when the nodes 27 i+1 go low. A voltage boost of one V DD is thus supplied to the node 29 i by means of the transistor 34 i . The node 29 i is thus charged at 3V DD -V T and discharges onto the boost line 22, minus a threshold V T determined by the transistor 32 i . The transfer of a charge equal to 3V DD -2V T onto the boost line has thus been achieved. This sequence of steps is repeated for each stage 20 i of the loop oscillator. As long as the value of the boost line is sufficiently lower than 2V DD -V T , the pump circuit behaves like a single-stage pump, transferring charge to the boost line 22. Instead, when the level reached by said boost line is too high for further charge transfer to occur, that is to say, when a balance is reached, then it is not necessary to wait for discharge to continue transferring charges, but the second section of the stage 20 i of the pump circuit automatically becomes active and behaves, in this step, like a two-stage pump and is able to transfer charges to the boost line 22 by virtue of the higher voltage difference (3V DD -2V T ). This "two-stage" behavior thus engages after the "single-stage" behavior of the pump circuit in a gradual and progressive manner, until it becomes exclusively of the two-stage type only if the desired level is greater than, or equal to, 2V DD -V T . If the output node of the inverter 23 n of the last stage 20 n has a low value (0), this value is transmitted over the line 46, is inverted by the two transistors 44 and 45, and is inverted again by the inverter 23; therefore, a high value (1) is present at the node 27 1 in the subsequent cycle. During this step, a 0 is present at the gate terminal of the transistor 43 and the transistors 42 and 43 are off. Instead, when a 1 is present on the line 41, the transistors 42 and 43 are on and the transistors 44 and 45 are off. The advantage of using a flip-flop configuration of this type with respect to the circuit with an AND gate 12 and a NOR gate 13 of the known embodiments of figures 1 and 3 is due to the following reason. Assume that the output of the AND gate 12 is a low signal (0) and that the SYNC signal is low (0); in this case, a high signal (1) is present in output from the NOR gate 13 and therefore the first node 27 1 of the charge pump circuit is high (1) and another high level (1) is present at the output node of the last stage 20 n and is inverted by the NOR gate 13; therefore, a low level (0) will be present at the subsequent cycle on the first node 4 1 of the pump circuit and will begin to propagate, with its inversion cycles, by means of the inverters 23 i . At this point, assume that the output signal from the AND gate 12 goes low and that therefore the output signal from the NOR gate 13 becomes suddenly high. Since the nodes 4 i of the pump circuits of figures 1 and 3 correspond to the nodes 27 i of the circuit according to the invention, this last reference numeral is used for the sake of simplicity. Therefore, it might occur that while the signal has not yet reached the output node of the last stage, that is to say, the inversion cycle has not completed yet, a new inversion cycle may overlap on said cycle that has already begun, leading to a non-synchronized effect. With the solution of the flip-flop 24 adopted in the circuit according to the invention, this drawback is eliminated, since the flip-flop 24 interrupts the operation of the pump, freezing the last propagation that is occurring in the loop oscillator. The chart of figure 7 plots a comparison between the asymptotic value 2V DD -V T that can be attained with a single-stage pump (curve e) and the oscillating behavior of the nodes 27 i , 31 i , and 40 i , showing the asymptotic value that can be attained in theory by the pump according to the invention (curve d). The letter l designates the regular oscillation performed by the node 27 i which, starting from zero, reaches V DD at the most; the letter m designates the oscillation of the node 31 i , which starts from the level V DD and reaches at the most the level 2V DD ; and the letter n designates the oscillation of the node 40 i . The chart clearly shows that initially, during startup, starting from the voltage V DD , the two curves d and e tend to overlap and to be identical; then the curve d prevails, and its value tends to 3V DD -2V T . Figure 8 is instead a chart that compares the voltage levels, as a function of time, obtainable with the pump configurations of the single-stage type, of the two-stage type, and according to the invention. The curve designated by (a) relates to the behavior of a single-stage pump, in which the attainable asymptotic voltage value is 2V DD -V T ; curve (b) relates to the behavior of a two-stage pump, in which the attainable asymptotic value is 3V DD -2V T ; and curve (c) plots the voltage level that can be attained by a pump circuit according to the invention. The chart clearly shows that during startup, curve (a) lies above curve (b) and practically coincides with curve (c); this shows that the single-stage pump is initially more efficient than the two-stage pump. Then, after a certain time, the behavior of curve (b) prevails and tends to reach a higher asymptotic level than curve (a). The trend of curve (c) is instead always higher than curves (a) and (b), although it then tends asymptotically towards the same value as curve (b). It is thus evident that the pump circuit according to the invention, during startup, behaves like a single-stage pump and then becomes a two-stage pump, but with an efficiency that is always higher than that of a conventional two-stage pump. Figure 9 is a chart that compares the current levels obtainable, as a function of time, by the two known types of charge pump circuit and by the circuit according to the invention. In this chart, curve (f) relates to the current obtainable from a charge pump circuit of the "single-stage" type and therefore with high startup efficiency (high deliverable current) and with a sudden decrease in efficiency after a short period of time. Curve (h) shows the behavior of a "two-stage" charge pump circuit, with low initial efficiency due to the high impedance and with a later improvement (curve h passes above curve f). Finally, curve (g) plots the behavior of the circuit according to the invention, in which there is a high startup current value (equal to the curve f) and then there is a subsequent value that is in an intermediate position between curve (f) and curve (h). The apparent reduction in the current delivered by the pump circuit according to the invention (curve f) with respect to the two-stage pump (curve h) should not mislead, since this is due to the fact that the level attained, after an equal time, by the pump according to the invention is higher than the level reached by the two-stage pump and therefore the ability to deliver current decreases. Every pump in fact stops delivering current when it theoretically reaches its asymptotic level. Since one wishes to obtain a voltage of 4-4.5 volts starting from a supply voltage V DD equal to 2.7-3V, it is necessary to use a regulator to limit the voltage reached by the boost line. For this purpose, a regulator (not shown) is connected to the regulation line 60, so as to pump charges on the boost line, if required, and stop the charge pump circuit 100 when the desired voltage level is reached. In practice it has been observed that the charge pump circuit according to the invention fully achieves the intended aim, since it allows to provide a voltage multiplier of the type with dual behavior, initially of the "single-stage" type, with an attainable asymptotic voltage level equal to 2V DD -V T , and then of the "two-stage" type, with an attainable asymptotic voltage level equal to 3V DD -2V T . This behavior of the charge pump circuit has the advantage that during the initial part, that is to say at startup, the circuit behaves like a single-stage pump, and therefore has a low impedance, allowing to quickly reach a relatively high voltage level. Then, when in theory the discharge step would end due to the rise in the voltage level of the boost line, the pump gradually becomes a two-stage pump, so as to therefore maintain good efficiency in a step in which the single-stage pump would be ineffective. Therefore, an additional advantage of the pump circuit according to the invention is provided by the fact that the impedance remains constantly lower than in the single-stage solution and in the two-stage solution, allowing to deliver a higher current value than the single-stage case. Another important advantage arises from the possibility of restoring the desired voltage level if a load connected to the boost line absorbs current; the charge pump circuit according to the invention therefore allows to maintain the desired level, furthermore providing the ability to deliver current. The improved performance of the charge pump circuit allows to give smaller sizes and values to the capacitors of the circuit. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: Charge pump circuit (100), comprising a plurality of voltage boost stages (20i) that are mutually parallel-connected between a supply line (21) and an output line (22), wherein each one of said stages comprises: first (25i) and second (28i) charge storage means in which, respectively, a first terminal is connected to a charge and discharge node (31i,29i) and a second terminal is connected to a boost node (27i,27i+1) to switch between a first charge step and a second step for transferring the charge to said output line (22); an inverter (23i), in which an input node is connected to the boost node (27i) related to said first charge storage means (25i) and an output node is connected to the boost node (27i+1) related to said second charge storage means (28i); a first charge transfer diode (30i), which is connected between said charge and discharge node (31i) related to said first charge storage means (25i) and the charge and discharge node (29i) related to the second charge storage means (28i); a second charge transfer diode (32i), which is connected between said charge and discharge node (29i) related to said second charge storage means (28i) and said output line; characterized in that each one of said stages (20i) comprises an additional diode (35i) that is connected between said charge and discharge node (31i) related to said first charge storage means (25i) and said output line (22), said additional diode (35i) discharging said first charge storage means (25i) when the potential of said output line (22) is lower than the potential, minus the threshold of said additional diode (35i), of said charge and discharge node (31i) related to said first charge storage means (25i). Circuit (100) according to claim 1, characterized in that it comprises a third biasing diode (33i) interposed between said supply line (21) and said first charge transfer diode (30i). Circuit (100) according to claim 1, characterized in that it comprises a fourth biasing diode (34i) interposed between said supply line (21) and said charge and discharge node (29i) related to said second charge storage means (28i). Circuit (100) according to claim 1, characterized in that it comprises a sixth transistor (36i) connected between said supply line (21) and said charge and discharge node (31i) related to said first charge storage means (25i), said sixth transistor being of the N-channel MOS low-threshold type. Circuit (100) according to claim 1, characterized in that said additional diode (35i) comprises an N-channel MOS low-threshold transistor in which the drain terminal is connected to the source terminal of said third biasing diode (33i). Circuit according to claim 1, characterized in that said first, second, third, and fourth diodes comprise N-channel MOS low-threshold transistors. Circuit according to claims 1, 2, and 3, characterized in that the gate terminals of said third and fourth diodes are connected to an enabling control line. Circuit according to claims 1, 3, and 4, characterized in that the source terminal of said fourth diode of an even-numbered stage in said pump circuit is connected to the gate terminal of said sixth transistor that belongs to a stage that is also even-numbered. Circuit according to claims 1, 3, and 4, characterized in that the source terminal of said fourth diode of an odd-numbered stage in said pump circuit is connected to the gate terminal of said sixth transistor that belongs to a stage that is also odd-numbered. Circuit according to claim 1, characterized in that the output node of the inverter of the penultimate stage of said pump circuit is connected to the gate terminal of a transistor of a first pair of transistors, the source terminal of said transistor being connected to the ground, the gate terminal of the other transistor of said first pair of transistors receiving, in input, a signal for regulating said pump circuit, its drain terminal being connected to a first node of a latch circuit. Circuit according to claims 1 and 10, characterized in that the output node of the inverter of the last stage of said pump circuit is connected to the gate terminal of a transistor of a second pair of transistors, the source terminal of said transistor being connected to the ground, the gate terminal of the other transistor of said second pair of transistors receiving, in input, said signal for the regulation of said pump circuit, its drain terminal being connected to a second node of said latch circuit and to an inverter, in which the output node is connected to the input node of the inverter of the first stage of said latch circuit. Circuit according to claims 10 and 11, characterized in that said first and second pairs of transistors and said latch circuit constitute a flip-flop circuit. Circuit according to claim 1, characterized in that said first and second charge storage means respectively comprise a capacitor. Circuit according to one or more of the preceding claims, characterized in that said inverters and said flip-flop circuit constitute a loop oscillator with an odd number of inverting cycles.

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: G05F1
IPC codes: G05F3, H02M3