Integrated electronic device with reduced parasitic currents, and corresponding method

Abstract: The present invention relates to an electronic device integrated monolithically on a semiconductor material comprising a substrate (1) having a first conductivity type in which are formed a first (2) and second diffusion regions (3) of a second conductivity type with said substrate (1) and said first (2) and second (3) diffusion regions including respectively a base region, a collector region and an emitter region of a transistor (Tp1) and characterized in that in the second diffusion region (3) is formed a third diffusion region (8) having conductivity of the first type to provide in said second diffusion region (3) a resistive path (R) placed in series with the emitter region of the transistor (Tp1) while backfeeding it negatively and taking it to saturation with a resulting reduction of its current gain and limitation of the maximum current due thereto.

Description: The present invention relates to an integrated electronic device with reduced parasitic currents. The present invention also relates to a method for reduction of parasitic currents in an integrated electronic device. Field of application The field of application of the present invention concerns in particular but not exclusively integrated electronic devices in Vertical Integrated Power technology and the following description is made with reference to this field of application with the only purpose of simplifying the discussion. As known, when in an integrated device there are included a first and second semiconductor regions having a first type of conductivity, facing each other and separated by a third semiconductor region having a second type of conductivity, there can be created a parasite transistor whose entry into conduction depends on the electrical potentials applied to the device. Turning on this parasite transistor causes an undesired current flow between the first and second semiconductor regions. With reference to FIG. 1 the symbol IC indicates an integrated electronic device comprising a substrate 1 of semiconductor material having a first type of conductivity and in particular type N- in which are formed a first 2 and second 3 diffusion regions having a second type of conductivity and in particular type P. In the second diffusion region 3 is also incorporated a third diffusion region 9 having conductivity of the first type and in particular type N. Again with reference to FIG. 1 it is seen that in the substrate 1 and in the second 3 and third 9 diffusion regions are included respectively a collector region, a base region and an emitter region of an NPN power transistor POWER. The first diffusion region 2 includes a control circuitry for the above mentioned power transistor. In the substrate 1 and in the first 2 and second 3 diffusion regions are also incorporated respectively a base region, a collector region and an emitter region of a PNP parasite transistor Tp1. Generally the turning on this parasite transistor Tp1 appears during the conduction phase of the power transistor POWER when e.g. the base region of the above mentioned power transistor is at a potential of approximately 1V. If the power transistor POWER saturates, the junction formed by its base and collector regions is directly polarized. This causes turning on the parasite transistor Tp1 which extracts current from the base region of the power transistor POWER to inject it into the first diffusion region 2 containing the control circuitry, which is typically connected to ground. In this manner the power transistor POWER desaturates. At present numerous solutions are adopted to neutralize the negative effects of turning on the parasite transistor Tp1. A first prior art solution to meet this requirement is shown in FIG. 2 and calls for provision in a portion 16 of the substrate 1 included between the first 2 and the second 3 diffusion regions of a fourth diffusion region 4 having conductivity of the first type and in particular type N++. The presence of this fourth diffusion region 4 causes the substrate 1 to be considerably doped on the surface with resulting decrease in current gain of the parasite transistor Tp1. Although advantageous in some ways this first prior art solution exhibits the shortcoming that the diffusion region 4 is shallow. Consequently the current gain of the parasite transistor Tp1 is reduced only near the surface of the substrate 1 while in depth it remains unchanged. In addition, the presence of the diffusion region 4 causes both a withdrawal between the first 2 and second 3 diffusion regions with resulting increase in the area occupied by the integrated device IC and the requirement to provide in the above mentioned device an edge structure to withstand a high voltage which is created on the surface of the substrate 1. In FIG. 3 is shown a second prior art solution calling for provision in the portion 16 of the substrate 1 of a fourth diffusion region 5 having second type and specifically P conductivity. This leads to a splitting of the parasite transistor Tpl into two parasite transistors Tp1' and Tp1" as shown in FIG. 3. Now with reference to FIG. 4 showing a portion of an equivalent circuit structure of the integrated device IC shown in FIG. 3 it is seen that the overall current gain of this structure defined as the ratio of a current injected in the base region of the power transistor POWER to a parasitic current flowing towards the first diffusion region 2 is reduced because the parasite transistor Tp1" is forced to saturate. Although it meets the purpose, this second solution is not free of shortcomings either. Indeed, it exhibits the disadvantage of considerably increasing the area occupied by the integrated device IC. Lastly, FIG. 5 shows a third prior art solution calling for formation in the portion 16 of the substrate 1 of a fifth diffusion region 6 having first-type conductivity and specifically type N and placed near the fourth diffusion region 5. Again in this case there is splitting of the parasite transistor Tp1 into two parasite transistors Tp1' and Tp1" as shown in FIGS. 5 and 6. The parasite transistor Tp1' which is directly interfaced with the first diffusion region 2 is always off because its base-emitter junction is short-circuited. In this case there is complete suppression of the parasite transistor Tp1. Even this third solution however exhibits the shortcoming of considerably increasing the area occupied by the integrated device IC. In addition, near the surface of the substrate 1 there is created a high voltage requiring provision between the power transistor POWER and the first diffusion region 2 of an edge structure. The technical problem underlying the present invention is to provide an integrated electronic device having reduced parasitic currents and having structural and functional characteristics overcoming the limitation and/or shortcomings indicated above with reference to the prior art. The technical problem is solved by a device of the type indicated above and defined in the characterizing part of the annexed claims. The characteristics and advantages of the device in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of non-limiting example with reference to the annexed drawings. In the drawings: FIG. 1 shows in enlarged scale and vertical cross section a diagrammatic view of a generic integrated electronic device, FIG. 2 shows in enlarged scale and vertical cross section a first embodiment in accordance with the prior art of an integrated electronic device having reduced parasitic currents, FIG. 3 shows in enlarged scale and vertical cross section another embodiment in accordance with the prior art of the integrated electronic device having reduced parasitic currents, FIG. 4 shows a portion of a possible circuit diagram of the integrated electronic device shown in FIG. 3, FIG. 5 shows in enlarged scale and vertical cross section a third embodiment in accordance with the prior art of the integrated electronic device having reduced parasitic currents, FIG. 6 shows a portion of a possible circuit diagram of the integrated electronic device shown in FIG. 5, FIG. 7 shows in enlarged scale and vertical cross section a simplified embodiment in accordance with the present invention of an integrated electronic device with reduced parasitic currents, FIG. 8 shows a complete embodiment in accordance with the present invention of the integrated electronic device having reduced parasitic currents, and FIG. 9 shows a possible circuit diagram of the device shown in FIG. 7. With reference to the figures the symbol IC indicates as a whole and diagramatically an integrated electronic device having reduced parasitic currents and embodied in accordance with the present invention. Specifically and with reference to FIG. 7 it is seen that the integrated device IC comprises a substrate 1 of semiconductor material having a first conductivity type and specifically type N- and in which are formed a first 2 and second 3 diffusion regions of a second conductivity type and specifically type P. In the second diffusion region 3 are also included a third 8 and a fifth 9 diffusion regions having the first conductivity type and specifically type N. Again with reference to FIG. 7 it is seen that in the substrate 1 and in the second 3 and fifth 9 diffusion regions are included respectively a collector region, a base region and an emitter region of an NPN power transistor POWER. In the first diffusion region 2 is included a control circuit of the above mentioned power transistor. In the substrate 1 and in the first 2 and second 3 diffusion regions are also included respectively a base region, a collector region and an emitter region of a first parasite transistor Tp1 of type PNP. It is pointed out the by inserting the third diffusion region 8 in the second diffusion region 3 and short-circuiting these two regions on the side directly facing the fifth diffusion region 9 there is created a resistive path R placed in series with the emitter region of the first parasite transistor Tp1 so as to provide it negatively and permit its saturation with resulting drastic reduction of its current gain. In addition the presence of this resistive path R causes the parasitic current due to the above mentioned parasite transistor Tp1 to have limited maximum value. In the substrate 1 and in the second 3 and third 8 diffusion regions are also included respectively an emitter region, a base region and a collector region of a second parasitic transistor Tp2 of type NPN as shown in FIG. 9. In the substrate 1 is also included a fourth resistance R' shown in FIG. 9 and due to the narrowing created in the substrate 1 at the separation zone between the two diffusion regions 2 and 3. In FIG. 8 is shown a complete embodiment of the integrated device IC. In this FIG. it can be seen that the first diffusion region 2 includes a first buried region 2a having a conductivity of the second type over which is placed a sixth diffusion region 2b having the same conductivity type. The second diffusion region 3 is formed from a second buried region 3a having the first conductivity type and over which is placed a sixth diffusion region 3b having the same conductivity type. The emitter region of the power transistor POWER includes a third buried region 12 and a seventh 13 and eighth 14 and ninth 15 diffusion regions. The third diffusion region 8 includes a fourth buried region 11 having the first conductivity type and specifically type N+ and over which is placed a fourth diffusion region 10 having the same conductivity type and specifically type N++. Again with reference to FIG. 8 the resistive path R includes a first R1, second R2 and third R3 resistances connected in mutual series. Specifically the first R1 and third R3 resistances are layer resistances whose value is set by the dope level used. The second resistance R2 exhibits a high value due to the narrowness caused by the diffusion of the region 11. This value can be changed by modifying the width of this fourth diffusion region 11. Operation of the device in accordance with the present invention is now described with particular reference to the equivalent circuit structure shown in FIG. 9. In this FIG. it can be observed that when the voltage present on the collector region of the power transistor POWER assumes a smaller value than that of the conduction threshold forming the emitter of the first parasite transistor Tp1 the current circulation which derives therefrom causes a voltage drop on the resistive path R. In this manner the above mentioned parasite transistor Tp1 is reacted negatively and taken to saturation with a resulting reduction of its current gain and limitation in maximum value of the parasite current due thereto. The presence of the second parasitic transistor Tp2 does not influence the operation of the device IC because this transistor has a very low current gain with respect to that of the first parasite transistor Tp1. In any case the conduction of this second parasitic transistor Tp2 can only further depolarize the first parasite transistor Tp1 because it involves an injection of supplementary current which tends to raise locally the potential of the base region of the above mentioned transistor Tp1. In conclusion the device in accordance with the present invention allows reduction of the parasitic effects caused by the presence of the first transistor Tp1 in terms of parasitic current injected and occupation of area.

Claims: Electronic device integrated monolithically on a semiconductor material comprising a substrate (1) having a first conductivity type and in which are formed a first (2) and second (3) diffusion regions of a second conductivity type with said substrate (1) and said first (2) and second (3) diffusion regions forming respectively a base region, a collector region and an emitter region of a parasitic transistor (Tp1) and characterized in that in the second diffusion region (3) is formed a third diffusion region (8) having conductivity of the first type to provide in said second diffusion region (3) a resistive path (R) which is placed in series with the emitter region of the parasitic transistor (Tp1) while backfeeding it negatively and taking it to saturation with a resulting reduction of its current gain and limitation of the maximum current due thereto. Electronic device in accordance with claim 1 and characterized in that the third diffusion region (8) includes a buried region (11) having the first conductivity type and over which is placed a fourth diffusion region (10) of the same conductivity type. Electronic device in accordance with claim 1 and characterized in that the third diffusion region (8) has N-type conductivity. Electronic device in accordance with claim 2 and characterized in that the buried region (11) has type N+ conductivity. Electronic device in accordance with claim 2 and characterized in that the fourth diffusion region (10) has type N++ conductivity. Electronic device in accordance with claim 1 and characterized in that the resistive path (R) comprises a first (R1), second (R2) and third (R3) resistances connected in mutual series. Electronic device in accordance with claim 6 and characterized in that the first (R1) and third (R3) resistances are layer resistances with value set by a predetermined doping level. Electronic device in accordance with claim 6 and characterized in that the second resistance (R2) has a value which depends on the dimensions of the third diffusion region (8). Method for reducing the current gain of a parasitic transistor (Tpl) included in an electronic device integrated monolithically on a semiconductor material and including a substrate (1) having a first conductivity type and in which are formed a first (2) and second (3) diffusion regions of a second conductivity type with said first (2) and second (3) diffusion regions incorporating respectively a base region, a collector region and an emitter region of the parasitic transistor (Tp1) and characterized in that it comprises the step of: forming in the second diffusion region (3) a third diffusion region (8) to provide in said second diffusion region (3) a resistive path (R) placed in series with the emitter region of the parasitic transistor (Tp1) while backfeeding it negatively and taking to saturation with the resulting reduction of its current gain and limitation of the maximum current due thereto.

Inventors: AIELLO NATALE, GRAZIANO VITO, AIELLO, NATALE, GRAZIANO, VITO
Applicants: CONS RIC MICROELETTRONICA, CO.RI.M.ME.
Application year: 1995
Main classification: H01L29
IPC codes: H01L27