Method of manufacturing a semiconductor device with auto-aligned polycide gate

Abstract: An electronic semiconductor device (20) with a control electrode (19) consisting of self-aligned polycrystalline silicon (4) and silicide (12), of the type in which said control electrode (19) is formed above a portion (1) of semiconductor material which accommodates active areas (9) of the device (20) laterally with respect to the electrode, has the active areas (9) at least partially protected by an oxide layer (10) while the silicide layer (12) is obtained by means of direct reaction between a metal film deposited on the polycrystalline silicon (4) and on the oxide layer (10).

Description: FIELD OF APPLICATION The present invention relates to a method for forming electronic semiconductor device with a control electrode consisting of self-aligned silicide and polycrystalline silicon. More particularly, the invention relates to a process for providing a semiconductor device with a control electrode consisting of self-aligned silicide and polycrystalline silicon, of the type in which said silicide layer is formed above the polycrystalline silicon following definition of active areas of the device formed on a portion of semiconductor material laterally with respect to said control electrode. KNOWN ART In the specific technological sector of the present invention it is well-known to use polycrystalline silicon or polysilicon to form the gate electrode of field-effect semiconductor devices, for example MOS transistors also provided with source electrodes and drain. Polycrystalline silicon offers several advantages compared to other materials and can be used to form both logic and analog integrated circuits as well as power devices. Precisely with reference to power devices, it is known that they are formed by means of a multicellular structure which is derived from the ordered repetition of a basic cell. This cell can have a square, rectangular or hexagonal structure or any other suitable shape which is normally defined by means of openings formed in the polycrystalline gate electrode. The power device can therefore be regarded as the result of a parallel connection of a large number of basic cells. In this context, the polycrystalline silicon gate electrode of each basic cell represents a first level of interconnection which is electrically insulated from an overlying metallisation layer by means of an intermediate dielectric layer. The metallisation layer generally consists of aluminium and permits the formation of a source electrode which collects all the current which passes through the device, connecting together all the basic active areas. A small portion of the metallisation area is intended for polarisation of the gate electrode; this portion is separated by means of photolithographic techniques from the source electrode and is placed in direct contact with the polycrystalline silicon layer. It is also well-known that the gate electrode is electrically insulated with respect to the underlying semiconductor substrate by means of a thin layer of silicon oxide. By varying the polarisation of the gate electrode with respect to the source electrode it is possible to regulate conduction of the electronic device. According to the physical principles which govern the operation of MOS devices, a capacitance which is not constant is present between the gate electrode and the source electrodes and drain. This capacity requires a certain quantity of charge so that its potential can be varied. The charge is supplied or recalled by an external circuit driving the gate electrode and, in MOS power devices, it can be reach or exceed a few hundred nanocoulombs. In order to obtain fast MOS devices, it is necessary to polarise the gate electrode rapidly and uniformly. The commutation speed of these devices depends in fact also on the rapidity of polarisation of the gate, in particular for frequencies greater than 100 kHz. On account of the high resistivity of the polycrystalline silicon (ρ = 2*10 -3 - 6*10 -3 Ωcm) with respect to the distributed capacitance, the gate electrode during the commutation transient does not reach immediately and uniformly the same potential which is applied from outside via the driving circuit. Consequently, there will be a certain delay during polarisation of the entire electrode; this delay will be all the more accentuated, the greater the distance between the basic cell and the contact termination of the metal gate electrode. In an attempt to speed up and render uniform the polarisation phase, the known art proposes a first solution which consists in sacrificing a part of the active area of the device in order to form an aluminium gate termination of suitable shape extending over most of the polycrystalline silicon area. This particular aluminium termination normally assumes a fingers configuration and makes it possible to achieve a continuous contact with the underlying polycrystalline silicon layer. Although advantageous in various respects, this solution does not resolve entirely the problem of speeding up the MOS devices and has the drawback that it requires active area to be sacrificed and places constraints on the topography of the metallisation structure owing to the presence of the gate fingers. A second solution proposed by the known art consists in attempting to reduce the layer resistance of the polcrystalline silicon, forming above it a layer of silicide. Owing to the low resistivity of silicide (ρ = 17*10 -6 - 150*10 -6 Ωcm) compared to that of polysilicon and owing also to its greater thermal and chemical stability compared to pure metals, it is possible to integrate the silicides in the semiconductor devices into an intermediate phase of the production process; that is to say into a phase following which further heat treatments are envisaged. Tungsten silicide (WSi) is the material normally used for forming the silicide layer above the polycrystalline silicide by means of chemical vapour deposition (CVD) techniques. The tungsten silicide cannot be obtained from the reaction between a tungsten film and the silicon, but it is necessary to deposit simultaneously both the atom species, tungsten (W) and silicon (Si). This means that, contrary to that which occurs in the case of silicides obtained from the reaction of a metal film with silicon, the tungsten silicide layer must be defined by means of a photolithographic process. For this reason, the tungsten silicide layer is deposited after the polysilicon layer, then proceeding with etching of both the layers so as to obtain self-alignment. Tungsten silicide, however, has disadvantages, one of which is a high resistivity (ρ = 100*10 10-6 - 150*10 -6 Ωcm) which keeps the layer resistance of the gate electrode high. Moreover, as already mentioned above, the silicide is deposited onto the surface of the polysilicon before both the layers are defined by a photolithographic process. However, the MOS power devices are subjected to ion implantation and heat diffusion phases also following definition of the gate electrode. In particular, in the case of MOS power devices, the formation of the body and source junctions takes place folling definition of the gate electrode and the presence of tungsten silicide on the surface of the polysilicon imposes some constraints on the production processes. The known art has therefore proposed the use of alternative materials such as titanium silicide (TiSi 2 ) or cobalt silicide (CoSi 2 ), which have a resistivities of between 17*10 -6 and 20*10 -6 Ωcm. These silicides are normally obtained by reaction of a metal film with the silicon and are also defined "self-aligned" in that the reaction between the metal film deposited and the silicon takes place only when the two materials are brought into close contact. Consequently, if the semiconductor substrate is protected by an oxide layer in which some openings have been formed, then the formation of the compound will occur only inside these openings. Titanium silicide and cobalt silicide have been proposed for the formation of structures such as that illustrated in the enclosed Figure 1. This figure shows the basic cell of a MOS power device during an intermediate phase of the formation process, where a silicide layer is grown above the polysilicon gate electrode and also above the monocrystalline silicon regions. The silicide layer is also used for the formation of ohmic contacts with the monocrystalline silicide above the active areas or regions of monocrystalline silicon. In order to ensure, however, insulation between the gate electrode and these active regions, oxide spacers have been provided along the perimeter of the electrode so as to prevent the formation of silicide on the side walls of the polysilicon. On account of the chemical reaction between the metal and the semiconductor, which gives rise to the formation of silicide, the excess metal on the walls of the spacer may give rise to the formation of a metal compound with the silicon. The latter may in fact spread from the polcrystalline or monocrystalline region towards the side wall of the spacer. This phenomenon has been extensively studied and is known in the literature as "lateral rising" and may be the cause of a short-circuit between the two layers of silicide deposited respectively above the polysilicon and above the active areas. The danger of short-circuiting is due to the fact that the metal compound which rises up the spacers cannot be etched selectively with respect to the silicide, unlike that which is possible in the case of pure metal. If the metal compound grown on the side wall of the spacer manages to join electrically the two electrodes at any point on the perimeter, then the device will not function. Therefore, the formation of the silicide on the surface of the monocrystalline silicon may be damaging on account of the phenomenon of lateral rising. This fact must be duly taken into account when designing a MOS-type power device since, for reasons associated with the efficiency of the device, the channel perimeter which coincides substantially with that of the spacers tends to be maximised. In doing so, however, there may be a very high probability of a short-circuit occurring owing to the phenomenon of lateral rising, to the extent that that the efficiency will be reduced. Moreover, in a MOS power device, typically an N-channel MOS device, the formation of the silicide in the contact regions may be superfluous, if not even damaging since the dimensions of the contacts are rarely less than a few micrometres. With dimensions of this order of magnitude, normal metallisation with aluminium already enables a good ohmic contact to be formed both on n+ type semiconductors (for example the source region) and on p-type semiconductors (for example the body region). Instead, most of the silicides useful for these applications have the special characteristic that they produce slight emptying of dopant inside the semiconductor and in the vicinity of the silicide/silicon interface. This phenomenon has the effect of increasing the specific contact resistance between the silicide and the semiconductor. This is particularly important for the p-type region (body) present inside the cell of an N-channel MOS transistor or in the p-type region (emitter) in the case of an IGBT transistor. In the particular case of the MOS device, the body region forms the anode of a body/drain diode and this junction is used in some circuit applications as a "recirculation diode"; therefore, the drop in potential at its terminals when it is directly polarised must be less than a predetermined value which depends on the type of device. Self-aligned silicides could, owing to their low resistivity, be used in place of tungsten silicide by growing these materials soon after the deposition of the layer of polycrystalline silicon. Subsequently, via a photolithographic process, openings in the gate electrode may be defined. However, since these materials have a thermal stability which is lower than that of tungsten silicide, their integrity would be affected by the subsequent heat processes required for completion of the device. It is known in the art from Narita et al ., "A High-Speed 1-Mbit EPROM With A Ti-Silicided Gate, IEEE Transactions on Magnetics SC20, Feb. 1985, No. 1, New York, USA to create a self-aligned titanium silicide layer on a control gate of a Flash-EPROM memory device. A thermal oxide layer is put on the active areas and side walls of the control gate using a protective layer as an oxidation mask. A diffusion step is performed separately from the heating step to grow the thermal oxide. It is known in the art from Murao et al ., "A High Performance CMOS Technology With Ti-Silicided P/N-Type Poly-Si Gates, International Electron Devices Meeting 1983 Technical Digest, Washington DC, USA, 5-7 Dec. 1983, 1983, New York, NY, USA, pages 518-521 York, USA to create a self-aligned titanium silicide layer on a control gate of a CMOS device. It is known in the art from EPA 393 949 in the name of General Electric to create a silicide layer on a gate electrode of a Power FET device and to use cobalt as an alternative to Titanium in forming the silicide layer. The technical problem underlying the present invention is that of improving a method of forming a semiconductor device, in particular a field-effect power device having structural and functional characteristics such as to enable a control electrode consisting of self-aligned silicide and polycrystalline silicon to be obtained, overcoming the limitations and/or the drawbacks indicated previously with respect to the known art. SUMMARY OF THE INVENTION The novel idea underlying the present invention is that of forming a gate electrode with a double layer of polysilicon and silicide, the latter being obtained by means of a direct reaction between metal and silicon precisely and only in the region of the gate electrode, while the active areas of the device are protected from this reaction. On the basis of this novel idea, the technical problem is solved by a process for forming a device of the aforementioned type defined in Claim 1. The characteristic features and advantages of the device according to the invention will emerge from the description, provided hereinbelow, of an example of embodiment provided by way of a non-limiting example with reference to the accompanying drawings. Brief description of the drawings Figure 1 shows a schematic view, in vertical section, of a basic cell of an electronic semiconductor device during an intermediate phase of formation according to the known art; Figure 2 shows a schematic view, in vertical section, of a portion of semiconductor material on which a basic cell of an electronic device manufactured according to the present invention is formed; Figures 3 and 8 show respective schematic views of the portion of semiconductor material according to Figure 2 during subsequent phases of the production process resulting in formation of the device manufactured according to the invention; Figure 9 shows a schematic view, in vertical section, of an electronic semiconductor device formed according to the present invention; Figure 10 shows a schematic view, in vertical section, of a second electronic semiconductor device manufactured according to the invention. Detailed description of the invention With reference to these figures, 1 denotes an epitaxial layer formed in a conventional manner on a substrate of semiconductor material, for example n+ type monocrystalline silicon. In the epitaxial layer 1 there is defined a deep-body pocket 2 inside which active areas 9 of an electronic device 20 according to the present invention will be formed. Figures 2 to 10 show substantially respective views, in vertical section, of a portion of semiconductor material on which a basic cell according to the invention is formed. A thin layer 3 of gate oxide is grown above the epitaxial layer 1. A polycrystalline or polysilicon layer 4 is deposited above the oxide layer 3 over a thickness of about 5000 Anstromg (A). This layer 4 is n+ doped via an ion implantation or by means of oven preparation so as to obtain a concentration of dopant of the order of 10 19 atoms/cm 3 . A subsequent oxidising heat process allows the growing of a thin layer 5 of oxide, of the order of 150 A, onto which a layer 6 of silicon nitride of about 1000 A is deposited. The growth of the oxide 5, 150 A thick, can also be avoided by depositing the layer 6 of nitride directly onto the surface of the polycrystalline silicon. This choice depends on the type of equipment used for etching, in sequence, the nitride 6 and the polycrystalline silicon 4. The absence of the oxide 5 is preferable for better control of the self-alignment between silicide and polysilicon. Figure 2 schematically illustrates this basic structure on the basis of which the device according to the invention is obtained. Referring now to Figure 3, the process which results in the formation of the device according to the invention envisages the definition of an opening 15 having, in plan view, a square, rectangular or hexagonal shape. The opening 15 is defined by means of a common photolithographic process which etches the nitride layer 6, the thin oxide 5, if it is present, and the polysilicon 4 until the gate oxide 3 is revealed. At this point, an implantation of boron at a dosage of between 10 13 and 10 14 ions/cm 2 and subsequent diffusion make it possible to obtain a surface pocket 7 which extends laterally with respect to the pocket 2. The pocket 7 is necessary for the formation of a channel region underneath the gate electrode 19 of the basic cell 20. The pocket 7 is clearly visible in Figure 4 and, in a preferred embodiment, is of the P- type for the formation of N-channel MOS devices. Inside the opening 15, in a practically central position, a masking 16 is formed with a layer 8 of photosensitive material, for example photoresist. Subsequent selective etching on the sides of the masking 16 enables portions of gate oxide 3 inside the opening 15 to be removed, revealing the surface of the semiconductor material belonging to the pockets 7. An implantation of arsenic ions enables the formation of active n+ doping areas 9 shown in Figure 5. These areas 9, after a suitable diffusion phase, define the source region associated with each basic cell 20. This latter diffusion phase is performed after removal of the layer 8 of photoresist and is advantageously performed in an oxidising environment so to enable the growth of a layer 10 of oxide of about 1500 A thickness on the uncovered regions of the semiconductor. The surface of the polysilicon 4 does not undergo oxidation since it is protected by the nitride layer 6. The resultant structure following growth of the oxide 10 is shown in Figure 6. At this point, selective etching of the nitride 6 with respect to the thermal oxide and brief etching of the oxide makes it possible to remove the thin layer 5, if it is present, and expose the entire surface of the polysilicon, except for the portion inside the opening 15 still protected by the oxide layer 10, as shown in Figure 7. This process phase is self-aligned with the polysilicon layer 4 and does not require additional phototechniques or masks. Now, a metal layer 11 is deposited over the entire device so that the reaction of the metal with the polysilicon gives rise to the selective formation of a silicide layer 12, as shown in Figure 8. The metal layer 11 may be formed with titanium or cobalt since both the corresponding silicides have low resistivity values (between 17 and 20*10 -6 Ωcm). The chemical reaction between metal and semiconductor is caused by a heat process. The chemical reaction between metal and semiconductor for the formation of silicide is inhibited only above the regions protected by the oxide layer 10. The metal layer 11 not reacted above the oxide surface 10 is selectively removed and a subequent deposition enables an intermediate dielectric layer 13 covering the entire device to be obtained. A new opening 17 is defined through this dielectric layer 13 and the thin oxide 10 by means of photolithographic process. Via this opening 17, the source region 9 and body region 2 are reached; the deposition of an aluminium contact layer 14 enables the source current of each device 20 to be collected, as shown in Figure 9, connecting together all the source terminations of all the basic devices. The device is then completed with a phase involving a photographic technique applied onto the aluminium surface so as to define the metal source and gate electrodes, not shown in Figure 9. Moreover, a dielectric layer 21 is deposited in order to passivate the surface of the device. This layer 21 is removed only in the region of the pad areas via which the device is connected to the interconnecting wires during package assembly. The drain contact is formed on the rear of the device by means of a metallisation layer 22 formed according to the known art. A valid alternative to the production process described above consists in avoiding the use of deep-body pockets 2. This makes it possible to simplify the formation of the devices 20 by simply increasing the dose and the energy of the boron implantation necessary for formation of the p- type pockets 7. In this way a single P+ type region 18, shown in Figure 10, is obtained, having a layer resistance comparable with that of the process which uses the deep-body pocket 2 and with a concentration of dopant in the channel region which is nevertheless adequate for correct operation of the device. The structure of the resulting device is therefore entirely identical to that described previously with the only substantial difference that there is no longer the pocket 2 shown in Figure 2 and instead there is an extensive region 18 as shown in Figure 10. This variation of embodiment is also effective for preventing the energisation of a parassitic npn bipolar transistor which is always present in the vicinity of the channel region and which tends to start conducting during the commutation transients. The MOS power device manufactured according to the invention is provided with a gate electrode with a double polysilicon/silicide layer having a low layer resistance. This compound is obtained directly by the reaction of a metal film with the polycrystalline semiconductor and, therefore, the resistivity of the silicide thus obtained can even be a tenth of that of tungsten silicide. The reaction between metal film and the polysilicon occurs exclsuively on the surface of the gate electrode, while the active areas of the device are covered with an oxide which inhibits this reaction. The resultant silicide structure is of the type self-aligned with polysilicon and no additional photolithographic phase is necessary in order to obtain this result. The fact that above the active areas there is no formation of silicide means that it is possible to avoid the presence of spacers and hence the dangerous possibility of short-circuits due to the phenomenon of "lateral rising". The main effect of the reduction in the layer resistance of the gate electrode is that of making the device two to four times faster during the de-energisation phase, thus reducing the power dissipated during commutation. This advantage is particularly important in applications where a high commutation speed is required. Moreover, the structure of the device manufactured according to the invention makes it possible to reduce the intensive use of aluminium interconnections for the gate electrode. The latter reduce the active area of the device, complicating the circuit layout and the design thereof.

Claims: Process for forming an electronic semiconductor device (20) with a control electrode (19) consisting of self-aligned polycrystalline silicon (4) and a self-aligned silicide layer (12), of the type in which said silicide layer (12) is formed above the polycrystalline silicon (4) following definition of active areas (2, 7, 9) of the device (20) formed on a portion of semiconductor material (1) laterally with respect to said control electrode (19), the device being a Power MOS device and the method comprising: providing a protective layer (6) to prevent oxidation of the polycrystalline layer; diffusing ions implanted into the active areas (9) in an oxidizing environment, the diffusing step growing a self-aligned oxide layer (10) to conceal the active areas and a side portion of the control electrode (19) ; subsequent deposition of a cobalt film above the polycrystalline silicon (4) and said oxide layer (10); a heat treatment for obtaining a direct reaction between the cobalt film and the polycrystalline silicon (4) with formation of the silicide layer (12); removal of the cobalt film above the oxide layer; defining an opening in the oxide layer (10) to provide contact to the active areas; and forming a contact (14) through said opening. Process according to Claim 1, characterized in that a protective layer (8) is formed over said polycrystalline silicon (4) before said oxide layer (19) is formed, said protective layer (8) preventing said oxide layer (19) from forming on said polycrystalline silicon (4), and in that said protective layer (8) is removed after forming said oxide layer (19) and before depositing said cobalt film. Process according to Claim 1, characterized in that , following removal of the cobalt film, deposition of an intermediate dielectric layer (13) is performed. Process according to Claim 3, characterized in that it comprises a further phase of metallisation of said areas (2, 9) via a contact opening (17). Process according to Claim 1, characterized in that the active areas (9) of an adjacent device (20) having a control electrode are formed in a common well (18) inside said portion (1) of semiconductor material.

Inventors: FERLA GIUSEPPE, SANTANGELO ANTONELLO, FERLA, GIUSEPPE, SANTANGELO, ANTONELLO
Applicants: CO RI M ME BR CONSORZIO PER LA, ST MICROELECTRONICS SRL, CO.RI.M.ME.<BR>CONSORZIO PER LA RICERCA SULLA<BR>MICROELETTRONICA NEL MEZZOGIORNO, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: H01L23
IPC codes: H01L29, H01L21