Signal processing circuit for vector scope

Abstract: A signal processing circuit for a vector scope adapted to display and measure characteristics of a color video signal on a screen therein is disclosed which comprises a variable gain circuit 3, a demodulation circuit 6, timing signal generator 7, amplitude detection circuits 8,9, memory 12 storing a reference amplitude and CPU11. An input signal V in through the variable gain circuit is supplied to demodulation circuiting from where chrominance components R-Y, B-Y are provided to the amplitude detection circuits. When the timing signal is provided to the amplitude detection circuits, the circuits detect their amplitudes. The CPU computes an amplitude of a burst signal in accordance with the detected amplitudes and the difference between the computed amplitude and the reference amplitude stored in the memory. If the difference is not zero, the CPU controls the variable gain circuit so that it become zero.

Description: The present invention relates to a signal processing circuit for a vector scope adapted to measure the characteristics of a color video signal, and more particularly to a signal processing circuit adapted to automatically set at least one of the amplitudes represented by vectors of a burst signal and a chroma signal at a specified amplitude position on a display screen. A vector scope in a measuring instrument for demodulating an input color video signal to display in terms of a vector the relation between R-Y and B-Y chrominance components containing color information and being capable of measuring and displaying the characteristics of the color video signal. The angle and amplitude of the displayed vector are related to the hue and the chroma of the color represented by the color information. The display screen of the vector scope is represented as shown in Fig. 1 for example. In Fig. 1, the vertical axis indicates the R-Y component while the horizontal axis indicates the B-Y component. The graduation "a" provided along the circumference of the display screen serves to indicate a phase of the chroma signal contained in the color video signal and is capable of indicating a jitter component contained in a burst signal. The graduation "b" provided at the leftward and of the horizontal axis serves to indicate a differential gain (DG) and a differential phase (DP) of the chroma signal. In use when a jitter component of a burst signal is desired to be measured, the tip end of a vector representation V b on the display screen which represents the burst signal must be aligned with the graduation "a", or a circumferential position of the display screen. According to a prior art, a lug on a front manipulation panel is manually operated to control a variable gain circuit incorporated in a signal processing circuit, watching the display screen as to align the tip end of the vector representation of a burst signal with a circumferential position of the display screen. In the case that a DG or DP of the chroma signal is to be measured, it is necessary to adjust the tip end of a vector representation V c of the chroma signal to the reference point 0 (the crossing point of the horizontal axis and the circumference). Also in the case, by manually handling lugs of the manipulation panel to control a gain and phase (angle) of the chroma signal, watching the display screen, the tip end of the vector representation of a chroma signal may be adjusted to the reference point 0 of the graduation "b". Although such a signal processing circuit has already been proposed as a vector representation of a burst signal which may be automatically aligned with the horizontal axis, even such a prior art processing circuit requires an amplitude of the vector representation to the manually adjusted and an amplitude and angle of a vector representation of a chroma signal cannot be automatically adjusted to given values. As explained above, according to the prior art, the amplitude and/or the angle of the vector representation have to be adjusted to and aligned with the given values by manually handling the lugs of the manipulation panel, watching the display screen. As the consequence, the operation is cumbersome and it is difficult to align the vector representation accurately with the specified positions (in respect of the amplitude and angle). US-3,820,156 describes a vectorscope which displays a test circle pattern without distortion on a screen. In order to accomplish this, amplitudes of U (=B-Y) and V (=R-Y) signals derived from a circular test signal are inputted during horizontal blanking (or flyback) intervals of a television signal. These are compared and adjusted to be the same. Phases of the U and V signals are also compared and adjusted to have a difference of 90°. The subject of the present invention is set out in claim 1. Fig. 1 shows a symbolic display screen of a vector scope; Figs. 2(A) and 2(B) show a block diagram of a signal processing circuit in a vector scope, according to an embodiment of the present invention; Figs. 3(A) - 3(C) respectively illustrate timing waveforms of input video signal, R-Y component and timing signal in the circuit shown in Fig. 2 in a burst signal amplitude automatic setting mode; Fig. 4 shows an operational flow chart of the circuit shown in Fig. 2 in the burst signal amplitude automatic setting mode; Figs. 5(A) and 5(B) show a block diagram of a signal processing circuit in a vector scope, according to another embodiment of the present invention; Figs. 6(A) - 6(D) respectively illustrate timing waveforms of input video signal, R-Y component, timing signal and sweep signal in the circuit shown in Fig. 5 in a DG/DP automatic setting mode; Figs. 7(A) and 7(B) show an operational flow chart of the circuit shown in Fig. 5 in the DG/DP automatic setting mode; and Fig. 8(A) illustrates a symbolic view of a display screen of a vector scope in the DG automatic setting mode, and Fig. 8(B) illustrates a symbolic view of a display screen of a vector scope in the DP automatic setting mode. Figs. 2(A) and 2(B) show an embodied signal processing circuit in a vector scope according to the present invention. In Fig. 2(A), reference numeral 1 designates an input terminal to which a color video signal V in is applied, 2 a manipulation panel, 3 a variable gain circuit of a voltage control type (a variable gain amplifier), 4 a sub-carrier regeneration circuit adapted to regenerate a sub-carrier signal from the color video signal V in , and 5 a digital phase shifter adapted to shift a phase of the sub-carrier signal regenerated at the circuit 4. Reference numeral 6 designates a demodulation circuit which receives an output signal from the variable gain circuit 3 and an output signal from the digital phase shifter 5. The demodulation circuit 6 includes multipliers 6 1 and 6 2 , low pass filters (LPF) 6 3 and 6 4 , amplifiers 6 5 and 6 6 having the same gain and a phase shifter 6 7 adapted to shift a phase of the output signal from the digital phase shifter 5 by -90°, and outputs vector signals R-Y and B-Y which are chrominance components of the input color video signal. These R-Y and B-Y signal are supplied respectively to vertical and horizontal drive circuits (not shown) for driving the vertical and horizontal axes of the display screen of the vector scope so that the components of the color video signal may be displayed in terms of vector. Referring to Fig. 2(B), reference numeral 7 designates a timing signal generation circuit which generates a timing signal T by monitoring R-Y and B-Y signals coming from the demodulation circuit 6, 8 and 9 amplitude detection circuits comprising sample and hold circuits having the same operation timing which is stipulated by the timing signal T supplied from the timing signal generation circuit 7. Numeral 10 designates an analog/digital (A/D) converter which converts analog signals coming from the amplitude detection circuits 8 and 9 into digital signals, and 11 a microprocessor (CPU) which controls the variable gain circuit 3 and the timing signal generation circuit 7 as well as operation of the entire vector scope. Referring to Fig. 2(A) again, reference numeral 12 designates a read/write memory which stores a reference amplitude value E (b)ref at a predetermined address. The reference amplitude value E (b)ref is used for setting an amplitude E (b) of a vector representation of a burst signal contained in the color video signal to a predetermined amplitude corresponding to the value E (b)ref . It is to be noted that the reference amplitude value E (b)ref is preferably so set that the amplitude of the vector representation coincides with the circumference of the display screen, in the course of measurement of jitter component. It is, of course, also to be noted that the amplitude need not necessarily coincide with the circumference but can be set at any arbitrary value if necessary. Accordingly, the value E (b)ref is changeable by operating the manipulation panel 2 by a user. An operation of the signal processing circuit shown in Fig. 2 will next be explained in detail by referring to Figs. 3 and 4. When a color video signal V in , as shown in Fig. 3(A) is input to the input terminal 1, the signal is supplied to the demodulation circuit 6 via the variable gain circuit 3. The color video signal is also supplied to the sub-carrier regeneration circuit 4 where a sub-carrier signal is regenerated. The sub-carrier signal is then supplied to the demodulation circuit 6 via the phase shifter 5. The demodulation circuit 6 supplies, in turn, R-Y and B-Y signals as shown in Fig. 3(B). These R-Y and B-Y signals are respectively provided to the vertical and horizontal drive circuits to drive the vertical and horizontal axes of the display screen of a vector scope. What has been described above is the operation of the signal processing circuit in the case of the normal mode. In order to automatically set an amplitude of a vector representation of a burst signal to a preset size, or in order to implement a burst signal amplitude automatic setting mode (BSAAS mode), an associated key on the manipulation panel 2 is depressed at Step S 1 in Fig. 4 by a user. It is assumed that a reference amplitude value E (b)ref has been stored in the memory 12 by entering the value from the manipulation panel 2. At Step S 2 , the CPU11 sets the timing signal generation circuit 7 to a burst mode so that the circuit 7 generates a timing signal T as a burst timing signal T (b) at a timing corresponding to the burst signal as shown in Fig. 3(C), by monitoring R-Y signal or B-Y signal provided from the demodulation circuit 6. This causes, in Step S 3 , the amplitude level of the burst signal parts R-Y (b) and B-Y (b) of R-Y and B-Y signals from the demodulation circuit 6 to be detected respectively at the amplitude detection circuits 8 and 9 and then converted by the A-D converter 10 to digital amplitude signals E R-Y(b) and E B-Y(b) . These amplitude signals E R-Y(b) and E B-Y(b) are input to CPU11 where an amplitude value E (b) at that time of the vector representation of the burst signal is obtained by computing the square root of E R-Y(b) 2 + E B-Y(b) 2 in accordance with the supplied amplitude signals in Step S 4 . Namely, E ( b ) = E R - Y ( b ) 2 + E B - Y ( b ) 2 In Step S 5 , the difference between the obtained amplitude value E (b) and the reference amplitude value E (b)ref which has been read out from the memory 12, or ΔE (b) (= E (b)ref - E (b) ) is computed and whether or not ΔE (b) is zero is decided. In the case that the difference ΔE (b) is not zero, the process proceeds to Step S 6 so as to control the gain of the variable gain control 3 in such a manner as the difference ΔE (b) is made to be zero. Subsequently, in Step S 3 , the amplitude value E (b) is computed again and Steps S 3 through S 6 are implemented repeatedly until ΔE (b) =0 is attained in Step S 5 . In Step S 5 , if ΔE (b) =0 is attained, the BSAAS mode is finished. In the present description, the expression "the difference is zero" signifies simply that it is mathematically or ideally zero. However, in an actual operation, it signifies that the difference is zero in the minimum resolution which is set in advance. In this way, the amplitude value E (b) of the vector representation of the burst signal may be automatically set to the predetermined reference amplitude value E (b)ref . Although the signal processing circuit shown in Fig. 2 can be so constituted that the phase shift amount in the digital phase shifter 5 may be controlled by manually rotating a lug on the manipulation panel 2 in order to coincide an angle (or phase) of the vector representation of a burst signal with a specified vector angle  (b)ref such as zero (coincident with the horizontal axis), it is preferably constituted so that a so-called one-touch operation of a switch on the operational panel allows the angle to automatically coincide with the reference angle  (b)ref . In order to attain the one-touch operation for the angle, the reference angle (or phase)  (b)ref may be previously stored in the memory 12, and a burst signal phase automatic setting mode (BSPAS mode) may performed. In the BSPAS mode, when a burst phase automatic setting key (BSPAS key) is depressed, the same operations as in Steps S 2 - S 3 are practiced and then the following equation is computed: ⊖ ( b ) = cos -1 E B - Y ( b ) E R - Y ( b ) 2 + E B - Y ( b ) 2 After the calculation above, the reference angle  (b)ref is read out from the memory 12 and the following calculation is performed: Δ (b) =  (b)ref -  (b) If the phase difference Δ (b) is not zero, the procedure goes to a phase compensation operation where the phase-shift amount at the phase-shifter is controlled to make Δ (b) =0. In Figs. 5(A) and 5(B), there is shown a signal processing circuit for a vector scope according to another embodiment of the present invention which is capable of operating in accordance with the BSAAS mode as explained above and also is capable of operating a DG/DP automatic setting mode. The term "DG/DP automatic setting mode" signifies such a mode as when a differential gain (DG) key or differential phase (DP) key on the manipulation panel 2 is depressed, an automatic adjustment is made so that an amplitude and/or phase of a vector representation of a chroma signal will coincide with a specified value which has been set in advance and the variation in amplitude or phase of a color video signal is displayed on the vector scope to measure the DG or DP level. In the signal processing circuit shown in Fig. 5, components identical or similar to those shown in Fig. 2 are identified with the same reference numerals. In addition to the components of the circuit shown in Fig. 2, the signal processing circuit shown in Fig. 5 further includes a synchronizing signal separation circuit 13, horizontal sweep signal generator 14, three switching circuits 15 through 17 and two amplifiers 18, 19 having different gains. In the signal processing circuit shown in Fig. 5, when the circuit is operated in the BSAAS mode, the switching circuit 15 is rendered to connect to a V/DP terminal and the switching circuits 16 and 17 are rendered to connect to V terminals respectively under a control of the CPU11 when it receives a burst signal amplitude automatic setting signal from the manipulation panel 2. By these switching operations, a signal channel or path similar to that of the signal processing circuit shown in Fig. 2 is formed whereby the BSAAS mode is executed as described above in connection with Fig. 2. The operation of the DG/DP automatic setting mode in the signal processing circuit shown in Fig. 5 will next be explained by referring to Figs. 6 and 7. Figs. 6(A) - 6(D) illustrate waveforms of signals output from components in the signal processing circuit shown in Fig. 5 and Figs. 7(A) and 7(B) show a flow chart in the DG/DP automatic setting mode therein. Fig. 6(A) designates a color video signal V in of one horizontal period, which is supplied to the video signal input terminal 1, Fig. 6(B) designates R-Y signal or (B-Y signal) which is output from the demodulation circuit 6, Fig. 6(C) designates a timing signal T (=T (c) ) output from the timing signal generation circuit, and Fig. 6(D) designates a horizontal sweep signal S output from the horizontal sweep signal generator 14. It is assumed that reference amplitude value E (c)ref and reference angle  (c)ref of a chroma signal are previously set and stored in specified respective addresses in the memory 12. In Step S 7 in Fig. 7(A), when either of the DG key or the DP key on the manipulation panel is depressed, DG/DP automatic setting mode will be activated. Then in Step S 8 , the switching circuit 15 is controlled to connect to the V/DP terminal while the switching circuits 16 and 17 are controlled to connect to the V terminals. The signal generation timing of the timing signal generation circuit 7 is changed to a chroma mode so that the timing signal generation circuit 7 generates the timing signal T as the signal T (c) in the chroma signal timing interval shown in Fig. 6(C) by monitoring R-Y signal or B-Y signal output from the demodulation circuit 6. By receiving the timing signal T (c) , the amplitude detection circuits 8 and 9 detect the levels of the amplitudes of the chroma signal components R-Y (c) and B-Y (c) of the R-Y signal and B-Y signal output from the demodulation circuit 6, and then the amplitude levels are converted into digital amplitude signals E R-Y(c) and E B-Y(c) , in Step S 9 . These amplitude signals E R-Y(c) and E B-Y(c) are input in Step S 10 to the CPU11 which, in turn, computes the amplitude value E (c) of the chroma signal by computing the square root of E R-Y(c) 2 + E B-Y(c) 2 , that is: E ( c ) = E R - Y ( c ) 2 + E B - Y ( c ) 2 In Step S 11 , the difference ΔE (c) between the computed amplitude value E (c) and the reference amplitude value E (c)ref read out from the memory 12 is computed, and if the difference ΔE (c) is not zero, the gain of the variable gain circuit 3 is so controlled that the difference will be zero in Step S 12 . Again in Step S 9 , the amplitude value E (c) is computed and thus, Steps S 9 through S 12 will be repeatedly executed until ΔE (c) =0 is detected in Step S 11 . If ΔE (c) is attained in Step S 11 , the amplitude E (c) of the vector representation of the chroma signal has coincided with the reference amplitude value E (c)ref which has been stored in the memory 12. Next, the process proceeds to Step S 13 in Fig. 7(B), where it is detected whether the depressed key is DG key or DP key. When the DG key has been depressed, a DG mode is exercised in Step S 14 . In this DG mode, the switching circuits 15 through 17 are subjected to connect to DG terminals, which causes a horizontal axis of the display screen to be driven by the horizontal sweep signal S, shown in Fig. 7(D), coming from the horizontal sweep signal generator 14 and the vertical axis to be driven by an amplitude signal through the amplifier 18, whereby the amplitude level of one horizontal cycle is displayed on the display screen as shown in Fig. 8(A). If it is detected that the DG key has not been depressed, the process proceeds from Step S 13 to Step S 15 . It is to be understood that in the case that DG key is decided not to be depressed in Step S 13 , it means that the DP key has been depressed. The switching circuit 15 remains as connected to the V/DP terminal while the switching circuits 16 and 17 remain as connected to the V terminals. In Step S 15 , the amplitudes of the R-Y (c) signal and B-Y (c) signal are detected, and in Step S 16 , using the digital amplitude signals E R-Y(c) and E B-Y(c) supplied from the A/D converter to CPU11, the phase or the angle  (c) of vector representation of the chroma signal is calculated as follows. ⊖ ( c ) = cos -1 E B - Y ( c ) E R - Y ( c ) 2 + E B - Y ( c ) 2 Next, in Step S 17 , the difference Δ (c) between the acquired angle  (c) and the reference angle  (c)ref , or Δ (c) =  (c)ref -  (c) , will be calculated so as to decide whether the difference Δ (c) is zero or not. If the difference is not zero, the process proceeds to Step S 18 to control the phase shift value at the digital phase shifter 5 so that the difference  (c) may be zero. Steps S 15 through S 18 are repeatedly performed, until Δ (c) =0 is obtained in Step S 17 . By this phase adjustment, the angle  (c) of the vector representation of the chroma signal may be made to coincide with the reference angle  (c)ref . When Δ (c) =0 is decided in Step S 17 , a DP mode is executed in Step S 19 . In this DP mode, the switching circuit 15 remains to connect to the V/DP terminal while the switching circuits 16 and 17 are switched to DP terminals whereby the horizontal axis of the display screen is driven by the horizontal sweep signal S as shown in Fig. 6(D) coming from the horizontal sweep signal generator 14 and the vertical axis is driven by the R-Y signal which has been amplified by the amplifier 19. Accordingly, the phase level of the color video signal is displayed on the display screen as shown in Fig. 8(B). It is also possible to respectively execute Steps S 15 and S 13 immediately after Steps S 11 and S 17 , wherein Steps S 14 and S 19 are respectively connected with YES branch and NO branch of Step S 13 . In this case, it is also possible to perform Steps S 15 - S 18 before Steps S 9 - S 12 . As explained above, by executing Steps S 7 - S 19 shown in Figs. 7(A) and 7(B), the amplitude and angle of the vector representation of the chroma signal can be automatically adjusted to the reference amplitude and angle E (c)ref and  (c)ref , and thus the tip end of the vector representation can be coincided with, for instance, a reference point "0" of the graduation "b" on the display screen shown in Fig. 1. Therefore, the DG and DP values can be measured by reading out the valves from the graduation "b". Further, the DG and DP levels of the color video signal can be displayed at an optimum level. Since the present invention is constituted as above explained, a vector representation of a burst signal contained in a color video signal may be automatically and precisely adjusted to a given amplitude. Further, a vector representation of a chroma signal can be automatically and precisely set to a given amplitude and angle (or phase). Accordingly, operability of a vector scope may be enhanced and there will not be caused any specific difference in positioning accuracy for users. In particular, in the circuit shown in Figs. 5(A) and 5(B), since it is able to comply with both the BSAAS mode and DG/DP automatic setting mode, an area required for the circuit can be made smaller in comparison with separate circuits which can carry out the same modes as in the subject circuit. The invention has been described in detail with particular reference to certain preferred embodiments, but it will be understood that variations and modifications can be effected with in the scope of the invention.

Claims: A signal processing circuit for a vector scope adapted to display and measure characteristics of a color video signal on a screen, the circuit including a variable gain means for amplifying a color video signal input thereto and a demodulation circuit for demodulating the amplified color video signal to provide first and second chrominance signals to vertical and horizontal drive circuits of the screen, respectively, charracterized in that the signal processing circuit further comprises: amplitude detection means for detecting at least one of amplitudes of burst and chroma signals contained in the color video signal in response to the first and second chrominance signals; memory means for storing at least one of reference amplitudes of the burst and chroma signals; and gain adjusting means for comparing the detected amplitude of the burst or chroma signal with the corresponding reference amplitude stored in the memory means and for adjusting the gain of the variable gain means so that the compared amplitudes coincide with each other. A signal processing circuit according to Claim 1, characterised in that the signal processing circuit further comprises timing signal generation means for generating at least one timing signal during a time period associated with the burst or chroma signal of the color video signal; and the amplitude detection means comprises: means for detecting amplitudes of the first and second chrominance signals at the generation of the timing signal; and means for calculating the amplitude of the burst or chroma signal on the basis of the detected amplitudes of the first and second chrominance signals. A signal processing circuit according to Claim 1 or 2, further comprising: phase detection means for detecting at least one of phases of burst and chroma signals contained in the color video signal in response to the first and second chrominance signals; memory means for storing at least one of reference phases of the burst and chroma signals; and phase adjusting means for comparing the detected phase of the burst or chroma signals with the corresponding reference phase stored in the memory means and for adjusting a phase-shift value of a sub-carrier at a phase-shift means so that the compared phases coincide with each other. A signal processing circuit according to Claim 3 depending on Claim 2, characterised in that the timing signal generation means is adapted to generate the timing signals associated with the burst or chroma signal, respectively: the amplitude detection means is adapted to detect the amplitudes of the burst or chroma signal at the generated corresponding timing signals, respectively: and the phase detection means is adapted to detect the phases of the burst or chroma signal at the generated corresponding timing signals, respectively. A signal processing circuit according to any one of Claims 1-4, further characterised by means for detecting a synchronizing signal of the video signal: means for generating a sweep signal in response to the detected synchronizing signal: first switching means for selectively applying the first chrominance signal and sweep signal to the horizontal drive circuit; and second switching means for selectively applying the second chrominance signal and a signal representing the amplitude of the color video signal to the vertical drive circuit.

Inventors: HIKA YOSHIMICHI, IKUZAWA KENZO, HIKA, YOSHIMICHI, IKUZAWA, KENZO, HIKA, YOSHIMICHI, C/O LEADER ELECTRONICS CORP., IKUZAWA, KENZO, C/O LEADER ELECTRONICS CORP.
Applicants: LEADER ELECTRONICS, LEADER ELECTRONICS CORP.
Application year: 1995
Main classification: H04N17
IPC codes: G01R13, H04N17, G01R31