A/D Converter

Abstract: An A/D converter comprises of the first inverter having a linear characteristic and receiving an analog input voltage, the first quantizing circuit for outputting a quantized output of the analog input voltage, a capacitive coupling to which an output of the first inverter and the first quantizing circuit are inputted, the second inverter receiving an output of the capacitive coupling and having the same characteristic of the first inverter, and the second quantizing circuit receiving an output of the second inverter and quantizing an output of the second inverter.

Description: The inventors of the present invention have proposed an A/D converter circuit in Japanese Patent Application Hei No. 06-08784 and US Patent Application No. 08/261,904. The A/D converter, as shown in Figure 5, has a plurality of thresholding circuits 11 to 13 with different and stepwise threshold voltages. A thresholding circuit is inputted an analog input voltage A and outputs of higher thresholding circuits, for example, the thresholding circuit 13 receives the input voltage A and the outputs of thresholding circuits 11 and 12. Each thresholding circuit outputs inverted or non-inverted output in response to the value of the input voltage A and whether the higher thresholding circuit, and the output is periodically y changed along with the increase of the input voltage. The outputs of the thresholding circuits correspond to bits of the digital output, which are summed with weighting by a capacitive coupling so that a discrete or quantized analog voltage corresponding to the input voltage is obtained. The accuracy of the A/D converter circuit depends upon thresholding accuracy of each thresholding circuit and upon accuracy of capacitive coupling for summing the outputs of the thresholding circuits. It is rather difficult to control the accuracy of these parts during LSI manufacturing process. US 5,274,377 describes a pipelined A/D converter comprising a first inverter having a linear characteristic and receiving an analog input voltage and a first quantizing circuit for outputting a quantized output of said analog input signal. In the proceedings of the IEEE 1994 Custom Integrated Circuits Conference, pages 499-502, May 1-4, 1994, another typical pipeline A/D converter architecture is described. As can be seen from figure 1, it consists of a cascade of identical stages of which each stage performs a coarse quantization, a D/A function on the quantization result, subtraction and amplification of the remainder. As can be seen from figure 1 and the accompanying text, the quantized analog voltage is subtracted from the signal by connecting the bottom plate of each capacitor to ± Vref or 0. The object of the present invention is to provide an improved A/D converter circuit for generating a highly accurate digital output. This object is achieved by an A/D converter circuit according to claim 1. Further embodiments are given by the subject-matter of the dependent claims. In the following two preferred embodiments of the present invention are illustrated by means of the accompanying figures. Figure 1 is a circuit diagram showing the first embodiment of A/D converter according to the present invention. Figure 2 is a circuit diagram of a quantizing circuit in figure 1, Figure 3 is an equivalent circuit showing the influence of parasitic capacity, Figure 4 is a block diagram showing the second embodiment of the present invention, and Figure 5 is a block diagram showing the conventional A/D converting circuit. Hereinafter, an embodiment of an A/D converter circuit according to the present invention is described with referring to the attached drawings. In Figure 1, an AID converter circuit has two sequential inverted amplifiers INV1 and INV2 which are connected with feedback capacitances Cf1 and Cf2, respectively, for feeding an output of the amplifier back to an input. A coupling capacitance C01 is connected to an input terminal of INV1 to which an analog input voltage Vin is connected. A coupling capacitance C02 is connected between an output terminal of INV1 and input terminal of INV2. The output of INV1 is connected to INV2 through C02. INV1 and INV2 consist of 3 stages MOS inverters I1, I2 and I13 and inverters I4, I5 and I6, respectively, so the inverters INV1 and INV2 have a high gain given by a product of open gains of these inverters of 3 stages. The output of INV1, designated by V1, is determined by a ratio of CO1 and Cf1, as shown by the formula 1. FORMULA 1 V 1= - C 01( Vin - Vb ) Cf 1 + Vb Besides the signal line through the inverters INV1 and INV2, there is provided a quantizing circuit parallel to the inverter INV1. The input voltage Vin is branched before the capacitance CO1 and inputted to the quantizing circuit Q11 an output of which is inputted to INV2 through capacitive coupling CP1. Quantizing circuit Q11 converts Vin into a binary number of a plurality of bits (4 bits in the present embodiment), and outputs binary bits b1, b2, b3 and b4 that are integrated by the capacitive coupling CP1. Capacitive coupling CP1 has capacitances Cq1, Cq2, Cq3 and Cq4 for receiving the binary bits from b1 to b4. Both outputs from Cp1 and C02 are parallelly inputted to INV2. When input voltage of INV2 is defined as V2 and output voltage is defined as Vo, then the following formula 2 is obtained. FORMULA 2 Here, a unit capacitance Cu can be defined as the minimum capacity shaped in a LSI, with relationships that C01=C02=Cf1=16Cu, Cf2=Cu, Cql=Cu, Cq2=2Cu, Cq3=4Cu and Cq4=8Cu, then Formula 3 is obtained. FORMULA 3 The formula (3) means that binarized data Vin of 4 bits is subtracted from the analog data Vin. The output Vo of INV2 is an analog data corresponding to lower 4 bits, while the digital data from Q11 is higher 4 bits. V0 is inputted to the second quantizing circuit Q12 which performs the second stage binarization of 4 bits. Q12 outputs a binarized data consisting of 4 bits a1, a2, a3 and a4. These data is the lower 4 bit of Vin. Hereinafter, the quantizng circuit Q11 is described. Since the quantizing circuits Q11 and Q12 are similar to each other, only Q11 is described referring to Figure 2. Quantizing circuit Q11 is composed of four thresholding circuits Th1 to Th4 shown in Figure 2, which generate outputs b1, b2, b3 and b4, respectively. Inverted outputs b1', b2', b3' and b4' of the outputs b1 to b4 are generated as intermediate data inside. In Figure 2, the most lowest thresholding circuit Th1 has capacitive coupling CP2 receiving Vin, b2', b3' and b4'. Three stages sequential inverters I211, I212, I213 are connected to an output of CP2. The output b1 is generated as an output of inverter I212 of second stage. An inverted output b1' is generated as an output of inverter I213 of the final stage. CP2 consists of capacitances C11a, C11b, C11c, C11d, C11e and C11f which are connected to Vin, b4', b3', b2', Vdd and the ground, respectively. Vdd is the reference voltage Vdd for controlling a threshold value of INV31. The voltage of the ground is provided for controlling the total capacity of CP2. Thresholding circuit Th2 of the second threshold from the minimum threshold has capacitive coupling CP3 receiving Vin, b3' and b4'. Three stage sequential inverters I221, I222 and I223 are connected to an output of CP3. An output b2 is generated as an output of inverter I222 of the second stage. An inverted output b2' is generated as an output of the final inverter I223. CP3 consists of capacitances C12a, C12b, C12c, C12d and C12e which are connected to Vin, b4', b3', Vdd and the ground, respectively. Vdd is the reference voltage for controlling a thresholding value of INV41. The voltage of the ground is provided for controlling the total capacity of CP3. Thresholding circuit Th3 of the third threshold from the minimum threshold has capacitive coupling CP4 receiving Vin' and b4'. Three stage sequential inverters I231, I232 and I233 are connected to an output of CP4. An output b3 is generated as an output of inverter I232 of the second stage. An inverted output b3' is generated as an output of the final inverter I233. CP4 consists of capacitances C13a, C13b, C13c and C13d which are connected to Vin, b4', Vdd and the ground, respectively. Vdd is the reference voltage for controlling a thresholding value of INV51. The voltage of the ground is provided for controlling total capacity of CP4. Thresholding circuit Th4 of the highest threshold has capacitive coupling CP5 receiving Vin. Three stage sequential inverters I241, I242 and I243 are connected to an output of CP5. An output b4 is generated as an output of inverter I242 of the second stage. An inverted output b4' is generated as an output of the final inverter I243. CP5 consists of capacitances C14a, C14b and C14c which are connected to Vin, Vdd and the ground, respectively. Vdd is the reference for controlling a thresholding value of INV61. The voltage of the ground is provided for controlling the total capacity of CP5. A capacity of each capacitance of CP2 to CP5 is shown in TABLE 1, and a relationships between Vin and the outputs b1, b2, b3 and b4 and a relationship between Vin and intermediate outputs b1', b2', b3' and b4' are shown in TABLE 2. It is not necessary that Cu in Table 1 is the minimum capacity. Any other capacity can be used available as far as the unit capacity is common for all capacitances in every capacitive couplings. TABLE 2 shows voltage (Vdd/16) as Va. CAPACITIVE COUPLING CAPACITANCE CAPACITY CP2 C11a 16Cu C11b 8Cu C11c 4Cu C11e 2Cu C11d Cu C11f Cu CP3 C12a 8Cu×2 C12b 4Cu×2 C12c 2Cu×2 C12d Cu×2 C12e Cu×2 CP4 C13a 4Cu×4 C13b 2Cu×4 C13c Cu×4 C13d Cu×4 CP5 C14a 2Cu×8 C14b Cu×8 C14c Cu×8 INPUT VOLTAGE INTERMEDIATE VOLTAGE OUTPUT in b1' b2' b3' b'4 b1 b2 b3 b4 0 ≦ Vin < Va Vdd Vdd Vdd Vdd 0 0 0 0 Va ≦ Vin < 2Va 0 Vdd Vdd Vdd Vdd 0 0 0 2 Va ≦ Vin < 3Va Vdd 0 Vdd Vdd 0 Vdd 0 0 3 Va ≦ Vin < 4Va 0 0 Vdd Vdd Vdd Vdd 0 0 4 Va ≦ Vin < 5Va Vdd Vdd 0 Vdd 0 0 Vdd 0 5Va ≦ Vin < 6Va 0 Vdd 0 Vdd Vdd 0 Vdd 0 6Va ≦ Vin < 7Va Vdd 0 0 Vdd 0 Vdd Vdd 0 7Va ≦ Vin < 8Va 0 0 0 Vdd Vdd Vdd Vdd Vdd 8Va ≦ Vin < 9Va Vdd Vdd Vdd 0 0 0 0 Vdd 9Va ≦ Vin < 10Va 0 Vdd Vdd 0 Vdd 0 0 Vdd 10Va ≦ Vin < 11Va Vdd 0 Vdd 0 0 Vdd 0 Vdd 11Va ≦ Vin < 12Va 0 0 Vdd 0 Vdd Vdd 0 Vdd 12Va ≦ Vin < 13Va Vdd Vdd 0 0 0 0 Vdd Vdd 13Va ≦ Vin < 14Va 0 Vdd 0 0 Vdd 0 Vdd Vdd 14Va ≦ Vin < 15Va Vdd 0 0 0 0 Vdd Vdd Vdd 15Va ≦ Vin < 16Va 0 0 0 0 Vdd Vdd Vdd Vdd The above quantizing circuit Q11 generates outputs b1 to b4, and outputs a1 to a4 are generated by Q12 in the same way. Then, analogue to digital conversion is realized. The quantizing circuit Q12 generates the lower 4 bits of the digitized data so that high accurate digital output can be generated even when capacitances of capacitive couplings are not so high in the accuracy. By the quantizing circuits of multi-stages, the highly accurate digital outputs can be easily obtained. The outputs of the thresholding circuits Th1 to Th4 sharply change by high gain of the multi-stage inverters. If four stages inverters are applied instead of 3 stages of Figure 2, sharpness is highered. In this case, outputs b1 to b4 are obtained from the final stage inverters. In the Table 1, the total capacity value of capacitances in the capacitive couplings are 32Cu equal to one another so that the influence of parasitic capacity of inverters I211, I221, I231 and I241 is negligible. In Figure 3, When it is designated that parasitic capacitances of inverters are Cpa1 at the power source side, Cpa2 at the ground side and Cpa3 at the output side and that capacity of capacitances of the capacitive coupling connected to an input of the inverters are W1 to Wn and input voltage to these capacitances are V1 to Vn, the input voltage VA1 to an inverter caused by the input voltage A(=V1) is defined as in FORMULA 4. FORMULA 4 According to an experience, Voo is equal to 0 as shown in FORMULA 5, then Formulas 6, 7 are defined. FORMUAL 5 Voo=0 FORMULA 6 FORMULA 7 VA 1 = ( W 1 V 1 + WddVdd ) / ( W 1 + Wdd + Cpa 2 + Cpa 3) Since the ratio of Cpa1 in Wdd is small, and deviation of the parasitic capacity is generally small, VA1 is not influenced by the parasitic capacity as far as the total capacity (W1+Wdd) of the capacitive coupling is constant. The circuit of Figure 1 includes a low-pass capacitance Clp and equiribium registences R1 and R2 in order to prevent unstable oscillation of the inverter circuit. In the figure, R1 and R2 are connected to a juncture between the second and the third inverters. It is also possible to connected the resistances to a juncture of the first and the second inverters. The resistance R1 is connected to the power source Vdd and R2 is connected to the ground. The high-pass capacitance is connected between the output of the inverter and the grounds. Figure 4 is the second embodiment of the present invention, in which the first stage inverted amplifier of the first embodiment is omitted. An A/D converter 2 has an inverted amplifier INV3 an output of which is connected to its input through a feed back capacitance Cf3. The input terminal of INV3 is connected to a coupling capacitance C03 and the analog input voltage Vin is connected to C03. INV3 is composed of inverters I7 to I9 of three stages and has a large gain given by a multiplication of these inverters' open gain. Input voltage Vin is inputted to quantizing circuit Q21 after branching in the front stage of C03, and an output of Q21 is inputted to INV3 through a capacitive coupling CP6. Q21 converts Vin into a binary number of 4 bits (d4, d3, d2 and dl), and binary bits of its inverted output d1', d2', d3' and d4' are integrated by the capacitive coupling CP6. The capacitive coupling CP6 has capacitances Cr1, Cr2, Cr3 and Cr4 which receive d1', d2', d3' and d4', respectively. Outputs of C03 and Cp6 are parallelly inputted to INV3. When an input voltage of INV3 is V3 and an output of it is Vo, formula 8 is obtained. FORMULA 8 Here, an unit capacitance is Cu, C03=16Cu, Cf3=Cu, Crl=Cu, Cr2=2Cu, Cr3=4Cu, Cr4=8Cu, then formula 7 is obtained. FORMULA 9 The formula (9) means that binarized data Vin of 4 bits is subtracted from the analog data Vin. The output Vo of INV3 is an analog data corresponding to lower 4 bits, while the digital data from Q21 is higher 4 bits. V0 is inputted to the second quantizing circuit Q22 which performs the second stage binarization of 4 bits. Q12 outputs a binarized data consisting of 4 bits a1, a2, a3 and a4. These data is the lower 4 bit of Vin. Quantizing circuit Q21 is similarly constructed to the quantizing circuit Q11, and the outputs of the final stage of the thresholding circuits are outputted as d1' to d4'. They are inputted to other thresholding circuit as intermediate data. The quantizing circuit Q22 is similar to Q11 the outputs a1, a2, a3 and a4 of the final stage are inputted to other thresholding circuits. According to the second embodiment, the same performance is obtained as the first embodiment with a circuit of small size. The present invention is invented so as to solve the conventional problems and A/D converter circuit according to the present invention performs successive steps of digitizing, the analog input voltage is subtracted from each digitized output for the next input of digitizing, so that it has an object to provide an A/D converter circuit for generating a highly accurate digital output.

Claims: An A/D converter comprising: a first quantizing circuit (Q11, Q21) receiving an analog input voltage (Vin) for outputting a quantized output of said analog input voltage (Vin); a first inverter (INV2, INV3) having a linear characteristic and being connected with its input to the output (b1-b4, d'1-d'4) of said quantizing circuit (Q11, Q21) via a first capacitive coupling means (Cq1-Cq4, Cr1-Cr4), a second quantizing circuit (Q12, Q22) providing a quantized output (Q1-Q4) of the output voltage (Vo) of said first inverter (INV2, INV3), characterized in that said analog input voltage (Vin) is inputted into said first inverter (INV2, INV3) via a second permanent capacitive coupling means (C02, C03). parallel to said first capacitive coupling means (C q 1-C q 4, Cr1-Cr4) The A/D converter according to claim 1, characterized in that said A/D converter further comprises a second inverter (INV1), said second inverter (INV1) being connected parallel to the series circuit consisting of said first quantizing circuit (Q11) and said first capacitive coupling means (Cq1 to Cq4). The A/D converter according to claim 2, characterized in that said first and second inverters, (INV1, INV2) comprise an odd number of at least 3 serially connected CMOS inverters (I211, I212, I213, I221). The A/D converter according to claim 1 or claim 2, characterized in that said quantizing circuits (Q11, Q12, Q21, Q22) comprise a plurality of thresholding circuits (Th1 to Th4) with thresholds stepwisely differing from one another, one thresholding circuit (Th1 to Th3) receiving all weighted outputs of the thresholding circuits with higher thresholds (Th2 to Th4) than said one thresholding circuit so that said one thresholding circuit (Th1 to Th4) repeatedly changes the output from inverted to non-inverted and vice versa in a constant cycle as said input voltage (Vin) is increased linearly. The A/D converter according to claim 4, characterized in that said thresholding circuits (Th1 to Th4) perform weighting by capacitive couplings (CP2 to CP5), the total capacity of each capacitive coupling (CP2 to CP5) being equal to one another.

Inventors: MOTOHASHI KAZUNORI, SHOU GUOLIANG, TAKATORI SUNAO, YAMAMOTO MAKOTO, MOTOHASHI, KAZUNORI, SHOU, GUOLIANG, TAKATORI, SUNAO, YAMAMOTO, MAKOTO, Motohashi, Kazunori, c/o Yozan Inc., Shou, Guoliang, c/o YOZAN Inc., TAKATORI, SUNAO, C/O YOZAN INC., YAMAMOTO, MAKOTO, C/O YOZAN INC.
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1995
Main classification: H03M1
IPC codes: H03M1