Linearly regulated voltage multiplier

Abstract: A regulating circuit for the output voltage of a voltage booster, of the type which comprises a first charge transfer capacitor (C1) adapted to draw electric charges from the supply terminal (2) and transfer them to the output terminal (3), through electronic switches controlled by non-overlapped complementary phase signals, and a second charge storage capacitor (C2) connected between the output terminal (3) and ground (GND), further comprises an error amplifier which generates, during one of the operational phases, a DC voltage corresponding to the difference between a reference voltage (Vrif) and a voltage (Vx) being a duplicate of the output voltage (Vout) of the voltage booster; this DC voltage is applied directly to one end of the transfer capacitor (C1).

Description: Field of the Invention This invention relates to a voltage multiplier or booster including an output voltage regulating circuit. Electronic systems quite often require that higher voltages than the supply voltage be generated internally thereof. This is the case, for example, with EEPROM memories, which require write voltages well above the conventional 5-volt supply, or with devices powered from low-voltage batteries, typically at 3 volts or less. The circuit that serves this function is known as the voltage multiplier or booster circuit, and is preferably provided within the integrated circuit. Background Art A conventional booster circuit, which is utilized in integrated circuits requiring a supply voltage multiplication factor of two, or at least an elevated supply voltage, comprises a charge transfer capacitor, which is switched by means of electronic switches driven by two phases of a clock generator, and a charge storage capacitor. That circuit can output fairly large currents (of up to a few tens of mA), and accordingly, is capable of generating a boosted voltage for supply to the integrated circuit as a whole or to a significant portion thereof. The clock generator utilized in association with that booster circuit generates two non-overlapping complementary phase signals. During the first phase, a supply voltage is applied to a first terminal of the transfer capacitor, while a second terminal of that same capacitor is connected to ground. During the second phase, the first terminal is cut off the supply, while the second terminal is disconnected from ground and connected to the supply voltage. In this way, the first terminal of the charge transfer capacitor is brought to a voltage level twice as high as the supply voltage. This boosted voltage is used for charging a charge storage capacitor. At the end of the second phase, the first terminal of the charge transfer capacitor is disconnected from the storage capacitor and coupled back to the supply voltage. The voltage that appears on the charge storage capacitor is the boosted output voltage from the voltage booster. With a zero current delivery, the output voltage Vout would obviously be twice as high as the supply voltage and become perfectly stable already after a few clock cycles. However, in the presence of a current on the load, the value of the output voltage is affected by the voltage drops across the capacitors and the switches provided for switching the capacitors. These voltage drops vary with the value of the output current, the process used, and the operating temperature. Further, any variations in the supply voltage, such as are typical to occur in systems powered from nickel-cadmium batteries, reflect on the booster output voltage, doubled or at least amplified in magnitude. It is quite often desirable, or even necessary, that the boosted output voltage be held constant as the current on the load and the value of the supply voltage Vbat vary. In such cases, the output voltage must be stabilized by a specially provided regulating circuit. One prior solution which includes a circuit for providing a stabilized output voltage is disclosed in European Patent Application No. 92118084.0 filed on October 22, 1992 by Motorola, Inc. and published under No. 0540948 on May 12, 1993. The voltage booster disclosed in that patent application is of the same type as that just described, and the regulating circuit therein is implemented by a negative output voltage regulating loop. The regulating loop is provided by an integrator adapted to generate a DC error signal which is proportional to the difference between the output voltage from the voltage booster and a reference voltage. This error signal is used to drive (at a conduction phase of the booster circuit operational cycle) the control gate of a MOS transistor, which functions as a switch to connect the charge transfer capacitor to the supply voltage, by controlling its internal resistance, and hence, the charge time constant of the capacitor. In this way, the output voltage of the voltage booster circuit can be held constant, in the steady state condition, at a proportional value to the reference voltage. A major problem encountered with this prior solution is that the dependence of the voltage applied to the control gate of a MOS transistor on the internal resistance of the latter is markedly non-linear. The presence of this non-linear element makes the regulating loop non-linear. As skilled persons in the art will readily recognize, a non-linear feedback loop may pose significant "lockup" problems, i.e. problems with the attainment of the proper output voltage value from the moment the circuit is turned on, and problems with holding this output voltage constant against the occurrence of sharp current variations on the load. Another prior solution, disclosed in European Patent Application No. 94830413.4 filed on August 31, 1994 by SGS-Thomson Microelectronics sr1 and published under No EP0 700 146 on March 06, 96, provides a voltage booster including a linear type of output voltage regulating circuit. This patent application describes a voltage booster circuit, illustrated in some detail by Figure 1, of a type comprising a charge transfer capacitor C1 which is switched, similar to the previously discussed circuit, between two phases of a clock signal, so as to have a charge storage capacitor C2 charged at a boosted voltage Vout relative to the booster supply voltage Vbat. The output voltage is controlled by a linear regulating loop which comprises an integrator adapted to generate an error signal of the difference between a reference voltage Vrif and a proportional voltage Vx to the output voltage Vout. This error signal is applied, during one of the two operational phases, directly to the bottom plate of the charge transfer capacitor C1 so as to supply a variable voltage on that plate which allows the output voltage to be held at a constant value. The integrator comprises an operational amplifier OA whose inverting input is connected to the center node of a voltage divider R1-R2 and to the output of the amplifier through a series of a resistor RZ, an integration capacitor CI, and a transfer switch or gate M7-M8. The non-inverting input is connected, through a switch M9, to a reference voltage Vrif, and through another switch M10, to a ground potential. Plotted in Figure 2 are timing diagrams for the control phases utilized in the circuit of Figure 1. As can be seen, phases F1 and F2 are non-overlapping complementary phases, phase F1_neg is substantially coincident with phase F1sur_neg, and phase F2_neg is essentially coincident with phase F2sur_neg. The phases F1sur_neg and F2sur_neg are commonly generated by a timing circuit being supplied the voltage Vout which is a boosted voltage relative to the supply voltage Vbat. In other words, the drive phases F1sur_neg and F2sur_neg are boosted phases. The MOS transistors M5 and M6 are driven by the phase signals F1sur_neg and F2sur_neg, the transistors M7 and M8 are driven by the phase signal F2 and its complement, the transistor M9 is driven by the phase signal F2, and the transistor M10 is driven by the phase signal F1. During the phase F1, the bottom plate of the capacitor C1 is forced to ground potential by the operational amplifier OA having its feedback loop open and non-inverting input connected to ground, while the top plate of the capacitor C1 is connected to the supply voltage Vbat. In this way, the capacitor C1 will be charged at the voltage Vbat. During the phase F2, the non-inverting input of the operational amplifier OA is brought to the voltage Vrif by the closed transistor M9, and concurrently therewith, the feedback loop of the amplifier OA is closed. Thus, the output voltage from the amplifier OA will reach a proportional value to the integral of the error between the voltage Vrif and the voltage Vx=Vout*(r1/(R1+R2) . The bottom plate of the capacitor C1 will, therefore, be at a suitable voltage value to bring the output voltage to the desired value, Vout = Vrif * ( (R1 + R2) / R1 ) The initial settling time period upon turning on this circuit, being typically on the order of 500 microseconds, is a relatively short one compared to the settling time period of the previously discussed voltage boosters. These voltage booster circuits are usually integrated on the same slice of semiconductor material, or chip, along with the electronic devices to be powered thereby. In the circuit of Figure 1, as well as in the other circuits previously discussed, the two capacitors C1 and C2 cannot be integrated because they would occupy too large an amount of the chip area due to their high capacitance value. All the other components, namely the operational amplifier OA, MOS transistors utilized as electronic switches, resistors, and integration capacitor CI, are instead integrated on the chip. The underlying technical problem of this invention is to provide a voltage multiplier or booster for relatively large output currents, which includes a linear type of output voltage regulating circuit, has a very short settling time, and has a simpler circuit construction than prior art devices, so as to facilitate its integration on silicon and afford a significant saving in chip area. This technical problem is solved by a voltage booster circuit as indicated in the preamble and defined in the characterizing portions of Claims 1 to 8. The booster circuit of this invention can be used for powering semiconductor electronic devices whose supply voltage needs boosting; by reason of its small size, the inventive circuit being advantageously integratable along with the circuit that it is expected to power. The features and advantages of a circuit according to the invention will be apparent from the following detailed description of an embodiment thereof, given by way of non limitative example with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 shows a functional diagram of a voltage booster circuit provided with an output voltage regulating circuit, according to the prior art; Figure 2 shows the waveform of the drive phases utilized in the circuit of Figure 1; Figure 3 shows a functional diagram of a voltage booster provided with an output voltage regulating circuit, according to this invention; Figure 4 shows the waveform of the drive phases utilized in the circuit of Figure 3; and Figure 5 is a timing diagram of the output voltage from the voltage booster circuit shown in Figure 3. Detailed Description With reference to the drawing figures, and in particular Figure 3, generally shown at 1 is a voltage booster which embodies the invention. This booster comprises a charge transfer capacitor C1 which is switched, as by means of electronic switches controlled by two phases of a clock signal generator, for charging a charge storage capacitor C2 at a boosted voltage Vout with respect to the supply voltage Vbat. The four transistors M1, M2, M3 and M4 serving as electronic switches are transistors of the MOS type, and have each a source terminal, a drain terminal, a gate or control terminal, and a substrate contact. In particular, the transistors M1 and M2 are p-channel MOS transistors, whereas the transistors M3 and M4 are n-channel MOS transistors. A first one, M1, of the MOS transistors has its source terminal connected to the supply terminal 2 of the booster, its drain terminal and substrate contact connected to a first terminal of the charge transfer capacitor C1, and receives a first clock signal F1sur_neg on its gate terminal. The first terminal of the capacitor C1 is also connected to the source of a second MOS transistor, M2, driven by a second clock signal F2sur_neg. The second transistor M2 has its drain terminal and substrate contact connected to the output terminal 3 of the booster. Connected across the output terminal 3 and a ground reference GND of the circuit are the charge storage capacitor C2 and a voltage divider formed of the two resistors R1 and R2. The intermediate node between the two resistors, R1 and R2, is connected to an inverting terminal of an operational amplifier OA. A non-inverting input of the operational amplifier OA is connected, through a third transistor M3 driven by a third clock signal F1, to the ground reference GND, and through a fourth transistor M4 driven by a fourth clock signal F2, to a voltage reference Vrif. The output of the operational amplifier OA is connected to a second terminal of the charge transfer capacitor C1. The clock signals F1, F2, F1sur_neg and F2sur_neg are generated by a non-overlapped phase clock signal generator of a conventional type, and are indicated on the timing diagram of Figure 4. The signals F1 and F2 are non-overlapped phase signals complementary of each other, the signal F1sur_neg is a negated signal which is voltage-boosted with respect to the signal F1, and F2sur_neg is a negated and voltage-boosted signal with respect to the signal F2. The logic level of the voltage-boosted signals is equal to the boosted voltage Vout present at the voltage booster output. During the phase F1, the transistors M1 and M3 are in the conduction state, whereas the transistors M2 and M4 are in the cutoff state. The first terminal of the capacitor C1 is connected to the supply voltage, while its other terminal is forced to ground potential by the operational amplifier OA having its non-inverting input connected to ground. The capacitor C1 is, therefore, charged at the voltage Vbat during the phase F1. During the phase F2, the transistors M1 and M3 are cut off, and the transistors M2 and M4 are conducting; the first terminal of the capacitor C1, disconnected from the supply terminal 2, is connected to the output terminal 3 of the booster, while the second terminal is brought to the potential present at the output of the operational amplifier OA. During this phase, the operational amplifier OA functions, in combination with the capacitor C1 and the resistors R1 and R2, as an error amplifier to integrate the difference between the reference voltage Vrif and the voltage Vx present at the center node of the divider R1-R2. In particular, with the transistor M2 in the conducting state, the capacitor C1 and resistor R2 form a feedback loop between the output and the inverting input of the amplifier OA. The conduction resistance of the transistor M2 is much lower than the resistance of R2, and therefore, negligible. The non-inverting input of the amplifier OA is connected, through the transistor M4, to the voltage reference Vrif. The voltage Vrif is set by a conventional voltage generator effective to supply a voltage which is stable versus temperature and independent of any variations in the supply voltage, while the voltage Vx is a duplicate of the output voltage Vout as given by the following formula: Vx = Vout * ( R1 / (R1 + R2) ) The high value of the DC gain of the feedback loop of the operational amplifier OA forces the output voltage Vout to attain the value sought, namely: Vout = Vrif * ( (R1 + R2) / R1 ). By suitably selecting the resistances of R1 and R2, the output voltage Vout can be regulated for the desired value. By virtue of the linearity and the simplicity of the regulating circuit, this output voltage value is attained, upon turning on the circuit, within a very short time period, as indicated by the timing diagram of Figure 5. That diagram illustrates the pattern for the output voltage Vout over time, after the circuit is turned on. In particular, it can be seen that the output voltage Vout rises to the desired value of 4.45 volts, from an initial voltage of 3 volts being the equal of the circuit supply voltage, within 50 microseconds, a far shorter time than the 500 microseconds required by the conventional booster previously discussed and shown in Figure 1. Another advantage of the inventive booster circuit over the foregoing conventional circuits comes from its simple construction, resulting in a significant saving of silicon area at the time of its integration. A comparison of this circuit with the booster circuit of Figure 1 brings out that fewer components are used in the former: in particular, the integration capacitor CI, resistor RZ, and electronic switch formed of the transistors M7 and M8 have been eliminated. These components jointly accounted, in the previous integrated circuit, for approximately 50% of the overall area occupied by the voltage booster circuit. Accordingly, the integration area for the booster circuit of this invention can be greatly reduced. Furthermore, compared to the conventional booster circuit of Figure 1 -- which uses six different clock signals, as shown in Figure 2 -- the circuit of this invention uses only four clock signals, F1, F2, F1sur_neg and F2sur_neg. This allows the circuitry employed for implementing the clock signal generator to be also simplified.

Claims: A voltage booster (1), having an input terminal (2) for receiving a supply voltage (Vbat) and an output terminal (3) for supplying a boosted voltage (Vout) with respect to the supply voltage, and comprising: a charge transfer capacitor (C1); a first switch (M1) controlled by a first drive signal (F1sur_neg) to connect a first terminal of said charge transfer capacitor (C1) to the booster input terminal (2); a second switch (M2) controlled by a second drive signal (F2sur_neg) to connect the first terminal of said charge transfer capacitor (C1) to the booster output terminal (3); a charge storage capacitor (C2) connected between the output terminal (3) and a first voltage reference (GND); an error amplifier (4) having an input coupled to the booster output terminal (3) and an output coupled to a second terminal of the transfer capacitor (C1); characterized in that said error amplifier comprises an operational amplifier (OA) having a first input terminal coupled to the booster output terminal (3) and a second input terminal connected to the first voltage reference (GND) through a third switch (M3) controlled by a third drive signal (F1) and to a second voltage reference (Vrif) through a fourth switch (M4) controlled by a fourth drive signal (F2). A voltage booster according to Claim 1, characterized in that the first input terminal of the operational amplifier (OA) is an inverting input terminal and the second input terminal is a non-inverting input terminal. A voltage booster according to Claim 2, characterized in that the inverting input terminal of the operational amplifier (OA) is coupled to the booster output terminal (3) through a voltage divider (R1,R2). A voltage booster according to Claim 3, characterized in that the voltage divider comprises a first (R2) and a second (R1) resistor connected in series between the booster output terminal (3) and the first voltage reference (GND), the common terminal (Vx) between the two resistors being connected to the inverting input terminal of the operational amplifier (OA). A voltage booster according to Claim 4, characterized in that, during a conduction phase of the transistor M2, the transfer capacitor (C1) and first resistor (R2) form a feedback loop for the operational amplifier (OA) connected between the output and the inverting input of the latter. A voltage booster according to Claim 5, characterized in that the third (F1) and fourth (F2) drive signals are non-overlapped phase logic signals. A voltage booster according to Claim 6, characterized in that the first drive signal (F1sur_neg) is a voltage-boosted logic signal complementary of the third drive signal (F1), and the second drive signal (F2sur_neg) is a voltage-boosted logic signal complementary of the fourth drive signal (F2). A voltage booster according to Claim 1, characterized in that the first (M1) and second (M2) transistors are p-channel MOS transistors, and the third (M3) and fourth (M4) transistors are n-channel MOS transistors. A voltage booster according to Claim 1, characterized in that the first voltage reference (GND) is a ground voltage reference. A semiconductor electronic device powered from or incorporating a generator of boosted voltage, characterized in that it comprises a voltage booster as claimed in Claim 1.

Inventors: NICOLLINI GERMANO, NICOLLINI, GERMANO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: H02M3
IPC codes: H02M3