Memory architecture for solid state disc

Abstract: A solid state disc (SSD) Memory comprising the following functional blocks: a memory block (DATA ARRAY) wherein check data bytes are written; a transcoder memory block (SCRAMBLE RAM) which contains the table enabling the reallocation of the data matrix addresses, wherein redundant rows are included; a block (SCRAM DEC) for decoding the addresses of the decoder table; a logic block (FUSE LOGIC) to enable a step to be executed to locate any non-useable row and to substitute said redundant rows therefor; an error correction code (ECC) block for implementing the error correction algorithm; an input buffer block (LOGICAL ROW ADDRESS BUFFER) for storing the row addresses coming from the external bus; a non-volatile memory block, programmed during the test stage and available to a possible processor for handling the contents of the transcoder memory (SCRAMBLE RAM); a word counter block (WORD COUNTER) that is driven from the external clock signal (clock) and counts the number of the addressed words and generates the word addresses; two input and output buffer blocks (DATA IN/OUT) for the data to be written in or read out; a multiplexer block (MUX) by which the data stream is driven to the data memory (DATA ARRAY) or to the transcoder memory (SCRAMBLE RAM).

Description: This invention broadly relates to the memory field and more particularity concerns a novel memory architecture adapted for manufacturing solid state discs. Among the presently available techniques for mass storage of data, of increasing importance are solid state discs (SSD). These are structures in which commercial memory chips are used, usually intended to operate as resident memories and arranged so as to act as magnetic discs. It has been found that the utilisation of the presently available commercial memories (typically DRAM memories) produces an increase in the weight of the global structure of the solid state disc, and the need has been identified that a specific memory architecture be designed in order that an optimum operation of these systems be achieved. It should also be noted that the solid state discs should be compatible with the presently available mass storage systems, and, therefore, they should be structured as 512 byte blocks. In the state of the art, the memory devices have been considered as devices to be used as central nodes of systems which are directly interfaced with a microprocessor. This means that both the functionality and the electrical and logical interface have been designed so as to optimise communication between the central processing unit (CPU) and the cells of the memory device itself. As soon as other applications and other architectures are considered, the interface type and the functionality type may not be the optimum ones. Document US-A-5 321 697 discloses an improved solid state storage device with memory organised into a plurality of groups, each group including a plurality of ranks and each rank having at least two banks sharing a bi-directional data bus. A matrix reorder circuit is used to distribute data across individual memory components as to prevent multibit uncorrectable error due to failure of a single memory component. The matrix reorder circuit is used for both reading and writing data and operates on a stream of pipelined data of arbitrary length. Based upon the experimental work carried out in the field of the solid state discs, it is the broad object of this invention to design an optimum architecture, such that the whole design of a mass memory system based upon silicon memories is simplified. From this view point and also in efforts to ensure costs are minimised, it is important that the memory obtained should have an optimum grade of fault tolerance and a special relevance has been assigned in the present invention to incorporating suitable error correction mechanisms into the same memory device. The aim is to design the arrangement in such a way that the generic external user requesting data from the memory should deal with the memory architecture only at an optimum time, for example at the initialisation time. In addition, the user should not need to deal with it at each data extraction step. This means that, when the user requests a data block stored at a nominal address xxx, the memory itself retrieves the requested data block, even if it is not stored at the effective address xxx, but it is stored at a different address where it was physically possible to insert it. It is an object of this invention to build-up a map of failing bits at multi-probe level, i.e. before the memory is assembled. In addition, the map of failing bits is permanently incorporated within the memory and remains therewith until it is found necessary or convenient to modify it. An advantage of this approach is that such a memory utilised for mass storage applications is not tested as a computer memory, but it is tested by using specific algorithms and by carrying out a specific test program. According to one aspect of the invention, which is defined in detail in appended claim 1, there is provided a first memory block structured as a cell matrix in which data bytes (DATA ARRAY) are stored and in which an error correction code (ECC) is stored; a second memory block (SCRAM) which contains a decoder table enabling the reallocation of the data matrix addresses, wherein redundant rows are included; a block (scram dec) for decoding the addresses of the decoder table; a logic block (FUSE LOGIC) to enable a step to be executed to locate any non-useable row and to substitute said redundant rows therefor; an error correction code block (ECC) for implementing the error correction algorithm; a non-volatile memory block (FAIL MAD) , programmed during the test stage and available to a possible external processor for handing the content of the second memory (SCRAM); a word counter block (WORD COUNTER) that is driven from the external clock signal and counts the number of the addresses words and generates the word addresses; two input and output buffer blocks for the data to be written in or read out; and a multiplexer block by which the data stream is driven to the data memory or to the transcoder memory. The memory according to this invention, compared to a conventional memory, is structured in such a manner that the cell matrix includes not only locations for storing data, but also locations for storing an error correction code. This means that all information is contained within the chip and there is no need for an external circuitry be employed. In this way, the information exchange with the external world is enhanced. The chips used can be affected by faults of various kinds and, as a consequence, errors are likely to occur in the bits stored therein. This raises the need for a mechanism adapted to implement an error correction code (ECC) algorithm be included within the solid state disc (SSD) itself. When use of an error correction code of the Reed Salomon Code type is considered, a redundancy of 12.5% is achieved and consequently a memory capacity larger than the conventional 512 bytes per sector is needed: more precisely, 64 test bytes are to be added to each block of 512 data bytes. The error correction code may implement an algorithm for correcting the data stored in the memory, thereby eliminating the harmful effects of the memory faults. Of course, the error correction code may be affected by a functional limit and non-correctable errors may remain. Aiming at solving the problem of non-correctable errors, the architecture according to this invention provides for a redundancy area intended to replace any "too faulty" regions. As above mentioned, the adopted approach produces a faulty bit map that will enable the error containing rows to be replaced. In addition, the ECC algorithm can be automatically generated. Should the memory array be manufactured by means of volatile techniques, the chip according to this invention may include an optional additional circuitry designed for executing internal refresh operations. The chip according to this invention is adapted to store the data and the error correction code, to rearrange the cell matrix when there are rows including faulty cells, to implement the error correction algorithm, to generate the refresh operations for volatile memories, to permit external access by means of suitable buffers. Further details, particulars and advantages of this invention will become apparent from the following description by referring to the annexed drawings, wherein the preferred embodiments are shown by way of illustration. In the drawings, the schematic view shown in Figure 1 represents the block design of the memory according to this invention. DESCRIPTION OF THE BLOCKS SCRAMBLE RAM (SCRAM): this is the transcoder memory which contains a table enabling the reallocation of the data matrix addresses; the redundant rows are employed when it is necessary to substitute any faulty rows; SCRAM DEC: this block enables decoding the addresses of the reallocation table; DATA ARRAY: this is in effect the memory wherein data bytes and test bytes or check bytes are stored. In this embodiment, the memory is organised as 500 rows and each row is organised as 512 + 64 bytes. The 500 rows have been calculated so as to obtain a 15 Mbit chip; FUSE LOGIC: this logic block enables a step to be performed to locate non-useable rows and to substitute redundant rows therefor, ECC: this block implements the error correction algorithm: Reed Salomon Code; LOGICAL ROW ADDRESS BUFFER: this is an input buffer memory that stores the row address coming from the external bus; FAIL MAP: this is the core of the chip, namely a non-volatile memory area, programmed during the testing stage and available to a possible processor for managing said SCRAM memory by means of a suitable bus, WORD COUNTER: this block performs a counting operation of the addressed words by means of an external clock signal and, in addition, it generates the word addresses; DATA IN/DATA OUT: these blocks represent data input (or write) and output (or read) buffers, that directly co-operate with the MUX block; MUX: this block represents a multiplexer circuit that is controlled by a SCRAM-EN signal for switching over the data transfer to the effective data memory or to the transcoder memory SCRAM; ARBITER: this block controls the refresh operations by acting upon the REFRESH block. Furthermore, it solves the conflict between the memory access operation and the memory refresh operation; REFRESH COUNTER (REFRESH CNT): this block generates the addresses needed for refreshing the two volatile memories included in the system, the data matrix memory and the transcoder memory; OSC: this is an internal oscillator providing for timing the ARBITER BLOCK. The memory can be made quasi-static only by means of this internal oscillator (internal refresh). Before analysing the operation, it should be noted that the memory according to this invention also offers an active performance since it also includes the possibility for certain local processes to be performed, even if it is only restricted to correcting the errors. This means that, when the error correction process is not positively concluded, then the memory itself supplies an interrupt signal (INT) to the central processor. Furthermore, it should be noted that, as a consequence of the fact that SCRAMBLE RAM is used, it is no more necessary to subdivide the data memory into sectors, as it was in the prior art; in fact, upon decoding the addresses of the SCRAMBLE RAM, any one of the provided redundant rows can replace any one of the faulty rows. OPERATION MODE The blocks shown in Figure 1 provide for a correct operation of the memory. Some operation modes will now be analysed. ACCESS : first of all, it is necessary that the chip be enabled: this is achieved by setting signal CE = active, subsequently the addresses should be transferred, by loading them into suitable buffers DATA IN/DATA OUT. Signal W (write/read) determines the direction of the data. WRITE: upon applying the logic address, the transcoder memory translates it into a material address and in the mean time during the real address generation step, it provides for skipping any faulty rows. The error correction (ECC) block provides for adding the redundancy bytes loaded into the input buffer to the data and such bytes are conveyed by means of a multiplexer circuit MUX to the cell matrix wherein they are all stored in a single row. Contemporaneously, the clock signal enables the word counter to count the number of the obtained addresses and consequently the transferred bytes by means of an external operation, for each input byte. READ : upon enabling the chip by means of CE active signal and upon switching it to a read condition by disabling signal W, the sector address is provided and the material address is generated to enable the desired row to be accessed to by means of the transcoder table. The data will reach the above said buffer circuits and will be processed by the error correction block ECC, which locates and corrects any storage errors by means of the redundant bits. Should this operation be unsuccessfully performed, it will notify the non-correctable error status to the central processor by means of said INT signal. The construction according to this invention will also permit a direct access to the SCRAMBLE memory, as it is necessary during the diagnostic stage of the solid state disc: this operation, takes places by setting signal SCRAMBLE_EN active. As previously mentioned, the memory according to this invention is a memory of quasi-static type; in fact, the concerned chip automatically handles both the refresh operation of the data memory and the refresh operation of the SCRAMBLE memory. These performances are assured by the following blocks: REFRESH, by which the refresh function is effectively carried out, ARBITER, by which any conflicts between access and refresh operations are solved, and OSC, by which the synchronisation between the operations of the above two blocks is assured. DESCRIPTION OF SIGNALS AND BUSES CE: active low signal enabling the activation of the memory chip, A0-A11: 12 bit buses used to supply the chip with the required addresses, CLK: this signal is enabled each time a byte arrives and, in turn, it enables the word counter to count the addressed bytes, INT: this is an interrupt signal by which the ECC block indicates the existence of a non-correctable error, FAIL-MAP: it permits access to the memory area, I/O: this is the 16 bit, bi-directional, data bus, W: low active signal that enables the data flow direction to be controlled: read/write, SCRAM_EN: it enables the data bus to be connected either to the cell matrix or to the map memory. Many advantages are connected with using the memory as shown in Figure 1. First of all, it enables the control operations as well as the control module to be simplified. In particular the interface circuit between the microprocessor and the memories of the solid state disc SSD is simplified. The control module will then perform only the function to bypass the addresses by making them compatible with the memory as carried out by the control module itself. This reduces both the physical size of the control module itself and the complexity of the algorithm of the logic connection between data and control byte. The memory according to this invention, (ASM: Application Specific Memory) guarantees a noticeable advantage during the manufacturing stage, in particular during the test stage of the memory chips. This is in comparison to DRAM memories. A single pass test is sufficient. Since the control bytes are all sequentially stored in a single row, the addressing operation can only be effected in the so-called "page mode" and an immediate logic connection exists between the memory area allotted to the data and the memory area allotted to the check bytes. In view of this, the two different kinds of analysis of the DRAM memory faults as presently needed would be simplified and unified into a single test operation, with apparent improvements in terms of production rates. Furthermore, the restriction to a single faulty byte per block no more exists, in contradiction to conventional memories. In fact, since all 576 bytes are consecutive, it will be sufficient to check that the maximum number of faulty bytes within the string be less than or equal to the maximum allowable fault rate. In conventional DRAM memories, since it is not possible to logically connect the data and ECC memory areas, it is necessary to adopt more restrictive rules, so as to avoid that the sum of the defects of the two concerned areas be greater than the correction capability of the selected code. Lastly, the production rate of ASM memories is less expensive than that of DRAM memories. The number of the manufacturing stages is decreased. By analysing the data concerning the effects upon the chip ageing errors, it can be noted that, in effect, all kinds of errors occurring therein do not raise any problem to the solid state disc (SSD) manufactured with built-in ("on-chip") ECC. This results in the fact that the test procedure of this new memory will no longer need the 'burn-in' stage and the repetition of the whole test procedure at room temperature. The preferred embodiment of this invention has been described and a number of variations have been suggested hereinbefore, but it should expressly be understood that those skilled in the art can make other variations, changes and modifications in the details and in the construction particulars, without departing from the scope of this invention.

Claims: A memory comprising: a first memory block structured as a cell matrix in which data bytes (DATA ARRAY) are stored and in which an error correction code (ECC) is stored; a second memory block (SCRAM) which contains a decoder table enabling the reallocation of the data matrix addresses, wherein redundant rows are included; a block (SCRAM DEC) for decoding the addresses of the decoder table; a logic block (FUSE LOGIC) to enable a step to be executed to locate any non-useable row and to substitute said redundant rows therefor; an error correction code block (ECC) for implementing the error correction algorithm; a non-volatile memory block (FAIL MAP) , programmed during the test stage and available to a possible external processor for handing the content of the second memory (SCRAM); a word counter block (WORD COUNTER) that is driven from the external clock signal and counts the number of the addresses words and generates the word addresses. The memory according to claim 1, further comprising: an input buffer block for storing the row addresses coming from the external bus; two input and output buffer blocks (DATA IN; DATA OUT) for the data to be written in or read out, and a multiplexer block (MUX) by which the data stream is driven to the first memory (DATA ARRAY) or to the second memory (SCRAM). The memory according to claim 1 or claim 2, further including a refresh counter block (REFRESH CNT) to generate the addresses of both the first memory (DATA ARRAY) and the second memory (SCRAM); an arbiter block that, by acting upon a refresh counter (REFRESH OUT), controls the refresh operations and solves the conflict between the memory access and the memory refresh operations; a local oscillator block (OSC) that provides for timing the arbiter block. The memory according to any preceding claim, wherein the following signals operate the memory: CE: active low signal enabling the activation of the memory chip, CLK: a clocking signal which is enabled each time a byte arrives and in turn enables the word counter to count the addressed bytes, INT: an interrupt signal by which the error correction code (ECC) block indicates the existence of a non-correctable error, FAIL_MAP: a signal permitting access to the memory area, W: a low active signal that enables the data flow direction to be controlled, read/write, SCRAM_EN: a signal which enables the data bus to be connected either to the first or to the second memory. The memory of any preceding claim, wherein the following buses are connected to the memory: A0-A11: 12 bit buses used to supply the chip with the required 12 bit addresses, I/O: a 16 bit, bi-directional, data bus, a further bus being provided for an external processor to access the FAIL MAP block. The memory of any preceding claims wherein the first memory is a data array. The memory of any preceding claim, wherein the second memory is a transcoder memory. The memory of any preceding claim in the form of a Solid State Disk Memory.

Inventors: DI ZENZO MAURIZIO, GRIMANI RODOLFO, DI ZENZO, MAURIZIO, GRIMANI, RODOLFO
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS ITALIA SPA, TEXAS INSTRUMENTS INCORPORATED, TEXAS INSTRUMENTS ITALIA S.P.A.
Application year: 1995
Main classification: G06F11
IPC codes: G06F11, G11B20, G11C29