LOW POWER, HIGH PERFORMANCE, ON-CHIP CACHE WITH NO STALL AFTER A WRITE HIT

Abstract: An n-way set associative cache is provided which stores address and information (e.g. data, instructions) blocks in a plurality of respectively associated but independently accessible address and information memory arrays, or banks. The address and information arrays are accessible during different phases of a two phase CPU block. An information array is accessed only if a hit occurred in its associated address array. This arrangement produces a one cycle throughput and a reduction in power consumption.

Description: LOW POWER, HIGH PERFORMANCE, ON-CHIP CACHE WITH NO STALL AFTER A WRITE HIT Field of the Invention This invention is directed to a cache memory for use with a high performance central processing unit ("CPU") of a digital computer system as a level of memory hierarchy between the CPU and main memory and, in particular, to a technique for enabling the CPU to execute a read operation to the cache immediately after a write operation with no latency or stall and with one cycle throughput, and which also significantly reduces the power consumption of the cache. Background of the Invention Under ideal conditions, increased processing speed translates into an increased demand on memory per unit time. CPUs are often capable of operating at rates that exceed those of the main memory which typically is comprised of dynamic random access memories (DRAMs) . When system performance is paramount, an additional level of memory hierarchy is used, called a "cache", the performance of which is matched to that of the associated CPU. Such a cache memory is typically comprised of static random access memories (SRAMs) . An instruction cache or a data cache is used for on-chip fast access storage of recently used code or data. Programs tend to reuse data and instructions that have been used recently. A widely held rule of thumb is that a program spends 90% of its execution time in only 10% of the code. This hypothesis, which holds that most programs favor a portion of their address space at any instant in time, has the following two dimensions: (1) temporal locality (locality in time) - if an item is referenced, it will tend to be referenced again soon, and (2) spatial locality (locality in space) - if an item is referenced, nearby items will tend to be referenced soon. There are three categories of cache organization, as follows: (1) direct-mapped - each block (defined as the minimum unit of information that can be either present or not present in the cache) has only one possible location in the cache; (2) set-associative - each block has a restricted set of locations in the cache. If a set has two possible locations, for example, the cache is called 2-way set associative. The implementation thereof uses two block arrays (interchangeably referred to herein as banks) , with each set being formed of one block from each array. Stated in a more general way, if there are n blocks in a set, the cache placement is called n-way set associative; and (3) fully-associative - each block can be anywhere in the cache. The range of caches from direct mapped to fully associative is really a continuum of levels of set associativity in that direct mapped is simply one-way set associative and a fully associative cache with m blocks could be called m-way set associative (meaning that all of the m blocks are in one set) . An address generated by the CPU ("CPU ADDRESS") is divided into three fields to find data in a set- associative cache, namely, the block offset field ("B/O") which is used to select the requested information (i.e. code or data) from within the block (e.g. when one word is of interest and the block is multi-word) , the index field ("INDEX") which is used to select the restricted set of locations in which the block of interest might be found, and the tag field ("TAG") which is used for performing a comparison to verify that a block in the indexed set contains the requested information. This arrangement of the CPU ADDRESS is illustrated as follows: BLOCK TAG INDEX OFFSET A schematic block diagram of a prior art 4-way set associative cache is presented in Fig. 1. The CPU ADDRESS (also commonly known as the block-frame address) is shown as separated into its TAG, INDEX AND B/O fields. Arrays 10, 20, 30 and 40 each store 256 blocks of data corresponding to INDEX values 0 to 255. Decoder 50 receives the bits in the INDEX field and generates therefrom a cache index value which is inputted to each one of the arrays or banks, 10, 20, 30, 40 to select a set of four blocks shown with a shaded background. Each of these arrays, at a given INDEX value, stores along with the data bits of a block ("Data") an associated valid ("V") bit and tag bits ("Tag") . The V bit indicates whether or not the entry (i.e. the block stored in that array at the indexed position) contains valid data. The Tag bits from the cache are compared with the TAG bits from the CPU ADDRESS to verify whether or not the entry contains the information of interest. However, a match between the TAG and Tag is ignored if the V bit is not set to a logic 1, for example. To this end, comparators 12, 22, 32 and 42 receive the TAG from CPU ADDRESS and the respective Tags from arrays 10, 20, 30, 40 to determine whether a match exists and, if so, to produce a logic 1. AND gates 14, 24, 34 and 44 pass this logic high therethrough only if V has been set. OR gate 50 is coupled to all of AND gates 14, 24, 34, 44 to indicate a hit (i.e. the block of interest is found in the set indexed in the cache) , and the AND gates are all also coupled to multiplexor 60 which has inputs respectively coupled to the Data in arrays 10, 20, 30, 40. If a comparator finds a match between the TAG and the Tag (i.e. a hit) in bank 40 for example, and the associated V is set, multiplexor 60 transfers the associated Data from bank 40 to the CPU. This condition is shown in Fig. 1 by virtue of the line extending between array 40 and multiplexer 60 being thicker and in bold relative to the corresponding lines from the other banks. Cache functionality and policies may differ from one architecture or design to another, but the essential purpose of all caches is for read and write operations. Reads dominate cache accesses. All instruction accesses are reads, and most instructions do not write to memory. Therefore, optimizing caches for read accesses speeds up overall performance. However, high performance designs cannot neglect the speed of write accesses. To speed up read accesses of a data cache, for example, a block of the Data can be read at the same time that the Tag is read and compared with the TAG. As a result, the block read of Data begins as soon as the block-frame address is available. If the Tag comparison is a hit, the Data is ready to be passed on to the CPU immediately. If it is a miss (i.e. the block is not found in the cache) , the cache is of no benefit, and the only drawback of having done the read of Data is unnecessary power consumption. On a read miss the cache sends a stall signal to the CPU telling it to wait, and the requested block is read from the main memory. When the data arrives, it is written to the cache, thereby updating the Data, the Tag and the V bit, and sent to the CPU. The above-described operation is not used for writes. For write accesses, the processor specifies the length of the data to be written, usually between 1 and 8 bytes. It is possible to change all or only a portion of the block in the cache. This results in a read-modify-write sequence of operations on the block of interest, i.e., read the original block, modify a portion thereof, and write the new block value. Moreover, modification of a block cannot begin until the Tag is checked to see if it is a hit. Unlike the case for reads with the Tag verification being carried out simultaneously with a read of Data, verification of the Tag cannot be performed in parallel (i.e. simultaneously) with a write into the cache. Therefore, writes normally take longer than reads, i.e. writes have a serialization penalty. Thus, most cache designs differ one from another based on the adopted write policies. The following two basic options are available when writing to the cache in case of a write hit: (1) Write-through (or store-through) - the information is written to both the block in the cache and to the block in the main (lower level) memory. (2) Write-back (also called copy-back or store- in) - the information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced. The following two ways are available to deal with a write miss: (1) Write-allocate (also called fetch-on-write) - the block is loaded into the cache from main memory. (2) No-write-allocate (also called write- around) - the block is modified in the main memory, but it is not loaded into the cache. Minimizing cache write latency is particularly challenging because the processor must often stall until the cache access is completed. Cache designs currently used in microprocessors and digital computer systems perform read accesses from the on- chip cache in one CPU cycle with a one cycle throughput, and write accesses to the on-chip cache in two CPU cycles (or at least 1.5 CPU cycles) with a one CPU cycle throughput for consecutive write operations. However, when a write access to the cache is followed in the next CPU cycle by a read access to the cache, a one cycle latency that stalls the CPU execution of the read operation is introduced by the cache following the completion of the write access. A more detailed explanation of read and write operations is provided in relation to Fig. 2. The read access, in most cache designs, is performed in the following steps. Per step 66, the CPU ADDRESS provided to the cache is divided into two fields, namely the block-frame address and the B/O. The block-frame address is further divided into a TAG and an INDEX. Step 68 starts a new CPU cycle, and step 70 decodes the INDEX to select one of the sets of blocks in the set associative cache. Step 72 determines whether a read has been called for by the CPU and, if so, then step 74 reads the Tag and simultaneously reads the Data for all four of the arrays in Fig. 1. If a match for one of the arrays is found together with the V bit being set, as determined by step 76, then step 78 sends the corresponding Data from that array to the CPU. These steps occur within a single CPU cycle. To reduce the hit time (i.e. the time to access the cache memory, which includes the time to determine whether the access is a hit or a miss) , the Data is read by step 74 at the same time as the Tags are read. Thus, by the time the Tag comparisons are completed by step 76, the Data is ready to be sent immediately to the CPU by step 78. On a read miss, as determined by step 76, the cache sends a signal per step 80 to the CPU telling it to wait, and the requested block is read from the main memory. When the Data arrives, it is written to the cache, thereby updating the Data, the Tag and V. The Data is also sent to the CPU. The first steps of a write access are similar to those performed during read accesses. These steps are 66 , 68, 70 and 72. The difference is that only after steps 82 and 84 find a match in the Tag comparison (i.e. a "write hit") will the data be written into the cache per step 86. Of course, step 86 is carried out in a CPU cycle subsequent to the one in which steps 70, 72, 82 and 84 are performed due to the serialization penalty. Step 87 starts the subsequent CPU cycle in which step 86 is performed. When a no-write-allocate policy on a write miss is implemented, for example, then in case step 84 determines a write miss condition step 88 writes "around" the cache to the lower-level memory, i.e., the main memory, and does not affect the cache. Consequently, if a read access is initiated by the CPU to the cache immediately following a write access (which is a hit) , then the cache stalls the execution of the read operation until the write operation in the cache is completed. The stall is caused by a contention on the cache data memory array (i.e. data memory cells cannot be read and written in the same access phase) . It should now be clear that one significant shortcoming of existing cache designs is the stall penalty imposed on the CPU performance every time a read-after-write hit sequence occurs. Another major shortcoming of existing cache designs is due to the fact that on every read access both the Tag and Data in the cache memory arrays are read, whether or not the access is a hit in the cache. As a result, cache power consumption is relatively high. Additional details of the prior art cache designs discussed above can be found in Hennessy and Patterson, Computer Architecture, a Quantitative Approach. Morgan Kaufman Publishers, Inc., 1990, Chapter 8 and in Patterson & Hennessy, Computer Organization & Design, The Hardware/Software Interface, Morgan Kaufman Publishers, 1994, Chapter 7, the contents of which are hereby incorporated by reference. Summary of the Invention An object of the present invention is to improve the performance of an on-chip cache. Another object of the present invention is to reduce the power consumption of an on-chip cache. These and other objects of the present invention are attained by an n-way set associative cache, where n is an integer, to store information accessible by a requested address. The cache includes n information arrays in which information blocks are accessible in accordance with an assigned address, and n address arrays in which addresses are stored independently of the n information arrays. Addresses stored in the n address arrays are respectively assigned to information blocks in the n information arrays. Another aspect of the invention is directed to an n-way set associative cache, where n is an integer, to store information accessible by a requested address. The cache includes n address arrays each storing a plurality of addresses, and n information arrays each storing a plurality of information blocks accessible in accordance with respective assigned addresses. The n information arrays are respectively associated with the n address arra\s, with associated ones of the n address and the n information arrays having the plurality of addresses in an address array being the assigned addresses, respectively, for the plurality of information blocks in the associated information array. The cache further includes n comparators respectively receiving an output of the n address arrays, with one input of each of the n comparators being coupled to the output of its address array, and another input of the n comparator receiving a signal corresponding to the requested address. Drivers are provided for each of the n information arrays, with the drivers having their outputs respectively coupled to the plurality of information blocks, each of the drivers receiving as inputs (a) a signal corresponding to the requested address and (b) a signal corresponding to an output from the one of the n comparators receiving an output from the address array associated with such information array. Yet another aspect of the present invention is directed to an n-way set associative cache, where n is an integer, to store information accessible by a requested address. The cache includes n address arrays each storing a plurality of addresses, and n information arrays each storing a plurality of information blocks accessible in accordance with respective assigned addresses. The n information arrays are respectively associated with the n address arrays, with associated ones of the n address and the n information arrays having the plurality of addresses in an address array being the assigned addresses, respectively, for the plurality of information blocks in the associated information array. The cache further includes means for verifying whether the requested address matches a particular address stored in a location selected in each of the n address arrays, means for, if a particular address is verified in one of the n address arrays, accessing only the particular information array associated with whichever one of the n address arrays stores the verified address. Another aspect of the present invention is directed to an n-way set associative cache including a clock providing a CPU cycle with multiple phases, a memory in which are stored a plurality of addresses and a plurality of information blocks respectively assigned thereto, means responsive to a requested address for verifying, during one of the phases, whether any one of the plurality of stored addresses matches the requested address, and means for accessing, during another of the phases, whichever of the plurality of information blocks is assigned to a verified address, whereby a one cycle throughput is achieved. One further aspect of the present invention is directed to an n-way set associative cache including a memory in which are stored a plurality of addresses and a plurality of information blocks respectively assigned thereto, means responsive to a requested address for verifying, during one time period, whether any one of the plurality of stored addresses matches the requested address, and means for accessing, during another time period, only whichever of the plurality of information blocks is assigned to a verified address, whereby reduced power consumption is achieved. Brief Description of the Drawings Fig. 1 is a schematic block diagram of a prior art cache. Fig. 2 is a flow chart for operating the cache of Fig. 1 in a conventional manner. Fig. 3 is a schematic block diagram of a cache arranged in accordance with the invention. Fig. 4 is a flow chart for operating the cache of Fig. 3 in accordance with the invention. Fig. 5 is a timing diagram showing the access stages of a data cache in accordance with the invention. Detailed Description of the Invention For the sake of simplifying the following explanation of the invention, an implementation of a 2-way set associative cache will be described. However, it must be understood that the invention applies broadly to an n-way set associative cache, with each set consisting of n blocks, n being any integer. Moreover, the cache can be a data cache, an instruction cache or a mixed data/instruction cache. It must also be understood that a CPU implementation may use one or more bits in addition to those that are discussed below. For example, one such additional bit can be a least recently used (LRU) bit. Another such bit is a lock bit which locks data into the cache in order to prohibit overwrite of crucial data. The lock bit can be reset only if there is a complete invalidation of the cache. Another such bit (SEL) enables selective invalidation of the cache. However, since such additional bits are not directly related to the invention, no discussion thereof will be presented in order to facilitate the explanation of the invention. Moreover, details about such additional bits can be found in USP 5,249,286. The cache policies applied by the invention are: (a) read-through, (in case of a read miss, data is sent simultaneously from main memory to the cache and CPU) , (b) write-through (in case of a write hit) , and (c) no-write-allocate (in case of a write miss) . It will be recalled that Fig. 1 shows the Tag and associated Data of any particular cache INDEX as being stored together in the same cache array. Also, it is common in the prior art to retrieve the Tag and Data simultaneously for all blocks of the indexed set (i.e. 2 blocks in the present example of a 2-way set associative cache) . In contrast, the present invention performs neither of these operations. In accordance with a key feature of the invention, the Tag and its associated Data for each INDEX are separated from each other to be independently accessible in different arrays, as shown in Fig. 3. Arrays 100 and 110 store V and Tag bits which are assigned, respectively, to blocks of DATA bits stored in arrays 100A and 110A in accordance with the same INDEX values. Thus, the V and Tag bits in array 100 and the Data bits in array 100A of Fig. 3 correspond in combination to the V, Tag and Data bits in array 10 of Fig. 1, for example. Likewise, the bits in arrays 110 and 110A of Fig. 3 correspond in combination to the bits in array 20 of Fig. 1. Since the cache can be a data cache, instruction cache or a mixed data cache, for the sake of convenience arrays 100A and 110A, regardless of type, are referred to herein interchangeably as data or information arrays. Likewise, arrays 100 and 110 are referred to herein interchangeably as Tag or address arrays since the primary portion of the number of bits stored therein corresponds to a portion of the CPU ADDRESS. Also, the term access will refer hereinafter to both read and write operations. In accordance with the present invention, the Data is not accessed simultaneously with the associated Tag for a given INDEX so as to be available for transfer to the CPU upon completion of the Tag comparison as in the prior art. In contrast, separate INDEX value decoders are provided for the Tag and the Data. In particular, decoder 102 is coupled to arrays 100 and 110, whereas decoder 102A is coupled to arrays 100A and 110A via drivers 108 and 109, respectively. Each of drivers 108 and 109 is a set of AND gates. The number in the set corresponds to the number of indexed positions. Only one representative AND gate is shown for each driver. Each of the AND gates in driver 108 receives an input from the decoder 102A and from OR gate 116 (discussed below) . Each of the AND gates in driver 109 receives an input from the decoder 102A and from OR gate 117 (discussed below) . The decoders 102 and 102A are activated at different phases of the CPU cycle. (The definition of a "CPU cycle" in connection with the present invention is the same as set forth on page 251 of the above-mentioned book "Computer Architecture, A Quantitative Approach" for a machine cycle, namely the time required to move an instruction one step down the pipeline.) A two-phase clock design is used. The two clock phases are called PHIl, which is basically the time period when the CPU cycle is high, and PHI2, which is basically the time period when the CPU cycle is low. Specifically, decoder 102 is activated at the first phase PHIl, while decoder 102A is activated at the second phase PHI2. Thus, the arrangement of Fig. 3 enables retrieval of the Tag and its associated Data at a given INDEX value independently from each other ?,nd at different phases of the same CPU cycle. The ε ifics of how this is done, and the benefits which flow therefrom, are explained below. It is important to note that arrays 100, 110, 100A and 110A are SRAMs which have an access time of less than half of a CPU cycle. Arrays 100 and 110 are connected to respective comparators 104, 105 and to respective AND gates 106, 107. Comparators 104, 105 compare the TAG bits of the CPU ADDRESS with the respective TAG bits from arrays 100 and 110 at the cross-hatched INDEX number. If a match is found by, say, comparator 105, it will send a logic 1 to AND gate 107 which passes this logic 1 only if the V bit is set to 1 indicating that the Data associated therewith (albeit stored in a separate array 100A) is valid. It should be noted that while the above- described operations are being performed during PHIl by decoder 102, by arrays 100 and 110, by comparators 104 and 105 and by AND gates 106 and 107, no activity has yet occurred in arrays 100A and 110A. That activity is triggered by the start of PHI2. More specifically, decoder 102A responds to the start of PHI2 by enabling the selection of a block from the set of blocks in arrays 100A and 110A based on the INDEX value. In particular, the decoded INDEX value generated at the output of decoder 102A accesses a particular one of the AND gates in driver 108 and a particular one of the AND gates in driver 109. However, only one of these drivers will enable a read of the Data in the two banks because the drivers are enabled only upon receiving a logic 1 from both the decoder 102A and whichever of AND gates 106, 107 is coupled to it by OR gates 116, 117, respectively. Thus, in the above-stated example in which a hit is detected for the Tag of bank 110, AND gate 107 produces a logic 1 that, in turn, activates driver 109 via OR gate 117 to read the indexed Data. On the other hand, driver 108 remains inactive because the input it receives from OR gate 116 is not a logic 1 since the output of AND gate 106 is a logic 0 (i.e. a match was not found for the Tag in array 100) and there is no overwrite operation (as explained below) . Therefore, the Data stored in bank 100A is not read. It should be noted that after driver 109 is activated, the corresponding Data block is read and inputted to a multiplexer (not shown) . The B/O bits control which portion of the read-out Data block is provided to the CPU by the multiplexer. The multiplexer and its connections to arrays 100A, 110A and to the CPU are not shown because this part of the circuitry is well known and, therefore, would unnecessarily clutter the drawing. Thus, the B/O bits are utilized to identify the specific portion of the Data block in bank 110A that has been requested by the CPU ADDRESS. Providing further details is not deemed necessary. Thus, in the above-presented example, only bits from the cross-hatched Data block in array 110A will be read and sent to the CPU. The lack of cross- hatching in any block of array 100A represents the fact that no read of any of its Data has occurred. Of course, if a hit was not detected, then no Data in either of the two arrays 100A and 110A would have been read. The above-described elimination of a read in one or more of the arrays in an n-way set associative cache results in a significant reduction in power consumption. Referring to Fig. 4, the CPU ADDRESS is decoded by step 202 as the first phase of a CPU cycle begins per step 200. Step 204 reads the Tags of the set selected by the INDEX in arrays 100 and 110. Step 206 determines whether a match exists and whether the V bit is set. If so, then as the second phase of the CPU cycle begins per step 207, step 208 identifies the operation as a read or write. If it is a read, then step 210 reads the Data block in the array identified by the Tag match and uses the B/O bits to select the requested portion of the read-out Data block. Step 212 then sends that portion of the Data block to the CPU. When a miss is identified by step 206, and step 214 identifies the request as a read miss, step 216 carries out a read miss operation in which the already computed information of the read request is used for fetching data from the main memory. The data cache stores the following information in a dedicated latch 120 (see Fig. 3) : ■ CPU ADDRESS. • Tag hit/miss indication. This is obtained from the Tag comparison. Whether a hit was produced is derived from OR gate 125 which receives the outputs of AND gates 106 and 107. In addition, LATCH 120 also stores a signal indicative of which of AND gates 106 and 107 has an output at a logic 1 (i.e. to signal the hit) . Consequently, LATCH 120 indicates not only that a hit occurred, but also the identity of the array 100 or 110 in which the matching Tag is stored. • A cacheable/non-cacheable indication. A read request which is missing in the cache is defined as non-cacheable if at least one of the following is true: the cache is disabled, the request is a miss and both entries in the selected set are locked (per the lock bit) , or the bus interface unit returns the missing data along with a cache-inhibit signal from the system for data which is not intended to be written into the cache. After a read miss, the read-through cache policy is implemented as follows. The bus interface unit (not shown) gets control of the system bus (not shown) and fetches the missing data from the main memory while the CPU stalls the read operation until the data is returned by the bus interface unit. At this stage the cache is pending for the bus interface unit to signal that the missing data is available on the CPU data bus. When the data returns from the main memory, the data cache performs an overwrite operation to the cache. This cache access is actually a write access to both tag and data arrays, and is thus different from the regular write access (described below) . More specifically, at PHIl address decoding is performed by DECODER 102 which receives over line 129 the CPU ADDRESS stored in LATCH 120, and the resulting cache INDEX accesses the Tag array of the selected set. LATCH 120 has Tag overwrite lines 130 and 132 connected to the Tag blocks in arrays 100 and 110, respectively, which provide the replacement Tag bits. LATCH 120 also has V overwrite lines 134 and 136 connected to the V bits in arrays 100 and 110, respectively, which provide the replacement V bits. By relying on the Tag hit/miss data in LATCH 120, the new Tag and V bits are outputted on the overwrite lines 130, 134 or 132, 136 that correspond to the array which stores the matching Tag. Thus, the new Tag is written, and the V bit (along with any additional bits, as discussed above, that are used) is updated (if the returning data is cacheable) . If the- returning data is cacheable, then in PHI2 the data from the CPU data bus (not shown) is written into the selected entry in the Data array corresponding to the updated Tag array. The dual capability of a read to retrieve data and an overwrite to store data pertaining to the Data banks 100A and 110A is depicted by the double ended arrows representative of data flow to and from the CPU. The Data is received from the CPU and the INDEX is decoded by DECODER 102A, from the CPU ADDRESS provided by LATCH 120 over line 129. The Data array corresponding to the Tag array having the matching Tag is identified by overwrite control signals inputted to OR gates 116 and 117. The overwrite control signals are derived from LATCH 120 which, as explained above, contains the identity of whichever one of the arrays 100 and 110 has a Tag resulting in a hit. LATCH 120 outputs an overwrite control signal at a logic 1 to only the OR gate coupled to the information array 100A, 110A which corresponds to the address array with the matching Tag. For a write operation, the same steps 200, 202, 204 and 206 are carried out in PHIl to generate the Tag hit/miss indication at the completion of step 206. The Tag comparison also results in an indication of, in case of a hit, in which of the two entries of the selected 2-way associative set the requested Data is stored. This indication selects which of the two data banks will be accessed to write the Data thereinto. If there is a hit on one of the Tags, and the request was not canceled by the CPU, then if step 208 identifies the request as a write, PHI2 is used to write the data from the CPU into the selected entry in the Data array, per step 218. Of course, the V and Tag bits remain unchanged (in contrast to a read miss operation, as pointed out above) . If the Tag comparison fails, however, per step 206, and step 214 identifies a write miss condition, the Data array is not accessed (i.e. the cache does not perform any write operation) . The data bypasses the cache and is "written through" to the main memory, per step 217. In the next PHIl a new request (read or write) can enter the Tag comparison steps, thus improving the total CPU performance by as much as 5%. By virtue of the above-described technique, the cache operates like a two-stage non-pipelined machine. During PHIl, a read or write access can perform a Tag comparison (represented in Fig. 5 by "TAG") while a previous access has been completed in the previous PHI2. In the next PHI2, the read or write operation performs an operation involving the Data (represented in Fig. 5 by "DATA") . A new read or write operation may then perform a Tag comparison in the following PHIl. This invention allows a one-CPU cycle access for every cache operation, and a one-CPU cycle throughput for every combination of multiple access sequence, i.e., a write operation on a write hit can be followed immediately, and without any latency or stall, by a read operation or another write operation, and vice versa (see Figure 5) . If a miss has occurred, the requested CPU ADDRESS does not result in the Data arrays being accessed nevertheless. On the contrary, by limiting a read of Data to only a hit situation, and only to the particular array which stores the requested Data, the cache power consumption is reduced by as much as 50%. This invention enables the execution of a read access to the cache immediately following a write access, with no latency and without having to stall the CPU execution. It improves the CPU performance by as much as 5% in normal operating conditions and typical applications at the same time as it reduces the power consumed by the cache by as much as 50%. In some applications, the performance improvement can be even greater. Although a preferred embodiment of the invention has been described in detail above, various modifications thereto will be readily apparent to one with ordinary skill in the art. For example, the operations described above as being respectively carried out in phases PHIl and PHI2 can be interchanged so that those associated with PHIl are performed in PHI2, and so on. Also, although Fig. 3 shows use of AND gates 106, 107 to verify that the V bit is set, this operation can be performed by comparators 104 and 105 simply by adding a leading bit, for example, to the CPU ADDRESS and putting the V bit as a leading bit to the Tag bits. In addition, DRAMs can be used for the cache rather than SRAMs with the corresponding provision of associated bit refresh circuits. Furthermore, although a particular set of cache policies has been specified above, other sets of cache policies are also usable with the present invention. Another modification is the use of a CPU cycle with more than two phases. A further modification eliminates all but one of the decoders disclosed above. The single decoder can be used for the address arrays, with a latch being used to store the decoded address for the information arrays. Alternatively, the same decoder output could be applied to all the arrays, but a control switch would actuate operation of either the address or information arrays. All such modifications are intended to fall within the scope of the present invention as defined by the following claims.

Claims: WE CLAIM: 1. An n-way set associative cache, where n is an integer, to store information accessible by a requested address, comprising: n information arrays in which information blocks are accessible in accordance with an assigned address; n address arrays in which addresses are stored independently of said n information arrays, addresses stored in said n address arrays being respectively assigned to information blocks in said n information arrays. 2. The cache of claim 1, further comprising a decoder receiving a portion of said requested address and having its output coupled to said n address arrays. 3. The cache of claim 2, further comprising another decoder receiving said portion of said requested address and having its output coupled to said n information arrays. 4. The cache of claim 3, further comprising a clock circuit coupled to said decoders. 5. The cache of claim 4, wherein said clock circuit actuates said decoders to operate at different times. 6. The cache of claim 5, wherein said clock circuit provides a two phase CPU cycle, and said different times are respectively related to said two phases. 7. The cache of claim 1, further comprising, for each of said n address arrays, a comparator receiving (a) a portion of the requested address and (b) an address accessed in such address array based on said requested address. 8. The cache of claim 1, further comprising drivers having an output respectively coupled to information blocks stored in said n information arrays, those of said drivers having an output coupled to the information blocks of one of said n information arrays being coupled to receive an output of the comparator of an address array storing addresses assigned to information blocks in said one information array. 9. The cache of claim 1, further comprising a clock circuit coupled to said n information arrays and said n address arrays to actuate access at different times to said n information arrays and said n address arrays. 10. An n-way set associative cache, where n is an integer, to store information accessible by a requested address, comprising: n address arrays each storing a plurality of addresses, and n information arrays each storing a plurality of information blocks accessible in accordance with respective assigned addresses, said n information arrays being respectively associated with said n address arrays, with associated ones of said n address and said n information arrays having the plurality of addresses in an address array being the assigned addresses, respectively, for the plurality of information blocks in the associated information array; n comparators respectively receiving an output of said n address arrays, with one input of each of said n comparators being coupled to the output of its address array, and another input of said n comparator receiving a signal corresponding to said requested address; and drivers for each of said n information arrays, said drivers having their outputs respectively coupled to said plurality of information blocks, each of said drivers receiving as inputs (a) a signal corresponding to said requested address and (b) a signal corresponding to an output from the one of said n comparators receiving an output from the address array associated with such information array. 11. The cache of claim 10, further comprising a decoder receiving a portion of said requested address and having its output coupled to said n address arrays. 12. The cache of claim 11, further comprising another decoder receiving said portion of said requested address and having its output coupled to said n information arrays. 13. The cache of claim 12, further comprising a clock circuit coupled to said decoders, wherein said clock circuit actuates said decoders to operate at different times. 14. The cache of claim 10, further comprising a clock circuit coupled to said n information arrays and said n address arrays to actuate access at different times to said n information arrays and said n address arrays. 15. An n-way set associative cache, where n is an integer, to store information accessible by a requested address, comprising: n address arrays each storing a plurality of addresses, and n information arrays each storing a plurality of information blocks accessible in accordance with respective assigned addresses, said n information arrays being respectively associated with said n address arrays, with associated ones of said n address and said n information arrays having the plurality of addresses in an address array being the assigned addresses, respectively, for the plurality of information blocks in the associated information array; means for verifying whether the requested address matches a particular address stored in a location selected in each of said n address arrays; and means for, if a particular address is verified in one of the n address arrays, accessing only the particular information array associated with whichever one of said n address arrays stores the verified address. 16. The cache of claim 15, wherein said accessing means accesses only an information block in said particular information array assigned to the verified address. 17. The cache of claim 15, wherein said verifying means simultaneously verifies all of said n address arrays for a match with the requested address. 18. The cache of claim 15, wherein said verifying means and said accessing means are operated at different times. 19. The cache of claim 18, wherein said different times correspond to phases of a CPU cycle. 20. The cache of claim 15, wherein said verifying means includes decoder means coupled to receive a first portion of the requested address and to generate therefrom said selected location. 21. The cache of claim 20, wherein said verifying means includes, for each of said n address arrays, a comparator receiving a second portion of the requested address and an accessed address stored at said selected location. 22. The cache of claim 21, wherein said accessing means for each information array is responsive to an output of said comparator of the address array associated with such an information array. 23. An n-way set associative cache comprising: a clock providing a CPU cycle with multiple phases; a memory in which are stored a plurality of addresses and a plurality of information blocks respectively assigned thereto; means responsive to a requested address for verifying, during one of said phases, whether any one of the plurality of stored addresses matches the requested address; and means for accessing, during another of said phases, whichever of the plurality of information blocks is assigned to a verified address; whereby a one cycle throughput is achieved. 24. The cache of claim 23, wherein said accessing means performs a read operation in said other phase after a read hit in the one phase. 25. The cache of claim 23, wherein said accessing means performs a write operation in said other phase after a write hit in the one phase. 26. The cache of claim 25, wherein said accessing means performs a read in one CPU cycle after a write hit in an immediately preceding CPU cycle. 27. The cache of claim 23, wherein said CPU cycle has two phases. 28. An n-way set associative cache comprising: a memory in which are stored a plurality of addresses and a plurality of information blocks respectively assigned thereto; means responsive to a requested address for verifying, during one time period, whether any one of the plurality of stored addresses matches the requested address; and means for accessing, during another time period, only whichever of the plurality of information blocks is assigned to a verified address; whereby reduced power consumption is achieved. 29. The cache of claim 28, wherein said accessing means performs a read in said other time period after a read hit in the one time period. 30. The cache of claim 28, wherein said accessing means performs a write in said other time period after a write hit in the one time period. 31. The cache of claim 28, wherein said time periods are phases of a CPU cycle.

Inventors: AZMANOV ZIV, INTRATER GIDEON, AZMANOV, ZIV, INTRATER, GIDEON
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1995
Main classification: G06F12
IPC codes: G06F12