Process for fabricating a microtip cathode assembly for a field emission display panel

Abstract: A process for forming a microtip cathode structure on a field emission display panel avoids the need of vacuum depositing a lift-off layer for the microtip deposition overstructure in specially equipped reactors to accomplish a deposition at a grazing angle, by co-patterning the lift-off layer together with an underlying metal grid layer by a succession of different etching steps through the openings of a grid definition mask. According to an embodiment, nickel is used as lift-off material and is either wet-etched or sputter-etched before performing a plasma etch of the underlying grid metal layer. According to an alternative embodiment the masking resist layer is used as lift-off material.

Description: Field of the invention This invention relates to a device for limiting and making uniform the current through microtips of a cathodic structure for flat panel displays (FPD) of the field emission type (FED). More in particular, the process of the invention relates to the formation of microtips of a refractory metal by sputtering in preformed wells and removing the deposition overstructure. Background of the invention The continuous evolution towards portable electronic products such as laptop computers, personal organizers, pocket TVs and electronics games, has created an enormous market for monochromatic or color display screens of small dimensions and reduced thickness, having a light weight and a low dissipation. Especially, the first two requirements cannot be met by conventional cathode ray tubes (CRTs). For this reason, among the emerging technologies, let alone those related to liquid-crystal-displays (LCD), flat panel field emission display technology has been receiving increasing attention by the industry. A remarkable research and development work has been carried out in the past few decades on field emission displays (FED) employing a cathode in the form of a flat panel provided with a dense population of emitting microtips co-operating with a grid-like extractor essentially coplanar to the apexes of the microtips. The cathode-grid extractor structure is a source of electrons that are accelerable in a space, evacuated for ensuring an adequate mean free-path, towards a collector (anode) constituted by a thin and transparent conductor film upon which are placed luminescent phosphors excited by the impinging electrons. Emission of electrons is modulately excitable pixel by pixel through a matrix of columns and rows, constituted by parallel strips of said population of microtips and parallel strips of said grid-like extractor, respectively. The fundamental structure of these display systems and the main problems related to the fabrication technology, reliability and durability, as well as those concerning the peculiar way of exciting individual pixels of the display system and various proposed solutions to these problems, are discussed and described in a wealth of publications on these topics. Among the pertinent literature the following publications may be cited: US 5,391,259; Cathey, et al. US 5,387,844; Browning US 5,357,172; Lee, et al. US 5,210,472; Casper, et al. US 5,194,780; Meyer US 5,064,396; Spindt US 4,940,916; Borel, et al. US 4,857,161; Borel, et al. US 3,875,442; Wasa, et al. US 3,812,559; Spindt, et al. US 3,755,704; Spindt, et al. US 3,655,241; Spindt, et al. "Beyond AMLCDs: Field emission displays?", K. Derbyshire, Solid State Technology, Nov. 94; "The state of the Display", F. Dawson, Digital Media, Feb.-Mar. 94; "Competitive Display Technologies", 1993, Stanford Resources, Inc.; "Field-Emission Display Resolution", W. D. Kesling, et al., University of California, SID 93 DIGEST 599-602; "Phosphors For Full-Color Microtips Fluorescent Displays", F. Lévy, R. Meyer, LETI - DOFT - SCMM, IEEE 1991, pages 20-23; "Diamond-based field emission flat panel displays", N. Kumar, H. Schmidt, Solid State Technology, May 1995, pages 71-74; "Electron Field Emission from Amorphic Diamond Thin Films", Chenggang Xle, et al., Microelectronics and Computer Technology Corporation, Austin, TX; University of Texas and Dallas, Richardson, TX; SI Diamond Technology, Inc., Houston, TX; "Field Emission Displays Based on Diamond Thin Films", Natin Kumar, et al:, Microelectronics and Computer Technology Corporation, Austin, TX; Elliot Schlam Associates, Wayside, NJ; SI Diamond Technology, Inc., Houston, TX; "U.S. Display Industry on the Edge", Ken Werner, Contributing Editor, IEEE Spectrum, May 1995; "FEDs: The sound of silence in Japan", OEM Magazine, Apr. 1995, pages 49, 51; "New Structure Si Field Emitter Arrays with low Operation Voltage", K. Koga, et al., 2.1.1, IEDM 94-23. In particular the document DE-A-33 40 777, discloses a method of fabricating a microtip cathode on a FED panel, in which, the deposited overstructure that remains after the formation of the microtips within the pre-formed wells, is removed by a lift-off technique using a lift-off sacrificial layer that is co-defined together with the apertures of the wells, into which the microtips are formed by sputter deposition. A metal stencil mask is used during sputter deposition to reduce the extent of the deposited overstructure on the lift-off layer to allow for an effective lift-off. The major advantages of FEDs compared to modern LCDs are: low dissipation; same color quality of traditional CRTs; visibility from any viewing angle. FED technology has developed itself on the basic teachings contained in US Patent No. 3,665,241; 3,755,704 and 3,812,559 of C.A. Spindt and in US Patent No. 3,875,442 of K. Wasa, et al.. FED technology connects back to conventional CRT technology, in the sense that light emission occurs in consequence of the excitation of the phosphors deposited on a metallized glass screen bombarded by electrons accelerated in an evacuated space. The main difference consists in the manner in which electrons are emitted and the image is scanned. A concise but thorough account of the state of modern FED technology is included in a publication entitled "Competitive Display Technologies - Flat Information Displays" by Stanford Resources. Inc., Chapter B "Cold Cathode Field Emission Displays". A schematic illustration contained in said publication and giving a comparison between a conventional CRT display and a FED (or FED array) is herein reproduced in Fig. 1. In a traditional CRT there is a single cathode in the form of an electron gun (or a single cathode for each color) and magnetic or electrostatic yokes deflect the electron beam for repeatedly scanning the screen, whereas in a FED the emitting cathode is constituted by a dense population of emission sites distributed more or less uniformly over the display area. Each site is constituted by a microtip electrically excitable by means of a grid-like extractor. This flat cathode-grid assembly is set parallel to the screen, at a relatively short distance from it. The scanning by pixel of the display is performed by sequentially exciting individually addressable groups of microtips by biasing them with an adequate combination of grids and cathode voltages. As shown in Fig. 2, a certain area of the cathode-grid structure containing a plurality of microtips and corresponding to a pixel of the display is sequentially addressed through a driving matrix organized in rows and columns (in the form of sequentially biasable strips, into which the cathode is electrically divided and of sequentially biasable strips into which the grid extractor is electrically divided, respectively). A typical scheme of the driving by pixel of the cathodic structure of a FED is shown in Fig. 3. This figure illustrates the driving scheme of a fragment of nine adjacent pixels through a combination of the sequential row biasing pulses for the three rows R1, R2, R3, relative to a certain bias configuration of the three columns C1, C2 and C3. A typical cross-sectional view of a FED structure is shown in Fig. 4. The microtip cathode plate generally comprises a substrate of an isolating material such as glass, ceramic, silicon (GLASS BACKPLATE), onto which is deposited a low resistivity conductor layer as for example a film of aluminum, niobium, nickel or of a metal alloy (NICKEL ELECTRODE), eventually interposing an adhesion layer for example of silicon (SILICON FILM) between the substrate and the conductor layer. The conductor layer (NICKEL ELECTRODE) is photolithographically patterned into an array of parallel strips each constituting a column of a driving matrix of the display. A dielectric layer, for example of an oxide (SILICON DIOXIDE), is deposited over the patterned conductor layer. A conductor layer (NIOBIUM GATE METAL), from which the grid extractor will be patterned, is deposited over the dielectric layer. The grid structure is eventually defined in parallel strips, normal to the cathode parallel strips (NICKEL ELECTRODE). According to a known technique, microapertures or wells that reach down to the surface of the underlying patterned conductor layer (NICKEL ELECTRODE) are defined and cut through the grid conductor layer (NIOBIUM GATE METAL) and through the underlying dielectric layer (SILICON DIOXIDE). Onto the surface of the conductor layer exposed at the bottom of the "wells", are fabricated microtips (MOLIBDENUM MICROTIPS) that will constitute as many sites of emission of electrons. On the inner face of a glass faceplate of the display is deposited a transparent thin conducting film, for example of a mixed oxide of indium and tin (ITO CONDUCTOR) upon which is deposited a layer of phosphors (monochromatic phosphor or color phosphors) excitable by the electrons accelerated toward the conducting layer (ITO CONDUCTOR) acting as a collector of the electrons emitted by the microtips. Emission that is stimulated by the electric field produced by suitably biasing the grid conductor and the cathode tips. In order to improve color resolution, the realization of a "switched" anodic (collector) structure for separately biasing adjacent strips, each covered with a phosphor of a different basic color, has been suggested in a publication entitled: "Phosphors For Full-Color Microtips Fluorescent Displays" by F. Lévy and R. Mayer, LETI - DOFT - SCMM, Grenoble - Cedex - France. Fabricating processes of microtips cathode plates are described in US Patents No. 4,857,161; 4,940,916; 5,194,780 and 5,391,259. One of the most widely used proceses for fabricating the cathodic structure of a FED is described in the above-mentioned US Patent No. 4,857,161. According to this well known process, after completing the formation of the grid of niobium or of any other selfpassivating metal the etching solutions normally used in the fabricating process, a lift-off layer is deposited on the grid. This lift-off layer is generally constituted by a metal that is easily and selectively wet-etchable through its exposed edges so to allow the removal (lift-off) of the cone deposition overstructure. This deposition process is carried out by sputtering at a normal incidence with the panel surface, a metal (usually a refractory metal such as molibdenum) that is also capable of resisting to the etch conditions during the the lift-off to form deposition cones within the wells that have been formed through the grid openings layer and an underlying dielectric layer. The bottom of the deposition wells of the cones is constituted by a substantially conductive layer and more preferably by a special conductive layer purposely having a high resistivity, superimposed to the highly conductive material of the selectable cathodic conductors or strips. Prevention of lift-off material deposition inside the wells is of paramount importance. At present this critical requisite of the fabrication process is fulfilled by using deposition techniques of the lift-off layer that avert deposit onto the bottom of the wells. Commonly, a lift-off layer of nickel is deposited by vacuum evaporation while maintaining an extremely small angle of incidence of the impinging nickel (i.e. at grazing angle). Of course, the panel under fabrication must be rotated around its own axis while maintaining a minimum angle of incidence in respect to the impinging flow so as to obtain a deposit of uniform thickness. This requires the presence of complex and inevitably encumbring organs for rotating the panel in the vacuum deposition chamber, considering that the panels can reach dimensions of 27 x 36 cm. All this sensibly increases the costs of fabrication of these panels. The criticality of this stage of the fabrication process has also negative repercussions on production yields. Aims and advantages of the invention Confronted with this state of the art technique, an improved fabricating procedure that substantially obviates the above-mentioned critical aspects of well known processes has now been found. The process of the invention as defined in claim 1 does not require the use of special grazing-angle-deposition devices and reduces the manufacturing costs while improving the yield. Basically, the process of the invention, differently from well known processes, does not contemplate a complete predefinition of the grid structure, rather the deposition onto a matrix layer of a corrosion-resisting metallic material from which the grid structure will be defined, of a layer of a lift-off material that can be easily and selectively etched, prior to forming the grid apertures and the corresponding wells, inside which the cathodic microtips will be eventually formed. The lift-off material can be the same masking resist or, if of another type of material, such a layer is contextually defined with the grid matrix layer and the underlying isolation dielectric layer during the etching that is performed to form the grid apertures angle and the corresponding wells. According to a first embodiment of the invention, a lift-off layer constituted by a thin layer of nickel or of another easily dissolvable metal may be used. The lift-off layer may be deposited by vacuum evaporation or sputtering at a normal incidence directly onto the surface of a grid metal matrix (still unpatterned) layer whose thickness is generally greater than the thickness of the lift-off layer. The grid matrix layer may be for example of niobium, tungsten, chromium or tantalum or alloys or stacked layers thereof deposited by vacuum evaporation, or it may be of an adequately doped polycrystalline or amorphous silicon. Parallel strips orthogonal to the cathodic conductors may or may not be predefined before depositing of the nickel or similar lift-off material. In any case, circular apertures with a diameter of about 1.0-1.5 micrometers, densely and uniformly distributed over the surface of each strip are thereafter defined through a masking step. The etching of the stack through the apertures of the resist mask, that comprise the thin lift-off layer of nickel or alike metal, the grid matrix layer of corrosion resistant metal and the underlying dielectric layer, typically of silicon oxide, may be conducted in different phases. The known difficulty of dry-etching (i.e. plasma etching) of the nickel, caused by the formation of non-volatile nickel compounds is overcome by resorting to an ion-milling technique or the like. The etching of the thin top layer of nickel or alike metal through the apertures of the mask can be carried out by a sputter etch with Argon ions. In particular, nickel shows a relatively high yield to sputtering. The possibility of carrying out a "sputter etch" in an Argon plasma is generally offered by standard of deposition plasma reactors. This feature is normally available for allowing the removal of possible superficial (native) oxide layer before starting the vacuum deposition, however this feature may be easily included in other common apparatuses such as in the same R.I.E. reactor that is used for eventually etching the grid matrix layer and the underlying isolating oxide. For example the R.I.E. etchor Precision 5000 or Centura models, both by Applied Materials Corporation, may be easily equipped to permit the carrying out of an Argon sputter etch. For instance, in the above-identified R.I.E. etcher, a preliminary Argon sputter etch phase can be carried out with a power of 300W (corresponding to a plasma voltage of about 500V) and the removal of a thin lift-off layer of nickel, whose thickness may be in the order of 15-20 nanometers (nm), would require a treatment of about two to three minutes. In a case such this, it may be convenient to use, as a grid matrix material, a doped polycrystalline or amorphous silicon layer or a tungsten layer, because both these materials are characterized by a sputter yield markedly lower that that of nickel and therefore they would provide for advantageous conditions for implementing an automatic stop of the sputter etching of the nickel layer, according to well known techniques. The anisotropic plasma etching of the grid matrix layer (for example of polycrystalline silicon, tungsten or niobium) and subsequently also of the underlying oxide or similar dielectric layer, that isolates the cathodic structure from the grid, can be carried out in sequence in the same etcher, using different chambers thereof, with different plasma compositions, specifically suited for the progression of the etching through the different materials that make up the "stack" to be etched until exposing the surface of the high resistivity layer, for example of doped polycrystalline silicon, of the cathodic structure. Alternatively, the lift-off layer of nickel can be preliminarily etched through the masking apertures, by carrying out a wet-etching step in an appropriate etching solution, for example a solution of hydrochloric acid, in a controlled manner so as to avoid overetching the nickel layer underneath the edges of the resist mask. There exists also the possibility of alternating the two types of etchings in order to ensure a complete removal of the nickel from the unmasked areas without undercutting the nickel under the mask. After having completed the etching through the stack and removed the resist mask a suitable refractory and etch-resistant metal, as for example molibdenum, is deposited by "vertical" or "quasi-vertical" sputtering, according to a common technique. This phase of construction of the microtips can comprise a plurality of steps. For example it may comprise a first stage during which a thin film (in the order of some hundreds of Angstroms) of an adhesion (for example of Chromium, tantalum or the like) material having a relatively good crystallographic affinity with the base material, typically a high resistivity doped polycrystalline silicon layer is deposited. Obviously, several layers of different materials may be deposited prior to effect a final deposition step. During last deposition step, the shielding effect of the walls of the preformed wells determines the formation of cones of deposition inside the wells whose sharp vertex approximately reaches the level of the grid before an eventual occlusion of the deposition window in the deposited overstructure that grows over the lift-off layer. Through an electrochemical etching of the lift-off layer, left exposed at the rims of the wells, the deposited overstructure of molibdenum is removed (lifted-off), thus leaving the deposition cones inside the wells cut through the isolating dielectric layer in correspondence with the grid openings. The dissolution of the lift-off layer is accelerated by anodically biasing the nickel in an acid bath, commonly with a pH ranging between 2.5 and 3. The lift-off etching of the nickel layer can be performed in an aqueous bath containing ammoniun chloride, nickel chloride and boric acid and using a biasing counterelectrode (cathode) of nickel. The anodic biasing of the lift-off nickel layer can be arranged by contacting the front of the panel, that is, the deposited conductive overstructure. In this lift-off step of the deposition overstructure of molibdenum or of a stack of superimposed etch-resistant-metals through an anodic dissolution of the underlying nickel layer, the FED panel performed cathodic structure is suitably left floating to prevent any possibility of corrosion of metallic components of the cathodic structure and in particular of the microtips themselves. Moreover, the relative corrosion resistance of the molibdenum tips and of the tungsten and/or niobium grid, is also ensured by a lower electronegativity of these metals as compared to that of nickel and by the ability of these so-called valve metals to passivate themselves under anodic polarization condition, thus impeding any further flow of corrosion current. Similar wet etch resistance properties are also shown by the polycrystalline silicon of the bottom layer of the wells onto which the cones of deposition are grown. On the contrary, the end edges of the cathodic conductors, when they are realized with an easily corrodable metal such as nickel, must be appropriately protected during the lift-off wet-etching step. Obviously, if the cathodic conductors are made of a noncorrodable material, such as for example of mixed indium and tin oxides, these precautions will not be necessary. According to a preferred embodiment of the invention, and prior to depositing a thin lift-off layer, for example of nickel, the grid matrix layer, for instance of a doped polycrystalline or amorphous silicon, tungsten, chromium or niobium, may be patterned in parallel strips, orthogonally oriented to the cathodic conductors through a first masking and etching step. In this first patternign step of the grid structure in the form of a plurality of parallel strips, the etching is not continued through the underlying dielectric. By performing such a preliminary patterning in parallel strips of the grid structure, prior to defining the wells into which will be formed the cones, produces "steps" that interrupt the continuity of the grid matrix layer along a direction orthogonal to the orientation of the strips into which the grid is subdivided. This advantageously increases the number and extension of the exposed edges of the lift-off layer, that has a thickness lower than the patterned strips of the grid matrix layer, through which will make headway the electrochemical etching. In this way, the lift-off etching can proceed more rapidly and uniformly throughout the panel. According to an alternative embodiment, the lift-off layer may be constituted by the residual layer of masking resist employed for defining the grid apertures during the etching of the grid conductor layer and of the underlying dielectric. According to this embodiment, through a first patterning step using an appropriate resist to define circular apertures of a diameter ranging approximately between 1.0-1.5 micrometers, densely distributed over the surface of the grid matrix layer, and the successive anisotropic etching, for example by R.I.E., circular apertures (holes or wells) are formed through each grid strip and through the underlying dielectric layer, typically of silicon oxide, until reaching the surface of a high resistivity layer, for example of doped polycrystalline silicon, for limiting the emission current through the microtips. Without removing the residual resist layer of the mask a suitable etch-resistant and refractory metal such as molibdenum is deposited via "vertical" or "quasi vertical" sputtering, according to a standard technique. The shielding effect of the walls of the preformed wells determines the growth of deposition cones in the wells whose sharp-pointed vertex reaches approximately the level of the grid layer before an eventual occlusion of the corresponding deposition window through the overstructure that grows above the resist layer. By using a resist particularly resistant to high temperature and eventually hardened after development by exposure to UV radiation and/or heat, for example the same type of resist commonly used for shielding drain and source implantations for defining the grid apertures and the corresponding wells, the resist mask layer that remains at the completion of the anisotropic plasma etching of the grid apertures and of the corresponding wells may be used as lift-off layer for removing the deposition overstructure of the conductive cones growth by sputtering. By etching this residual layer of masking resist in an oxygen plasma, which may precede or follow a wet-softening of the resist, for example with organic strippers, such as EKC265, that are composed of chemically activated organic solvents having a medium boiling temperature, the deposition overstructure is lifted-off. The definition of the grid into parallel strips orthogonal to the cathodic conductors may take place in a quite customary manner, through a distinct masking step. In either one of the above described embodiments of the invention, the need of carrying out depositions at a "grazing" angle of incidence requiring the use of special devices to ensure an acceptable uniformity of the deposit is avoided. Moreover, any accidental depositioin of lift-off material inside (on the bottom) of preformed wells is positively prevented thus eliminating the consequent critical aspects of the known processes. Brief description of the drawings Figure 1 is a comparative scheme of a conventional CRT display device) and a FED; Figure 2 shows in a schematic way the general architecture of a FED panel and of the respective driving circuit; Figure 3 is a schematic representation of a pixel driving mode in a FED; Figure 4 is a schematic cross-section of a FED panel; Figures 5 to 11 , illustrate a first embodiment of the process of the invention; Figures 12 to 15 , illustrate an alternative embodiment of the process of the invention. Description of preferred embodiments With reference to Figures 5 to 11 and 12 to 15, on a support plate of the dielectric material 1, typically a ceramic or a glass plate, parallel conductive strips 2 constituting the cathodic conductors of the driving matrix by pixel of the panel are defined. Commonly, in the case of relatively large panels, the cathodic conductors 2 can be patterned from a matrix layer, for example of nickel, deposited by vacuum evaporation directly onto the face of the substrate 1 or after interposition of an adhesion layer, for instance of silicon oxide (not shown in the figures). Preferably, in place of the nickel is possible to use other materials of sufficient conductivity, including nonmetals preferably having a good corrosion resistance, as for example a conductive mixed oxide of indium and tin (I.T.O.). The I.T.O. is a particularly preferred material especially in the case of screens of medium and small dimensions or destined to particular uses, for example as video cameras, oculars, etc.. Preferably, according to a well known technique, a second layer of a high resistivity material 3, as for example of polycrystalline silicon adequately doped, is deposited over the conductor layer 2. This second layer has the function of introducing a limitating resistance of the current emitted through a selectedly excited pixel. The high resistivity layer 3, may be patterned together with the matrix layer 2 of the cathodic conductors by the same masking step. Above the cathodic conductors defined on the face of the panel substrate 1, ,an isolating dielectric layer 4, for example of silicon dioxide with a thickness varying between 0.6 and 1.3 micrometers, depending on the panel characteristics is chemically deposited from a by vapor phase. Over the isolating layer 4 a conductive matrix layer of the grid 5 is deposited. The conductor material used for constituting the grid matrix layer must possess an appropriate crystallographic affinity with the material of the dielectric layer 4 to ensure a satisfactory adhesion and mechanic stability and a good chemical resistance to the etching solutions used for removing lift-off material employed in the fabrication of the panel. Preferably, the grid matrix layer 5 is of a refractory and passivable metal such as niobium, tantalum, tungsten or the like or may be of amorphous and/or polycrystalline silicon, adequately doped to reach a sufficient electric conductivity, or even of a multilayer of different conductor materials, though it is essential that they be corrosion-resistant to the lift-off etchants. The grid matrix layer 5, depending on its nature, can be deposited by vacuum evaporation or according to any other suitable method and can have a thickness of about 0.5µm, and more generally ranging between 0.2 and 0.7 µm. Preferably, the lift-off layer that is defined during the same definition step of the grid apertures, may be a thin sputtered layer of nickel. According to a preferred embodiment, illustrated in the set of Figures 5 to 11, prior to depositing the lift-off layer, a predefinition of the grid matrix metal layer 5 into a plurality of parallel strips, orthogonal to the cathodic conductors 2 (and 3), is performed to improve the etching conditions during the lift-off step. As shown in Fig. 5, after completing the deposition of the grid matrix layer 5, for instance the layer of tungsten, tantalum, niobium or polycrystalline and/or amorphous silicon adequately doped for exhibiting a sufficient electric conductivity, a definition mask R1 of the grid strips is formed. The matrix layer 5 is etched through the aperture of this mask, forming parallel strips 5a and 5b which are orthogonal to the strips constituting the cathodic conductors 2 (and 3). As noted, in this predefinition phase of the grid, the etching stops on the dielectric layer 4, without cutting through the dielectric, as shown in Fig. 6. At this point a thin layer of nickel or of any other material easily wet-etchable chemically and/or electrolitically, is deposited. In the preferred case of using nickel as lift-off material, the layer 6, deposited by sputtering, may have a thickness generally ranging between 15 and 20 nm. In any case, it is essential that the thickness of the lift-off layer 6 deposited during this phase of the process be substantially smaller than the thickness of the grid matrix layer 5, already defined in parallel strips. This with the aim of creating lines of discontinuity of the lift-off layer 6 in coincidence with the definition steps of the parallel strips 5a and 5b of the grid matrix layer 5. This is highlighted in Fig. 7. By referring to Fig. 8, a second definition mask R2 of the grid openings is formed, and through the apertures of this mask R2 a substantially anisotropic etching, of the multilayer composed by the lift-off layer of nickel 6, the grid matrix layer 5, for example of doped polycrystalline silicon, and the dielectric layer 4, for example of silicon oxide, is carried out until exposing the surface of the high resistivity layer 3 of doped polycrystalline silicon, as shown in Fig. 9. The known difficulty of dry-etching the nickel (in plasma) because of the formation of nonvolatile compounds, is overcome by submitting the panel to a process of ion-milling by way of a sputter etch with Argon for removing the nickel, as already described above. Alternatively, the top layer of nickel can be leached off by wet-etching, under controlled conditions, so to prevent or limit an undue progress of etching under the edge of the masking resist. Once the removal of the topping nickel layer 6 is completed, the underlying grid matrix layer, for example of niobium or tungsten, can be plasma etched through a common R.I.E. technique, using a Cl 2 +He+O 2 plasma or any other suitable plasma composition. Finally the R.I.E. plasma etching can continue through the isolating oxide layer 4, using a CF 4 or a CHF 3 mixture in Ar under a vacuum of about 170 mT. In place of niobium or tungsten a doped polycrystalline or amorphous silicon is used as the conductor material of the grid matrix layer 5, the R.I.E. etching of this material can be carried out using an HBr or Cl 2 mixture under a vacuum of about 300 mT, after performing a preliminary cleaning step, for example in a He+O 2 plasma and removing the native oxide in a C 2 F 6 plasma. The diameter of the grid apertures and of the underlying wells 7 may usually range from 0.5 to 1.5 micrometers, depending on the size of the panel. The walls of the etched wells are substantially vertical, in view of the high anisotropy of the plasma etching process used. The structure that is obtained in schematically shown in Fig. 9. The structure is substantially similar to the one obtained by the known process, without resorting to the special and burdensome techniques of deposition at a grazing angle of incidence of the lift-off layer 6. Moreover, the etching that produces the circular apertures 7 through the grid matrix layer 5 and the underlying dielectric layer until exposing the surface of the high resistivity layer 3, takes place after having deposited the lift-off material 6 onto the grid matrix layer 5, thus eliminating any possibility of contaminating the bottom of the wells 7 produced. After an eventual deposition of one or more layers of "adhesion" or "compatibility" conductive materials, the process of deposition via sputtering at normal incidence, produce a conoidal growth of the deposit within the wells 7 due to the shielding effect of the vertical walls of the well that continues and becomes more and more accentuated with the growing of the deposit 9 onto the surface of the lift-off layer. The growth of the cones eventually terminates with an almost complete occlusion of the correspondent narrowing deposition window through the overstructure 9 resting on the nickel layer 6. This peculiar form of deposit that is produced is schematically illustrated in the cross-section of Fig. 10. The deposition cones 8 that are produced within the wells because of the shielding effect of the surrounding walls are clearly visible. This effect is due to a progressive narrowing of the deposition window that occurs with the growth of the deposition overstructure 9, up to an almost complete occlusion of the opening. Of course, the diameter of the well 7, the thickness of the dielectric layer 4 and the thickness of the grid conductor 5, are coordinated among themselves and with the conditions of deposition via sputtering of the molibdenum in wells formed in this stack so that the apex of the deposition cones reach approximately the same level of the grid electrode 5, as shown in Fig. 10. Removal of the deposition overstructure 9 is carried out by electrochemically etching the lift-off layer of nickel according to the embodiment already described above. According to the alternative embodiment illustrated in the set of Figures 12 to 15, onto the surface of the conductive matrix layer 5 of the grid structure is formed a mask R defining the openings that are to be formed through the matrix layer 5 of the underlying wells 7 to be dug in the isolating dielectric layer 4, the bottom of which will be constituted by the surface of the underlying high resistivity layer 3. This mask R is photolithographically defined using preferably a negative resist, for example the NFR 020 resist produced by the JSR Company, having enhanced characteristics of thermal stability and able of withstanding the sputter deposition of the conductive materials forming the microtips, as well as eventual heat and vacuum treatments, as normally performed to prevent outgassing phenomena during the deposition of the microtip metal. The etching of the grid matrix layer and of the underlying isolation dielectric layer is carried out through the apertures of the resist mask R. Once the etching is completed, the residual resist of the mask R is not removed, instead the sputter deposition of a refractory metal, for example molibdenum is carried out. This deposition may or may not be preceded by the deposition of one or more thin compatibility or adhesion layers, for example of chromium. The peculiar shape of the molibdenum deposit that is eventually produced is illustrated in a cross-schematic way in the section of Fig. 14. These are clearly visible the deposition cones 8 that are produced within the wells 7 by virtue of the shielding effect of the surrounding walls, effect which is substantially due to a progressive shrinking of the deposition window that occurs with the growing of the deposit 9, until an eventual nearly complete occlusion of the openings. The diameter of the wells 7, the thickness of the dielectric layer 4 and the grid conductor layer 5, and in this case also, thickness R of the resist mask, are coordinated among them and with the sputtering conditions of the molibdenum, in order to ensure that the apex of the deposition cones 8 reach almost the same level of the grid electrode 5, as shown in Fig. 15. According to this alternative embodiment of the invention, the lift-off of the deposition overstructure 9 takes place by leaching off the resist layer R by medium boiling point organic strippers as for example the EKC 265 solvent, followed or preceded by a dry etching in an oxygen plasma.

Claims: A process for forming a microtip cathode on a field emission display (FED) panel (1) comprising the steps of depositing a first conductive layer (2) on a dielectric substrate and optionally depositing thereon at least a layer (3) of a material having a resistivity higher than the first conductive layer (2), defining by masking and etching parallel strips of said conductive first layer or multilayer (2, 3), forming a plurality of cathode conductors that constitute the columns of a driving matrix of the display organized in rows and columns, depositing an insulating layer (4) of a dielectric material over the entire surface of the substrate and of said cathodic conductors (2, 3) defined thereon, depositing at least a second conductive layer (5) above said dielectric layer (4), defining by masking and etching a population of circular apertures in said second conductive layer and digging wells (7) through said dielectric layer (4) in coincidence with said circular apertures until exposing the surface of said cathode conductors (2, 3) at the bottom of said wells (7), depositing by sputtering a conductive material (8, 9) causing the growth of deposition cones (8) on the bottom of each of said wells, removing from the surface the deposited overstructure (9) of said conductive material by a lift-off technique using a lift-off layer (6), patterning said second conductive layer (5) into parallel strips orthogonal to said cathodic conductors constituting the rows of said driving matrix, characterized by patterning by a second masking and etching steps said second conductive layer (5) into parallel strips orthogonal to said cathodic conductors (2, 3) and successively defining together, by a third masking and etching step, said circular apertures and a layer (6) of lift-off material deposited over said second conductive layer (5). The process according to claim 1, characterized in that said lift-off layer (6) is constituted by a patterned resist layer of a mask through the apertures of which said second conductive layer (5) and said dielectric layer (4) are etched and which is left purposely on the surface of the panel during the subsequent sputter deposition of the cone material (8, 9). The process according to claim 1, characterized in that said lift-off layer (6) is a nickel layer deposited above said second conductive layer (5) and etched by a wet-etching step and/or by an ion bombardment step through the openings of said mask for defining said second conductor layer (5). The process according to claim 1, characterized in that said isolating dielectric layer (4) is of silicon oxide, said second conductive layer (5) is of a material belonging to the group composed of niobium, tungsten, chromium, tantalum, doped polycrystalline or amorphous silicon and said material forming the cones (8) belongs to the group composed of molibdenum, tungsten, chromium and tantalum. The process according to claim 4, characterized in that said second conductive layer (5) is a stack of said conductive materials. The process according to claim 1, characterized in that said lift-off layer (6) is metallic and has a thickness lower than the thickness of said second conductive layer (5). The process according to claim 6, characterized in that said lift-off layer (6) is of nickel and has a thickness ranging from 15 to 20 nm, while said second conductive layer (5) is of a material belonging to the group composed of tungsten and doped polycrystalline or amorphous silicon, and has a thickness comprised between 200 and 700 nm.

Inventors: BALDI LIVIO, TONTI ALESSANDRO, BALDI, LIVIO, TONTI, ALESSANDRO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: H01J9
IPC codes: H01J9