Latch circuit

Abstract: The present invention discloses an improved latch circuit. In the latch circuit, a composite gate takes in a basic clock signal and a delayed clock signal which is delayed by a delay circuit for a specific amount with respect to the basic clock signal, and puts out to a second drive circuit a first signal identical in waveform with the basic clock signal, and further puts out to a first drive circuit a second signal that is delayed in the rising timing with respect to the first signal. As a result of such arrangement, when a transition is made from a feedback period during which an input switch has an off state while a feedback switch has an on state to a sampling period during which the input switch has an on state while the feedback switch has an off state, neither the input switch nor the feedback switch has an on state.

Description: This invention pertains to a latch circuit for use in semiconductor integrated circuits. There have been demands for down-sized, lightweight electric appliances. Generally portable electric appliances for personal use are battery-powered. As the battery size becomes smaller the electric appliance becomes down-sized and lightweight. Therefore, decreasing the battery size requires low-power electronic circuit sections and mechanism sections. The semiconductor industry is thus now trying to produce low-power semiconductor integrated circuit devices. Especially a low-power analog-to-digital converter for processing of video signals for use by portable video cameras is demanded. Therefore, for the purpose of accomplishing low power dissipation, a chopper inverter amplifier is often used in analog-to-digital (A/D) converters. Japanese Patent Application, published under Pub. No. 63-80617, shows an A/D converter. A comparator is made up of a chopper inverter amplifier and a latch circuit that is located at a stage after the chopper inverter amplifier. This latch circuit includes two inverters (the first- and second-stage inverters) connected in series, an input switch connected between an input terminal of the first-stage inverter and an output terminal of the chopper inverter amplifier, and a feedback switch connected between the input terminal of the first-stage inverter and an output terminal of the second-stage inverter. FIGURE 17 illustrates a conventional latch circuit structure. 51 is an external input terminal. 52 is a first inverter. 53 is a second inverter. 54 is an external output terminal. An input switch S1 is made up of a PMOS 55a and an NMOS 55b . A feedback switch S2 is made up of a PMOS 56a and an NMOS 56b . Whereas a control voltage V  is applied to a gate of the PMOS 55a and to a gate of the NMOS 56b , a control voltage /V  that is an inversion of the control voltage V  is applied to a gate of the NMOS 55b and to a gate of the PMOS 56a . If V  is HIGH, then /V 0 is LOW. Both the PMOS 55a and the NMOS 55b go into the nonconducting state, and the input switch S1 turns off. Meanwhile, both the PMOS 56a and the NMOS 56b go into the conducting state, and the feedback switch S2 turns on. This period is called a feedback period. If V  is LOW, then /V  becomes HIGH. The PMOS 55a and the NMOS 55b each go into the conducting state, and the input switch S1 turns on. On the other hand, the PMOS 56a and the NMOS 56b each go into the nonconducting state, and the feedback switch S2 turns off. This period is called a sampling period. In the FIGURE 17 latch circuit, the input switch S1 and the feedback switch S2 make their transition at the same time. If V in (the voltage applied at the external input terminal 51 ) is greater than V a (the first inverter's 52 threshold voltage) at the end of a sampling period, then an output voltage of the second inverter 53 is fed back in a positive feedback manner to become V DD (the supply voltage) in a feedback period. If V in is lower than V a at the end of a sampling period, then an output voltage of the second inverter 53 is fed back in a positive feedback manner to become V SS (the ground voltage) in a feedback period. A conventional latch circuit, however, presents the following problems. The inventors of the present application found that in actual latch circuit operations a phenomenon that the input switch S1 and the feedback switch S2 simultaneously have an on state occurs resulting in impeding high-speed, high-accuracy latch circuit operations. The aforesaid phenomenon is explained in detail. FIGURE 18 shows the operation of the input switch S1 as well as the operation of the feedback switch S2 . As seen from FIGURE 18, V 0 remains HIGH until time t 1 , which is to say, the latch circuit is in a feedback period. Suppose V  begins making a HIGH→LOW transition at time t 1 and the latch circuit holds V DD in a feedback period. Applied at terminals of the input switch S1 are V in applied at the external input terminal 51 and V DD held by the latch circuit. As shown in a graph (the above one) of FIGURE 18, the PMOS 55a of the input switch S1 conducts when V  becomes lower than V DD by V tp (the threshold voltage), and the NMOS 55b of the input switch S1 conducts when /V 0 becomes greater than V in by V tn (the threshold voltage). Applied at the terminals of the feedback switch S2 is V DD held by the latch circuit. As shown in a graph (the below one) of FIGURE 18, the PMOS 56a of the feedback switch S2 goes into the nonconducting state when /V  becomes lower than V DD by V tp , and the NMOS 56b of the feedback switch S2 remains nonconducting because it is impossible for V  to become greater than V DD by V tn . Accordingly, at the time when a feedback→sampling transition is made, there is a period during which both the input switch S1 and the feedback switch S2 simultaneously have an on state. Likewise at the time when a sampling→ feedback transition is made, there is a period during which both the input switch S1 and the feedback switch S2 simultaneously have an on state. The operation of the latch circuit is shown in FIGURE 19. The FIGURE 19 latch circuit has the first inverter 52, the second inverter 53 , and the input switch S1 , and the feedback switch S2 . 61 is a preceding-stage amplifier. As shown in FIGURE 19, there exists a first transitional period during which both the input switch S1 and the feedback switch S2 have an on state at the same time when there is made a feedback→sampling transition, while there exists a second transitional period during which both the input switch S1 and the feedback switch S2 have an on state at the same time when there is made a sampling→feedback transition. The presence of the first transitional period produces some problems. FIGURE 20 is a graph showing changes in the output voltage of the amplifier 61 in the first transitional period. The amplifier's 61 output voltage is represented by solid line and the second inverter's 53 output voltage is represented by dot-dash line. V a is the first inverter's 52 threshold voltage. If in the feedback period the latch circuit holds V DD , then the second inverter's 53 output voltage is V DD . Suppose the amplifier 61 outputs a voltage of V in that is slightly lower than V a . In the first transitional period, both the input switch S1 and the feedback switch S2 each have an on state, as a result of which the amplifier's 61 output voltage is driven to the second inverter 53 to go up to near V DD . In the sampling period, the feedback switch S2 turns off, so that the amplifier's 61 output voltage is again driven to V in . However, the amplifier's 61 output voltage has been increased to near V DD in the first transitional period, so that it needs a period of time known as the settling time to become V in again. If a next feedback operation is performed during the settling time, then the latch circuit is likely to hold V DD although V in was lower than V a . This prolongs the length of the sampling period because the settling time must be included therein. More specifically, 10-15 ns is required, thereby producing a bar to high-speed latch circuit operations. The presence of the second transitional period, too, produces some problems. FIGURE 21 is a graph showing changes in the input voltage of the first inverter 52 in the second transitional period. The first inverter's 52 input voltage is represented by solid line and the second inverter's 53 output voltage is represented by dot-dash line. V a is the first inverter's 52 threshold voltage. If in the sampling period the first inverter's 52 output voltage changes from a certain voltage level below V a to a higher level, the second inverter's 53 output voltage changes with a delay with respect to the first inverter's 52 input voltage. If the latch circuit goes into the second transitional period when the first inverter's 52 input voltage exceeds V a and when the second inverter's 53 output voltage is below V a , both the input switch S1 and the feedback switch S2 have an on state and the first inverter's 52 input voltage is driven to the second inverter 53 to become lower than V a . Accordingly the latch circuit comes to hold V SS in the feedback period although the first inverter's 52 input voltage was higher than V a at the end of the sampling period. The accuracy of latch circuit operation is reduced. US-A-4 691 122 describes a CMOS D-type flip-flop stage consisting of a master and a slave section. Each section includes an input switch and an inverting amplifier connected in series. A feedback switch and a further inverting amplifier are provided in each section to perform a feedback operation. The input and feedback switch of a section are controlled by separate clock signals such that the input and feedback switch do not have a simultaneous on-state. A charge balancing comparator is described in US-A-4 547 683. Gain stages are provided with a switch connected between an input node and an output node of the gain stage. By closing the switch, the nodes are brought to a predetermined voltage value. It is an object of the present invention to provide an improved latch circuit. This object is achieved by the features of claim 1. In accordance with this latch circuit, it is arranged such that the first and second switch means do not have at the same time an on state. This eliminates a period for the noninverting amplifier to drive a voltage coming in from the external input terminal. Input voltage disturbance occurring in a conventional latch circuit can be controlled thereby improving the rate and accuracy of latch circuit operation. In the above-described latch circuit, the noninverting amplifier comprises an even number of inverting amplifiers connected in series. The latch circuit includes a capacitor with two terminals, one of which being connected to an input terminal of a last-stage inverting amplifier of the inverting amplifiers and the other of which being connected to an output terminal of the last-stage inverting amplifier. The provision of the capacitor reduces the effect of the operation of a circuit located at a stage after the latch circuit, and voltage transition disturbance in a latch circuit feedback operation can be controlled. FIGURE 1 is a block diagram outlining a structure of a first latch circuit useful for the understanding of the present invention. FIGURE 2 , comprised of FIGURES 2a, 2b , 2c , and 2d , shows structural elements of the first latch circuit of FIGURE 1 , wherein FIGURE 2a shows a delay circuit, and FIGURE 2b shows a switch device, and FIGURE 2c shows a drive circuit, and FIGURE 2d shows a composite gate. FIGURE 3 is a circuit diagram showing an embodiment of the first latch circuit. FIGURE 4 is an input/output signal timing diagram for a composite gate included in the first latch circuit. FIGURE 5 is a timing diagram useful in understanding the operation of a latch section of the first latch circuit. FIGURE 6 is a graph showing changes in the voltage applied at an external input terminal, in the operation of the latch section of the first latch circuit. FIGURE 7 illustrates an embodiment of a second latch circuit useful for the understanding of the present invention. FIGURE 8 is an input/output signal timing diagram for a composite gate included in the second latch circuit. FIGURE 9 is a timing diagram useful in understanding the operation of a latch section of the second latch circuit. FIGURE 10 is a graph showing changes in the voltage applied at an external input terminal, in the operation of the latch section of the second latch circuit. FIGURE 11 , comprised of FIGURES 11a and 11b , shows structural elements of a third latch circuit useful for the understanding of the present invention, wherein FIGURE 11a shows a composite gate and FIGURE 11b shows a delay circuit. FIGURE 12 shows an embodiment of the third latch circuit. FIGURE 13 is an input/output signal timing diagram for a composite gate included in the second latch circuit. FIGURE 14 is a timing diagram useful in understanding the operation of a latch section of the third latch circuit. FIGURE 15 illustrates a latch section of a fourth latch circuit useful for the understanding of the present invention. FIGURE 16 illustrates a latch section of a fifth latch circuit in accordance with the present invention. FIGURE 17 is a circuit diagram showing a conventional latch circuit structure. FIGURE 18 shows the operation of an input switch as well as the operation of a feedback switch in a conventional latch circuit. FIGURE 19 is a diagram showing the operation of a conventional latch circuit. FIGURE 20 is a graph showing changes in the output voltage of an amplifier 61 in the operation of a conventional latch circuit. FIGURE 21 is a graph showing changes in the input voltage of a first inverter 52 in the operation of a conventional latch circuit. In the following description, a latch circuit in accordance with the present invention comprises an inverter, a switch, a logical circuit, a delay circuit, and the like. An inverter is formed by a circuit which takes in a positive voltage and puts out a negative one, or vice versa such as a CMOS inverter, an E/D inverter, and an NMOS inverter. A switch is formed by a CMOS switch, an NMOS switch, or a PMOS switch. Referring now to the drawing figures, preferred embodiments of the present invention are described below. FIGURE 1 outlines a first latch circuit useful for the understanding of the present invention. The first latch circuit has a latch section 12 formed by an external input terminal 1 , a first inverter 2 , a second inverter 3 , an external output terminal 4 , an input switch S1 as a first switch means, and a feedback switch S2 as a second switch means. The first and second inverters 2 and 3 together form a noninverting amplifier 5 . The input switch S1 is connected between the external input terminal 1 and an input terminal of the first inverter 2 . When the input switch S1 has an on state, an input voltage applied at the external input terminal 1 is fed to the first inverter 2 . The first inverter 2 is associated with the input switch S1 and acts as an amplifier for input voltage inverting amplification. The second inverter 3 is connected in series to the first inverter 2 and acts as an amplifier for inversion-amplifying an output voltage of the first inverter 2 . The feedback switch S2 is connected between the input terminal of the first inverter 2 and an output terminal of the second inverter 3 . When the feedback switch S2 has an on state, an output voltage of the second inverter 3 is fed back in a positive feedback manner to the first inverter 2 via the feedback switch S2 . The external output terminal 4 is an output terminal at which an output voltage of the second inverter 3 is put out to outside the latch circuit. Additionally the first latch circuit has a control section 11 comprising a first drive circuit 6 , a second drive circuit 7 , a composite gate 8 as a signal generation means, a delay circuit 9 , and a signal input terminal 10 . Whereas the first drive circuit 6 is operable to turn on or off the input switch S1 , the second drive circuit 7 is operable to turn on or off the feedback switch S2 . The composite gate 8 accepts a signal from the signal input terminal 10 and a signal from the delay circuit 9 and performs a logical operation on the signals received. The signal input terminal 10 is an input terminal for accepting a basic clock signal based on which each operation period of the latch section 12 is determined. FIGURE 2a is a circuit diagram depicting an example of the delay circuit 9 . As shown in the figure, the delay circuit 9 is made up of a first-stage inverter 14 and a second-stage inverter 15 connected together in series. A sum of the time taken for a pulse to traverse the inverter 14 and the time taken for a pulse to traverse the inverter 15 is the delay circuit's 9 delay time. Since the number of inverters to be connected in series is designed to be even, a signal taken in at an input terminal 13 and a signal put out at an output terminal 16 have the same polarity. FIGURE 2b is a circuit diagram showing an example of the switch S1 ( S2 ). Since the input switch S1 and the feedback switch S2 are identical in configuration with each other, only the input switch S1 is described here. As shown in FIGURE 2b , the input switch S1 is a transmission gate formed by a PMOS transistor and an NMOS transistor. The input switch S1 has input terminals 17 , 18 and control terminals 19 , 20 . The FIGURE 2b switch is turned on or off by control signals applied at the control terminals 19 and 20 . FIGURE 2c is a circuit diagram showing an example of the drive circuit 6 ( 7 ). Since the drive circuits 6 and 7 are identical circuits, only the drive circuit 6 is described here. As shown in FIGURE 2c , the drive circuit 6 is formed by an in-series connection path consisting of five inverters connected in series and a branch path consisting of three inverters connected in series and branching off at the output side of a first-stage inverter of the in-series connection path. The drive circuit 6 has an input terminal 21 , an inverting output terminal 22 , and a noninverting output terminal 23 . If a signal, taken in at the input terminal 21 , is transmitted through the in-series connection path, an inverting signal is put out at the inverting output terminal 22 . On the other hand, if a signal is transmitted first through the first-stage inverter and then through the branch path, a noninverting signal is put out at the noninverting output terminal 23 . These noninverting and inverting signals are applied as control signals to the terminals 19 and 20 of the FIGURE 2b switch, respectively. FIGURE 2d is a circuit diagram showing an example of the composite gate 8 . As shown in FIGURE 2d , this composite gate 8 is made up of a first NAND gate with two input terminals associated with a terminal I1 , a first inverter which is connected to a stage after the first NAND gate and which has an output terminal associated with a terminal O1 , a second NAND gate with two input terminals respectively associated with the terminal I1 and a terminal I2 , and a second inverter which is connected to a stage after the second NAND gate and which has an output terminal associated with a terminal O2 . FIGURE 3 is an embodiment of the first latch circuit. This embodiment is implemented employing the FIG. 2a delay circuit, the FIG. 2b switch, the FIG. 2c drive circuit, and the FIG. 2d composite gate. In the latch section 12 , the terminal 17 of the input switch S1 is connected to the external input terminal 1 and the terminal 18 thereof is connected to the input terminal of the noninverting amplifier 5 . The terminal 17 of the feedback switch S2 is connected to the input terminal of the noninverting amplifier 5 and the terminal 18 thereof is connected to the output terminal of the noninverting amplifier 5 . In the control section 11 , the input terminal 13 of the delay circuit 9 is connected to the signal input terminal 10 . The terminal I1 of the composite gate 8 is connected to the signal input terminal 10 and the terminal I2 is connected to the output terminal 16 of the delay circuit 9 . The terminal O1 of the composite gate 8 is connected to the input terminal 21 of the second drive circuit 7 and the terminal O2 thereof is connected to the input terminal 21 of the first drive circuit 6 . The inverting output terminal 22 of the first drive circuit 6 is connected to the terminal 19 of the input switch S1 and the noninverting output terminal 23 thereof is connected to the terminal 20 of the input switch S1 . The inverting output terminal 22 of the second drive circuit 7 is connected to the terminal 20 of the feedback switch S2 and the noninverting output terminal 23 thereof is connected to the terminal 19 of the feedback switch S2. The internal organization of each of the first drive circuit 6 , the second drive circuit 7 , and the composite gate 8 is not shown in FIGURE 3 . The operation of the first latch circuit is explained by making reference to FIGURES 4 and 5 . FIGURE 4 is an input/output signal timing diagram for the composite gate 8 . A basic clock signal is directly applied to the terminal I1 of the composite gate 8 from the signal input terminal 10 . This basic clock signal is also indirectly applied to the terminal I2 of the composite gate 8 via the delay circuit 9 . In other words, the terminal I2 accepts a delayed clock signal that is delayed by means of the delay circuit 9 a specific amount with respect to the basic clock signal. The composite gate 8 puts out at the terminal O1 a first signal identical in waveform with the basic clock signal. The composite gate 8 further puts out at the terminal O2 a second signal that is delayed only in the rising timing with respect to the first signal. The first drive circuit 6 generates from a signal from the terminal O2 of the composite gate 8 a noninverting signal and an inverting signal, for on-off controlling of the input switch S1 . Likewise the second drive circuit 7 generates from a signal from the terminal O1 of the composite gate 8 a noninverting signal and an inverting signal, for on-off controlling of the feedback switch S2 . FIGURE 5 is a timing diagram showing the operation of the latch section 12 . As shown in FIGURE 5 , the latch section 12 is characterized in that there is established a separation period between a feedback period and a sampling period, during which both the input switch S1 and the feedback switch S2 have an off state. In the sampling period, the input switch S1 has an on state while on the other hand the feedback switch S2 has an off state. In this situation, the first inverter 2 takes in a voltage, applied at the external input terminal 1 , as its input voltage. The first inverter 2 inversion-amplifies this input voltage on the basis of V a (the threshold voltage). This inversion-amplified voltage is further inversion-amplified by the second inverter 3 and is put out. A voltage that the first inverter 2 takes in and a voltage that the second inverter 3 puts out have the same polarity on the basis of V a . In the feedback period, the input switch S1 has an off state while the feedback switch S2 has an on state. The on/off state of the input switch S1 and the on/off state of the feedback switch S2 are switched simultaneously. Upon completion of such switching, an output voltage of the second inverter 3 is fed back, in a positive feedback manner, to the input terminal of the first inverter 2 by way of the feedback switch S2 that is now in the on state. Because of such positive feedback, an input voltage of the first inverter 2 and an output voltage of the second inverter 3 are driven to the supply voltage or ground voltage. Therefore a voltage that the external input terminal 1 accepts at the end of the sampling period is driven to the supply voltage or ground voltage on the basis of V a (i.e., the first inverter's 2 threshold voltage), and is put out from the external output terminal 4 . Next, the input switch S1 stays off while the feedback switch S2 makes an on→off transition. Such a situation where both the input switch S1 and the feedback switch S2 have an off state is called a separation period. The provision of the separation period prevents the input switch S1 and the feedback switch S2 from simultaneously having an on state. Although a conventional latch circuit produces the phenomenon that in the feedback→sampling transition a voltage that the external input terminal 1 accepts is driven towards a voltage held by the second inverter 3 in the feedback period, the present invention, as a result of the foregoing arrangement, prevents the occurrence of such a phenomenon. Additionally this enables a circuit located at a preceding stage to the latch circuit to operate without distortion. FIGURE 6 is a graph showing changes in the voltage applied at the external input terminal 1 in a feedback→ sampling transition. In FIGURE 6 , the voltage applied at the external input terminal 1 is represented by solid line and the voltage held by the second inverter 3 in the feedback period is represented by dot-dash line. As seen from FIGURE 6 , a voltage applied at the external input terminal 1 is not affected by a voltage held by the second inverter 3 in the feedback period because there is provided a separation period. Since the settling time can be reduced, this provides fast latch operations. A separation period of, say, about 1.5 ns will produce sufficient effects. Therefore the separation period can be set much lower than the settling time (10-15 ns). In accordance with the first latch circuit, the control section 11 , consisting of the first drive circuit 6 , the second drive circuit 7 , the composite gate 8 , and the delay circuit 9 , controls in an active manner the operation order of the switches S1 and S2 of the latch section 12 , and a separation period is established between a feedback period and a sampling period. This arrangement not only allows a circuit located at a preceding stage to the latch circuit to operate without distortion but also enables high-speed latch operations. Referring to the drawing figures, a second latch circuit useful for the understanding of the present invention is described below. FIGURE 7 illustrates an embodiment of the second latch circuit. As in the first embodiment, the second latch circuit is made up of different circuits as shown in FIGURE 2 . Only features of the second latch circuit are described here. In the first embodiment (see FIGURE 3 ), the terminal I1 of the composite gate 8 is connected to the signal input terminal 10 while the terminal I2 thereof is connected to the output terminal 16 of the delay circuit 9 . In the second latch circuit, however, the terminal I2 of the composite gate 8 is connected to the signal input terminal 10 while the terminal I1 thereof is connected to the output terminal 16 of the delay circuit 9 . With the exception of such connection differences, the second latch circuit is identical in configuration with the first latch circuit. Elements in the second embodiment, which are functionally equivalent to their counterparts of the first embodiment, are thus assigned the same reference numerals and they are not described in detail here accordingly. By making reference to FIGURES 8 and 9 , how the second latch circuit operates is explained. FIGURE 8 is an input/output signal timing diagram for the composite gate 8 . As shown in FIGURE 8 , a delayed clock signal that is delayed by the delay circuit 9 for a specific amount with respect to a basic clock signal is applied to the terminal I1 of the composite gate 8 . The terminal I2 of the composite gate 8 accepts a basic clock signal directly from the signal input terminal 10 . Thereafter the composite gate 8 provides a first signal identical in waveform with the basic clock signal at the terminal O1 . The composite gate 8 further puts out a second signal that is advanced only in the falling timing with respect to the first signal, at the terminal O2 . The first drive circuit 6 generates from a signal from the terminal O2 of the composite gate 8 a noninverting signal and an inverting signal for on-off controlling of the input switch S1. Likewise the second drive circuit 7 generates from a signal from the terminal O1 of the composite gate 8 a noninverting signal and an inverting signal for on-off controlling of the feedback switch S2 . FIGURE 9 is a timing diagram showing the operation of the latch section 12 . As shown in FIGURE 9 , the latch section 12 is characterized in that there is established a hold period between a sampling period and a feedback period, during which both the input switch S1 and the feedback switch S2 have an off state. Neither the sampling period operation nor the feedback operation is not described here since they are identical with their counterparts of the first embodiment. Accordingly only the hold period operation is described. In a sampling→feedback transition, the feedback switch S2 stays off while the input switch S1 makes an on→ off transition. Such a situation where both the input switch S1 and the feedback switch S2 are in the off state is called a hold period. The provision of the hold period prevents the input switch S1 and the feedback switch S2 from simultaneously having an on state. Although a conventional latch circuit produces the phenomenon that in a sampling→feedback transition a voltage applied at the external input terminal 1 is driven towards a voltage provided by the second inverter 3 in a sampling period, the present invention, as a result of the foregoing arrangement, prevents the occurrence of such a phenomenon. Additionally this enables a circuit located at a preceding stage to the latch circuit to operate without distortion. FIGURE 10 is a graph showing changes in the input voltage of the first inverter 2 in a sampling→feedback transition. In FIGURE 10 , the input voltage of the first inverter 2 is represented by solid line and the output voltage of the second inverter 3 is represented by dot-dash line. In the hold period, an input voltage of the first inverter 2 is not affected by an output voltage of the second inverter 3, being maintained at the same level as at the end of the sampling period. Since the first inverter 2 takes in a voltage greater than V a (i.e., the first inverter's 2 threshold voltage), this causes the second inverter 3 to provide a supply voltage in a feedback period. This provides improvements in latch circuit operation accuracy. In accordance with the second latch circuit, the control section 11 , consisting of the first drive circuit 6 , the second drive circuit 7 , the composite gate 8 , and the delay circuit 9 , controls in an active manner the operation order of the switches S1 and S2 of the latch section 12 , and a hold period is established between a sampling period and a feedback period. This arrangement not only enables a circuit located at a preceding stage to the latch circuit to operate without distortion but also improves the accuracy of latch circuit operation. By making reference to the drawing figures, a third latch circuit useful for the understanding of the present invention is described below. FIGURE 11a shows an example of a composite gate 8A for use in the third latch circuit. As shown in FIGURE 11a , the composite gate 8A is composed of a first NAND gate with two input terminals both connected to a terminal I1 , a first inverter which is connected to the next stage after the first NAND gate and which has an output terminal connected to a terminal O1 , a second NAND gate with two input terminals, one of which being connected to a terminal I2 and the other being connected to a terminal I3 , and a second inverter which is connected to the next stage after the second NAND gate and which has an output terminal connected to a terminal O2 . FIGURE 11b shows an example of a delay circuit 9A employed in the third latch circuit. As shown in FIGURE 11b , the delay circuit 9A is composed of a first delay section circuit of inverters 25 and 26 connected in series and a second delay section circuit of inverters 27 and 28 connected in series, the first and second delay sections being connected together in series. A sum of the time taken for a pulse to traverse the inverter 25 and the time taken for a pulse to traverse the inverter 26 is defined as the first delay time, and a sum of the time taken for a pulse to traverse the inverter 27 and the time taken for a pulse to traverse the inverter 28 is defined as the second delay time. Since the number of inverters to be connected in series in each of the first and second delay section circuits is designed to be even, a signal applied at an input terminal 24 and signals provided at output terminals 29 and 30 are the same in polarity. FIGURE 12 shows an embodiment of the third latch circuit wherein FIGURE 2b switches are used as the input switch S1 and as the feedback switch S2 , FIGURE 2c drive circuits are used as the first drive circuit 6 and as the second drive circuit 7 , a FIGURE 11a composite gate is used as the composite gate 8A , and a FIGURE 11b delay circuit is used as the delay circuit 9A . In the control section 11 , the input terminal 24 of the delay circuit 9A is connected to the signal input terminal 10 . The terminal I1 of the composite gate 8A is connected to the output terminal 29 of the delay circuit 9A , and the terminal I2 is connected to the signal input terminal 10 , and the terminal I3 is connected to the output terminal 30 of the delay circuit 9A . The terminal O1 of the composite gate 8A is connected to the input terminal 21 of the second drive circuit 7 and the terminal O2 is connected to the input terminal 21 of the first drive circuit 6 . With the exception of such interconnection relationships the second latch circuit is identical in organization with the first and second latch circuits. Elements in the third embodiment, which are functionally equivalent to their counterparts of FIGURES 1 , 3 , 7 , are thus assigned the same reference numerals and they are not described in detail here accordingly. Referring now to FIGURES 13 and 14 , the operation of the third latch circuit is described below. FIGURE 13 is an input/output signal timing diagram for the composite gate 8A . A basic clock signal is delayed by the first delay section circuit of the delay circuit 9A by the first delay time, thereafter being applied as a first delayed clock signal to the terminal I1 of the composite gate 8A . The terminal I2 of the composite gate 8A accepts a basic clock signal directly from the signal input terminal 10 . The first delayed clock signal is further delayed by the second delay section circuit of the delay circuit 9A by the second delay time, thereafter being applied as a second delayed clock signal to the terminal I3 of the composite gate 8A . The composite gate 8A operates to provide a first signal identical in waveform with the basic clock signal at the terminal O1 . The composite gate 8A further provides, at the terminal O2 , a second signal that is delayed in the rising timing and advanced in the falling timing with respect to the first signal. The first drive circuit 6 generates from a signal from the terminal O2 of the composite gate 8 a noninverting signal and an inverting signal for on-off controlling of the input switch S1 . Likewise the second drive circuit 7 generates from a signal from the terminal O1 of the composite gate 8 a noninverting signal and an inverting signal for on-off controlling of the feedback switch S2. FIGURE 14 is a timing diagram showing the operation of the latch section 12 of the third latch circuit. As shown in FIGURE 14 , the latch section 12 is characterized in that there is established not only a separation period between a feedback period and a sampling period during which both the input switch S1 and the feedback switch S2 have an off state but also a hold period between a sampling period and a feedback period during which both the input switch S1 and the feedback switch S2 have an off state. In the sampling, feedback, separation, and hold periods, the latch section 12 of the third latch circuit operates in the same way that the first and second latch circuits operate and the operation of each period is not described here. In accordance with the third latch circuit, the control section 11 , consisting of the first drive circuit 6 , the second drive circuit 7 , the composite gate 8A , and the delay circuit 9A , controls in an active manner the operation order of the switches S1 and S2 of the latch section 12 , and a separation period between a feedback period and a sampling period as well as a hold period between a sampling period and a feedback period is provided. This arrangement not only enables a circuit located at a preceding stage to the latch circuit to operate without distortion but also increases the rate and accuracy of latch circuit operation. With reference to the drawing figures, a fourth latch circuit useful for the understanding of the present invention is now described below. FIGURE 15 is a circuit diagram of a latch section of the fourth latch circuit. The latch section of the fourth latch circuit is identical in configuration with the latch section 12 of the first latch circuit of FIGURE 1 except that the present latch section has a capacitor C1 connected between the input and output terminals of the first inverter 2 . The capacitor C1 is provided to reduce the degree of affection produced by a parasitic capacitor Cs between the input terminal of the first inverter 2 and ground. Elements of FIGURE 15 , which are functionally equivalent to their counterparts of FIGURE 1 , are thus assigned the same reference numerals and they are not described in detail here accordingly. The latch section of the fourth latch circuit may find applications in any one of the first, second, and third latch circuits. However, a case where the present latch section is used in the second latch circuit is described here because the effect of the capacitor C1 is demonstrated most characteristically when employed in the second latch circuit (see FIGURE 9 ). Here V a is the first inverter's 2 threshold voltage and G is the voltage gain in the vicinity of V a (G < 0). In the sampling period, V in (i.e., a voltage applied at the external input terminal 1 ) is applied to one terminal of the capacitor C1, and a voltage of G × (V in - V a ) + V a is applied to the other terminal thereof. Therefore q S (i.e. the amount of electric charge held by the capacitor C1) is given as follows. q S = C1 × (V in - (G × (V in - V a ) + V a )) q SS (i.e., the amount of electric charge held by the parasitic capacitor Cs connected between the input terminal of the first inverter 2 and ground) is given as follows. q SS = Cs × V in In the hold period, an input voltage of the first inverter 2 is set to a voltage of V H . The first inverter 2 then provides a voltage of G × (V H - V a ) + V a . The as-provided voltage (i.e., G × (V H - V a ) + V a ) of the first inverter 2 becomes a terminal voltage of the capacitor C1. Therefore q SH (the amount of electric charge distributed to the capacitor C1) is given as follows. q SH = C1 × (V H - (G × (V H - V a ) + V a )) Further q SSH (the amount of electric charge held by the parasitic capacitor Cs) is given as follows. q SSH = Cs × V H Both in the sampling period and in the hold period, the conservation of charge holds at a point where the capacitor C1 and the parasitic capacitor Cs are connected together. Here, q f , which is the amount of electric charge injected, at the time when a transition to a hold period is made, into the point by charge redistribution accompanied with movement between power sources of terminal voltages of parasitic capacitors in the switches S1 and S2 , is added to a formula expressing the conservation of charge, for obtaining circuit characteristics as close as possible to actual ones. q S + q SS + q f = q SH + q SSH Formulas (1)-(4) are substituted in Formula (5), to make an arrangement on V H . As a result of such a substitution, the following is obtained. V H = V in + q f /(Cs + (1 - G) × C1) In the absence of C1, C1 = 0 in the formula (6). Therefore: V H = V in + q f /Cs The second terms of the right sides of the formulas (6) and (7), that is, q f /(Cs + (1 - G) × C1) and q f /Cs, each represent an error voltage of V H versus V in . As can be seen from comparing the formula (6) with the formula (7), the presence of C1 reduces the value of error voltage. In other words, the capacitor C1 contributes to lowering an error voltage. In actual latch circuits, there are variations in the parasitic capacitor Cs due to fabrication steps of the semiconductor integrated circuit. Because of this, the error voltage varies greatly in an actual latch circuit. Conversely the capacitor C1 controls the parasitic capacitor Cs variation and can be formed having a greater value than the parasitic capacitor Cs. The presence of the capacitor C1 reduces the effect of the parasitic capacitor Cs. V H can be approximately expressed as follows. V H = V in + q f /((1 - G) × C1) (∴ Cs << (1 - G) × C1) Therefore the error voltage of the second term of the right side becomes independent on the parasitic capacitor Cs, whereupon the error voltage variation is reduced. Thereafter the latch circuit performs a feedback operation according to V H . In order to perform high-accuracy operations, the error voltage must be kept as low as possible. In accordance with the fourth latch circuit, the capacitor C1 is connected between the input and output terminals of the first inverter 2 . As a result of the provision of the capacitor C1, error voltage can be controlled in the hold period, and the variation in the error voltage due to fabrication steps of the semiconductor integrated circuit can be controlled. EMBODIMENT 5 A fifth latch circuit of the present invention is now described by making reference to FIGURE 16. FIGURE 16 shows a latch section of the fifth latch circuit. The latch section of the fifth latch circuit is characterized in that a capacitor C2 is connected between the input and output terminals of the second inverter 3 so as to prevent a circuit, located at the next stage after the latch circuit, from affecting the latch circuit. Elements of FIGURE 16 , which are functionally equivalent to their counterparts of FIGURE 15 , are thus assigned the same reference numerals and they are not described in detail here accordingly. The latch section of the fifth latch circuit may find applications either in the second latch circuit or in the third latch circuit. However, the operation of the present latch section is described when employed in the first latch circuit of FIGURE 3 . The effect of the capacitor C2 characteristically appears when the output voltage of the latch circuit makes a transition in the feedback operation. In a circuit consisting of the second inverter 3 and the capacitor C2, the capacitor C2 acts as a feedback circuit network. When a voltage, which is generated at the time when a circuit connected to the next stage after the latch circuit operates, appears at the external output terminal 4 , such a generated voltage is then applied to the input terminal of the second inverter 3 via the capacitor C2 and is inversion-amplified. Because of such arrangement, disturbance voltage from a stage after the latch circuit can be prevented. This reduces the effect of the operation of a circuit after the latch circuit with respect to the output voltage of the latch circuit and controls voltage transition disturbance occurring when the latch circuit is in a feedback operation. The latch section of the fifth latch circuit may be used in the second or third latch circuit with the same effect. In accordance with the fifth latch circuit, the capacitor C2 is connected between the input and output terminals of the second inverter 3 . Such an arrangement not only reduces the effect of the operation of a circuit after the latch circuit with respect to the output voltage of the latch circuit but also controls voltage transition disturbance occurring when the latch circuit is in a feedback operation and increases the accuracy of latch circuit operation. If any one of the latch circuits of the present invention is applied to A/D converters, this improves the performance of an A/D converter (e.g., the differential non-linearity and the integral non-linearity).

Claims: A latch circuit comprising: an external input terminal (1) for accepting a voltage coming in from outside said latch circuit; a noninverting amplifier(5) with an input terminal and an output terminal for amplifying said voltage in a noninverting amplification manner; a first switch means (S1) which is connected between said external input terminal (1) and said input terminal of said noninverting amplifier (5) and which is capable of having either an on state for establishing a connection between said external input terminal (1) and said input terminal of said noninverting amplifier (5) or an off state for establishing a disconnection between said external input terminal (1) and said input terminal of said noninverting amplifier (5); a second switch means (S2) which is connected between said input terminal and said output terminal of said noninverting amplifier (5) and which is capable of having either an on state for establishing a connection between said input and output terminals of said noninverting amplifier (5) or an off state for establishing a disconnection between said input and output terminals of said noninverting amplifier (5); a control means (11) for controlling the on/off state of said first switch means (S1) and the on/off state of said second switch means (S2) in such a way as to prevent both said first switch means (S1) and said second switch means (S2) from having an on state at the same time when said first switch means (S1) and said second switch means (S2) together make their respective state transitions; said noninverting amplifier (5) comprising an even number of inverting amplifiers (2, 3) connected in series, characterized by a capacitor (C2) with two terminals, one of which being connected to an input terminal of a last-stage inverting amplifier (3) of said even number of inverting amplifiers and the other of which being connected to an output terminal of said last-stage inverting amplifier (3).

Inventors: KUSUMOTO KEIICHI, MATSUZAWA AKIRA, MURATA KENJI, KUSUMOTO, KEIICHI, MATSUZAWA, AKIRA, MURATA, KENJI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1995
Main classification: H03K3
IPC codes: H03K3