Semiconductor booster circuit

Abstract: A semiconductor booster circuit includes: a plurality of stages, each having a first MOS transistor (Q 1 , Q 3 , Q 5 , Q 7 , Q 9 ) and a first capacitor (C 1 , C 3 , C 5 , C 7 , C 9 ) having one terminal connected to a drain terminal of the first MOS transistor, the stages being connected in series by connecting the first MOS transistors of the stages in cascade; and at least one of a first arrangement wherein a source terminal of the first MOS transistor of each of the stages is electrically connected to its substrate, and the substrates of the first MOS transistors in the plurality of stages are electrically insulated from one another, and a second arrangement wherein one terminal of a second capacitor (C 2 , C 4 , C 6 , C 8 , C 10 ) is connected to a gate terminal of the first MOS transistor of each of the stages, and a first clock signal generating unit (12) for inputting a first clock signal to the other terminal of the first capacitor in each stage and a second clock signal generating unit (14, 16) for inputting a second clock signal having a larger amplitude than a power supply voltage (Vdd) to the other terminal of the second capacitor, in each stage are provided.

Description: The present invention relates to a semiconductor booster circuit and more particularly to a semiconductor booster circuit, such as a charge pump circuit, which is used in an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a flash memory. In recent years, along with the promotion of a single 5V power supply or the promotion of a single 3V power supply for semiconductor integrated circuits such as EEPROMs and flash memories, the boosting has been performed in the inside of the integrated circuit. As a result, semiconductor booster circuits such as a Cockcroft Walton circuit and a charge pump circuit have been employed. Fig. 22 shows a configuration of a conventional semiconductor booster circuit. As shown in the figure, N-channel MOS transistors Q 20 to Q 24 are connected in cascade to configure a booster circuit having n stages. The gate terminals of the transistors Q 20 to Q 24 are connected to the respective source terminals N 20 to N 24 to which a clock signal  A or  B is input through respective capacitors C 20 to C 24 . As shown in Fig. 23, the clock signals  A and  B are in opposite phase with each other. Each of the clock signals  A and  B has a period of 1/f and an amplitude of V  . The clock signals  A and  B are obtained from a clock signal CK through two NAND circuits ND 1 and ND 2 and three inverters IV 1 to IV 3 , and the amplitude V  thereof is equal to a power supply voltage Vdd. Incidentally, in Fig. 22, reference symbol G designates a ground terminal. As shown in Fig. 22, in this semiconductor booster circuit, the power supply voltage Vdd is output as an input signal from a source terminal N 27 of a transistor Q 25 , and an output voltage V POUT is output as an output signal from an output terminal N 26 . As described in an article "Analysis and Modeling of On-Chip High-voltage Generator Circuits for Use in EEPROM Circuits (IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 24, No. 5, October 1989) for example, the output voltage V POUT of a sort of the semiconductor booster circuit is expressed by the following expressions: where V in is an input of the booster circuit, V  is an amplitude voltage of the clock signal, f is a clock frequency, C is a coupling capacitance to the clock signal, Cs is a parasitic capacity in each of stages in the booster circuit, n is the number of stages of the booster circuit, V POUT is the output voltage in the final stage of the booster circuit, I OUT is a load current in the output stage, Vto is a threshold voltage when a substrate bias is absent, Vbs is a substrate bias voltage (a potential difference between the source and a substrate or a well),  f is a Fermi potential, Vt is a threshold voltage of the transistor, and K 2 is a substrate bias coefficient. From the expression (1), it is understood that when the load current I OUT is zero and the relation of C/(C + Cs)=1 is established, the output voltage V POUT is increased in proportion to both a value of (V  - Vt) and the number n of stages of the booster circuit. In the conventional booster circuit shown in Fig. 22, since the amplitude voltage V  of the clock signal is equal to the power supply voltage Vdd, the output voltage V POUT is increased in proportion to both the value of (Vdd - Vt) and the number of stages of the booster circuit. However, in the conventional booster circuit, there occurs a phenomenon that as the level of the output voltage V POUT is increased, as shown in the expression (2), the threshold voltage Vt of each of the transistors Q 20 to Q 24 is increased due to the substrate effect. Therefore, in the case where the stages of the booster circuit are discretely configured in order to prevent the substrate effect from occurring, the level of the output voltage V POUT is increased in proportion to the number n of stages of the booster circuit. On the other hand, in the case where the transistors Q 20 to Q 24 are integrated to be formed on the same substrate, since the substrate effect occurs, as the number n of stages of the booster circuit is increased, the value of (Vdd - Vt) is decreased. As a result, as shown in Fig. 24, along with the increasing of the number n of stages of the booster circuit, the output voltage V POUT is decreased to a level lower than a value which is obtained when no substrate effect occurs, and is saturated at the point where the value of (Vdd - Vt) becomes zero. This means that no matter how the number n of stages of the booster circuit is increased, there is a limit in the resultant output voltage V POUT . Fig. 25 shows the relationship between the power supply voltage Vdd and a maximum output voltage when the number n of stages of the booster circuit is made infinitely large. When the number n of stages of the booster circuit, is made infinitely large, in the case where no substrate effect occurs, the resultant output voltage V POUT becomes theoretically infinite. On the other hand, in the case where the substrate effect actually occurs, the resultant output voltage V POUT is limited to a value depending on the power supply voltage Vdd. That is, in the conventional booster circuit, there arises a problem that in the case where the level of the power supply voltage Vdd is low, the desired output voltage V POUT can not be obtained even if the number n of stages of the booster circuit is set to any large value. For example, in the conventional booster circuit shown in Fig. 22, in the case where the power supply voltage Vdd is 2.5V, and the threshold voltage Vto is 0.6V when no substrate effect occurs (the substrate bias voltage is 0V), when the number n of stages of the booster circuit, is set to 20, 20V can be obtained as the output voltage V POUT . However, in the case where the power supply voltage Vdd is 2.0V, even if the number n of stages of the booster circuit is set to 100, only 12V can be obtained as the output voltage V POUT . On the other hand, in JP-A-61-254078, there is disclosed a Cockcroft type booster circuit in which a threshold voltage Vt of a MOS transistor in the subsequent stage having the remarkable substrate effect is made lower than that of a MOS transistor in the preceding stage, thereby improving the reduction of the output voltage due to the substrate effect. However, in this configuration as well, the increasing of the threshold voltage Vt due to the substrate effect can not be suppressed in itself. For example, in the case where the level of the power supply voltage Vdd is approximately halved (Vdd=1 to 1.5V), even if the number n of stages of the booster circuit is set to any value, the desired output voltage V POUT can not be obtained. In addition, since the threshold voltages Vt of the MOS transistors are set to a plurality of different levels, for example, it is necessary to conduct additionally the extra process of photomask and ion implantation. As a result, the manufacturing process becomes complicated. This is a disadvantage. Fig. 26 shows a configuration of still another conventional semiconductor booster circuit. As shown in Fig. 26, eight N-channel MOS transistors M 1 to M 8 are connected in series with one another to configure a booster circuit having four stages. Gate terminals of the transistors M 1 to M 8 are connected to respective drain terminals (represented by nodes N 0 to N 7 ). To the drain terminals N 0 , N 2 , N 4 and N 6 , a clock signal  A as shown in Fig. 21 is input through capacitors C 1 , C 3 , C 5 and C 7 , respectively. To the drain terminals N 1 , N 3 , N 5 and N 7 , a clock signal  B which is in opposite phase with the clock signal  A is input through capacitors C 2 , C 4 , C 6 and C 8 , respectively. In addition, substrate terminals of the transistors M 1 to M 8 are connected to a ground terminal (represented by a node N 21 ). In addition, both a drain terminal and a gate terminal of each of the N-channel MOS transistors M 20 and M 21 are connected to an associated input terminal (represented by a node N 20 ), and a substrate terminal thereof is connected to the ground terminal N 21 . That is, the node N 0 is respectively connected to the source terminal of the transistor M 20 , both the drain terminal and the gate terminal of the transistor M 1 , and one terminal of the capacitor C 1 . The node N 1 is respectively connected to the source terminal of the transistor M 21 , both the drain terminal and the gate terminal of the transistor M 2 , the source terminal of the transistor M 1 and one terminal of the capacitor C 2 . The node N 2 is respectively connected to both the drain terminal and the gate terminal of the transistor M 3 , the source terminal of the transistor M 2 and one terminal of the capacitor C 3 . The node N 3 is respectively connected to both the drain terminal and the gate terminal of the transistor M 4 , the source terminal of the transistor M 3 and one terminal of the capacitor C 4 . The node N 4 is respectively connected to both the drain terminal and the gate terminal of the transistor M 5 , the source terminal of the transistor M 4 and one terminal of the capacitor C 5 . The node N 5 is respectively connected to both the drain terminal and the gate terminal of the transistor M 6 , the source terminal of the transistor M 5 and one terminal of the capacitor C 6 . The node N 6 is respectively connected to both the drain terminal and the gate terminal of the transistor M 7 , the source terminal of the transistor M 6 and one terminal of the capacitor C 7 . In addition, the node N 7 is respectively connected to both the drain terminal and the gate terminal of the capacitor M 8 , the source terminal of the transistor M 7 and one terminal of the capacitor C 8 . Further, an output terminal (represented by a node N 8 ) of this semiconductor booster circuit is connected to the source terminal of the MOS transistor M 8 . The above-mentioned expressions (1) and (2) are also applied to this booster circuit. Then, if the load current I OUT is zero, the capacitance ratio C/(C + Cs) is 1, and the amplitude voltage V  of the clock signal is equal to the power supply voltage Vdd in the expression (1), the voltage which is boosted per stage is expressed by (Vdd - Vt). Therefore, it is understood that the output voltage V POUT is influenced by the margin between the threshold voltage Vt of each of the MOS transistors and the power supply voltage Vdd. In particular, it is understood that when the relation of Vt≥Vdd is established, the boosting operation is not performed in the corresponding stage. That is, if the threshold voltage Vt is increased, the voltage which is boosted per stage becomes either small or zero. Therefore, even if the number n of stages of the booster circuit is increased, the output voltage V POUT is hardly or never increased. For example, since the source potential of the MOS transistor shown in Fig. 26 is equal to the output voltage V POUT , and the substrate potential is 0V, the substrate bias voltage Vbs is equal to the output voltage V POUT . Now, since the booster circuit shown in Fig. 26 is provided for generating the positive high voltage, the output voltage V POUT takes one of positive values. Therefore, the threshold voltage of the MOS transistor M 8 becomes very high, and hence the boosting efficiency is reduced. This problem becomes especially remarkable during the low power source voltage operation in which the margin between the threshold voltage Vt and the power supply voltage Vdd is small. In this booster circuit, as shown in Fig. 26, all the substrate terminals of the MOS transistors M 1 to M 8 are grounded. That is, the MOS transistors M 1 to M 8 are, as shown in Fig. 27, respectively constituted by sources/drains 454 to 462, which are formed in a P type semiconductor substrate 451, and gates 464 to 471, and the substrate terminal is connected to a ground terminal N 21 through a P + type impurity diffusion layer 452 in the semiconductor substrate 451. Incidentally, reference numeral 453 designates a drain of a MOS transistor 20 and reference numeral 463 designates a gate of the MOS transistor 20. Therefore, there arises a problem that the potential of the source terminal of the MOS transistor, which is located in the more backward stage, becomes higher, and the difference in the potential between the source terminal and the substrate portion is increased so that due to the so-called substrate bias effect, the threshold voltage Vt is increased, and hence the output voltage V POUT is limited due to the increasing of the threshold voltage Vt. EP-A-0 349 495 discloses a CMOS voltage multiplier particularly useful for EPROM and EEPROM and a semiconductor booster having the phase opposition signals as the square-wave switching signals. It is therefore an object of the present invention to provide a semiconductor booster circuit in which a desired output voltage is capable of being obtained, even in the case where a level of a power supply voltage is low, without the necessity of the complicated manufacturing process. The object above can be achieved by the features defined in the claims. The invention is described in more detail in connection with the drawings, in which; Fig. 1 is a circuit diagram showing a configuration of a semiconductor booster circuit according to a first embodiment of the present invention; Fig. 2 is a circuit diagram showing a configuration of the two continuous stages of the semiconductor booster circuit according to the first embodiment shown in Fig. 1; Fig. 3 is a timing chart showing the timing of clock pulses used in the semiconductor booster circuit shown in Fig. 1; Figs. 4A to 4D are respectively graphical representations showing waveforms of voltages at respective nodes of the semiconductor booster circuit shown in Fig. 1; Figs. 5A to 5F are respectively circuit diagrams useful in explaining the operation of the semiconductor booster circuit shown in Fig. 1; Fig. 6 is a cross sectional view showing a device structure of the semiconductor booster circuit shown in Fig. 1; Fig. 7 is a circuit diagram showing a configuration of a semiconductor booster circuit; Fig. 8 is a time chart showing the timing of clock pulses used in the semiconductor booster circuit shown in Fig. 6; Fig. 9 is a circuit diagram showing a configuration of a semiconductor booster circuit; Fig. 10 is a cross sectional view showing a device structure of the semiconductor booster circuit shown in Fig. 9; Fig. 11 is a circuit diagram showing a configuration of a semiconductor booster circuit according to a second embodiment of the present invention; Fig. 12 is a time chart showing the timing of clock pulses used in the semiconductor booster circuit shown in Fig. 11; Fig. 13 is a graphical representation showing the relationship between the number of stages and an output voltage of the semiconductor booster circuit; Fig. 14 is a graphical representation showing the relationship between a power supply voltage and a maximum output voltage when the number of stages of the semiconductor booster circuit is infinite; Fig. 15 is a circuit diagram showing a configuration of a semiconductor booster circuit according to a third embodiment of the present invention; Fig. 16 is a time chart showing the timing of clock pulses used in the semiconductor booster circuit shown in Fig. 15; Fig. 17 is a circuit diagram showing a configuration of a semiconductor booster circuit according to a fourth embodiment of the present invention; Fig. 18 is a cross sectional view showing a device structure of the semiconductor booster circuit shown in Fig. 17; Fig. 19 is a circuit diagram showing a configuration of a semiconductor booster circuit according to a fifth embodiment of the present invention; Fig. 20 is a time chart showing the timing of clock pulses used in the semiconductor booster circuit shown in Fig. 17; Fig. 21 is a time chart showing the timing of clock pulses used in the semiconductor booster circuit shown in Fig. 19; Fig. 22 is a circuit diagram showing a configuration of a conventional semiconductor booster circuit; Fig. 23 is a time chart showing the timing of clock pulses used in the conventional semiconductor booster circuit; Fig. 24 is a graphical representation showing the relationship between the number of stages and an output voltage of the conventional semiconductor booster circuit; Fig. 25 is a graphical representation showing the relationship between a power supply voltage and a maximum output voltage when the number of stages of the conventional semiconductor booster circuit is infinite; Fig. 26 is a circuit diagram showing a configuration of another conventional semiconductor booster circuit; and Fig. 27 is a cross sectional view showing a device structure of another conventional semiconductor booster circuit. A first embodiment of the present invention will hereinafter be described in detail with reference to Figs. 1 to 10. Fig. 1 shows a configuration of a semiconductor booster circuit according to the first embodiment of the present invention. As shown in Fig. 1, n elements of P-channel MOS transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 are connected in cascade to configure a booster circuit having n stages. Substrate portions of the transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 are electrically insulated from one another and also are connected to source terminals of the transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 , respectively. In addition, to drain terminals (represented by nodes N 1 , N 3 , N 5 , N 7 , ..., N 9 ) a clock signal  2A or  2B which is shown in Fig. 3 is inputted through respective capacitors C 2 , C 4 , C 6 , C 8 , ..., C 10 . In addition, to gate terminals (represented by nodes N 2 , N 4 , N 6 , N 8 , ..., N 10 ) of the transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 , a clock signal  2A which is shown in Fig. 3 is inputted through respective capacitors C 2 , C 4 , C 6 , C 8 , ..., C 10 . Further, P-channel MOS transistors Q 2 , Q 4 , Q 6 , Q 8 , ..., Q 10 are respectively connected between the gate terminals N 2 , N 4 , N 6 , N 8 , ..., N 10 and source terminals (represented by nodes N 3 , N 5 , N 7 , N 11 , ..., N 12 ) of the transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 , and gate terminals of the transistors Q 2 , Q 4 , Q 6 , Q 8 , ..., Q 10 are respectively connected to the drain terminals N 1 , N 3 , N 5 , N 7 , ..., N 9 of the transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 . In the booster circuit of the present embodiment, a power supply voltage Vdd is inputted as an input signal from a common source terminal (represented by a node N 0 ) of N-channel MOS transistors Q 12 and Q 13 to the source terminals N 1 and N 3 of the transistors Q 1 and Q 3 , and an output voltage V POUT is outputted as an output signal from an output terminal (represented by a node N 13 ) through an N-channel MOS transistor Q 11 . As shown in the figure, the gate terminals of the transistors Q 12 and Q 13 are respectively connected to the source terminal N 0 . In addition, to a source terminal (represented by a node N 12 ) of the transistor Q 11 , the clock signal  1A which is shown in Fig. 3 is inputted through a capacitor C 11 . Further, a gate terminal of the transistor Q 11 is connected to a drain terminal (represented by the node N 13 ). As shown in Fig. 3, the clock signals  1A and  1B are in opposite phase with each other and have the same amplitude as the power supply voltage Vdd, and the clock signals  2A and  2B are pulse-like signals which have the amplitude equal to or larger than the power supply-voltage Vdd and are in an off state at periods when the clock signals  1A and  1B are in an on state, respectively. As for a clock signal generating unit 120 which operates to generate the clock signals  1A and  1B , the same unit as the conventional unit may be employed. As for clock signal generating units 140 and 160 which operate to generate the clock signals  2A and  2B , respectively, any units may be employed which operate to receive clock pulse signals CLK 2 and CLK 3 of the same timings as those of the generating timings of the clock signals  2A and  2B , respectively, and control the amplitudes thereof. Next, the description will hereinbelow be given with respect to the operation of the semiconductor booster circuit according to the first embodiment with reference to Figs. 2 to 5. Fig. 2 is a circuit diagram showing a configuration of two consecutive stages (a first stage and a second stage) of the semiconductor booster circuit shown in Fig. 1. In addition, Figs. 4A to 4D show waveforms of the voltages at nodes N A to N D of the circuit of Fig. 2 for a time period ranging from (I) to (VI) shown in Fig, 3. Further, Figs. 5A to 5F are respectively circuit diagrams useful in explaining the conduction state of transistors M 1 to M 4 of Fig. 2 for a time period ranging from (I) to (VI). Firstly, for a period of time of (I), as shown in Fig. 3, the level of the clock signal  1A is raised from the ground potential up to the power supply voltage Vdd, and also the potential at the drain terminal N A of the transistor M 1 shown in Fig. 2 is, as shown in Fig. 4A, raised by a voltage corresponding to the power supply voltage Vdd. At the same time, the level of the clock signal  1B is dropped from the power supply voltage Vdd down to the ground potential 0V, and also the potential at the source terminal N B of the transistor M 1 is, as shown in Fig. 4B, dropped by a voltage corresponding to the power supply voltage Vdd. At this time, the electric charges which have been transferred from the preceding stage are accumulated in the capacitor C A2 which is connected to the source terminal N B of the transistor M 1 , and hence the potential at the source terminal N B of the transistor M 1 is raised by a voltage corresponding to the electric charges accumulated in that capacitor C A2 . In addition, the potential at the gate terminal N A of the transistor M 2 becomes higher than that at the source terminal N B , and hence the transistor M 2 is, as shown in Fig. 5A, switched from the on state to the off state. At this time, as will be described later, since the P N junction which is formed between the drain terminal N A and the source terminal N B of the transistor M 1 is biased in the forward direction, the substrate portion of the transistor M 1 which is connected to the source terminal N B is maintained at the potential which is obtained by subtracting the forward bias voltage across the P N junction from the potential at the drain terminal N A . In addition, as shown in Fig. 4C, the potential at the gate terminal N C of the transistor M 1 is dropped down to the same potential as that at the drain terminal N A , but the transistor M 1 remains, as shown in Fig. 5A, in the off state. In addition, as the level of the clock signal  1A is raised from the ground potential 0V up to the power supply voltage Vdd, the potential at the source terminal N D of the transistor M 3 is, as shown in Fig. 4D, raised by a voltage corresponding to the power supply voltage Vdd. At this time, the electric charges which have been transferred from the preceding stage are accumulated in the capacitor C A3 , and hence the potential at the source terminal N D of the transistor M 3 is raised by a voltage corresponding to the electric charges accumulated in the capacitor C A3 . In addition, at the time when the level of the clock signal  1B has been dropped from the power supply voltage Vdd down to the ground potential 0V, the potential at the gate terminal N B of the transistor M 4 is dropped and hence the transistor M 4 is switched from the off state to the on state. Therefore, the potential at the gate terminal N E of the transistor M 3 becomes the same potential as that at the source terminal N D of the transistor M 3 . At this time, as shown in Fig. 5A, the transistor M 3 remains in the off state. Next, for a period of time (II), the level of the clock signal  2A is dropped from the power supply voltage Vdd down to the ground potential 0V, and hence the potential at the gate terminal N C of the transistor M 1 is, as shown in Fig. 4C, dropped by a voltage corresponding to the power supply voltage Vdd. As a result, as shown in Fig. 5B, the transistor M 1 is turned on and hence a current is caused to flow from the drain terminal N A to the source terminal N B of the transistor M 1 until the potential at the drain terminal N A becomes equal to that at the source terminal N B . That is, the electric charges are transferred from the capacitor C A1 to the capacitor C A2 , and hence the potential at the drain terminal N A of the transistor M 1 is, as shown in Fig. 4A, dropped, and also the potential at the source terminal N B of the transistor M 1 is, as shown in Fig. 4B, raised. In addition, with respect to the source terminal N D of the transistor M 3 as well, in the same manner as that in the case of the drain terminal N A of the transistor M 1 , as shown in Fig. 4D, the potential at the source terminal N D is dropped. At this time, the clock signal  2A which is used to turn the transistor M 1 on is supplied from the outside through the capacitor C B1 , and no voltage drop occurs between the drain terminal N A and the source terminal N B when turning the transistor M 1 on. Therefore, as compared with the prior art, the boosting capability is further improved. That is, in the above-mentioned expression (1), this state corresponds to the situation in which in the term within the brackets, Vt is equal to 0V. Thus, the boosting operation can be performed with an exceptionally good efficiency. Next, for a period of time (III), the level of the clock signal  2A is raised from the ground potential 0V up to the power supply voltage Vdd, and hence the potential at the gate terminal N C of the transistor M 1 is, as shown in Fig. 4C, raised by a voltage corresponding to the power supply voltage Vdd. As a result, as shown in Fig. 5C, the transistor M 1 is turned off. In addition, as shown in Figs. 4A, 4B and 4D, the potentials at the drain terminal N A and the source transistor N B of the transistor M 1 , and the potential at the source terminal N D of the transistor M 3 do not change. Next, for a period of time (IV), the level of the clock signal  1A is dropped from the power supply voltage Vdd down to the ground potential 0V, and hence the potential at the drain terminal N A of the transistor M 1 is urged to drop by a voltage corresponding to the power supply voltage Vdd. However, in the first stage, since the transistor Q 12 shown in Fig. 1 goes to the on state, as shown in Fig. 4A, the potential at the drain terminal N A of the transistor M 1 goes to the potential of (Vdd - Vt). In addition, the level of the clock signal  1B is raised from the ground potential 0V up to the power supply voltage Vdd, and hence the potential at the source terminal N B of the transistor M 1 is, as shown in Fig. 4B, raised by a voltage corresponding to the power supply voltage Vdd. At this time, since the electric charges which have been transferred from the preceding stage are accumulated in the capacitor C A2 , the potential at the source terminal N B of the transistor M 1 is raised by a voltage corresponding to the electric charges accumulated in the capacitor C A2 . In addition, the potential at the gate terminal N A of the transistor M 2 becomes lower than that at the source terminal N B thereof, and hence the transistor M 2 is, as shown in Fig. 5D, switched from the off state to the on state. As a result, the potential at the gate terminal N C of the transistor M 1 is, as shown in Fig. 4C, raised up to the same potential as that at the source terminal N B of the transistor M 1 . In addition, as the level of the clock signal  1A is dropped from the power supply voltage down to the ground potential 0V, the potential at the source terminal N D of the transistor M 3 is, as shown in Fig. 4D, dropped by a voltage corresponding to the power supply voltage Vdd. At this time, the electric charges which have been transferred from the preceding stage are accumulated in the capacitor C A3 , and hence the potential at the source terminal N D is raised by a voltage corresponding to the electric charges accumulated in the capacitor C A3 . As a result, the potential at the drain terminal N B of the transistor M 4 becomes higher than that at the source terminal N D thereof, and hence the transistor M 4 is, as shown in Fig. 5D, switched from the on state to the off state. In addition, in the same manner as that in the case of the above-mentioned transistor M 1 , since the PN junction which is formed between the drain terminal N B and the source terminal N D of the transistor M 3 is biased in the forward direction, the substrate portion of the transistor M 3 connected to the source terminal N D is maintained at a voltage which is obtained by subtracting the forward bias voltage across the PN junction from the potential at the drain terminal N B . Next, for a period of time of (V), the level of the clock signal  2B is dropped from the power supply voltage Vdd down to the ground potential 0V, and hence the potential at the gate terminal N E of the transistor M 3 is dropped by a voltage corresponding to the power supply voltage Vdd. As a result, as shown in Fig. 5E, the transistor M 3 is turned on, and also a current is caused to flow from the drain terminal N B to the source terminal N D of the transistor M 3 until the potential at the drain terminal N B becomes equal to that at the source terminal N D . That is, the electric charges are transferred from the capacitor C A2 to the capacitor C A3 , and hence as shown in Fig. 4B, the potential at the drain terminal N B of the transistor M 3 is dropped and also as shown in Fig. 4D, the potential at the source terminal N D of the transistor M 3 is raised. In addition, since the transistor M 2 remains in the on state, and the potential at the gate terminal N C of the transistor M 1 is equal to that at the drain terminal N B of the transistor M 3 , as shown in Fig. 4C, the potential at the gate terminal NC of the transistor M 1 is dropped. At this time, the clock signal  2B which is used to turn the transistor M 3 on is supplied from the outside through the capacitor C B2 , and no voltage drop occurs between the drain terminal N B and the source terminal N D when turning the transistor M 3 on. Therefore, as compared with the prior art, the boosting capability is further improved. Next, for a period of time of (VI), the level of the clock signal  2B is raised from the ground potential 0V up to the power supply voltage Vdd, and hence the potential at the gate terminal N E of the transistor M 3 is raised by a voltage corresponding to the power supply voltage Vdd. As a result, as shown in Fig. 5F, the transistor M 3 goes to the off state. In addition, as shown in Figs. 4A to 4D, the potentials at the nodes N A to N D do not change. In the operation as described above, since the source terminals of the transistors M 1 to M 3 are boosted such that the source terminal of the transistor located in the more backward stage becomes higher, the substrate effect acts inherently to raise, as shown in the above-mentioned expression (2), the threshold voltage Vt of each of the transistors M 1 and M 3 . However, in the present embodiment, as shown in Fig. 2, since the substrate portions of the transistors M 1 and M 3 are connected to the source terminal, no substrate effect occurs, and hence the transfer of the electric charges from the preceding stage to the subsequent stage is effectively performed. Fig. 6 is a schematic cross sectional view showing a device structure of the transistors M 1 and M 3 shown in Fig. 2. As shown in Fig. 6, two N type well regions 11 are respectively formed in a P type semiconductor substrate 10 so as to be insulated from each other, and in each of the N type well regions 11, there is formed a MOS transistor which includes a polycrystalline silicon layer 16, as a gate electrode, which is formed on the substrate portion of the well 11 with a gate oxide film 15 disposed therebetween, and P + type impurity diffusion layers 12 as source/drain regions. The P + type impurity diffusion layer 12 of the source side in each of the transistors is electrically connected to the N type well region 11, in which the transistor is formed, through a N + type impurity diffusion layer 14, and the source of the transistor in the preceding stage is connected to the drain of the transistor in the subsequent stage. By adopting this structure, the potential at the N type well region 11 as the substrate portion of each of the transistors is fixed to the source potential of each of the transistors, and hence the substrate effect can be effectively prevented from occurring. In addition, for a period of time of (I) of Fig. 5A or (IV) of Fig. 5D, the PN junction which is formed between the P + type impurity diffusion layer 12 of the drain side and the N type well region 11 of each of the transistors is biased in the forward direction. Then, through that PN junction, the electric charges can be transferred from the node N A to the node N B and from the node N B to the node N D through the N type well region 11 of the substrate and the N + type impurity diffusion layer 14. In this case, the voltage difference corresponding to the forward bias voltage V F (normally, about 0.7V) across the PN junction which is independent of the threshold voltage Vt of the MOS transistor is utilized for the boosting operation, and hence V F is employed instead of Vt in the above-mentioned expressions (1) and (2). Since the forward bias voltage V F across the PN junction is not influenced by the substrate effect, it is possible to realize the booster circuit which, even when the number of stages of the booster circuit is increased, is free from the reduction of the boosting capability due to the substrate effect. As described above, in the semiconductor booster circuit according to the first embodiment of the present invention, the substrate portions of the MOS transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 shown in Fig. 1 are electrically insulated from one another, and also the substrate portions are respectively connected to the source terminals N 3 , N 5 , N 7 , N 11 , ..., N 12 , whereby the increasing of the threshold voltage Vt due to the substrate effect is effectively prevented. Therefore, it is possible to obtain the output voltage V POUT which is increased in proportion to the number n of stages of the booster circuit and also it is possible to provide the semiconductor booster circuit which has the higher boosting capability than that of the prior art. In addition, with respect to the structure of the present embodiment, as shown in Fig. 6, the N type well regions 11 in which the respective transistors are formed are formed to be isolated from each other and also the N + type impurity region 14 of each of the N type well regions 11 is electrically connected to the P + type impurity region 12 of the source side of each of the transistors. Thus, the process for making the threshold voltages of the respective transistors different from one another, as in the prior art, is not required at all. Therefore, the number of manufacturing processes is not increased so much. In addition, the substrate portion of each transistor is electrically connected to the source terminal, whereby the PN junction which is formed in the boundary between the drain and the substrate portion is connected in parallel between the source and drain of the transistor. Then, when transferring the electric charges from the preceding stage to the subsequent stage in the booster circuit, the PN junction is rendered to the on state, whereby the potential at the substrate portion of each transistor can be fixed to a voltage difference corresponding to the forward bias voltage V F (normally, about 0.7V) across the PN junction. Thus, it is possible to suppress the influence of the substrate effect. In addition, as shown in Fig. 5, to the gate terminals N C and N E of the transistors M 1 and M 3 , the pair of clock signals  2A and  2B which are independent from the pair of clock signals  1A and  1B , which are respectively inputted to the drain terminals N A and N B , are respectively inputted, whereby each of the transistors M 1 and M 3 can be turned on in such a way that no potential difference occurs between the source and the drain thereof. Therefore, when transferring the electric charges from the preceding stage to the subsequent stage in the booster circuit, it is possible to realize the transfer of the electric charges such that the voltage drop does not occur which corresponds to the potential difference between the source and the drain. Therefore, since in the above-mentioned expression (1), the threshold voltage Vt can be regarded as zero, the boosting operation can be more efficiently performed as compared with the conventional booster circuit, and even in the case where the number n of stages of the booster circuit and the power supply voltage Vdd are the same as those of the conventional booster circuit, the larger output voltage V POUT can be obtained. In addition, in the case where the output voltage V POUT is the same as that of the conventional booster circuit, the booster circuit of the present embodiment can obtain the larger load current I OUT . For example, in the case where the power supply voltage Vdd is 20V, and the number n of stages of the booster circuit is 20, assuming that the capacitance ratio C/(C + Cs) is 0.9, the absolute value of the threshold voltage |Vt| is 0.6, and the load current I OUT of the output stage is zero, only 20V can be obtained as the output voltage V POUT in the conventional booster circuit, but in the booster circuit according to the present embodiment, about 47V can be obtained. In addition, in the semiconductor booster circuit according to the present embodiment, even in the low power supply voltage Vdd which can not be boosted by the conventional booster circuit, the desired output can be obtained. In other words, in the conventional booster circuit, as shown in Fig. 25, even if the number n of stages of the booster circuit is set to any value, the maximum output voltage is limited to a predetermined value depending on the power supply voltage Vdd. However, in the semiconductor booster circuit according to the present embodiment, such a limit is not present substantially. For example, in the case where the power supply voltage Vdd is 2.0V, assuming that the capacitance ratio C/(C + Cs) is 0.9, the absolute value of the threshold voltage |Vt| is 0.6V, and the load current I OUT in the output stage is zero, even in the booster circuit in which the number n of stages of the booster circuit is 50, only 12V can be obtained as the output voltage V POUT in the conventional booster circuit, but in the booster circuit according to the present embodiment, when the number n of stages of the booster circuit is 20, about 37V can be obtained as the output voltage V POUT , and also when the number n of stages of the booster circuit is 50, about 91V can be obtained. Incidentally, in the semiconductor booster circuit according to the present embodiment, in the case where the absolute value of the threshold voltage |Vt| is set to 0.6V, the lower limit of the boostable power supply voltage Vdd is about 0.7V. In the above explanation, the substrates of the MOS transistors in n stages are electrically insulated from each other. Alternatively, the n stages are divided into at least two groups, for example two groups i.e. a first group of the first to third stages and a second group of the fourth to sixth stages and the substrates of the MOS transistors included in each group are electrically insulated form the substrates of the MOS transistors included in the other group. Next, the description will hereinbelow be given with respect to a semiconductor booster circuit with reference to Figs. 7 and 8. Fig. 7 is a circuit diagram showing a configuration of the semiconductor booster circuit. In Fig. 7, n elements of P-channel MOS transistors Q 30 to Q 34 are connected in cascade to configure a booster circuit having n stages. Substrate portions of the respective transistors Q 30 to Q 34 are electrically insulated from one another, and also gate terminals and the substrate portions are connected to respective source terminals N 31 to N 35 . Then, a clock signal  A or  B which is shown in Fig. 8 is inputted to the source terminals N 30 to N 35 through capacitors C 30 to C 35 , respectively. In the booster circuit of the present structure, as an inputted signal, the power supply voltage Vdd is inputted from a source terminal N 37 of a P-channel MOS transistor Q 36 to a drain terminal N 30 of the transistor Q 30 , and also as an output signal, an output voltage V POUT is outputted from an output terminal N 36 through a P-channel MOS transistor Q 35 . The clock signals  A and  B are, as shown in Fig. 8, in opposite phase with each other and have the amplitude of a voltage V  . In addition, the device structure of the transistors Q 30 to Q 34 of the present structure may be the same as that shown in Fig. 6. That is, the N type well regions 11 are formed in the P type semiconductor substrate, and in each of the N type well regions 11, the polycrystalline silicon layer 16 which is formed on the substrate portion of the well region 11 with an intermediate gate oxide film 15 therebetween is provided as the gate electrode. and also the P + type impurity diffusion layer 12 is provided as the source/drain region. In such a manner, the MOS transistor is formed. The P + type impurity diffusion layer 12 of the source side of each of the transistors is connected to the N type well region 11 through the N + type impurity diffusion layer 14, and also the source of the transistor in the preceding stage is connected to the drain of the transistor in the subsequent stage. As a result, the potential at the N type well region as the substrate portion of each of the transistors is fixed to the source potential of each of the transistors, and hence the substrate effect is effectively prevented from occurring. In addition, the PN junction, which is formed between the P + type impurity diffusion layer 12 of the drain side and the N type well region of each of the transistors, is biased in the forward direction, whereby through that PN junction, the electric charges are transferred from the node N A to the node N B and from the node N B to the node N D through the N type well region 11 of the substrate portion and the N + type impurity diffusion layer 14. In the case of the present structure, each transistor is not rendered substantially perfectly conductive unlike the state as shown in Figs. 5B and 5E of the above-mentioned first embodiment, and hence the transfer of the electric charges from the preceding stage to the subsequent stage is performed through the above-mentioned PN junction. Therefore, in the case of the present structure, the potential difference corresponding to the forward bias voltage V F (normally, about 0.7V) across the PN junction which is independent of the threshold voltage Vt of the MOS transistor is utilized for the boosting operation, and also V F is employed instead of Vt in the above-mentioned expressions (1) and (2). Since that forward bias voltage V F across the PN junction is not influenced by the substrate effect at all, it is possible to realize the booster circuit in which even when the number of stages of the booster circuit is increased, the reduction of the boosting capability due to the substrate effect does not occur at all. More specifically, in the present structure as shown in Fig. 7, the substrate portions of the transistors Q 30 to Q 34 are electrically connected to the source terminals N 31 to N 35 , respectively, whereby the PN junction which is formed in the boundary between the drain and the substrate portion is connected in parallel between the source and the drain of each of the transistors Q 30 to Q 34 . Then, when transferring the electric charges from the preceding stage to the subsequent stage in the booster circuit, the PN junction is rendered conductive, whereby the potential at the substrate portion of each of the transistors Q 30 to Q 34 can be fixed to the potential difference corresponding to the forward bias voltage V F (normally, about 0.7V) across the PN junction. Therefore, it is possible to suppress the influence of the substrate effect. Next, the description will hereinbelow be given with respect to a semiconductor booster circuit with reference to Figs. 9 and 10. Fig. 9 is a circuit diagram showing a configuration of the semiconductor booster circuit. In Fig. 9, n N-channel MOS transistors Q 40 to Q 44 are connected in cascade to configure the booster circuit having n stages. Substrate portions of the respective transistors Q 40 to Q 44 are electrically insulated from one another, and also the substrate portions and gate terminals are connected to respective source terminals N 40 to N 44 . Then, the clock signal  A or  B which is the same as that shown in Fig. 8 is inputted to the terminals N 40 to N 44 through capacitors C 40 to C 44 , respectively. In the booster circuit according to the present structure, the power supply voltage Vdd is inputted as an input signal from a source terminal N 47 of an N-channel MOS transistor Q 45 to the terminal N 40 , and also the output voltage V POUT is outputted as an output signal from an output terminal N 46 through the N-channel MOS transistor Q 44 . Fig. 10 shows a device structure of the transistors Q 40 to Q 44 according to the present structure. In Fig. 10, P type well regions 51 are formed in an N type semiconductor substrate 50, and in each of the P type well regions 51, a polycrystalline silicon layer 56 which is formed on the substrate portion of the well region 11 with a gate oxide film 55 disposed therebetween is provided as a gate electrode, and also an N + type impurity diffusion layer 52 is provided as a source/drain region. In such a manner, the MOS transistor is formed. The N + type impurity diffusion layer 52 of the source side of each of the transistors is electrically connected to the P type well region 51, in which the transistor is formed, through the P + type impurity diffusion layer 54, and the source of the transistor in the preceding stage is connected to the drain of the transistor in the subsequent stage. As a result, the potential at the P type well region of the substrate portion of each of the transistors is fixed to the source potential of each of the transistors, and hence the substrate effect can be effectively prevented from occurring. In addition, the PN junction is formed between the N + type impurity diffusion layer 52 of the drain side and the P type well region 51 of each of the transistors. When in the operation, the PN junction is biased in the forward direction, the potential at the substrate portion of each of the transistors is fixed to the forward bias voltage across the PN junction. In such a manner, the substrate effect can be effectively prevented from occurring. As described above, in the semiconductor booster circuit according to this structure, the substrate portions of the MOS transistors are electrically insulated from one another, and also the substrate portions are electrically connected to the source terminals of the MOS transistors, respectively, whereby it is possible to prevent the increasing of the threshold voltage Vt due to the substrate effect. Therefore, it is possible to obtain the output voltage V POUT proportional to the number n of stages of the semiconductor booster circuit. In addition, with respect to the device structure, as shown in Fig. 10, the P type well regions 51 in which the transistors Q 40 to Q 44 are respectively formed are formed independently of each other and also the P + type impurity diffusion region of each of the P type well regions is electrically connected to the N + type impurity diffusion region 52 of the source side of each of the transistors Q 40 to Q 44 . Therefore, in particular, the number of manufacturing processes is not increased at all. In addition, the substrate portions of the transistors Q 40 to Q 44 are electrically connected to the source terminals N 40 to N 44 , respectively, whereby the PN junction which is formed in the boundary between the drain and the substrate portion is connected in parallel between the source and the drain of each of the transistors Q 40 to Q 44 . Then, when transferring the electric charges from the preceding stage to the subsequent stage in the booster circuit, the PN junction is switched to the on state, whereby the potential at the substrate portion of each of the transistors Q 40 to Q 44 can be fixed to the potential difference corresponding to the forward bias voltage V F (normally, about 0.7V) across the PN junction. Thus, it is possible to suppress the influence of the substrate effect. In the semiconductor booster circuits according to the both structures, the forward junction bias voltage V F can be employed instead of the threshold voltage Vt in the above-mentioned expressions (1) and (2). In particular, in the case where the threshold voltage Vt is larger than the forward junction bias voltage V F , since the voltage drop when transferring the electric charges from the preceding stage to the subsequent stage in the booster circuit is reduced, it is possible to improve the boosting capability of the booster circuit. That is, the voltage drop when transferring the electric charges to the subsequent stage depends on the smaller one of the threshold voltage Vt and the forward junction bias voltage V F . For example, in the case where the power supply voltage Vdd is 2.5V and the number n of stages of the booster circuit is 20, assuming that the capacitance ratio C/(C + Cs) is 0.9, the absolute value of the threshold voltage |Vt| is 0.6V, the load current I OUT in the output stage is 0A, and the forward junction bias voltage V F across the PN junction is 0.7V, only 20V can be obtained as the output voltage V POUT in the conventional booster circuit. But in the booster circuit according to the latter structure, about 33V can be obtained as the output voltage V POUT . In addition, for example, in the case where the power supply voltage Vdd is 2.0V, assuming that the capacitance ratio C/(C + Cs) is 0.9, the absolute value of the threshold voltage |Vt| is 0.6V, the load current I OUT in the output stage is 0A, and the forward junction bias voltage V F across the PN junction is 0.7V, only 12V can be obtained as the output voltage V POUT in the conventional booster circuit, even when the number n of stages of the booster circuit is 50. But in the booster circuit according to the latter structure of the present invention, when the number n of stages of the booster circuit is 20, about 23V can be obtained as the output voltage V POUT , and also when the number n of stages of the booster circuit is 50, about 56V can be obtained. In the semiconductor booster circuits according to the both structures, assuming that the forward junction bias voltage V F across the PN junction is 0.7V, and the capacitance ratio C/(C + Cs) is 0.9, the lower limit of the boostable power supply voltage Vdd is about 0.8V. In the above, the description has been given with respect to the first embodiment of the present invention and the both structures since in the booster circuit according to the first embodiment, the voltage drop when transferring the electric charges to the subsequent stage can be made substantially zero, and hence, the booster circuit according to the first embodiment has the larger boosting capability as compared with the booster circuits according to the both structures. In particular, in the power supply voltage Vdd of about 0.8V to 2.0V, the difference in the boosting capability between the booster circuit according to the first embodiment and the booster circuit according to the both structures becomes remarkably large. In particular, in the power supply voltage Vdd of about 0.8V to 2.0V, when the desired output voltage is larger, the number n of stages needs to be increased in the booster circuits according to the both structures due to the voltage drop when transferring the electric charges to the subsequent stage. However, in the booster circuit according to the first embodiment, this is not required. For example, in the case where the power supply voltage Vdd is 2.0V, the number n of stages of the booster circuit required for obtaining 23V as the output voltage V POUT is 20 in the booster circuits according to the both structures, but only 12 in the booster circuit according to the first embodiment. On the other hand, the booster circuit according to one of the both structures is advantageous as compared with the booster circuit according to the first embodiment in that the circuit configuration is simpler and also only two kinds of clock signals are enough. In any one of the above-mentioned embodiments, since the substrate portions of the MOS transistors are electrically insulated from one another, and also the substrate portions are electrically connected to the source terminals of the MOS transistors, respectively, the substrate effect can be effectively prevented from occurring, and also the high boosting capability can be obtained. In addition, no complicated manufacturing process is especially required. Further, in the case where the same boosting capability is obtained, the number of stages of the booster circuit can be further reduced as compared with the prior art. Next, the description will hereinbelow be given with respect to a second embodiment of the present invention with reference to Figs. 11 to 14. Fig. 11 shows a configuration of a semi-conductor booster circuit according to the second embodiment of the present invention. As shown in Fig. 11, n elements of N-channel MOS transistors Q 51 , Q 53 , Q 55 , Q 57 , ..., Q 59 are connected in cascade to configure a booster circuit having n stages. To source terminals (represented by nodes N 51 , N 53 , N 55 , N 57 , ..., N 59 ) of the transistors Q 51 , Q 53 , Q 55 , Q 57 , ..., Q 59 , a clock signal  1A or  1B which is shown in Fig. 12 is inputted through capacitors C 51 , C 53 , C 55 , C 57 , ..., C 59 , respectively. In addition, to gate terminals (represented by nodes N 52 , N 54 , N 56 , N 58 , ..., N 60 ) of the transistors Q 51 , Q 53 , Q 55 , Q 57 , ..., Q 59 , a clock signal  2A or  2B which is shown in Fig. 12 is inputted through capacitors C 52 , C 54 , C 56 , C 58 , ..., C 60 , respectively. In addition, MOS transistors Q 52 , Q 54 , Q 56 , Q 58 , ..., Q 60 are connected between the gate terminals N 52 , N 54 , N 56 , N 58 , ..., N 60 and source terminals (represented by nodes N 51 , N 53 , N 55 , N 57 , ..., N 59 ) of the transistors Q 51 , Q 53 , Q 55 , Q 57 , ..., Q 59 , respectively, and gate terminals of the transistors Q 52 , Q 54 , Q 56 , Q 58 , ..., Q 60 are respectively connected to the drain terminals N 53 , N 55 , N 57 , N 59 , ..., N 62 of the transistors Q 51 , Q 53 , Q 55 , Q 57 , ..., Q 59 . In the booster circuit of the present embodiment, the power supply voltage Vdd is inputted as an input signal from a common source terminal (represented by a node N 50 ) of N-channel MOS transistors Q 62 and Q 63 to the source terminals N 51 and N 53 of the transistors Q 51 and Q 53 , respectively, and the output voltage V POUT is output as an output signal from an output terminal (represented by a node N 63 ) through an N-channel MOS transistor Q 61 . As shown in the figure, gate terminals of the transistors Q 62 and Q 63 are respectively connected to the source terminal N 50 . In addition, to a source terminal (represented by a node N 62 ) of the transistor Q 61 , a clock signal  1B which is shown in Fig. 12 is inputted through a capacitor C 61 . Further, a gate terminal of the transistor Q 61 is connected to a drain terminal (represented by a node N 63 ). As shown in Fig. 12, the clock signals  1A and  1B are in opposite phase with each other. The clock signals  1A and  1B are obtained from a clock signal CLK 1 through NAND circuits ND 61 and ND 62 and inverter circuits IV 61 to IV 63 shown in Fig. 11. Normally, the amplitude V  of each of the clock signals  1A and  1B is equal to the power source voltage Vdd. In addition, the clock signals  2A and  2B are the pulse-like signals which are in the on state when the corresponding clock signals  1A and  1B are in the on state, respectively. The clock signals  2A and  2B are obtained from clock signals CLK 2 and CLK 3 through bootstrap circuits BS 51 and BS 52 , respectively, so as to have a larger amplitude than the power supply voltage Vdd. As shown in the figure, the bootstrap circuit BS 51 is constituted by MOS transistors Q 64 , Q 65 and Q 66 , an inverter circuit IV 64 , and capacitors C 62 and C 63 , and the bootstrap circuit BS 52 is constituted by MOS transistors Q 67 , Q 68 and Q 69 , an inverter circuit IV 65 , and capacitors C 64 and C 65 . Reference symbols N 66 to N 69 designates nodes, respectively. Next, the description will hereinbelow be given with respect to the operation of the semiconductor booster circuit of the present embodiment. Firstly, for a period of time of (I) of Fig. 12, since the level of the clock signal  1A is raised from the ground potential 0V up to the power supply voltage Vdd and also the electric charges corresponding to the voltage of (Vdd - Vt) are accumulated in the capacitor C 51 , the potential at the source terminal N 61 of the transistor Q 51 is about (2Vdd - Vt). In addition, the level of the clock signal  1B is dropped from the power supply voltage down to the ground potential 0V, and hence the potential at the source terminal N 53 of the transistor Q 53 is to be dropped. However, since the transistor Q 63 goes to the on state, the potential at the source terminal N 53 goes to (Vdd - Vt). In addition, since the transistor Q 52 is in the off state, and the electric charges corresponding to the voltage of (Vdd - Vt) are accumulated in the capacitor C 51 , the potential at the gate terminal N 52 of the transistor Q 51 is about (Vdd - Vt). Therefore, the transistor Q 51 is in the off state. Next, for a period of time of (II) of Fig. 12, the level of the clock signal  1A is maintained at the power supply voltage Vdd, the level of the clock signal  1B is maintained at the ground potential 0V, and the level of the clock signal  2A is raised from the ground potential 0V up to the boosted voltage Vhh (larger than the power supply voltage Vdd). Therefore, the potential at the gate terminal N 52 of the transistor Q 51 is at about (Vdd - Vt + Vhh). As a result, the transistor Q 51 is turned on, and hence the electric charges are transferred from the source terminal N 51 of the transistor Q 51 to the source terminal N 53 of the transistor Q 53 . Then, the equilibrium is obtained at the time point when the potential at the source terminal N 51 of the transistor Q 51 has become equal to that at the source terminal N 53 of the transistor Q 53 and the potential at each of the source terminals N 51 and N 53 is at about (3/2Vdd - Vt). At this time, as shown in the above-mentioned expression (2), the threshold voltage Vt of the transistor Q 51 has been increased due to the substrate effect. Then, in the case where the level of the clock signal  2A is not raised, the transistor Q 51 is turned off at the time point when the potential difference between the drain terminal N 53 and the gate terminal N 52 of the transistor Q 51 has become equal to the threshold voltage Vt of the transistor Q 51 . Therefore, the transfer of the electric charges from the capacitor C 51 to the capacitor C 53 is interrupted. Therefore, since the raising of the potential at the source terminal N 53 of the transistor Q 53 is not perfectly performed and hence the potential at the source terminal N 53 of the transistor Q 53 goes to a level lower than (3/2Vdd - Vt), the boosting capability of the booster circuit is reduced. On the other hand, in the case where the level of the clock signal  2A is raised, the transistor Q 51 can be maintained in the on state until the potential at the source terminal N 51 of the transistor Q 51 becomes equal to that at the source terminal N 53 of the transistor Q 53 , and hence the transfer of the electric charges from the capacitor C 51 to the capacitor C 53 is perfectly performed. Therefore, as shown in Fig. 13, the boosting capability is further improved as compared with the conventional booster circuit. Incidentally, Fig. 13 is a graphical representation in which the output voltage of the booster circuit of the second embodiment of the present invention obtained when increasing the number of stages of the booster circuit is compared with that of the conventional booster circuit. As can be seen from Fig. 13, the larger output voltage can be obtained by the booster circuit according to the second embodiment of the present invention, as compared with the conventional booster circuit, in the case of the same number of stages of the booster circuit. In addition, from Fig. 13, it is also understood that in order to obtain the same output voltage, the number of stages of the booster circuit according to the second embodiment of the present invention may be reduced as compared with the conventional booster circuit. In addition, Fig. 14 is a graphical representation in which the relation between the power supply voltage and the maximum output voltage when making infinite the number of stages of the booster circuit according to the second embodiment of the present invention is compared with that in the conventional circuit. From Fig. 14, it is understood that in the booster circuit according to the second embodiment of the present invention, a power supply voltage lower than that of the prior art can be used in order to obtain the desired output voltage. Incidentally, the scales in Figs. 13 and 14 are different from those in Figs. 24 and 25. Next, for a period of time of (III) of Fig. 12, since the level of the clock signal  1A is equal to the power supply voltage Vdd, the level of the clock signal  1B is equal to the ground potential 0V, and the level of the clock signal  2A is equal to the ground potential 0V, the potential at the gate terminal N 52 becomes about (Vdd - Vt). In addition, the potential at each of the source terminals N 51 and N 53 remains at about (3/2Vdd - Vt). Therefore, both the transistors Q 51 and Q 53 are turned off. Next, for a period of time of (IV) of Fig. 12, since the level of the clock signal  1A is dropped from the power supply voltage Vdd down to the ground potential 0V, the potential at the source terminal N 51 of the transistor Q 51 is to be dropped. However, since the transistor Q 62 is turned on, the potential at the source terminal N 51 becomes (Vdd - Vt). In addition, since the electric charges corresponding to the voltage of (3/2Vdd - Vt) are accumulated in the capacitor C 53 , the potential at the source terminal N 53 of the transistor Q 53 becomes about (5/2Vdd - Vt). Therefore, the transistor Q 52 is turned on. Accordingly, the potential at the gate terminal N 52 of the transistor Q 51 becomes equal to that at the source terminal N 51 of the transistor Q 51 , and the potential at the gate terminal N 52 becomes about (Vdd - Vt). Next, for a period of time of (V) of Fig. 12, the level of the clock signal  1A is the ground potential 0V, the level of the clock signal  1B is the power source voltage Vdd, the level of the clock signal 2B is raised from the ground potential 0V up to the boosted voltage Vhh (larger than the power supply voltage Vdd), and the electric charges corresponding to the voltage of (3/2Vdd - Vt) are accumulated in the capacitor C 54 . Therefore, the potential at the gate terminal N 54 of the transistor Q 53 becomes about (3/2Vdd - Vt + Vhh). Therefore, the transistor Q 53 is turned on, and the electric charges are transferred from the source terminal N 53 of the transistor Q 53 to the source terminal N 55 of the transistor Q 55 . Then, at the time point when the potential at the source terminal N 53 of the transistor Q 53 has become equal to that at the source terminal N 55 of the transistor Q 55 , the equilibrium is obtained. At this time, the potential at the source terminal N 55 is raised. Next, for a period of time of (VI) of Fig. 12, the level of the clock signal  1A is the ground potential 0V, the level of the clock signal  1B is the power supply voltage Vdd, and the level of the clock signal  2A is dropped from the boosted voltage Vhh down to the ground potential 0V. Therefore, the potential at the gate terminal N 54 goes to about (3/2Vdd -Vt). As a result, both the transistors Q 53 and Q 54 are turned off. In the above description, for better understanding of the operation of the booster circuit, the description has been given with the interval of one cycle of the clock signal CK divided into six periods of (I) to (VI). However, the rising and falling ends of the clock signals CLK 2 and CLK 3 may be substantially at the same timings as those of the clock signal CK. As a result, the clock frequency f of the clock signal can be increased, and hence, as seen from the above-mentioned expression (1), the output voltage V POUT produced from the output stage in the presence of the load current I OUT can be increased. Next, the bootstrap circuit BS 51 will hereinbelow be described with reference to Figs. 11 and 12. When the level of the clock signal CLK 2 is raised from the ground potential 0V up to the power supply voltage Vdd in a period of time of (II) of Fig. 12, the level of the clock signal  2A is changed from the ground potential 0V to the voltage of (Vdd - Vt) after a delay of the time constant which is determined by both the transistor Q 66 and the capacitor C 62 . In addition, after a delay of the time constant which is determined by both the inverter IV 64 and the capacitor C 63 , the potential at the gate terminal N 66 of the transistor Q 66 is changed from the power supply voltage Vdd to the ground potential 0V. At this time, the transistor Q 66 is switched from the on state to the off state, and the potential at the source terminal N 67 of the transistor Q 65 is changed from the ground potential 0V to the power supply voltage Vdd. Therefore, at the time point when the transistor Q 60 has been switched from the on state to the off state, the voltage of (Vdd - Vt) is applied across the capacitor C 62 . Therefore, when the load capacity of the clock signal  2A is considerably smaller than the capacitance of the capacitor C 62 , the voltage level of the clock signal  2A is changed to (2Vdd - Vt). The operation of the other bootstrap circuit BS 52 is the same as that of the above-mentioned bootstrap circuit BS 51 . Therefore, the clock signals CLK 2 and CLK 3 are respectively inputted to the bootstrap circuits BS 51 and BS 52 , whereby it is possible to obtain the clock signals  2A and  2B each having a larger amplitude than the power supply voltage Vdd. As described above, in the semiconductor booster circuit according to the present embodiment, the levels of the clock signals  2A and  2B are boosted by the respective bootstrap circuits so as to have the larger amplitude than the power supply voltage Vdd, whereby the gate voltage of each of the MOS transistors Q 51 , Q 53 , Q 55 , Q 57 , ..., Q 59 which are connected in cascade can be increased to a higher level than that of the prior art. Therefore, since even if the threshold voltage Vt is increased due to the substrate effect, the MOS transistors Q 51 , Q 53 , Q 55 , Q 57 , ..., Q 59 can be normally turned on, it is possible to obtain an output voltage V POUT which is increased in proportion to the number n of stages of the semiconductor booster circuit. In addition, by applying to the gate terminals N 52 , N 54 , N 56 , N 58 , ..., N 60 of the transistors Q 51 , Q 53 , Q 55 , Q 57 , ..., Q 59 the clock signals  2A and  2B , respectively, which are independent of the clock signals  1A and  1B applied to the source terminals N 51 , N 53 , N 55 , N 57 , ..., N 59 , so as to turn on each of the transistors Q 51 , Q 53 , Q 55 , Q 57 , ..., Q 59 , with no potential difference between its source and drain whereby when transferring the electric charges from the preceding stage to the subsequent stage in the booster circuit, it is possible to realize the transfer of the electric charges in which the voltage drop corresponding to the potential difference between the source and the drain does not occur. Therefore, in the above-mentioned expression (1), the threshold voltage Vt can be regarded as zero, and therefore, as compared with the conventional booster circuit, the boosting operation can be more efficiently performed. Thus, even in the case where the number n of stages of the booster circuit, and the power supply voltage Vdd are the same as those of the conventional booster circuit, it is possible to obtain a larger output voltage V POUT than that of the conventional booster circuit. For example, in the case where the power supply voltage Vdd is 2.5V, and the number n of stages of the booster circuit is 20, assuming that the capacitance ratio C/(C + Cs) is 0.9, the absolute value of the threshold voltage |Vt| is 0.6V, the load current I OUT in the output stage is zero, and the boosted voltage Vhh is 3.0V, only 20V can be obtained as the output voltage V POUT in the conventional circuit, but in the booster circuit according to the present embodiment, about 47V can be obtained as the output voltage V POUT . This means that in the case where the output voltage V POUT is the same, the booster circuit according to the present embodiment can provide a larger load current I OUT than that in the conventional circuit. In addition, in the booster circuit according to the present embodiment, as can be seen from Fig. 14, even with a low power supply voltage Vdd which can not be boosted by the conventional circuit, the desired output voltage can be obtained. For example, assuming that the capacitance ratio C/(C + Cs) is 0.9, the absolute value of the threshold voltage |Vt| is 0.6V, the load current I OUT in the output stage is zero, and the boosted voltage Vhh is 3.0V, the power supply voltage Vdd needs to be set to 2.5V or more, in the conventional booster circuit, in order to obtain 20V as the output voltage V POUT , but only 1.5V is sufficient for the power supply voltage Vdd in the booster circuit according to the present embodiment. According to the second embodiment, since the clock signal which is used to render the MOS transistor constituting each of the stages conductive is boosted so as to have a larger amplitude than the power supply voltage Vdd, the desired output voltage can be obtained even in the case where the power supply voltage is low. In addition, in the case where the power supply voltage is constant, a larger load current than that in the prior art can be obtained. Furthermore, in the case where the same output voltage as that in the prior art is to be obtained, the number of stages of the booster circuit can be further reduced as compared with the prior art. Next, the description will hereinbelow be given with respect to a third embodiment of the present invention with reference to Figs. 15 and 16. A circuit configuration shown in Fig. 15 is identical to that of Fig. 1 except for the provision of bootstrap circuits BS 1 and BS 2 illustrated in the lower half of the figure. Therefore, the operation of the booster circuit according to the third embodiment of the present invention is substantially the same as that of the booster circuit according to the first embodiment. That is, the configuration of the first and second stages which are consecutive in the booster circuit of the third embodiment is the same as that of Fig. 2. Then, when the clock signals  1A ,  1B ,  2A and  2B are inputted in the timing as shown in Fig. 16 in the booster circuit of Fig. 15, the state in change of the operation of each of the transistors of the booster circuit as shown in Fig. 2 and the tendency in change of the potentials at the nodes N A , N B , N C and N D are the same as those in the first embodiment shown in Figs. 5A to 5F and Figs. 4A and 4D. The only differences between the first embodiment and the third embodiment are as follows. (a) For a period of time of (II) of Fig. 16, the potential at the gate terminal N C of the transistor M 1 is dropped as shown in Fig. 4C. However, the voltage drop is equal to the power supply voltage Vdd in the first embodiment, but is equal to the boosted voltage Vhh in the fifth embodiment. (b) For a period of time of (III) of Fig. 16, the potential at the gate terminal N C of the transistor M 1 is raised as shown in Fig. 4C. In this connection, the raised voltage is equal to the power supply voltage Vdd in the first embodiment, but is equal to the boosted voltage Vhh in the third embodiment. (c) For a period of time of (V) of Fig. 16, the potential at the gate terminal N E of the transistor M 3 is dropped. In this connection, the voltage drop is equal to the power supply voltage Vdd in the first embodiment, but is equal to the boosted voltage Vhh in the third embodiment. (d) For a period of time of (VI) of Fig. 16, the potential at the gate terminal N E of the transistor M 3 is raised. In this connection, the raised voltage is equal to the power supply voltage Vdd in the first embodiment, but is equal to the boosted voltage Vhh in the third embodiment. Next, the description will hereinbelow be given with respect to the operation of the bootstrap circuit BS 71 with reference to Figs. 15 and 16. Firstly, when the level of the clock signal CLK 2 shown in Fig. 17 is changed from 0V up to Vdd. At first, the potential of  2A is changed from 0V to Vdd - Vt (Vt is the threshold voltage of the transistor Q 84 ). The threshold voltage Vt of the transistor Q 84 is, for example, 0.1V. When Vdd=lV, and the clock signal CLK 2 is changed from 0V to 1V, the initial potential of  2A becomes 0.7V (Vt of the transistor Q 84 is raised by about 0.2V due to the back bias effect). At the same time, the inverter IV 85 performs the inversion operation at the time when the level of the input voltage  2A has exceeded the logical threshold voltage (normally, about Vdd/2), and also the potential at the node N 90 is dropped from Vdd to 0V. As a result, the transistor Q 85 is turned on. Next, on the basis of the function of both the inverter IV 84 and the capacitor C 83 , the potential at the node N 87 is changed from Vdd down to 0V after a lapse of predetermined time delay from the clock signal CLK 2 and the node N 90 . Therefore, although the transistor Q 86 is initially in the on state, after a lapse of the predetermined time delay, the transistor Q 86 is turned off. Until a lapse of the predetermined time delay, both the transistors Q 85 and Q 86 are in the on state. In this connection, by setting the on-resistance of the transistor Q 86 to a value sufficiently smaller than the on-resistance of the transistor Q 85 , the potential at the node N 88 is maintained at about 0V until a lapse of the predetermined time delay. That is, after a lapse of the predetermined delay time, the potential at the node N 88 is changed from about 0V to Vdd. Next, at the same time the potential at the node N 88 is changed from about 0V to Vdd, the potential of the clock signal  2A goes to (2Vdd - Vt) on the basis of the function of the capacitor C 82 . Thus, it is possible to obtain the larger voltage than Vdd. For example, in the case of Vdd=1V, the level of the clock signal  2A settles to 1.7V. This is also applied to the other bootstrap circuit BS 72 . Therefore, by inputting the clock signals CLK 2 and CLK 3 to the bootstrap circuits BS 71 and BS 73 , respectively, it is possible to obtain the clock signals  2A and  2B each having a larger amplitude than the power supply voltage Vdd. The third embodiment offers basically the same effects as those of the first embodiment in that the high output voltage can be obtained. In addition, in the third embodiment, the level of each of the clock signals  2A and  2B is boosted by the bootstrap circuit BS 1 or BS 2 to a larger amplitude than the power supply voltage Vdd, whereby the gate voltage of each of the MOS transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 , which are connected in cascade, can be made higher than that in the prior art. Therefore, even if the threshold voltage Vt is increased due to the substrate effect, the MOS transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 can be normally turned on, and hence it is possible to obtain the output voltage V POUT which is increased in proportion to the number n of stages of the semiconductor booster circuit. The relationship between the number of stages of the booster circuit and the output voltage is substantially the same as that in the second embodiment shown in Fig. 13. In addition, in the semiconductor booster circuit according to the present embodiment, the MOS transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 are driven by the clock signals  2A and  2B which are respectively obtained by boosting the clock signals CLK 2 and CLK 3 to a larger amplitude than the power supply voltage Vdd, whereby the MOS transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 can be sufficiently turned on even with the very low power supply voltage value (e.g., Vdd=0.7 to 1.0V). In the present embodiment, the lowest power supply voltage which can be boosted is determined by the threshold voltage Vt of each of the P-channel MOS transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 constituting the booster circuit. As in the first embodiment, in the case where the amplitude V 2 of each of the clock signals  2A and  2B is equal to the power supply voltage Vdd, the voltage drop at the node N C in a period of time of (II) shown in Fig. 4C does not reach the threshold voltage Vt (e.g., -0.6V) of each of the P-channel MOS transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 if Vdd becomes a level equal to or lower than 1V and hence the P-channel MOS transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 can not be sufficiently turned on. On the other hand, as in the third embodiment, the amplitude V 2 of each of the clock signals  2A and  2B is boosted by the bootstrap circuit BS 1 or BS 2 to a larger amplitude than the power supply voltage Vdd, whereby the boosting operation can be stably performed even in the very low power supply voltage value of Vdd=0.7 to 1.0V. In addition, since the P-channel MOS transistors Q 1 , Q 3 , Q 5 , Q 7 , ..., Q 9 can be sufficiently turned on, it is also possible to prevent the reduction of the boosting capability of the booster circuit. Now, the description will hereinbelow be given with respect to the relationship between the power supply voltage Vdd and the maximum output voltage V POUT when making the number of stages of the booster circuit infinite with reference to Fig. 14. In the case of the conventional booster circuit, even if Vdd becomes larger than Vto, the relationship has a characteristic as shown in the curve (c) of Fig. 14 since Vt is increased due to the substrate effect with the increasing of the output voltage V POUT . On the other hand, in the booster circuit of the present embodiment, in the case where the relation of V 1 =V 2 =V  =Vdd is established, and also the parasitic capacity can be perfectly disregarded, i.e., for example, the relation of C/(C + Cs)=1 is established, the boosting operation can be performed depending on only the number n of stages of the booster circuit if the desired voltage equal to or higher than Vdd=V  =Vto is obtained. However, actually, since the parasitic capacity can not be perfectly disregarded, e.g. C/(C + Cs) is about 0.9, the boosting operation can not be performed when V = Vdd, unless Vdd is equal to or larger than 1.1, like the second embodiment. In addition in the MOS transistor, even if the gate to source voltage exceeds Vto slightly, the boosting capability of the booster circuit is slightly reduced since the source to drain resistance is large and hence the booster circuit provides a characteristic as shown in the curve (b) of Fig. 14. On the other hand, in the structure of the third embodiment, since V 2 can be set to 1.7Vdd for example, it is possible to supply a gate to source voltage by which the MOS transistor can be sufficiently turned on even if the parasitic capacity is present. As a result, the third embodiment provides a characteristic as shown in the curve (a) of Fig. 14. Next, the description will hereinbelow be given with respect to a fourth embodiment of the present invention with reference to Figs. 17 and 18. Fig. 17 shows a configuration of a semi-conductor booster circuit according to the fourth embodiment of the present invention. As shown in Fig. 17, N-channel depletion type MOS transistors M 101 to M 108 are connected in series between an input terminal N 120 and an output terminal to configure a booster circuit having four stages. That is, each pair of the transistors M 101 and M 102 ; M 103 and M 104 ; M 105 and M 106 ; M 107 and M 108 constitute respective stages. Gate terminals of the transistors M 101 to M 108 are respectively connected to drain terminals (represented by nodes N 100 to N 107 ). Then, a clock signal  A which is shown in Fig. 20 is inputted through capacitors C 101 , C 103 , C 105 and C 107 , respectively, to the drain terminals N 100 , N 102 , N 104 and N 106 and also a clock signal  B which is in opposite phase with the clock signal  A is inputted through capacitors C 102 , C 104 , C 106 and C 108 , respectively, to the drain terminals N 101 , N 103 , N 105 and N 107 . In addition, both drain terminals and gate terminals of N-channel MOS transistors M 120 and M 121 are connected to the input terminal (represented by a node N 120 ), and substrate terminals thereof are connected to a ground terminal (represented by a node N 121 ). In addition, substrate terminals of the transistors M 101 to M 108 are divided into two groups, as will be described later, i.e., the group of the transistors M 101 to M 104 and the group of the transistors M 105 to M 108 . In this connection, the substrate terminals of the transistors M 101 to M 104 and the substrate terminals of the transistors M 105 to M 108 are respectively connected to the drain terminal N 100 of the transistor M 101 and the drain terminal N 104 of the transistor M 105 . That is, the node N 100 is connected to the source terminal of the transistor M 120 , both the drain terminal and the gate terminal of the transistor M 101 , one terminal of the capacitor C 101 and the substrate terminals of the transistors M 101 to M 104 . The node N 101 is connected to the source terminal of the transistor M 121 , both the drain terminal and the gate terminal of the transistor M 102 , the source terminal of the transistor M 101 and one terminal of the capacitor C 102 . The node N 102 is connected to both the drain terminal and the gate terminal of the transistor M 103 , the source terminal of the transistor M 102 and one terminal of the capacitor C 103 . The node N 103 is connected to both the drain terminal and the gate terminal of the transistor M 104 , the source terminal of the transistor M 103 and one terminal of the capacitor C 104 . The node N 104 is connected to both the drain terminal and the gate terminal of the transistor M 105 , the source terminal of the transistor M 104 , one terminal of the capacitor C 105 and the substrate terminals of the transistors M 105 to M 108 . The node N 105 is connected to both the drain terminal and the gate terminal of the transistor M 106 , the source terminal of the transistor M 105 and one terminal of the capacitor C 106 . The node N 106 is connected to both the drain terminal and the gate terminal of the transistor M 107 , the source terminal of the transistor M 106 and one terminal of the capacitor C 107 . In addition, the node N 107 is connected to both the drain terminal and the gate terminal of the transistor M 108 , the source terminal of the transistor M 107 and one terminal of the capacitor C 108 . Further, the output terminal of the semiconductor booster circuit is connected to the source terminal of the transistor M 108 . In this configuration, the series-connected four stages are divided into a group of two stages of the input side including the transistors M 101 to M 104 and a group of two stages of the output side including the transistors M 105 to M 108 . Therefore, the substrate terminals of the transistors M 101 to M 108 are divided into the group of substrate terminals of the transistors M 101 to M 104 and the group of substrate terminals of the transistors M 105 to M 108 . In this connection, the substrate terminals of the transistors M 101 to M 104 are connected to the drain terminal N 100 of the transistor M 101 and the substrate terminals of the transistors M 105 to M 108 are connected to the drain terminal N 104 of the transistor M 105 . Therefore, as compared with the conventional booster circuit shown in Fig. 26, a substrate bias voltage Vbs of the transistors M 101 to M 107 in the booster circuit of the present embodiment is smaller than that of the transistors M 1 to M 7 in the conventional booster circuit. As a result, the threshold voltage Vt of the transistors M 105 to M 108 in the booster circuit of the present embodiment is lower than that of the transistors M 5 to M 8 in the conventional booster circuit. As a result, as compared with the conventional booster circuit, the boosting capability is further improved in the booster circuit of the present embodiment so that the high output voltage is obtained, and also the number of stages required for obtaining the same output voltage can be further reduced, as compared with the conventional booster circuit. In addition, since the threshold voltage Vt in each of the stages is lowered, the lower limit of the boostable power supply voltage Vdd becomes small, and hence the drive with the low power supply voltage becomes possible. Next, the description will hereinbelow be given with respect to the device structure of the booster circuit shown in Fig. 17 with reference to Fig. 18. As shown in Fig. 18, in an N type well region 402 which is formed in a P type semiconductor substrate 401, P type well regions 403, 404 and 405 are respectively formed. P + type impurity diffusion layer 406 and N + type impurity diffusion layers 409 and 410 are respectively formed in the P + type well region 403, and also a polycrystalline silicon film 421 as a gate electrode is formed above a channel region between the N type impurity diffusion layers 409 and 410 as the drain and the source with an interposed gate oxide film (not shown), thereby constituting the transistor M 120 . In addition, a P + type impurity diffusion layer 407 and N + type impurity diffusion layers 411 to 415 are respectively formed in the P type well region 404, and also polycrystalline silicon films 422 to 425 as gate electrodes of the transistors are formed above channel regions between N + type impurity diffusion layers 411 to 415 constituting the drains or the sources of the transistors with an intermediate gate oxide film (not shown), thereby constituting the four transistors M 101 to M 104 . In addition, a P + type impurity diffusion layer 408 and N + type impurity diffusion layers 416 to 420 are respectively formed in the P type well region, and also polycrystalline silicon films 426 to 429 as gate electrodes of the transistors are formed above channel regions between N + type impurity diffusion layers 416 to 420 constituting the drains or the sources of the transistors with an intermediate gate oxide film (not shown), thereby constituting the four transistors M 105 to M 108 . The polycrystalline silicon films 422 to 425 as the gate electrodes of the transistors M 101 to M 104 are respectively connected to the N + type impurity diffusion layers 411 to 414, and the polycrystalline silicon films 426 to 429 as the gate electrodes of the transistors M 105 to M 108 are respectively connected to the N + type impurity diffusion layers 416 to 419. In addition, the clock signal  A as shown in Fig. 4 is inputted through the capacitors C 101 , C 103 , C 105 and C 107 , respectively, to the polycrystalline silicon films 422, 424, 426 and 428 as the gate electrodes of the transistors M 101 , M 103 , M 105 and M 107 and the clock signal  B which is in opposite phase with the clock signal  A is inputted through the capacitors C 102 , C 104 , C 106 and C 108 , respectively to the polycrystalline silicon films 423, 425, 427 and 429 as the gate electrodes of the transistors M 102 , M 104 , M 106 and M 108 . In addition, both the N + type impurity diffusion layer 409 as the drain and the polycrystalline silicon film 421 as the gate electrode of the transistor M 120 are connected to the power supply terminal N 120 . The P type well region 403 is connected to the ground terminal N 121 through the P + type impurity diffusion layer 406, and hence the substrate potential of the transistor M 120 is equal to the potential at the P type well region 403. In addition, the P type well region 404 is connected to both the N + type impurity diffusion layer 410 as the source of the transistor M 120 and the N + type impurity diffusion layer 411 as the drain of the transistor M 101 through the P + type impurity diffusion layer 407, and hence the substrate potential of each of the transistors M 101 to M 104 is equal to the potential at the P type well region 404. Further, the P type well region 405 is connected to both the N + type impurity diffusion layer 415 as the source of the transistor M 104 and the N + type impurity diffusion layer 416 as the drain of the transistor M 105 through the P + type impurity diffusion layer 408, and hence the substrate potential of each of the transistors M 105 to M 108 is equal to the potential at the P type well region 405. Although in the embodiment described above, the substrate portions of the eight transistors M 101 to M 108 constituting the booster circuit are divided into two groups, the number of groups is not limited thereto. For example, the substrate portions are divided by every stages, and thus the four groups may be formed. But, if each division is too small, the boosting efficiency is improved, but there arises a problem that the integration of the elements can not be increased. Incidentally, although the above-mentioned embodiment has the circuit configuration having the four stages, it is to be understood that the number of stages is not limited thereto. Next, the description will hereinbelow be given with respect to a fifth embodiment of the present invention with reference to Figs. 19 and 21. As shown in Fig. 19, four circuit blocks PCH 01 to PCH 04 are connected in cascade to configure the semiconductor booster circuit according to the fifth embodiment of the present invention. Each of the circuit blocks PCH 01 to PCH 04 is configured by connecting P-channel MOS transistors P 201 and P 202 in series with each other. Now, to a drain terminal N 201 of the transistor P 201 , a clock signal  1A which is shown in Fig. 21 is inputted through a capacitor C 201 . To a gate terminal N 203 of the transistor P 201 , a clock signal  1A shown in Fig. 21 is inputted through a capacitor C 202 . To a drain terminal N 202 of the transistor P 202 , a clock signal  1B is inputted through a capacitor C 203 . In addition, to a gate terminal N 205 of the transistor P 202 , a clock signal  2B is inputted through a capacitor C 204 . Further, a P-channel MOS transistor P 203 is connected between the source terminal N 202 and the gate terminal N 203 of the transistor P 201 , and the gate terminal of the transistor P 203 is connected to the drain terminal N 201 of the transistor P 201 . In addition, a P-channel MOS transistor P 204 is connected between the source terminal N 204 and the gate terminal N 205 of the transistor P 202 , and the gate terminal of the transistor P 204 is connected to the drain terminal N 202 of the transistor P 202 . In addition, drain terminals and gate terminals of N-channel depletion type MOS transistors M 220 and M 221 are respectively connected to a power supply terminal N 220 , substrate terminals thereof are connected to a ground terminal N 221 , and source terminals thereof are respectively connected to the drain terminals N 201 and N 202 of the transistors P 201 and P 202 in the circuit block PCH 01 . Incidentally, instead of the N-channel depletion type MOS transistors M 220 and M 221 , N-channel enhancement type MOS transistors may also be available. Substrate terminals of the four transistors P 201 to P 204 in the circuit blocks PCH 01 and PCH 02 are connected to a substrate terminal SUB 1 formed of a common N type well region, and the substrate terminal SUB 1 is connected to a source terminal (not shown) of the transistor P 204 in the circuit block PCH 02 . On the other hand, substrate terminals of four transistors P 201 to P 204 in the circuit blocks PCH 03 and PCH 04 are connected to a substrate terminals SUB 2 formed of a common N type well region, and the substrate terminal SUB 2 is connected to the source terminal (not shown) of the transistor P 204 in the circuit block PCH 04 . Incidentally, the substrate terminals SUB 1 and SUB 2 are electrically insulated from each other. The source terminal N 204 of the transistor P 202 in the circuit block PCH 01 is connected to the drain terminal N 201 of the transistor P 201 in the circuit block PCH 02 , the source terminal N 204 of the transistor P 202 in the circuit block PCH 02 is connected to the drain terminal N 201 of the transistor P 201 in the circuit block PCH 03 , and the source terminal N 204 of the transistor P 202 in the circuit block PCH 03 is connected to the drain terminal N 201 of the transistor P 201 in the circuit block PCH 04 so that the four circuit blocks PCH 01 to PCH 04 are connected in cascade. In addition, the source terminal of the transistor P 202 in the circuit block PCH 04 is connected to an output terminal to output the output voltage V POUT . Next, the description will hereinbelow be given with respect to the operation of the semiconductor booster circuit according to the fifth embodiment of the present invention. Incidentally, in the following description, it is meant by "smaller than the threshold voltage" that the potential at the drain or the source is lower than that at the gate, or the potential at the source or the drain is higher than that at the gate, but the difference therebetween is smaller than the threshold voltage. By "larger than the threshold voltage", it is meant that the potential at the source or the drain is higher than that at the gate and additionally the difference therebetween is larger than the threshold voltage. Firstly, for a period of time of (I) of Fig. 21, the level of the clock signal  1A is the low potential ("L"), and the level of each of the clock signals  2A ,  1B and  2B are the high potential ("H"). Thus, a current is caused to flow from the power supply terminal N 220 shown in Fig. 19 to the drain terminal N 201 of the transistor P 201 through the transistor M 220 , and hence the electric charges are accumulated in the capacitor C 201 . The potential at the drain terminal N 202 of the transistor P 202 is higher than its previous potential existing when the level of the clock signal 1B was previously "L" by V  C/(C + Cs)(V  is the amplitude of each of the clock signals  1A and  1B ) shown in the above-mentioned expression (1). Thus, if the relation in magnitude between the potential at the drain terminal N 201 of the transistor P 201 and the potential at the drain terminal N 202 of the transistor P 202 becomes larger than the threshold value of the transistor P 203 , the transistor P 203 is turned on, and hence the conduction is established between the gate terminal N 203 of the transistor P 201 and the drain terminal N 202 of the transistor P 202 . At this time, since the potential relation between the gate terminal N 203 and the drain terminal N 201 or the source terminal N 202 of the transistor P 201 is lower than the threshold voltage of the transistor P 201 , the transistor P 201 is turned off. In addition, both the transistors P 202 and P 204 are turned off since the potential relation between the gate terminal and the drain terminal or the source terminal is lower than the threshold voltage. Next, when the operation proceeds from a period of time of (I) to a period of time of (II), the level of each of the clock signals  2A and  2B remains "H", and also the level of the clock signal  1A is changed from "L" to "H" and the level of the clock signal  1B is changed from "H" to "L". Therefore, the potential at the gate terminal N 201 of the transistor P 203 is changed from "L" to "H", and also the potential at the gate terminal N 202 of the transistor P 204 is changed from "H" to "L". Then, at the time point when the potential relation between the gate terminal N 201 and the drain terminal N 202 or the source terminal N 203 of the transistor P 203 has become lower than the threshold voltage of the transistor P 203 , the transistor P 203 is switched from the on state to the off state. In addition, at the time point when the potential relation between the gate terminal N 202 and the drain terminal N 204 or the source terminal N 205 of the transistor P 204 has become larger than the threshold voltage of the transistor P 204 , the transistor P 204 is switched from the off state to the on state, and also the conduction is established between the drain terminal N 204 and the source terminal N 205 of the transistor P 204 . Next, when the operation proceeds from a period of time of (II) to a period of time of (III), the level of each of the clock signals  1A and  2B remains "H", and the level of the clock signal  1B remains "L", and also the level of the clock signal  2A is changed from "H" to "L". Therefore, the potential at the gate terminal N 203 of the transistor P 201 is changed from "H" to "L", and hence at the time point when the potential relation between the gate terminal N 203 and the drain terminal N 201 or the source terminal N 202 of the transistor P 201 has become larger than the threshold voltage of the transistor P 201 , the transistor P 201 is switched from the off state to the on state, a current is caused to flow from the drain terminal N 201 of the transistor P 201 to the drain terminal N 202 of the transistor P 202 , and the potential at the drain terminal N 202 of the transistor P 202 is raised. Next, when the operation proceeds from a period of time of (III) to a period of time of (IV), the level of each of the clock signals  1A and  2B remains "H", and the level of the clock signal  1B remains "L", and also the level of the clock signal  2A is changed from "L" to "H". Therefore, the potential at the gate terminal N 203 of the transistor P 201 is changed from "L" to "H", and also the transistor P 201 is switched from the on state to the off state. Next, when the operation proceeds from a period of time of (IV) to a period of time of (V), the level of each of the clock signals  2A and  2B remains "H", and also the level of the clock signal  1A is changed from "H" to "L", and the level of the clock signal  1B is changed from "L" to "H". Therefore, the potential at the gate terminal N 201 of the transistor P 203 is changed from "H" to "L", and the potential at the gate terminal N 202 of the transistor P 204 is changed from "L" to "H", and at the time point when the potential relation between the gate terminal N 201 and the drain terminal N 202 or the source terminal N 203 of the transistor P 203 has become larger than the threshold voltage of the transistor P 203 , the transistor P 203 is switched from the off state to the on state, and the conduction is established between the drain terminal N 202 and the source terminal N 203 of the transistor P 203 . In addition, at the time point when the potential relation between the gate terminal N 202 and the drain terminal N 204 or the source terminal N 205 of the transistor P 204 has become smaller than the threshold voltage of the transistor P 204 , the transistor P 204 is switched from the on state to the off state. Next, when the operation proceeds from a period of time of (V) to a period of time of (VI), the level of each of the clock signals  2A and  1B remains "H", the level of the clock signal  1A remains "L", and the level of the clock signal  2A is changed from "H" to "L". Therefore, the potential at the gate terminal N 205 of the transistor P 202 is changed from "H" to "L", and hence at the time point when the potential relation between the gate terminal N 205 and the drain terminal N 202 or the source terminal N 204 of the transistor P 202 has become larger than the threshold voltage of the transistor P 202 , the transistor P 202 is changed from the off state to the on state, a current is caused to flow from the drain terminal N 202 to the source terminal N 204 of the transistor P 202 , and the potential at the source terminal N 204 of the transistor P 202 is raised. Next, when the operation proceeds from a period of time of (VI) to a period of time of (VII), the level of each of the clock signals  2A and  1B remains "H", and also the level of the clock signal  1A remains "L", and the level of the clock signal  2B is changed from "L" to "H". Therefore, the potential at the gate terminal N 205 of the transistor P 202 is changed from "L" to "H", and hence at the time point when the potential relation between the gate terminal N 205 and the drain terminal N 202 or the source terminal N 204 of the transistor P 202 has become smaller than the threshold voltage of the transistor P 202 , the transistor P 202 is switched from the on state to the off state. In the above-mentioned operation, with respect to the transistors P 201 and P 203 and the capacitors C 201 and C 202 for example, when the potential at the node N 201 is "H" and the potential at each of the nodes N 202 and N 203 is "L" (for a period of time of (III)), the transistor P 201 is turned on, a current is caused to flow from the node N 201 to the node N 202 , and hence the potential at the node N 202 is further raised as compared with its potential at the time before the transistor P 201 is turned on. Subsequently, when the level of the clock signal  1A goes to "L", the level of the clock signal  1B goes to "H", and also the potential at the node N 201 goes to "L" and the potential at the node N 202 goes to "H" (for a period of time of (V)), the transistor P 203 is turn on, and the node N 202 becomes conductive with the node N 203 . Therefore, the potential difference between the source and the gate of the transistor P 201 becomes zero. At this time, although the potential at the node N 201 becomes lower than that at the node N 202 , no current is caused to flow between the nodes N 202 and N 201 since the transistor P 201 is turned off. In addition, the potential at the node N 202 becomes higher than the potential existing when the transistor P 201 is in the on state by about V·C/(C + Cs) as shown in the expression (1), and therefore the potential at the node N 202 becomes higher than the potential existing when the "H" state has been obtained. The above-mentioned operation is also applied to the circuit blocks PCH 02 to PCH 04 , and hence the output potential of the circuit block located more backward stage or closer to the output terminal becomes higher in the positive direction. That is, the semiconductor booster circuit according to the fifth embodiment is the positive high voltage generating circuit employing the P-channel MOS transistors. Incidentally, in the semiconductor booster circuit according to the fifth embodiment, for example, since the potential at the substrate terminal SUB 1 is higher than the potential at the sources or drains of the transistors P 201 and P 202 , the absolute value of the threshold voltage is increased due to the substrate effect, and hence both the transistors P 201 and P 202 are difficult to be turned on, or there is a possibility that the on-current becomes small. However, the whole substrate potentials are divided into the two potentials, i.e., the potential at SUB 1 and the potential at SUB 2 , whereby the increasing of the threshold voltage due to the substrate bias effect is reduced. If the substrate potentials are divided into four blocks and the potential of each block is controlled, the integration becomes poor but the increasing of the threshold voltage due to the substrate bias effect can be further reduced. In the semiconductor booster circuit according to the fifth embodiment, since the voltage drop when transferring the electric charges from the preceding stage to the subsequent stage can be made substantially zero, the larger boosting capability is obtained as compared with the fourth embodiment. In particular, in the case where the power supply voltage Vdd is about 0.8V to 2.0V, the difference in boosting capability between the fourth embodiment and the fifth embodiment becomes remarkably large. For example, in the case where the power supply voltage Vdd is about 0.8V to 2.0V, the number n of stages of the booster circuit required for obtaining a desired output voltage needs to be greatly increased in the booster circuit of the fourth embodiment due to the voltage drop when transferring the electric charges from the preceding stage to the subsequent stage, but in the booster circuit of the fifth embodiment, it is not required at all. For example, in the case where the power supply voltage Vdd is 2.0V, in the fourth embodiment, the number of stages of the booster circuit required for obtaining the output voltage V POUT of 23V is 20 whereas in the booster circuit of the fifth embodiment, the required number of stages is only 12. On the other hand, the booster circuit of the fourth embodiment is advantageous as compared with the booster circuit of the fifth embodiment in that the configuration is simpler and also only two kinds of clock signals are enough. Incidentally, it is to be understood that in the above-mentioned embodiments, the various changes may be made. For example, the number of stages of the booster circuit is not limited to four in the above-mehtioned embodiment, and hence it may be set to any value determined in accordance with the voltage to be boosted, the circuit scale and the like. In addition, the N-channel depletion type MOS transistors M 101 to M 108 are exemplarily employed as the transistors constituting the booster circuit in the fourth embodiment and also the P-channel MOS transistors P 201 to P 204 are exemplarily employed as the transistors constituting the booster circuit in the fifth embodiment. However, as for those transistors, other transistors such as N-channel enhancement type MOS transistors may also be employed. For example the N-channel MOS transistors M 101 to M 108 in the fourth embodiment may be substituted by P-channel MOS transistors which are formed in the N type well region, and also the power supply terminal N 120 may be grounded to provide the negative high voltage generating circuit. In addition, the P-channel MOS transistors P 201 to P 204 in the fifth embodiment may be substituted by N-channel MOS transisters which are formed in the P type well region to provide the negative high voltage generating circuit. In the fourth and fifth embodiments, the substrate terminals of the MOS transistors constituting the booster circuit are divided into the necessary groups, and also are controlled to the different potentials for the groups, whereby it is possible to prevent the substrate bias effect from occurring. Therefore, the high boosting capability can be obtained and also the increasing of the circuit area can be suppressed to the minimum.

Claims: A semiconductor booster circuit, comprising: a plurality of stages, each having a first MOS transistor (Q 1 , Q 3 , Q 5 , Q 7 , or Q 9 ), a first capacitor (C 1 , C 3 , C 5 , C 7 , or C 9 ) and a second capacitor (C 2 , C 4 , C 6 , C 8 , or C 10 ), said first MOS transistor being formed in a well and having a drain, a source and a gate, said first capacitor having one terminal connected to the drain of said MOS transistor, and said second capacitor having one terminal connected to the gate of said MOS transistor; said plurality of stages being connected in series between an input terminal and an output terminal by connecting said first MOS transistors(Q 1 , Q 3 , Q 5 , Q 7 , and Q 9 ) of said plurality of stages in cascade; means for applying a power supply voltage (Vdd) to the drain of said first MOS transistor (Q 1 ) in the stage closest to said input terminal so that said power supply voltage is boosted by said first MOS transistor in each of said stages thereby generating a boosted voltage which is higher than said power supply voltage at the source of said first MOS transistor in the stage closest to said output terminal; a first clock signal generating means (12) for generating a first clock signal ( 1A or  1B ), and supplying said first clock signal to another terminal of said first capacitor (C 1 , C 3 , C 5 , C 7 , or C 9 ) in each stage; and a second clock signal generating means (14 or 16) for generating a second clock signal ( 2A or  2B ) and supplying said second clock signal to another terminal of said second capacitor (C 2 , C 4 , C 6 , C 8 , or C 10 ) in each of said plurality of stages; wherein in each of said plurality of stages, the source of said MOS transistor is electrically connected to the well in which said first MOS transistor is formed; and the wells of said plurality of stages are electrically insulated from each other, characterized in that : each of said plurality of stages has a second MOS transistor (Q 2 , Q 4 , Q 6 , Q 8 , or Q 10 ) having a drain connected to said source of said first MOS transistor, a source connected to said gate of said first MOS transistor, and a gate connected to said drain of said first MOS transistor; and said second clock signal ( 2A or  2B ) is in an off state during a predetermined period in which said first clock signal ( 1A or  1B ) is in an on state, and said off state period of said second clock signal is shorter than said on state period of said first clock signal. A semiconductor booster circuit according to Claim 1, characterized in that said second clock signal ( 2A or  2B ) has a larger amplitude (Vhh) than said power supply voltage (Vdd). A semiconductor booster circuit according to Claim 1 or 2, characterized in that : the wells of said plurality of stages are N-type wells formed in a semiconductor substrate, and are electrically insulated from each other; and said first MOS transistors of said plurality of stages are P-channel MOS transistors formed in said N-type wells, respectively. A semiconductor booster circuit according to any one of Claims 1-3 characterized in that : said first clock signal comprises first first and second first clock signals ( 1A and  1B ) which are in opposite phase; said second clock signal comprises first second clock signal and second second clock signal ( 2A and  2B ), said first second clock signal ( 2A ) is in an off state only at a predetermined period when said first first clock signal ( 1A ) is in an on state, and said second second clock signal ( 2B ) is in an off state only at a predetermined period when said first second clock signal ( 2A ) is in an on state; said first first clock signal ( 1A ) is supplied to another terminal of said first capacitor (C 1 ) in a first stage; said first second clock signal ( 2A ) is supplied to another terminal of said first capacitor (C 3 ) in a second stage; said second first clock signal ( 1B ) is supplied to another terminal of said second capacitor (C 2 ) in said first stage; and said second second clock signal ( 2B ) is supplied to another terminal of said second capacitor (C 4 ) in said second stage. A semiconductor booster circuit according to any one of Claims 1-4, characterized in that said plurality of stages are divided into at least two groups; and said first MOS transistors included in each group are formed in a well electrically insulated from another well in which said first MOS transistors included in another group are formed.

Inventors: SAWADA KIKUZO, SUGAWARA YOSHIKAZU, SAWADA, KIKUZO, SUGAWARA, YOSHIKAZU, SAWADA, KIKUZO, C/O NIPPON STEEL CORP., SUGAWARA, YOSHIKAZU, C/O NIPPON STEEL CORP.
Applicants: NIPPON STEEL CORP, NIPPON STEEL CORPORATION
Application year: 1995
Main classification: H02M3
IPC codes: H02M3