Silicon on insulating substrate and manufacturing method for same

Abstract: A first silicon single crystal substrate and a second silicon single crystal substrate are bonded together and the first silicon single crystal substrate is formed thin as an SOI layer. An insulation film is buried in portions of the bonding surface of one of the two silicon single crystal substrates, and in addition, a polycrystal silicon layer is formed on the bonding surface of the silicon single crystal substrate on the side into which the insulation film is buried.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates to a Silicon On Insulating (SOI) substrate and its method of manufacture, and in particular, relates to an SOI substrate that is useful in a power IC, and its method of manufacture. 2. Description of the Related Art: When monolithically integrating high-voltage vertical power elements and control circuit elements having current routes from the front to rear surface of a silicon substrate, partial SOI substrates are used that have been treated so as to allow the formation of only the control circuit elements on the SOI layer. This type of partial SOI substrate is disclosed in Japanese patents laid-open No. 29353/92 and No. 82138/91. Fig. 1 shows a sectional view of the progression of steps in a manufacturing method of SOI substrates (to be refered to as "the first example of the prior art") disclosed in Japanese patent laid open No. 29353/92 or in "Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs", pages 119 - 123; "A WAFER BONDED SOI STRUCTURE FOR INTELLIGENT POWER ICs" from T. Ohoka et al. First, as shown in Fig. 1a, a photoresist is formed by photolithography in a prescribed pattern on one main surface of an n + -type silicon single crystal substrate 4. This photoresist is used as a mask to form a shallow step by, for example, an ion etching method, and an SiO 2 insulation film 2 is formed by a method such as thermal oxidation or low-temperature chemical vapor deposition (CVD). Next, as shown in Fig. 1b, the protruding step portion of the insulation film 2 is removed by means of grinding-polishing or etching, and the exposed surface of the n + -type silicon single crystal substrate 4 and the insulation film 2 are leveled. The level surface obtained by the above-described steps is bonded to one main surface of an n - -type silicon single crystal substrate 1 and subjected to heat treatment to obtain a single firmly bonded compound substrate (Fig. 1c). Next, the n - -type silicon single crystal substrate 1 is ground and polished as far as the Y-Y plane shown in Fig. 1c to make the silicon substrate 1 a desired thickness as well as to level its surface. Next, an insulation film is formed on this leveled surface, the insulation film is patterned by means of photoetching, and using this film as a mask, alkali etching is carried out to form isolation grooves for isolation, thereby both isolating a vertical power element formation zone 6 and a control circuit element formation zone 7 and dividing the silicon single crystal substrate 1 of control circuit element formation zones 7 into silicon single crystal islands 8. Next, an insulation film 9 composed of, for example SiO 2 , is formed across the entire surface of the n - -type silicon single crystal substrate 1 by thermal oxidation or low-temperature CVD, following which a polycrystal silicon layer 10 is formed by CVD. The polycrystal silicon layer 10 and insulation film 9 on the substrate main surface are next removed by grinding-polishing or etching, leaving the isolation grooves covered by the insulation film 9 and polycrystal silicon film 10 to produce an SOI substrate with insulated and isolated element formation zones (Fig. 1d). Next, as another example of the prior art to be referred to hereinbelow as "the second prior art example," explanation is given with reference to Fig. 2 regarding the partial SOI substrate disclosed by Japanese patent laid-open No. 82138/91. First, as shown in Fig. 2a, a prescribed portion of one main surface of an n - -type silicon single crystal substrate 1 is oxidized by a selective oxidation method to form a LOCOS oxide film 11. Next, as shown in Fig. 2b, on the side of the silicon substrate 1 on which the LOCOS oxide film has formed, epitaxial growth of silicon is carried out by CVD to form an n + -type silicon single crystal layer 14 on the portion of the main surface of the n - -type silicon single crystal substrate 1 not covered by the LOCOS oxide film 11, and a polycrystal silicon layer 3 is formed on the LOCOS oxide film 11. Next, a mechanochemical grinding method is employed to grind as far as the X-X plane to make the surfaces of the n + -type silicon single crystal layer 14 and the polycrystal silicon layer 3 a single level plane. Next, as shown in Fig. 2c, an n + -type silicon single crystal substrate 4 is bonded to the flat plane of the n + -type silicon single crystal layer 14 and the polycrystal silicon layer 3 formed on the main surface of the n - -type silicon single crystal substrate 1, and a heat process is carried out to obtain a single compound substrate. Finally, as shown in Fig. 2d, the surface of the n - -type silicon single crystal substrate 1 is ground and polished as far as the Y-Y plane shown in Fig. 2c to produce a level surface, following which, by diffusing p-type impurities at high concentration at prescribed locations to form p + -type diffusion layers 12, a vertical power element formation zone 6 and a control circuit element formation zone 7 are isolated and the silicon single crystal substrate 1 of the control circuit element formation zone 7 is divided into silicon single crystal islands 8. In the first example of the prior art described hereinabove, silicon single crystal and silicon oxide film (or silicon nitride film) are mixed on the bonding surface of an SOI substrate, and in the second example of the prior art, silicon single crystal and polycrystal silicon are mixed on the bonding side of an SOI substrate. When leveling a surface in which differing substances are mixed in this way, suppressing variations in surface level to less than 100 Å is extremely difficult using current grinding or etching technology. For this reason, insufficient flatness in the bonding surface may give rise to voids in the bonded plane, and as a consequence, there is the problem that peeling may originate from the vicinity of these voids during subsequent heat treatments, thereby causing the vertical power elements to be inoperable. Furthermore, EP-A-0 553 857 discloses a process for preparing a semiconductor substrate comprising a step of porousifying a silicon monocrystalline substrate in form of a porous layer, a step of making a silicon monocrystalline thin film to epitaxially grow on a surface of the porous layer, a step of oxidizing the surface of the epitaxial grow layer, a step of forming a deposited film on the oxidized surface, thereby obtaining a first substrate, a step of closely contacting the deposited film of the first substrate to a second substrate, a step of heat treating the closely contacted substrate and a step of selectively etching the porous layer. US-A-5,138,421 discloses a semiconductor substrate comprising a first semiconductor layer, an insulation layer formed on the first semiconductor layer, a buffer layer formed on the insulation layer having at least one of getter ability and layer distortion buffering ability, and a second semiconductor layer formed on the buffer layer. SUMMARY OF THE INVENTION The object of the present invention is to improve the evenness of a bonding surface in which differing substances are mixed to provide a highly reliable SOI substrate having no voids in its plane of bonding, and to provide a manufacturing method for such an SOI substrate. To achieve the above object there is provided a SOI substrate according to claim 1. A method for manufacturing this SOI substrate is disclosed in claim 2. The dependent claim is related to a further advantageous aspect of the present invention. An SOI substrate manufacturing method is provided comprising: a first step in which a buried insulation film is formed in portions of one main surface of the first or the second silicon single crystal substrate; a second step in which the surface of silicon single crystal on a main surface of a silicon single crystal substrate into which the insulation film is buried and the surface of the insulation film are made a level surface along the same plane; a third step in which a polycrystal silicon layer is formed on the leveled surface. Through the above-described construction, minute unevenness resulting when leveling a surface in which a silicon single crystal is mixed with an insulation film can be absorbed in a polycrystal silicon layer, and by grinding this polycrystal silicon layer, an extremely even surface can be obtained. In addition, because lower resistivity can be achieved through prior introduction of impurities or through diffusion of impurities from either or both silicon single crystal substrates to a polycrystal silicon layer sandwiched between silicon single crystal substrates, it is possible to ensure that vertical power elements are virtually unaffected by the interposition of a polycrystal silicon layer, and it is possible to maintain the reliability of an SOI substrate while forming power elements with required characteristics. The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate an example of a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1a to 1d are sectional views illustrating the process of the SOI substrate manufacturing method of the first example of the prior art; Figs. 2a to 2d are sectional views illustrating the process of the SOI substrate manufacturing method of the second example of the prior art; Figs. 3a to 3f are sectional views illustrating the process of an SOI substrate manufacturing method according to the third example; Figs. 4a and 4b are sectional views illustrating the process of the SOI substrate manufacturing method according to the fourth example; Figs. 5a and 5b are sectional views illustrating the process of the SOI substrate manufacturing method according to the fifth example; Figs. 6a to 6f are sectional views illustrating the process of the SOI substrate manufacturing method according to the sixth example; and Figs. 7a to 7c are sectional views illustrating the process of the SOI substrate manufacturing method according to an embodiment of the present invention. Figs. 3a to 3f are sectional views of the progression of manufacturing steps and illustrate the structure and manufacturing method of an SOI substrate according to the third example. First, a silicon substrate is prepared having a concentration of impurities that is considered to enable the desired characteristics of a device to be formed. For example, an n - -type silicon single crystal substrate 1 is prepared into which 10 14 /cm 3 - 10 15 /cm 3 of phosphorus has been introduced, and on one main surface of this substrate a silicon oxide film (not shown) of uniform film thickness is formed by thermal oxidation. Then, by applying photolithography or dry etching, a prescribed portion of the silicon oxide film is removed to expose the silicon single crystal surface of this portion, and using the silicon oxide film as a mask, the silicon single crystal is etched to form a shallow step. The oxidized film used as a mask is then removed, following which an insulation film 2 of uniform film thickness is formed over the surface into which the shallow step has been formed (Fig. 3a). This insulation film 2 may be a silicon oxide film (SiO 2 ) formed by such processes as thermal oxidation or low-temperature CVD, or may be a silicon nitride film (Si 3 N 4 ) formed by low-temperature CVD. The thickness of this insulation film 2 is of a degree suitable to bury the shallow step. The thickness of the substrate step and insulation film 2 is selected from a range between several 1000 Å and several µm according to the necessary isolation voltage. Next, as shown in Fig. 3b, the protruding step portion of the insulation film 2 is removed by grinding-polishing or by etching, and the exposed surface of the n - -type silicon single crystal substrate 1 and the surface of the insulation film 2 are made an approximately level surface, following which the step is further adjusted by using a selective grinding or etching method on either the silicon single crystal or the insulation film, or alternatively, by using a method that enables simultaneous grinding of both surfaces at the same speed. In either case, the surface is leveled such that the maximum surface irregularity over the wafer surface is of the order of several 100 Å. Next, as shown in Fig. 3c, a polycrystal silicon layer 3 is formed by a method such as CVD. The thickness of this polycrystal silicon layer 3 is ideally of an order of 1 -3 µm to allow covering of the aforementioned surface irregularities of an order of several 100 Å as well as to allow for necessary additional grinding and leveling. Next, the polycrystal silicon layer 3 is ground and leveled as far as the X-X plane, and an extremely even surface is formed in which surface irregularities are reduced to a maximum of approximately several tens of Å across the wafer surface. Next, to make the polycrystal silicon layer 3 conductive, impurities of a conduction type identical to that of the n - -type silicon single crystal substrate 1 are introduced into the polycrystal silicon layer by ion injection or impurity diffusion. Alternatively, impurities may also be introduced before grinding the polycrystal silicon layer 3. Next, as shown in Fig. 3d, one main surface of an n + -type silicon single crystal substrate 4 of n-type and having an impurity concentration of 10 18 /cm 3 , and the surface of an extremely even polycrystal silicon layer 3 formed on a main surface of an n - -type silicon single crystal substrate 1 are given a hydrophilic treatment, following which the two hydrophilically treated surfaces are bonded together and heat processed for two hours at 1100 - 1200°C. In this way, a single, firmly bonded compound substrate can be obtained. Because the introduction of impurities to the polycrystal silicon layer 3 is brought about by heat diffusion from the n + -type silicon single crystal substrate 4, which has a high impurity concentration, both during the heat treatment following bonding and during the heat treatment in subsequent device-forming processes, it is possible to omit special steps such as ion injection or impurity diffusion for introducing impurities into the polycrystal silicon layer 3 before bonding. The other main surface of the n - -type silicon single crystal substrate 1 is next ground and polished as far as the Y-Y plane to obtain an even surface while leaving the thickness necessary for an SOI layer. Next, a silicon oxide film (not shown) is formed in a uniform thickness by thermal oxidation or CVD, and patterning is carried out to remove the silicon oxide film at prescribed locations. This oxide film is used as a mask for forming isolation grooves 5 for element isolation by alkali etching or reactive ion etching (RIE), thereby isolating the vertical power element formation zone 6 and control circuit element formation zone 7 and dividing the silicon single crystal substrate 1 of the control circuit element formation zone 7 into silicon single crystal islands 8. The silicon oxide film used as a mask is then removed (Fig. 3e). Next, an insulation film 9 composed of SiO 2 is formed over the entire surface of the silicon single crystal substrate 1 by such methods as thermal oxidation or low-temperature CVD, following which a polycrystal silicon layer 10 is formed by CVD. The polycrystal silicon layer 10 and insulation film 9 on the substrate surface are then removed by grinding-polishing or etching such that the isolation grooves 5 are filled in with the insulation film 9 and polycrystal silicon layer 10 to obtain an SOI substrate in which each element formation zone is insulated and isolated (Fig. 3f). Figs. 4a and 4b are sectional views of the progression of steps illustrating the fourth example. A silicon oxide film approximately 500 Å thick is formed by a method such as thermal oxidation on an n - -type silicon single crystal substrate 1 having a phosphorus concentration of the order of 10 14 /cm 3 - 10 15 /cm 3 , following which a silicon nitride film (neither film being shown) approximately 2500 Å thick is formed by CVD. After patterning the silicon nitride film, a LOCOS oxide film 11 is formed by steam thermal oxidation, and the silicon nitride film used as an oxide mask is removed (Fig. 4a). The protruding LOCOS oxide film 11 portions are then removed by polishing and grinding or etching to expose part of the surface of the n - -type silicon single crystal substrate 1. The exposed surface of the silicon single crystal and the surface of the LOCOS oxide film 11 are further leveled such that surface irregularities across the surface of the wafer are reduced to a maximum of several 100 Å (Fig. 4b). In addition, before thermal oxidation, the portion of the silicon substrate in which the LOCOS oxide film 11 is to be formed can also be slightly excavated to reduce dead space due to bird's beak. Finally, the same processes as those shown in Figs. 3c to 3f are applied to obtain an SOI substrate of the present example. Figs. 5a and 5b are sectional views showing the progression of steps illustrating the manufacturing method of an SOI substrate according to the fifth example. The bonded substrate shown in Fig. 3d is ground and polished as far as the Y-Y plane to obtain a compound substrate having a leveled surface as shown in Fig. 5a. Next, a photolithography method is applied to form a photoresist pattern which is used as a mask to inject boron at high concentration to form p + -type isolation areas 12 (Fig. 5b). These isolation areas 12 both isolate the vertical power element formation zone 6 and the control circuit element formation zone 7 as well as divide the silicon single crystal substrate 1 in the control circuit element formation zone 7 into silicon single crystal islands 8. The fifth example may be applied in cases allowing low isolation voltage between the vertical power element formation zones 7 and the control circuit element formation zones, and by omitting isolation processes involving isolation grooves 5 such as those in the third example, this example enables a simplification of the manufacturing process. Figs. 6a-6f are sectional views of the progression of steps illustrating the manufacturing method according to the sixth example. A silicon oxide film (not shown) of uniform thickness is first formed across a main surface of an n - -type silicon single crystal substrate 1 by, for example, thermal oxidation. Photolithography method and dry etching are then employed to remove the silicon oxide film at prescribed portions and expose the silicon single crystal surface at these prescribed portions, following which the silicon oxide film is used as a mask to etch the silicon single crystal and form shallow steps. Next, photolithography is applied to form a photoresist mask through which boron is ion-injected at an energy of 50 keV and a dosage of 2.5 x 10 14 /cm 2 to form p + -type diffusion layers 12a (Fig. 6a). Next, an insulation film 2 composed of a silicon oxide film or a silicon nitride film is formed over the entire surface by thermal oxidation or low-temperature CVD, and the protruding step portion of the insulation film 2 is removed by a method such as grinding-polishing or etching, after which the surface is further subjected to a leveling process to produce an even surface having surface irregularities no greater than several 100 Å over the wafer surface (Fig. 6b). Next, as shown in Fig. 6c, a polycrystal silicon layer 3 is formed by a method such as CVD and impurities are introduced as necessary. Mechanical and chemical grinding is then applied to grind and level the polycrystal silicon layer 3 as far as the X-X plane and to reduce surface irregularities within the wafer surface to a maximum of several tens of Å. Next, as shown in Fig. 6d, one main surface of an n + -type silicon single crystal substrate 4 having an impurity concentration on the order of 10 18 /cm 3 and the extremely even surface of the polycrystal silicon layer 3 formed on the n - -type silicon single crystal substrate 1 are bonded together and subjected to heat treatment at 1100 - 1200°C for about two hours to obtain a single firmly bonded compound substrate. The other main surface of the n - -type silicon single crystal substrate 1 is next ground and polished as far as the Y-Y plane and leveled to leave a silicon single crystal with an SOI layer thickness of about 20 µm. A photoresist pattern is then formed by photolithography, and this is used as a mask to ion-inject boron at an energy of 50 keV and a dosage of 5 x 10 15 /cm 2 to form p + -type diffusion layers 12b (Fig. 6e). A heat treatment is then carried out to join the upper and lower diffusion layers 12a, 12b and form p + -type isolation zones 12 which both isolate the vertical power element formation zone 6 and control circuit element formation zone 7 as well as divide the silicon single crystal substrate 1 in the control circuit element formation zone 7 into silicon single crystal islands 8 (Fig. 6f). This example is ideal for applications in which isolation cannot be achieved using the isolation technique of the fifth example (Fig. 5) due to thickness of the SOI layer. Furthermore, the heat treatment for joining the upper and lower p + -type diffusion layers 12a, 12b may also be substituted by the heat treatment of the element forming process. Embodiment: Figs. 7a - 7c are sectional views of the progression of steps illustrating the manufacturing method according to an embodiment of the present invention. Using the same techniques as for the third example, an n - -type silicon single crystal substrate 1 having a buried insulation film 2 in portions is formed as shown in Fig. 3b, and after applying a leveling process, impurities of the same conductive type as the substrate are introduced into the surface of the n - -type silicon substrate by a method such as ion injection at a concentration greater than that of the substrate concentration to form an n + -type diffusion layer 13 (Fig. 7a). Next, using SiH 4 as the raw material gas, silicon is grown by CVD with an interior furnace temperature of 600-700°C to form a nondoped polycrystal silicon layer 3a (Fig. 7b). The nondoped polycrystal silicon layer 3a is then ground to the X-X plane to level the surface such that maximum surface irregularities are several tens of Å. A main surface of the n + -type silicon single crystal substrate 4 and the surface of the extremely even polycrystal silicon layer formed on a main surface of the n - -type silicon single crystal substrate 1 are then bonded together and subjected to heat treatment at 1100-1200°C to obtain a single firmly bonded compound substrate. At this time, the impurities of the n + -type diffusion layer 13 formed on the surface of the silicon single crystal substrate 1 and the impurities of the n + -type silicon single crystal substrate 4 diffuse into the nondoped polycrystal silicon layer 3a and convert this layer into an n + -type polycrystal silicon layer 3b and an n-type polycrystal silicon layer 3c (Fig. 7c). In addition, the impurities of the n + -type diffusion layer 13 formed on the surface of the n - -type silicon single crystal substrate 1 and the impurities of the n + -type silicon single crystal substrate 4 are not only introduced into the polycrystal silicon by the above-described bonding heat treatment, but also by the heat treatment during subsequent device forming processes. The compound substrate is next ground and polished to the Y-Y plane (Fig. 7c), and isolation zones are further formed to obtain an SOI substrate according to the present embodiment. As impurities for forming the n + -type diffusion layer 13, phosphorus, arsenic (As), and antimony (Sb) may be used. Moreover, instead of forming a high-concentration impurity diffusion layer on the substrate surface on the n - -type silicon single crystal substrate 1 side, an n-type impurity may be introduced into the substrate surface on the n + -type silicon single crystal substrate 4 side. Although explanation has been presented in the foregoing description regarding the embodiment, the present invention is not limited to this embodiment, and various changes may be made without departing from the scope of the invention. For example, although in the embodiment an insulation film is buried and a polycrystal silicon layer is formed on the n - -type silicon single crystal substrate side, these may also be formed on the n + -type silicon single crystal substrate side.

Claims: A Silicon On Insulating substrate wherein a first silicon single crystal substrate (1) and a second silicon single crystal substrate (4) are bonded to each other, said first silicon single crystal substrate being formed as a Silicon On Insulating layer, and wherein an insulating film (2) is formed in portions of the surface of the bonding side of either one of said two silicon single crystal substrates characterized in that a polycrystalline silicon layer (3) is formed on the surface of the bonding side of the silicon single crystal substrate into which said insulating film is formed; and a high-concentration impurity diffusion layer (13) of the same conduction type as that of the silicon single crystal substrates is formed at least in a portion of either one of said two silicon single crystal substrates that contacts said polycrystalline silicon layer and that does not oppose said insulating film. A Silicon On Insulating substrate manufacturing method comprising: a first step in which an insulating film (2) is formed into portions of one main surface of a first silicon single crystal substrate (1) or a second silicon single crystal substrate (4); a second step in which the surface of the silicon single crystal substrate into which said insulating film is formed, that is, the surface on which the silicon and said insulating film exist, is made an extremely flat surface; a third step in which a polycrystalline silicon layer (3) is formed on said leveled surface; a fourth step in which the surface of said polycrystalline silicon layer is leveled by grinding and polishing; a fifth step in which the leveled surface of said polycrystalline silicon layer is bonded with one main surface of the one of the first and second single crystal substrate into which an insulation film is not formed, and the two substrates are subjected to a heat treatment to unify the two substrates; and a sixth step in which the other main surface of said silicon single crystal substrate into which said insulating film is formed, is grounded and polished to a thickness necessary for a Silicon On Insulating layer; further comprising either an additional step between said second step and said third step in which impurities of the same conduction type as the conduction type of the silicon single crystal substrate are introduced at high concentration into the surface of the silicon single crystal substrate into which said insulation film is formed, on the side into which said insulation film is formed at least in a portion that contacts said polycrystalline silicon layer and that does not oppose said insulating film, or, an additional step preceding said fifth step in which impurities of the same conduction type as the silicon substrate conduction type are introduced at high concentration into at least portions contacting said polycrystalline silicon layer and not opposing said insulating film of the bonding surface of the silicon single crystal substrate into which said insulating film is not formed. A Silicon On Insulating substrate manufacturing method according to claim 2 further comprising a step, between said third step and said fourth step or between said fourth step and said fifth step, in which impurities of the same conduction type as the conduction type of the first and second silicon single crystal substrates are introduced into said polycrystalline silicon layer.

Inventors: HAMAJIMA TOMOHIRO, KOBAYASHI KENYA, OKONOGI KENSUKE, HAMAJIMA, TOMOHIRO, C/O NEC CORPORATION, KOBAYASHI, KENYA, C/O NEC CORPORATION, OKONOGI, KENSUKE, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1995
Main classification: H01L27
IPC codes: H01L21