EXTREME LEVEL CIRCUIT

Abstract: An extreme level circuit for determining an extreme level off a plurality of input levels includes a plurality of independent parallel branches (T4+M2+M5, T5+M3+M6) with intercoupled output terminals (MAX) from which the extreme level can be taken. Each branch has an input terminal (INA, INB) for receiving a respective one of the input levels, and includes a separate distortion compensation circuit (M2+M5, M3+M6) which is independent of the distortion compensation circuits of the other parallel branches.

Description: Extreme level circuit. The invention relates to an extreme level circuit, i.e. a circuit for detecting an extreme level (maximum or minimum value) of a plurality of input signals. EP-A-0,430,707 describes such an extreme level circuit for detecting an extreme level of two input signals. Starting from a well-known circuit comprising a pair of differential transistors wim interconnected emitters from which the output extreme level can be taken, an improvement is presented to prevent distortions from occurring. This improvement comprises a pair of bias generating circuits which are cross-connected to the collectors of the differential transistors. This cross-connection makes it very difficult to expand the circuit to a circuit suitable for determining die extreme level of more than two input signals. It is, inter alia, an object of the invention to provide an extreme level circuit which also prevents distortions from occurring but which can easily be expanded to a circuit suitable for determining the extreme level of more than two input signals. To this end, one aspect of the invention provides an extreme level circuit as defined in claim 1. Advantageous embodiments are defined in the dependent claims. The extreme level circuit for determining an extreme level of a plurality of input levels in accordance widi the present invention includes a plurality of independent parallel branches wim intercoupled output terminals from which the extreme level (maximum or mmimum) can be taken. Each branch has an input terminal for receiving a respective one of the input levels, and includes a separate distortion compensation circuit which is independent of the distortion compensation circuits of the other parallel branches. It is thus easily possible to add further independent parallel branches in order to be able to calculate the extreme value of as many input values as is desired. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. In the drawings: Fig. 1 shows a first embodiment of an extreme level circuit in accordance with the present invention; Fig. 2 shows a second embodiment of an extreme level circuit in accordance with the present invention; In Fig. 1, input signals INA, INB and INC are applied to me base terminals of NPN transistors T4, T5 and T6, respectively. The emitters of the transistors T4, T5 and T6 are interconnected, connected to ground thru a current source J3 which pulls a current I, and connected to an output terminal which delivers the maximum value of the input signals INA, INB and INC. The collectors of the transistors T4, T5 and T6 are connected to a positive supply line thru respective PMOSFETs M2, M3 and M4, which FETs form a current mirror with an input FET Ml whose gate and drain are connected to ground thru a current source J2 which pulls a current 1/3. Further, the emitters of die transistors T4, T5 and T6 are connected to the positive supply line thru respective PMOSFETs M5, M6 and M7, whose respective gate terminals are connected to d e collectors of the transistors T4, T5 and T6, respectively. In this circuit, the maximum current thru the transistors T4, T5 and T6 is limited by the current sources M2, M3 and M4. So the current mru the transistors T4, T5 and T6 will not exceed 1/3. Suppose that the base of transistor T5 receives me largest of the three input signals INA, INB and INC. In this case, me current thru transistor T5 will be 1/3, while the currents thru the transistors T4 and T6 will be lower, determined by their respective base-emitter voltages Vbe(T4) = INA - (INB - Vbe(T5)) and Vbe(T6) = INC - (INB - Vbe(T5)). Consequently, the series-FETs M2 and M4 will go into saturation, so that me gate-source voltages of the corresponding parallel-FETs M5 and M7 will be so low that these parallel-FETs M5 and M7 are switched off. The parallel-FET M6 will convey a current which is given by the current I thru the current source J3 minus me current 1/3 thru the transistor T5 and minus the collector currents of me transistors T4 and T6. As a result of the constant collector current mru the transistor T4, T5, T6 which (from time to time) receives the largest of the three input signals INA, INB, INC, its δVbe will be small, so that no significant amplitude distortion will be shown. For M2, M3 and M4 MOS (PMOS) transistors were chosen, because if the current thru the NPN transistors is lower than the current source feeding its collector, the current source pulls the collector node to the supply voltage. Wim PNP transistors instead of MOSFETs, mis would lead to big substrate currents when the current source saturates, and me PNPs would only slowly come out of saturation which would make the circuit less suitable for high frequencies. In principle, also FETs could be used for the transistors T4, T5 and T6, but bipolar transistors can more easily be matched. For M5, M6 and M7 MOS transistors are chosen because the gate-source capacitance of a MOS transistor is smaller than me corresponding base-emitter capacitance of corresponding bipolar PNP transistors which are thus less suitable for high frequencies. In Fig. 2, two parallel branches of another maximum detection circuit are shown; extension to any desired number of parallel branches is easily possible. Input signal levels INI, IN2 are applied to base terminals of NPN transistors Nl and N3, respectively, whose collectors are connected to a positive supply line and whose emitters are connected to ground thru respective current sources II, 12, and connected to respective base terminals of NPN transistors N2, N4. Emitters of the transistors N2, N4 are connected to an output supplying me maximum value MAX of me input signals. Collectors of the transistors N2, N4 are connected to meir respective base terminals thru respective PNP current mirrors PI, P2 and P3, P4. This circuit mus comprises in each branch two base-emitter junctions in series (Nl, N2 and N3, N4). If me current thru the transistor N2 (N4) increases, the additional current is mirrored by me current mirror PI , P2 (P3, P4) so that me current thru the transistor Nl (N3) decreases, as me sum of the current to me emitter of the transistor Nl (N3) and the current to the transistor P2 (P4) is constant due to the constant current source II (12). Consequently, a current increase diru me transistor N2 (N4) is compensated by an identical current decrease dim the transistor Nl (N3), and as a result, a Vbe modification of me transistor N2 (N4) is compensated by an identical Vbe modification of the transistor Nl (N3). Any distortions caused by mese Vbe modifications as set out in detail in EP-A- 0,430,707 are thus automatically compensated for. It should be noted that the above-mentioned embodiments illustrate rather than limit me invention, and mat those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In me claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The embodiments of Figs. 1, 2 show maximum detection circuits; minimum detection circuits can easily be obtained therefrom by interchanging NPN and PNP transistors etcetera. Alternatively, a minimum can be calculated by taking me inverted maximum of inverted input signals, which causes no additional components in a balanced environment in which at several stages both an output and an inverted output and bom an input and an inverted input are available. The circuit of Fig. 2 provides tne advantage mat it can be build in pure bipola manufacturing processes. The extreme level circuits according to me present invention can very advantageously be used in luminance transient improvement circuits.

Claims: Claims: 1. An extreme level circuit for determining an extreme level of a plurality of input levels, the extreme level circuit comprising a plurality of independent parallel branches (T4+M2+M5, T5+M3+M6; N1 +N2+P1 +P2+I1, N3+N4-I-P3+P4-I-I2) with intercoupled output terminals (MAX) from which the extreme level can be taken, each branch having an input terminal (INA, INB; INI, IN2) for receiving a respective one of the input levels, and including a separate distortion compensation circuit (M2+M5, M3+M6; P1 +P2+I1, P3+P4+I2) which is independent of me distortion compensation circuits of the omer parallel branches. 2. An extreme level circuit as claimed in claim 1, wherein each branch comprises first (Nl, N3) and second (N2, N4) bipolar transistors wim base-emitter junctions connected in series, a current mirror (P1+P2, P3+P4) having an input (PI, P3) connected to the collector of me second transistor (N2, N4) and an output (P2, P4) connected to a connection point of me base-emitter junctions, and a constant current source (II, 12) for furnishing a constant sum current to me first transistor (Nl, N3) and me output of die current mirror (P2, P4), the input terminal (INI, IN2) being connected to the base of the first transistor (Nl, N3) and me output terminal (MAX) being connected to me emitter of the second transistor (N2, N4). 3. An extreme level circuit as claimed in claim 1, wherein each branch comprises: a first transistor (T4, T5, T6) having a control terminal coupled to me input terminal (INA, INB, INC), a first main terminal coupled to the output terminal (MAX), and a second main terminal; a second transistor (M5, M6, M7) having a control terminal coupled to the second terminal of the first transistor (T4, T5, T6), a first main terminal coupled to a supply terminal, and a second main terminal coupled to the first main terminal of the first transistor (T4, T5, T6); and current source means (M2, M3, M4) coupled to the second terminal of the first transistor (T4, T5, T6). 4. An extreme level circuit as claimed in claim 3, wherein said constant current source means comprises: a first current source transistor (M2, M3, M4) having a control terminal, a first main terminal coupled to me supply terminal, and a second main terminal coupled to me second terminal of the first transistor (T4, T5, T6); a second current source transistor (Ml) having a control terminal coupled to the control terminal of me first current source transistor (M2, M3, M4), a first main terminal coupled to me supply terminal, and a second main terminal coupled to its control terminal and to a constant current source (J2). 5. An extreme level circuit as claimed in claim 4, wherein said first (M2, M3, M4) and second (Ml) current source transistors are MOSFETs. 6. An extreme level circuit as claimed in claim 3, wherein said first transistor (T4, T5, T6) is a bipolar transistor. 7. An extreme level circuit as claimed in claim 3, wherein said second transistor (M5, M6, M7) is a MOSFET.

Inventors: LEISTRA WIETZE BEREND, VAN LAMMEREN JOHANNES PETRUS M, LEISTRA, WIETZE, BEREND, VAN LAMMEREN, JOHANNES, PETRUS, MARIA
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1995
Main classification: G01R19
IPC codes: G01R19