Ball grid array package for an integated circuit and method of reducing ground bounce

Abstract: A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss traces. Other vias electrically couple Vdd and IC signals from Vdd and signal traces on the upper and lower surfaces of the BGA package. Solder balls connected to the BGA package lower traces are soldered to matching traces on a system PCB. The periphery Vss traces, vias and solder balls help maintain current flow in the BGA Vss plane. In addition to providing a low impedance current return path (and thus reduced ground bounce and reduced IC signal delay time) for current sunk by an IC within the BGA package, the BGA Vss plane provides heat sinking. A four-layer BGA package further includes a BGA Vdd plane located intermediate the BGA Vss plane and the traces on the lower surface of the BGA package. Fabricated from two pieces of symmetrical printed circuit board material, this embodiment reduces ground bounce for IC current sourcing as well as IC current sinking, and provides approximately a 100% improvement in thermal dissipation as compared to prior art BGA packages.

Description: The invention relates to a ball grid array package according to the preamble of claim 1 and to a method of reducing ground bounce according to the preamble of claim 13. This invention thus relates to packaging integrated circuits, and more particularly to improving thermal and electrical characteristics in ball grid array packaging for high speed integrated circuits. Integrated circuits ("ICs") are fabricated on a semiconductor substrate that is mounted within a typically epoxy or ceramic overmold for later mounting on a printed circuit board ("PCB"). As fabrication techniques improve, ICs tend to include circuits with increased complexity and increased number of input and output leads ("pinouts"). Further, as more transistors are fabricated on an IC die of a given size, dissipating heat from the IC becomes a greater challenge. One packaging system for providing an IC with a large number of pinouts in a relatively small package area is known as the ball grid array ("BGA") package. Figure 1 depicts a standard two-layer BGA mounting system, similar to the so-called OMNI™ system promoted by Motorola, Inc. In this system, a BGA package 2 includes a double-sided copper clad printed circuit board ("PCB") 4 with conductive and/or thermal vias 6A, 6B, 6C connecting upper BGA package conductive traces 8A, 8B, 8C to lower BGA package conductive traces 10A, 10B, 10C. The 8A traces and the 8B traces may each be donut-shaped, as may the corresponding 10A and 10B traces. The various vias preferably are identical and may be referred to interchangeably as conductive or thermal vias. The BGA package further includes the IC die 12 to be packaged, and a plurality of meltable solder balls 14A, 14B, 14C in contact with the lower conductive traces 10A, 10B, 10C. The upper and lower BGA package traces 8A, 8B, 8C, 10A, 10B, 10C are typically formed by etching the copper clad upper and lower surfaces of BGA PCB 4. An overmold, shown in phantom as 16, encapsulates and thus protects the IC die 12. Overmold 16 could, of course, be sized to extend over a greater or lesser portion of the upper surface of BGA package 2 than what is depicted in Figure 1. Package 2 will eventually be soldered to a system printed circuit board ("PCB") 18, whose upper surface includes conductive traces 20A, 20B, 20C that will contact various of the solder balls 14A, 14B, 14C. Thus, while Figure 1 shows BGA package 2 and system PCB 18 spaced apart vertically, in practice the solder balls and the system PCB traces are placed in contact with one another, whereupon an infrared reflow process melts the solder balls. Upon melting, the solder balls electrically and mechanically join various of the BGA package traces 10A, 10B, 10C to various of the system PCB traces 20A, 20B, 20C. The various solder balls may be arrayed in a relatively dense matrix, with adjacent balls being spaced-apart horizontally 0.050" to 0.060" (1.3 mm to 1.5 mm). As a result, BGA package 2 can advantageously provide a dense pattern of pinout connections with IC 12. Those skilled in the art will appreciate that IC 12 may include various semiconductor devices such as bipolar or metal- oxide-semiconductor ("MOS") transistors, as well as effective resistor and capacitor components. These transistors and components will form one or more circuits that are typically coupled to an upper power source Vdd, and to a lower power source Vss (usually ground). Bonding wires such as 22, 24 make electrical connection from pads formed on IC 12 (not shown) to a BGA package trace or plane formed by etching the copper clad on the upper surface of BGA structure 2. Bond wire 22, for example, connects to a BGA package Vdd upper plane trace 8A that connects to a conductive via 6A, which connects to a BGA package Vdd lower plane trace 10A that connects to a solder ball 14A. On the underlying system PCB 18, one or more system PCB traces 20A couple to the Vdd power source that is connected to the system PCB 18. In similar fashion, one or more bond wires (not shown) will couple IC 12 to Vss on the system PCB 18. Similarly, bonding wire 24 is shown coupled to an upper signal BGA package trace 8B that is connected to vias 6B, to BGA package lower signal trace 10B, and signal solder balls 14B. On system PCB 18, system PCB traces 20B couple electrical signals to or from IC 12. Other bonding wires will also be present but are not shown for ease of illustration. Of course, IC 12 will generally be coupled by various bond wires, upper BGA package traces, vias, lower BGA package traces to various different signal solder balls, for contact with various system PCB 18 signal traces. As shown in Figure 1, the lower substrate surface of IC 12 is connected to a BGA package IC die Vss plane 8C, that connects through several vias 6C to a BGA package lower surface Vss plane 10C to which solder balls 14C are attached. As noted, Vss connections to IC 12 generally are also brought out through Vss IC pads, bond wires, traces, vias, traces and solder balls in a manner similar to what is described herein with respect to the connections for Vdd. The underlying system PCB 18 includes a system PCB Vss ground plane 20C that electrically connects to such Vss solder balls, including solder balls 14C. BGA package 2 is relatively economical to manufacture because PCB 4 may be a symmetrical and relatively inexpensive generic commodity. By symmetrical, it is meant that PCB 4 is manufactured with copper clad on the upper and lower surfaces of a typically epoxy glass core 22, commonly referred to as FR4 material. (It is from this copper clad that the upper and lower BGA package traces or planes 8A, 8B, 8C, 10A, 10B, 10C are formed.) Alternatively, core 22 may be fabricated from an adhesive-like resin commonly termed pre-preg. It is important that PCB 4 be sufficiently rigid so that the various solder balls will register properly for soldering to corresponding system PCB traces. As a result, the vertical thickness of core 22 in Figure 1 will typically be at least 0.02" to 0.03" (0.5 mm to 0.8 mm). Although the BGA configuration of Figure 1 has the advantage of being inexpensive to fabricate, it has several shortcomings. Specifically, BGA 4 does not provide a good signal plane for current surges into or out of IC 12, and does not do a good job of dissipating heat generated by IC 12. The relatively poor electrical and thermal performance associated with BGA structure 4 is especially apparent when IC 12 includes high density, high frequency digital circuitry. Essentially these performance shortcomings arise because the efficient system Vss and Vdd planes on PCB 18 are too far away from IC 12 to be truly effective. Thermally, although the system PCB Vss plane 20C can sink heat dissipated by IC 12 and down-conducted through vias 6C, the system PCB Vss plane is just too remote for good dissipation. The prior art configuration of Figure 1 has a thermal resistance  ja of about 35°C/W, which means that for an increase of one watt dissipation, the junction temperature of the IC die 12 will increase 35°C. As a result, IC 12 may overheat, or require bulky and relatively expensive heat sinking. Alternatively, IC 12 may have to be operated at a lower equivalent duty cycle to reduce dissipation, thus sacrificing IC 12 performance because of the poor thermal characteristics associated with prior art two-layer BGA packages. Electrically, the current paths from the system PCB Vdd plane 20A, up into IC 12, through the system Vss plane 20C, and vice versa, are simply too long. As will be described, these long path lengths can result in the Vdd and Vss potentials within IC 12 impermissibly varying in magnitude during current surges. What occurs is that an effective inductance L exists in series with the relatively long power supply current paths. Large mutual inductances may be present that force some transient surge ground current to return undesirably through IC 12, rather than through the system PCB planes. This IC 12 transient surge current flow can cause ground bounce and crosstalk between various circuits within IC 12. In addition, the effective inductance L can contribute to an undesirable time delay for signals propagating through IC 12. More specifically, an excessively long path between a signal node on the IC chip and a signal return ground plane increases the effective series inductance (L) therebetween. In the presence of current spikes through such path, the voltage at the Vss pad(s) and/or Vdd pad(s) within IC 12 can deviate or "bounce" from their nominal DC voltage. Consider, for example, the effect of a relatively long current return path for a high speed CMOS digital circuit fabricated within IC 12. The output of circuit typically will include a PMOS pull-up and an NMOS pull-down transistor coupled in series between Vdd and Vss. When outputting a digital "1", the NMOS transistor is off, and the PMOS transistor is on, and the circuit sources current from Vdd through the PMOS transistor to an output load coupled to Vss. When outputting a digital "0", the PMOS transistor is off, the NMOS transistor is on and sinks current from the output load. But when this CMOS circuit changes states from "1" to "0" or vice versa, for a brief interval the PMOS and NMOS transistors may both be simultaneously on due to imperfect switching. When both transistors are on during transitions a rapid change (or "spike") in current (di/dt) through the circuit can occur. In the presence of series inductance L, current spiking results in an L di/dt = dV/dt change or "bounce" in the voltage present at the Vdd and/or Vss pads on IC 12. Ground bounce results from this dV/dt for Vdd and/or Vss within IC 12. Such voltage bouncing within IC 12 is especially troublesome at "0" to "1" transitions because CMOS transistors exhibit less noise immunity margin for error near "0" voltage states as contrasted to "1" voltage states. For this reason, it is especially important that a low inductance impedance Vss path within IC 12 be maintained. In addition to producing overshoot and undershoot on output voltage waveforms, ground bounce can degrade digital switching reliability. This degradation occurs because any variations in Vdd or Vss within IC 12 can alter CMOS trip points. Generally, the configuration of Figure 1 will exhibit an output impedance between a signal output pad on IC 12 and Vss of about 250 Ω. A 250 Ω output impedance is undesirably high for matching to a system PCB that typically is characterized by an impedance in the 50 Ω to 75 Ω range. The resultant impedance mismatch contributes to overshoot and ringing on signals coupled from the BGA package to the system PCB. The configuration of Figure 1 also exhibits an effective series inductance of 12 nh to 15 nh, and an equivalent output shunt capacitance at a signal output pad of about 1.2 pF. As noted, the series inductance can produce overshoot and ringing in IC 12 signals, especially when a relatively light capacitive load is to be driven. Further, the series inductance and shunt capacitance associated with the two-layer BGA package of Figure 1 can undesirably delay a signal passing through IC 12 by several nanoseconds. If IC 12 includes high speed switching devices (e.g., wherein the operating frequency is greater than 30 MHz), a BGA package-imposed time delay of a few nanoseconds may be unacceptable. In summary, there is a need for a BGA package having improved thermal and electrical characteristics, especially for high speed digital ICs. To reduce ground bounce and enhance IC operating reliability, such BGA package should preferably exhibit approximately 50Ω output impelance and decreased effective series inductance. Further, it should preferably be possible to manufacture such a BGA package using generic symmetrical PCB materials. Known from US-A-4 739 448 is a ball grid array package for an integrated circuit comprising upper and lower layer package traces, a plurality of vertically arranged layers comprising a signal line layer, a ground layer, a power conductor layer and separating layers in between, and a plurality of vias each extending between and soldered to opposing surfaces of adjacent layers. The invention is defined in claims 1 and 13. In a first three-layer embodiment, the present invention provides a BGA package with a BGA Vss plane disposed between the upper and lower BGA package traces. Further, this embodiment also provides upper and lower BGA package Vss traces on the outer periphery of the BGA package, to help maintain a low impedance between an IC packaged with the three-layer embodiment, and the BGA Vss plane. This embodiment is three-layered in that there are traces at the upper surface of the BGA package, there is an inter-mediate BGA Vss plane, and there are traces at the lower surface of the BGA package. The additional BGA Vss plane preferably is a copper clad surface on a portion of PCB material from which the BGA package is fabricated. IC-generated heat is coupled from the BGA package IC die Vss trace through vias to the BGA Vss plane, through the lower portion of the same vias to the BGA package Vss trace on the lower surface of BGA package, as well as to a Vss plane on the underlying system PCB. The BGA Vss plane is closer to the IC than is the underlying system PCB, and thus performs an IC heat sinking function by lowering thermal resistance  ja . The BGA Vss plane also provides a closer Vss plane for sinking current output by the IC than is provided by the underlying PCB Vss plane. The presence of this closer Vss plane reduces series inductance to the IC, reduces ground bounce, at least for IC output signals transitioning from "1" to "0", and reduces time delay through the IC. While the closer Vss plane reduces series inductance, closer Vss plane proximity to the IC slightly increases shunt capacitance as seen by a BGA package upper surface trace to Vss. However, the slight increase in shunt capacitance appears beneficial in reducing noise seen by the IC. A more preferred embodiment of the present invention provides a four-layer BGA package that is similar to the above-described three-layer embodiment, except that a BGA Vdd plane is also provided intermediate the BGA Vss plane and the traces on the lower surface of the BGA package. This embodiment is preferred because it may be fabricated from two pieces of symmetrical printed circuit board material, and because it reduces ground bounce for "0" to "1", as well as for "1" to "0" IC output signal transitions. The BGA Vdd plane provides a plane that is relatively closer to the IC than is the underlying PCB Vdd plane, and reduces series inductance when the IC sources current, as in a "0" to "1" output signal transition. This "0" to "1" ground bounce improvement is in addition to the "1" to "0" current sinking improvement afforded by the BGA Vss plane, which also improves heat sinking. Because it provides an even number of planes, the four-layer embodiment is preferred for ease of fabrication. This embodiment may be manufactured using two pieces of symmetrical double clad PCB material, wherein the clad on each piece of material provides two planes. As such, this embodiment provides technical advantages in ease and economy of fabrication over a three layer embodiment. Further, when compared to a prior art two-layer BGA package, a four-layer embodiment according to the present invention reduces series inductance by about 50%, reduces the effective output impedance from about 250 Ω to about 50 Ω, and increases shunt capacitance to about 1.3 pF. When compared to a prior art two-layer BGA package, the four-layer embodiment reduces time delay through the packaged IC by about 2 ns, and improves thermal dissipation by about 50%. Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail, in conjunction with the accompanying drawings. FIGURE 1 is a sectional view of a conventional two-layer ball grid array configuration for packaging an integrated circuit, according to the prior art; FIGURE 2 is a sectional view of a three-layer ball grid array configuration for packaging an integrated circuit, according to the present invention; FIGURE 3 is a sectional view of a four-layer ball grid array configuration for packaging an integrated circuit, according to the present invention; FIGURE 4 is a computer simulation comparing voltage waveforms for the four-layer embodiment of Figure 3 and the two-layer embodiment for Figure 1, for a CMOS buffer integrated circuit. In a first three-layer embodiment shown in Figure 2, the present invention provides a BGA package 50 with a BGA Vss plane 60 disposed between the upper and lower BGA package traces 8A, 8B, 8C, 8C', and 10A, 10B, 10C, 10C'. Among these BGA package traces, the present invention adds upper and lower BGA package Vss traces 8C', 10C' on the outer periphery of the BGA package. This embodiment is three-layered in that there are traces 8A, 8B, 8C, 8C' at the upper surface of the BGA package, there is an intermediate BGA Vss plane 60, and there are traces 10A, 10B, 10C, 10C' at the lower surface of the BGA package. The embodiment of Figure 2 improves thermal dissipation performance and partially improves electrical performance in a BGA package when compared to the two-layer embodiment of Figure 1. These improvements result by providing a BGA Vss plane 60 relatively close to IC die 12, and by optionally providing outer Vss planes 8C', 10C' (and associated vias 6C' and outer solder balls 14C'). Outer planes or traces 8C', 10C' may be donut-shaped, and are coupled together by the BGA Vss plane 60, to which planes or traces 8C, 10C are also coupled. This coupling is affected by the vias 6C, 6C' which pass tightly through via-sized openings in plane 60 such that electrical (and thermal) contact results. By contrast, all other vias (e.g., 6A, 6B) pass through oversized openings in plane 60 that are sufficiently large as to not make electrical (or thermal) contact with the Vss plane 60. As was the case in Figure 1, an IC die 12 mounted within the BGA package has its substrate coupled to a BGA package IC die Vss trace or plane 8C on the upper surface of the BGA package. A plurality of vias 6C, 6C' electrically and thermally couple the BGA Vss plane 60 to the BGA package IC die Vss trace 8C, and to the outer periphery traces 8C', 10C' on the upper and lower BGA package surfaces. Vss solder balls couple the various Vss traces on the lower BGA package surface to corresponding Vss planes on an underlying system PCB. As in the prior art, Vdd solder balls couple the various Vdd and signal traces on the lower BGA package surface to corresponding traces and planes on the underlying system PCB. Vdd vias 6A and signal vias 6B also couple respective Vdd and signal traces 8A, 14A and 8B, 14B. It is understood that the BGA Vss plane 60 makes electrical contact with the Vss vias 6C, 6C', but not with the Vdd vias 6A or the signal vias 6B. Electrical connection with vias 6A, 6B is avoided by defining through openings in the BGA Vss plane 60 sufficiently large to permit vias 6A, 6B to pass through without contact between the outer wall of the via and the inner surface of the opening in plane 60. By contrast, the Vss vias 6C, 6C' pass through openings defined in plane 60 that will result in electrical contact. The additional BGA Vss plane preferably is a copper clad surface on a portion of PCB material from which the BGA package is fabricated. In Figure 2, BGA Vss plane may be either the lower copper clad on a piece of symmetrical printed circuit board material 52 whose core is shown as 56, or the upper copper clad on a piece of symmetrical printed circuit board material 54 whose core is shown as 58. Typically, core 56 and core 58 will typically have a combined thickness of at least 0.02" to 0.03" (0.5 mm to 0.8 mm) to provide rigidity for BGA package 50. In practice, core 56 may be relatively thin (e.g., 0.005" or 0.13 mm) material to place BGA Vss plane 50 closer to IC 12. If desired, the thickness of core 58 may be increased to compensate for a thinner core 56, to maintain overall rigidity for BGA package 50. Thermally, heat from IC 12 is coupled from the BGA package IC die Vss trace 12 through vial 6C to the BGA Vss plane 60, through the lower portion of the same vias to the BGA package Vss trace 14C on the lower surface of BGA package 50. From trace 14C, conduction to the Vss plane 20C on the system PCB 18 occurs (after soldering of BGA package 50 to the system PCB 18). The BGA Vss plane 60 may be relatively closer to the IC than is the underlying system PCB 18, and will thus sink heat and allow IC 12 to operate at a lower package temperature. A three-layer BGA package as depicted in Figure 2 will exhibit a  ja of about 20°C/W. Electrically, the BGA Vss plane 60 provides a closer and lower impedance Vss plane for sinking current output by IC 12 than is provided by the underlying PCB Vss plane 20C. The closer proximity of this Vss plane to IC 12 actually increases slightly the shunt capacitance by perhaps 0.1 pF. In practice, this slight capacitance increase can help IC 12 performance by emulating a small decoupling capacitor that is moved closer to the IC. Although on IC signal output pads further shunt capacitance is undesired, the relative increase is small, e.g., from about 1.2 pF to about 1.3 pF. As shown in Figure 2, the upper surface of BGA package 50 provides both a. central BGA package IC die Vss trace 8C, and peripheral BGA package traces 8C'. As noted, these traces 8C, 8C' are coupled through vias 6C, 6C' to the BGA Vss plane 60 to corresponding traces 10C, 10C' on the lower surface of the BGA package, and thence through solder balls 14C, 14C' to corresponding traces 20C, 20C' on the system PCB 18. So coupled, BGA Vss plane 60 advantageously reduces series inductance to IC 12, thus reducing ground bounce, at least for IC output signals transitioning from "1" to "0". The outer periphery BGA package traces 8C', 10C' and their associated vias and solder balls help maintain a low impedance between IC 12 and the BGA Vss plane 60, and thus help ensure that return current is present in the BGA Vss plane. If the outer BGA package Vss traces 8C', 14C' and associated vias and solder balls were eliminated, the ground bounce improvement otherwise available from BGA package 50 would suffer degradation, perhaps in the 40% range. During a "1" to "0" IC output signal transition, a low impedance ground current return path is present in BGA Vss plane 60, since the effective series inductance L is minimized. As a result, IC 12 is not forced to provide a substantial current return path, and any dV ≈ Ldi/dt voltage changes at the Vss pad within IC 12 are relatively minimal during "1" to "0" output voltage transitions. In this fashion, the Vss pad within IC 12 can maintain a relatively stable potential with minimum voltage bounce, at least during DC and "1" to "0" output voltage conditions, with attendant current sinking. Although the embodiment of Figure 2 provides improved thermal and electrical performance when compared to the prior art configuration of Figure 1, a three-layered embodiment is difficult to fabricate economically. As noted, BGA Vss plane may be either the lower surface of a PCB 52, or the upper surface of a PCB 54. As such, one of PCB 52 and 54 must be single sided, which is to say a non-symmetrical PCB. Combining a generic double-sided PCB with a single-sided PCB using, for example, pre-preg material is expensive, time consuming, and simply not a preferred mode of construction. Similarly, coating a copper clad surface on a symmetrical PCB (e.g., 52) with a pre-preg material (e.g. 58) that is then clad with copper (e.g., layer 10) is likewise not a preferred mode of construction. Further, the three-layered embodiment of Figure 2 minimizes ground bounce during IC current sourcing transitions only, and does not improve ground bounce for IC current sinking transitions. Figure 3 depicts a more preferred embodiment of the present invention, wherein a four-layer BGA package 100 is provided. This embodiment is somewhat similar to the above-described three-layer embodiment, except that a BGA Vdd plane 260 is also provided intermediate a BGA Vss plane 200 and the traces on the lower surface of the BGA package. This embodiment is preferred because it reduces ground bounce for "0" to "1" and for "1" to "0" IC output transitions. Further, this embodiment exhibits improved heat dissipation and advantageously may be fabricated from two pieces of symmetrical printed circuit board material. Thermally, the four-layer embodiment of Figure 3 has a  ja of about 15°C/W, which compares very favorably to the 35°C/W rating of a prior art two layer embodiment. For a given dissipation, IC 12 packaged in the four-layer embodiment of Figure 3 can safely dissipate about twice as much heat as can the same IC in a prior art two-layer BGA package. Thus, while the two-layer packaged IC would require the additional expense and volume associated with heat sinking, heat sinking may be avoided by using the four-layer package described herein. More specifically, as shown in Figure 3, a four-layer BGA package 100 provides a BGA Vss plane 200 and a BGA Vdd plane 260 disposed intermediate upper and lower BGA package conductive traces 8A, 8B, 8C, 8C', and 10A, 10B, 10C and 10C'. As in the embodiment of Figure 2, at least a portion of these upper and lower BGA package traces or places are in vertical registration to permit coupling therebetween using one or more vias. Because it is generally more important to reduce bounce at an IC Vss pad than at the IC Vdd pad due to decreased "0" level noise margins, the BGA Vss plane 200 preferably is placed closer to IC 12 than is the BGA Vdd plane 260. Similar to what was described with respect to Figure 2, the addition of the BGA Vss plane decreases series inductance substantially, but increases slightly the shunt capacitance as seen by a signal pad on the IC. However, the approximately 0.1 pF increase (e.g., from 1.2 pF without the BGA Vss plane to about 1.3 pF) appears beneficial in decoupling the IC signal lines from noise. In Figure 3, the Vss vias 6C, 6C' make electrical and thermal connection with the BGA Vss plane 200, but not with the underlying BGA Vdd plane 260. Similarly, the Vdd vias 6A are electrically insulated from the BGA Vss plane 200, but make electrical contact with the BGA Vdd plane 260. The various signal vias 6B are electrically insulated from both planes 200, 260. Such insulation can result from defining a relatively large opening in plane 200 and/or 260 through which a via passes that is not to make electrical contact with the plane. As in the three-layer embodiment, vias 6A, 6B, 6C, 6C' connect corresponding upper and lower BGA package traces 8A, 8B, 8C, 8C' and 10A, 10B, 10C, 10C', with vias 6C thermally conducting heat from the die Vss plane 8C to the BGA Vss plane 200, and thence downward. As described with respect to Figure 2, solder balls 14A, 14B, 14C, 14C' provide electrical contact with corresponding traces 20A, 20B, 20C, 20C' on an underlying system PCB 18. While vias 6C may also thermally conduct heat to the BGA Vdd plane 260 and the underlying system PCB ground plane or trace 20C, the Vdd plane 260 serves a relatively minor role in heat dissipation. More importantly, BGA Vdd plane 260 advantageously provides a Vdd plane that is relatively closer to IC 12 than is the underlying PCB Vdd plane or trace 20A. As a result, series inductance to IC 12 is reduced when the IC sources current, as in a "0" to "1" output signal transition. Further, as noted, the BGA Vss plane 200 reduces series inductance when IC 12 sinks current, as in a "1" to "0" output signal transition. The four-layer embodiment is preferred for ease of fabrication in that it can be manufactured using two pieces of symmetrical double clad PCB material 270, 280 with a core 290 therebetween. As such, PCB 270 has a core 272 sandwiched between copper clad layers defining the BGA package upper traces 8A, 8B, 8C, 8C' and the BGA Vss plane 200. PCB 280 has a core 282 sandwiched between copper clad layers defining the BGA Vdd plane 260 and the BGA package lower traces 10A, 10B, 10C, 10C'. Cores 272 and 282 may advantageously be conventional 0.005" (0.13 mm) FR4 epoxy glass material, joined together by a pre-preg core 290 whose thickness is whatever is desired to provide necessary rigidity for the BGA package 100, e.g., 0.020" to 0.060" (0.5 mm to 1.5 mm). Compared to a prior art two-layer BGA package, the four-layer embodiment of Figure 3 can reduce series inductance to about 6 nh to about 9 nh, and can reduce the effective IC output impedance to about 50 Ω. A 50 Ω output impedance advantageously permits high frequency signals from IC 12 to match 50 Ω transmission lines formed on the system PCB 18. Figure 4 depicts a computer simulation showing the response of an IC buffer encapsulated in a four-layer BGA package as shown in Figure 3, as contrasted with the same buffer packaged in the prior art two-layer configuration of Figure 1. In each simulation, a positive-going pulse (V IN ) was provided as input, and a relatively heavy 50 pF load was assumed. V OUT4 represents the voltage output of the four-layer configuration of Figure 3, and V OUT2 represents the voltage output of the two-layer prior art configuration of Figure 1. Because of the heavy capacitive load, neither output voltage waveform exhibits ringing. However, the decreased series inductance associated with the four-layer embodiment is apparent by the approximately 2 ns decrease in delay as contrasted with the delay in V OUT2 . At the top and bottom of Figure 4, V dd4 , V dd2 , V ss4 and V ss2 depict the upper and lower power supply signals as seen at the IC. In each instance, supply voltages at the IC associated with the four-layer embodiment are cleaner and exhibit less bounce than the corresponding two-layer embodiment signals. The improved voltage waveforms shown in Figure 4 result from diminished ground bounce in the four-layer package due to decreased effective series inductance. It will be appreciated that in a digital system comprising perhaps thousands of digital ICs that overall system reliability is enhanced by providing a four-layer BGA package according to the present invention. A more predictable noise margin is attained, and a more stable performance is realized, especially under increased ambient temperature, wherein the present invention advantageously permits the encapsulated IC to operate at lower junction temperature without heat sinking.

Claims: A ball grid array package (50) for an Integrated circuit ("IC") (12), comprising: upper layer package traces (8A-8C') which are suitable to be coupled to a corresponding IC pad by means of bond wires (22, 24), lower layer package traces (10A-10C') with regions that are solderable to solder balls (14) used to solder said package (50) to an underlying system printed circuit board ("PCB") (18), the upper and lower layer traces (8A-8C'; 10A-10C') each including a Vss trace (8C, 10C), a Vdd trace (8A, 10A), and a signal trace (8B, 10B); isolating material disposed between the upper and lower layer package traces (8A-8C'; 10A-10C') and comprising two cores (56, 58) having a combined thickness to provide rigidity to the package (50); vias (6A-6C') including a Vdd via (6A) coupling the upper layer Vdd trace (8A) to a corresponding lower layer Vdd trace (10A) and a signal via (6B) coupling the upper layer signal trace (8B) to a corresponding lower layer signal trace (10B); a Vss plane (60) disposed intermediate said upper and said lower layer package traces (8A-8C'; 10A-10C') and making contact with a Vss via (6C) coupled to an upper and lower layer Vss trace (8C, 10C); characterized in that one of said cores (56, 58) together with the Vss plane (60) and the package traces (8A-8C'; 10A-10C') belonging to this core forming a symmetrical PCB and the other core (58, 56) together with the package traces (8A-8C'; 10A-10C') belonging to said other core forming an asymmetrical PCB; the vias (6A-6C') including the Vss via (6C) are unitary-construction vias extending through vertically aligned associated openings in the cores (56, 58) and the Vss plane (60) and thus through the combined thickness of said cores (56, 58) from the upper layer package traces (8A-8C') through cores (56, 58) to the lower layer package traces (10A-10C'); and the lower layer package traces (10A-10C') coupled to corresponding ones of the upper layer package traces (8A-8C') through the vias (6A-6C') are in vertical alignment. The package according to claim 1, characterized by a third core (290) sandwiched between the Vss plane (200) of a first (272) of said two cores and a Vdd plane (260) of a second (282) of said two cores; the three cores (260, 272, 282) and the Vss and Vdd Planes (200, 260) each having at least three via openings defined therethrough; the Vdd via (6A) coupling the upper layer Vdd trace (8A) to the Vdd plane (260) and to the lower layer Vdd trace (10A) by passing through the via opening in the Vdd plane (260) while contacting the Vdd plane (260) and by passing through the via opening in the Vss plane (200) without contacting the Vss plane (200); the signal via (6B) coupling the upper layer signal trace (8B) to the lower layer signal trace (10B) while passing through via openings in the Vss and Vdd planes (200, 260) without contacting the Vss or the Vdd planes (200, 260); and by the Vss via (6C) coupling the upper layer. Vss trace (8C) to the Vss plane (200) and to the lower layer Vss trace (10C) by passing through the via opening in the Vss plane (200) while contacting the Vss plane (200) and by passing through the via opening in the Vdd plane, (260) without contacting the Vdd plane (260). The package according to one of the claims 1 or 2, characterized in that said upper layer package Vss trace (8C) includes an IC die plane soldered to a substrate of said IC (12). The package according to claim 2, characterized in that at least one of said first core (272) and said second core (282) comprises a symmetrical PCB (170, 280). The package according to claim 3 or 4, characterized in that said Vss plane (200) is disposed closer to said IC (12) than is said Vdd plane (260). The package according to one of the claims 1 to 5, characterized in that said Vss plane (60, 200) is vertically spaced-apart from said substrate of said IC (12) at a distance less than 0.03" (0.8 mm). The package according to one of the claims 1 to 6, characterized in that at least one core (56, 58, 272, 282, 290) includes a material selected from the group consisting of (a) FR4 epoxy glass, and (b) pre-preg. The package according to one of the claims 1 to 7, characterized by an overmold (16) encapsulating said IC (12). The package according to one of the claims 1 to 8, characterized in that the output impedance between a signal output pad on said IC (12) and said Vss plane (60, 200) is about 50 Ω. The package according to one of the claims 1 to 9, characterized in that said IC (12) includes a digital circuit operating at a frequency of at least 30 MHz. The package according to claim 1, characterized in that the upper layer Vdd and Vss traces (8A, 8C) are an upper layer surface Vdd and Vss plane, respectively, and in that the lower layer Vdd and Vss traces (10A, 10C) are a lower layer surface Vdd and Vss plane, respectively. The package according to claim 11, characterized in that the output impedance between a signal output pad on said IC (12) and said upper layer surface Vss plane and said lower layer surface Vss plane is about 50 Ω. A method of reducing ground bounce and increasing thermal dissipation in a ball grid array package (50) for an integrated circuit ("IC") (12), the package (50) comprising two cores (56, 58) sandwiched between upper and lower layer package traces (8A-8C'; 10A-10C') coupled together by vias (6A-6C'), said IC (12) suitable to be coupled to chosen ones of said upper layer package traces (8A-8C') by means of bond wires, and chosen ones of said lower layer package traces (10A-10C') being solderable to solder balls (14) adapted to be soldered to traces on an underlying system printed circuit board (18), the method comprising the following steps: (a) disposing a Vss plane (60) intermediate said upper and lower layer package traces (8A-8C'; 10A-10C'); (b) coupling said Vss plane (60) using at least one Vss via (6C) to a Vss trace included among said upper and lower package traces (8A-8C'; 10A-10C'); (c) coupling an upper layer V DD trace (8A) to a corresponding lower layer V DD trace (10A) using at least one V DD via (6A); (d) coupling an upper layer signal trace (8B) to corresponding lower layer signal trace (10B) using at least one signal via (6B); characterized by (e) using a symmetrical printed circuit board for forming one of said cores (56, 58) together with the Vss plane (60) and the package traces (8A-8C'; 10A-10C') belonging to this core; (f) using an asymmetrical printed circuit board for forming the other core (58, 56) together with the package traces (8A-8C'; 10A-10C') belonging to said other core; (g) using as the vias (6A-6C') including the Vss via (6C) unitary-construction vias extending through vertically aligned associated openings in the cores (56, 58) and the Vss plane (60) and thus through the combined thickness of said cores (56, 58) from the upper layer package traces (8A-8C') through cores (56, 58) to the lower layer package traces (10A-10C'); and (h) aligning the lower layer package traces (10A-10A') coupled to corresponding ones of the upper layer package traces (8A-8A') through the vias (6A-6C') in vertical direction. The method according to claim 13, characterized by disposing a V dd plane (260) intermediate said Vss plane (200) and said lower package traces (10A-10C'); and coupling said V dd plane (260) using at least one V DD via (6A) to a V dd trace (8A) among said upper and lower package traces (8A-8C'; 10A-10C'), said V dd plane (260) defining via openings through which other of said vias (6A-6C') not coupled to V dd pass without making electrical contact. The method according to claim 13 or 14, characterized in that for at least one of said (i) upper layer package traces (8A-8C'), a portion of said cores (56, 58, 272, 282), and said Vss plane (60, 200), and (ii) said V dd plane (260), a portion of said cores (56, 58, 272, 282), and said lower layer package traces (10A-10C') double-sided printed symmetrical PCB material is chosen. The method according to the claims 13 to 15, characterized in that a material comprised in said cores (56, 58, 272, 282) is selected from the group consisting of (a) FR4 epoxy glass, and (b) pre-preg. The method according to one of the claims 13 to 16, characterized in that at step (a) said Vss plane (60) is disposed vertically spaced apart from a substrate of said IC (12) at a distance less than 0.03" (0.8 mm).

Inventors: SELNA ERICH, SELNA, ERICH
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 1995
Main classification: H01L23
IPC codes: H01L23, H05K1, H05K3