ENHANCED TRANSFER METHOD (ETM) FOR HIGH SPEED DATA TRANSMISSION SYSTEM

Abstract: An adaptor (36) processes and transfers data from a computer (12) to a printer (16). The data is divided by the computer (12) into blocks of non-repeated (different) and repeated (identical) data elements. The adaptor (36) receives the blocks of non-repeated data elements from the computer (12) and re-transmits them to the printer (16) without alteration. Rather than transmitting a block of repeated data elements per se, the computer (12) transmits a number of alternating high and low strobe signals that are equal to the number of repeated data elements in the block. The first repeated data element is latched by the adaptor (36), and then repeatedly transmitted to the printer (16) in response to each respective alternating strobe signal.

Description: ENHANCED TRANSFER METHOD (ETM) FOR HIGH SPEED DATA TRANSMISSION SYSTEM BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to the art of electronic computers, and more specifically to an Enhanced Transfer Method (ETM) for a high speed data transmission system which transmits data from a computer to a peripheral device such as a printer at high speed. Description of the Related Art A computer system for personal or business use generally includes a peripheral device in the form of a printer for producing hard copy documents. FIGs. l and 2 illustrate a conventional method of transmitting data from a computer to a printer in parallel form. FIG. 1 illustrates the operations performed by the computer, whereas FIG. 2 illustrates the operations performed by the printer. The computer determines the availability of the printer to receive a data element in the form of a parallel byte by polling a BUSY signal line. If the printer is busy, it generates a logically high BUSY signal and the computer will not attempt to transmit data to the printer. If the printer is available, it generates a logically low signal on the BUSY line. The computer then transmits a byte to the printer by setting a STROBE line low, outputting the data byte to an output latch and then setting the STROBE line high. The printer polls the STROBE line. If the STROBE signal is high, the printer will not attempt to input a byte from the computer. When the strobe signal goes low, the printer sets the BUSY signal high, latches in the data byte, generates an ACKNOWLEDGE signal and then sets the BUSY signal low. The conventional method uses four program instructions or input/output (I/O) calls to output one byte of data. A first instruction (IN) is required to poll the BUSY line, a second instruction (OUT) sets the STROBE line low, a third instruction (OUT) outputs the data to the latch and a fourth instruction (OUT) sets the STROBE line high. The requirement of four instructions, one IN instruction and three OUT instructions, to output a single data byte inherently limits the speed or rate at which data is transmitted from the computer to the printer. For example, the data transmission rate for a standard parallel port of an Intel 486 computer system operating at a clock speed of 33 MHz is approximately 60 to 100 kilobytes per second. A parallel port is a very convenient means for connecting a peripheral device. Various devices, for example tape data backup drives, CD ROM drives, telecommunications adapters such as modems, and network adapters such as Ethernet can be driven from parallel ports, but the data transfer rate is too slow using the conventional method for practical applications. There exists in the art a need for an improved parallel data transfer method that will enable peripheral devices such as these to be driven from a standard parallel port. SUMMARY OF THE INVENTION It is an object of the present invention to provide an Enhanced Transfer Method (ETM) for a data transmission system which is capable of operation at substantially higher data transmission rates than those which are achievable in the prior art. It is another object of the present invention to provide an adaptor for practicing the present method. In accordance with a high speed data transmission system using the present method, the adaptor processes and transfers data from a computer to a printer. The data is divided by the computer into blocks of non-repeated (different) and repeated (identical) data elements. The adaptor receives the blocks of non-repeated data elements from the computer and re-transmits them to the printer without alteration. Rather than transmitting a block of repeated data elements per se, the computer transmits a number of alternating high and low strobe signals that are equal to the number of repeated data elements in the block. The first repeated data element is latched by the adaptor, and then repeatedly transmitted to the printer in response to each respective alternating strobe signal. The adaptor thereby transmits a data element to the printer in response to sensing a received data element that is different from the previous received data element, or in response to a received strobe signal that is different from a previous received strobe signal. The computer requires only one program instruction to output a non-repeated data element or an alternating strobe signal, as compared to four instructions in the prior art. This enables the data transmission rate for an Intel 486 computer system implementing the present method to be increased from the prior art value of 60 to 100 kilobytes per second to approximately 1,000 kilobytes per second. The present invention enables tape data backup drives, CD ROM drives, telecommunications adapters such as modems, and network adapters such as Ethernet to be driven from a standard parallel port at a speed that is sufficiently high for practical applications. The above and other objects, features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description taken with the accompanying drawings, in which like reference numerals refer to like parts. DESCRIPTION OF THE DRAWINGS FIGs. 1 and 2 are flowcharts illustrating a prior art method of transmitting data from a computer to a printer; FIG. 3 is a simplified block diagram illustrating a high speed data transmission system according to the present invention; FIG. 4 is a diagram illustrating a data port arrangement of the present system; FIG. 5 is an electrical schematic diagram illustrating a data adaptor of the system; FIG. 6 is a flowchart illustrating the operation of the present data transmission system; and FIG. 7 is a timing diagram for further illustrating the operation of the system. DETAILED DESCRIPTION OF THE INVENTION A high speed data transmission system 10 utilizing an Enhanced Transfer Method (ETM) of data transmission according to the present invention is illustrated in Fig. 3. The system 10 generally comprises a transmitter in the form of a personal computer 12, and a receiver in the form of a peripheral device 14. The present system 10 is especially suited to an application in which the peripheral device 14 comprises a printer 16, although the invention is not so limited. The computer 12 comprises a motherboard 18, including a Central Processing Unit (CPU) 20, a Read Only Memory (ROM) 22, a Random Access Memory (RAM) 24 and a parallel data Input/Output (I/O) unit 26 having a data port 26a, a status port 26b and a control port 26c. The computer 12 further comprises a monitor 28 for displaying data being processed, a keyboard 30 for data input and a disk storage 32 including a hard disk drive and/or a floppy disk drive. The CPU 20 is typically an Intel 486 microprocessor, although the invention is not limited to any particular configuration. The RAM 24 is divided, under control of an operating program, into a data array 24a and a control array 24b. The remainder of the RAM 24 constitutes a main area 24c for storing program instructions, data and variables. The sizes of the data array 24a and the control array 24b are selected in accordance with a particular application. A suitable size of the data array 24a for operation with an Intel 486 microprocessor system has been found to be approximately 1 megabyte, whereas the control array 24b will typically have a size of 2 kilobytes. The computer 12 transmits data in parallel form through the I/O unit 26 and a communications cable 34 to the peripheral device 14. In accordance with the present invention, the device 14 includes an adaptor 36 which is connected between the cable 34 and the printer 16. The I/O unit 26 is illustrated in FIG. 4. The data port 26a is accessed by writing to a BASE ADDRESS, whereas the status port 26b is accessed by writing to the BASE ADDRESS + 1 and the control port is accessed by writing to the BASE ADDRESS + 2. Each data element that is transmitted from the computer 12 to the peripheral unit 14 is typically an eight bit byte, although the invention is not so limited. The eight bits of each byte are output in parallel from the data port 26a as signals BO to B7 respectively. Bits 1 to 7 of the status port 26b are unused in accordance with the present method, whereas a BUSY signal that is generated by the printer 16 is input at bit 8 of the status port 26b and can be used for flow control in a conventional manner. A negative logic strobe signal STRB is output at bit 1 of the control port 26c. A negative logic initialization signal INIT is output at bit 3, whereas bits 2 and 4 to 8 of the control port 26c are unused. In accordance with the present method, the computer 12 transmits data to the printer 16 in two different forms depending on whether the data is repeated or non-repeated. Non-repeated data consists of consecutive data elements, in the present case 8-bit bytes, that have different numerical values. Repeated data consists of consecutive bytes that have the same numerical value. Non-repeated data is transmitted without alteration. However, repeated data is not transmitted per se. Instead, only the first byte of repeated data (the last byte of previously transmitted non-repeated data) is transmitted, and alternating strobe signals are transmitted for the other bytes of the repeated data. Data to be transmitted from the computer 12 to the printer 16 is stored in the data array 24a of the RAM 24. Under program control, the data array 24a is searched to locate and map blocks of repeated data and non-repeated data. The blocks are output as either data or alternating strobe signals in burst mode depending on the type of data. The detailed operation of the present system 10 will be described with reference to the flowchart of FIG. 6. An operating program that controls the operation of the computer 12 is stored in the main area 24c of the RAM 24. The program first performs an initialization routine that establishes pointers to the required addresses in the system, including the first byte of data in the data array 24a and the first byte of alternating strobe data in the control array 24b. The system I/O address is initially set to the address of the data port 26a of the I/O unit 26 so that data will be output therethrough. The program then sets up a "BYTE COUNT" that designates the number of bytes to be output in one operation. The BYTE COUNT is selected in accordance with the particular application. The first byte in the data to be transmitted is compared with the last byte of the data transmitted in the previous operation. If these bytes are different, indicating the beginning of a block of at least two bytes of non-repeated data, the program branches to a point A. If the bytes are the same, indicating the beginning of a block of at least two bytes of repeated data, the program branches to a point B. For the case of non-repeated data, the program proceeds from the point A to determine if the BYTE COUNT is zero. If so, the program terminates after updating the pointers for the data array 24a and the control array 24b. If not, the data in the array 24a is scanned from the pointer to the first repeated byte. The next step is to output all bytes from the pointer to and including the first repeated byte as a burst of sequential data. The data is output through the data port 26a and transmitted to the printer 16. Then, the data pointer is set to the address of the second repeated byte and the BYTE COUNT is decremented by the number of bytes that were transmitted. The program then branches to the point B. Since two repeated data bytes were found, the next operation is to burst output the next block of repeated bytes. The program first checks to see if the BYTE COUNT has been decremented to zero. If so, the program terminates as described above. If the BYTE COUNT is not zero, the data is scanned starting from the updated pointer to locate the first non-repeated byte. The number of repeated bytes in the block is computed as being equal to the number of bytes from the pointer to the first non-repeated byte. The system I/O address is then changed to the address of the control port 26c to cause data to be output therethrough. The data stored in the control array 24b consists of a series of bytes having alternating strobe bits. More specifically, bit 1, which is the negative logic strobe bit of the control port 26c, is logically high in the first byte in the array 24b, logically low in the second byte, logically high in the third byte, etc. A number of sequential bytes equal to the number of repeated bytes in the block that was computed as described above is then output from the control array 24b through the control port 26c as a burst, with the first repeated byte being skipped. During this operation, the strobe signal STRB that is output and transmitted to the adaptor 36 is logically high or low depending on the value of the bit in the respective byte in the control array 24b. As will be described in detail below, each time the adaptor 36 receives an alternating strobe signal STRB (the logical sense of the signal STRB changes from high to low or from low to high) , it transmits the previously received repeated byte to the printer 16. The byte that is transmitted is the last byte of the previously transmitted block of non-repeated data, which was stored in a latch in the adaptor 36 upon termination of the previous operation. It will be recalled that the last byte of data that is transmitted in a block of non-repeated data is the first byte of subsequent repeated data. This byte is skipped in the subsequent operation of transmitting a block of repeating data. Thus, no bytes are duplicated or omitted. In this manner, the adaptor 36 repeatedly transmits the same byte of data until the number of bytes that have been transmitted is equal to the number of bytes in the block of repeated data. When the entire block has been transmitted, the system I/O pointer is set to the address of the data port 24a, the data pointer is set to the address of the first non-repeated byte and the BYTE COUNT is decremented by the number of bytes that were transmitted. The adaptor 36 is illustrated in FIG. 5, and comprises a transparent data latch 38 having data inputs Dl to D8 that are connected to receive the signals BO to B7 from the data port 26a of the computer 12 respectively. The latch 38 is preferably embodied by a SN74ALS843 9-BIT BUS INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS that is commercially available from Texas Instruments. Signals LBO to LB7 which are latched versions of the signals BO to B7 appear at data outputs Ql to Q8 of the latch 38 and are applied to inputs of exclusive-OR gates 40 to 54 of a comparator 56. The signals LBO to LB7 are transmitted to the printer 16. The signals BO to B7 are applied to other inputs of the exclusive-OR gates 40 to 54 respectively. The strobe signal STRB is applied to a data input D9 of the latch 38, and a latched version thereof that is designated as a latched strobe signal LSTRB is output from a data output Q9 of the latch 38. The signals STRB and LSTRB are applied to inputs of an exclusive-OR gate 59. The outputs of the exclusive-OR gates 40, 42 and 44 are connected to inputs of an OR gate 58, the outputs of the exclusive-OR gates 46, 48 and 50 are connected to inputs of an OR gate 60, whereas the outputs of the exclusive-OR gates 52 and 54 are connected to inputs of an OR gate 62. The outputs of the OR gates 58, 60 and 62 are connected to inputs of an OR gate 64, the output of which is connected to an input of an OR gate 66. The output of the exclusive-OR gate 59 is connected to another input of the OR gate 66. A compare output or latch trigger signal LTCHTRG appears at the output of the OR gate 66. The comparator 56 is preferably embodied by a PAL22V1024-PIN TTL VERSATILE PROGRAMMABLE LOGIC DEVICE (PAL) DEVICE that is commercially available from Advanced Micro Devices. The adaptor 36 further comprises a reset unit in the form of a monostable multivibrator 68 that is preferably embodied by a SN74LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATOR which is commercially available from Texas Instruments. The multivibrator 68 has a high-level-active B input connected to receive the latch trigger signal LTCHTRG. The latch strobe signal LTCHSTRB signal appears at a Q output of the multivibrator 68 and is applied to a clock input C of the latch 38. The initialization signal INIT is applied to clear inputs CLR of the latch 38 and the multivibrator 68. The adaptor 36 senses a non-repeated input byte and transmits it to the printer 16. The adaptor 36 also senses a changed strobe signal and transmits the previously latched byte to the printer 16 in response thereto. More specifically, the comparator 56 compares the data BO to B7 transmitted from the computer 12 with the data LBO to LB7 at the output of the latch 38. If these data are different, as in the case of non-repeated data, the adaptor 36 latches and outputs the new data to the printer 16. In the case of repeated data, the data LBO to LB7 will be the same as the data BO to B7, since the computer 12 will continuously output the same byte. However, the strobe signal STRB will change for each repeated byte. The adaptor 36 latches and outputs the data BO to B7 for each change of the strobe signal STRB. The exclusive-OR gates 40 to 54 will produce a logically high output whenever the respective inputs are different. In this manner, the signals BO to B7 which represent the data being output by the computer 12 are compared bit by bit with the previously latched signals LBO to LB7 which represent the previous byte. If any of these bits are different, at least one of the exclusive-OR gates 40 to 54 will produce a high output. Consequently, at least one of the OR gates 58, 60 and 62 will produce a high output, and the OR gate 64 will produce a high output that is fed through the OR gate 66 as the latch trigger signal LTCHTRG. Similarly, the exclusive-OR gate 59 compares the current strobe signal STRB with the previously latched strobe signal LSTRB and generates a high output when they are different. This causes the OR gate 66 to produce the signal LTCHTRG. The signal LTCHTRG is applied to the trigger input B of the multivibrator 68, causing the output Q to go logically high for a pulse duration that is selected in accordance with a particular application. A suitable pulse duration for Intel 486 system operation is 200 nanoseconds. The pulse generated by the multivibrator 68 is the latch strobe signal LTCHSTRB, which is applied to the clock input of the latch 38. This causes the signals BO to B7 and the strobe signal STRB to be latched into the latch 38. The signal LTCHSTRB is also fed to the printer 16 to cause it to input the new data byte represented by the signals LBO to LB7. The adaptor 36 is further capable of being reset to a known state. This is accomplished by applying the initialization signal INIT to the clear inputs of the latch 38 and the multivibrator 68. This causes the data LBO to LB7 and the strobe bit LSTRB in the latch 38 to be set to zero. With the INIT signal held low, the computer 12 can set the data signals BO to B7 and the strobe signal STRB to low states without transmitting a signal to the printer 16. FIG. 7 illustrates the timing of operation of the adaptor 38. At a time TO, the nine inputs (data BO to B7 and strobe STRB) are in a steady state, and the latched signals LBO to LB7 and LSTRB have the same values as the corresponding input signals. The adaptor 38 is ready to receive a new byte of data. At a time Tl, either the input data byte or the strobe signal STRB has changed (one of the nine inputs has changed) . This causes the latch trigger signal LTCHTRG to go high and trigger the multivibrator 68 at a time T2. The LTCHTRG signal causes the multivibrator 68 to produce the latch strobe pulse LTCHSTRB for a duration of 200 nanoseconds starting at a time T3. This causes the latch 38 to latch in the data signals B0 to B7 and the strobe signal STRB at a time T4. The input signals B0 to B7 are latched into the latch 38 and the inputs to the comparator 56 become the same at a time T5. This causes the latch trigger signal LTCHTRG to go low at a time T6. The latch strobe signal LTCHSTRB pulse goes low at a time T7. The operation of scanning the data in the array 24a to determine the number of bytes in a block of repeated data is preferably performed using a COMPARE STRING BY BYTE (CMPSB) instruction in combination with a REPEAT UNTIL NOT EQUAL (RPNE) qualifier that are standard commands in the Intel 386/486 programming language. The number of bytes in a block of non-repeated data is determined in an essentially similar manner using the CMPSB instruction in combination with a REPEAT UNTIL EQUAL (REPE) qualifier. An exemplary assembly language code fragment for a block of repeated data is as follows. (1) LDS SI,Ptrl (2) LES DI,Ptr2 (3) MOV CX,BYTE COUNT (4) REPNE COMPSB DS: [SI] ,ES: [DI] Steps (1) to (3) set up the registers that are required to perform step (4) . More specifically, step (1) loads the DATA SEGMENT register DS and the SOURCE INDEX register SI with the address pointed to by Ptrl, which is the address pointer described above with reference to FIG. 6. Step (2) similarly loads the EXTENDED SEGMENT register ES and the DESTINATION INDEX register DI with the address of a pointer Ptr2 which is equal to Ptrl + 1. Step (3) loads the BYTE COUNT into the COUNT register CX. The REPNE COMPSB instruction in step (4) compares the byte addressed by the pointer Ptrl with the byte addressed by the pointer Ptr2. These bytes are consecutive. The pointers Ptrl and Ptr2 are incremented each time step (4) is performed such that the data in the array 24a starting at the pointer Ptrl is sequentially searched by comparing each two consecutive bytes. Step (4) is repeated until two non-repeated (different) bytes are found or the CX register is decremented to zero. If a non-match is found, the CX register will contain the number of bytes not scanned and DS:[SI] will point to the first non-repeated byte. The size of the block of repeated data is equal to the initial BYTE COUNT minus the count in the CX register. An exemplary assembly language code fragment for a block of non-repeated data is as follows. (1) LDS SI,Ptrl (2) LES DI,Ptr2 (3) MOV CX,BYTE COUNT (4) REPE COMPSB DS: [SI] ,ES: [DI] Steps (1) to (3) set up the registers that are required to perform step (4) in the same manner as for the case of repeated data. Step (4) is performed until two repeated (identical) bytes are found or the CX register is decremented to zero. If a match is found, the CX register will contain the number of bytes not scanned, and DS: [SI] will point to the first repeated byte. The size of the block of non- repeated data is equal to the initial BYTE COUNT minus the count in the CX register. Data is preferably output by the computer 12 using a single program instruction for each byte, more specifically the OUTPUT STRING BY BYTE (OUTSB) with the REPEAT (REP) qualifier. An example of assembly language code for performing data output is as follows. (1) LDS SI,Prtl (2) MOV CX,BYTE COUNT (3) MOV DX,PORT ADDRESS (4) REP OUTSB Step (1) loads an address pointer Ptrl into the DS and SI registers. The pointer Ptrl points to the first address of the block of data in the data array 24a for outputting a block of non-repeated data, and points to the first address of the block of alternating strobe data in the control array 24b for outputting a block of repeated data. Step (2) loads the BYTE COUNT, in this case indicating the number of bytes in the block of data to be output. into the CX register. Step (3) loads the PORT ADDRESS into the DX register. The PORT ADDRESS is the address of the data port 26a for outputting a block of non-repeated data, and the address of the control port 26c for outputting a block of repeated data. Step (4) performs the actual output operation by outputting consecutive bytes of data until the CX register has been decremented to zero. Upon completion, the DX register will be unaffected and DS:[SI] will point to the address of the byte of data following the last byte of data that was output. In summary, the present invention enables a byte of data to be output using only one program instruction, and thereby achieves the goal of substantially increasing the rate at which data can be transmitted from the computer 12 to the printer 16. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof. For example, although the adaptor 36 is preferably provided at the peripheral device 14 with the printer 16, it is within the scope of the invention to provide the adaptor 36 at the computer 12 or at an intermediate position in the cable 34. As another exemplary modification, data can be transmitted serially, rather than in parallel.

Claims: WHAT IS CLAIMED IS: 1. A data transmission system, comprising: a transmitter for transmitting sequential non- repeated data elements, and for transmitting alternating status signals corresponding to sequential repeated data elements respectively; and an adaptor for re-transmitting said non-repeated data elements received from the transmitter, and for repeatedly transmitting a previously received repeated data element in response to said alternating status signals respectively. 2. A system as in claim 1, further comprising a receiver for receiving said non-repeated data elements and said repeated data elements from the adaptor. 3. A system as in claim 2, in which: the transmitter comprises a computer; and the receiver comprises a peripheral device. 4. A system as in claim 3, in which the peripheral device comprises a printer. 5. A system as in claim 1, in which the adaptor comprises: a latch for latching said previously received repeated data element; and a controller for transmitting said previously received repeated data element from the latch to the receiver in response to said alternating status signals. 6. A system as in claim 5, in which the controller comprises a comparator for sensing said alternating status signals received from the transmitter, and causes said previously received repeated data element to be transmitted from the latch to the receiver in response to said sensing. 7. A system as in claim 5, in which the controller causes said non-repeated data elements to be latched into the latch and transmitted from the latch to the receiver. 8. A system as in claim 7, in which the controller comprises a comparator for sensing said non-repeated data elements received from the transmitter, and causes said non-repeated data elements to be latched into the latch and transmitted from the latch to the receiver in response to said sensing. 9. A system as in claim 1, in which the transmitter comprises: a data element memory for storing said non- repeated data elements and said repeated data elements; and a controller for locating said repeated data elements in the data element memory, producing said alternating status signals as corresponding to said repeated data elements and transmitting said alternating status signals to the adaptor as a block. 10. A system as in claim 9, in which the controller further locates said non-repeated data elements in the data element memory and transmits said non-repeated data elements to the adaptor as a block. 11. A system as in claim 9, in which: the transmitter further comprises a status signal memory for storing alternating status signals; and the controller reads out and transmits a number of alternating status signals from the status signal memory that is equal to a number of said non-repeated data elements in said block. 12. A system as in claim 1, in which said status signals comprise strobe signals. 13. An adaptor for re-transmitting received non-repeated data elements, and for repeatedly transmitting a previously received repeated data element in response to received alternating status signals respectively, comprising: a latch for latching said previously received repeated data element; and a controller for repeatedly transmitting said previously received repeated data element from the latch in response to said alternating status signals respectively. 14. An adaptor as in claim 13, in which the controller comprises a comparator for sensing said alternating status signals upon receipt thereof, and causes said previously received repeated data element to be transmitted from the latch in response to said sensing. 15. An adaptor as in claim 13, in which the controller causes said non-repeated data elements to be latched into the latch and re-transmitted from the latch. 16. An adaptor as in claim 15, in which the controller comprises a comparator for sensing said non-repeated data elements upon receipt thereof, and causes said non- repeated data elements to be latched into the latch and re-transmitted from the latch in response to said sensing. 17. A data transmission method, comprising the steps of: (a) transmitting alternating status signals corresponding to sequential repeated data elements; and (b) repeatedly transmitting a previously received repeated data element in response to said alternating status signals respectively. 18. A method as in claim 17, further comprising the step of: (c) re-transmitting received non-repeated data elements. 19. A method as in claim 17, in which step (b) comprises the substeps of: (c) latching said previously received repeated data element in a latch; and (d) repeatedly transmitting said previously received repeated data element from the latch in response to said alternating status signals respectively. 20. A method as in claim 19, in which: step (b) further comprises the substep, performed between steps (c) and (d) , of: (e) sensing said alternating status signals upon receipt thereof; and step (d) comprises causing said previously received repeated data element to be transmitted from the latch in response to said sensing in step (e) .

Inventors: FRAZIER ALAN L, FRAZIER, ALAN, L.
Applicants: DP TEK INC, DP-TEK, INC.
Application year: 1995
Main classification: G06F13
IPC codes: G06F3