Voltage-level shifter

Abstract: A voltage level shifter is provided which complies with the situation that a voltage source of an input signal supplies a low voltage and/or a large potential difference exists between a voltage source of an input signal and a voltage source of a voltage level shifter. When the input signal transits from an "L" level to the "H" level, a MOS transistor to be turned off is surely controlled to be turned off, and a voltage level of an output signal of the voltage level shifter is surely fixed at the "L" level while surely preventing flow of a through current.

Description: BACKGROUND OF THE INVENTION The present invention relates to a voltage-level shifter. A semiconductor device using a plurality of voltage sources requires a voltage-level shifter for shifting potentials of signals to potential levels of the respective voltage sources. A voltage-level shifter the prior art will be described below. Fig. 7 shows a circuit structure of a conventional voltage-level shifter in the prior art, and Fig. 3 shows an operation timing of the conventional voltage-level shifter. In these figures, I30 indicates an input signal, 030 indicates an output signal, VCC indicates a first voltage source, VPP indicates a second voltage source, VSS indicates a ground voltage source, 3001 indicates a voltage-level shifter, Qn3001 and Qn3002 indicate N-channel MOS transistors, Qp3001 and Qp3002 indicate P-channel MOS transistors, and N3001 indicates a node name. A circuit structure in Fig. 7 will be described below. The input signal I30 is connected to a source of the N-channel MOS transistor Qn3001 and a gate of the N-channel MOS transistor Qn3002. A gate of the N-channel MOS transistor Qn3001 is connected to the first voltage source VCC, and a source of the N-channel MOS transistor Qn3002 is connected to the ground voltage source VSS. A source of the P-channel MOS transistor Qp3001 and a source of the P-channel MOS transistor Qp3002 are connected to the second voltage source VPP. A drain of the N-channel MOS transistor Qn3001, a drain of the P-channel MOS transistor Qp3001 and a gate of the P-channel MOS transistor Qp3002 are connected together. The output signal 030 is connected to a drain of the N-channel MOS transistor Qn3002, a gate of the P-channel MOS transistor Qp3001 and a drain of the P-channel MOS transistor Qp3002. Fig. 8 shows a basic structure of the voltage-level shifter in Fig. 7. The structure in Fig. 8 differs from that in Fig. 7 in that an N-channel MOS transistor Qn3001' is supplied on its gate with a signal formed by inverting the input signal by an inverter INV32, has a source connected to the voltage source VSS of the input signal, and has a drain connected to the P-channel MOS transistor Qp3202. In other words, the structure in Fig. 31 eliminates the inverter circuit INV32 by employing the appropriate connection structure of the N-channel MOS element Qn3001, but performs the same operation as the basic structure in Fig. 8 . Accordingly, the operation will be described below only in connection with the structure in Fig. 7. Referring to an operation timing diagram of Fig. 9, the operation will be described below. When the input signal I30 is at the "L" (Low) level, the node N3001 is at the "L" level, the N-channel MOS transistor Qn3002 is off, P-channel MOS transistor Qp3002 is on, output signal 030 is at the "H" level set by the second voltage source VPP, and the P-channel MOS transistor Qp3001 is completely off. When the input signal 130 transits from the "L" level to the "H" level, the N-channel MOS transistor Qn3002 is completely turned off, the node N3001 attains a potential (VCC-Vtn) which is lower than the potential of the first voltage source VCC by a threshold voltage (Vtn) of the N-channel MOS transistor Qn3001, and the P-channel MOS transistor Qp3002 is substantially turned off. Then, the output signal 030 attains the "L" level, the P-channel MOS transistor Qp3001 is completely turned off, the node N3001 attains the potential of the second voltage source VPP, and the p-channel MOS transistor Qp3002 is completely turned off. Fig. 10 shows another voltage-level shifter. This voltage-level shifter amplifies both the maximum and minimum values of an amplitude of an input signal to produce a signal having a large amplitude. The voltage-level shifter includes a signal inverter circuit 50 inverting the input signal, a positive level shifter 51 which receives the input signal and an output signal of the signal inverter circuit 50 to amplify the maximum value of the amplitude of the input signal, a negative level shifter 52 which receives the input signal and the output signal of the signal inverter circuit 50 to amplify the minimum value of the amplitude of the input signal, and a positive/negative level shifter 53 which receives output of the positive and negative level shifters 51 and 52 to compose them. However, in the voltage-level shifters of the conventional structures shown in Figs. 7 and 9, when the input signal I30 transits from the "L" level to the "H" level, the N-channel MOS transistor Qn3002 is completely off, and the P-channel MOS transistor Qp3002 is substantially off as already described. In particular, if the first voltage source VCC supplies a low voltage, and/or a large potential difference exists between the first and second voltage sources VCC and VPP, the P-channel MOS transistor Qp3002 is on. Therefore, a through current flows from the second voltage source VPP to the ground voltage source VSS via the N-channel MOS transistor Qn3002 and the P-channel MOS transistor Qp3002, which causes a disadvantage that the voltage level of the output signal 030 cannot fixed at the "L" level. The conventional voltage-level shifter shown in Fig. 10. requires three level shifters and hence many transistors forming them, and is constructed to compose the shifted outputs of the positive and negative level shifters, resulting in reduction of the operation speed. SUMMARY OF THE INVENTION An object of the invention is to provide a voltage-level shifter which can operate as follows if a voltage source of an input signal supplies a low voltage and/or a large potential difference exists between a voltage source of an input signal and a voltage source of a voltage-level shifter. When the input signal transits from an "L" level to the "H" level, an MOS transistor to be turned off is surely controlled to be turned off, and a voltage level of an output signal of the voltage-level shifter is surely fixed at the "L" level while surely preventing flow of a through current. Another object of the invention is to provide a voltage-level shifter, in which both maximum and minimum values of an input signal are amplified by level shift at one stage, so that a speed for the level shift can be improved, and component transistors are reduced in number to simplify a structure. In order to achieve the above objects, a voltage-level shifter according to the invention is designed such that, when an input signal transits from the "L" level to the "H" level, electric charges are actively supplied to a gate of an MOS transistor to be turned off for controlling this MOS transistor to be surely turned off. According to the voltage-level shifter of the invention, there is especially provided a circuit which fixes an output signal of the voltage-level shifter at the "L" level during transition of the level of the input signal from the "L" level to the "H" level, even if the MOS transistor to be turned off is turned on, as defined by the features of claim 1. Preferred embodiments of the invention are subject matter of the dependent claims. According to the voltage-level shifter of the invention, the amplitude of the input signal is increased by the level shift at a single stage for outputting the signal of a large amplitude, so that the operation of shifting the voltage level can be performed fast, and required transistors can be reduced in number. Other objects, features and advantages of the invention will appear more fully from the following detailed description thereof taken in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings showing preferred embodiments of the invention: Fig. 1 shows a structure of a first embodiment of a voltage-level shifter of the invention; Fig. 2 shows an operation timing of the first embodiment of the voltage-level shifter of the invention; Fig. 3 shows a structure of the second embodiment of the voltage-level shifter of the invention; Fig. 4 shows an operation timing of the second embodiment of the voltage-level shifter of the invention; Fig. 5 shows a structure of a signal generation circuit used in the voltage-level shifter of the invention; Fig. 6 shows an operation timing of the signal generation circuit of Fig.5; Fig. 7 shows a structure of a voltage-level shifter in the prior art; Fig. 8 shows a basic structure of the voltage-level shifter in the prior art; Fig. 9 shows an operation timing of the voltage-level shifter in the prior art; and Fig. 10 shows a structure of another conventional voltage-level shifter. DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the invention will be described below with reference to the drawings. [First Embodiment] A voltage-level shifter of a first embodiment of the invention will now be described below. Fig. 1 shows a circuit structure, and Fig. 2 shows an operation timing. I6 indicates an input signal, 06 indicates an output signal, VCC indicates the first voltage source, VPP indicates the second voltage source and VSS indicates the ground voltage source. 601 indicates a voltage-level shifter, Qn601 and Qn602 indicate N-channel MOS transistors, Qp601 and Qp602 indicate P-channel MOS transistors, C601 indicates a capacitor, 61 indicates a delay circuit, and N601 and N602 indicate node names. The circuit structure in Fig.1 will be described below. The input signal I6 is connected to a source of the N-channel MOS transistor Qn601 and a gate of the N-channel MOS transistor Qn602. A gate of the N-channel MOS transistor Qn601 is connected to VCC, and a source of the N-channel MOS transistor Qn602 is connected to VSS. A source of the P-channel MOS transistor Qn601 and a source of the P-channel MOS transistor Qp602 are connected to the second voltage source VPP. A drain of the N-channel MOS transistor Qn601, a drain of the P-channel MOS transistor Qp601 and a gate of the P-channel MOS transistor Qp602 are connected together, and the output signal 06 is connected to the drain of the N-channel MOS transistor Qn601, the drain of the P-channel MOS transistor Qp601 and the gate of the P-channel MOS transistor Qp602. A delayed signal of the same phase as the input signal I6 is supplied to the node 602, and the capacitor C601 is connected between the nodes N601 and N602. The delay circuit 61 and the capacitor C601 connected in serial form a signal potential raising circuit 62. An operation will be described below with reference to the operation timing diagram of Fig. 2. First, when the input signal I6 is at the "L" level, the node N601 is at the "L" level, the node N602 is at the "L" level, the N-channel MOS transistor Qn602 is off, the P-channel MOS transistor Qp602 is on, the output signal 06 is at the potential of the second voltage source VPP and thus at the "H" level, and the P-channel MOS transistor Qp601 is completely turned off. When the input signal I6 transits from the "L" level to the "H" level, the node N601 attains the potential of (VCC-Vtn). Thereafter, the node N602 transits from the "L" level to the "H" level, and the node N601 attains the potential of (2xVCC-Vtn). Since the input signal I6 is at the "H" level, the N-channel MOS transistor Qn602 is completely turned off, so that the node N601 attains the potential of (2xVCC-Vtn), and the P-channel MOS transistor Qp602 is substantially or completely turned off. Then, the output signal 06 attains the "L" level, and the P-channel MOS transistor Qp601 is completely turned off, so that the node N601 attains the potential of the second voltage source VPP, and the P-channel MOS transistor Qp602 is completely turned off. The foregoing voltage-level shifter 601 has such a feature that, when the input signal I6 transits from the "L" level to the "H" level, the node N601 is set to the potential not lower than VCC, i.e., potential of (2xVCC-Vtn), whereby the P-channel MOS transistor Qp602 is substantially turned off. Thereby, it is possible to suppress a through current flowing from the second voltage source VPP to the ground voltage source VSS via the N-channel MOS transistor Qn602 and the P-channel MOS transistor Qp602. Also, the voltage level of the output signal 06 can be rapidly fixed at the "L" level. In particular, even when the first voltage source VCC supplies a low voltage, and/or there is a large potential difference between the first and second voltage sources VCC and VPP, the voltage level of the output signal 06 can be rapidly fixed at the "L" level. [Second Embodiment] A voltage-level shifter of a second embodiment of the invention will now be described below. Fig. 3 shows a circuit structure, and Fig. 4 shows an operation timing. I6 and S1 indicate input signals, 06 indicates an output signal, VCC indicates the first voltage source, VPP indicates the second voltage source and VSS indicates the ground voltage source. 801 indicates a voltage-level shifter, Qn601 and Qn602 indicate N-channel MOS transistors, Qp601 and Qp602 indicate P-channel MOS transistors, C601 indicates a capacitor, and N601 and N602 indicate node names. The circuit structure in Fig. 3 will be described below. In the voltage-level shifter 801, the input signal I6 is connected to a source of the N-channel MOS transistor Qn601 and a gate of the N-channel MOS transistor Qn602. A gate of the N-channel MOS transistor Qn601 is connection to the input signal S1. A source of the P-channel MOS transistor Qp602 is connected to the ground voltage VSS. Source of the P-channel MOS transistors Qp 601 and Qp602 are connected to the second voltage source VPP. A drain of the N-channel MOS transistor Qn601, a drain of the P-channel MOS transistor Qp601 and a gate of the P-channel MOS transistor Qp602 are connected together. The output signal 06 is connected to the drain of the N-channel MOS transistor Qn602, the gate of the P-channel MOS transistor Qp601 and the drain of the P-channel MOS transistor Qp602. A delayed signal of the same phase as the input signal I6 is supplied to the node N602, and the capacitor C601 is connected between the nodes N601 and N602. An operation will be described below with reference to the operation timing diagram of Fig. 4. The signals I6 and S1 are supplied as the input signals in Fig 3 from a signal generating circuit 401 shown in Fig. 5. The circuit structure in Fig. 5 will now be described. An inverted signal of the input signal I4 is sent to the node N402, and a NOR between the node N402 and the input signal I6 is supplied to the node N401 as a delay signal of a phase opposite to that of the node N402. The capacitor C401 is connected between the node N401 and the input signal S1. The input signal S1 is connected to a drain of the N-channel MOS transistor Qn401, of which source and gate are connected to the first voltage source VCC. An operation will be described below with reference to the operation timing diagram of Fig. 6. First, when the input signal I4 is at the "L" level, the input signal I6 in the signal generating circuit 401 is at the "L" level, the node N401 is at the "L" level, and the input signal S1 is at a potential (VCC-Vtn) which is lower than the first voltage source VCC by a value corresponding to a threshold voltage (Vtn) of the N-channel MOS transistor Qn401. When the input signal I4 transits from the "L" level to the "H" level, the signal generating circuit 401 operates such that the node N401 generates a pulse signal changing between the "L" level and the "H" level during a delay time of the input signal I6 from the node N402. Therefore, the input signal S1 connected to the node N401 via the capacitor C401 generates a pulse signal changing between a potential of (VCC-Vtn) and a potential of (2xVCC-Vtn). In the voltage-level shifter 801, when the input signal I4 to the signal generating circuit 401 is at the "L" level, the signal I6 is at the "L" level, the node N401 is at the "L" level, and the input signal I6 is at the potential (VCC-Vtn) which is lower than the first voltage source VCC by the threshold voltage (Vtn) of the N-channel-MOS transistor Qn401. In the voltage-level shifter 801 in Fig. 3. the input signal I6 is at the "L" level, the node N601 is at the "L" level, the node N602 is at the "L" level, the N-channel MOS transistor Qn602 is off, the P-channel MOS transistor Qp602 is on, the output signal 06 is at the potential of the voltage source VPP and thus at the "H" level, and the P-channel MOS transistor Qp601 is completely turned off. When the input-signal I4 to the signal generation circuit 401 transits from the "L" level to the "H" level, the signal generating circuit 401 in Fig. operates such that the node N401 generates a pulse signal changing between the "L" level and the "H" level during a delay time of the input signal I6 from the node N402. Therefore, the input signal S1 connected to the node N401 via the capacitor C401 generates a pulse signal changing between a potential of (VCC-Vtn) and a potential of (2xVCC-Vtn). In the voltage-level shifter 801 in Fig. 3, the input signal I6 transits from the "L" level to the "H" level with a delay from input-signal I4, and the N-channel MOS transistor Qn602 is completely turned on. The node N601 attains the lower one of the potential of (2xVCC-Vtn) and the potential of the first voltage source VCC because the input signal 54 has already changed its potential from (VCC-Vtn) to (2xVCC-Vtn). Assuming that VCC is 1.5V and Vtn is 0.7V, the node N601 attains the potential of the first voltage source VCC. Thereafter, the node N602 transits from the "L" level to the "H" level, and the node N101 attains the potential of (2xVCC). Therefore, the P-channel MOS transistor Qp 02 is substantially off. Then, the output signal 06 attains the "L" level, and the P-channel MOS transistor Qp601 is completely turned on, so that the node N601 is set to the potential of the second voltage source VPP, and the P-channel MOS transistor Qp602 is completely turned off. The foregoing voltage-level shifter 801 has such a feature that, when the input signal I6 transits from the "L" level to the "H" level, the voltage level of the output signal 06 can be rapidly fixed at the "L" level.

Claims: A voltage-level shifter comprising: a high voltage power source (Vpp); first and second P-channel MOS transistors (Qp601, Qp602); a first N-channel MOS transistor (Qn601) including: a source receiving an input signal (I6) having a set potential (Vcc); a gate receiving a different input signal (Vcc, S1); and a drain connected to a drain of said first P-channel MOS transistor (Qp601) and a gate of said second P-channel MOS transistor (Qp602); and a second N-channel MOS transistor (Qn602) including; a gate receiving said input signal (I6); a source that is grounded (Vss); and a drain, the potential of which serves as an output signal (06): wherein said high voltage power source (Vpp) is connected to each source of said first and second P-channel MOS transistors (Qp601, Qp602), the gate of said first P-channel MOS transistor (Qp601), the drain of said second P-channel MOS transistor (Qp602) and said drain of said second N-channel MOS transistor (Qn602) are connected to one another, and said voltage-level shifter further comprising: a signal potential raising circuit (62; N602, C601), which generates a signal (N601) of a potential exceeding the set potential (Vcc) of said input signal (16) when said input signal transits from the "L" level to the "H" ievel and supplies the generated signal to the gate of said second P-channel MOS transistor (Qp602). The voltage-level shifter according to claim 1, wherein the different signal that the gate of the first N-channel MOS transistor (Qn601) receives has a potential (VCC) of the input signal of the voltage source. The voltage-level shifter according to claim 1, further comprising: a signal generation circuit (401) which generates the different signal (S1) of a potential exceeding the set potential of said input signal (16) prior to transition of said input signal from the "L" level to the "H" level, and supplies the generated signal to the gate of said first N-channel MOS transistor (Qn601). The voltage-level shifter according to claim 3, wherein said signal generation circuit (401) includes: an inverter circuit (40) inverting a signal (14); a delay circuit (41) delaying an output signal of said inverter circuit (40) for a predetermined time and inverting the same; an NOR gate (42) producing a signal by negating a logical sum of the output signal of said inverter circuit (40) and the output signal of said delay circuit; a third N-channel MOS transistor (Qn401) having a source and a gate which are connected to a voltage source of the input signal; and a capacitor (C401) connected between a drain of said third N-channel MOS transistor and said NOR gate (42), wherein the output signal of said delay circuit forms the input signal (16), and the different signal (S1) of a potential exceeding the set potential of said input signal is generated at the drain of said third N-channel MOS transistor (Qn401). The voltage-level shifter according to claim 1, in which the signal potential raising circuit (62) comprises a series circuit including a signal delay circuit (61) for delaying the input signal (16) and a capacitor (C601) connected together in series, the capacitor in the series circuit being connected to a gate of the second P-channel MOS transistor (Qp602).

Inventors: HIRANO HIROSHIGE, HIRANO, HIROSHIGE
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1995
Main classification: H03K19
IPC codes: H03K19