Semiconductor device having a MOS gate structure and a surface protective film and method of fabricating the same

Abstract: There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (V th ) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, thereby reducing the amount of hydrogen atoms migrating to a silicon-silicon oxide interface in a cell area and, accordingly, reducing the number of Si-H chemical bonds at the interface.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device according to the preamble of claim 1 and a method of fabricating the same. More particularly, the invention relates to a device structure for reducing variations in threshold voltage V th of a power semiconductor device having an MOS gate with time to stabilize electrical characteristics, and a method of fabricating the same. Description of the Background Art Fig. 19 is a fragmentary plan view of a power insulated gate bipolar transistor (referred to hereinafter as an IGBT) as an example of the conventional semiconductor devices. Fig. 20 is a cross-sectional view taken along the line XX-XX of Fig. 19. In Figs. 19 and 20, the reference numeral 1 designates a P + substrate; 2 designates an N + layer; 3 designates an N - layer; and 4 designates a semiconductor body comprised of the P + substrate 1, the N + layer 2 and the N - layer 3. The reference numeral 5 designates a P + base layer; 6 designates an N + emitter layer; 7 designates a gate insulating film made of silicon oxide; 8 designates a gate electrode of polysilicon; 9 designates a gate interconnection line of Al; 10 designates an emitter electrode; 11 designates guard rings; 12 designates a passivation film for isolation between the gate electrode 8 and the emitter electrode 10; 13 designates an emitter wire bonding region; 14 designates a surface protective film of silicon nitride for covering the IGBT surface except the emitter wiring bonding region 13 and a gate bonding pad (not shown) which is a part of the gate interconnection line 8; 15 designates a channel stopper; 16 designates a silicon oxide film; 17 designates a polysilicon film; 18 designates a passivation film; and 19 designates a collector electrode. Fig. 21 is a flow chart of the fabrication process of the conventional IGBT. Referring to Fig. 21, the semiconductor body 4 is initially formed, and the P + base layer 5, and P wells, P + layers serving as the guard rings 11 are formed in the surface of the N - layer 3 of the semiconductor body 4. The gate insulating film 7 of silicon oxide is formed on the surface of the P + base layer 5, and a polysilicon film is formed on the surface of the gate insulating film 7. Then the N + emitter layer 6 and the channel stopper 15 are formed by diffusion, and the passivation films 12 and 17 are formed. The gate interconnection line 9 and the emitter electrode 10 are formed as Al electrodes. Thereafter, the surface protective film 14 is formed to cover the IGBT surface except the emitter wire bonding region 13 and the gate bonding pad which is a part of the gate interconnection line 9. A silicon nitride film serving as the surface protective film 14 is formed by plasma CVD process (referred to hereinafter as P-CVD process) at a temperature of about 300 to 400°C in an atmosphere of a mixed silane-ammonia gas. Then the IGBT is exposed to radiation for lifetime control thereof and is subjected to heat treatment at a temperature of 300 to 400°C to eliminate distortion resulting from the radiation. The surface protective film 14 is formed for the following purposes: (1) to prevent shorting of the emitter electrode 10 and gate interconnection line due to mechanical scratches, (2) to prevent shorting of an aluminum electrode (not shown) formed on the guard rings 11 in a peripheral area of a chip due to external contamination, and (3) to prevent moisture from corroding aluminum thin wires of the device. In the past, oxide films formed by the low pressure CVD process (referred to hereinafter as LP-CVD process), such as phospho-silicate glass (PSG), have been used as the surface protective film of the IGBT. However, silicon nitride films formed by the P-CVD process have recently been used as the surface protective film since the material of the silicon nitride films is more air-tight and mechanically stronger as a surface protective film than that of the PSG films. In this manner, the conventional IGBT is constructed as above described using the silicon nitride film formed by the P-CVD process as the surface protective film and is fabricated through the above-mentioned fabrication process. To evaluate the long-term stability of electrical characteristics of the IGBT, a HTGB test (high temperature gate bias test) was performed. The HTGB test is to continuously apply a gate signal V GES = +20 V or -20 V between the gate and emitter, with the emitter and collector grounded, at an atmospheric temperature T a = 125°C to determine the relation between a V GES voltage application time and variations in threshold voltage V th with time. Fig. 22 is a graph of the result of the HTGB test made on the conventional semiconductor devices. The test conditions in Fig. 22 are an atmospheric temperature Ta = 125°C and V GES = ±20 V for an IGBT, and an atmospheric temperature Ta = 150°C and V GES = -30 V for an MOSFET. Variations in threshold voltage V th is represented by the percentage of V th variations. The MOSFET used herein is constructed such that the P + substrate is removed from the structure of Fig. 20 and the N + layer 2 is replaced with an N + substrate. The fabrication process of the MOSFET does not include the radiation and the heat treatment for distortion elimination of Fig. 21. Referring to Fig. 22, for the IGBT, with V GES = +20 V applied, the V th variation percentage is several percent which presents no particular problems in terms of long-term stability of the electrical characteristics. For the IGBT, with V GES = -20 V applied, V th decreases with the passage of the V GES application time, and the V th variation percentage exceeds 10 % after an elapse of 1000 hours. In addition, the V th variation does not tend to become saturated over 1000 hours. Thus, the conventional IGBT has been disadvantageous in long-term stability of the electrical characteristics. For the conventional MOSFET, with V GES = -30 V applied, V th decreases with the passage of the V GES application time and tends to become saturated after an elapse of 500 hours, as compared with the IGBT. However, the MOSFET exhibits the V th variation percentage reaching 10 %. Thus, the conventional MOSFET has been disadvantageous in long-term stability of the electrical characteristics. The application of a negative voltage V GES varies the threshold voltage V th which in turn is slow in becoming saturated, possibly for the reasons to be described below. The silicon nitride film formed by the P-CVD process contains a large amount of hydrogen atoms. For example, the number of Si-H chemical bonds in the silicon nitride film formed by the P-CVD process is 1.0 × 10 22 to 1.6 × 10 22 cm -3 by measurement using FT-IR (Fourier transform infrared spectroscopy) technique. The number of Si-H chemical bonds in the PSG film is on the order of 0.4 × 10 22 cm -3 . The hydrogen atoms in the silicon nitride film readily migrate through the surface protective film 14 of silicon nitride, the aluminum electrodes such as the gate interconnection line 9 and emitter electrode 10, the passivation film 17 and the gate insulating film 7 of silicon oxide depending upon the atmospheric temperatures and the polarity and magnitude of the applied voltage to reach a silicon-silicon oxide interface at the surface of the semiconductor body 4 without difficulty. Dangling bonds at the silicon-silicon oxide interface are bonded to hydrogen atoms from the silicon nitride film to form Si-H chemical bonds at the silicon-silicon oxide interface, resulting in an unstable interface state. It takes time to stabilize the interface state, which is considered to cause the difficulty in saturating the varying threshold voltage V th . One of the reasons why such a problem is not encountered for the conventional PSG film is considered to be the fact that the PSG film contains fewer Si-H chemical bonds and, accordingly, fewer hydrogen atoms than the silicon nitride film formed by the P-CVD process. Further, the radiation for lifetime control of the IGBT increases the defects at the silicon-silicon oxide interface to accelerate the formation of Si-H bonds at the silicon-silicon oxide interface, probably resulting in increased V th variations with time. Document US-A-5,196,354 discloses a semiconductor device and a method of manufacturing the same, wherein a passivation layer of an organic material is provided over the part of the substrate in which the field effect transistor section is not located. Thus, the first semiconductor layer includes a first semiconductor region in which at least a second semiconductor region is provided. A MOS-FET section comprises a channel region, a gate insulating film and a first gate portion provided thereon. However, the electrical characteristics of the semiconductor device are not sufficient. Document JP-A-62 73 766 discloses a further semiconductor device with a specific planar structure to improve a high voltage withstanding of the semiconductor device. In detail, a plate is formed outside of an effective element region in order to form a resistive field plate at an end of a source electrode. At the other end, the effective element is provided including a first semiconductor layer with a first semiconductor region and a second semiconductor region as well as a channel region. Even if the withstand characteristic concerning high voltages is thus improved there still exists a problem concerning, e. g. variations in threshold voltage. Document "IEEE Transactions VOL. ED-27, No. 2, pages 340 to 343" discloses a further high performance planar power MOSFET defining a specific topological design. In order to improve a breakdown voltage and to avoid latch-up phenomena a specific design is used. Finally, document JP-A-42 12 468, on which the preamble of claim 1 is based, discloses a semiconductor device with a first semiconductor layer in which at least one first semiconductor region is formed so that the first semiconductor layer is exposed in a peripheral portion of its major surface, while it is exposed in the form of an insular region in a central portion of the major surface. A second semiconductor region which is formed on the surface of the first semiconductor region comprises a channel region between the second semiconductor region and the insular region. A gate portion with a gate insulating film is formed on a surface of the channel region. Over the surface of the first gate portion a first main electrode is formed, while a second main electrode is formed on the second major surface of the first semiconductor layer. The peripheral portion of the first major surface is covered by an integral surface protective film. However, also this semiconductor device is disadvantageous in long term stability of the electric characteristics, particularly with respect to the breakdown voltage characteristic. It is therefore an object of the present invention to provide a semiconductor device and a method of fabricating the same which is electrically highly stable and shows a satisfactory breakdown voltage characteristic by using a conventional fabrication line. Concerning the semiconductor device this object is accomplished by the measures indicated in the present independent claim 1. Concerning the method of fabricating a semiconductor device, the above mentioned object is achieved by the measures indicated in independent claim 9. The advantages of the invention will become apparent and obvious to those skilled in the pertinent art upon referring to the following description provided in connection with the accompanying drawings of which: BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a fragmentary plan view of a power IGBT according to a first preferred embodiment of the present invention; Fig. 2 is a fragmentary cross-sectional view taken along the line II-II of Fig. 1; Fig. 3 is a fragmentary plan view taken along the line III-III of Fig. 2 at the surface of a semiconductor body; Fig. 4 is a fragmentary plan view illustrating a plan configuration of a gate electrode of Fig. 1; Fig. 5 is a flow chart of fabrication process of the semiconductor device according to the present invention; Figs. 6 to 12 are cross-sectional views illustrating the fabrication process of the semiconductor device according to the present invention; Fig. 13 is a cross-sectional view of a test piece for use in a C-V test; Fig. 14 is a graph illustrating ΔV FB (normalization value) for the C-V test; Fig. 15 is a graph illustrating a breakdown voltage characteristic yield of the semiconductor device according to the present invention; Fig. 16 is a fragmentary plan view of the semiconductor device according to a second preferred embodiment of the present invention; Fig. 17 is a fragmentary cross-sectional view taken along the line XVII-XVII of Fig. 16; Fig. 18 is a graph for comparison between a threshold voltage V th variation percentage of the present invention and a threshold voltage V th variation percentage of the background art; Fig. 19 is a fragmentary plan view of a conventional semiconductor device; Fig. 20 is a cross-sectional view taken along the line XX-XX of Fig. 19; Fig. 21 is a flow chart of fabrication process of the conventional semiconductor device; and Fig. 22 is a graph of an HTGB test result for the conventional semiconductor device. DESCRIPTION OF THE PREFERRED EMBODIMENTS First Preferred Embodiment Fig. 1 is a fragmentary plan view of a power IGBT according to a first preferred embodiment of the present invention. Fig. 2 is a fragmentary cross-sectional view taken along the line II-II of Fig. 1. Fig. 3 is a fragmentary plan view taken along the line III-III of Fig. 2 at the surface of a semiconductor body. Fig. 4 is a fragmentary plan view illustrating a plan configuration of a gate electrode shown in Fig. 1. In the fragmentary plan view of the gate electrode in Fig. 4, only the gate electrode and portions formed simultaneously with the gate electrode are illustrated and other portions are not illustrated. In Figs. 1 and 2, the reference numeral 1 designates a P + substrate serving as a second semiconductor layer; 2 designates an N + layer; 3 designates an N - layer. The N + layer 2 and the N - layer 3 form a first semiconductor layer. The reference numeral 4 designates a semiconductor body comprised of the P + substrate 1, the N + layer and the N - layer 3; 5 designates a P + base layer serving as a first semiconductor region; 6 designates an N + emitter layer serving as a second semiconductor region; 7 designates a gate insulating film of silicon oxide; 8 designates a gate electrode of polysilicon serving as a gate; 9 designates a gate interconnection line of Al; 10 designates an emitter electrode of Al serving as a first main electrode; 11 designates guard rings which are P + diffusion regions; 12 designates a passivation film of PSG serving as an interlayer insulating film for isolation between the gate electrode 8 and the emitter electrode 10; 14 designates a surface protective film which is a semi-insulation film of silicon nitride for covering a peripheral area surface of the IGBT; 15 designates a channel stopper; 16 designates a silicon oxide film; 17 designates a polysilicon film; 18 designates a passivation film; and 19 designates a collector electrode serving as a second main electrode. Referring to Fig. 3, the N - layer 3 is exposed in the form of insular regions on the surface of a central portion of the device, and the P + base layer 5 covers the surface except the insular regions of the N - layer 3. The N + emitter layer 6 is formed in the P + base layer 5, with narrow portions of the P + base layer 5 sandwiched between the N + emitter layer 6 and the insular regions of the N - layer 3. The narrow portions of the P + base layer 5 between the insular regions of the N - layer 3 and the N + emitter layer 6 serve as channel regions. The gate insulating film 7 on the surface of the channel region is formed integrally over the plurality of channel regions. The integral gate electrode 8 of substantially the same configuration as the gate insulating film 7 is formed on the surface of the integral gate insulating film 7, as shown in Fig. 4. As the number of channels opposed to the gate electrode 8 increases, gate potentials opposed to the respective channels are not necessarily uniform in the gate electrode 8. To provide uniform gate potentials, the gate interconnection line 9 of aluminum is provided to connect the portions of the gate electrode 8 opposed to the respective channels (Figs. 1 and 2). The gate interconnection line 9 extends to the center of the device and is connected to a gate bonding pad (not shown) in the center of the device. Connection lines to the exterior are bonded to the gate bonding pad. An area in which the gate interconnection line 9 and the bonding pad are provided is a gate wiring area 32. The emitter electrode 10 is formed on the surface of the gate electrode 8 except the portion where the gate interconnection line 9 is formed, with the passivation film 12 formed therebetween. The emitter electrode 10 short-circuits the P + base layer 5 and the N + emitter layer 6 on the surface of the semiconductor body 4 and is electrically isolated from the gate interconnection line 9 by a trench. An area in which the emitter electrode 10 is formed is a cell area 31 (Figs. 1 and 2). The N - layer 3 is exposed in a peripheral portion surrounding the surface of the semiconductor body 4. The peripheral portion generally corresponds to a device peripheral area 30 on the surface of the semiconductor body 4 other than the gate wiring area 32 and the cell area 31. The plurality of annular guard rings 11 are formed in the N - layer 3 in the peripheral portion to surround the outer periphery of the cell area 31. The channel stopper 15 which is an N + diffusion region is formed on the outermost edge of the N - layer 3 in the peripheral portion to surround the guard rings 11. The inner periphery of the channel stopper 15 is adapted such that the channel stopper 15 are generally equally spaced from the outermost guard ring 11 over the entire circumference. The surface protective film 14 which is a semi-insulation film of silicon nitride directly covers the surface of the channel stopper 15, and covers the surfaces of the N - layer 3 in the peripheral portion and the outer peripheral portion of the P + base layer 5, with the silicon oxide film 16 and passivation film 18 formed therebetween. The surface protective film 14 is integrally formed such that an inner peripheral end thereof overlapping and covering the outer peripheral portion of the emitter electrode 10 and an outer peripheral end thereof extends to the outer end of the channel stopper 15 to prevent the surface of the passivation film 18 from being exposed. An area in which the surface protective film 14 is formed is the device peripheral area 30. An MOSFET is similar in construction to the IGBT except that the MOSFET does not include the P + substrate 1 of the IGBT. That is, the MOSFET is constructed such that the P + substrate 1 of the IGBT is removed and the N + layer 2 of the IGBT is replaced with an N + substrate on which a drain electrode is formed. A method of fabricating a semiconductor device will now be described hereinafter. Fig. 5 is a flow chart of the fabrication process of an IGBT as an example of the semiconductor device of the present invention. Figs. 6 to 12 are cross-sectional views illustrating the fabrication process of the IGBT. Referring to Fig. 5 and Figs. 6 to 12, the N + layer 2 and the N - layer 3 are formed on the P + substrate 1 in this order by the epitaxial growth technique to form the semiconductor body 4 (Fig. 6). When the N + layer 2 and the N - layer 3 are thicker than the P + substrate 1, a P + layer may be formed on an N substrate by the epitaxial growth technique. Otherwise, a P + layer and an N layer joined together may be formed on a P or N substrate by diffusion. The silicon oxide film 16 is formed on the surface of the semiconductor body 4 and is then etched by photolithography, and the P wells and the P + base layer 5 are formed by diffusion (Fig. 7). The oxide film 16 is then etched, if necessary, after photolithography process, and the gate insulating film 7 of silicon oxide is formed by thermal oxidation. The gate electrode 8 of polysilicon is formed on the surface of the gate insulating film 7 after photolithography process (Fig. 8). Photolithography process and thermal diffusion process are performed to form the N + emitter layer 6 in the P + base region 5 and the channel stopper 15 in the peripheral portion surface of the N - layer 3 (Fig. 9). The passivation films 12 and 18 of PSG are formed on the top surface, and electrode contact portions are etched (Fig. 10). The gate interconnection line 9 and the emitter electrode 10 are formed by Al-Si sputtering (Fig. 11). For the IGBT, radiation for lifetime control and heat treatment for elimination of distortion generated in portions subjected to the radiation are performed, and the surface protective film 14 is formed on the device top surface. The order of the process steps is the feature of the method of fabricating the IGBT according to the present invention. Specifically, according to the present invention, the radiation for lifetime control is performed first. Then the heat treatment is performed to eliminate the distortion generated in the portions subjected to the radiation. Finally, the surface protective film 14 is formed on the top surface of the device. The heat treatment for distortion elimination is performed, for example, at a temperature of about 300 to 400°C. The final P-CVD process in an atmosphere of a mixed silane-ammonia gas is performed at a temperature slightly lower than the heat treatment temperature for distortion elimination. The film may be formed at a temperature of about 300°C with the current state of the art. To form the surface protective film 14, a semi-insulation silicon nitride film is formed over the device surface by the P-CVD process, and a mask is formed by photolithography, and then plasma etching is performed in an atmosphere of CF 4 and O 2 to remove the silicon nitride film in the cell area 31 centrally of the device and in the gate wiring area 32 is removed, with the silicon nitride film left only in the device peripheral area 30. This completes the fabrication process (Fig. 12). In the above described method, the radiation for lifetime control, the heat treatment for distortion elimination, and the step of leaving the silicon nitride film only in the device peripheral area 30 by the P-CVD process are carried out in this order. Only the arrangement in which the silicon nitride film is left only in the device peripheral area 30 can considerably reduce the variations in threshold voltage V th . Thus, the above-described process may be replaced with a process of forming the electrode by Al-Si sputtering (Fig. 11), forming the semi-insulation silicon nitride film only in the device peripheral area 30 by the P-CVD process, performing the radiation for lifetime control, and then performing the heat treatment for distortion elimination. Such a method can provide an electrically highly stable IGBT with a satisfactory breakdown voltage characteristic by using a conventional fabrication line without a new fabrication line. A method of fabricating an MOSFET is similar to the method of fabricating the IGBT except that the radiation for lifetime control and the heat treatment for distortion elimination are not performed. Operation will be described below. The above stated IGBT according to the present invention includes the semi-insulation silicon nitride film formed by the P-CVD process only in the device peripheral area 30 other than the gate wiring area 32 and cell area 31. Hydrogen atoms to be bonded to dangling bonds at the silicon-silicon oxide interface are contained only in the silicon nitride film in the device peripheral area 30. The hydrogen atoms, if moved, migrate to the silicon-silicon oxide interface under the surface protective film 14, and fewer hydrogen atoms migrate up to the cell area 31. This decreases the number of hydrogen atoms bonded to the dangling bonds at the silicon-silicon oxide interface in the channel regions under the gate electrode 8 in the cell area 31 and, accordingly, reduces the number of Si-H chemical bonds generated at the silicon-silicon oxide interface, to prevent an unstable interface state. Therefore, the phenomenon in which the threshold voltage V th varies over a long time period and requires long time to be saturated is difficult to occur. Operation of the MOSFET is similar to that of the IGBT when the silicon nitride film is formed only in the device peripheral area 30. For the IGBT, the radiation for lifetime control and the heat treatment for distortion elimination are essential. If the formation of the silicon nitride film by the P-CVD process after the two process steps increases the number of defects at the silicon-silicon oxide interface due to the radiation to increase the dangling bonds, the subsequent heat treatment reduces the number of defects at the silicon-silicon oxide interface to reduce the number of dangling bonds and, accordingly, the number of Si-H chemical bonds generated at the silicon-silicon oxide interface, preventing the unstable interface state. The influence of the radiation is eliminated, and the acceleration of the V th variations due to the radiation is difficult to occur. The use of the semi-insulation silicon nitride film as the surface protective film 14 causes a slight current to flow between the emitter and channel stopper to produce an electric field shield effect in the device peripheral area 30. This provides a shield against external impurity ions, to improve the breakdown voltage characteristic of the device. For example, an IGBT having a breakdown voltage as high as 1700 V requires the electric field shield effect using the semi-insulation silicon nitride film. To simply examine the evaluation of the V th variations for an MIS structure (metal insulator semiconductor structure) as the premise of the present invention, a C-V test (capacitance-voltage test) was performed under various conditions. Fig. 13 is a cross-sectional view of a test piece used for the C-V test. In Fig. 13, the reference numeral 40 designates a surface protective film; 41 designates an aluminum electrode; 42 designates a thermal oxidation film; 43 designates an N-type silicon layer; and 44 designates a capacitance measuring device. The C-V test employs the test piece as above described for measuring a voltage and capacitance between the aluminum electrode 41 and the N-type silicon layer 43, with the voltage varied, to determine a flat-band voltage V FB between the thermal oxidation film 42 and the N-type silicon layer 43. There is a correlation between the flat-band voltage V FB and the threshold voltage V th . The value of variation ΔV FB of the flat-band voltage V FB is determined under various conditions such as the presence/absence of the surface protective film 40 of the test piece and processing conditions. On the basis of the value ΔV FB is evaluated and examined the value of variation ΔV th of the threshold voltage V th of the surface protective film 14 of a device having an MOS gate. As the test piece for the C-V test was used a (100) crystal plane oriented N-type silicon on which was formed a silicon thermal oxidation film of about 1000 Å in thickness, with aluminum sputtered on the surface thereof for use as an electrode. After the aluminum electrode 41 was formed, the surface protective film 40 was formed. A P-CVD nitride film containing a large amount of hydrogen atoms and an LP-CVD oxide film containing a small amount of hydrogen atoms were selected as the surface protective film 40. For hydrogen sintering, heat treatment was performed in a high-temperature furnace in an atmosphere of hydrogen at a temperature of 400°C for 30 minutes. The radiation is an electron beam irradiation which is a conventional IGBT carrier lifetime control process, followed by heat treatment for distortion elimination. spec. protective film hydrogen sintering radiation & heat treatment ΔV th (normalization value) judgment A no film not done not done 0.10 ○ B LP-CVD oxide film not done not done 0.10 ○ C P-CVD nitride film not done not done 0.50 ▵ D no film done not done 0.45 ▵ E LP-CVD oxide film not done done 0.10 ○ F P-CVD nitride film not done done 1.00 × G no film done done 0.90 × H hydrogen sintering after radiation & heat treatment 0.10 ○ Table 1 illustrates the conditions and results of the C-V test. Additional explanation of Table 1 will be described below. (1) To determine the value of variation ΔV th , the flat-band voltage V FB was first determined, and then the test piece was held at 150°C, and a 30 V d.c. bias voltage was applied for 5 minutes, with the aluminum electrode 41 being negative. The flat-band voltage V FB was measured again to calculate the difference ΔV FB between the first and second V FB measurements. (2) The LP-CVD oxide film in spec. B was a PSG film formed by the LP-CVD process. (3) The P-CVD nitride film in spec. C was a semi-insulation film containing a large amount of silicon. (4) The radiation and heat treatment were performed after the protective film was formed in specs. E and F. (5) The radiation and heat treatment were performed after the hydrogen sintering in spec. G. (6) No protective film was formed in spec. H. (7) ΔV FB (normalization value) was a ratio of ΔV FB in each spec. to ΔV FB in spec. F. Fig. 14 is a graph illustrating ΔV FB (normalization value) for the C-V test of Table 1. Referring to Fig. 14, ΔV FB (normalization value) is low in specs. A, B and E with few hydrogen atoms and is high in specs. C and D with a large amount of hydrogen atoms. The radiation after the formation of the protective film further increases ΔV FB (normalization value). It will be apparent from the graph of Fig. 14 that: (1) V FB is varied by introduction of hydrogen atoms into the MIS structure (specs. C and D), (2) V FB is varied more widely by the radiation in addition to the introduction of hydrogen atoms (specs. F and G), (3) V FB is not varied by the radiation only (spec. E), and (4) V FB is not varied by the introduction of hydrogen atoms after the radiation and the heat treatment (spec. H). Therefore, it will be understood that: (i) it is necessary to prevent hydrogen atoms from entering the cell area 31 having the channels in the MIS structure or the device having the MOS gate, (ii) it is also necessary to prevent hydrogen atoms from entering the cell area 31, particularly in the IGBT performing lifetime control, and (iii) the introduction of hydrogen atoms after the radiation and heat treatment exerts no influence on the V FB variations in the IGBT performing lifetime control. An electrically highly stable IGBT with a satisfactory breakdown voltage characteristic is accomplished by the provision of the surface protective film 14 which is the semi-insulation silicon nitride film formed by the P-CVD process only in the device peripheral area 30 like the first preferred embodiment and by the process steps of performing radiation for lifetime control, performing heat treatment for distortion elimination, and then forming the surface protective film 14 on the device top surface. An electrically highly stable MOSFET with a satisfactory breakdown voltage characteristic is accomplished by the provision of the surface protective film 14 which is the semi-insulation silicon nitride film formed by the P-CVD process only in the device peripheral area 30 other than the gate wiring area 32 and the cell area 31. Fig. 15 is a graph illustrating a breakdown voltage characteristic yield of the structure of the first preferred embodiment. Referring to Fig. 15, the guard ring structure A includes eight guard rings 11 surrounding the outer periphery of the cell area 31, and the guard ring structure B includes ten guard rings 11 such that a distance between the outermost guard ring 11 and the channel stopper 15 is 1.3 times the distance therebetween of the guard ring structure A. It will be appreciated from the graph of Fig. 15 that there is a difference in breakdown voltage characteristic yield between the guard ring structure A and the guard ring structure B when the conductivity of the surface protective film 14 is less than 1 × 10 -13 /Ωcm, but there is no difference in breakdown voltage characteristic yield therebetween with the increasing breakdown voltage characteristic yield when the conductivity is not less than 1 × 10 -13 /Ωcm. This indicates not only the improvement in breakdown voltage characteristic by the electric field shield effect but also that the device breakdown voltage characteristic is stabilized by the use of the semi-insulation surface protective film 14 with the conductivity of not less than 1 × 10 -13 /Ωcm. This increases the degree of freedom to determine the guard ring structure dimension and the degree of freedom of design, for example, the stable breakdown voltage characteristic independent of variations in fabrication process of the guard ring structure. However, an excessively high conductivity eliminates the function of the insulating film. Thus, the conductivity of the surface protective film 14 is required to be on the order of 1 × 10 -14 to 1 × 10 -10 (1/Ωcm) and is preferably 1 × 10 -13 to 1 × 10 -11 (1/Ωcm) which permits easy control of the conductivity of the semi-insulation silicon nitride film by measuring the refractive index of the film. Second Preferred Embodiment Fig. 16 is a fragmentary plan view of the IGBT according to a second preferred embodiment of the present invention. Fig. 17 is a fragmentary cross-sectional view taken along the line XVII-XVII of Fig. 16. Referring to Figs. 16 and 17, the IGBT comprises the surface protective film 14 formed in the gate wiring area 32 and the device peripheral area 30. The emitter electrode 10 is electrically isolated from the gate interconnection line 9 by a narrow trench. The emitter electrode 10 and the gate interconnection line 9 which are Al-Si sputtering film are easily scratched, for example, when the semiconductor device is handled by a handling device during the fabrication process, resulting in shorting of the emitter electrode 10 and the gate interconnection line 9. However, such a failure is prevented by the surface protective film 14 extending to the surface of the narrow trench. In addition, since there is no channel regions serving as cells under the gate wiring area 32, the covering of the semi-insulation surface protective film 14 of silicon nitride formed by the P-CVD process and containing a large amount of hydrogen atoms does not cause the V th variations. Therefore, an electrically highly stable IGBT is accomplished, with shorting of the emitter electrode 10 and the gate interconnection line 9 being prevented, like the first preferred embodiment. Further, an electrically highly stable MOSFET is accomplished, with shorting of the emitter electrode 10 and the gate interconnection line 9 being prevented, like the first preferred embodiment by the provision of the surface protective film 14 in the gate wiring area 32 and the device peripheral area 30 of the MOSFET. Third Preferred Embodiment The third preferred embodiment according to the present invention includes an IGBT device structure identical with the conventional structure of Fig. 19 but fabricated by the process corresponding to that of Fig. 5 and Figs. 6 to 12. Specifically, the third preferred embodiment is similar to the first preferred embodiment in the process steps between the formation of the semiconductor body 4 (Fig. 6) and the electrode formation by Al-Si sputtering (Fig. 11). Then radiation is performed for lifetime control, and heat treatment is performed to eliminate distortion, and the surface protective film 14 is finally formed on the device top surface. The surface protective film 14 on the device top surface is a semi-insulation silicon nitride film formed by the P-CVD process to cover the IGBT surface except the emitter wire bonding region 13, the gate interconnection line, and the gate bonding pad which is a part of the gate interconnection line. As concluded from the C-V test result that (iii) the introduction of hydrogen atoms is permitted after the radiation for lifetime control and heat treatment for distortion elimination in the IGBT performing lifetime control, the use of the fabrication method of the third preferred embodiment allows defects generated due to the radiation to be reduced by the heat treatment to reduce the number of dangling bonds at the silicon-silicon oxide interface. The Si-H chemical bonds becomes difficult to generate at the silicon-silicon oxide interface. For this reason, if the P-CVD nitride film containing a large amount of hydrogen atoms is provided in the cell area 31, the number of Si-H chemical bonds is reduced at the silicon-silicon oxide interface in the cell area 31, providing a stable interface state. Thus, there is provided an electrically highly stable IGBT of the conventional construction with a small amount of long-term V th variations, wherein shorting of the emitter electrode 10 and gate interconnection line 9 is prevented, like the first preferred embodiment. Fig. 18 is a graph for comparison of the percentage of variations in threshold voltage V th between the present invention and the background art. Referring to Fig. 18, the percentage of variations in threshold voltage after a reverse bias test is a little over 15 % and a little over 10 % for the IGBT of the conventional construction having the protective film covering 90 % and 70 % of the cell area, respectively. The percentage of variations in threshold voltage after the reverse bias test is about 2 % for the IGBT of the first preferred embodiment of the present invention having the protective film covering 0 % of the cell area, and the percentage is about 2 % for the IGBT of the second preferred embodiment of the present invention having the protective film covering 10 % of the cell area. The first and second preferred embodiments provide the percentage generally equal to the percentage of variations in threshold voltage for the conventional IGBT having the PSG film containing a small amount of hydrogen atoms and formed by the LP-CVD process. For the IGBT of the third preferred embodiment having the protective film covering 75 % of the cell area and fabricated by the process of performing radiation, performing heat treatment for distortion elimination, and then forming the silicon nitride surface protective film by the P-CVD process, the percentage of variations in threshold voltage is a little higher than but generally equal to the percentages of the first and second preferred embodiments. In this manner, the first, second and third preferred embodiments achieve the electrically highly stable semiconductor device with the MOS gate having a satisfactory breakdown voltage characteristic. The above-mentioned preferred embodiments describe the power semiconductor device having the MOS gate. However, the present invention is also applicable to semiconductor integrated circuit devices, such as memories, having an MOS gate. While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.

Claims: A semiconductor device comprising: a first semiconductor layer (3) of a first conductivity type having first and second major surfaces; at least one first semiconductor region (5) of a second conductivity type formed selectively in said first major surface of said first semiconductor layer so that said first semiconductor layer is exposed in a peripheral portion (30) of said first major surface and said first semiconductor layer is exposed in the form of at least one insular region in a central portion of said first major surface; at least one second semiconductor region (6) of the first conductivity type formed in a surface of said first semiconductor region (5), with a channel region provided between said second semiconductor region (6) and said at least one insular region of said first semiconductor layer (3), a gate insulating film (7) formed on a surface of said channel region; a first gate portion (8) formed on said gate insulating film; a first main electrode (10) formed over a surface of said first gate portion (8), with an interlayer insulating film (12) therebetween, for covering a surface of said second semiconductor region (6) and electrically connected to said second semiconductor region, said first main electrode (10) having an end extending to a boundary between said peripheral portion (30) of said first major surface and the central portion thereof; a second main electrode (19) formed on said second major surface of said first semiconductor layer, and an integral surface protective film (14) for covering at least said peripheral portion (30) of said first major surface other than the central portion of said first major surface, characterized by a second gate portion (17) which is not covered by said main electrode (10); a gate interconnection line (9) formed selectively on the surface of said second gate portion (17); a trench formed between said first main electrode (10) and said gate interconnection line (9) for electrical isolation therebetween; wherein said first gate portion (8) and said second gate portion (17) are electrically connected by said gate interconnection line (9). The semiconductor device of claim 1, characterized in that said at least one insular region is a plurality of insular region, said at least one first semiconductor region (5) is a plurality of first semiconductor regions, and said at least one second semiconductor region (6) is a plurality of second semiconductor regions. The semiconductor device of claim 1 or 2, characterized in that said integral surface protective film (14) extends from said peripheral portion (30) of said first major surface to a surface of said first main electrode (10) at said end. The semiconductor device of claim 1 or 2, characterized by a second semiconductor layer (1) of the second conductivity type formed between said second major surface of said first semiconductor layer (3) and said second main electrode (19). The semiconductor device according to any of claims 1 to 4, characterized in that said integral surface protective film (14) extends from a surface of said gate interconnection line (9) through said trench to the surface of said first main electrode (10). The semiconductor device of claim 5, characterized in that said integral surface protective film (14) is a semi-insulation film having a conductivity ranging from 1 x 10 -14 to 1 x 10 -10 (1/Ω). The semiconductor device of claim 5, characterized in that said integral surface protective film (14) is a semi-insulation film having a conductivity ranging from 1 x 10 -13 to 1 x 10 -11 (1/Ω). The semiconductor device of claim 5, characterized in that said integral surface protective film (14) is a nitride film. A method of fabricating a semiconductor device, comprising the steps of: forming a first semiconductor layer (3) of a first conductivity type having first and second major surfaces on a second semiconductor layer (1) of a second conductivity type having first and second major surfaces such that said second major surface of said first semiconductor layer contacts said first major surface of said second semiconductor layer to form a semiconductor body (4); selectively forming at least one first semiconductor region (5) of the second conductivity type in said first major surface of said first semiconductor layer so that said first semiconductor layer is exposed in a peripheral portion of said first major surface of said first semiconductor layer and said first semiconductor layer is exposed in the form of at least one insular region in a central portion of said first major surface of said first semiconductor layer; forming at least one second semiconductor region (6) of the first conductivity type in a surface of said first semiconductor region, with a channel region provided between said second semiconductor region and said at least one insular region of said first semiconductor layer in the surface of said at least one first semiconductor region; forming a gate insulating film (7) on a surface of said channel region; forming a first gate portion (8) on said gate insulating film; forming a second gate portion (17) electrically connected to said first gate portion; forming an interlayer insulating film (12) on the surfaces of said first and second gate portions; forming a first main electrode (10) electrically connected to said at least one second semiconductor region with said interlayer insulating film therebetween, said first main electrode extends to a boundary between the peripheral portion of said first major surface of said first semiconductor layer and the central portion thereof; selectively forming a gate interconnection line (9) on the surface of said second gate portion (17) to provide uniform gate potentials, such that a trench is formed between said first main electrode (10) and said gate interconnection line (9) for electrical isolation therebetween; performing radiation for lifetime control; performing heat treatment for eliminating distortion; integrally forming a surface protective film (14) at least over the peripheral portion of said first major surface of said first semiconductor layer other than the central portion thereof after said steps of performing radiation and performing heat treatment; and forming a second main electrode (19) on said second major surface of said second semiconductor layer. A method of fabricating a semiconductor device according to claim 9, characterized in that said step of integrally forming a surface protective film (14) includes integrally forming said surface protective film from a surface of said gate interconnection line (9) to an inside of said trench and a surface of said first main electrode (10) in the vicinity of said trench. A method of fabricating a semiconductor device according to claim 9, characterized in that said step of integrally forming a surface protective film (14) includes forming said surface protective film over the entire top surface except a part of a surface of said first main electrode (10) and a part of a surface of said gate interconnection line (9).

Inventors: MOCHIZUKI KOUICHI, YANO MITSUHIRO, MOCHIZUKI, KOUICHI, YANO, MITSUHIRO, MOCHIZUKI, KOUICHI, C/O FUKURYO SEMICONDUCTOR, YANO, MITSUHIRO, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1995
Main classification: H01L29
IPC codes: H01L29, H01L21, H01L23