NT2 UNIT FOR AN ATM NETWORK

Abstract: The NT2 (Network Termination type 2) unit comprises a terminal and control unit and an arbitrary number of identical switching units (39) which are interconnected in a loop configuration by means of two connecting lines (123, 124). Similarly to an NT1 (Network Termination type 1) unit, each of said switching units (39) comprises two mutually opposed transmitting paths (23, 24) for ATM (Asynchronous Transfer Mode) cells as well as two input/output circuits (22.1, 22.2) to which said connecting lines (123, 124) are connected. Said switching unit (39) further comprises a third input/output circuit (22.3) allowing the connection of terminal equipment. Finally, it is provided with an extractor (31) and an inserter (32) which are inserted in said transmitting paths (23, 24) and are connected to said third input/output circuit (22.3) via connecting lines (35.1, 35.2). According to address indications contained in the cells, said extractor (31) directs incoming cells either to the second or to the third input/output circuit (22.2 resp. 22.3). Said inserter (32) multiplexes incoming cells to the first input/output circuit (22.1). The switching unit (39) thus provides a switching facility operating in one direction which allows a clear arrangement and a flexible and economical production of the NT2 unit.

Description: NT2 UNIT FOR AN ATM NETWORK The present invention refers to an NT2 unit for an ATM net¬ work according to the preamble of claim 1. The designation ATM (asynchronous transfer mode) refers to a wide band communication technology in the range of ap¬ proximately 10 to 622 Mbit/s. A kind of packet transfer is concerned wherein said packets have a uniform length and comprise an address part (header) as well as an information part (payload). These packets are currently referred to as cells. Central switching centers for ATM networks are e.g. known from the documents EP-A-299 473 and W091/13505. These switching centers or nodes direct the cells arriving on various lines to the required outgoing lines under control of the addresses of the cells, and prevent congestions. Today, extensive norms concerning the structure and the interfaces of ATM networks exist. There is a division into a public domain and a private domain of the ATM network. So-called Network Terminations type 1 (NT1 ) serve as inter¬ face units between these areas, any kind of Terminal Equip- ment (TE) being connectable to each NT1 on the private side. A Network Termination type 2 (NT2) is defined for the connection of a plurality of terminal equipments of the same user. By this definition, the required basic func¬ tions and intersections ϋ, T, and S are essentially deter- mined. In a general manner, low-priced and universally applicable structural units are desired for the construction of ATM networks. It is therefore an object of the invention to provide an economical NT2 unit for arbitrary applications in the private domain of an ATM network. This object is attained by the characterizing part of claim 1. The dependent claims define embodiments of the inven¬ tion. The invention is explained in more detail by way of an ex¬ ample with reference to four figures. Fig. 1 shows a schematical view of an ATM network (prior art); Fig. 2 shows the basic structure of an NT1 unit (prior art); Fig. 3 shows a modified NT1 unit; and Fig. 4 shows the structure of an NT2 unit. Fig. 1 shows a schematical view of an ATM network 10 accor¬ ding to the state of the art. It is divided into a public domain 11 having any number of switching nodes 12 and transmitting lines 13 between said nodes 12, and into a private domain 15 comprising terminals 16 and NT2 (Network Termination type 2) units 17. At the border of the public domain 11, a plurality of NT1 (Network Termination type 1) units 19 are disposed. Each NT1 unit 19 is connected by its first connection and an intersection ϋ to one of said switching nodes 12. By its second terminal and an intersection T, each NT1 unit 19 is connected to one of terminal equipments 16 or to an NT2 unit 17. In this structure of ATM network 10, NT1 units 19 form a clear boundary between the interests of the public network operator and the interests of the various terminal equipment users, i.e. the network subscribers. Fig. 2 shows the basic structure of an NT1 unit 19, partly corresponding to the state of the art. This NT1 unit 19 comprises two equal input/output circuits 22.1, 22.2 via which it is connected to two transmission paths 23, 24 wor- king in opposite directions. Externally, said input/output circuits 22 fulfill the conditions of said intersections U and T. In the incoming direction, each of them (22.1, 22.2) comprises an input amplifier 26 and a following Hea¬ der Error Control HEC (27), and in the outgoing direction, an output amplifier 28. In said input amplifier 26 and in said output amplifier 28, a serial-parallel conversion resp. a parallel-serial conversion takes place, inter alia. This is necessary because of the high bit speed of the cells. In Fig. 2, the parallel treatment inside NT1 unit 19 is indicated by bold connecting arrows. Header error control 27 verifies the correctness of the header of each incoming cell. In the case of a minimal error, it attempts to correct the error. If this is not possible or if the error is too large, header error control 27 deletes the entire concerned cell. If the header is correct or if a small error has been corrected, the respec¬ tive cell is forwarded without any substantial delay in the same direction. It is now advantageous to implement further functions in said NT1 unit 19 in addition to the normed regenerating and verifying functions which are provided by the two input/output circuits 22.1, 22.2. An extractor 31 in path 23 and an inserter 32 in path 24 serve this purpose. Fur¬ thermore, a microprocessor 34 and a feedback line 35 be¬ tween extractor 31 and inserter 32 serve said purpose. The additional functions provided by said units 31, 32, 34, 35 are the following: extractor 31 is capable ofto recei¬ ving instructions and requests from the public network do- main 11 from passing cells and to supply them to micropro¬ cessor 34. Conversely, the microprocessor 34 can transmit error messages and/or answers via inserter 32 and passing cells to the public network domain 11. Further, on order of a cell, this entire cell may be deviated from path 23 to path 24 for checking purposes. This is equivalent to loo¬ ping back of this cell coming from the public domain 11 to said public domain. By means of the mentioned functions, i.e. <check header of each incoming cell>, <receive and retransmit each cell hav¬ ing a correct header and delete each cell having an incor¬ rect header>, and <loop back cells with specially labelled header arriving from public domain 11 >, each connection to the private domain 15 can be checked for operativeness from the public domain 11. In the case of a malfunction, it is possible to decide at a central location whether the error source is to be found in the public domain 11 including the concerned NT1 unit 19, or in the private domain 15. This facilitates the operation of network 10 considerably. Fig. 3 shows the structure of a switching unit 39. The construction of this unit 39 is substantially the same as that of the described NT1 unit 19. The main difference consists in the fact that feedback line 35 is divided into two lines 35.1, 35.2 which are connected to an additional input/output circuit 22.3. Switching unit 39 thus com¬ prises three input/output circuits 22.1, 22.2, 22.3 of identical design. An associated difference is that the loopback function of NT1 unit 19 is transformed into a de¬ viating function. This modification only requires a small intervention in extractor 31. In this manner, switching unit 39 is suitable for the transmission or the controlled deviation of complete cells, a possible deviating order being comprised in the header of the cell to be deviated. This means that switching unit 39 comprises a switching function on account of which cells arriving on path 23 are either forwarded to input/output circuit 22.2 or to input/output circuit 22.3. On the other hand, both the cells arriving on input/output circuit 22.2 and those arriving on input/output circuit 22.3 are direc¬ ted to input/output circuit 22.1, inserter 32 performing the necessary multiplexing of the cells. Fig. 4 shows the structure of an NT2 unit 17. Unit 17 com¬ prises any number of switching units 39, e.g. six. Said switching units 39 are connected in a loop configuration by parallel lines 123, 124 corresponding to the mentioned transmitting paths 23, 24. For the connection to the pub- lie domain 11, a connecting and control unit 40 is provided which is connected to said domain 11 by an intersection T and an NT1 unit 19, as described. Terminal equipment 16 of any kind is connected or connectable to each one of swit¬ ching units 39. The loop structure of NT2 unit 17 provides substantial ad¬ vantages. The greatest advantage consists in the fact that the terminals for terminal equipments 16, i.e. switching units 39, are already existing units essentially, namely NT1 units 19. As described, these units only require small additions and modifications in order to be transformed into switching units 39. The production costs of the switching units 39 is thereby drastically reduced since on one hand, the costs for development are largely avoided, and on the other hand, the manufacturing costs are strongly reduced due to large-scale manufacture. Besides these very deci¬ sive economical advantages, however, the described NT2 unit 17 also offers purely technical advantages since it has a simple and clear concept which provides constructional, and subsequently, operational flexibility. For example, this flexibility may consist in the fact that the involved swit- - 6 - ching units 39 may be placed at large distances from each other, the length of lines 123, 124 being almost unlimited. Furthermore, the subsequent addition or the removal of a switching unit 39 from the loop of the NT2 unit is easy.

Claims: Claims 1. An NT2 unit (17) for an ATM network (10), - said ATM network (10) being composed of a public do- main (11) comprising switching nodes (12) and transmitting paths (13), and of a private domain (15) comprising termi¬ nal equipments (16) and NT2 units (17), - the transmission of information being effected by means of cells comprising a header and a payload, and - NT1 units (19) serving as interfaces between said public domain (11) and the private domain, said NT1 units (19) having at least two mutually opposed transmitting paths (23, 24) for cells and two identical input/output circuits (22.1, 22.2), characterizsed by a terminal and control unit (40) and an arbitrary number of identical switching units (39) which are interconnected in an loop configuration by two connect¬ ing lines (123, 124) , - said terminal and control unit (40) being connectable to the public domain (11) by way of an NT1 unit (19), - any kind of terminal equipment (16) being connectable to each of said switching units (39), - cells being transmitted on said connecting lines (123, 124) in opposite directions, - said switching units (39) comprising, like said NT1 units (19), two mutually opposed transmitting paths (23, 24) for cells and two input/output circuits (22.1, 22.2) to which said connecting lines (123, 124) are connected, and - said switching units (39) further comprising a third input/output circuit (22.3) for the connection of the res¬ pective terminal equipment (16), as well as an extractor (31) and an inserter (32) which are inserted in said two transmitting paths (23, 24), connected to said third input/ output circuit (22, 23) via connecting lines (35.1, 35.2), and are designed for the controlled deviation of complete cells from one path (23) to the first (35.1) of said connecting lines, resp. for multiplexing complete cells from the second (35.2) of said connecting lines to said other path (24) .

Inventors: POTTS MARTIN, RAO SATHYANARAYANA, POTTS, MARTIN, RAO, SATHYANARAYANA
Applicants: ASCOM TECH AG, POTTS MARTIN, RAO SATHYANARAYANA, POTTS, MARTIN, RAO, SATHYANARAYANA
Application year: 1995
Main classification: H04Q11
IPC codes: H04L12, H04Q3, H04Q11