Static random access memory device and manufacturing method therefor

Abstract: A static random access memory (SRAM) device in which a first active region of annular shape and a second active region bisecting the annulus are provided repeatedly over the whole cell array. Since a contact hole (c) for connecting a power line to the active region can be formed larger without increasing the cell size, contact resistance can be decreased. Thus, the manufacturing method can be simplified since just one gate oxide layer formation process is required.

Description: The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a static random access memory device comprising a first active region having an annular shape and a second active region bisecting the first active region and a manufacturing method therefor. Research into a static random access memory (SRAM) cell consisting of two transmitting transistors (access transistors), two driving transistors (driver transistors) and two resistors has been performed in various fields, including a CMOS SRAM using a silicon-on-insulator (SOI) layer for reducing the power consumption and required area of a memory cell. The CMOS SRAM uses a thin-film transistor (TFT), instead of a polysilicon having high resistance, as a resistor, and is thus very useful for reducing standby current. FIG. 1 of the accompanying drawings is a general circuit diagram of an SRAM cell and shows a full CMOS SRAM using a PMOS TFT as the resistor. The CMOS SRAM cell comprises an NMOS first transmitting transistor T 1 whose gate is connected to a word-line and whose drain (or source) is connected to a first bit line; an NMOS second transmitting transistor T 2 whose gate is connected to the word-line and whose drain (or source) is connected to a second bit line; an NMOS first driving transistor T 3 whose drain is connected to the source (or drain) of first transmitting transistor T 1 , whose source is connected to a first constant power line V ss (i.e., ground) and whose gate is connected to the source (or drain) of second transmitting transistor T 2 ; an NMOS second driving transistor T 4 whose drain is connected to the source (or drain) of second transmitting transistor T 2 , whose source is connected to first constant power line V ss and whose gate is connected to the source (or drain) of first transmitting transistor T 1 ; a first PMOS TFT T 5 whose drain is connected to the source (or drain) of first driving transistor T 3 , whose source is connected to a second constant power line V cc and whose gate is connected to the gate of first driving transistor T 3 and the source (or drain) of second transmitting transistor T 2 ; and a second PMOS TFT T 6 whose drain is connected to the source (or drain) of second driving transistor T 4 , whose source is connected to second constant power line V cc and whose gate is connected to the gate of second driving transistor T 4 and the source (or drain) of first transmitting transistor T 1 . FIG. 2 of the accompanying drawings is a diagram showing a conventional layout of the SRAM cell, obtained from an article entitled "A Stacked Split Word-line (SSW) Cell for Low Voltage Operation, Large Capacity, High Speed SRAMs" (see: IEDM '93, pp809-812). Here, reference numeral 100 designates a mask pattern defining a semiconductor substrate into active and non-active regions, reference numerals 102 and 104 are mask patterns for forming the gates of first and second driving transistors, reference numerals 106 and 108 are mask patterns for forming the gates of first and second transmitting transistors, reference numeral 110 is a mask pattern for forming a contact hole for connecting first constant power line V ss to the active region, and reference numeral 112 is a mask pattern for forming first constant power line V ss . In FIG. 2, the layout drawn in the same mask is represented as the same kind of lines. For example, mask patterns 102 and 104 represented by a dot/dashed line are the layouts drawn in a first mask, and mask patterns 106 and 108 represented by two dots/dashed line are the layouts drawn in a second mask. Referring to FIG. 2, under the consideration of a general photo etching process in which one mask is used for one etching process, it is known that the gates of first and second transmitting transistors and the gates of first and second driving transistor are formed on different levels. According to the layout of FIG. 2, mask pattern 110 for forming the contact hole for connecting first constant power line V ss to the active region is placed between mask patterns 104 for forming the gate of the driving transistor. Also, mask pattern 100 for forming the active region is arranged over the whole cell array, as an annular shape. FIGS. 3A-3D of the accompanying drawings are cross-sectional diagrams cut along line III-III' of FIG. 2 and FIGS. 4A-4D of the accompanying drawings are cross-sectional diagrams cut along line IV-IV' thereof, for illustrating a conventional SRAM cell manufacturing process. Referring to FIGS. 3A and 4A, a field oxide layer 12 is formed on the surface of a substrate 10 by an oxidation process adopting mask pattern 100. After a first gate oxide layer 14, a first conductive layer and a first insulating layer are stacked on the whole surface of the structure, a photolithography process using mask patterns 102 and 104 is performed, so that gate (not shown) of first driving transistor T 3 and gate 16 of second driving transistor T 4 are formed. Subsequently, a second insulating layer is deposited on the whole surface and then etched back, so that spacers are formed on the sidewalls of the gates of first and second driving transistors T 3 and T 4 . As a result, a first insulating layer 18 for insulating the gates of first and second driving transistors from another conductive layer (not shown) is formed. Referring to FIGS. 3B and 4B, after sacrificially oxidizing the structure, a wet etching is performed, so that the surface of the active region damaged by the processes for forming the gates of first and second driving transistors and first insulating layer 18 is cured. After a second gate oxide layer 20 and a second conductive layer are stacked on the whole surface of the structure, a photolithography process is performed using mask patterns 106 and 108, so that gate 22 and 24 of first and second transmitting transistors T 1 and T 2 are formed. Then, the impurities are doped on the whole surface of the structure, and the source/drain regions 17, 19, 21 and 23 of each transistor are formed. Referring to FIGS. 3C and 4C, after a third insulating layer is deposited on the structure on which bulk transistors (that is, first and second transmitting transistors T 1 and T 2 and first and second driving transistors T 3 and T 4 ) are formed, the structure is etched back, to thereby form spacers 26 on the sidewalls of gates 22 and 24 of the first and second transmitting transistors T 1 and T 2 . Then, the impurities are doped on the whole surface of the structure, to thereby make the source/drain regions 21 and 23 of the first and second transmitting transistors T 1 and T 2 as a lightly doped drain (LDD) structure. Referring to FIGS. 3D and 4D, after forming a further insulating layer 32 on the whole surface of the structure, the photolithography process using mask pattern 110 is performed. Thus, the contact holes C for connecting first constant power line V ss with source (not shown) of first driving transistor T 3 and with source 19 of second driving transistor T 4 are formed while being self-aligned to the gates of first and second driving transistors. After depositing a third conductive layer on the whole surface of the structure, the photo etching process using mask pattern 112 is performed, to thereby form first constant power line V ss 34 which connects to the active region via contact hole C. According to the conventional layout diagram of the SRAM and the manufacturing method thereof, since the gates of the driving transistor and the transmitting transistor are formed from different conductive layers, the size of the unit cell can be reduced. There are, however, certain problems with the above conventional technique, as follows. First, the gate oxidation layer is formed twice. That is, since the gate oxidation layer 14 of the driving transistor and the gate oxidation layer 20 of the transmitting transistor are separately formed, the process is complicated. Secondly, since the gate oxidation layer 20 of the transmitting transistor is formed after gate 16 of the driving transistor is formed, the quality of gate oxidation layer 20 of the transmitting transistor may be deteriorated due to the damages generated on the substrate surface during the formation of gate 16 of the driving transistor. During the processes shown in FIGS. 3B and 4B, the sacrificial oxidation and wet etching are performed to prevent the quality deterioration of the gate oxidation layer of the transmitting transistor, to thereby cure the damaged portion on which the gate oxidation layer of the transmitting transistor is formed. However, this complicates the process. Thirdly, the width of the spacers A formed on the sidewalls of the gate (not shown) of the first driving transistor and the gate 16 of second driving transistor is different from that of the spacers 26 formed on the sidewalls of the gates 22 and 24 of the first and second transmitting transistors. Referring to FIGS. 3A and 4C, the width of the spacers A formed on the sidewalls of the gate (not shown) of the first driving transistor and the gate 16 of the second driving transistor is wider than that of the spacers 26 formed on the sidewalls of the gates 22 and 24 of the first and second transmitting transistors, because spacers 26 are formed through just one depositing/etching process while spacers A are formed through two such processes (i.e., for forming the gate (not shown) of the first driving transistor and the gate 16 of the second driving transistor and for forming the gates 22 and 24 of the first and second transmitting transistors). If the width of the spacers formed on the sidewalls of gates of the driving transistors is wider than that of the spacers formed on the sidewalls of the gates of the transistors, the cell ratio decreases in accordance with the ratio of the driving transistor's current to the transmitting transistor's current. Fourthly, the area of the contact hole decreases. That is, referring to FIG. 4D, if the distance between gates 16 is defined as a minimum feature size, the width of contact hole C formed therebetween decreases to below the minimum feature size due to the spacers A formed on the sidewalls of the gates during each etching back process, thereby to increase the contact resistance of first constant power line V ss . Furthermore, EP 0 593 247 A2 discloses a semiconductor memory device having a unit memory cell composed of cross connected flip flops, in which a first inverter having a first access transistor and first driver transistor and a second inverter having a second access transistor and a second driver transistor form one flip flop, and a third inverter having a first load element and the first driver transistor and the fourth inverter having a second load element and the second driver transistor form the other flip flop and wherein the gate of the first access transistor and the gate of the second access transistor are formed from a different conductive layer than that for a word line. In this device, the gates of the driving and transmitting transistors are formed from the same conductive layer. However, the size of the contact hole to the active region is not maximized. A similar device is disclosed in an article entitled "A split word line cell for 16 Mb SRAM using polysilicon sidewall contacts", published in the Technical Digest of International Electron Devices Meeting (IEDM) of 8th to 11th December 1991, Washington DC United States of America pages 477-80 by Itabashi et al, which discloses a 16 Mbit SRAM cell having a split word line memory cell layout and using a double gated PMOS thin film transistor load. Additionally, polysilicon sidewall contacts were applied to the cell storage node to reduce the number of fabrication process steps. According to a first aspect of the present invention a static random access memory device is provided, said device comprising an array of memory cells wherein each memory cell comprises a first and a second access transistor and a first and a second driver transistor, each of said transistors having a gate electrode, a source region and a drain region, and wherein each memory cell has a word line electrically connected to the gates of the first and second access transistors, and wherein each memory cell has a power line electrically connected to the source regions of the first and second driver transistors, and wherein said SRAM device further comprises an array of active semiconductor region units wherein each unit is surrounded by field oxide, wherein each unit is shared by four adjacent memory cells, each unit comprises a first active region having an annular shape and a second active region bisecting said first active region, and electrical contact between the power line and the source regions of the first and second driver transistors occurs via a contact hole provided on the second active region wherein said contact hole is shared by four adjacent memory cells and is located at the centre of the active semiconductor region unit. According to a second aspect of the present invention, there is provided a method for manufacturing a static random access memory (SRAM) device according to the first aspect of the present invention, comprising the step of forming an array of active semiconductor region units in a substrate, each unit including a first active region having an annular shape and a second active region bisecting the first active region. Preferred embodiments of the invention are disclosed in the dependent claims. In the present invention, the manufacturing process is simplified and the change of the cell ratio, caused by the different width of spacers, can be prevented. Also, the width of the contact hole can be maintained as a minimum feature size, so that the increase of the contact resistance, caused by the decrease in the width of the contact hole due to the spacers formed on the sidewalls of the gates, can be prevented. Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: FIG. 1 is a circuit diagram of a static random access memory (SRAM) cell; FIG. 2 is a conventional layout diagram used for obtaining the SRAM cell shown in FIG. 1; FIGS. 3A-3D are cross-sectional diagrams cut along line III-III' of FIG. 2, for illustrating a conventional SRAM cell manufacturing process; FIGS. 4A-4D are cross-sectional diagrams cut along line IV-IV' of FIG. 2, for illustrating a conventional SRAM cell manufacturing process; FIGS. 5A-5E are exploded layout diagrams for sequentially illustrating manufacturing process steps according to an embodiment of the present invention; FIGS. 6A-6F are cross-sectional diagrams cut along line VII-VII' of FIGS. 5A-5E respectively, for illustrating this embodiment of the method for manufacturing the SRAM cell of the present invention, and FIGS. 7A and 7B are diagrams showing an active region of a conventional SRAM cell and that according to an embodiment of the present invention, respectively. An embodiment of the method for manufacturing the SRAM cell according to the present invention will be described in detail with reference to FIGS. 5A-5E and 6A-6F. First, with reference to FIGS. 5A and 6A, a field oxide layer 42 for dividing semiconductor substrate 40 into the active and non-active regions is formed according to a conventional method using mask patterns 200. FIG. 5A shows a unit cell which is symmetrical with respect to a central vertical dashed line. The unit cell shown in FIG. 5A is symmetrically arranged with respect to the horizontal and vertical axes, and this arrangement is repeated throughout the whole cell array. Referring to FIGS. 5B and 6B illustrating the process for forming the bulk transistors, the process comprises the steps of: stacking a gate oxide layer 44 and a first conductive layer on the semiconductor substrate on which field oxide layer 42 is formed and performing a photolithography process using mask patterns 202, 204, 206 and 208 to form gate 46 of the first transmitting transistor and gate (not shown) of the second transmitting transistor and the gate (not shown) of the first driving transistor and gate 48 of the second driving transistor; doping impurities using the gates as the mask; forming an insulating layer on the structure and etching-back the insulating layer to form spacers 50 on the sidewalls of the gates; and forming source/drain regions 52, 54 and 56 of the bulk transistors of LDD structure by again doping the impurities on the semiconductor substrate. According to the above process, the gates of the bulk transistors are formed using one mask. That is, differently from a conventional SRAM manufacturing process in which the gates of the driving transistors are formed from a first conductive layer and the gates of the transmitting transistors are formed from a second conductive layer, the gates are formed from one conductive layer so that it is not necessary to perform the process for forming a gate oxide layer twice. Here, the gates of the transistors are separately formed as shown in FIG. 5B, so as to minimize the cell size. Then, the gates of the transmitting transistors are connected to the word line. Since the gates of all the bulk transistors are simultaneously formed through a one-time masking process, there is no occurrence of a phenomenon in which the width of the spacers formed on the sidewalls of the gates of the transmitting transistors is different from that of the spacers formed on the sidewalls of the gates of the driving transistors. Thus, by contrast with same conventional SRAM cells, there is no cell ratio decrease caused by the different width of the spacers. Also, according to the manufacturing method of the present invention, all bulk transistors can be formed in an LDD structure, differently from a conventional SRAM cell manufacturing method in which only transmitting transistor has an LDD structure. FIGS. 5C and 6C show the process for forming a contact hole C1 for connecting the word line to the gates of the transmitting transistors. The process is composed of the steps of: forming a first insulating layer 57 on the structure comprising the bulk transistors, by depositing an insulator such as a high temperature oxide (HTO) layer; and partially removing the first insulating layer 57 formed on the gates 44 of the transmitting transistors through a photolithography process using mask patterns 210, so as to form contact hole C1. FIGS. 5D and 6D are diagrams for illustrating the process for forming word line 58. The process is composed of the steps of: depositing a second conductive layer on the structure comprising the contact hole C1 for connecting the word-line to the gates of the transmitting transistors; and forming word line 58 connected to the gates of the transmitting transistors via the contact hole C1 by performing a photolithography process on the second conductive layer using mask patterns 212. Here, as shown in FIG. 5D, word line 58 is arranged perpendicular to the gates of the driving transistors. FIGS. 5E and 6E show the process for forming a contact hole C2 for connecting the power line to the active region. The process is composed of the steps of: forming a second insulating layer 60 on the structure having the word-line 58 formed by depositing an insulator such as an HTO layer; and forming contact hole C2 for connecting the power line to the source regions 56 of the driving transistors through the photolithography process using mask patterns 214. As shown in FIG. 6E, the contact hole C2 is formed according to the conventional photolithography process in which the contact hole for connecting the power line to the active region is formed to be self-aligned with respect to the driving transistor. As a result, a small contact hole is formed, to thereby decrease cell size. According to the present invention, the active region is designed as shown in FIG. 5A, so as to prevent the increase of the contact resistance by maximizing the size of the contact hole without increasing cell size. That is, according to the layout diagram of the conventional SRAM cell (see FIG. 2), since the active region is square or roughly circular in shape (i.e., annular), the center of the active region could not be used as a region for forming the contact hole for connecting the power line to the active region. In the present invention, however, with the active region being formed as a square or roughly circular shape having a central band (crossbar) which effectively bisects the conventional pattern (see FIG. 5A), the contact hole is placed in the center of the active region (see FIG. 5E), thereby to make the most of the remaining region of the cell. Thus, the size of the contact hole can be increased without increasing cell size, thereby to lower the contact resistance. Referring to FIG. 6F showing the process for forming the power line 62, the second conductive layer for a power line is deposited on the structure comprising the contact hole C2 for connecting the power line to the active region. In FIG. 6F, since the second conductive layer is not patterned after deposition (that is, no masking process is required), the power line is planar in shape. As a result, the power line resistance decreases and the planar power line can serve as a flat lower layer for the following process. Here, since the power line is formed without a masking process, there is, of course, no mask. FIGS. 7A and 7B are diagrams showing the active region of a conventional SRAM cell and that according to an embodiment of the present invention, respectively. The conventional active region has a simple annular shape, but the active region according to the present invention includes a crossbar bisecting the simple annulus. Also, according to the conventional active region, mask patterns C for forming the contact hole are placed on both sides of the active region. By contrast, according to the present invention, mask pattern C are arranged on the bisecting crossbar. In FIGS. 7A and 7B, the dashed line indicates a cell unit. As shown in FIG. 7B, the mask pattern C for forming the contact hole according to an embodiment of the present invention is placed on the center of the unit active region, so that the mask pattern is shared by four cells. Also, a first column in which the unit active regions are repeatedly located and a second column in which the unit active regions are repeatedly located while being shifted by 1/2 pitch along the column from the unit active regions in the first column are repeated over the whole cell array. According to the present invention, since the contact hole for connecting the power line to the active region can be formed larger without increasing the cell size, the contact resistance can be decreased.

Claims: A static random access memory device comprising an array of memory cells wherein each memory cell comprises a first and a second access transistor and a first and a second driver transistor, each of said transistors having a gate electrode (44, 48,46), a source region (52,54,56) and a drain region (52,54,56), and wherein each memory cell has a word line (58) electrically connected to the gates of the first and second access transistors, and wherein each memory cell has a power line (62) electrically connected to the source regions of the first and second driver transistors, and wherein said device further comprises an array of active semiconductor region units wherein each unit is surrounded by field oxide (42), wherein each unit is shared by four adjacent memory cells and comprises a first active region having an annular shape, characterised in that each unit further comprises a second active region bisecting said first active region and in that electrical contact between the power line (62) and the source regions of the first and second driver transistors occurs via a contact hole (C2) provided on the second active region, wherein said contact hole (C2) is shared by four adjacent memory cells and is located at the centre of the active semiconductor region unit. A device according to claim 1, wherein said power line (62) has a planar shape. A device according to claim 1, wherein the gates (48) of the driver transistors of each memory cell and the gates (46) of the access transistors of each memory cell are electrically separated from each other and wherein there are contact holes (C1) on the gates (46) of the access transistors of each memory cell, the word line of each memory cell being connected to the gates of the access transistors of said memory cell via said contact holes. A device according to claim 1, wherein the word line (58) of each memory cell extends in a direction perpendicular to the direction in which the gates (48) of said first and second driver transistors of said memory cell extend. A device according to claim 3 or 4, wherein said transistors each have a lightly doped drain structure. A device according to claim 1, wherein over the whole array of memory cells, said active semiconductor region units are arranged in columns in which the units are repeated, the units in each column being shifted by a half unit along the column from those units in the immediately adjacent column or columns. A method for manufacturing a static random access memory device according to claim 1, comprising the step of : (a) forming an array of active semiconductor region units in a substrate (40), each unit including a first active region having an annular shape and a second active region bisecting said first active region. A method as claimed in claim 7, further comprising after said step (a), the steps of: (a') forming first and second driver transistor gates (44, 48) and first and second access transistor gates (44, 46) on said substrate said gates having sidewalls; (b') forming a contact hole (C1) on each gate of said first and second access transistors, and (c') forming a word line (58) connected to the gates of said first and second access transistors via said contact hole. A method as claimed in claim 8, further comprising after step (a'), the steps of: (a") implanting impurity ions on the structure resulting from step (a'); (b") forming an insulating layer on the whole surface of the structure resulting from step (a"); (c") forming spacers (50) on the sidewalls of the gates of the transistors by etching back said insulating layer, and (d") forming lightly doped source and drain regions (52, 54, 56) by doping impurities on the structure resulting from step (c''). A method as claimed in claim 7, further comprising after step (a), the steps of: (a"') forming a contact hole (C2) by which said second active region is partially exposed, and (b''') forming a power line (62) connected to said second active region via said contact hole.

Inventors: KIM YOUNG-KWANG, SHIN HEON-JONG, KIM, YOUNG-KWANG, SHIN, HEON-JONG
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1995
Main classification: H01L27
IPC codes: H01L21, H01L27