Vertical PNP transistor and relative fabrication method

Abstract: A vertical PNP transistor integrated in a semiconductor material wafer having an N type substrate (40) and an N type epitaxial layer (41) forming a surface (42). The transistor has a P type buried collector region (43) astride the substrate and the epitaxial layer; a collector sinker (44) insulating an epitaxial tub (45) from the rest of the wafer; a gain-modulating N type buried base region (46; 46'; 46'') astride the buried collector region and the epitaxial tub, and forming a base region with the epitaxial tub; and a P type emitter region in the epitaxial tub. An N + type base sinker (47) extends from the surface, through the epitaxial tub to the buried base region. The gain of the transistor may be modulated by varying the extension and dope concentration of the buried base region (46), forming a constant or variable dope concentration profile of the buried base region (46), providing or not a base sinker (47), and varying the form and distance of the base sinker from the emitter region.

Description: The present invention relates to a vertical PNP transistor and relative fabrication method. As is known, in integrated circuits, vertical PNP transistors (i.e. in which current flows vertically, crosswise to the surface of the wafer of semiconductor material in which the transistors are integrated) are frequently formed simultaneously with NPN transistors. As traditional methods, however, of fabricating integrated circuits comprising both types of transistors involve a good deal of time and expense, various solutions have been devised for reducing the fabricating steps required, one of which is described for example in European Patent N. 0 339 732 filed by SGS-THOMSON MICROELECTRONICS (and corresponding to US Patent 4,898,836) and is shown in Figure 1. As illustrated in Figure 1, which shows a cross section of a semiconductor material wafer 1 with a top surface 2, the known solution referred to and recognized in the preamble of claims 1 and 9 is based on the use of an N type substrate 4 on which an N type epitaxial layer 5 is grown; and separate P + type buried regions 6, 7 are formed astride substrate 4 and epitaxial layer 5, and are connected to surface 2 by respective P + type sinkers 8, 9 extending from the outer lateral edges of respective P + type buried regions 6, 7 and externally defining respective epitaxial tubs 10, 11 for respectively housing an NPN transistor 12 and PNP transistor 13. More specifically, P + type buried region 6 constitutes an isolation region for electrically separating the NPN transistor from substrate 4 and epitaxial layer 5; an N + type buried collector region 15 is formed inside buried isolation region 6 and projects slightly inside epitaxial tub 10; a low-resistivity N + type region 14 and a detached P + type base region 16 are formed inside tub 10 and facing surface 2 of wafer 1; an N + type emitter region 17 is formed inside base region 16 and facing surface 2; and NPN transistor 12 is completed by collector, base and emitter metal contact regions 20, 21, 22 formed through a protective oxide layer 18 and in direct electric contact with respective regions 14, 16, 17. Together with sinker 9 and a P type region 25 extending inside epitaxial tub 11, P + type region 7 forms a collector region. More specifically, region 25 extends vertically from surface 2 of wafer 1 to buried collector region 7, and houses an N + type base region 26 facing surface 2 of wafer 1; a low-resistivity N + type region 27 and a detached P + type emitter region 28 are formed inside base region 26 and facing surface 2; and PNP transistor 13 is completed by collector, base and emitter metal contact regions 30, 31, 32 formed through protective oxide layer 18 and in direct electric contact with respective regions 9, 27, 28. The structure is completed by a low-resistivity N + type region 33 formed in the epitaxial region outside sinkers 8, 9, facing surface 2, in direct contact with an isolation metal region 34 for biasing substrate 4. Using the fabrication method described in the above patent, the Figure 1 structure is formed by first simultaneously forming isolation sinker 8 of NPN transistor 12 and collector sinker 9 of PNP transistor 13; P type doping agents are then implanted and diffused with low concentration in epitaxial tub 11 to form region 25 and ensure electric continuity between base region 26 and sinker collector region 9; and base region 26 and regions 27, 28 are then formed. The above known method therefore requires specific steps for forming collector region 25 and base region 26, and, though reduced as compared with former structures, still involves considerable fabrication cost in need of reduction. Patent Abstracts of Japan, Vol. 6, N. 72 (E-105), 7 May 1982, JP-A-57 010 963 describes a vertical PNP transistor integrated in a semiconductor material wafer, comprising a P type substrate collector region, an N type base region, and a P type emitter region extending through the epitaxial layer. The base region comprises an N type buried base region formed between the substrate collector region and the epitaxial layer, and an N type contact region formed through the epitaxial layer. It is an object of the present invention to provide a vertical PNP transistor and relative fabrication method enabling a reduction in the number of fabrication steps as compared with known transistors. According to the present invention, there are provided a vertical PNP transistor as claimed in Claim 1, and a method of fabricating a vertical PNP transistor, as claimed in Claim 9. A number of preferred, non-limiting embodiments which may be in accordance with the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a cross section of a semiconductor material wafer in which are formed an NPN transistor and a known PNP transistor; Figure 2 shows a cross section of a semiconductor material wafer in which is formed a PNP transistor according to a first embodiment; Figure 3 shows the same cross section as in Figure 2, relative to a second embodiment; Figure 4 shows the same cross section as in Figures 2 and 3, relative to a third embodiment; Figure 5 shows a cross section of a detail of a fourth embodiment; Figure 5a shows a top plan view of the fourth embodiment in Figure 5; Figure 6 shows a top plan view of a fifth embodiment; Figure 7 shows the same cross section as in Figures 2-4, relative to a sixth embodiment of the transistor according to the present invention; Figures 8-11 show cross sections of different steps in the fabrication of the first embodiment in Figure 2; Figures 12 and 13 show graphs relative to the Figure 7 embodiment; Figure 14 shows a cross section of a semiconductor material wafer relative to one application of the PNP transistor. In all the embodiments described herein below, the variable transparency technique described with reference to Figure 7 may be applied. As shown in Figure 2 illustrating a first embodiment, the PNP transistor is integrated in an N type substrate 40 on which is superimposed an N type epitaxial layer 41 having a surface 42; a P type buried collector region 43 extends astride substrate 40 and epitaxial layer 41, and a P + type collector sinker 44 extends from the outer edges of region 43 to surface 42; collector sinker 44, when viewed from above, is closed in known manner, laterally surrounds an epitaxial tub 45 to insulate it from the rest of epitaxial layer 41, and also permits surface contact of buried collector region 43; an N type buried base region 46 of extension 11 is formed inside buried collector region 43 and projects slightly inside epitaxial tub 45; an N + type base sinker 47 extends from an edge portion of buried base region 46 to surface 42 to minimize the contact resistance of the base region and connect buried base region 46 to the surface; a P + type emitter region 48 extends from surface 42 to base sinker 47 from which it is laterally spaced; and the structure is completed by collector, base and emitter metal contact regions 49, 50, 51 formed through a protective oxide layer 52 covering surface 42, and formed at and in direct electric contact with respective regions 44, 47, 48. Buried base region 46 constitutes a gain modulating region. More specifically, by appropriately selecting the area of region 46 (length 11 in Figure 2) in relation to the area of epitaxial tub 45 (length 12 in Figure 2) and/or the dope concentration, it is possible to modulate the gain of the PNP transistor and so design transistors with different gain characteristics. Buried base region 46 also provides for preventing buried collector region 43 from reaching emitter region 48 (vertical punch-through of the transistor), and contributes towards reducing base resistance. Besides assisting a reduction in base resistance, base sinker 47 also provides for improving dynamic performance of the transistor. Figure 3 shows a variation of the Figure 2 transistor, in which the length 13 of buried base region 46' is greater than 11, so that the Figure 3 structure presents a lower gain than the Figure 2 structure, in exactly the same way as increasing the dope concentration of buried base region 46. According to a further variation, the base sinker extends annularly and contiguously about the whole of emitter region 48, as shown in the Figure 4 section in which the base sinker is indicated 47'. Alternatively, the base sinker may be formed annularly, but spaced apart from emitter region 48. According to a further solution, the base sinker extends contiguously but discontinuously about emitter region 48, as shown in the top plan view in Figure 5a which shows four sinkers 47"; and the gain of the PNP transistor may be modulated by appropriately selecting the number and area of sinkers 47". In the Figure 5 and 5a embodiment, sinkers 47" are all connected electrically by a heavily doped N type annular surface region 55, at which one or more base metal contact regions 50 may be provided. In a further embodiment shown in Figure 6, a number of base sinkers 47" are provided as in Figures 5 and 5a, but are connected electrically by a number of metal contact regions 50' - one for each base sinker 47" - connected to one another by a metal base connection (not shown). According to a further embodiment in accordance with the invention, gain may also be modulated by forming a buried base region of variable resistivity using the VLD (Variation Lateral Doping) or variable transparency technique, as shown schematically in Figure 7, in which the buried base region 46" comprises heavily doped portions 57 (N + ) alternating with lightly doped portions 58 (N - ) along its length. Figures 12 and 13 show two graphs of the dope concentration along section A-A in Figure 7, and the variation in concentration C (measured as a logarithm of the absolute difference between acceptor and donor doping agents) along buried base region 46". As explained in more detail later on, by varying the geometry of the implant mask of buried base region 46", it is possible to achieve a difference of one order of magnitude between the concentration of the peaks and valleys of the two graphs, i.e. between portions 57 and 58, and hence a considerable variation in gain. The method of fabricating the Figure 2 PNP transistor will now be described with reference to Figures 8 to 11. Commencing from N type substrate 40, the first step comprises masking, implanting and diffusing P type doping agents to form buried collector region 43, as shown in Figure 8. The next step comprises masking, implanting and diffusing N type doping agents into buried collector region 43 to form buried base region 46, as shown in Figure 9. As explained above, at this step, the size and dope concentration of the buried base region and the provision of a variable dope concentration provide for modulating the gain of the finished PNP transistor. Over the entire surface of the wafer (having the intermediate structure shown in Figure 9) N type epitaxial layer 41 in which to subsequently form the base and emitter regions is then grown; P type dope is implanted and diffused in the wafer to simultaneously form sinker 44 contacting buried collector region 43, and emitter region 48; and epitaxial tub 45 is defined to give the intermediate structure shown in Figure 10. N type doping agents are then implanted (or deposited) at the edge of buried base region 46, and subsequently diffused to form base sinker 47, as shown in Figure 11. The fabrication method also comprises the final steps of defining the contact regions (forming openings in protective oxide layer 52) and forming the metal contact and connecting regions to give the structure shown in Figure 2. The Figure 3 structure (with a buried base region 46 of a different size) is formed by appropriately modifying the implant mask of region 46. Similarly, the Figure 4 structure, featuring an annular base sinker 47 contiguously surrounding emitter region 48, is formed by appropriately modifying the implant mask of region 47. To obtain the Figure 5 and 5a structure, the implant mask of the base sinker must be so designed as to form discontinuous portions 47", and a final step for implanting and diffusing N type dope in the wafer must be provided to form annular region 55 prior to final oxidation of the surface and formation of the metal contact and connecting regions. The Figure 6 structure only requires appropriate shaping of the implant mask of the base sinker (portions 47") and the mask for opening the contacts in oxide layer 52. As already stated, the Figure 7 structure is formed using the known variable transparency technique, whereby a region is implanted using a mask with openings of given size and a given spacing to achieve a desired variation in the doping level and, hence, a nonconstant dope concentration in one implant step. Gain may therefore be modulated using implant masks with varying openings, but such as to ensure electric continuity throughout the region. For example, the doping profile in Figure 12 is obtained using a mask 60 with 4 µm square openings (light regions) 61 separated by dark regions 62, and wherein the light regions 61 are arranged in a regular grid formation and separated by a distance of 4 µm, i.e. by a distance equal to the length of each side. The Figure 13 profile, on the other hand, is obtained using a mask 65 with 4 µm square openings (light regions) 66 spaced 6 µm apart by dark regions 67 and arranged in a regular grid formation. In test and simulation specimens made by the Applicants of the Figure 2 and 3 embodiments, substrate 40 and epitaxial layer 41 presented a resistivity of roughly 65 Ω*cm; buried collector region 43 presented a layer resistance R S of 2500 Ω/□ in the portion beneath buried base region 46, and 670 Ω/□ in the lateral portion; buried base region 46 presented a layer resistance R S of 18 Ω/□ ; base sinker 47 presented a layer resistance R S of 1 Ω/□ ; and emitter region 48 presented a layer resistance R S of 40 Ω/□. At the end of the fabrication process, the annular surface region 55 of other specimens of the Figure 5 and " 5a embodiments presented a layer resistance R S of 20 Ω/□. Simulation tests performed by the Applicants have shown a considerable variation in gain of the PNP transistors alongside variations in the following parameters: extension and doping level of the buried base region; presence or absence of a base sinker; formation of a single base sinker contacting one point along the lateral edge of the buried base region, or formation of an annular region; distance between the base sinker and the emitter region; deep emitter region (extending as far as the buried base region) or shallow emitter region (some distance from the buried base region); forming the buried base region using the variable transparency technique (exposure of only portions of the implant area) according to the invention. In particular, in the case of a transistor with no base sinker and with a collector current of 100 µA and a voltage (collector-emitter voltage V CE ) of 2.5 V, a continuous buried base region 46 with an area of 46x52 µm 2 gives a gain hfe of 139; and a variable transparency buried base region 46" formed using nine 6 µm square light regions 4 µm apart gives a gain hfe of 340. In the case of a transistor with the Figure 2 structure and the above collector current and voltage V CE , a continuous buried base region 46 with an area of 46x52 µm 2 gives a gain hfe of 74; and a variable transparency buried base region 46" formed as described above gives a gain hfe of 138. In the case of an annular sinker 47' contiguously and completely surrounding emitter region 48, and with a shallow emitter region (terminating some distance from buried base region 46), a continuous buried base region 46 with an area of 46x52 µm 2 gives a gain hfe of 2; and a variable transparency buried base region 46" formed as described above gives a gain hfe of 6. Finally, in the case of a transistor formed as shown in Figure 7, the Figure 12 mask 60 gives a gain of 800, and the Figure 13 mask 65 a gain of 600. The advantages of the PNP transistor and relative fabrication method according to the invention are as follows. Fabrication of the PNP transistor is simplified as compared with the known transistor in Figure 1, by eliminating the steps for forming base region 25. Buried base region 46, 46' or 46", in fact, does not represent an additional region as compared with the known transistor in Figure 1, by virtue of being formed simultaneously with and using the same implant mask as for forming the low-resistivity buried collector region 15 of the NPN transistor. The PNP transistor according to the invention provides for modulating gain as required, by appropriately selecting the design parameters described above. By appropriately selecting and combining the design parameters, it is therefore possible to form, on the same wafer, transistors with a different gain and with specific characteristics for adapting device performance to specific requirements. The PNP transistor according to the invention may also be used in the drive circuits of monolithic semiconductor devices also comprising a power stage. Such devices, in which low-voltage components (drive circuits) and high-voltage components (power stage) are integrated on the same chip, generally feature an isolation structure of the type shown in Figure 14, which is formed using a known integrating technique involving an intermediate epitaxial growth in which to define the isolation tubs of the various circuit components. As shown in Figure 14, in which the low-voltage portion is indicated 70 and the high-voltage portion 71, the low-voltage portion presents a P type buried region 72 from which P type sinkers 74 defining N type epitaxial tubs 75 extend towards surface 73 of the device. N type buried regions 76 are provided astride respective epitaxial tubs 75 and buried region 72 to prevent buried region 72 from extending as far as surface 73, and for forming a low-resistivity path for the components requiring one. The Figure 14 structure adapts well to integrating the PNP transistor according to the invention. In fact, a comparison with Figures 2-7 shows clearly that the buried collector region 43 of the transistor according to the invention may be implemented by buried region 72 in Figure 14; and the buried base region 46, 46', 46" may be implemented by buried regions 76. Moreover, since emitter region 48, collector sinker 44 and the other structures forming the transistor according to the invention do not require additional fabrication steps, the PNP transistor according to the invention involves no additional cost as compared with known semiconductor devices comprising a power stage. Clearly, changes may be made to the transistor and fabrication method as described and illustrated herein without, however, departing from the scope of the present invention.

Claims: A vertical PNP transistor integrated in a semiconductor material wafer having a surface (42), the transistor comprising a P type buried collector region (43), an N type base region (45-47) contacting said collector region, and a P type emitter region (48) surrounded by said base region; characterized in that said base region comprises an N type buried base region (46; 46'; 46") having selected physical parameters for modulating the transistor gain; said base region (45-47) comprising an N type epitaxial portion (45) delimited at the bottom by said buried collector region (43); said buried base region (46; 46'; 46") being located astride said buried collector region and said epitaxial portion; and in that said buried base region (46") has an N type dope concentration profile varying over its area in a direction parallel to said wafer surface (42). A PNP transistor as claimed in Claim 1, characterized in that it comprises an N type base sinker (47; 47'; 47") extending from said surface (42) as far as said buried base region (46; 46'; 46"). A PNP transistor as claimed in Claim 2, characterized in that said base sinker (47) extends through said epitaxial portion (45) and at a distance from said emitter region (48). A PNP transistor as claimed in Claim 2, characterized in that said base sinker (47'; 47") extends through said epitaxial portion (45) and is contiguous to said emitter region (48). A PNP transistor as claimed in any one of Claims 2-4, characterized in that said base sinker (47') presents a closed annular shape and surrounds said emitter region (48). A PNP transistor as claimed in any one of Claims 2-4, characterized in that said base sinker comprises a number of base portions (47") spaced about said emitter region (48). A PNP transistor as claimed in Claim 6, characterized in that it comprises an N type annular contact region (55) in direct electric contact with said base portions (47") and facing said surface (42). A PNP transistor as claimed in Claim 6, characterized in that it comprises a number of metal contact regions (55), each in direct electric contact with a respective base portion (47"). A method of manufacturing a vertical PNP transistor as claimed in any of the foregoing Claims, the method comprising the step of integrating, in a semiconductor material wafer having a surface, a P type buried collector region, an N type base region contacting said collector region, and a P type emitter region surrounded by said base region; characterized in that it comprises the step of forming an N type buried base region having selected physical parameters for modulating the transistor gain; and in that said buried base region is formed using a variable transparency technique so that said buried base region (46") has an N type dope concentration profile varying over its area in a direction parallel to said wafer surface. A method as claimed in Claim 9, characterized in that said step of forming a buried base region comprises the step of introducing N type doping agents in a P type buried collector region formed in an N type substrate; and in that it comprises the subsequent step of growing an epitaxial layer on said substrate. A method as claimed in Claim 10, characterized in that it comprises the step of forming an N type base sinker through said epitaxial layer down to said buried base region. A method as claimed in Claim 11, characterized in that it comprises the step of forming a P type emitter region through said epitaxial layer; said base sinker and said emitter region being formed at a distance from each other. A method as claimed in Claim 11, characterized in that it comprises the step of forming a P type emitter region through said epitaxial layer; said base sinker and said emitter region being formed contiguous to each other. A method as claimed in Claim 12 or 13, characterized in that said step of forming a base sinker comprises the step of implanting doping agents along a closed line surrounding said emitter region. A method as claimed in Claim 12 or 13, characterized in that said step of forming a base sinker comprises the step of forming a number of N type sinker portions spaced about said emitter region. A method as claimed in Claim 15, characterized in that it comprises the step of forming a low-resistivity N type annular surface layer in said epitaxial layer and through said number of N type sinker portions. A method as claimed in Claim 15, characterized in that it comprises the step of forming a number of metal contact regions, each in direct electric contact with a respective portion of said base sinker. A method as claimed in any one of Claims 12-17, characterized in that it comprises the step of simultaneously forming said P type emitter region and a P type insulating region surrounding said epitaxial layer.

Inventors: LEONARDI SALVATORE, LIZZIO PIETRO, PALARA SERGIO, PATTI DAVIDE GIUSEPPE, LEONARDI, SALVATORE, LIZZIO, PIETRO, PALARA, SERGIO, PATTI, DAVIDE GIUSEPPE
Applicants: CONS RIC MICROELETTRONICA, ST MICROELECTRONICS SRL, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO - CORIMME, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: H01L29
IPC codes: H01L29, H01L21