DIGITAL-TO-DIGITAL CONVERSION USING NONUNIFORM SAMPLE RATES

Abstract: A method and apparatus for digital-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that noise produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where it can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated (16) by fixed ratio and then decimated (21) under control of a first sigma-delta modulated frequency selection signal (26) that represents, on average, the data rate of the incoming digital data stream. Thereafter, the digital data is interpolated (30) under control of a second sigma-delta modulated frequency selection signal (46) that represents, on average, the data rate of the digital data to be output by the converter and then decimated (40) by a fixed ratio. In another embodiment, the digital data is interpolated under control of a first sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream and then decimated by a fixed ratio. Thereafter, the digital data is interpolated by a fixed ratio and then decimated under control of a second sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The first and second frequency signal selection numbers are modulated using n-th order m-bit sigma-delta modulators. The method and apparatus converts the data rate of the incoming digital data stream to the data rate of the first n-th m-bit sigma-delta modulator and then converts the digital data stream from the first sigma-delta modulator (20) to an output data rate determined by the second n-th order m-bit sigma-delta modulator (32).

Description: DIGITAL-TO-DIGITAL CONVERSION USING NONUNIFORM SAMPLE RATES CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of our co-pending application Serial No. 08/120,957, filed September 13, 1993, entitled DIGITAL TO ANALOG CONVERSION USING NONUNIFORM SAMPLE RATES, application Serial No. 08/121,104, filed September 13, 1993, entitled ANALOG TO DIGITAL CONVERSION USING NONUNIFORM SAMPLE RATES, application Serial No. 08/241,059, filed May 11, 1994, entitled DIGITAL TO DIGITAL CONVERSION USING NONUNIFORM SAMPLE RATES, International Application Serial No. PCT/US94/10268, filed September 13, 1994, entitled ANALOG TO DIGITAL CONVERSION USING NONUNIFORM SAMPLE RATES, and International Application Serial No. PCT/US94/10269, filed September 13, 1994, entitled DIGITAL TO ANALOG CONVERSION USING NONUNIFORM SAMPLE RATES, the disclosures of which are incorporated herein by reference in their entirety. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to the field of methods and circuits for digital-to-digital conversion. More particularly, the present invention relates to a method and circuit for digital-to-digital signal conversion using sigma-delta modulation of the temporal spacing between digital samples. 2. Discussion of the Related Art Digital-to-digital converter circuits and methods for digital-to-digital conversion are well-known in the art. One example of a conventional digital-to-digital converter is the AD1890/AD1891 asynchronous sample rate converter, manufactured by Analog Devices, Incorporated, One Technology Way, P.O. Box 9106, Norwood, Massachusetts, 02062. Conceptually, these converters interpolate the input data up to a very high equivalent internal sample rate with a time resolution of 300 picoseconds and then decimate the interpolated data down to the desired output sample rate. The equivalent frequency of the oversampled digital data is approximately 3.2768 gigahertz. FIG. 1 is an overall functional block diagram of the AD 1890/1891. As shown in FIG. 1, the input digital data at a data rate Fsl is interpolated at some ratio by inserting zero valued samples between each of the original input signal samples by the interpolator. The oversampled signal is then fed into a digital FIR low-pass filter to smooth or integrate the sequence. The interpolated and filtered digital data is then passed to a zero-order hold register and then asynchronously resampled by decimating the digital data stream in the decimation block to produce the digital data out at a data rate Fs2. One of the limitations of conventional digital-to-digital converters is that they only determine the magnitude of the input signal at equally spaced temporal intervals. This is known aε uniform sampling. Additionally, in conventional digital-to-digital converters, the sample rate, that is, the rate of the incoming digital data stream cannot be independent of the master clock that is used to clock the digital-to-digital converter. The incoming digital data rate must be some integer division of the master clock of the digital-to-digital converter chip. This means that if the digital-to-digital converter were to receive digital data at two different data rates, that are not necessarily divisible into the master clock (or more generally, digital data at a rate that is not integrally divisible into the master clock) , there must be two different frequency master clocks available for clocking the digital-to-digital converter (or more generally, there must be a master clock that has an integer relationship with the data rate of the incoming digital data available to clock the digital-to-digital converter). Another problem with conventional digital-to-digital converters is that they are typically not designed to be clocked by an externally supplied clock signal. The components of the digital-to-digital converter are typically optimized to operate at the clock frequency determined by the master clock on the digital-to-digital converter chip. This leads to the additional limitation that some digital-to-digital converters cannot lock to and operate at some externally supplied clock signal. Therefore, if there are any changes in the digital data rate, since the incoming digital data stream and the master clock for the digital-to-digital converter are not necessarily related to each other, any temporal changes in the relative frequencies of the incoming digital data rate and the master clock can disrupt the entire digital-to-digital conversion process. In addition, the number of FIR filter taps and associated coefficients can become so large as to make the filter complicated and difficult to obtain a high throughput when the incoming digital data stream has a fast data rate. Therefore, an object of the present invention is to provide a method and apparatus for performing digital-to-digital conversion using NONUNIFORM sampling (i.e., variable temporal spacing of the sampling points). Another object of the present invention is to provide a method and apparatus for performing digital-to-digital conversion that can lock to an externally supplied clock signal and can provide a sampling rate that is independent of the converter's master clock. SUMMARY OF THE INVENTION The present invention overcomes the limitations of the prior art by providing a method and apparatus for digital-to-digital conversion using NONUNIFORM sampling. In one embodiment of the invention, the apparatus includes a first interpolator or other comparable circuitry such as a sample and hold circuit for receiving digital signals at a first data rate and for supplying the digital signals at a first increased data rate and a first decimator, coupled to the first interpolator, for decimating the digital signals at the first increased data rate to provide digital signals at a second data rate. In one embodiment, a first sigma-delta modulator is coupled to and controls the first decimator and provides a first sigma-delta modulated output signal representative of the first data rate and controls the first decimator to provide the digital signals at the second data rate. This part of the invention interpolates digital data by a fixed ratio and then decimates the interpolated digital data by a variable ratio depending on the second data rate desired. ' In another embodiment, a sigma-delta modulator is coupled to and controls the interpolator and provides a sigma-delta modulated output signal representative of the first data rate and controls the interpolator to provide a digital data stream at the increased data rate so that, upon decimation by the decimator, the digital signals are at the second rate. This part of the invention interpolates the digital data by a variable ratio depending on the second data rate desired and then decimates the interpolated data by a fixed ratio. Depending on the performance requirements of the particular application, the decimated digital data at the second data rate may then be filtered to remove, for example, sigma-delta noise introduced by the variable decimation of the digital data at the first increased data rate. The digital data at the second data rate is supplied to a second interpolator or other comparable circuitry such as a sample and hold circuit that receives the digital data at the second data rate and supplies the digital signals at a second increased data rate. A second decimator is coupled to the interpolator and decimates the digital signals at the second increased data rate to provide digital signals at a third data rate. . In one embodiment, a second sigma-delta modulator is coupled to and controls the second interpolator and provides a second sigma-delta modulated output signal representative of the third data rate to control the second interpolator to provide the digital signals at the second increased data rate so that, upon decimation by the second decimator, the digital signals are at the third data rate. This part of the invention interpolates the digital data by a variable ratio depending on the third data rate desired and then decimates the interpolated digital data by a fixed ratio. In another embodiment, a sigma-delta modulator is coupled to and controls the decimator and provides a sigma-delta modulated output signal representative of the third data rate and controls the decimator to provide the digital signals at the third data rate. This part of the invention interpolates the digital data by a fixed ratio and then decimates the interpolated digital data by a variable ratio depending on the third data rate desired. In another embodiment of the invention, a first phase locked loop (PLL) which may be a digital PLL or may be an analog PLL having its output coupled to the first sigma-delta modulator is provided for receiving a signal representative of the first data rate, locking to the signal, and providing a first control signal to the first sigma-delta modulator that controls the first sigma-delta modulator to provide the sigma-delta modulated output signal. In one embodiment, the first sigma-delta modulator forms part of the digitally controlled oscillator in the PLL. The first phase locked loop allows the circuit to lock to and track any externally-supplied clock signal. In another embodiment of the invention, a second phase locked loop (PLL) which may be a digital PLL or may be an analog PLL having its output coupled to the second sigma-delta modulator is provided for receiving a signal representative of the third data rate, locking to the signal, and providing a second control signal to the second sigma-delta modulator that controls the second sigma-delta modulator to provide the second sigma-delta modulated output signal. The second sigma-delta modulator forms part of the digitally controlled oscillator in the PLL. The second phase locked loop allows the circuit to lock to and track any externally-supplied clock signal. Broadly stated, the method of the present invention includes sigma-delta modulation of the time base such that errors produced by NONUNIFORM sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. That is, the present invention provides temporally noise-shaped digital signals. In one part of the invention, the method is to perform a fixed interpolation (or other method of increasing the data rate or sample rate of the digital signal or digital data stream) and filtering to remove images followed by variable decimation with the decimation controlled by a first sigma-delta modulator that is fed a frequency selection signal representing the sampling frequency or data rate of the input data stream. Fixed interpolation means that the interpolation ratio is the same regardless of the sample rate. Variable decimation means that the decimation ratio is varied as a function of the desired output sample rate. More particularly, a digital data stream at a data rate within some predetermined limits is interpolated to a higher data rate. This higher data rate digital data stream is then decimated using a control signal that is a sigma-delta modulated signal that represents the data rate of the incoming digital data stream. The frequency selection signal is modulated using a first n-th order m-bit sigma-delta modulator. This control signal (the sigma-delta modulated frequency selection number output by the second sigma-delta modulator) represents, on average, the data rate of the incoming digital data stream. Data thus emerges from the interpolation/decimation process at the clock rate of the first n-th order m-bit sigma-delta modulator. This part of the method thus converts the data rate of the incoming digital data stream to the data rate of the first n-th order m-bit sigma-delta modulator. Once the data rate of the incoming digital data stream has been converted to the data rate of the first n-th order m-bit sigma-delta modulator, another part of the method is to perform a variable interpolation (or other method to increase the data rate or sampling frequency of the digital signal or digital data stream) and filtering to remove images followed by a fixed decimation with the interpolation controlled by a second sigma-delta modulator that is fed a frequency selection signal representing the desired output sample rate. Variable interpolation means that the interpolation ratio is varied as a function of the desired output sample rate. Fixed decimation means that the decimation ratio is the same regardless of the sample rate. More particularly, the digital data stream at the data rate of the first n-th order m-bit sigma-delta modulator is interpolated to a higher data rate using a control signal that is a sigma-delta modulated signal that represents the desired output data rate (i.e., sample rate or sampling frequency). The frequency selection signal is modulated using a second n-th order m-bit sigma-delta modulator. This control signal (the sigma-delta modulated frequency selection signal output by the second sigma-delta modulator) represents, on average, the sample rate of the digital data to be output by the converter . The control signal controls the interpolator to increase the data rate such that, upon fixed decimation, data emerges from the interpolation/decimation process at the desired output sample rate. This part of the method thus converts the data rate of the digital data stream output by the variable decimation process from an oversampled signal to a digital data stream having the desired sample rate. In another part of the invention, the method is to perform a variable interpolation (or other method to increase the sample rate of the digital data stream) and filtering to remove images followed by a fixed decimation with the interpolation controlled by a sigma-delta modulator that is fed a frequency selection number representing the sampling frequency of the input data stream. Variable interpolation means that the interpolation ratio is varied as a function of the desired output sample rate. Fixed decimation means that the decimation ratio is the same regardless of the sample rate. A digital data stream at a data rate within some predetermined limits is interpolated to a higher data rate using a control signal that is a sigma-delta modulated signal that represents the data rate of the incoming digital data stream. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. This control signal (the sigma-delta modulated frequency selection number output by the sigma-delta modulator) represents, on average, the data rate of the incoming digital data stream. The control signal controls the interpolator to increase the data rate such that, upon fixed decimation, data emerges from the interpolation/decimation process at the clock rate of the n-th order m-bit sigma-delta modulator. The part of the method thus convert the data rate of the incoming digital data stream to the data rate of the n-th order m-bit sigma-delta modulator. Once the data rate of the incoming digital data stream has been converted to the data rate of the first n-th order m-bit sigma-delta modulator, another part of the method is to perform a fixed interpolation (or other method to increase the sample rate of the digital data stream) and filtering to remove images followed by a variable decimation with the decimation controlled by a second sigma-delta modulator that is fed a frequency selection number representing the desired sample rate of the output digital data stream. Fixed interpolation means that the interpolation ratio is the same regardless of the sample rate. Variable decimation means that the decimation ratio is varied as a function of the desired output sample rate. More particularly, a digital data stream at the data rate of the first n-th order m-bit sigma-delta modulator iε interpolated to higher data rate. This higher data rate digital data stream is then decimated using a control signal that is a sigma-delta modulated εignal that represents the desired output data rate (or sample rate) . The frequency selection signal iε modulated using a second n-th order m-bit sigma-delta modulator. This control signal (the sigma-delta modulated frequency selection signal output by the sigma-delta modulator) represents, on average, the sample rate of the digital data to be output by the converter. Data thus emerges from the interpolation/decimation process at the desired output sample rate. The part of the method thus converts the data rate of the digital data stream output by the variable interpolation process from an oversampled signal to a digital data stream having the desired sample rate. The features and advantages of the present invention will be more readily understood and apparent from the following detailed description of the invention, which should be read in conjunction with the accompanying drawings, and from the claims which are appended at the end of the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, which are incorporated herein by reference and in which like elements have been given like reference characters, FIG. 1 is a block diagram of a conventional digital-to-digital converter; FIG. 2 is a block diagram of a digital-to-digital converter circuit incorporating a first embodiment of the invention; FIG. 3 is a more detailed block diagram of the circuit of FIG. 2; FIG. 4.is a block diagram of a circuit for supplying previously stored frequency numbers to the n-th order m-bit sigma-delta modulator of FIGS. 2-3, 5-5A, 9-10, 12, and 14-17; FIG. 5 is a block diagram illustrating a locking circuit in the circuits of FIGS. 2-3 and 16-17; FIG. 5A is a block diagram illustrating the use of a combination of a locking circuit and a sigma-delta modulator in the circuits of FIGS. 2-3 and 16-17; FIG. 6 is a block diagram of a locking circuit that may be used in conjunction with the circuits of FIGS. 2-3, 5-5A, 9-10, 12, and 14-17, to lock the digital-to-digital converter to an externally supplied clock signal; FIG. 7 is a block diagram of a second locking circuit that may be used in conjunction with the circuits of FIGS. 2-3, 5-5A, 9-10, 12, and 14-17, to lock the digital-to-digital converter to an externally supplied clock signal; FIG. 8 is a flow chart illustrating the steps of a first embodiment of the method of the present invention; FIG. 9 is a block diagram of a digital-to-digital converter circuit incorporating a second embodiment of the invention; FIG. 10 is a more detailed block diagram of the circuit of FIG. 9; FIG. 11 is a flow chart illustrating the steps of a second embodiment of the method of the present invention; FIG. 12 is a block diagram of a digital-to-digital converter circuit incorporating a third embodiment of the invention; FIG. 13 is a graph illustrating the relationship between the four-bit codes and the corresponding sampling frequency in the circuit of FIG. 12; FIG. 14 is a block diagram illustrating a locking circuit in the circuits of FIGS. 9-10, 12, and 14-17; FIG. 15 is a block diagram illustrating the use of a combination of a locking circuit and a sigma-delta modulator in the circuits of FIGS. 9-10, 12, and 14-17; FIG. 16 is a block diagram illustrating a circuit that provides for digitally mixing signals that may have differing sample rates; FIG. 17 is a block diagram illustrating a circuit for providing, from a digital data stream having one data rate, digital data streams that may have differing data rates; FIG. 18 is a flow chart illustrating the steps of the method of digitally mixing signals of the present invention; and FIG. 19 is a flow chart illustrating the stepε of the method of providing multiple digital data streams from one digital data stream in accordance with the present invention. DETAILED DESCRIPTION For purposes of illustration only, and not to limit generality, the present invention will now be explained with reference to specific data rates, interpolation (or more generally sample rate increase) ratios, decimation ratios, and clock frequencies of operation. One skilled in the art will recognize that the present invention is not limited to the specific embodiment discloεed, and can be more generally applied to other circuits and methods having different operating parameters than those illustrated. FIG. 2 is a block diagram broadly illustrating a first embodiment of the invention. The overall purpose of circuit 10 is to receive a digital data stream on line 12 at any data rate within a predetermined working range of the system and to convert the digital data to a digital data stream on line 42. The data rate of the digital data stream on line 42 can be the same as, higher, or lower than the data rate of the digital data stream on line 12. Circuit 10 performs this function by increasing the sample rate (Fsl) of the digital data stream on line 12 to create a first so-called "oversampled" signal and then decimates this higher rate data stream so that the data stream presented on line 14 is at a fixed, predetermined data rate. In other words, circuit part 13 of circuit 10 receives digital data at any data rate within the predetermined working range of the system, and converts this data to a digital data εtream on line 14 at another data rate. The data rate on line 14 may or may not be the same as the data rate of the input data stream and may be a fixed or a variable rate. The digital data stream on line 12 may be of any width (i.e., any number of bits). Once the digital data on line 12 has been converted to the predetermined data rate on line 14, circuit 10 increases the sample rate of the digital data on line 14 to create a second so-called "oversampled" signal and then decimates this higher rate digital data stream so that the data presented on line 42 is at a desired output sampling rate. In other words, circuit part 15 of circuit 10 receives digital data at the fixed, predetermined data rate and converts this data to a digital data stream at another data rate. In circuit part 13 of the circuit 10 illustrated in FIG. 2, an interpolator 16 receives the digital data εtream on line 12 at any data rate (Fεl) within the predetermined working range. Interpolator 16 increases the sample rate of the digital data εtream (that iε, converts the digital data stream into a higher sample rate digital data εtream) on line 12 by, for example, inεerting zeroε between data samples, in a manner well-known to those skilled in the art. One skilled in the art will appreciate that other techniques may be used for increasing the sample rate of the data stream on line 12, such aε sample and hold techniqueε. The purpoεe of interpolator 16 iε to increaεe the εample rate of the digital data stream on line 12 to create an oversampled signal. A higher sample rate digital data stream 17 is then sent to a digital filter 18 which attenuates any images of the original digital signal as a result of the interpolation procesε. The filtered digital data stream on line 19 is then sent to a decimation block 21 that decimates digital data stream on line 19 under control of the sigma-delta modulator 20. Although filter 18 and decimation block 21 have been r illustrated as separate circuit elements for illustrative purposes, one skilled in the art will appreciate that these functions may be performed by a single computational element, εuch aε an FIR or IIR filter in a well-known manner. The sigma-delta modulator 20 produces digital data at the frequency of clock 22, the data controlling the decimation of decimation block 21. As will be explained in more detail hereinafter, the εigma-delta modulator 20 εigma-delta modulateε a εignal 24 representative of the data rate (Fsl) of the digital data εtream on line 12. An example will εerve to illuεtrate this function. Asεume that the data rate of the data stream on line 12 is 48 kHz. Interpolator 16 increases this data rate to 18.432 mHz by interpolating the data by a factor of 384. Assume the frequency of clock 22 is 3.072 mHz. Since the data rate of data stream 12 is 48 kHz, signal 24 is therefore a multi-bit digital number representative of a εampling rate of 48 kHz where the number of bitε in the digital number control the preciεion with which the data rate of digital data stream on line 12 can be specified. This digital number is sigma-delta modulated by the sigma-delta modulator 20 and uεed to control decimation block 21 to produce one output εignal for every εix samples in digital data stream 19. The 18.432 mHz data iε then effectively decimated by a factor of εix and the digital data stream on line 14 is therefore at, on average, a 3.072 mHz data rate. Sigma delta modulator 20 is preferably an n-th order m-bit sigma-delta modulator. The higher the order of the sigma-delta modulator, the better the noise shaped characteristics of the output signal on line 26. The signal on line 26 output by εigma-delta modulator 20 iε choεen to be m-bits (where m 1 an d i s more than one bit in a preferred embodiment) because, as the number of bits is increased, the clock rate necessary to operate sigma-delta modulator 20 can be reduced. However, it is to be appreciated that the invention is not so limited. Sigma-delta modulator 20 could also be a one bit modulator if the clock frequency used to run the modulator is increased aε neceεεary. A key feature of the present invention as a whole and in particular circuit part 13 is that the temporal spacing of the sampling points is controlled by the n-th order m-bit sigma-delta modulator such that any errors (i.e., noise on the sampling points) produced by this NONUNIFORM sampling are shaped in the frequency domain. That is, the digital signal output by the present invention as well as the control signal produced by the εigma-delta modulator are temporally noise-shaped. All embodimentε of the invention provide thiε feature. As is well-known in the field of sigma-delta εystems, this noise on the digital εignal produced by circuit part 15 produced by errors resulting from the NONUNIFORM εampling can be removed by conventional digital filtering techniqueε. Several other advantageε are also obtained. By appropriate choice of the rate at which the sigma-delta spaced sampling points are generated and the number of bits used in controlling the spacing of these sampling points, the signal to noise ratio of the digital data stream on line 14 can be controlled. Further degrees of freedom are available by varying the order of the sigma-delta modulator used to control the oversampling ratio. In another aspect of the invention, the degree of filtering used on the digital data stream on line 17 can also be varied to vary the signal-to-noiεe ratio aε well. The digital data at the predetermined data rate on line 14 iε optionally filtered by a filter 11 depending on the performance requirementε of the particular application. Filter 11 removes any sigma-delta noise on the digital data stream on line 14 as a result of the sigma-delta modulator's control of decimation block 21. Filter 11 may be a sine-type 4 filter, such as a sine 96 filter, well known to those skilled in the art. The filtered data from filter 11 on line 28 is sent to circuit part 15 of circuit 10. In circuit part 15 of the circuit 10 illustrated in FIG. 2, the filtered digital data εtream on line 28 is then sent to interpolator 30. Interpolator 30 increaseε the εample rate of the digital data εtream (that iε, converts the digital data stream into a higher sample rate digital data εtream) on line 28 by uεing a εample and hold technique that repeatε the digital εample for a specified number of clock cycles in a manner well-known to those skilled in the art. One skilled in the art will appreciate that other techniqueε may be used for increasing the sample rate of the data stream on line 28, such as interpolation techniques that insert zeroes between data samples. The purpose of interpolator 30 is to increase the sample rate of the digital data stream on line 28 to create an oversampled signal. The interpolation ratio (i.e., the ratio by which the sample rate of the digital data on line 28 is increased by interpolator 30) is controlled by a sigma-delta modulator 32. Sigma-delta modulator 32 may be the same type of modulator as sigma-delta modulator 20. A higher sample rate digital data stream on line 34 is then sent to a digital filter 36 which removes any imageε of the original digital εignal aε a reεult of the interpolation proceεε. The filtered digital data stream on line 38 iε then εent to a decimation block 40 that decimates the digital data stream on line 38 by a fixed decimation ratio to produce the digital data stream on line 42 having a sample rate (Fε2) εelected by a sampling frequency εelect signal 44. Although filter 36 and decimation block 40 have been illuεtrated as separate circuit elements for illustrative purposeε, one εkilled in the art will appreciate that these functions may be performed by a single computational element, such aε an FIR or IIR filter in a well known manner. The sigma-delta modulator 32 produces digital data at the frequency of clock 22, the data controlling the interpolation of interpolator 30. As will be explained in more detail hereinafter, the sigma-delta modulator 32 sigma-delta modulates a signal 44 representative of the desired output sample rate (Fs2) of the digital data stream on line 42. An example will serve to illustrate this f nction. Aεsume that the data rate of the digital data stream on line 28 is 3.072 mHz. Assume the frequency of clock 22 is 3.072 mHz. If the desired data rate of the data stream on line 42 is 32 kHz, signal 44 is therefore a multi-bit digital number representative of a sampling rate of 32 kHz where the number of bits in the digital number control the precision with which the data rate (Fs2) of the data εtream on line 42 can be εpecified. This digital number is sigma-delta modulated by the εigma-delta modulator 32 and uεed to control interpolator 30 to increase the sample rate of the digital data stream on line 28 by a factor of four. Interpolator 28 increases this data rate to 12.288 mHz by interpolating the data by a factor of four. The resulting 12.288 mHz data is then decimated, after filtering by filter 36, by a factor of 384 (decimator 40 having a decimation ratio of 384) and the digital data stream emerging on line 42 is therefore at, on average, a 32 kHz data rate. Sigma-delta modulator 32 iε preferably an n-th order m-bit εigma-delta modulator. The higher the order of the εigma-delta modulator, the better the noise shaped characteristics of the output signal on line 42. The signal on line 46 output by sigma-delta modulator 32 is chosen to be m-bits (where m 1 n an< 3 is more than one bit in a preferred embodiment) because, aε the number of bitε which control interpolator 30 is increased, the clock rate necesεary to operate εigma-delta modulator 32 can be reduced. However, it iε to be appreciated that the invention iε not εo limited. Sigma-delta modulator 32 could alεo be a one bit modulator if the clock frequency used to run the modulator is increased as neceεsary. A key feature of the present invention is as a whole (aε diεcussed previously) and circuit part 15 in particular that the temporal spacing of the sampling points is controlled by the n-th order m-bit sigma-delta modulator such that any errors (i.e., noise on the sampling points) produced by this NONUNIFORM sampling are shaped in the frequency domain. That is, the digital signal output by the present invention as well as the control signal produced by the sigma-delta modulator are temporally noise-εhaped. All embodiments of the invention provide this feature. As is well-known in the field of sigma-delta systems, this noise on the digital signal produced by circuit part 15 produced by errors reεulting from the NONUNIFORM εampling can be removed by conventional digital filtering techniqueε. Several other advantageε are alεo obtained. By appropriate choice of the rate at which the sigma-delta spaced sampling points are generated and the number of bits used in controlling the spacing of theεe sampling points, the signal-to-noiεe ratio of the digital data stream on line 42 can be controlled. Further degrees of freedom are available by varying the order of the sigma-delta modulator used to control the oversampling ratio. In another aspect of the invention, the degree of filtering used on the digital data stream on line 34 can also be varied to vary the εignal-to-noise ratio as well. FIG. 3 illustrates a more detailed embodiment of the digital-to-digital converter of FIG. 2. In circuit 100, circuit part 51 is analogouε to circuit part 13 in FIG. 2 and circuit part 90 iε analogouε to circuit part 15 in FIG. 2. In the circuit 100 of FIG. 2, an n-bit wide digital data εtream on line 50 which may be, for example, in the range of 4 kHz to 48 kHz is received by interpolator 52. Interpolator 52 increases the sample rate (Fsl) of digital data εtream on line 50 by a factor of four uεing, for example, a zero fill technique that inεerts zeros between the digital samples. The higher sample rate signal output by interpolator 52 (now in the range of 16 kHz to 192 kHz) iε then fed into a digital low paεε filter 54 which may be, for example, a finite impulse response type filter. Low pasε filter 54 filters out of band images of the digital εignal on line 50 out of the digital data stream on line 53. The filtered digital data stream on line 56 from low pasε filter 54 is then fed into interpolator 58 that increases the sample rate of the digital data stream on line 56 by a factor of ninety-six. Inserting ninety-five zeros into the digital data stream on line 56 will reduce the gain of the original signals because of the dilution of the signal by the inserted zeros. However, as is well-known, the parameters of filter 62 can be adjusted to compensate for this losε of gain. The higher εample rate digital data εignal on line 60 (now in the range of 1.536 mHz to 18.432 mHz) provided by interpolator 58 iε fed into digital filter 62. Aε εtated previouεly, other techniques, such as sample and hold techniques, may be used to increase the εample rate in place of interpolatorε 52, 58. The use of a sample and hold technique is advantageous because it automatically compensates for the energy lost in creating the images of the original signal due to the interpolation procesε. In one embodiment, digital filter 62 iε a εinc 96"-type filter that iε designed to have zeros at the image frequencies of the digital data stream on line 60. Filter 62 could, however, be any type of IIR or FIR filter. In the embodiment illuεtrated in FIG. 3, digital filter 62 provides both a low pass filtering function and a decimation function. One skilled in the art will appreciate that these two functions could be separated in the manner illustrated in FIG. 2. As will be explained in greater detail hereinafter, filter 62 outputs a digital data stream on line 64 at 3.072 mHz. It iε to be noted that the digital data streams on lines 53, 56, 60, and 64 are indicated as being n-bits wide in FIG. 3. N may be any number of bits and is typically chosen to be the widest bit stream commensurate with the signal-to-noiεe ratio requirementε of the particular application. Furthermore, the digital data streams may be different widths on each of the lines. The n-th order m-bit εigma-delta modulator 66 provides a four-bit number on line 68 that controlε filter 62 to produce the output data εtream on line 64. Sigma-delta modulator 66 iε, in one embodiment, a third order four-bit modulator. Sigma delta modulator 66 iε clocked using a 3.072 mHz clock 70. In one embodiment, a twenty-bit frequency selection number 72 (representing Fsl) iε input into εigma-delta modulator 66N Frequency selection number 72 ranges from -2 to +2 9 . Thiε twenty-bit number controls the precision with which the four-bit number output by sigma-delta modulator 66 representε the εampling rate (Fsl) of the input digital data stream on line 50. Sigma-delta modulator 66 modulates the twenty-bit number to produce sigma-delta modulated four-bit codes that control filter 62. The first bit of the code is a sign bit. The remaining three bits produce codes that direct the filter 62 to calculate and produce an output every P samples of the data stream on line 60, effectively sample rate converting the data stream. Table 1 illustrateε the relationship among the four-bit codes that are produced by sigma-delta modulator 66, the intervals at which filter 62 produces an output, and the sampling frequency that the four-bit code correspondε to when modulator 66 is clocked using a 3.072 mHz clock. Some exampleε will illuεtrate the operation of thiε part of the εystem. Table 1 4 BIT CODE PRODUCE AN CORRESPONDING OUTPUT EVERY TO SAMPLING P SAMPLES FREQUENCY OF (kHZ) ALLOW P CLOCKS TO PASS THROUGH +4 8 64 +3 7 56 +2 6 48 +1 5 40 0 4 32 -1 3 24 -2 2 16 -3 1 8 -4 0 DC Assume, for purposeε of illustration, that the digital data stream on line 50 has a data rate (Fsl) of 48 kHz. Interpolator 52 increases this data rate to 192 kHz. Interpolator 58 increaεes the 192 kHz εampling rate to 18.432 mHz. To produce the digital data stream on line 64 at 3.072 mHz at the output of filter 62 (i.e, at the clock rate of the clock controlling sigma-delta modulator 66), the digital data stream on line 60 at 18.432 mHz must be decimated by a factor of six. Therefore, twenty-bit frequency εelection number 72 is selected such that upon sigma-delta modulation by the third order four-bit sigma-delta modulator 66, the four bit codes generated will be, on average, a +2 code although other four bit codes will be produced but with a lower frequency of occurrence. A key point to remember is that the +2 code is the resulting average of all the codes produced by sigma-delta modulator 66 upon sigma-delta modulation of twenty-bit frequency selection number 72. A +2 code is not produced every time sigma-delta modulator 66 is clocked even though the input sample rate (Fsl) and the output sample rate of the data stream on line 64 are related to each other by an integer multiple. Even if the sample rates were related to each other by an integer multiple, any errors, no matter how small, that result in a temporal displacement between the sample points in the input digital data stream on line 50 and the sample pointε in the rate-converted digital data εtream on line 64 would increaεe the εignal-to-noise ratio to a point where the conversion procesε would not be acceptable. In the present invention, the time base (i.e., the temporal spacing between samples) is sigma-delta modulated so that the errors due to temporal displacement between the input and rate-converted digital data stream that cause noise are pushed into a higher frequency range. This noise is then removed by conventional filtering techniques εuch aε in filter 74. Aε εhown in Table 1, the +2 (on average) code directε filter 62 to produce an output every εix data εamples of digital data stream on line 60. This results in the output data stream on line 64 having a data rate (i.e., a εample rate or εampling frequency) of 3.072 mHz on average. In another example, aεεume that the digital data εtream on line 50 has a data rate (i.e., a sample rate or sampling frequency) (Fsl) of 4 kHz. Interpolator 52 increases this data rate to 16 kHz. Interpolator 58 increases the 16 kHz data rate to 1.536 mHz. In order that the digital data stream on line 64 have a data rate of 3.072 mHz (i.e., the clock rate of the clock controlling sigma-delta modulator 66), the digital data stream on line 60 at 1.536 mHz must be effectively interpolated by a factor of 2. Therefore twenty-bit frequency selection number 72 (representing Fsl) is chosen such that εigma-delta modulator 66 produces, on average, an equal number of -3 and -4 codes although other four bit codes will be produced, but with a lower frequency of occurrence. That is, occasionally, -2, -1, and even less frequently, +1, +2 codes will be produced. As shown in Table 1, the -3 code directε εinc filter 62 to produce an output for each input εample corresponding to a sampling frequency of 8 kHz for the clock frequencies and interpolation ratios illustrated. The -4 code is uεed to control filter 62 εo that it doeε not produce a new output but rather repeatε the previous output. That is, the filter 62 is directed to produce an output, but since a new data point has not been received and the previouε data point iε εtill at the filter input, the filter 62 repeatε the calculation and produceε the same output again. At the illustrated interpolation ratioε and clock frequencieε, the -3 code repreεents a sampling frequency of 8 kHz and the -4 code representε a sampling frequency of DC (i.e., no signal). Therefore, on an average of many sampleε, the -3 and -4 four-bit codes produce a εampling frequency of 4 kHz to provide a digital data stream on line 64 at 3.072 mHz. One skilled in the art will appreciate that any sampling frequencieε within the 0 to 64 kHz range may be produced by varying the ratio of four-bit codes produced by sigma-delta modulator 66. For example, to obtain a εampling frequency between 56 kHz and 64 kHz, the appropriate ratio of +3 and +4 codeε would be output by εigma-delta modulator 66 aε a function of twenty-bit number 72. One εkilled in the art will alεo appreciate that any εample rate within the working range of the εyεtem can be produced through the appropriate combination of four-bit codeε. Although modulator 66 haε been illustrated as a four-bit εigma-delta modulator, the invention is not so limited. For example, a εigma-delta modulator that outputε fewer bitε can be uεed if the clock rate of the clock εupplied to the modulator iε increaεed as necessary. In the same manner, a sigma-delta modulator that outputs a larger number of bits can be used and the modulator can then be clocked at a lower rate. One skilled in the art will appreciate the number of bits used and the clock rate used are a function of the desired noise shaping and signal to noise ratio, and may be traded-off depending upon the requirements of a particular application. One of the advantages of εigma-delta modulation of the time baεe iε that the jitter or time variation produced on the εampling time (or εampling interval) due to the fact that digital filter 62 or decimator 21 (under control of sigma-delta modulator 20 or 66) reεpectively produces output sampleε at time intervalε that may not correεpond exactly to the εpecified εampling frequency (the 3.072 mHz clock rate in the illustrated embodiments) iε varied by the sigma-delta modulator so that any noiεe that reεult from the error or jitter around the εampling point haε a εigma-delta characteriεtic that can be removed by conventional filtering techniqueε, aε for example, by filter 74. FIG. 4 is a block diagram of an alternative syεtem for determining frequency εelection number 72. In FIG. 4, a memory 80 (which may be RAM or ROM, for example) iε used to store a look up table containing twenty-bit numbers and the sampling frequency to which they correεpond. In response to a frequency select εignal from a user or an external source, decoder 82 selects the twenty-bit number from memory 80 most closely correεponding to the desired sampling frequency specified by the frequency εelect signal. The twenty-bit number is then output on bus 84 to sigma-delta modulator 66. The system of FIG. 4 can be used in conjunction with all embodiments of the invention. The sample rate converted digital data stream on line 64 optionally is sent to filter 74 which operates in a manner analogous to filter 11 in FIG. 2. That is, depending on the performance requirementε of the particular application, filter 74 may be uεed to filter out sigma-delta noise on the digital data stream on line 64 as a reεult of εigma-delta modulation control of εinc filter 62. In one embodiment of the invention, filter 74 may be a εinc-type filter, such aε a 4 εmc 96 -type filter. The filtered digital data εtream having a data rate of 3.072 mHz on line 86 iε then fed into circuit part 90 of circuit 100. The filtered digital data stream on line 86 is then εent to interpolator 92. Interpolator 92 increaεeε the εample rate of the digital data stream on line 86 by using a sample and hold technique or an interpolation technique under control of sigma-delta modulator 94. The use of a sample and hold technique is advantageous because it automatically compenεates for the energy lost in creating the images of the original signal due to the interpolation process. One skilled in the art will appreciate that other techniques, εuch aε interpolation techniqueε that inεert zeroeε between data samples may be used to increase the sample rate of the data stream on line 86. The higher rate digital data stream on line 96 is then sent to low-pasε filter 98 that removeε i ages and sigma-delta noise from the digital data stream on line 96 that may be present as a result of the interpolation process. In one embodiment, digital filter 98 is a sine 96 3 -type filter. Filter 52 could, however, be any type of IIR or FIR filter. The filtered digital data stream on line 102 iε then sent to a decimation block 104 that decimates the digital data εtream on line 102 by a fixed decimation ratio (96 in the illustrated embodiment). The decimated digital data εtream on line 106 iε then filtered by low paεs filter 108 to remove images and εigma-delta noiεe as a result of the NONUNIFORM sampling. The filtered digital data εtream on line 110 iε then εent to a decimation block 112 that decimates the digital data εtream on line 110 by a fixed decimation ratio (4 in the illuεtrated embodiment) to provide the digital data εtream on line 114 at the data rate (Fs2) selected by a 20 bit sampling frequency selection number 116. It is to be noted that the digital data streams on lines 86, 96, 102, 106, and 110 are indicated as being n-bits wide in FIG. 3. N may be any number of bits and is typically chosen to be the widest bit stream commensurate with the signal-to-noise ratio requirements of the particular application Furthermore, the digital data streams may be different widthε on each of the lines. The n-th order m-bit sigma-delta modulator 94 provides a four-bit number on line 117 that controls interpolator 92 to produce the digital data εtream on line 96. In one embodiment, sigma-delta modulator 94 iε a third order four-bit modulator. Sigma-delta modulator 94 iε alεo clocked using the 3.072 mHz clock 70. In one embodiment, a twenty-bit frequency selection number 116 (representing Fs2) is input into εigma-delta modulator 94N Frequency selection number 116 ranges from -2 19 to +2 19 . This twenty-bit number controls the precision with which the four-bit number output by sigma-delta modulator 94 represents the desired sampling rate RECTIFIED SHEET (RULE 91) ISA/EP (Fε2) of the output digital data stream on line 114. Sigma delta modulator 94 modulates the twenty-bit number to produce sigma-delta modulated four-bit codes that control interpolator 92. The first bit of the code iε a εign bit. The remaining three bits produce codes that control the interpolation ratio (i.e., the factor by which the sample rate of the digital data stream on line 86 is increased) provided by interpolator 92 to effectively convert the sample rate of the data stream. Table 2 illustrates the relationship among the four-bit codes that are produced by sigma-delta modulator 94, the ratio by which the sample rate of the digital data stream on line 86 is increased, and the sampling frequency that the four-bit code corresponds to when modulator 94 is clocked using a 3.072 mHz clock. Some examples will illustrate the operation of this part of the syεtem. Table 2 4 BIT CODE SAMPLE RATE CORRESPONDING INCREASE FACTOR TO SAMPLING ALLOW P CLOCKS FREQUENCY OF (kHz) TO PASS THROUGH +4 8 64 +3 7 56 +2 6 48 +1 5 40 0 4 32 -1 3 24 -2 2 16 -3 1 8 -4 0 DC Assume, for purposeε of illustration, that the sample rate of the digital data stream on line 86 is an oversampled data stream having a constant sample rate of 3.072 mHz as a result of the interpolation/decimation procesε performed by circuit part 51 on the digital data εtream on line 50. Aεεume that the deεired sample rate (Fs2) of the digital data stream on line 114 iε 32 kHz. To produce the digital data stream on line 114 at 32 kHz, the digital data stream on line 110 muεt have a sample rate of 128 kHz and the digital data stream on line 96 must have a sample rate of 12.288 mHz. Therefore, twenty-bit frequency selection number 116 is selected such that upon εigma-delta modulation by the third order four-bit εigma-delta modulator 94, the four-bit codes generated will be, on average, a 0 code, although other four-bit codes will be produced but with a lower frequency of occurrence. Interpolator 92 useε, in one embodiment, a εample and hold technique under control of εigma-delta modulator 94 to increaεe the εample rate of the digital data stream on line 86. The use of a sample and hold technique is advantageous because it automatically compenεateε for the energy lost in creating the images of the original εignal due to the interpolation proceεε. A key point to remember iε that the 0 code is the resulting average of all codes produced by sigma-delta modulator 94 upon εigma-delta modulation of twenty-bit frequency selection number 116. A 0 code iε not produced every time sigma-delta modulator 94 is clocked even though the εample rate of the digital data εtream on line 86 and the sample rate of the digital data stream on line 114 are related to each other by an integer multiple. Even if the sample rates were related to each other by an integer multiple, any errors, no matter how small, that result in a temporal displacement between the sample pointε in the digital data εtream on line 86 and the εample pointε in the rate-converted digital data stream on line 96 would increase the εignal-to-noiεe ratio to a point where the conversion proceεε would not be acceptable. In the preεent invention, the time baεe (i.e., the temporal spacing between samples) is sigma-delta modulated so that the errorε due to temporal diεplacement between the digital data εtream on line 86 and the rate-converted digital data εtream on line 96 that cause noise are pushed into a higher frequency range. This noiεe iε then removed by conventional filtering techniqueε such as in digital filters 98 and 108. As shown in Table 2, the 0 code (on average) directε interpolator 92 to increaεe the sample rate of the digital data stream on line 86 by a factor of four. Interpolator 92 useε, in one embodiment, a εample and hold technique under control of sigma-delta modulator 94 to increase the εample rate of the digital data εtream on line 86. The uεe of a εample and hold technique iε advantageous because it automatically compensates for the energy lost in creating the images of the original signal due to the interpolation process. Alternatively, interpolator 92 may increase the sample rate by interpolation using a zero fill technique to insert four zeros between every sample of the digital data stream on line 86. Inserting zeros into the digital data εtream on line 86 will reduce the gain of the original signals because of dilution of the signal. The higher sample rate digital data stream on line 96 haε a εample rate of, on average, 12.288 mHz in thiε example. Upon decimation by decimator circuit 104 and decimator circuit 112, the digital data εtream on line 114 emergeε with a sample rate of, on average, 32 kHz. In another example, assume that the desired sample rate of the digital data stream on line 114 is 4 kHz. To produce the digital data εtream on line 114 at 4 kHz, the digital data εtream on line 110 muεt have a εample rate of 16 kHz and the digital data εtream on line 96 muεt have a εample rate of 1.536 mHz. Therefore, 20-bit frequency selection number 116 is selected εuch that sigma-delta modulator 94 produceε, on average, an equal number of -3 and -4 codeε, although other 4-bit codeε will be produced, but with a lower frequency of occurrence. Aε shown in Table 2, the -3 code directs interpolator ■ 92 not to increaεe the εample rate (becauεe the sample rate increaεe factor is 1). This correspondε to a εampling frequency of 8 kHz for the clock frequencieε and interpolation ratios illustrated. The -4 code controlε interpolator 92 to increaεe the sample rate of the digital data stream by a factor of zero. That is, interpolator 92, in responεe to a -4 code, produceε no output, thus effectively decimating the digital data stream on line 86. At the illustrated interpolation ratios and clock frequencies, the -3 code represents a sampling frequency of 8 kHz and the -4 code repreεentε a sampling frequency of DC (i.e., no signal). Therefore, on average of many samples, the -3 and -4 4-bit codes represent a sampling frequency of 4 kHz. Thuε, on average of many sampleε, after decimation by decimator 104 and decimator 112, the data rate of the digital data on line 114 will be, on average, 4 kHz. One skilled in the art will appreciate that any εampling frequencieε within the 0 to 64 kHz range may be produced by varying the ratio of four-bit codes produced by sigma-delta modulator 94. For example, to obtain a sampling frequency between 56 kHz and 64 kHz, the appropriate ratio of +3 and +4 codeε would be output by εigma-delta modulator 94 aε a function of twenty-bit number 116. One εkilled in the art will also appreciate that any sample rate within the working range of the syεtem can be produced through the appropriate combination of four-bit codes. Although a four-bit sigma-delta modulator haε been illuεtrated, the invention is not so limited. For example, a sigma-delta modulator that outputs fewer bits can be uεed if the modulator iε clocked at a faεter rate. In the same manner, a sigma-delta modulator that outputs a larger number of bits can be uεed and the modulator can then be clocked at a lower rate. One εkilled in the art will appreciate that the number of bitε uεed and the clock rate used are a function of the desired noise εhaping and εignal-to-noise ratio and may be traded off depending upon the requirements of a particular application. As previouεly discussed with respect to circuit part 51, one of the advantages of sigma-delta modulation of the time base in circuit part 90 is that the jitter or time variation produced on the sampling time (or sampling interval) due to the fact that interpolator 92 (under control of sigma-delta modulator 94) produces output sampleε at time intervalε that may not correspond exactly to the specified output sampling frequency (0 kHz to 64 kHz in the illustrated embodiment) on line 117 is varied by the sigma-delta modulator so that any noise that resultε from the error or jitter around the sampling point has a εigma-delta characteristic that can be removed by conventional filtering techniques, as for example, by filter 98. The alternative system for determining a frequency selection number as illustrated in FIG. 4 can also be used to determine 20 bit frequency selection number 116 in the same manner. FIG. 5 illustrates another embodiment of the invention in which digital phase locked loops 120 and 122 are incorporated into the circuits of FIGS. 2 or 3. The phase locked loops allow the digital-to-digital converter to operate at and lock to external clock signals, such as off-chip signalε. Phaεe locked loop 120 locks to and tracks an external frequency εource on line 124. The frequency source on line 124 may be the sampling frequency select signal or the twenty bit frequency selection number illustrated in FIGS. 2 and 3, reεpectively. The frequency εource on line 124 may be a clock running at the data rate (Fsl) of the digital data coming into the circuit on line 126. Alternatively, the frequency source on line 124 may be a clock from the circuit that supplieε the digital data on line 126 at a data rate of Fsl. Therefore, phase locked loop 120 will track changes in the clock that controls the data rate of the digital data on line 126, thus allowing this part of the circuit to respond to an external frequency source. In this way, the first part of circuit 150 including interpolator 128, filter 130, and decimator 132 can be made to track the clock that controls the data rate of the digital data on line i26, thuε allowing this part of the circuit to RECTIFIED SHEET (RULE 91) ISA/EP operate independent of the clock rate of clock 134. In a like manner, phase locked loop 122 responds to an external frequency source on line 136 to control interpolator 138, filter 140, and decimator 142. The frequency εource :>n line 136 may be the εampling frequency εelect signal or the twenty bit frequency selection number illustrated in FIG. 2 and 3, reεpectively. The external frequency εource on line 136 iε typically a clock running at the desired output data rate (Fε2) of the digital data on line 144. In thiε manner, the data rate of the digital data on line 144 can be made to be independent of the clock rate of clock 134, εince the phase locked loop 122 locks to and tracks the frequency of the external frequency εource on line 136. FIG. 5A illuεtrateε another embodiment of the invention in which phase locked loop 120 receives, on line 124, an external frequency source having a frequency equal to the clock rate of the digital data stream being supplied to interpolator 128. Since phase locked loop 120 responds to a clock having the data rate of the incoming digital data stream, any changes in the frequency of the digital data on line 126 are tracked by phase locked loop 120, thereby keeping the operation of interpolator 128, filter 130, and decimator 132 in εynchroniεm with the data rate of the incoming digital data on line 126. The circuit of FIG. 5A alεo includeε the εigma-delta modulator and variable interpolation/fixed decimation circuitry 90 illuεtrated in FIG. 3. Thiε portion of the circuitry of FIG. 5A operateε in the manner described in conjunction with FIG. 3. The circuit of FIG. 5A is advantageouε in that the fixed interpolation, variable decimation portion can be locked to the data rate of the incoming digital data εtream. The data rate of the outgoing digital data εtream on line 114 iε controlled by the 20 bit frequency εelection number 116. Thuε, both portionε 146 and 90 can reεpectively receive data and output data independent of the clock rate of clock 134. In addition, the data rate of the digital data on line 114 can be independent of and unrelated to the data rate of the digital data on line 126. Theεe same advantages also are provided by the circuit of FIG. 5. One skilled in the art will appreciate that FIGS. 5 and 5A are exemplary and that phase locked loops and εigma-delta modulatorε can be combined in other wayε in accordance with the preεent invention. FIG. 6 illuεtrateε a detailed embodiment of phaεe locked loop 120 of FIG. 5. Digital phaεe locked loop 120 incorporateε a sigma-delta modulator such as εigma-delta modulator 20 or 66. In circuit 120, an external clock source on line 124 is applied to a frequency counter 164 that produces a signal representative of the period of the external frequency source on line 124. In addition, the external clock on line 124 is applied to a phase detector 166 that produces a signal proportional to the phaεe difference between the external clock on line 124 and a signal on line 168 to be described in more detail hereinafter. The output of the phaεe detector 166 iε filtered by differentiating filter 170 and εummed in summer 172 with the εignal repreεentative of the period of the external clock εource on line 124 from the frequency counter 164. The output of summer 172 is fed into an integrating filter 174 that functions as a low-pasε filter. The output of integrating filter 174 iε then sent to a circuit 176 that converts the period to a frequency by performing a 1/period function and providing any application dependent scaling of the frequency signal. The signal from circuit 176 is then sent to sigma-delta modulator 66. The four-bit code from sigma-delta modulator 66 is uεed to control decimator 132 or decimate block 21 or εinc filter 62 in the εame manner aε deεcribed in connection with the embodiment of FIGS. 2 and 3, respectively. The four-bit code is also fed into a clock generation circuit 178 that effectively produces an output clock at 384 times greater than the εignal on line 124. Circuit 178 performs this function by suppressing a certain number of 24.576 mHz clock cycleε in response to the four-bit code from sigma-delta modulator 66. The following examples will serve to illustrate. Assume sigma-delta modulator 66 is clocked by a 3.073 mHz clock. For every 3.072 mHz clock, there are eight 24.576 mHz clocks applied to circuit 178. In accordance with Table l, circuit 178 suppresses a number of 24.576 mHz clocks aε a function of the four bit code output by sigma-delta modulator 66. For example, if the external frequency source on line 162 is 48 kHz, then sigma-delta modulator 66 outputε, on average, a +2 code. The +2 code directs circuit 178 to allow six out of every eight 24.576 mHz clockε to paεε through. Stated another way, circuit 178 εuppreεεeε two out of every eight 24.576 mHz clocks in responεe to a +2 code. If the external clock frequency εource iε 4 kHz, then sigma-delta modulator 66 outputε, on average, an equal number of -3 and -4 codes. The -3 code directs circuit 178 to allow one out of every eight 24.576 mHz clocks to pass through (i.e., circuit 178 suppreεεeε εeven out of every eight 24.576 mHz clockε in reεponse to a -3 code) . The -4 code directε circuit 178 to allow no 24.576 mHz clockε to paεε through (i.e., circuit 178 suppreεses eight out of every eight 24.576 mHz clockε in reεponεe to a -4 code) . On average, therefore, one out of every εixteen 24.576 mHz clockε will paεs through suppreεεor circuit 178 in reεponεe to an average of -3 and -4 codeε. If, however, the εame clockε are suppresεed for each four-bit code from sigma-delta modulator 66, then unwanted tones may appear in the output data stream on line 182. Therefore, circuit 178 also performs the additional function of randomly suppreεεing clock cycles in order to prevent unwanted tones in the output data stream on line 182. Randomizing enεures that pulseε in each of the eight poεitions (recall that there are eight 24.576 mHz clock pulseε for each 3.072 mHz clock pulse controlling εigma-delta modulator 66) are εuppressed equally, on average. Thiε may be accomplished by providing a latch for each bit position that iε set whenever the pulse in that position is εuppressed. Pulεeε in that poεition are not εuppreεsed again until all latches correεponding to all the poεitionε have been εet, at which time the latches are cleared and the sequence of suppreεεion iε repeated. Thiε reduces tones that result from the clock pulse suppreεεor. Clock εuppressor circuits are well-known in the art. One example of εuch a circuit may be found in Phaεe Locked Loopε, Theory, Deεign, and Applicationε by Dr. Roland E. Beεt, publiεhed by McGraw-Hill Book Company, © 1984. Clock randomizer/suppreεεor circuit 178 outputε a clock signal on line 182 that is εent through divider 184 having a divider ratio of 96 and a divider 188 having a divider ratio of 4 that reduce the suppresεed and randomized 24.576 mHz clock output by clock randomizer circuit 178 to the frequency of the external clock on line 124. Circuitε 184 and 188 may be counterε. For the examples just discuεεed above, if the external clock on line 124 iε 48 kHz, then the εignal on line 182 is approximately 18.432 mHz. When divided by ninety-six and then four, the εignal on line 168 iε 48 kHz. If the external clock on line 124 is 4 kHz, then the signal on line 182 is approximately 1.536 mHz. When divided by ninety-six and then four, the εignal on line 168 iε 4 kHz. Circuit 176, sigma-delta modulator 66 and clock randomizer/suppreεsor circuit 178 together form a digitally-controlled oscillator. FIG. 7 illustrates one embodiment of the phase locked loop 122 used in the circuit of FIG. 5. Phase locked loop 122 is the same as phase locked loop 120. In circuit 122, an external clock source on line 136 is applied to a frequency counter 164 that produces a εignal representative of the period of external frequency source on line 136. In addition, the external clock on line 136 is applied to phase detector 166 that produceε a εignal proportional to the phaεe difference between the external clock on line 136 and a εignal on line 166 to be deεcribed in more detail hereinafter. The output of phase detector 166 iε filtered by differentiating filter 170 and summed in summer 172 with the signal representative of the period of the external clock source on line 136 from the frequency counter 164. The output of summer 172 is fed into an integrating filter 174 that functions as a low-paεs filter. The output of integrating filter 174 iε then εent to a circuit 176 that converts the period to a frequency by performing a 1/period function and providing any appropriate scaling. The signal from circuit 136 iε then εent to εigma-delta modulator 94. The four-bit code from εigma-delta modulator 94 is used to control interpolator 138 or interpolators 30 or 92 in the εame manner aε described in connection with the embodiment of FIGS. 2 and 3, respectively. The 4-bit code iε also fed into a clock generation circuit 179 that effectively produces an output clock at 384 times greater than the signal on line 136. Circuit 179 performs this function by suppressing a certain number of 24.576 mHz clock cycles in responεe to the 4-bit code from εigma-delta modulator 94. The following exampleε will εerve to illuεtrate. Aεεume sigma-delta modulator 94 is clocked by a 3.072 mHz clock. For every 3.072 mHz clock, there are eight 24.576 mHz clocks applied to circuit 179. In accordance with Table 2, circuit 179 suppresεeε a number of 24.576 mHz clockε as a function of the 4-bit code output by sigma-delta modulator 94. For example, if the external frequency source on line 136 is 32 kHz, then sigma-delta modulator 94 outputs, on average, a 0 code. The 0 code directε circuit 179 to allow four out of every eight 24.576 mHz clockε to paεε through. Stated another way, circuit 179 εuppreεεeε four out of every eight 24.576 mHz clockε in reεponεe to a 0 code. If the external clock frequency source is 4 kHz, then sigma-delta modulator 94 outputs, on average, an equal number of -3 and -4 codeε. The -3 code directε circuit 179 to allow one out of every eight 24.576 mHz clockε to pass through (i.e, circuit 179 εuppreεεeε εeven out of every eight 24.576 mHz clockε in reεponse to a -3 code) . The -4 code directs circuit 179 to allow no 24.576 mHz clocks to pass through (i.e., circuit 179 suppresεes eight out of every eight 24.576 mHz clocks in response to a -4 code). On average, therefore, one out of every sixteen 24.576 mHz clocks will paεs through suppresεor circuit 178 in reεponεe to an average of -3 and -4 codes. The remainder of phase locked loop 122 including randomizer/suppressor circuit 179, divider 184, and divider 188 operate in the same manner as discussed in connection with phase locked loop 120. For the examples just discussed above, if the external clock on line 136 is 32 kHz, then the signal on line 182 is approximately 12.288 mHz. When decimated by ninety-six and then four, the εignal on line 168 is 23 kHz. If the external clock on line 136 is 4 kHz, then the signal on line 182 is approximately 1.536 mHz. When decimated by ninety-six and then four, the εignal on line 168 is 4 kHz. Circuit 176, sigma-delta modulator 94, and clock randomizer/suppreεεor circuit 179 together form a digitally-controlled oscillator. The embodiments of the present invention including phase locked loops allow the digital-to-digital converter to accept digital data at any data rate within the working range of the system, and lock to an externally supplied clock source that allows converεion of the incoming digital data to a data rate that is not necesεarily the εame as or even an integer or rational relationship with the master clock controlling the digital-to-digital converter. The embodimentε of the invention illuεtrated in FIGS. 2-3 and 5-5A may be characterized as using a combination of fixed interpolation followed by variable decimation and then variable interpolation followed by fixed decimation. That is, with reference to FIG. 2, the digital data stream on line 12 is interpolated by a fixed ratio to increase the sample rate. Thiε higher εample rate digital signal is then variably decimated under control of sigma-delta modulator 20 to provide the digital data stream on line 14 at another εample rate. Thereafter, the digital data εtream on line 28 (which has the same data rate as the digital data stream on line 14) is variably interpolated under control of sigma-delta modulator 32 to variably increase the sample rate. This higher sample rate digital signal iε then decimated by a fixed ratio to provide the digital data εtream on line 42 at another εample rate. The εample rates of the digital data εtream on lineε 14 and 28 are at a common εample rate. In the illuεtrated embodiment, the common sample rate iε 3.072 mHz. Reference iε now made to FIG. 8 which iε a flow chart illuεtrating a first embodiment of a method of the present invention. FIG. 8 illustrates the method of fixed interpolation followed by variable decimation and then variable interpolation followed by fixed decimation. In FIG. 8, the method begins in εtep 200 in which the input digital data having a first data rate is received. From step 200, the method proceeds to εtep 202 in which the input digital data iε interpolated by a fixed ratio to increase the sample rate of the digital data to provide an overεampled digital data εtream. From εtep 202, the method proceedε to εtep 204 in which a firεt sampling frequency select signal representative of the sample rate of the digital data received in εtep 200 iε received. From εtep 204, the method proceedε to εtep 206 in which the first sampling frequency select signal is sigma-delta modulated. From step 206, the method proceeds to εtep 208 in which the interpolated digital data iε decimated under control of the sigma-delta modulated frequency select signal by a ratio determined by the sigma-delta modulated firεt sampling frequency select signal. From step 208, the method proceeds to step 210 in which a εecond εampling frequency εelect εignal representative of the desired output sample rate is received. From εtep 210, the method proceedε to εtep 212 in which the εecond εampling frequency εelect signal is εigma-delta modulated. From εtep 212, the method proceedε to step 214 in which the digital data iε interpolated by a ratio determined by the εigma-delta modulated εecond εampling frequency εelect εignal to increase the sample rate of the digital data. From step 214, the method proceeds to step 216 in which the interpolated digital data is decimated to provide the output digital data at the desired sample rate. From step 216, the method proceeds to step 218 in which the digital signal is output. FIG. 9 is a block diagram broadly illustrating a second embodiment of the invention. Aε with the firεt embodiment illuεtrated in FIGS. 2-3, the overall purpoεe of circuit 250 iε to receive a digital data εtream on line 12 at any data rate within a predetermined working range of the εyεtem and to convert the digital data to a digital data stream on line 42. The data rate of the digital data stream on line 42 can be the same as, higher, or lower than the data rate of the digital data stream on line 12. Except as specified, circuit 250 operates in the εame manner aε the firεt embodiment of the invention. In circuit part 274 of the circuit 250 illustrated in FIG. 9, the digital data on line 12 is interpolated by interpolator 252 under control of clock randomizer/suppresεor circuit 178 which is in turn controlled by sigma-delta modulator 20 to produce a higher sample rate digital signal on line 17. Interpolator 252 increases the sample rate of the digital data stream (that is, converts the digital data stream into a higher sample rate digital data stream) on line 17 by using a sample and hold technique that repeats the digital sample for a specified number of clock cycles in a manner well— nown to those skilled in the art. One skilled in the art will appreciate that other techniques may be used for increasing the sample rate of the data stream on line 12, εuch aε interpolation techniqueε that insert zeros between data samples. The purpose of interpolator 252 iε to increaεe the εample rate of the digital data εtream on line 12 to create a εo-called overεampled εignal. The interpolation ratio (i.e., the ratio by which the εample rate of the digital data on line 12 iε increased by interpolator 252 is controlled by clock rando izer/suppreεεor circuit 178 which iε in turn controlled by εigma-delta modulator 20. The higher εample rate digital data εtream on line 17 iε then εent to a digital filter 18 which removes any images of the original digital signal aε a reεult of the interpolation proceεε. The filtered digital data εtream on line 19 iε then εent to a decimation block 254 that decimates the digital data stream on line 19 by a fixed decimation ratio to produce the digital data stream on line 14 having a fixed predetermined data rate. Although filter 18 and decimation block 254 have been illuεtrated aε εeparate circuit elements for illustrative purpoεeε, one εkilled in the art will appreciate that theεe functions may be performed by a single computation element, such as an FIR or IIR filter in a well known manner. Sigma-delta modulator 20 operateε in the εame manner aε deεcribed in connection with the embodiment of FIGS. 2-3. The m-bit code output εignal on line 260 from εigma-delta modulator 20 iε fed into the clock randomizer/εuppreεεor circuit 178 that effectively produceε an output clock at 384 timeε greater than the data rate of the digital εignal on line 12. In one embodiment, clock 262 iε a 24.576 mHz clock. Circuit 178 operateε in the εame manner aε already deεcribed in connection with FIGS. 6 and 7. The following explanation is provided for additional clarification. Circuit 178 provides a clock on line 258 by εuppreεεing a certain number of clockε from clock 262 in reεponεe to the m-bit code on line 260 from sigma-delta modulator 20. If, however, clocks in the same temporal positions are suppreεεed for each multi-bit code from sigma-delta modulator 20, then unwanted tones may appear in the output data stream on line 258. Therefore, circuit 178 alεo performε the additional function of randomly εuppressing clock cycleε in order to prevent unwanted toneε in the output data εtream on line 258. Aε deεcribed previouεly, clock εuppreεsor and randomizer circuits are well known in the art. One example of such a circuit may be found in Phase Locked Loops by Dr. Roland E. Best, published by McGraw-Hill Book Company, copyright 1984. Clock randomizer/suppressor circuit 178 is needed in the second embodiment to produce a clock on line 258 having a clock frequency that is 384 times the data rate specified by sampling frequency selection signal 24 since εigma-delta modulator 20 iε clocked uεing a fixed clock frequency and a variable clock frequency iε needed to variably interpolate the data on line 12. Clock randomizer/suppresεor circuit 178 outputε a clock signal on line 258 that controls the interpolation of interpolator 252. The digital data at the predetermined data rate on line 14 is optionally filtered by a filter 11 aε deεcribed in connection with the firεt embodiment of the invention. The filter data from filter 11 on line 28 iε sent to circuit part 276 of circuit 250. In circuit part 276 of the circuit 250 illustrated in FIG. 9, the filtered digital data stream on line 28 is εent to interpolator 270. Interpolator 270 increaεes the sample rate of the digital data stream (that iε, convertε the digital data εtream into a higher εample rate digital data εtream) on line 28 by, for example, inεerting zeros between data samples, in a manner well-known to those skilled in the art. One skilled in the art will appreciate that other techniques may be used for increasing the sample rate of the data stream on line 28, such as sample and hold techniques. As noted previously, the purpoεe of interpolator 170 iε to increaεe the εample rate of the digital data εtream on line 28 to create a so-called oversampled signal. A higher εample rate digital data stream on line 34 is then εent to a digital filter 36 which removeε any imageε of the original digital εignal aε a result of the interpolation procesε. The filtered digital data εtream on line 38 is then sent to a decimation block 272 that decimates the digital data stream on line 38 under control of clock randomizer/suppreεεor circuit 179 which is in turn controlled by the εigma-delta modulator 32 aε will be explained in more detail hereinafter. Although filter 36 and decimation block 272 have been illuεtrated as separate circuit elements for illustrative purposes, one skilled in the art will appreciate that these functions may be performed by a εingle computational element, such as an FIR or IIR filter in a well-known manner. Sigma-delta modulator 20 operates in the same manner as deεcribed in connection with the embodiment of FIGS. 2-3. The m-bit code output εignal on line 264 from εigma-delta modulator 32 iε fed into a clock randomizer/εuppreεεor circuit 179 that effectively produceε an output clock at 384 times greater than the data rate of the digital signal on line 28. In one embodiment, clock 262 iε a 24.576 mHz clock. Circuit 179 operateε in the same manner as circuit 178. The following explanation is provided for additional clarification. Circuit 179 provideε a clock on line 268 by εuppreεεing a certain number of cycleε of clockε from clock 262 in reεponεe to the m-bit code on line 264 from sigma-delta modulator 32. If, however, the same clocks in the εame temporal poεitions are suppresεed for each multi-bit code from εigma-delta modulator 32, then unwanted tones may appear in the output data stream on line 268. Therefore, circuit 179 also performs the additional function of randomly suppreεεing clock cycleε in order to prevent unwanted toneε in the output data εtream on line 268. Aε deεcribed previouεly, clock suppressor and randomizer circuits are well-known in the art. One example of such a circuit may be found in Phaεe Locked Loopε by Dr. Roland E. Beεt, publiεhed by McGraw-Hill Book Company, © 1984. Clock εuppressor/randomizer circuit 179 is needed in the second embodiment to produce a clock on line 268 having a clock frequency that is 384 times the data rate specified by εampling frequency selection number 44 since sigma-delta modulator 32 iε clocked uεing a fixed clock frequency and a variable clock frequency iε needed to variably decimate the data on line 38. Clock randomizer/εuppressor circuit 179 outputε a clock εignal on line 268 that controls the decimation of decimator 272 to provide the digital data stream on line 42 having a sample rate (Fs2) selected by sampling frequency select signal 44. FIG. 10 illustrateε a more detailed embodiment 300 of the circuit illuεtrated in FIG. 9. The purpose and operation of circuit 300 is analogous to the first embodiment of the invention illustrated in FIGS. 2-3. The higher sample rate digital data on line 60 iε then εent to a sine 96 3 -type filter 302 that removeε imageε of the digital data εtream on line 60 that reεult from the interpolation process. The filtered higher sample rate digital data on line 304 is then sent to interpolator 306 that increases the sample rate by a variable ratio so that the digital data on line 308, after filtering by filter 310 and decimation by a fixed ratio of eight in decimator 314, emerges on line 64 with a sample rate of 3.072 mHz. Filter 310 may be an FIR or IIR filter. The functions of decimator 314 and filter 74 may be combined into a single element as noted previously. Sigma-delta modulator 66 produces a four-bit code representative of frequency selection number 72 at a constant rate of 3.072 mHz in responεe to clock 70. However, interpolator 306 muεt produce the digital data εtream on line 308 having a εample rate of 24.576 mHz εo that, when decimated by a factor of eight by decimator 314, the data emergeε on line 64 with a sample rate of 3.072 mHz. Therefore, clock randomizer/εuppressor circuit 178 iε needed to produce a variable rate clock on line 316 to variably interpolate the data on line 304. Table 1 illuεtrateε the relationship among the four-bit codes that are produced by εigma-delta modulator 66, the number of clockε that are allowed to paεε through randomizer/εuppreεεor circuit 178 and the output εample rate that the four-bit code correεponds to when modulator 66 is clocked uεing a 3.072 mHz clock and when clock randomizer/εuppreεεor circuit 178 and interpolator 306 are clocked uεing a 24.576 mHz clock. Some exampleε will illuεtrate the operation of the εecond embodiment. Aεέume, for purpoεes of illustration, that the εample rate of the digital data εtream on line 50 iε 48 kHz. Interpolator 52 increaεes this εample rate to 192 kHz. Interpolator 58 increaεeε the 192 kHz εignal to 18.432 mHz. Twenty-bit frequency εelection number 72 iε εelected εuch that upon εigma-delta modulation by the fourth order four-bit εigma-delta modulator 66, the four-bit codes generated will be, on average, a +2 code although other four-bit codes will be produced with a lower frequency of occurrence. In accordance with Table 1, the +2 code is processed by clock randomizer/suppreεsor circuit 178 to allow six out of every eight 24.576 mHz clock cycles from clock 262 to pasε through to generate a clock having an average frequency of 18.432 mHz. Interpolator 306 deliverε data on line 308 at a rate of 24.576 mHz. Data arriveε at the interpolator 306 on line 304 at 18.432 mHz in thiε example. Each time the 18.432 mHz clock on line 316 iε active, a new data point haε arrived at the interpolator input on line 304. Interpolator 306 inεertε thiε data point into the outgoing data εtream on line 308 εo that the 18.432 mHz data iε delivered at 24.576 mHz on line 308. Interpolator 306 performε thiε function by εample and holding each 18.432 mHz data point every 24.576 mHz clock until the next 18.432 mHz data point arriveε. Alternatively, Interpolator 306 may inεert zeroε between each data point at 18.432 mHz to deliver the data at 24.576 mHz. The uεe of a εample and hold technique iε advantageouε becauεe it automatically compenεateε for the energy lost in creating the imageε of the original εignal due to the interpolation process. As a result, interpolator 306 increaεes the sample rate of the digital data εtream on line 304 from 18.432 mHz to 24.576 mHz on line 308. Upon filtering by filter 310 and decimation by decimator 314, the digital data emerges on line 64 with a εample rate of, on average, 3.072 mHz. In another example, aεεume that the digital data εtream on line 50 has a data rate of 4 kHz. Interpolator 52 increases this data rate to 16 kHz. Interpolator 58 increases the 16 kHz data rate to 1.536 mHz. In order that the digital data stream on line 64 have a data rate of 3.072 mHz, the digital data stream on line 60 at 1.536 mHz must be effectively interpolated by a factor of sixteen so that the data rate of the digital data εtream on line 308 haε a data rate of 24.576 mHz. Therefore, the twenty-bit frequency εelection number 72 iε choεen εuch that εigma-delta modulator 66 produceε, on average, an equal number of -3 and -4 codeε although other four-bit codeε will be produced, but with a lower frequency of occurrence. That is, occasionally, -2, -1, and even leεε frequently, +1, +2 codes will be produced. As εhown in Table 1, the -3 code directs circuit 178 to allow one out of every eight 24.576 mHz clocks to pasε through (i.e. circuit 178 suppresses seven out of every eight 24.576 mHz clocks in reεponεe to a -3 code) . The -4 code directε circuit 178 to allow no 24.576 mHz clockε to paεε through (i.e. circuit 178 εuppreεεeε eight out of every eight 24.576 mHz clockε in reεponse to a -4 code). On average, therefore, one out of every sixteen 24.576 mHz clocks will paεε through εuppreεεor circuit 178 in reεponεe to an average of -3 and -4 codeε. At the illuεtrated interpolation ratios and clock frequencies, the -3 code repreεentε a sampling frequency of 8 kHz and the -4 code represents a sampling frequency of DC (i.e. no signal). Therefore, on average of many samples the -3 and -4 four-bit codes represent a εampling frequency of 4 kHz timeε 384 to provide a clock on line 316 at (384) (4 kHz) = 1.536 mHz. In the manner juεt described in the previous example, interpolator 306 respondε to the clock on line 316 to increaεe the εampling frequency of the 1.536 mHz data on line 304 to 24.576 mHz on line 308. It is to be noted that the digital data streams are indicated as being N-bitε wide. N may be any number of bitε and iε typically choεen to be the wideεt bit εtream commenεurate with the signal-to-noise ratio requirements of the particular application. The εample rate converted digital data εtream on line 64 optionally is sent to filter 74 which operates as described in connection with FIG. 3. The filtered digital data stream having a data rate of 3.072 mHz on line 86 is then fed into circuit part 303 of circuit 300. The filtered digital data εtream on line 86 is then sent to interpolator 320. Interpolator 320 increases the sample rate of the digital data stream on line 86 by a factor of eight uεing, for example, a zero fill technique that inεertε zeroε between the digital εampleε. As is well-known, the parameters of filter 324 can be adjusted to compensate for any loss of gain. A higher sample rate signal on line 322 output by interpolator 320 (now at 24.576 mHz) iε then fed into digital filter 324. Aε stated previously, other techniques, such as sample and hold techniqueε, may be uεed to increase the sampling rate in place of interpolator 320. The filtered higher εample rate digital data on line 326 iε then sent to decimator 328 that decreaseε the sample rate by a variable ratio so that the digital data on line 114, after filtering by filter 98 and decimation by a fixed ratio of ninety-six in decimator 104 and a fixed ratio of four in decimator 112, emerges on line 114 with a sample rate specified by frequency selection number 116. Filter 98 is a εinc 93 3 -type filter but could be any type of FIR or IIR filter. In addition, filter 98 and decimator 328 could be combined into a εingle element aε noted previouεly. Sigma-delta modulator 94 produceε a four-bit code repreεentative of frequency εelection number 116 at a conεtant rate of 3.072 mHz in reεponεe to clock 70. However, decimator 328 muεt produce the digital data εtream on line 96 having εample rateε of, for example, between 1.536 mHz and 24.576 mHz depending upon the desired sample rate of the output data stream. Therefore, clock randomizer/suppresεor circuit 179 is needed to produce a variable rate clock on line 318 to variable decimate the data on line 326. Table 2 illustrates the relationship among the four-bit codeε that are produced by sigma-delta modulator 94, the number of clockε that are allowed to paεε through randomizer/suppressor circuit 179, and the output sample rate that the four-bit code corresponds to when modulator 94 is clocked using a 3.072 mHz clock and when clock randomizer/εuppressor circuit 179 is clocked using a 24.576 mHz clock. Some examples will illustrate the operation of the εecond embodiment. Assume, for purposeε of illuεtration, that the εample rate of the digital data εtream on line 86 iε an overεampled data εtream having a conεtant εample rate of 3.072 mHz. Aεεume that the deεired sample rate of the digital data stream on line 114 iε 48 kHz. Interpolator 320 increases the data rate of the digital data stream on line 86 by a factor of eight to 24.576 mHz. To produce the digital data stream on line 114 at 48 kHz, the digital data stream on line 102 must have a sample rate of 192 kHz and the digital data stream on line 110 must have a sample rate 18.432 mHz. Therefore, twenty-bit frequency selection number 116 is selected. such that upon εigma-delta modulation by the fourth order four-bit εigma-delta modulator 94, the four bit codeε generated will be, on average, a +2 code although other four bit codeε will be produced but with a lower frequency of occurrence. The +2 code is then applied to clock randomizer/suppressor circuit 179. For every 3.072 mHz clock applied to sigma-delta modulator 94, there are eight 24.576 mHz clocks applied to clock randomizer/suppressor circuit 179. In accordance with Table 2, circuit 179 suppresses a number of 24.576 mHz clocks as a function of the four-bit code output by sigma-delta modulator 94. The +2 code directs circuit 98 to allow six out of every eight 24.576 mHz clocks to pasε through. Stated another way, circuit 179 εuppreεseε two out of every eight 24.576 mHz clockε in response to a +2 code. As discussed previously, circuit 179 randomly suppresses the specified number of clock cycles in order to prevent unwanted tones in the output data stream on line 318. In another example, asεume that the deεired sample rate of the digital data stream on line 114 is 4 kHz. Interpolator 320 increaseε the data rate of the digital data stream on line 86 by a factor of eight to 24.576 mHz. To produce the digital data stream on line 114 at 4 kHz, the digital data εtream on line 102 muεt have a sample rate of 16 kHz and the digital data stream on line 110 must have a sample rate of 1.536 ml- Therefore, twenty-bit frequency selection number 116 is selected such that εigma-delta modulator 94 produces, on average, an equal number of -3 and -4 codes although other four-bit codes will be produced, but with a lower frequency of occurrence. That is, occasionally, -2, -1, and even less frequently, +1, +2 codes will be produced. Aε εhown in Table 2, the -3 code directs circuit 179 to allow one out of every eight 24.576 mHz clockε to paεε through (i.e., circuit 179 εuppreεses seven out of every eight 24.576 mHz clockε in reεponεe to a -3 code). The -4 code directε circuit 179 to allow no 24.576 mHz clocks to paεs through (i.e., circuit 179 suppreεεes eight out of every eight 24.576 mHz clocks in responεe to a -4 code). On average, therefore, one out of every εixteen 24.576 mHz clockε will paεs through suppressor circuit 179 in response to an average of -3 and -4 codes. RECTIFIED SHEET (RULE 91) ISA EP At the illustrated interpolation ratios and clock frequencies, the -3 code representε a εampling frequency of 8 kHz and the -4 code repreεentε a εampling frequency of DC (i.e., no εignal). Therefore, on average of many εamples, the -3 and -4 four-bit codes represent a sampling frequency of 4 kHz times 384 to provide a clock on line 318 at (4 kHz (384)=1.536 mHz. It is to be noted that digital data εtreams are indicated as being N-bits wide. N may be any number of bitε and iε typically choεen to be the widest bit stream commensurate with the signal-to-noise ratio requirements of the particular application. The embodiments of the invention illustrated in FIGS. 9-10 may be characterized as using a combination of variable interpolation followed by fixed decimation and then fixed interpolation followed by variable decimation. That is, with reference to FIG. 9, the digital data stream on line 12 is interpolated under control of εigma-delta modulator 20 to provide the digital data εtream on line 17 at a higher εample rate. Thiε higher εample rate digital data εtream iε then decimated by a fixed ratio to provide the digital data stream on line 14 at another sample rate. Thereafter, the digital data stream on line 28 (which has the εame data rate as the digital data stream on line 14) is interpolated by a fixed ratio to increaεe the sample rate. Thiε higher sample rate digital εignal iε then variably decimated under control of εigma-delta modulator 32 to provide the digital data εtream on line 42 at another data rate. The sample rates of the digital data stream on lines 14 and 28 are at a common sample rate. In the illustrated embodiment, the common sample rate is 3.072 mHz. Reference is now made to FIG. 11 which is a flow chart illustrating a second embodiment of a method of the present invention. FIG. 11 illuεtrateε the method of variable interpolation followed by fixed decimation and then fixed interpolation followed by variable decimation. In FIG. 11, the method beginε in step 340 in which the input digital data having a first data rate iε received. From step 340, the method proceeds to εtep 342 in which a first sampling frequency select εignal representative of the sample rate of the digital data received in step 340 iε received. From εtep 340, the method proceeds to εtep 344 in which the firεt εampling frequency εelect εignal iε εigma-delta modulated. From εtep 344, the method proceeds to εtep 346 in which the digital data iε interpolated by a ratio determined by the εigma-delta modulated first sampling frequency select signal to increaεe the sample rate of the digital data. From step 346, the method proceeds to step 348 in which the interpolated digital data is decimated by a fixed ratio. From step 348 the method proceeds to step 350 in which the decimated digital data from step 348 is interpolated by a fixed ratio to increase the εample rate of the digital data to provide an oversampled digital data stream. From εtep 350, the method proceedε to εtep 352 in which a εecond εampling frequency select signal representative of the desired output sample rate is received. From εtep 352, the method proceeds to εtep 354 in which the second sampling frequency select signal is εigma-delta modulated. From 354, the method proceeds to step 356 in which the interpolated digital data is decimated under control of the sigma-delta modulated frequency select signal by a ratio determined by the εigma-delta modulated εecond sampling frequency select εignal to provide the output digital data at the deεired sample rate. From step 356, the method proceedε to εtep 358 in which the digital signal is output. Reference iε now made to FIG. 12 which figure illuεtrateε a third embodiment 370 of the preεent invention. In particular, FIG. 12 modifies the circuit of FIG. 10 by eliminating the clock randomizer/suppreεεor circuit. In all other respects, the components and operation of the circuit of FIG. 12 are the εame as those illustrated in FIG. 10. The circuit of FIG. 12 operateε in accordance with the method illuεtrated in FIG. 11. Since the clock randomizer/suppresεor circuit iε eliminated, εigma-delta modulator 94 produceε a four-bit code that directly controls the decimation ratio provided by decimation block 328 and sigma-delta modulator 66 produces a four-bit code that directly controlε the interpolation ratio provided by interpolator 306. Table 3 illuεtrateε the relationεhip among the four-bit codes that are produced by sigma-delta modulator 66 or 94, the intervals at which decimator 328 produces an output or the ratio by which the sample rate on line 304 is increaεed, and the εampling frequency that the four-bit code correspondε to when modulator 66 or 94 iε clocked uεing a 3.072 mHz clock. For example, a -4 code controlε decimator 328 to produce one output for every sample on line 326 and a +3 code controls decimator 328 to produce one output every eight samples on line 326. In the same way, a -4 code controls interpolator 306 to maintain the same sample rate aε on line 304 and a +3 code controlε interpolator 306 to increaεe the εample rate on line 304 by a factor of eight. Table 3 SAMPLE RATE INCREASE FACTOR 4 BIT CODE PRODUCE AN OUTPUT CORRESPONDING EVERY P SAMPLES TO SAMPLING FREQUENCY OF (kHz) +5 10 4.8 +4 9 5.333 +3 8 6 +2 7 6.857 +1 6 8 0 5 9.6 -1 4 12 -2 3 16 -3 2 24 1 48 -5 0 00 FIG. 13 graphically illustrateε the 1/n relationεhip between the four-bit codeε and the correεponding εampling frequency. One εkilled in the art will appreciate that the εyεtem iε nonlinear in the sense of mapping the four-bit codes to a corresponding sampling frequency only because of the particular interpolation ratios, decimation ratios, and data rates chosen. However, the syεtem itεelf iε linear and, by providing an operation that corrects for the nonlinear mapping of the four-bit codes to the corresponding sampling frequency, a linearly mapped syεtem aε in the first two embodiments previously deεcribed can be provided. Alternatively, the interpolation ratioε, decimation ratioε, and data rateε may be εelected εo that there iε a linear relationship between four-bit codeε and corresponding sampling frequencies. One skilled in the art will also appreciate that the 1/n relationship between four-bit codes and εampling frequency illuεtrated in FIG. 13 and Table 2 is meant to be exemplary only; other relationships are possible (for all embodiments of the invention) and are to be conεidered within the εcope of the preεent invention. The circuit illuεtrated in FIG. 12 can generate εampling frequencieε within the 0 to 64 kHz range by varying the ratio of four-bit codeε in the same manner as discuεεed in conjunction with the first two embodiments. The embodiment illustrated in FIG. 12 can alεo be uεed with the circuitε illuεtrated in FIGS. 14 and 15 in the εame manner. Although the mapping between four-bit codeε and εampling frequency iε nonlinear in the embodiment illuεtrated in FIG. 12, this embodiment does provide certain advantageε. In the embodiment illuεtrated in FIGS. 9-10, a clock randomizer/suppressor circuit was used. The clock randomizer/εuppreεεor circuit can reεult in a εyεtem having a reduced εignal to noiεe ratio aε compared to the embodimentε of the invention illuεtrated in FIGS. 2-3, εince the clock randomizer/suppresεor circuit reproceεεeε the εigma-delta modulated clock εignal generated by the εigma-delta modulator and εuppreεεeε clock εignalε in a linear manner. This may degrade the noise shaping provided by the sigma-delta modulator. The circuit illuεtrated in FIG. 12 is advantageous in that the clock randomizer/suppreεεor circuit iε eliminated thereby avoiding degradation in the εignal to noiεe ratio. FIG. 14 illuεtrateε another embodiment 251 of the invention in which digital phaεe locked loopε 120 and 122 are incorporated into the circuits of FIGS. 9 or 10. The phase locked loops operate aε previously described in connection with the discussion of FIG. 5. FIG. 15 illustrates another embodiment 253 of the invention in which a single phase locked loop iε uεed in the εecond embodiment of the invention. The phaεe locked loop operateε in the manner deεcribed in connection with FIG. 5A. Phaεe locked loops can be used in all embodiments of the invention. FIG. 16 illustrateε another embodiment of the invention in which a number of digital εignalε that may have different data rateε can be combined into a combined or mixed -digital signal having a data rate that is not necesεarily and an integer multiple of any of the data rateε of the incoming digital data εtreamε. In circuit 380, a number of digital data streams are supplied to a multiple number of circuit parts 13, 51, 146, 274 or 301. These circuit parts operate as already previouεly deεcribed. Aε long aε each circuit part iε clocked uεing the εame clock frequency, the digital data εtream on lineε 388, 390, . . . 392 will all have the same data rate that can then be combined in summer 394 to provide a combined or mixed digital signal on line 396. In this aspect of the invention, any combination of circuit parts 13, 51, 146, 274 and 301 can be used to provide the digital data streams at the common data rate. This aεpect of the invention thuε advantageouεly provideε an apparatus for mixing digital signals that may have differing data rates. FIG. 17 illustrates, in circuit 400 an apparatus for suppling digital signalε that may have different data rates from a digital data stream having a single data rate where the data rate of the digital data εtreamε to be output doeε not need to be an integer multiple of the common digital data rate. Aε illuεtrated in FIG. 17, a digital data εtream on line 402 having a common data rate is supplied to a multiple number of circuit parts 15, 90, 276, or 303. Each of theεe circuit parts takes the common data rate and can convert the digital data to digital data streams 404, 406, . . . 408 that may have different data rates. Any combination of circuit parts 15, 90, 276 or 303 can be used in the circuit of FIG. 17. In both FIGS. 16 and 17, if analog to digital converters were used to supply the input digital signalε and/or digital to analog converterε were used on the outputs of these circuitε, an apparatus that can advantageously digitally combine analog signals to provide a εingle digital signal or a combined analog signal can be provided. FIG. 18 illustrates the method of digitally mixing or combining digital signals having differing data rates in accordance with the present invention. In FIG. 18, the method begins in step 420 in which digital data at a first data rate is received. From εtep 420, the method proceedε to εtep 422 in which the digital data at the first data rate is converted to digital data at a second data rate in responεe to a firεt εigma-delta modulated control signal to provide a first digital data εtream at the εecond data rate. From step 422, the method proceeds to step 424 in which digital data at a third data rate iε received. From step 424, the method proceeds to step 426 in which the digital data at the third data rate in converted to digital data at the second data rate in response to a second sigma-delta modulated control εignal to provide a εecond digital data stream at the second data rate. From step 426, the method proceedε to εtep 428 in which the firεt and second digital data streamε are combined RECTIFIED SHEET (RULE 91) ISA/EP into a εingle digitally mixed data εtream. From εtep 428, the method proceedε to εtep 430 in which the digitally mixed data εtream iε output. FIG. 19 illuεtrateε the method of the invention for digitally providing different digital data εtreamε from a single digital data stream. The method beginε in εtep 440 in which digital data at a firεt data rate iε received. From εtep 440, the method proceeds to step 442 in which the digital data at the first data rate is converted to digital data at a second data rate in response to a first sigma-delta modulated control signal. From step 442, the method proceeds to step 444 in which the digital data at the first data rate is converted to digital data at a third data rate in reεponεe to a second sigma-delta modulated control signal. From step 444, the method proceeds to εtep 446 in which the digital data at the εecond data rate iε output. From εtep 446, the method proceeds to εtep 448 in which the digital data at the third data rate iε output. For the methodε illuεtrated in FIGS. 18 and 19, converting εtepε 422, 426, 442, and 444 can be performed aε specifically illustrated by the methods illuεtrated in FIGS. 8 and 11. In εummary, the present invention, in one embodiment, converts an incoming digital data stream to a common data rate by interpolating to create an oversampled εignal and then variably decimating the overεampled εignal to provide a digital data εtream at the common data rate. The common data rate digital data εtream iε then variably interpolated to create an overεampled signal and then decimated by a fixed decimation ratio to provide a digital data stream at the output having a deεired εample rate. In another embodiment, the present invention converts an incoming digital data stream to a common data rate by variably interpolating the incoming digital data stream to provide an oversampled signal and then decimating the oversampled signal by a fixed decimation ratio to provide a digital data stream at the common data rate. The common data rate digital data εtream iε then interpolated by a fixed ratio to provide an overεampled εignal and then variably decimated to provide a digital data εtream at the output having a desired εample rate. The present invention can thus convert incoming digital data at any data rate within the working range of the system to an output digital data stream at any arbitrary data rate within the working range of the syεtem. The present invention may also be used to convert an incoming digital signal to a digital signal having the common data rate. For example, with reference to FIG. 2, an incoming digital signal on line 12 can be converted to a digital εignal having a common data rate on line 28. Thiε common rate digital on line 28 can be output aε an output signal to be used by other devices that require digital data at the common data rate. This aεpect of the preεent invention iε advantageouε because it allows digital data streamε having differing data rateε to be converted to a digital data εtream having a common data rate. Thiε εame kind of converεion is also provided by all embodiments of the invention. Aε a reεult, the present invention provides an advantageous apparatus and method for digitally mixing or combining signalε that may have different εample rate. In addition, when the digital εignalε to be combined are provided by analog to digital converterε and reconverted to analog signalε by a digital to analog converter aε in the co-pending applicationε incorporated herein by reference, the preεent invention provideε an advantageouε apparatuε and method for mixing or combining analog εignal εourceε. In the εame manner, the preεent invention can convert a digital data stream at the common data rate to a digital data stream at any data rate within the working range of the system. For example, with reference to FIG. 2, a digital data stream on line 28 can be converted to a digital data stream at any data rate and output on line 42. Thiε aεpect of the preεent invention iε advantageouε becauεe it allowε the digital data stream on line 28 at the common data rate to be converted to a digital data stream at any other data rate, thuε allowing the invention to provide an interface between a common data rate and data rateε that may be required by other digital εystemε. This same kind of conversion is also provided by all embodiments of the invention. In addition, when the digital signal to be interfaced iε provided by an analog to digital converter and when the rate-converted digital εignalε are reconverted to analog εignalε by digital to analog converters as in the co-pending applications incorporated herein by reference, the present invention provides an advantageous apparatus and method for providing a number of analog signal sources from digital signalε that may have different εample rateε. The present invention advantageously converts an incoming digital data stream at any data rate within the working range of the system to an outgoing digital data stream at any data rate within the working range of the system. The data rates of the incoming digital data stream, the outgoing digital data stream, the common data rate, and the clock rate of the system clock do not need to be related by any integer or rational relationship. Another significant advantage of the preεent invention is that the digital-to-digital converter does not have to be capable of interpolating the digital data up to the lowest common frequency between the incoming or outgoing digital data rate and the modulator clock frequency. Thiε iε due to the sigma-delta modulation of the sampling intervals. Unlike prior art digital-to-digital converterε, the sampling interval doeε not have to correεpond exactly to a fixed relationship between the incoming or outgoing digital data rate and the modulator clock. Since the incoming, outgoing, and common sample rates are sigma-delta encoded in the present invention, the sample rates, on average, will repreεent the deεired sample rates with the noise or jitter on the sampling points being pushed into the higher frequency rangeε. The present invention thus takeε advantage of εigma-delta encoding of the time baεe to avoid the need for interpolation to very high frequencies, which in the prior art, typically were in the gigahertz range. An additional benefit of this process is that when the preεent invention is incorporated into an integrated circuit, a significant savingε in chip area can be realized by the uεe of lower interpolation ratioε. Another important advantage of the preεent invention iε that the εigma-delta modulatorε uεed to control decimation and interpolation can be clocked uεing a fixed clock frequency, allowing optimization of the modulator operation at the fixed clock frequency. Finally, by appropriate combination of εigma-delta control codeε in appropriate percentageε, an infinite number of sample rateε for the output digital data εtream can be provided. Theεe sample rates do not need to have any integer or rational relationship with the master clock used to run the digital-to-digital converter or the εample rate of the incoming digital data εtream. Although interpolation haε been used herein to explain the method (and an interpolator aε the apparatuε) by which a digital data εtream is converted into a higher sample rate digital data εtream, the preεent invention iε not εo limited. Any method or apparatus that converts the digital data εtream into a higher εample rate digital data εtream may be uεed to practice the invention. Interpolators and decimators uεeful in the preεent invention may be constructed as εhown in Introduction to Digital Signal Proceεεing by John Proakis and Dimitris Manolakiε, published by Macmillan Publishing Company, © 1988. There are many referenceε describing sigma-delta εystems. One example iε entitled Mixed-Signal Design Seminar publiεhed by Analog Deviceε, Inc., 1991, which iε incorporated herein by reference. Having thuε deεcribed at leaεt one illuεtrative embodiment of the invention, variouε alterationε, modificationε, and improvementε will readily occur to thoεe skilled in the art. Such alterations, modifications, and improvements intended to be within the εpirit and εcope of the invention. Accordingly, the foregoing description is by way of example only and iε not intended aε limiting. The invention iε limited only aε defined in the following claims and the equivalents thereto.

Claims: CLAIMS 1. A digital to digital converter syεtem, compriεing: firεt interpolation meanε for receiving a digital εignal having a firεt data rate and for supplying a digital signal having a firεt increased data rate; firεt decimation meanε, coupled to the interpolation means, for decimating the digital εignal having the firεt increaεed data rate to provide a digital εignal having a εecond data rate; firεt modulator meanε, coupled to and controlling the first decimation means, for providing a firεt modulated output εignal repreεentative of the firεt data rate and for controlling the decimation meanε to provide the digital signal having the second data rate; second interpolation means, coupled to the firεt decimation means, for receiving the digital signal having the εecond data rate and for εupplying a digital εignal having a εecond increaεed data rate; εecond decimation meanε, coupled to the εecond interpolation meanε, for decimating the digital εignal having the εecond increased data rate to provide a digital signal having a third data rate; and εecond modulator meanε, coupled to and controlling the εecond interpolation meanε, for providing a εecond modulated output εignal repreεentative of the third data rate and for controlling the εecond interpolation meanε to provide the digital εignal having the εecond increaεed data rate. 2. A digital to digital converter εyεtem, compriεing: firεt interpolation meanε for receiving a digital εignal having a firεt data rate and for εupplying a digital εignal having a firεt increaεed data rate; firεt decimation meanε, coupled to the interpolation meanε, for decimating the digital εignal having the firεt increaεed data rate to provide a digital εignal having a second data rate; firεt modulator meanε, coupled to an controlling the firεt interpolation means, for providing a firεt modulated output εignal repreεentative of the firεt data rate and for controlling the firεt interpolation means to provide the digital signal having the first increased data rate; εecond interpolation meanε, coupled to the first decimation means, for receiving the digital signal having the second data rate and for suppling a digital signal having a εecond increaεed data rate; εecond decimation means, coupled to the second interpolation meanε, for decimating the digital signal having the εecond increased data rate to provide a digital signal having a third data rate; and second modulator means, coupled to and controlling the second decimation meanε, for providing a εecond modulated output εignal repreεentative of the third data rate and for controlling the second decimation means to provide the digital signal having the third data rate. 3. The digital to digital converter syεtem of claim 1 or 2, wherein the firεt and second modulator means compriεe a εigma-delta modulator. 4. The digital to digital converter εyεtem of claim 3, wherein the firεt and second modulated output signalε are multi-bit codes. 5. The digital to digital converter syεtem of claim 3, wherein the first and second sigma-delta modulators are n -order modulators wherein n l• 6. The digital to digital converter system of claim 3, wherein the first sigma-delta modulator modulates a εampling frequency select signal representative of the first data rate, 7. The digital to digital converter εyεtem of claim 6, wherein the εecond εigma-delta modulator modulates a εampling frequency select signal representative of the third data rate. 8. The digital to digital converter syεtem of claim 1 or 2, further comprising a filter means, coupled between the firεt decimation means and the second interpolation means, for filtering out noiεe and images of the digital signal having the first data rate. 9. The digital to digital converter syεtem of claim 3, further compriεing a memory meanε for storing a plurality of frequency selection numbers repreεentative of at least one of the firεt and third data rate and means for selecting one of the frequency selection numbers in responεe to a selection signal and for providing the selected number to at least one of the first and second sigma-delta modulators as the sampling frequency select signal. 10. The digital to digital converter system of claim 7, wherein the first interpolation meanε interpolates the digital signal having the first data rate by a fixed ratio. 11. The digital to digital converter syεtem of claim 9, wherein the firεt decimation meanε decimates the digital εignal having the first increased data rate by a ratio determined by the εampling frequency εelect εignal repreεentative of the firεt data rate to provide the digital εignal having the εecond data rate. 12. The digital to digital converter system of claim 11, wherein the second interpolation means interpolates the digital signal having the second data rate by a ratio determined-by the sampling frequency select signal representative of the third data rate to provide the digital signal having the εecond increaεed data rate. 13. The digital to digital converter εyεtem of claim 12, wherein the εecond decimation meanε decimateε the digital εignal having the second increased data rate by a fixed ratio. 14. The digital to digital converter system of claim 7, wherein the first interpolation meanε interpolateε the digital εignal having the firεt data rate by a ratio determined by the sampling frequency select-εignal representative of the firεt data rate to provide the digital signal having the first increased data rate. 15. The digital to digital converter syεtem of claim 14, wherein the first decimation means decimates the digital signal having the first increased data rate by a fixed ratio. 16. The digital to digital converter syεtem of claim 15, wherein the second interpolation means interpolateε the digital signal having the second data rate by a fixed ratio. 17. The digital to digital converter syεtem of claim 16, wherein the second decimation means decimateε the digital εignal having the εecond increased data rate by a ratio determined by the sampling frequency εelect εignal repreεentative of the third data rate to provide the digital signal having the third data rate. 18. The digital to digital converter syεtem of claim 17, further comprising a first clock generator means, coupled to the firεt modulator means, for generating, in response to the first modulated output signal, a clock having a frequency representative of the first data rate. 19. The digital to digital converter of claim 18, further compriεing a εecond clock generator means, coupled to the εecond modulator meanε, for generating, in reεponεe to the εecond modulated output εignal, a clock having a frequency repreεentative of the third data rate. 20. The digital to digital converter of claim 1 or 2, further compriεing: firεt phaεe locked loop means, coupled to the first εigma-delta modulator meanε, for receiving a εignal repreεentative of the firεt data rate, locking to the signal, and providing a first control signal to the firεt sigma-delta modulator means that controlε the firεt εigma-delta modulator meanε to provide the firεt εigma-delta modulated output εignal. 21. The digital-to-digital converter of claim 1, 2 or 20, further comprising: second phase locked loop means, coupled to the second sigma-delta modulator means, for receiving a signal representative of the third data rate, locking to the signal, and providing a control signal to the second εigma-delta modulator meanε that controlε the second sigma-delta modulator means to provide the εecond εigma-delta modulated output εignal. 22. A digital to digital converter εyεtem, comprising: a first interpolator; a first decimator having an input electrically coupled to an output of the first interpolator; a first modulator electrically coupled to a control input of the first decimator and providing a temporally noise-shaped control signal that controlε a decimation ratio provided by the firεt decimator; a second interpolator having an input electrically coupled to an output of the first decimator; a second decimator having an input electrically coupled to an output of the second interpolator; and a second modulator electrically coupled to a control input of the second interpolator and providing a temporally noiεe-εhaped control εignal that controlε an interpolation ratio provided by the second interpolator. 23. A digital to digital converter syεtem, compriεing: a firεt interpolator; a first decimator having an input electrically coupled to an output of the first interpolator; a first modulator electrically coupled to a control input of the first interpolator and providing a temporally noise-εhaped control εignal that controlε an interpolation ratio provided by the firεt interpolator; a εecond interpolator having an input electrically coupled to an output of the firεt decimator; a second decimator having an input electrically coupled to an output of the second interpolator; a εecond modulator electrically coupled to a control input of the εecond decimator and providing a temporally noiεe-εhaped control εignal that controls a decimation ratio provided by the second decimator. 24. The digital to digital converter of claim 22 or 23, wherein the first and second modulators compriεe εigma-delta modulatorε. 25. A method of converting a firεt digital εignal to a second digital signal, comprising the step of: receiving a digital signal having a first data rate; modulating a first control signal to provide a first modulated. output signal representative of the first data rate; increasing the first data rate to provide a digital signal having a first increaεed data rate; decimating the digital εignal having the firεt increased data rate in response to the first modulated output signal to provide a digital signal having a εecond data rate; modulating a second control signal to provide a εecond modulated output εignal representative of a third data rate; increaεing the εecond data rate to provide a digital signal having a εecond increaεed data rate in reεponεe to the second modulated output signal; and decimating the digital signal having the second increased data rate to provide a digital signal having the third data rate. 26. A method of converting a firεt digital εignal to a second digital signal, compriεing the εtepε of: receiving a digital εignal having a first data rate; modulating a first control signal to provide a first modulated output signal repreεentative of the firεt data rate; increaεing the firεt data rate to provide a digital signal having a first increased data rate in reεponse to the first modulated output εignal; decimating the digital εignal having the firεt increaεed data rate to provide a digital εignal having a εecond data rate; modulating a second control εignal to provide a εecond modulated output εignal representative of a third data rate; increasing the second data rate to provide a digital signal having a εecond increaεed data rate; and decimating the digital εignal having the second increased date rate in responεe to the εecond modulated output εignal to provide a digital εignal having the third data rate. 27. The method of claim 25 or 26, wherein the εtepε of modulating the first control signal and modulating the second control signal further comprise εigma-delta modulating the firεt control εignal and the second control signal. 28. The method of claim 25 or 26, further comprising the step of filtering the digital signal having the second data rate. 29. The method of claim 25, wherein the step of increasing the first data rate includes increasing the first data rate by a fixed ratio. 30. The method of claim 29, wherein the εtep of decimating the digital εignal having the first increased data rate includes decimating the digital signal having the first increased data rate by a ratio determined by the first modulated output signal. 31. The method of claim 30, wherein the step of increasing the second data rate includes increasing the second data rate by a ratio determined by the second modulated output εignal. 32. The method of claim 31, wherein the εtep of decimating the digital εignal having the second increased data rate includeε decimating the εecond increaεed data rate by a fixed ratio. 33. The method of claim 26, wherein the step of increasing the first data rate includes increaεing the first data rate by a ratio determined by the first modulated output signal. 34. The method of claim 33, wherein the εtep of decimating the digital εignal having the firεt increaεed data rate includeε decimating the digital signal having the first increased data rate by a fixed ratio. 35. The method of claim 34, wherein the step of increasing the εecond data rate includeε increaεing the εecond data rate by a fixed ratio. 36. The method of claim 35, wherein the εtep of decimating the digital εignal having the second increased data rate includeε decimating the digital εignal having the second increased data rate by a ratio determined by the second modulated output signal. 37. A method of converting a first digital signal to a second digital signal comprising the εtepε of: receiving a digital εignal having a firεt data rate; increasing the first data rate by a fixed ratio to provide a digital εignal having a firεt increaεed data rate; decimating the digital signal having .the first increased data rate to provide a temporally noiεe-εhaped digital εignal having a second data rate; increasing the εecond data rate by a variable ratio to provide a temporally noiεe-εhaped digital εignal having a εecond increaεed data rate; and decimating the noiεe-shaped digital signal having the εecond increaεed data rate by a fixed ratio to provide a digital εignal having a third data rate. 38. A method of converting a firεt digital εignal to a εecond digital εignal, compriεing the εtepε of: increasing the first data rate by a variable ratio to provide a temporally noise-shaped digital signal having a first increased data rate; decimating the noiεe-εhaped digital εignal having the firεt increased data rate by a fixed ratio to provide a digital signal having a second data rate; increasing the εecond data rate by a fixed ratio to provide a digital εignal having a εecond increaεed data rate; and decimating the digital signal having the second increased data rate to provide a temporally noiεe-εhaped digital εignal having a third data rate. 39. A method of combining at leaεt two digital εignalε, comprising the εtepε of: receiving a digital εignal having a firεt data rate; converting the digital εignal having the firεt data rate to a firεt digital εignal having a εecond data rate in reεponεe to a firεt modulated control εignal; receiving a digital εignal having a third data rate; converting the digital εignal having the third data rate to a εecond digital εignal having the εecond data rate in reεponεe to a second modulated control signal; combining the first digital signal having the second data rate and the second digital signal having the second data rate into a single digital signal having the second data rate. 40. A method of providing at least two digital signalε from a single digital εignal, comprising the steps of: receiving a digital signal having a firεt data rate; converting the digital εignal having a first data rate to a digital signal having a second data rate in reεponεe to a firεt modulated control εignal; converting the digital εignal having the firεt data rate to a digital εignal having a third data rate in reεponεe to a second modulated control signal; outputting the digital signal having the second data rate; and outputting the digital εignal having the third data rate. 41. The method of claim 39 or 40, wherein the firεt modulated control εignal and the εecond modulated control signal comprise sigma-delta modulated control εignalε. 42. An apparatuε for combining at leaεt two digital signals, comprising: means for receiving a digital εignal having a firεt data rate; meanε for converting the digital εignal having the first data rate to a first digital signal having a εecond data rate in responεe to a firεt modulated control εignal; means for receiving a digital signal having a third data rate; means for converting the digital signal having the third data rate to a second digital εignal having the εecond data rate in reεponεe to a εecond modulated control εignal; and meanε for combining the firεt digital εignal having the εecond data rate and the εecond digital εignal having the εecond data rate into a single digital signal having the εecond data rate. 43. An apparatuε for providing at leaεt two digital εignalε from a εingle digital εignal, compriεing: meanε for receiving a digital εignal having a firεt data rate; meanε for converting the digital εignal having the firεt data rate to a digital εignal having a εecond data rate in reεponεe to a first modulated control signal; means for converting the digital signal having the first data rate to a digital signal having a third data in reεponεe to a εecond modulated control εignal; means for outputting the digital signal having the second data rate; and means for outputting the digital εignal having the third data rate. 44. The apparatuε of claim 42 or 43, wherein the first modulated control signal and the εecond modulated control εignal compriεe εigma-delta modulated control εignalε. 45.. A digital to digital converter εystem, comprising: means for converting a digital signal having a first data rate to a digital εignal having a εecond data rate in reεponse to a first modulated control signal; and means for converting the digital εignal having the εecond data rate to a digital εignal having a third data rate in reεponεe to a εecond modulated control εignal. 46. The digital to digital converter of claim 45, wherein the firεt modulated control signal and the second modulated control signal comprise εigma-delta modulated control εignalε. 47. A method of converting a firεt digital εignal to a second digital signal, comprising the steps of: converting a digital signal having a first data rate to a digital signal having a second data rate in reεponεe to a firεt modulated control εignal; and converting a digital signal having the second data rate to a digital signal having a third data rate in response to a second modulated control signal. 48. The method of claim 47, wherein the firεt modulated control εignal and the εecond modulated control εignal compriεe sigma-delta modulated control εignalε.

Inventors: CELLINI RONALD A, SOBOL JAMES M, WILSON JAMES, CELLINI, RONALD, A., SOBOL, JAMES, M., WILSON, JAMES
Applicants: ANALOG DEVICES INC, CELLINI RONALD A, SOBOL JAMES M, WILSON JAMES, ANALOG DEVICES, INC., CELLINI, RONALD, A., SOBOL, JAMES, M., WILSON, JAMES
Application year: 1995
Main classification: H03H17
IPC codes: H03H17, H03L7, H03M7