BOOSTER

Abstract: This invention relates to a booster circuit for generating a boosted voltage higher than a source voltage using the source voltage. The booster circuit has two capacitors. The two capacitors are alternately charged and discharged in response to a voltage applied to an input terminal. The first capacitor is discharged to boost a voltage at a boosting node, whereas the second capacitor is discharged to boost a voltage at an output terminal. Further, the booster circuit includes a control circuit. When the voltage at the input terminal changes from an "H" level to an "L" level, the control circuit supplies a voltage for discharging the first capacitor to the first capacitor after the second capacitor has been brought into a charging state. Since the voltage at the output terminal is reduced under the charge of the second capacitor, a transistor is activated in response to the voltage at the output terminal. As a result, the boosting node and the source voltage can be prevented from being brought into conduction by the transistor. Thereafter, the voltage at the boosting node is boosted under the discharge of the first capacitor, and the output terminal and the source voltage are brought into conduction by transistors activated in response to the boosted voltage at the boosting node. It is thus possible to increase the voltage at the output terminal to the source voltage V CC .

Description: A dynamic random access memory or the like needs to increase or boost a source voltage using its inner circuit. In order to reliably read data written into a memory cell, for example, a word line needs to be boosted. With a change of the source voltage from a voltage of 5V to a low source voltage of 3.3V the source voltage needs to be boosted by the inner circuit. A booster circuit is used to cope with such a case. The booster circuit generates a voltage (hereinafter called "boosted voltage") higher than the source voltage based on the source voltage. The booster circuit now requires generating a boosted voltage stable even to a reduction in source voltage. Further, the booster circuit for generating the boosted voltage stable to the reduction in source voltage tends to increase in complexity. A booster circuit simple in circuit configuration is also required to reduce a chip area. US-A-3,949,047 discloses a MOS DC voltage booster circuit, which generates a stepped up DC voltage from a lower magnitude supply voltage and a periodic input signal. The circuit includes a field effect transistor load device coupled between a supply voltage conductor and a capacitor. From the junction between the load field effect transistor and the capacitor is a diode connected field effect transistor, the source of which is connected to an output node. The voltage booster circuit also comprises a voltage regulator circuit, which limits the voltage at the output node. DE 26 32 199 describes an integratable voltage multiplier with cascaded FET stages, each providing the supply for the next stage and each incorporating cross coupled FETs. The outputs of the cross coupled FETs are combined via two diodes to a common output. The outputs of both FETs are connected to two separate clock lines via capacitors. The integratable voltage multiplier also includes a third FET, which is in drain/source parallel with one of the other FETs, and its gate is connected to a precharging rail. The two diodes are formed by two FETs, and the circuit forms one stage of the multiplier. Several of the stages are cascaded such that the common output of one stage is connected to the supply rail of the next stage. An object of the present invention is to provide a booster circuit for generating a boosted voltage stable even to a reduction in source voltage. Another object of the present invention is to provide a booster circuit simple in circuit configuration. According to the present invention, there is provided a booster circuit for generating a boosted voltage higher than a source voltage, based on the source voltage, comprising:- an input terminal capable of being set to a first voltage and a second voltage; an output terminal; a boosting node capable of being set to the boosted voltage; a first conducting circuit for bringing said output terminal and a power voltage source into conduction in response to a voltage applied to said boosting node; a first diode circuit connected between said output terminal and said boosting node so as to be in the forward direction with respect to said boosting node; a first capacitor circuit connected between said input terminal and said output terminal, said first capacitor circuit being dischargeable in response to the second voltage set to said input terminal and chargeable based on a voltage applied to said output terminal in response to the first voltage set to said input terminal; a second capacitor circuit connected between said input terminal and said boosting node, said second capacitor circuit being dischargeable in response to the first voltage set to said input terminal and chargeable based on the voltage set to said boosting node in response to the second voltage set to said input terminal; and a clamping circuit connected to said output terminal, for reducing the voltage of said output terminal when the voltage thereof has reached a predetermined voltage or more. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a booster circuit showing a first embodiment of the present invention; Figure 2 is a timing chart for describing the operation of the booster circuit shown in Figure 1; Figure 3 is a circuit diagram of a booster circuit illustrating a second embodiment of the present invention; and Figure 4 is a timing chart for describing the operation of the booster circuit shown in Figure 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Booster circuits according to preferred embodiments of the present invention will hereinafter be described with reference to the accompanying drawings. Fig. 1 is a circuit diagram of a booster circuit 100 showing a first embodiment of the present invention. The booster circuit 100 shown in Fig. 1 comprises two cross-connected transistors 110 and 120, two MOS capacitors (hereinafter called "capacitors") 130 and 140, two inverters 150 and 160 and a control circuit 170. The transistors 110 and 120 are of N-type MOS transistors respectively. Both drains of the transistors 110 and 120, which serve as first electrodes, are respectively electrically connected to a power voltage source for supplying a source voltage V CC thereto. The source of the transistor 110, which serves as a second electrode and the gate of the transistor 120, which serves as a control electrode, are both electrically connected to a node 101. The source of the transistor 120, which serves as a second electrode and the gate of the transistor 110, which serves as a control gate, are both electrically connected to an output terminal V OUT . The gate of the capacitor 130, which serves as a first electrode, is electrically connected to the node 101. The gate of the capacitor 140, which serves as a first electrode, is electrically connected to the output terminal V OUT . The input of the inverter 150 is electrically connected to an input terminal V IN , whereas the output thereof is electrically connected to the input of the inverter 160. The output of the inverter 160 is electrically connected to the source and drain of the capacitor 140 each of which serves as a second electrode. The input of the control circuit 170 is electrically connected to the input terminal V IN , whereas the output thereof is electrically connected to the source and drain of the capacitor 130 each of which serves as a second electrode. The control circuit 170 comprises two inverters 171 and 172 and a NOR circuit 173. The input of the inverter 171 is electrically connected to the input terminal V IN , whereas the output thereof is electrically connected to the input of the inverter 172. Both inputs of the NOR circuit 173 are respectively electrically connected to the output of the inverter 172 and the input terminal V IN . The output of the NOR circuit 173 is electrically connected to the second electrode of the capacitor 130. The inverters 171 and 172 are identical in delay time to the inverters 150 and 160. A delay time caused by the NOR circuit 173 is identical to or slightly shorter than the delay time caused by each of the inverters 150 and 160. Namely, the control circuit 170 generates an output whose voltage level changes from a low-voltage level (hereinafter called "L" level) to a high-voltage level (hereinafter called "H" level), which is delayed a given amount with respect to an output voltage of the inverter 160, which changes from the "H" level to the "L" level. The operation of the booster circuit 100 constructed as described above will now be described with reference to a timing chart shown in Fig. 2. When the booster circuit 100 is in its initial state, the voltage at the input terminal V IN is of the "L" level. Therefore, a voltage outputted from the inverter 160 is brought to the "L" level and a voltage outputted from the control circuit 170 is brought to the "H" level. Consequently, the capacitor 130 is discharged to boost or increase a voltage at the node 101 which has been precharged to the source voltage V CC , up to a voltage of V CC + V t + α (where V t : threshold voltage of each of the transistors 110 and 120). Thus, since the voltage supplied to the control electrode of the transistor 120 is brought to the voltage of V CC + V t + α, the transistor 120 is activated to supply the source voltage V CC to the output terminal V OUT as it is. At this time, the capacitor 140 is charged based on the voltage at the output terminal V OUT . The transistor 110 is deactivated because the control electrode and the first electrode thereof are supplied with the source voltage V CC and the second electrode thereof is supplied with the voltage of V CC + V t + α. Next, the voltage applied to the input terminal V IN changes from the "L" level to the "H" level. Therefore, the voltage outputted from the inverter 160 is brought to the "H" level and the voltage outputted from the control circuit 170 is brought to the "L" level. Thus, the capacitor 130 is charged based on the voltage at the node 101. Further, the capacitor 140 is discharged to increase or boost the voltage at the output terminal V OUT to the voltage V CC + V t + α. At this time, the voltage at the node 101 is reduced to a voltage of less than V CC - V t under the charge of the capacitor 130. Since, however, the control electrode of the transistor 110 is supplied with the boosted voltage of the output terminal V OUT , the transistor 110 is activated. Therefore, the voltage at the node 101 can be raised up to the source voltage V CC . Next, the voltage applied to the input terminal V IN changes from the "H" level to the "L" level. Therefore, the output voltage of the inverter 160 is brought to the "L" level. Thus, the capacitor 140 is charged in accordance with the voltage at the output terminal V OUT . Owing to this charging operation, the voltage at the output terminal V OUT is reduced to a voltage of less than the source voltage V CC . Correspondingly, the transistor 110 is deactivated. Now, the voltage outputted from the NOR circuit 173 in the control circuit 170 changes from the "L" level to the "H" level after the voltage inputted to the input terminal V IN has been delayed by the inverters 171 and 172 in the control circuit 170. Namely, the voltage outputted from the control circuit 170 is changed after the output voltage of the inverter 160 has been changed. The capacitor 130 is discharged owing to the change in the output voltage of the control circuit 170. Therefore, the voltage at the node 101 is boosted up to the voltage of V CC + V t + α. The transistor 120 is activated in response to the boosted voltage at the node 101. Thus, the voltage at the output terminal V OUT is raised to the source voltage V CC . Since, at this time, the control electrode and the first electrode of the transistor 110 are supplied with the source voltage V CC and the second electrode thereof is supplied with the voltage of V CC + V t + α, the transistor 110 remains inactive. Now, the lowering of the voltage level of the output terminal V OUT by the capacitor 140 changes the output voltage of the control circuit 170 after deactivation of the transistor 110. By doing so, an electric charge corresponding to the boosted voltage at the node 101 can be prevented from being escaped into the source voltage V CC through the transistor 110. As described above, the booster circuit 100 shown in Fig. 1 sets the voltage at the node 101 to the source voltage V CC in advance in response to the voltage at the output terminal V OUT . Thus, the voltage level at the node 101 can be sufficiently ensured even in the case of a low source voltage lower than 5V. As a result, the voltage at the output terminal V OUT can be set to the source voltage V CC in advance. It is therefore possible to reliably set the output terminal V OUT to the boosted voltage. Further, since the voltage at the node 101 is brought to the source voltage V CC in advance in response to the voltage at the output terminal V OUT , the booster circuit 100 is simple in circuit configuration. A second embodiment of the present invention will now be described with reference to the accompanying drawings. Fig. 3 is a circuit diagram of a booster circuit 200 showing the second embodiment of the present invention. The booster circuit 200 shown in Fig. 3 comprises two transistors 210 and 220, capacitors 230 and 240 corresponding to two MOS capacitors, two inverters 250 and 260 and a clamping circuit 270. The transistors 210 and 220 are of N-type MOS transistors respectively. The drain of the transistor 210, which serves as a first electrode, is electrically connected to the gate of thereof, which serves as a control electrode. The source of the transistor 210, which serves as a second electrode, is electrically connected to a node 201. Namely, the transistor 210 is of a diode forward-connected in the direction of the node 201. The first electrode of the transistor 210 is also electrically connected to an output terminal V OUT . The drain of the transistor 220, which serves as a first electrode, is electrically connected to a power voltage source for supplying a source voltage V CC . The source of the transistor 220, which serves as a second electrode, is electrically connected to the output terminal V OUT . The gate of the transistor 220, which serves as a control electrode, is electrically connected to the node 201. The gate of the capacitor 230, which serves as a first electrode, is electrically connected to the node 201. The gate of the capacitor 240, which serves as a first electrode, is electrically connected to the output terminal V OUT . The input of the inverter 250 is electrically coupled to an input terminal V IN , whereas the output thereof is electrically connected to the source and drain of the capacitor 230 each of which serves as a second electrode. The input of the inverter 260 is electrically connected to the second electrode of the capacitor 230, whereas the output thereof is electrically connected to the source and drain of the capacitor 240 each of which serves as a second electrode. The clamping circuit 270 is electrically connected to the first electrode of the transistor 210. The clamping circuit 270 comprises two transistors 271 and 272. The transistors 271 and 272 are both of N-type MOS transistors. The source of the transistor 271, which serves as a second electrode, is electrically connected to the power voltage source for supplying the source voltage V CC . The drain of the transistor 271, which serves as a first electrode and the gate thereof, which serves as a control electrode, are both electrically connected to the source of the transistor 272, which serves as a second electrode. The drain of the transistor 272, which serves as a first electrode and the gate thereof, which serves as a control electrode, are both electrically connected to the first electrode of the transistor 210. Namely, each of the transistors 271 and 272 is of a diode forward-connected in the direction of the power voltage source. In other words, the clamping circuit 270 maintains the voltage of the output terminal V OUT at a voltage of less than a predetermined voltage. The operation of the booster circuit 200 constructed as described above will now be described with reference to a timing chart shown in Fig. 4. When the clamping circuit 200 is in its initial state, the voltage at the input terminal V IN is of an "L" level. Therefore, a voltage outputted from the inverter 250 is of an "H" level and a voltage outputted from the inverter 260 is of an "L" level. Consequently, the capacitor 230 is discharged to increase or boost a voltage at the node 201, which has been precharged to the source voltage V CC , up to a voltage of V CC + V t + α (where V t : threshold voltage of the transistor 220). Thus, since a voltage supplied to the control electrode of the transistor 220 is brought to the voltage of V CC + V t + α, the transistor 220 is activated to supply the source voltage V CC to the output terminal V OUT as it is. At this time, the capacitor 240 is charged based on the voltage applied to the output terminal V OUT . Since the control electrode and the first electrode of the transistor 210 are supplied with the source voltage V CC and the second electrode thereof is supplied with the voltage of V CC + V t + α, the transistor 210 is not activated. Next, the voltage at the input terminal V IN changes from the "L" level to the "H" level. Therefore, the output voltage of the inverter 250 is changed to the "L" level and the output voltage of the inverter 260 is changed to the "H" level. Thus, the capacitor 230 is charged based on the voltage at the node 201 and the capacitor 240 is discharged. Owing to the discharge of the capacitor 240, the voltage at the output terminal V OUT is boosted to the voltage of V CC + V t + α. Further, the voltage at the node 201 is lowered to a voltage of less than V CC - V t owing to the charge of the capacitor 230. However, the first electrode and control electrode of the transistor 210 are supplied with the boosted voltage of the output terminal V OUT so that the transistor 210 is activated. Therefore, the voltage at the node 201 can be raised to a voltage of V CC + α corresponding to a voltage reduced by the threshold voltage V t of the transistor 210 from the voltage at the output terminal V OUT . Since the control electrode, first electrode and second electrode of the transistor 220 are supplied with the source voltage V CC , the voltage of V CC + α and the voltage of V CC + V t + α respectively, the transistor 220 is brought into an inactive state. Next, the voltage applied to the input terminal V IN changes from the "H" level to the "L" level. Therefore, the output voltage of the inverter 250 is changed to the "H" level and the output voltage of the inverter 260 is changed to the "L" level. Thus, the capacitor 230 is discharged and the capacitor 240 is charged in accordance with the voltage at the output terminal V OUT . Owing to the discharge of the capacitor 230, the voltage at the node 201 is boosted from the voltage of V CC + α to the voltage of V CC + V t + α. Further, the voltage at the output terminal V OUT is reduced to a voltage of less than V CC owing to the charge of the capacitor 240. Since, however, the control electrode of the transistor 220 is supplied with the boosted voltage of the node 201, the transistor 220 is activated. Therefore, the voltage at the output terminal V OUT can be raised to the source voltage V CC . The operation of the clamping circuit 200 will now be described in detail. Now consider that the boosted voltage of the output terminal V OUT is brought to a voltage of V CC + 2V t or more, for example. At this time, each of voltages V gs between the control electrode (gate) and first electrode (source) of the clamping circuit 271 and between the control electrode (gate) and first electrode (source) of the clamping circuit 272 is brought to the threshold voltage Vt or more. Therefore, the transistors 271 and 272 are both activated. Owing to the activation of the transistors 271 and 272, the output terminal V OUT and the source voltage V CC are electrically brought into conduction. Thus, since current flows from the output terminal V OUT to the source voltage V CC , the voltage at the output terminal V OUT reaches the voltage of V CC + V t + α reduced from the voltage of V CC + 2V t . Correspondingly, the voltage at the node 201 also changes from a voltage of V CC + V t (i.e., V CC + 2V t - V t ) to a voltage of V CC - α. Since, at this time, the transistor 220 is in an deactivated state, an electric charge at the output terminal V OUT is prevented from being escaped into the source voltage V CC through the transistor 220. As described above, the booster circuit 200 shown in Fig. 3 sets the voltage at the node 201 to the source voltage V CC + α in advance in response to the voltage at the output terminal V OUT . Thus, the voltage level at the node 201 can be sufficiently ensured even in the case of a low source voltage lower than 5V. Further, the voltage level at the node 201 can be boosted from the voltage level of the source voltage V CC or more. As a result, the voltage at the node 201 can be reliably boosted as compared with the booster circuit 100 shown in Fig. 1. Further, the clamping circuit 270 is simple in circuit configuration as compared with the control circuit 170 of the booster circuit 100 shown in Fig. 1. The preferred embodiments have been described above in detail. However, the booster circuit of the present invention is not necessarily limited to the configurations of the two embodiments referred to above. Various changes can be made to them. The transistor 210 shown in Fig. 3 may be a PN-junction diode, for example. Further, the transistors 110 and 120 shown in Fig. 1 and the transistor 210 shown in Fig. 3 may be bipolar transistors. The circuit configuration of the control circuit 170 shown in Fig. 1 may be another one if it is operated in a manner similar to the control circuit 170. The number of the series-connected inverters 171 and 172 and the number of the series-connected inverters 150 and 160 may not be two respectively if they are provided as even. Further, the number of the diode-connected transistors in the clamping circuit 270 shown in Fig. 3 may not be two. The number of the transistors may be set according to the upper limit of the voltage applied to the output terminal V OUT .

Claims: A booster circuit (200) for generating a boosted voltage higher than a source voltage, based on the source voltage, comprising:- an input terminal (V IN ) capable of being set to a first voltage and a second voltage; an output terminal (V OUT ); a boosting node (201) capable of being set to the boosted voltage; a first conducting circuit (220) for bringing said output terminal (V OUT ) and a power voltage source (V cc ) into conduction in response to a voltage applied to said boosting node (201); a first diode circuit (210) connected between said output terminal (V OUT ) and said boosting node (201) so as to be in the forward direction with respect to said boosting node (201); a first capacitor circuit (240) connected between said input terminal (V IN ) and said output terminal (V OUT ), said first capacitor circuit (240) being dischargeable in response to the second voltage set to said input terminal (V IN ) and chargeable based on a voltage applied to said output terminal (V OUT ) in response to the first voltage set to said input terminal (V IN ); a second capacitor circuit (230) connected between said input terminal and said boosting node (201), said second capacitor circuit (230) being dischargeable in response to the first voltage set to said input terminal (V IN ) and chargeable based on the voltage set to said boosting node (201) in response to the second voltage set to said input terminal (V IN ); and a clamping circuit (270) connected to said output terminal (V OUT ), for reducing the voltage of said output terminal (V OUT ) when the voltage thereof has reached a predetermined voltage or more. A booster circuit (200) according to claim 1 wherein said first (240) and second (230) capacitor circuits are composed of MOS capacitors respectively. A booster circuit (200) according to claim 1 or 2 wherein said clamping circuit (270) comprises a second diode circuit (271) connected to the power voltage source (V cc ) and connected in the forward direction with respect to the power voltage source (V cc ) and a third diode circuit (272) connected between said second diode circuit (271) and said output terminal (V OUT ) and connected in the forward direction with respect to said second diode circuit (271). A booster circuit (200) according to claim 3, wherein said first (210), second (271) and third (272) diode circuits are composed of N-type MOS transistors respectively. A booster circuit (200) according to any one of claims 1 to 4, wherein said clamping circuit (270) is activated when the source voltage of said power source (V cc ) becomes greater than the sum of threshold voltages of said second (271) and third (272) diode circuits. A booster circuit (200) according to any one of claims 1 to 5, including a first inverter (250) connected between said input terminal (V IN ) and said first capacitor circuit (240) and a second inverter (260) connected between said first inverter (250) and said first capacitor circuit (240).

Inventors: MATSUSHITA YUICHI, MATSUSHITA,YUICHI, MATSUSHITA,YUICHI OKI MICRO DESIGN MIYAZAKI CO LTD
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1995
Main classification: H02M3
IPC codes: G11C11, H01L27, H01L21, H02M3