An image forming apparatus and method for manufacturing the same

Abstract: An image forming apparatus, according to the present invention, comprises a first substrate whereon are provided a functional element and electric wiring that is connected to the functional element, and a second substrate whereon is an area where an image is to be formed, and wherein, with the first substrate and the second substrate being located opposite to each other, space between the first substrate and the second substrate is kept in a pressure-reduced state so as to form an image in the area on the second substrate, and wherein the electric wiring is formed of a laminated conductive material by a process that plates a printed pattern, which is initially deposited by a printing process.

Description: The present invention relates to a method of manufacturing an image forming apparatus, especially but not exclusively one that has a large size display screen, and which is provided in a so-called vacuum container, in which the pressure is substantially reduced. Recently, a light, thin image forming apparatus, a so-called flat display, is attracting attention as the replacement for a large, heavy Braun tube. As such a flat display unit, a liquid crystal display has been enthusiastically studied and developed; there are, however, problems remaining for the liquid crystal display that an image is dark and an angle for field of view is narrow. As a replacement for the liquid crystal display there is a self-emitting flat display, i.e. a plasma display panel (PDP), a fluorescent display tube (VFD), or a multi-electronic source flat type display panel. When compared with a liquid crystal display, a self-emitting flat display provides a brighter image and a larger field of view angle. However, since such a flat display is so designed that a substrate where functional components and electric wiring are provided is arranged in a so-called vacuum container, in which air pressure is substantially reduced, a technique is required that can provide a stable performance for the flat display for an extended period of time. When the wiring for an electronic circuit is to be produced, generally a thin film is formed on a workpiece, such as a substrate, and patterning is performed on the resultant structure. For example, with such one method that is employed, after an Al material has been deposited on the substrate, a wiring pattern is formed for photolithography and etching. Since the procedures of photolithography and etching are complex, a method for forming a wiring pattern without using those procedures is disclosed in Japanese Unexamined Patent Publication No. 3-142894. With the disclosed method, printing is performed directly on a substrate by using an organic metal ink to describe a pattern, followed by electrolytic metal plating of the pattern to provide a metal film of 0.5 to 3 µm. According to the method disclosed in this publication, close adhesion of a fine pattern is increased and a sheet resistance of the fine pattern is reduced. While in the publication an explanation is given for the application of the method for a printer head, an image sensor, and a hybrid IC, there is no description for its application for a self-emitting flat display that is so designed that a substrate, whereon functional components and electric wiring are provided, is arranged in the above described vacuum container. As a self-emitting flat display, a flat image forming apparatus that employs a multi-electronic source to cause a phosphor to become luminescent will now be described. Conventionally a surface conductive emitter, which is described in a report by M. I. Elinson, Radio Eng. Electron Phys., 10 (1965), is known as an element with a simple structure that can emit electrons. This emitter employs a phenomenon whereby the emission of electrons occurs when, in parallel to the film face, a current is supplied to a thin film that is deposited on a substrate and that has a small dimension. Reported as such surface conductive emitters are an element with SnO 2 thin film deposited, as in the report by Elinson, an element with Au thin film deposited (G. Dittmer, Thin Solid Films, 9, 317 (1972)), an element with In 2 O 3 /SnO 2 thin film deposited (M. Hartwell and C. G. Fonstad, IEEE Trans. ED Conf., 519 (1975)), and an element with carbon thin film deposited (Araki et al., Vacuum, Vol. 26, No. 1, p. 22 (1983)). The arrangement of the above Hartwell element is illustrated in Fig. 15 as one specific arrangement of such a surface conductive emitter. In Fig. 15, reference number 201 denotes an insulating substrate, and 203, a thin film for forming an electron emission portion, which is, for example, a H-shaped metal oxide thin film that is deposited by sputtering. Conductive processing called forming, which will be described later, forms an electron emission portion 205. Conventionally, according to the general method for making a surface conductive emitter, before the emission of electrons, conductive processing called forming is performed in advance on the thin film 203 to form an electron emission portion, and the electron emission portion 205 is formed. More specifically, the forming is a process during which a voltage is applied to both ends of the thin film 203 to cause local damage, deformation, or deterioration of the thin film 203, and the electron emission portion 205 that has a high resistance to electricity is provided. In the electron emission portion 205, part of the thin film 203 is fractured and electrons are emitted in the vicinity of the fractured area. Disclosed in USP 5,066,883 is an innovative surface conductive emitter where between the element electrodes are dispersed and located particles that permit the emission of electrons. This electron emitter can control the positioning of electron emission portions more accurately than the conventional surface conductive emitters, making it possible for electron emitters to be arranged more accurately. A specific arrangement for such a surface conductive emitter is shown in Fig. 16. In Fig. 16, reference number 211 denotes an insulating substrate; 213 and 215, element electrodes for electric connection; and 217, a thin film that is made of an electron emission particle material that is dispersed and positioned. For the surface conductive emitter, an appropriate electrode interval between the paired electrodes 213 and 215 is 0.01 µm to 100 µm, and an appropriate a sheet resistance for the electron emission portion in the thin film 217 is 1 x 10 3 Ω/□ to 1 x 10 9 Ω/□. When the above described surface conductive emitter is employed as a flat display, it must be located in a vacuum container because an electron beam is irradiated. In the vacuum container, a face plate is positioned above and almost perpendicularly to the emitter to provide an electron emitting device. When a voltage is applied between the electrodes, a phosphor is irradiated by an electron beam, which is acquired from the electron emission portion, in order to cause the phosphor to become luminescent, making it possible for the emitter to be used as a flat display device. When the screen size of the above described flat display device has been increased, however, the following shortcomings have arisen. Specifically, for manufacturing a thus structured surface conductive emitter, a functional thin film is deposited on a workpiece and patterning is performed on the resultant structure. When the photolithographic technique is employed to produce a fine pattern on a large substrate that is, for example, 40 cm square or larger, a large manufacturing apparatus that includes an aligner is required and the manufacturing costs are enormous. Further, unlike an aligner that is employed for silicon semiconductors, it is difficult for an aligner that handles large substrates to set a pattern processing size to 4 µm or smaller because of optical limits and because a shorter processing time is required for each substrate. The production of a display device that requires much finer patterns is difficult. In addition, for a large substrate of about one meter square, it is difficult to increase the size of the manufacturing device itself. Even if a large device that can be used for exposing could be provided, the processing for each substrate would take longer and the manufacturing costs would be greatly increased. As other methods for processing an electronic circuit, there may be employed a screen printing method, or a method where pattern printing is performed by using a conductive paste or an insulating paste and then annealing the resultant structure to form an electrode wiring pattern and an insulation layer. The patterning that involves the use of a printing method can be employed for comparatively large substrates, and the processing time that is required for each substrate is shorter than that which is required for the photolithographic technique. However, a printed pattern tends to be deformed due to the flowability of resist ink, of a conductive paste or of an insulating paste, the generation of blank areas and the poor transfer of a print pattern, and the pressure exerted by a print pattern. Therefore, delicate control of a pattern meter and skill are required to maintain the high accuracy in the size of pattern. When wiring is formed by printing, that wiring is comparatively inferior in its density. When the surface is enlarged and examined, it is found to be comparatively porous. When such wiring that has inferior density is to be applied to the above described self-emitting flat display, since the circuit substrate with such wiring is positioned in a vacuum container, there are problems, such as the adsorption of gas or the discharge of gas by wiring that has less density, the change in the degree of vacuum due to the gas discharge, and the deterioration of the display performance. Further, to increase the size of the display screen of a flat image-forming apparatus, the length of the drive wiring that is arranged in the screen is extended, and in consonance with the length of the wiring, wiring resistance is increased between a wiring electrode end, to which a voltage is applied, and a wiring electrode end that is opposite it. The following problems may occur, depending on the amount of increase in wiring resistance: 1) A voltage drop relative to the applied voltage occurs, and accordingly, voltages that are applied between the connected elements are different at both ends of wiring are different, so that a difference in the display luminescence is incurred and an uneven image tends to be produced. 2) A time lag occurs between transmitted element drive signals, and the time when a drive signal is provided at the connected elements varies at both ends of wiring. Therefore, for image displaying on a large screen, the period of time for the display of one screen frame is extended and a displayed image is unnatural and is not visually smooth. Thus, the reduction of wiring resistance must also be considered. The present invention is intended as a solution to the problems aforesaid. According to the present invention there is provided a method of manufacturing an image forming apparatus according to claim 1, which comprises a first substrate whereon are provided a functional element and electric wiring that is connected to the functional element and a second substrate whereon is an area where an image is formed, and wherein, with the first substrate and the second substrate being located opposite to each other, space between the first substrate and the second substrate is kept in a pressure-reduced state so as to form an image in the area on the second substrate, comprises the steps of: forming a printed pattern with a printing process; and forming the electric wiring by employing a plating process to deposit a lamina of a conductive material on the printed pattern. According to the aforesaid method, the adsorption of gas by, or the discharge of gas from wiring that has inferior density can be held at zero, or be reduced considerably to a low amount. Thus, changes in the degree of vacuum in the vacuum container that constitutes the image forming apparatus can be limited to considerably small values. In addition, since the wiring resistance is low, an excellent display image condition can be formed stably for an extended period of time. By employing the method of manufacturing an image forming apparatus of the present invention, stable, low-cost manufacturing of image forming apparatuses that have a large display screen is possible. In the appended drawings: Figs. 1A through 1F are specific diagrams illustrating an electric wiring example that is applied to an image forming apparatus manufactured according to the present invention; Figs. 2A through 2E are specific diagrams illustrating a second substrate example in the image forming apparatus manufactured according to the present invention; Fig. 3 is a specific diagram illustrating an example of an image forming apparatus manufactured according to the present invention; Fig. 4 is a specific diagram illustrating another example of an image forming apparatus manufactured according to the present invention; Figs. 5A through 5E are specific diagrams illustrating another electric wiring example that can be applied by the present invention; Figs. 6A through 6E are specific diagrams illustrating an additional electric wiring example that can be applied by the present invention; Fig. 7 is a specific diagram illustrating a further electric wiring example that can be applied by the present invention; Figs. 8A through 8F are specific diagrams illustrating one more electric wiring example that can be applied by the present invention; Figs. 9A through 9C are specific diagrams illustrating still one more electric wiring example that can be applied by the present invention; Figs. 10A through 10F are specific diagrams illustrating still another electric wiring example that can be applied by the present invention; Figs. 11A through 11C are specific diagrams illustrating yet one more electric wiring example that can be applied by the present invention; Figs. 12A through 12F are specific diagrams illustrating yet another electric wiring example that can be applied by the present invention; Figs. 13A through 13C are specific diagrams illustrating a still further electric wiring example that can be applied by the present invention; Figs. 14A through 14F are specific diagrams illustrating yet one further electric wiring example that can be applied by the present invention; Fig. 15 is a specific diagram illustrating a surface conductive emitter example; and Figs. 16A and 16B are specific diagrams illustrating another surface conductive emitter example. A method of manufacturing an image forming apparatus according to the present invention is performed in the above described manner. The present invention is applied to a self-emitting display that is constituted by using a vacuum container. The present invention will now be explained by employing, as a self-emitting display that employs a vacuum container, an image forming apparatus that employs a multi-electronic source to emit a phosphor and that forms an image. One example of an image forming apparatus manufactured according to the present invention will be described while referring to Fig. 4. Fig. 4 is a specific perspective view of the image forming apparatus. In Fig. 4, an electron emitter 41, which serves as a functional element, is formed on a substrate 13 (hereafter also referred to as a "rear plate") while the electron emitter 41 is connected to electric wiring 55 and electric wiring 57. A substrate 53 (hereafter also referred to as a "face plate") is provided opposite the substrate 43 and has an area whereon an image is to be formed. Space between the substrates 43 and 53 is held in a pressure-reduced condition (a substantial vacuum condition) by an associated support frame 45, and in that condition, images are formed on the substrate 53. The substrate 53 is produced by forming a fluorescent film 49 and a metal back 51 on the internal face of a glass substrate 47. Electrons that have been emitted by the electron emitter 41 flow to the metal back 51, to which a high voltage has been applied, and when the electrons strike the fluorescent film 49 fluorescence is induced and an image is formed. More specifically, in the example shown in Fig. 4, via terminals Dox1 through Doxm and Doy1 through Doyn, a voltage is applied to the electron emitter 41, which in turn emits electrons. A high voltage of several kV or higher is applied through a high voltage terminal Hv either to the metal back 51 or to a transparent electrode (not shown) to accelerate an electron beam. When the electronic beam strikes against the fluorescent film 49 and makes the film 49 become fluorescent, an image is displayed. The space between the substrates 43 and 53 can be maintained at a degree of vacuum of 10 -3 Pa (10 -5 torr) to 10 -6 Pa (10 -8 torr). The feature of the present invention is that the electric wiring that is connected to the functional element 41 is formed by employing a plating process to deposit laminate of a conductive material on a printed pattern that is deposited by a printing process. To easily understand the feature of the present invention, an explanation will be given while referring to Fig. 3. Fig. 3 is a specific diagram illustrating another example of an image forming apparatus that employs a surface conductive electron emitter. In Fig. 3, a substrate 1 is constituted by an insulator, element electrodes 3 and 5 are employed for electric connections, and a thin film 7 is including particles which is dispersed. In the surface conductive electron emitter, it is preferable that the width of an interval between the paired electrodes 3 and 5 be from several microns to several hundred microns, that their thickness be several hundred Å (1Å ≡ 0.1 nm) to several µm, and that the thickness of the thin film 7 be several Å (1Å ≡ 0.1 nm) to several thousand Å, preferably several tens of Å to several hundred Å. These dimensions should be set as needed. Printed wiring 9 and printed wiring 11 are connected respectively to the element electrodes 3 and 5. Usually, the wiring 9 and the wiring 11 need have only a thickness that is acquired by the annealing of print paste ink and that is generally in the range of 1 µm to 100 µm, preferably, 2 µm to 80 µm. Plated wiring 13 and plated wiring 15 are deposited on the printed wiring 9 and the printed wiring 11 to a thickness that is selected in order to limit an applied drive voltage drop when wiring is provided over a large area and to reduce wiring resistance that is related to signal delay. In general, while taking stress into account, a wiring thickness is set that is from 1 µm to 100 µm. Since, when compared with thin film and plated wiring, the resistance reduction effect that is achieved with plated wiring having a thickness of about 10 microns or greater is substantial, the thickness of the plated wiring is preferably 10 µm to 100 µm. The face plate is formed by laminating a phosphor 19 and a metal back 21 on a glass substrate 17. A grid electrode 25 , which controls the electron flow, is provided as needed. One example of the method for manufacturing the above described image forming apparatus will now be described while referring to Figs. 1A through 2E. Figs. 1A through 1F concern an electron source substrate, and Figs. 2A through 2E concern a face plate substrate. In Figs. 1A through 1F, by using a screen printing process, conductive paste ink is printed on a substrate 1 that has been well washed, and the resultant structure is annealed to form wiring 11 and wiring 13 (Fig. 1A). Then, a gap resist 27, which serves as an element electrode gap, is formed between the wiring 9 and the wiring 11 by photolithography, and a conductive film that is composed of an element electrode material is deposited by vacuum deposition. The gap resist 27 is then removed and unnecessary conductive film is lifted off to form element electrodes 3 and 5. In this manner, the element electrodes 3 and 5 are laminated on and electrically connected to the wiring 9 and the wiring 11, respectively (Figs. 1B and 1C). Following this, a thin film 7 that is formed of an electron emitting material is deposited at the electrode gap by reverse etching. The formation of the electron emitting material film is performed by the coating and annealing, the vacuum evaporation, the sputtering, or the chemical vapour deposition of an organic metal compound solution, or by the dispersing, coating and annealing of ultra fine particles that consist of electron emitting material (Fig. 1D). Then, patterning with a plating resist 29 is performed to shield an electron emission portion while leaving uncovered portions of the wiring 5 and the wiring 11 This structure is then immersed in a plating bath to deposit plated wiring 13 and plated wiring 15 on the wiring 9 and the wiring 11 (Fig. 1E). Either an electrolytic plating process or a non-electrolytic plating process, or both, can be employed. After the plating is completed, the plating resist 29 is removed to acquire an electron source substrate (Fig. 1F). As a conductive material that is formed by the plating process, one of a metal that contains copper as a primary component, a metal that contains nickel as a primary component, a metal that contains chrome as a primary component, a metal that contains gold as a primary component, or a metal that contains silver as a primary component can be selected. Taking into account electric conductivity and cost, a metal that contains copper is recommended. As the substrate 1, silica glass, glass that contains a reduced amount of impurities such as sodium, soda lime glass, a glass substrate where SiO 2 that is formed by sputtering is laminated on soda lime glass, or ceramics such as alumina may be used. For the element electrodes 9 and 11 any material may be employed as long as it is conductive. For example, there are conductive materials that consist of metals, such as Ni, Cr, Au, Mo, W, Pt, Ti, Al, Cu, and Pd or its alloy, or metals, such as Pd, Ag, Au, RuO 2 , and Pd-Ag or its metal oxide, and glass; transparent conductive materials such as In 2 O 3 -SnO 2 ; and semiconductor materials, such as polysilicon. As the material that forms the thin film 7, which includes an electron emission portion, may be employed, for example, a metal such as Pd, Pt, Ru, Ag, Au, Ti, In, Cu, Cr, Fe, Zn, Sn, Ta, W, or Pb; an oxide such as PdO, SnO 2 , In 2 O 3 , PbO, or Sb 2 O 3 ; a boride such as HfB 2 , ZrB 2 , LaB 6 , YB 4 , or GdB 4 ; a carbide such as TiC, ZrC, HfC, TaC, SiC, or WC; a nitride such as TiN, ZrN, or HfN; a semiconductor such as Si or Ge; carbon; AgMg; NiCu; or PbSn. A fabrication method for a face plate is illustrated in Figs. 2A through 2E. First, a resin such as PVA (poly vinyl alcohol) and a phosphor slurry 31, to which a photosensitive agent is added to make the slurry 31 photosensitive are deposited as solids on the glass substrate 17 that has been well washed, and the resultant structure is dried. As the coating method, spinning, dipping, spray coating, roll coating, screen printing, or offset printing is employed (Fig. 2A). Then, a photomask (not shown) is employed to cover the deposited phosphor slurry 31 and only a necessary portion is exposed to light. During developing, the phosphor slurry 31 at the unneeded portion is removed. The resultant structure is then annealed, and the photosensitive resin is oxidized and burned out to produce the phosphor 19 on which patterning was performed (Fig. 2B). When phosphors for three prime colours, red (R), green (G) and blue (B), are required to provide colours for the display device, the procedures shown in Figs. 1A and 2B are repeated for each colour and patterning is performed to deposit the phosphors on the glass substrate 17 separately. The phosphor 19 is then immersed in a water solution, and a resin thin film, such as a clear lacquer, is developed. Following this, water is eliminated from the solution, a thin resin film 33 is developed and positioned on the phosphor 19, and the resultant structure is dried. This procedure is called filming (Fig. 2C). A metal thin film, such as Al, having a thickness of several hundred Å (1Å ≡ 0.1 nm) is formed by vacuum deposition on the phosphor on which filming was performed, and is employed as a metal back 21 (Fig. 2D). Then, the resin thin film 33 is burnt and removed from the face plate. At this time, the metal back 21 is flattened and positioned as a continuous film on the phosphor 19 (Fig. 2E). In this example, when multiple electron emitters and phosphors are arranged, the arrangement pitch is determined by the number of pixels and a screen size that are required for an image display device. For example, for a screen that is 40 cm long and that has a resolution of 560 scan lines, the pitch per pixel is about 720 µm. Further, for colours, a single pixel must be split so as to provide three prime colours, R, G, and B. If it is evenly split into three parts, the pitch is 240 microns. In this case, the phosphor that corresponds to the electron emission portion can be positioned with a one to one correspondence. In this example, the electron emission portion is accurately located on the substrate 1 by the element electrodes, which were provided by photolithography. The phosphor 19 that corresponds to the electron emission portion is also accurately located on the glass substrate 17 by photolithography. The accuracy in positioning a pattern with photolithography is generally high. Although the accuracy varies depending on the specifications for a mask exposure device, a positioning accuracy error that does not exceed 4 µm can be obtained when positioning a pattern in a 40 cm square printing area. If this positioning error is large, for example, if the position is shifted by 40 µm relative to a pixel pitch of about 240 µm, an adjacent phosphor will be irradiated by electrons, which are emitted from the electron emission portion, in a range of about one sixth the size of the pixel pitch. In this manner, crosstalk will occur at a luminance point. In this example, wiring patterning is performed by screen printing that can cope comparatively well with an increase in the size of a printing area. With screen printing, generally, the position of paste ink after patterning is shifted relative to the position of a print because a screen mesh mask, which serves as a print pattern, is pressed down and slid, together with the paste ink, by a rubber spatula called a squeegee. Although the printing condition affects the positioning difference, in many cases, a positioning difference of about 40 µm occurs locally relative to a printing area of 40 cm square. In this example, however, a pattern positioning difference due to screen printing does not directly relate to crosstalk that occurs because the position of the electron emission portion and the position of the phosphor centre are shifted. More specifically, as long as the electron emission portion is formed at an exact position by photolithography, and the element electrodes are connected to the wiring, a positioning difference for the wiring, on which patterning is performed by the screen printing, does not directly affect the crosstalk at the luminance point. Therefore, a large margin at the connection of the element electrodes and the wiring may be designed by taking into account the distance the wiring position is shifted. The plating process employed in this example can easily provide thick film wiring that has low resistivity. Although depending on a plating method for a film and conditions, the acquired film can have resistivity almost the same as a bulk value of metal and can have a thickness of several µm to 100 µm, so that wiring having a very low resistance can be provided. In a display device with a large screen, it is possible to reduce the voltage drop at an electron emitter that is caused by wiring resistance and to limit the time drive signals are delayed. The shape of the insulating layer may be designed and plated wiring may be formed in such a manner as to facilitate the electrical connection of element electrodes to wiring. Such an example will be explained below. As one example, there is a circuit board, which comprises lower wiring that is formed on an insulating substrate, upper wiring that is formed at right angles to the lower wiring, with an insulating layer in between, so that it is insulated from the lower wiring by the insulating layer, and an electron emitter that is constituted by element electrodes, which are two electrodes that are formed opposite to each other, and a thin film, which contains an electron emitting material, whereupon (a) one of the two element electrodes that are opposite to each other is connected to the lower wiring, and the other electrode is connected to a connection line that is discontinuously formed on the substrate, (b) the insulating layer is deposited extending at right angles to the lower wiring, and the width of the insulating layer is larger at the intersection with the lower wiring than at the intersection with the connection line, (c) the upper wiring is formed on the insulating layer at right angles to the lower wiring so as to have a smaller width at the intersection with the lower wiring than that of the insulating layer, and is insulated from the lower wiring, and (d) a lamina of plated wiring is deposited that has a greater width than that of the upper wiring and a smaller width at the intersection with the lower wiring than does the insulating layer, and the upper wiring is electrically connected to the connection line via the plated wiring. This circuit board will now be described while referring to Figs. 9A through 9C and 10A through 10F. Fig. 9A is a plan view of a partial arrangement of the circuit board; Fig. 9B is a cross sectional view taken along the line IXB-IXB; and Fig. 9C is a cross sectional view taken along the line IXC-IXC. In Figs. 9A through 9C, reference number 1 denotes an insulating substrate;139 and 141 element electrodes; 133, a thin film for forming an electron emission portion; 135 an electron emission portion;137 a thin film that includes the electron emission portion 135; 143 lower wiring; 147 an insulating layer; 149, upper wiring; 145 a connection line to electrically connect the upper wiring 149 and the element electrode 139 and 151 plated wiring. In this circuit board example, distance L1 between the element electrodes 139 and 141 is several µm to several hundred µm. Although the electrode distance L1 is determined by a voltage that is to be applied to the electrodes and an electric field strength with which electrons can be emitted, it is preferably several µm to several tens of µm. The length W1 of the element electrode is several µm to several hundred µm, and film thickness d of the element electrodes 139 and 141 is several hundred Å (1Å ≡ 0.1 nm) to several µm. The thin film 137 that includes the electron emission portion 135 is formed between, and partly on, the element electrodes 139 and 141. Its thickness is several Å to several thousand Å, preferably several tens of Å to several hundred Å. This value is determined as needed by step coverage of the element electrodes 139 and 141 resistances of the electron emission portion 135 and the element electrodes 139 and 141 and the diameter of conductive particles of the electron emission portion 135, conductive processing conditions, etc. The lower wiring 143 and the connection line145 are wiring that is formed on the insulating substrate 1 and that are several µm to several tens of µm. The lower wiring 143 is electrically connected to the element electrode 139. The insulating layer 147 is deposited extending at right angles to the lower wiring 143, and the upper wiring 149 lies over it. The width of the insulating layer 147 is greater at the intersection with the lower wiring 143 and is smaller at the intersection with the connection line 145. The thickness of the insulating layer 147 is several µm to several tens of µm. The thickness of the upper wiring 149 is several µm to several tens of µm. The plated wiring 151 is formed on the upper wiring 149, and with the plated wiring 151, the upper wiring 149, the connection line 145 and the element electrode 141 electrically connected. Since the insulating layer 147 is formed with a sufficient width at the intersection of the lower wiring 143 and the upper wiring 149, the lower wiring 143 is electrically insulated from the upper wiring 149 and the plated wiring 151. The plated wiring 151 connects the upper wiring 149 to the connection line 145. When wiring is to be provided on a large area, in order to reduce wiring resistance that induces a voltage drop of the applied drive voltage and that causes signal delays, an appropriate thickness for the plated wiring 151 is selected as needed. The thickness is generally several tens of µm to several hundred µm. A method for fabricating this circuit board example will be explained while referring to Figs. 10A through 10F. 1) The insulating substrate 1 is washed well with a detergent, pure water, and an organic solvent, and a conductive paste is printed on it by a printing process. The resultant substrate 1 is then annealed to form the lower wiring 143 and the connection line 145 (Fig. 10A). A screen process, for example, is employed as the printing process. 2) An insulating paste is printed, by a printing process on the substrate 1 extending at right angles to the lower wiring 143. The resultant structure is then annealed to form the insulating layer 147, as is shown in Fig. 10B. The width of the insulating layer 147 is greater at the intersection with the lower wiring 143 and is smaller at the intersection with the connection line 145. 3) A conductive paste is printed on the insulating layer 147 by a printing process, and the structure is then annealed to provide the upper wiring 149 (Fig. 10C). Although, in Fig. 10C, the upper wiring 149 is formed so as to be narrower than the insulating layer 147 the width of the upper wiring 149 may be greater than that of the insulating layer 147 at the intersection with the lower wiring 143 andmay be smaller than that of the insulating layer 147 at the intersection with the connection line 145. 4) The resultant substrate is then immersed in a plating bath, and the plated wiring 151 is deposited on the upper wiring 149, which is employed as an electrode. The plated wiring 151 is extended from the top and the side of the upper wiring149 until it reaches the connection line 145. As the plating is continued, the plated wiring 151 is also formed on the connection line 145. When plating is performed while a current that flows between the upper wiring 151 and the connection line 145 is monitored, conductance can be confirmed (Fig. 10D). 5) A conductive thin film is deposited by vacuum evaporation, sputtering, etc., and on it a photoresist that has a predetermined shape is formed by photolithography. By employing the photoresist as a mask, etching is performed on the conductive thin film and thus the element electrodes 139 and 141 are thus provided. Then, photolithography and a lift-off method are employed to deposit the thin film 133 for the forming of an electron emission portion. Vacuum evaporation, sputtering, chemical vapour deposition, coating and annealing of an organic metal compound solution, or the dispersing, coating, and annealing of ultra fine particles is employed for the formation of the thin film 133 (FIG. 10E). The deposition of the element electrodes 139 and 141 and the thin film 133 for forming an electron emission portion may be performed either before or after the plated wiring formation procedure. 6) Sequentially, a forming process is performed by applying, from a power source (not shown), a pulse voltage or a high-speed booster voltage to the element electrodes 139 and 141. Then, when a part of the structure of the thin film 133 is changed and the electron emission portion 135 is thereby formed to provide an electron emitter, the circuit board example is acquired (Fig. 10F). The electron emission portion 135 including conductive particles having a diameter of several Å (1Å ≡ 0.1 nm) to several thousand Å, preferably, 10 Å to 200 Å. This value for the electron emission portion 135 depends on the fabrication processing, such as the processing for the thickness of the thin film 137, which includes the electron emission portion 135, and the forming process conditions, and is determined as needed. The material for the electron emission portion 135 is the same as part, or all, of the elements of the material for the thin film 137 that includes the electron emission portion. It will be easily understood that the following effects can be acquired. (1) Since the rates of gas adsorption and the gas discharge by printed pattern wiring are extremely low, an image forming display is very stable. (2) Since printing and plating are employed, manufacturing costs for a circuit board and an image forming apparatus can be drastically reduced. (3) Since vacuum deposition and photolithography are employed for the formation of necessary portions, a highly functional element that is very accurately controlled can be formed over a large area on a substrate. (4) Since a voltage drop and a delay in the drive signal due to a wiring resistance can be reduced, an image forming device with a reduced degrading in an image quality can be provided. The present invention will now be described in detail while referring to specific embodiments. The present invention is, however, not limited to these embodiments, and the replacement of components and alteration of the design may be performed to the extent that the achievement of the objects of the present invention is not jeopardized. (Embodiment 1) Embodiment 1 will be explained while referring to Figs. 1A through 3. In Fig. 3, a substrate 1 is made of soda lime glass, and printed wiring 9 and printed wiring 11, which have a thickness of about 7 µm, are acquired by printing and annealing Ag paste ink. After the formation of the printed wiring 9 and the printed wiring 11, element electrodes 3 and 5 are formed by photolithographic technology. The element electrodes 3 and 5, respectively, are connected to the printed wiring 9 and the printed wiring 11, and are composed of Ni thin film that are 1000 Å (1Å ≡ 0.1 nm) thick and that employ Ti at a thickness of 50 Å as an underlayer. The electrode interval is 2 µm at the centre and the width of the electrodes is 300 µm. A thin film 7 that consists of Pd particles having a thickness of about 200 Å is acquired by coating with an organic metal compound solution and annealing. Sequentially, a Cr film was deposited by sputtering on a portion where the thin film 7 is not required, and a Cr pattern was fabricated by photolithographic technology. Plated wiring 13 and plated wiring 15 are provided on the printed wiring 9 and the printed wiring 11 by plating with Cu to a thickness of about 50 µm and a width of about 400 µm. After masking has been performed by using a resist on a portion where plating is not required, plating is performed by using the pyrophosphoric acid copper plating bath in Table 1. Pyrophosphoric copper (CuP 2 O 7 •3H 2 O) 80 g/ℓ Pyrophosphoric potassium (K 4 P 2 O 7 ) 300 g/ℓ Ammonia solution 2 ml/ℓ Bath temperature 50°C Cathode current density 4 A/dm 2 In Fig. 3, a glass substrate 17 which is a soda lime plate, is located opposite to the substrate 1 at an interval of 5 mm. A phosphor 19 is located on the substrate 17 at a position that corresponds to an interval between the element electrodes 3 and 5, which are located on the opposite substrate 1. A phosphor is mixed with a photosensitive resin to make a slurry and the mixture is deposited and dried. Patterning is then performed by photolithography to form the phosphor 19. A filming procedure is performed on the phosphor 19, an Al thin film of about 300 Å (1Å ≡ 0.1 nm) thick is deposited by vacuum evaporation, and the film layer is removed by annealing. A metal back 21 is thus provided. The structure where the elements are formed on the substrate 1 is called an element substrate, while the structure where the phosphor 19 and the metal back 21 are formed on the glass substrate 17 is called a face plate. A grid electrode 25 is located between the element substrate and the face plate. The above described components were arranged in a vacuum container, and when a voltage was applied between the plated wiring 13 and the plated wiring 15 to perform a forming process on the thin film 7, an electron emission portion 23 was formed. Then, with the metal back 21 being used as an anode electrode, a voltage of 3 kV for emitting electrons was applied, while a voltage of 14 V that was transmitted across the plated wiring 13 and the plated wiring 15 was applied to the electron emission portion 23 from the element electrodes 3 and 5. Electrons were thereupon emitted. The emitted electrons were controlled by changing the voltage of the grid electrode 25, and the amount of emitted electrons with which the phosphor 19 was irradiated could be adjusted. Therefore, the phosphor 19 could emit light arbitrarily to display an image. On a 40 cm square element substrate, a 350 x 350 matrix of electron emitters was arranged at an arrangement pitch of 1 mm. On the face plate that is opposite the element substrate, were located separate R, G and B phosphors 19. When the positioning accuracy of the printed wiring 9 and the printed wiring 11 on the element substrate was measured, a 30 µm positioning shift was found to have occurred at the end of the substrate with the centre of the substrate as an origin. On the other hand, the positioning of the phosphor 19 relative to the position of the electron emission portion 23 on which patterning was performed by photolithography, was found to be highly accurate with a positioning difference of 4 µm or less. Therefore, when a 350 x 350 pixel image was displayed on the 40 cm square substrate, crosstalk at a luminance point, which occurs due to a positioning shift of the electron emitter and the phosphor, was not caused. Further, the wiring resistance of the plated wiring 13 and the plated wiring 15 could be reduced to about 0.5 Ω between both ends of the 40 cm square substrate, a value which was 1/10 or less than the wiring resistance of only the printed wiring 9 and the printed wiring 11. Therefore, the problems, such as drive signal voltage drops and signal delays, which are caused in the 40 cm square substrate could be substantially removed. Since the printed wiring 9 and the printed wiring 11 are printed and annealed before the element that consists of the element electrodes 3 and 5 and the thin film is fabricated, the printing and annealing processes are not performed on this element and the element is therefore not damaged by heat during the annealing. According to the image forming apparatus of the Embodiment, the adsorption of gas by, or the discharge of gas from wiring that has inferior density could be held at zero, or be reduced considerably low. Thus, changes in the degree of vacuum in the vacuum container that constitutes the image forming apparatus could be limited to considerably small values. And an excellent display image condition could be stably formed for an extended period of time. (Embodiment 2) Embodiment 2 will now be described while referring to the procedure diagrams (plan views) in Figs. 5A through 5E. An example where nine electron emitters, together with wiring, are arranged in a 3 x 3 matrix on a soda lime glass substrate (not shown) is employed. In Figs. 5A through 5E, printed pads 63, which are arranged so that they are in parallel to lower printed wiring 61, are formed by annealing a printed metal paste following the same procedures that are employed for the lower printed wiring 61. Element electrodes 71 and 73, which are respectively connected to the lower printed wiring 61 and the printed pads 63, are formed by photolithography and by using a metal thin film. The element electrodes 71 and 73 have an electrode interval of 2 µm and an electrode width of 200 µm at a mutually adjacent portion. A thin film 75 includes an electron emission portion, which consists of Pd particles of an electron emitting material, and is located on and between the element electrodes 71 and 73. A thin film portion 71 that is located at each electrode gap serves as an electron emission portion, which will be described later. Plated wiring 79 is metallic wiring having a thickness of about 100 µm that is plated as a strip on upper printed wiring 69 A method for manufacturing this element substrate will now be described while referring to Figs. 5A through 5E. Screen printing was performed with Ag paste ink on a soda lime glass substrate that was washed well. By annealing the substrate, the lower printed wiring 61 having a 7 µm thickness and the print pads 63 were formed (Fig. 5A). Then, screen printing was performed using glass paste ink, and by annealing the resultant structure, an insulating layer 65 that is 500 µm wide and about 20 µm thick, and contact holes 67 with 100 µm square openings were provided (Fig. 5B). Thereafter, Ag paste ink was deposited on the insulating layer 65 by screen printing, and by annealing the resultant structure, the upper wiring 69 that is 300 µm wide and 10 µm thick was formed (Fig. 5C). The upper wiring 69 and the printed pads 63 were then electrically connected via the contact holes 67. At this time, step covers for the contact holes 67 are sometimes insufficient when the thickness of the upper wiring 69 is 10 µm in contrast to the thickness of 20 µm for the insulating layer 65. However, the formation of plated wiring during the following procedure can provide sufficient step cover for the contact holes 67. A 50 Å (1Å ≡ 0.1 nm) underlayer made of Ti was formed by sputtering, and was overlaid with 1000 Å of Ni. Then, a photoresist pattern was fabricated in the shape of the element electrode by exposing a projection mask aligner, and the element electrodes 71 and 73 were formed by etching. Sequentially, a Cr film was deposited by sputtering on a portion where the thin film 75 is not required, and a Cr pattern was fabricated by photolithographic technology. An organic palladium compound solution (Catapaste CCP4230, a product name of Okuno Pharmaceutical Co., Ltd.) was deposited and annealed to form a Pd particle film. Further, reverse etching was performed on the Cr pattern and patterning of the thin film 75 was performed at the element electrodes 71 and 73 and at electrode gaps (Fig. 5D). The plated resist was formed by photolithography so as to expose the upper printed wiring 69. The upper printed wiring 69 was rendered conductive and electrolyte plating with Cu was performed on the wiring 69 to provide a plated film of 100 µm. The plating bath employed in this case is the copper sulphate bath shown in Table 2. Copper sulphate (CuSO 4 ) 100 g/ℓ Sulfuric acid (K 4 P 2 O 7 ) 180 g/ℓ Bath temperature 40°C Cathode current density 5 A/dm 2 The element substrate was manufactured by removing the plated resist. At this time, the Cu plated film was deposited and was also adequately extended inside the contact holes 67, so that sufficient electric conductivity could be acquired between the printed pads 63 and the upper printed wiring 69. This element substrate, where a 350 x 350 matrix of electron emitters was arranged on a 40 cm square substrate as in Embodiment 1, was positioned in the vacuum container together with the face plate on which were phosphors for R, G, and B. Then, forming processing for the electron emitters was performed. An arbitrary voltage signal of 14 V was applied to the upper printed wiring of this element substrate, a potential of 0 V was applied to the lower printed wiring, and a potential of 7 V was applied to the other wiring. When an anode voltage of 3 kV was applied to the metal back on the face plate, an arbitrary image could be displayed. Crosstalk at the luminance point, which is caused by the shifting of the positions of the electron emitters and the phosphors, did not occur. The wiring resistance of the plated wiring 79 could be reduced to approximately 0.5 Ω between both ends of the substrate, and voltage drops and signal delays could be essentially eliminated. Further, since the electron emitters, which consist of the element electrodes 71 and 73 and the thin film 75 were fabricated after the printed wiring was annealed, the emitters were not subjected to the annealing process. Thus, the emitters were not damaged by heat during the annealing of the printed wiring. In addition, the lower printed wiring 61 and the printed pads 63 are identical layers on the substrate, and the contact to the electrodes 71 and 73 will not be cut off en route because the element electrodes 71 and 73 are formed on the substrate where there is no step on the surface and are connected to the printed wiring 61 and the printed pads 63. (Embodiment 3) Embodiment 3 will now be described while referring to the procedure diagrams (plan views) in Figs. 6A through 6E. An example where nine electron emitters are arranged in a 3 x 3 matrix together with wiring on a soda lime glass substrate (not shown) is employed. In Figs. 6A through 6E, lower printed wiring 81 is formed with a horizontally extended strip shape by annealing a print metal paste. An insulating layer 83 of print glass paste is deposited on almost the entire area and annealed. Contact holes 85 are openings in the insulating layer 83 and are positioned above the lower printed wiring 81. Upper printed wiring 87 is not exposed in the diagram since it is the underlayer for plated wiring 99. The upper printed wiring 87 is formed above the insulating layer 83 in a strip shape that has narrow portions. Narrow printed pads 89 are provided in the same procedure as is the upper printed wiring 87 by annealing print metal paste. The printed pads 89 are electrically connected via the contact holes 85 to the lower printed wiring 81. Element electrodes 91 and 93 which are respectively connected to the upper printed wiring 87 and the printed pads 89. are formed by photolithography and by using a metal thin film. The element electrodes 91 and 93 have electrode intervals of 2 µm with electrode widths of 300 µm at mutually adjacent portions. A thin film 95 includes an electron emission portion, which consists of Pd particles of an electron emitting material, and is located at and between the element electrodes 91 and 93. A thin film portion 97 that is located at each electrode gap serves as an electron emission portion, which will be described later. Plated wiring 99 is metallic wiring that is about 75 microns thick and that is formed by plating over the upper printed wiring 87. A method for manufacturing this element substrate will now be described while referring to Figs. 6A through 6E. Screen printing was performed with Ag paste ink on a soda lime glass substrate that was washed well. By annealing the substrate, the lower printed wiring 81, with a 7 µm thickness and with an 800 µm width, was formed (Fig. 6A). Then, screen printing was performed with glass paste ink, and by annealing the resultant structure, an insulating layer 83 about 20 µm thick, in which were contact holes 85 with 200 µm square openings, was provided over almost the entire surface (Fig. 6B). Further, Ag paste ink was deposited on the insulating layer 83 by screen printing, and the resultant structure was annealed to form the upper wiring 87 900 µm wide and 10 µm thick, whereon depressions of 700 µm were partially provided. During this procedure, the printed pads 89 of 400 µm square were formed at the same time (Fig. 6C). The lower wiring 81 and the printed pads 89 were then electrically connected via the contact holes 85. At this time, step cover for the contact holes 85 is sometimes insufficient when the thickness of the printed pads 87 is 10 µm in contrast to the thickness of 20 µm for the insulating layer 83. In such a case, screen printing for the contact holes 85 was performed with Ag paste ink before the formation of the plated pads 89. Then, when the resultant structure was annealed to provide contact pillars, sufficient step cover for the contact holes 85 could be acquired. A 50 Å (1Å ≡ 0.1 nm) underlayer made of Ti was formed by sputtering, and was overlaid with 1000 Å of Ni. Then, a photoresist pattern was fabricated in the shape of the element electrode by exposing a projection mask aligner, and the element electrodes 91 and 93 were formed by etching. Sequentially, a Cr film was deposited by sputtering on a portion where the thin film 95 is not required, and a Cr pattern was fabricated by photolithographic technology. An organic palladium solution (Catapaste CCP4230, a product name of Okuno Pharmaceutical Co., Ltd.) was deposited and annealed to form a Pd particle film. Further, reverse etching was performed on the Cr pattern and patterning of the thin film 95 was performed at the element electrodes 91 and 93 and at electrode gaps (Fig. 6D). The plated resist was formed by photolithography so as to expose the upper printed wiring 87. The upper printed wiring 87 was rendered conductive and electrolyte plating with Cu was performed on the wiring 87 to provide a plated film of 75 µm. The plating bath employed in this case is the copper sulphate bath shown in Table 3. Copper sulphate (CuSO 4 ) 100 g/ℓ Sulfuric acid (K 4 P 2 O 7 ) 160 g/ℓ Bath temperature 50°C Cathode current density 5 A/dm 2 The element substrate was manufactured by removing the plated resist. As in Embodiment 2, a 350 x 350 matrix of electron emitters was arranged on a 40 cm square substrate that was positioned in a vacuum container together with the face plate on which were phosphors for R, G, and B. When electric driving was performed in the same manner as in Embodiment 2, an image of excellent quality could also be displayed for this embodiment. (Embodiment 4) A substrate shown in Fig. 7 was manufactured in the same manner as in Embodiment 2, except that contact holes were not formed. In Fig. 7, reference number 101 denotes lower printed wiring; 107, upper printed wiring; 103 printed pads that are projecting portions of the upper printed wiring 103, or that are formed separately from the upper printed wiring and that contact the upper printed wiring 107; 105, insulating layers; and 109 plated wiring. The thus fabricated structure could provide the same effect as in Embodiment 2. Especially, fractures did not occur at locations where the element electrodes were connected to rough, uneven portions of the printed wiring and the printed pads. (Embodiment 5) Figs. 8A through 8F are plan views of Embodiment 5 where the fabrication procedures that are employed differ from those in Embodiment 2. In Figs. 8A through 8F, element electrodes 121 and 123 are formed in a first procedure by photolithography and by using a metal thin film. Lower printed wiring 111 and printed pads 113 are formed in a single procedure by annealing print metal paste. In this procedure, the element electrodes 121 and 123 are respectively connected to the lower printed wiring 111 and the printed pads 113. Insulating layers 115 with a strip shape are formed by annealing printed glass paste, and in them are contact holes 115 openings that are positioned in the center of the intersections with the printed pads 113. Upper printed wiring 115 is connected to the printed pads 113 Thin films 125 that consist of Pd particles of an electron emitting material are provided at the element electrodes 121 and 123 and at the electrode gaps. Thin film portions 127 at the electrode gaps serve as electron emission portions. Plated wiring 129 with a strip shape is formed by plating on the upper printed wiring 115. As is described above, according to the fabrication procedures in this embodiment, element electrodes that are part of an active element are formed during the first procedure, and then printed wiring and printed pads are deposited. In this embodiment, the element electrodes, which are formed by photolithography, can be adequately connected electrically to the lower printed wiring and the printed pads, which are formed by a printing process. The thus manufactured substrate can provide the same effects as those provided by Embodiment 2. Especially, the element electrodes can be adequately connected electrically to the printed wiring and the printed pads. Although the fabrication procedures in Embodiment 2 are changed and employed for this embodiment, the fabrication procedures are not thus limited, and in Embodiment 3, the element electrodes 36 and 37 can be fabricated after the upper printed wiring 34 and the printed pads 35 have been formed. Further, in Embodiments 2, 3, and 5, the fabrication of the element electrodes and the thin films 75, 95 or 125, which include electron emission portions, can be performed following the formation of the printed wiring and printed pads. (Embodiment 6) Fig. 11A is a plan view of part of a circuit board that employs a surface conductive emitter that is fabricated in this embodiment. Fig. 11B is a cross sectional view taken along the line XIB-XIB in Fig. 11A, and Fig. 11C is a cross sectional view taken along the line XIC-XIC in Fig. 11A. Figs. 12A through 12F are diagrams for the procedures for fabricating the circuit board. In these diagrams, reference number 1 denotes an insulating substrate; 139 and 141 element electrodes that are formed of a Ni thin film; 137, thin film that includes an electron emission portion of which Pd is a main component; and 135 an electron emission portion. Reference number 143 denotes lower wiring; 145, a connection line; 147, an insulating layer; 149, upper wiring; and 151, plated wiring. The insulating layer 147 is formed so as to be wider at the intersection of the lower wiring 143 and the upper wiring 149 and narrower at the intersection of the connection line 145 and the upper wiring 149. The element electrode is connected to the lower wiring 143, and is electrically insulated from the upper wiring 149 by the insulating layer 147. In this embodiment, a 40 cm square soda lime glass plate was employed as the insulating substrate 1, and a 350 x 350 matrix of the electron emitters was provided at an arrangement pitch of 1 mm (in the diagrams only a 3 x 3 emitter portion is shown). A method for manufacturing the element substrate will now be described while referring to Figs. 12A through 12F. 1) Screen printing with a silver paste was performed on the washed soda lime glass plate 1, and the resultant substrate was annealed to form the lower wiring 143, which is 300 µm wide and 7 µm thick, and the connection line 145 at the same time (Fig. 12A). 2) Screen printing with glass paste was performed on the structure and the substrate was then annealed to form the insulating layer 147. The width of the insulating layer 147 was set to 600 µm at the intersection with the lower wiring 143 and 300 µm at the intersection with the connection line 145. The thickness of the insulating layer 147 was set to 15 µm (Fig. 12B). 3) Screen printing with silver paste was performed on the insulating layer 147. The resultant structure was then annealed to provide the upper wiring 149, which is 200 µm wide and 10 µm thick (Fig. 12C). 4) The substrate 1 was immersed in a Cu plating bath, the upper wiring 149 was rendered conductive, Cu electrolytic plating to a thickness of 100 µm was performed, and the plated wiring 151 was thus formed (Fig. 12D). A resist mask was employed to cover the portion where plating was not required. The plating bath shown in Table 4 was employed. Pyrophosphoric copper (CuP 2 O 7 •3H 2 O) 80 g/ℓ Pyrophosphoric potassium (K 4 P 2 O 7 ) 280 g/ℓ Ammonia solution 2 ml/ℓ Bath temperature 45°C Cathode current density 4 A/dm 2 The plated wiring 151 also extended down the sides of the upper wiring 149 until it reached the connection line 145, and was also deposited on the connection line 145. The lower wiring 143 and the plated wiring 151 were electrically insulated from each other by the insulating layer 147, and no short-circuit occurred between the upper and lower wiring. 5) A 1000 Å (1Å ≡ 0.1 nm) thick Ni thin film was deposited by sputtering while Ti having a thickness of 50 Å was employed as an underlayer. Etching of the Ni and Ti films, by using as a mask a photoresist that was formed in a predetermined shape by photolithography, was performed to provide the element electrodes 139 and 141. The width of the element electrodes 139 and 141 was 300µm and the distance between them was 3 µm. Then, a Cr mask pattern was formed that had an opening in a portion where the thin film 133 for the formation of an electron emission portion was to be deposited. Sputtering was employed to form the Cr film, and etching was used to form the mask pattern. The mask pattern was coated with an organic palladium solution (CCP4230, a product of Okuno Pharmaceutical Co., Ltd.), and was annealed at 300°C for 20 minutes. Then, by removing the Cr film, the thin film 123, which is a particle film that contains Pd as a primary component, was provided for the forming of an electron emission portion (Fig. 12E). 6) Sequentially, a voltage of several V was applied between the element electrodes 139 and 141 power source (not shown) in a vacuum, and a forming process was performed to provide the electron emission portions 135 (Fig.12F) In this embodiment, the forming process was performed after the image display device, which will be described later, was assembled. In the above described manner, a circuit board was fabricated that had multiple electron emitters formed on the insulating substrate 1. An image forming apparatus was manufactured using that circuit board. A method for the manufacture of the image display device will now be described while referring to Fig. 4. The substrate 1 on which the electron emitters 41 were provided was fixed to the rear plate 43. The face plate 53 (where the fluorescent film 49 and the metal back 51 were formed on the internal surface of the glass substrate 47 ) was positioned 5 mm above the substrate 1 by the support frame 45 and was bonded to the support frame 45. The fluorescent film 49 was fabricated with RGB stripes by first forming black stripes and then depositing phosphors for individual colours between the black strips. The metal back 51 is normally provided on the internal surface of the phosphor 49 In this embodiment, after the formation of the phosphor 49, smoothing (commonly called filming) was performed on its internal surface, and the metal back 51 was then fabricated by vacuum evaporation of Al. Since the positions of the individual phosphors and the electron emitters had to correspond, positioning of them was performed carefully. Atmosphere in the glass container thus provided was discharged via a discharge pipe (not shown) by a vacuum pump until a sufficient degree of vacuum was obtained within the container. A voltage was applied to the gap between the element electrodes 139 and 141 of the electron emitters via external terminals, Dox1 through Doxm and Doy1 through Doyn, of the container. A conductance process (forming process) was performed for the thin film 153 to form the electron emission portions 135. To seal the vacuum container, the discharge pipe (not shown) was heated and welded by a gas burner while a vacuum of about 10 -4 Pa (10 -6 torr) was maintained within it. Finally, a getter process was performed to maintain the degree of vacuum after the container was sealed. In this process, immediately before the container was to be sealed a getter that was located at a predetermined position (not shown) in the image forming apparatus was heated by a heating process, such as a high frequency heating process, and an evaporation film was formed. The employed getter contained Ba, etc., as prime components. According to the image display device manufactured by the above described method, the electron emitters emitted electrons upon the application of a voltage of 14 V via the container's external terminals Dox1 through Doxm and Doy1 through Doyn. An electron beam was accelerated by applying a voltage of 3 kV to the metal back 51 via high voltage terminal Hv, so that the phospher 49 was irradiated by that beam and was excited and rendered fluorescent. The image display was thus enabled. The wiring resistance of the plated wiring 151 could be reduced to approximately 0.5 Ω between both ends of the 40 cm square substrate, i.e., 1/10 or less than the resistance of only the upper wiring 149 Therefore, variances in luminance due to voltage drops, and the deterioration of image quality due to drive signal delays could be prevented. (Embodiment 7) Embodiment 7 will now be described while referring to Figs. 13A through 13C and 14A through 14F. Fig. 13A is a plan view of part of a circuit board that employs a surface conductive emitter that is fabricated in this embodiment. Fig. 13B is a cross sectional view taken along the line XIIIB-XIIIB in Fig. 13A, and Fig. 13C is a cross sectional view taken along the line XIIIC-XIIIC in Fig. 13A. Figs. 14A through 14F are diagrams for the methods that are used to fabricate the circuit board. In these diagrams, reference number 1 denotes an insulating substrate; 139 and 141 element electrodes that are formed of a Ni thin film; 137, athin film that includes an electron emission portion of which Pd is a main component; and 135, an electron emission portion. Reference number 143 denotes lower wiring; 145, a connection line; 147, an insulating layer;149, upper wiring; and 151 plated wiring. The insulating layer 147 is formed so as to be wider at the intersection of the lower wiring 143 and the upper wiring 149 and narrower at the intersection of the connection line 145 and the upper wiring 149. The element electrode is connected to the lower wiring 143, and is electrically insulated from the upper wiring 149 by the insulating layer 147. In this embodiment, a 40 cm square soda lime glass plate was employed as the insulating substrate 1, and a 350 x 350 matrix of the electron emitters was provided at an arrangement pitch of 1 mm (in the diagrams only a 3 x 3 emitter portion is shown). A method for manufacturing the element substrate will now be described while referring to Figs. 14A through 14F. 1) Screen printing with silver paste was performed on the washed soda lime glass plate 1, and the resultant substrate was annealed to form the lower wiring 143, which is 300 µm wide and 7 µm thick, and the connection line 145 at the same time (Fig. 14A). 2) Screen printing with glass paste was performed on the structure, and the substrate was then annealed to form the insulating layer 147. The width of the insulating layer 147 was set to 600 µm at the intersection with the lower wiring 143 and 240 µm at the intersection with the connection line 145. The thickness of the insulating layer 147 was set to 20 µm (Fig. 14B). 3) Screen printing with silver paste was performed on the insulating layer 147. The resultant structure was then annealed to provide the upper wiring 149, which is 300 µm wide and 10 µm thick (Fig. 14C). In this embodiment, a part of the upper wiring 149 was formed so as to cover part of the side of the insulating layer 147. However, since the upper wiring 149 was not thick enough relative to the thickness of the insulating layer 147, the coverage was insufficient. 4) A resist mask was arranged on a portion of the substrate 1 where plating was not necessary, and then the substrate 1 was immersed in the Cu plating bath that is shown in Table 1. The upper wiring 149 was rendered conductive and Cu electrolytic plating to a thickness of 80 µm was performed in order to deposit the plated wiring 151 (Fig. 14D). The plated wiring 151 also extended down the sides of the upper wiring 149, which was formed on the insulating layer 147, until it reached the upper wiring 149, which was formed on the connection line 145. The plated wiring 151 was also deposited on the connection line 145 and was connected electrically to the connection line 145 Since the upper wiring 149 was formed on the connection line 145 in this embodiment, electric connection was ensured within a shorter period of time. The lower wiring 143 and the plated wiring 151 were electrically insulated from each other by the insulating layer 147 and no short-circuit occurred between the upper and the lower wiring. 5) A 1000 Å (1Å ≡ 0.1 nm) thick Ni thin film was deposited by sputtering while Ti having a thickness of 50 Å was employed as an underlayer. The element electrodes 139 and 141 were formed in the same manner as in Embodiment 6. The width of the element electrodes 139 and 141 was 200 µm and the distance between them was 3 µm. Then, a Cr mask pattern was formed that had an opening in a portion where the thin film 133 for the formation of an electron emission portion was to be deposited. Sputtering was employed to form the Cr film, and etching was used to form the mask pattern. The mask pattern was coated with an organic palladium solution (CCP4230, a product of Okuno Pharmaceutical Co., Ltd.), and was annealed at 300°C for 20 minutes. Then, by removing the Cr film, the thin film 133, which is a particle film that contains Pd as a primary component, was provided for the forming of an electron emission portion (Fig. 14E). 6) Sequentially, the forming process as in Embodiment 6 was performed and the electron emission portion 135 was formed (Fig. 14F). In the above described manner, a circuit board was fabricated that had multiple electron emitters formed on the insulating substrate 1. When, as well as in Embodiment 6, an image display device was manufactured by using the above circuit board and was driven, an image could be displayed across the entire screen. The wiring resistance of the plated wiring 151 could be reduced to approximately 0.5 Ω between both ends of the 40 cm square substrate, i.e., 1/10 or less than the resistance of only the upper wiring 149. Therefore, variances in luminance due to voltage drops, and the deterioration of image quality due to drive signal delays could be prevented.

Claims: A method of manufacturing an image forming apparatus, which comprises a first substrate (1) whereon are provided a functional element (3, 5, 7, 9, 11, 23; 41; 71, 73, 75, 77; 91, 93, 95, 97; 121, 123, 125, 127; 135, 137, 139, 141) and electric wiring (13, 15; 55, 57; 61, 69, 79; 81, 87, 99; 101, 107, 109; 111, 119, 129; 143, 149, 151) that is connected to said functional element and a second substrate (17, 19, 21; 47, 49, 51, 53) whereon is an area where an image is formed, and wherein with said first substrate and said second substrate being located opposite to each other, space between said first substrate and said second substrate is kept in a pressure-reduced state so as to form an image in said area on said second substrate, comprising the steps of: forming a printed pattern (9, 11; 55, 57; 61, 69; 81, 87; 101, 107; 111, 119; 143, 149) constituting a part of said electrical wiring with a printing process; and forming said electric wiring (13, 15; 55, 57; 61, 69, 79; 81, 87, 99; 101, 107, 109; 111, 119, 129; 143, 149, 151) by employing a plating process to deposit a lamina of a conductive material (13, 15; 79; 99; 109; 129; 151) on said printed pattern. A method according to claim 1 wherein said pressure-reduced state is a degree of vacuum within a range 10 -3 - 10 -6 Pa (10 -5 - 10 -8 Torr). A method for manufacturing according to any one of claims 1 or 2 wherein the thickness of said printed pattern (9, 11; 55, 57; 61, 69; 81, 87; 101, 107; 111, 119; 143, 149) is set within a range from 1 µm to 100 µm. A method according to claim 3, wherein the thickness of said printed pattern (9, 11; 55, 57; 61, 69; 81, 87; 101, 107; 111, 119; 143, 149) is set within a range from 2 µm to 80 µm. A method according to any one of claims 1 to 4, wherein said conductive material (13, 15; 79; 99; 109; 129; 151) has a thickness in a range of 1 µm - 100 µm. A method according to claim 5, wherein said conductive material (13, 15; 79; 99; 109; 129; 151) has a thickness in a range of 10 µm -100 µm. A method according to any one of claims 1 to 6, wherein said functional element (3, 5, 7, 9, 11, 23; 41; 71, 73, 75, 77; 91, 93, 95, 97; 121, 123, 125, 127; 135, 137, 139, 141) comprises an electron emission element (23; 77; 97; 127; 135). A method according to claim 7, wherein said electron emission element (23; 77; 97; 127; 135) is a surface conductive type. A method according to any one of claims 1 to 8, wherein said electric wiring comprises plural upper wiring (79) which with plural lower wiring (61) is arranged to sandwich an insulating layer (65) between said lower (61) and upper (79) wiring, so that said upper wiring (79) is insulated from and crosses said lower wiring (61), and a plurality of said functional elements (71, 73, 75, 77) are connected to said upper (79) and lower (61) wiring. A method according to claim 9, wherein said upper and lower wiring (101, 109) and said insulating layer (105) are produced by steps of: forming said insulating layer (105) on said lower wiring (101) at an intersection between said lower (101) and upper (109) wiring according to a printing method; forming a printed pattern (107) crossing said lower wiring (101) according to the printing method so that said printed pattern (107) extends over said insulating layer (105) and is insulated from said lower wiring (101); and forming said upper wiring (109) on said printed pattern (107) by depositing a lamina of the conductive material according to a plating process. A method according to claim 10, wherein each of said plural functional elements (133, 135, 137, 139, 149) is an electron emission element having two element electrodes (139, 149) arranged opposite to each other, and a thin film (133) containing an electron emission material, one (139) of said two element electrodes is connected to said lower wiring (143), the other (141) of said two element electrodes is connected to a connection line (145) formed discontinuously and parallel to said lower wiring on the first substrate (1), said insulating layer (147) is formed to cross said lower wiring (143) and said connection line (145), said insulating layer (147) has a width greater at the intersection with said lower wiring (143) and smaller at the intersection with said connecting line (145), said printed pattern (149) crosses said lower wiring (143) on said insulating layer (147) and has a width smaller than the width of said insulating layer (147) at the intersection with said lower wiring (143), said conductive material (151) has a width greater than the width of said printed pattern (149), smaller than the width of said insulating layer (147) at the intersection with the lower wiring (143) and greater than the width of said insulating layer (147) at the intersection with said connection line (145), and said upper wiring (151) is electrically connected by said conductive material to said connecting line (145).

Inventors: HASEGAWA MITSUTOSHI, KANEKO TETSUYA, SANDO KAZUHIRO, TAMURA MIKI, YANAGISAWA YOSHIHIRO, HASEGAWA, MITSUTOSHI, KANEKO, TETSUYA, SANDO, KAZUHIRO, TAMURA, MIKI, YANAGISAWA, YOSHIHIRO, HASEGAWA, MITSUTOSHI, C/O CANON K. K., KANEKO, TETSUYA, C/O CANON K. K., SANDO, KAZUHIRO, C/O CANON K. K., TAMURA, MIKI, C/O CANON K. K., YANAGISAWA, YOSHIHIRO, C/O CANON K. K.
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1995
Main classification: H01J31
IPC codes: H01J29, H01J31, H01J9, H01J1