Input/output data ports

Abstract: The present invention disclosed an input/output data port circuit which connects a parallel data bus with an input serial data bus and an output serial data bus. The input/output data port is selectively operable in either a linear mode or a buffered mode. The input/output port is comprised of an interface register that is connected to a parallel data bus, a serial input bus and a serial output bus; a temporary register that is serially connected to the interface register, an outbound register that is connected in parallel to the temporary register and serially connected to a serial bus; and an inbound register that is connected in parallel to the temporary register and serially connected to a serial bus.

Description: This invention relates to circuit architecture for inputting and outputting serial digital data to and from a parallel data bus. More particularly, this invention relates to circuit architecture capable of interfacing a parallel data bus with a serial bus wherein the same bit registers are used to transmit and receive outbound and inbound data. Description of the Prior Art Both serial and parallel interfaces are well known to those of ordinary skill in the art. Serial interfaces involve time-sequential processing of the individual parts as a whole, such as the bits of a character, characters of a word, and so on, using the same circuit facilities for processing the successive parts. Parallel interfaces, on the other hand, involve simultaneous processing of individual parts of a whole, using separate facilities for the various parts. It is often necessary to convert serial data to parallel data and parallel data to serial data so that two apparatus can communicate digitally with one another. Digital Signal Processing (DSP) integrated circuits (ICs), for example, may have an internal parallel bus, but may communicate with other devices or circuitry in a serial data fashion. Therefore, serial to parallel and parallel to serial conversion must be performed so that serial data to and from other devices can be placed on and taken off of the DSP's internal parallel bus. Shift registers are generally used to make these conversions. For example, a 16-bit serial to parallel port and a 16-bit parallel to serial port would consist of two 16-bit registers. One 16-bit register for the serial to parallel path and one 16-bit register for the parallel to serial path. Using two 16-bit registers for two separate circuits consumes both circuit space and power. Consequently, additional control circuitry must control each serial to parallel and parallel to serial data port so that they operate without locking up the data bus. Furthermore, in a normal 8-bit serial to parallel and an 8-bit parallel to serial port having buffered 8-bit registers (two 8-bit registers for each parallel to serial and serial to parallel port), one register is used to latch inbound serial data. After the inbound serial data is received, the data is transferred to a buffer register so, for example, the microcode of the DSP IC could extract the data from the register in a parallel fashion. Double buffering mode allows microcode to access data during a later clock cycle. Similarly, a separate transmit or outbound register is used to shift 8-bit parallel data from a parallel bus. The register would buffer the outbound data from, for example, microcode so that the buffered register could hold and transfer the outbound data to an outbound register, which allows the outbound data to be shifted serially at the next timing frame onto the transmit serial bus. The general 8-bit buffered serial to parallel circuit and parallel to serial circuits require two separate 8-bit registers connected to the parallel bus, one 8-bit register for each circuit. For example, if the parallel bus is internal to a DSP IC and the serial bus is external to the DSP IC, and outbound data is being transferred from the parallel internal bus to the external serial bus and inbound data is being transferred from the external serial bus to the internal parallel bus, two separate data port circuits are required, one circuit for outbound data and a second circuit for inbound data. Each circuit has its own separate register connected to the internal parallel bus. Thus, circuit space and power are required for each of the inbound and outbound data port circuits. Furthermore, if an internal parallel bus received and transmitted both linear data and pulse code modulated (PCM) data wherein the linear data is 16-bit data and the PCM data is 8-bit, according to the above discussion, four separate circuits would be required. One for inbound serial to parallel 16-bit linear data, a second for outbound parallel to serial 16-bit linear data, a third for inbound serial to parallel PCM 8-bit data, and a fourth for outbound parallel to serial PCM 8-bit data. The four separate circuits would each require circuitry space and power if all are placed within an electronic apparatus and, in particular, a DSP IC. Thus, the above discussed normal architectures for inbound and outbound data are disadvantageous because they all require their own circuitry and power, they are not combined into a single circuit capable of handling both inbound and outbound n-bit linear data as well as inbound and outbound m-bit PCM data (where m ≤ n). EP-A-0,311,798 discloses a data input/output circuit capable of operating with different data formats and including a shift register having four reversible stages arranged to form a cyclic register. Audio signal data bits are stored or fetched into the shift register from a parallel data bus and are then fed out in bit-serial fashion through the shift register and selected output gate circuits. TMS320C2x User's Guide, January 1993, Texas Instruments illustrates a serial-to-parallel and parallel-to-serial conversion circuit in which received data is serially shifted into an inbound register and then transferred in parallel to a buffer register when all bits have been received, while data being transmitted is separately transferred from a buffer register to an outbound register connected to a serial output line. According to the present invention there is provided an input/output data port circuit electrically connecting a parallel data bus with an input serial data bus and an output serial data bus, the circuit being selectively operable in a linear mode and a buffer mode, and the circuit comprising: an interface register with parallel bit connections to said parallel data bus, the register comprising at least two flip-flops; whereby, with the circuit operating in the linear mode, serial data shifted serially into the interface register on the input serial data bus is transferred in parallel to the parallel data bus and parallel data transferred from the parallel data bus to the interface register is shifted serially from the interface register to the output serial bus, characterised in that the circuit further comprises a temporary register interposed between the interface register and respective inbound and outbound registers, the temporary register and the inbound and outbound registers each comprising at least two flip-flops , the temporary register having respective serial bit connections to a more significant and a less significant flip-flop of the interface register, and having parallel bit connections to the inbound and outbound registers, respectively, the outbound register having a bit serial connection to the output serial data bus, and the inbound register having a bit serial connection to the input serial data bus whereby, with the circuit operating in the buffer mode, serial data shifted into the inbound register from the input serial data bus is transferred in parallel to the temporary register and serially shifted from the temporary register into the interface register for parallel transfer to the parallel data bus, while data transferred to the interface register from the parallel data bus is serially shifted into the temporary register and transferred in parallel to the outbound register for serial transfer on to the output serial data bus. The serial bit connections of the temporary register are preferably formed with the flip-flops in a portion of the interface register to form a circular register whereby data stored in the temporary register is shifted into the said portion of the interface register during the same clock cycle in which data stored in the said portion of the interface register is shifted into the temporary register. Moreover, the flip-flops of the temporary register preferably comprise master-slave flip-flops whereby transmit data from the interface register is latched into the slave sections of the flip-flops and receive data from the inbound register is latched into the master sections of the flip-flops, or vice versa. The result is a buffered data I/O port capable of simultaneously transmitting and receiving data through the same temporary register so that a minimum number of registers, overall circuitry and power is required. These and other objects and advantages of this invention will become apparent and more readily appreciated from the following description taken in conjunction with the accompanying drawings, wherein by way of example only: FIGURE 1 is a block diagram of an embodiment of the present invention in linear mode; FIGURE 2 is a block diagram of an embodiment of the present invention in buffered mode; FIGURE 3 is a general block diagram of the flip-flop/register arrangement of the present invention; FIGURE 4 is a schematic diagram of a preferred embodiment of a flip-flop; FIGURE 5 is a schematic diagram of a preferred exemplary embodiment of the present invention; FIGURES 6A and 6B are timing diagrams of the present invention in linear mode; and FIGURE 7 is a timing diagram of the present invention in buffered mode. The following detailed description primarily addresses the preferred embodiment in an application to time division multiplexed (TDM) communication systems conforming to the CT2 standard. Generally, the invention, in one embodiment, includes apparatus and methods for sending and receiving X-bit serial data to and from an X-bit parallel bus as well as sending and receiving Y-bit serial data, in a buffered fashion, to and from the X-bit parallel bus, Y being less than or equal to X. The transfer of both X and Y-bit data is performed in the same registers of a single data input/output port circuit. The preferred embodiment of the present invention, an input/output data port, is incorporated into a digital signal processing (DSP) integrated circuit (IC). The input/output port of the present invention allows an internal parallel bus of the DSP IC to process 8-bit data, being for example 8-bit A-law PCM and/or 8-bit u-law PCM data; 4-bit data, being for example 4-bit ADPCM data; and 16-bit data, being for example, 16-bit linear data through the same input/output data port without requiring extensive extra circuitry to accommodate the various data formats. This flexibility allows a DSP IC to interface with many different other DSP processors and ICs. The inventors note that this input/output port is not limited to use within a DSP IC, but can also be used in microprocessors, general I/O circuitry and a wide variety of peripheral IC's and circuits. Furthermore, the inventors recognize that the present invention can interface a parallel bus of X-bits, X being any positive non-zero integer, to various types of serial data buses. The preferred exemplary embodiment of the present invention is part of a multi-coded DSP which is implemented as an integrated circuit (IC). The multi-coded DSP can include A-law, u-law, PCM, and linear encoded data which are transmitted and received by the DSP through a data port representative of the present invention input/output data port. Referring to FIGS. 1, 2 and 3 the input/output data port (I/O data port) 10 of the preferred exemplary embodiment comprises a 16-bit interface register 12, and three 8-bit registers which include a temporary register 14, an inbound register 16 and an outbound register 18. There are two preferred modes of operation; the 16-bit linear mode and the 8-bit buffered mode. Referring first to the 16-bit linear mode, depicted in FIG 1, serial data can be shifted serially into the 16-bit interface register via a serial-in-bus 22. The serial data is inbound to the I/O data port 10 and considered to be "receive data" with respect to a parallel bus 20. Also, parallel data can be shifted in a parallel fashion from the parallel data bus 20 to the interface register 12 and then shifted serially out the serial-out-bus 24. Here, the parallel data is considered outbound to the serial out bus 24 and "transmit data" to the parallel data bus 20. Both transmit data and receive data propagate through interface register 12. Referring now to the 8-bit buffer mode depicted in FIG 2, the 16-bit interface register 12 can be converted via a program, software, firmware, hardware, a flip-flop transfer gate, a mux control, etc., explained in more detail below, into a 8-bit interface register 13 that performs parallel to serial and serial to parallel transfers. It is understood that the interface register can be converted into an interface register having less than or equal to the number of flip-flops in the interface register 12. Sixteen flip-flops are being used in the preferred embodiment for interface register 12. The temporary register 14, inbound register 16 and outbound register 18 are all 8-bit registers in this embodiment and are only used in the 8-bit buffer mode. The inbound register 16 converts receive data inbound from a serial-in-bus 23 from serial to parallel. The received data is shifted in a parallel fashion to the temporary register 14. The received data is then serially shifted to the 8-bit interface register 13, and then is parallel shifted to the parallel data bus 20. At the same time inbound receive data is being shifted from the serial-in-bus 23 to the parallel data bus 20, outbound, transmit data is being shifted from the parallel data bus 20 to the 8-bit interface register 13, and then serially shifted to the temporary register 14. From the temporary register 14, the transmit data is sent parallel to the outbound register 18 where it is serially shifted onto the serial-out-bus 25. In FIGURE 3 a block diagram of the flip-flop/register arrangement of the I/O data port 10 is shown. Both the linear mode and buffer mode of operation are explained in more detail with respect to FIGURE 3 below. In linear mode, transmit data, outbound from the parallel data bus, is shifted from the parallel data bus 20 into the interface register 12 and held in the master portion of each of the register's master/slave flip-flops 28 for bits 0 to 15. The transmit data is shifted to the serial-out-bus 24 during a time slot strobe (FIGS 6A and 6B). During the time slot, receive data is serially shifted from serial bus 22, most significant bit first, and into the master/slave flip-flops 28. It is understood that the data can also be shifted least significant bit first. After the time slot strobe, the receive data is held in the slave portion of each of the register's master/slave flip-flops 28 for bits 0-15. In this preferred embodiment there are 16 master/slave flip-flops 28 in the interface register 12. The receive data is shifted from the bit-0 register to the bit-15 register and then shifted in a parallel fashion to the parallel bus 20. FIGS 6A and 6B, are timing diagrams for the linear mode. As shown in FIGS 6A and 6B, both transmit and receive functions are triggered by the leading edge of the strobe signal TS0 or TS2. TS0 and TS2 can occur in the same frame to use the present invention as an echo port I/O. Furthermore, as also shown in FIG 3, both transmit data and receive data propagate through the same flip-flops 28 in the interface register 12. The preferred embodiment input/output data port 10 requires only one 16-bit register to transmit 16-bit data from the parallel data bus 20 and receive 16-bit data from the serial-in-bus 22. Furthermore, the input/output data port transfers transmit and receive data simultaneously through the same flip-flops 28. Thus, the present invention uses less logic circuitry and power than previous circuits and can move data continuously without having to wait for the port to change from an input port to an output port. The present invention I/O data port 10 operates as both an input and output port simultaneously. The inventors note that linear mode can accommodate linear sign extended data which carries a sign bit. The interface data register of the preferred embodiment is configured to accommodate the sign bit by duplicating the sign bit (shown at bit-15). FIGURES 3 and 7 illustrate the buffer mode of operation of the I/O data port 10. A frame is a single 8 Khz clock period. Inside a frame 8-bits of serial data are shifted into inbound register 16 during a data receive time slot (RE). Inbound, receive data can be shifted into inbound register 16 at various frequencies. The preferred embodiment inbound, receive data frequencies include 64, 128, 256, 512, 1024 and 2048 KHz. It is understood that the frequency can be a frequency above 64 KHz. At the end of the frame, the receive data is latched in parallel to the master portion of the temporary register flip-flops 29 (bits 7-14). A circular shift occurs causing receive data to be shifted from the temporary register 14 to the interface register 12. Once the inbound, receive data is in the interface register 12, the parallel data bus 20 has access to the receive data. In the preferred embodiment the microcode, associated with the DSP IC uses the received data placed on parallel data bus 20. Transmit data is placed on the parallel data bus 20 near the end of the frame. The DSP microcode directs the interface register 12 to latch the transmit data into its flip-flops 28. A circular shift takes place which serially shifts the transmit data to the slave portion of temporary register 14. At the end of the frame, when inbound, receive data is latched into the temporary register 14, the transmit data is also latched in parallel fashion to the outbound register 18 from the temporary register 14. The transmit data is then serially transmitted out the serial-out-bus 25 by the outbound register 18 during a transmit time slot (TE). RE and TE are independent time slots although each occurs in a frame and are, preferably, active for 8 clock (CLK) cycles. Preferably, TE and RE are synchronized to an 8 KHz time frame and do not span the rising edge of an 8 KHz sync pulse. Both the receive data and transmit data are buffered by the temporary register 14. Furthermore, both transmit and receive data are processed simultaneously by the circular shifter 30 which comprises the 8-bit portion of the interface register 13 and the temporary register 14. Between the flip-flops 28 in the interface register 12 and temporary register 14 is a switching mechanism or mux 32 that is set by control logic 40 so that the I/O data port can be placed in either linear or buffer mode. That is, the mux 32 will switch so that the interface register 12 will work alone or will cooperate with the temporary register 14 in order to form a circular shifter. Inbound, receive data, and outbound, transmit data are thus transferred simultaneously by the same registers in a single frame. It is preferred that there are two circular shifts within a frame so that inbound and outbound data will not be delayed. Transfer gates 34 are located between each flip-flop of interface register 12 and the parallel data bus 20. When a transfer gate 34 is turned "on" data can be latched from the associated interface register flip-flop 28 to the parallel data bus 20. In other words, the transfer gates 34 allow the latched data from the interface register 12 to be driven onto the parallel data bus 20, as described above. It is understood that the parallel data bus may be wider (have more parallel bits) than the number of interface register flip-flops being used when the I/O data port is in buffer mode. The preferred embodiment latches to only eight of the 16 available parallel data bus lines. It is further understood that more or less than eight interface register flip-flops can be used. FIGURE 3 also depicts a mux or switching device 33 (serial mux) for configuring the linear mode serial-out-bus 24 and the buffer mode serial-out-bus 25 to output to general serial-out-bus 27. The buffer mode reuses the interface register hardware (of the linear mode) thereby eliminating the necessity of extra hardware. Circuitry costs are lowered, less IC real estate is needed and power consumption of the overall IC or circuit is lowered. Conversion of the 16-bit interface register 12 to an 8-bit interface register requires at least one mux 32 and the space to route signal lines (serial in, serial out, and two control signal for switching the mux). FIGURE 4 depicts a master/slave flip-flop circuit used in the preferred embodiment. The master latch 36 portion and slave latch 38 portion of the flip-flop 28 are indicated. FIGURE 5 depicts a schematic for the preferred exemplary I/O data port control logic 40 which operates in conjunction with microcode to operate the interface register 12, temporary register 14, inbound register 16, outbound register 14 and all the mux 32 and transfer gates 34. The parallel data bus 20 is connected via the transfer gates 34 and the mux 32 to the interface register flip-flops 28. Between the interface register flip-flops are mux switches 32. Similar components are used in the temporary register 14, inbound register 16 and outbound register 18. One possible application of the present invention is an integrated circuit for use in a cordless telephone handset and/or base unit, for example, the integrated circuit disclosed in our copending applications 0,581,480, 0,580,338, 0,580,337, 0,581,479, 0,580,341, 0,580,339, 0.580,347, 0,581,478, 0,580,340, 0,582,392, 0.582,391 and 0,581,477. If the present invention is so applied to the integrated circuit disclosed in those applications, the integrated circuit can be synchronized to an external 500 Hz signal (slave) or to an internally generated 500 Hz signal (master, default), to meet the requirements of CT2 Annex N for CFP's. The present invention offers lower power requirements and reduced IC real estate requirements over prior art I/O data ports because of the need for less circuitry. Furthermore, the present invention accomplishes simultaneous data receive and transmit to and from a parallel data bus of, for example a DSP. The present invention performs both linear mode input/output and buffered mode input/output functions which allow a parallel data bus to be connected to a variety of peripheral devices via the same data I/O port. Furthermore, the present invention transmits and receives data in either linear or buffered mode through the same registers, thereby decreasing overall circuit size.

Claims: An input/output data port circuit electrically connecting a parallel data bus (20) with an input serial data bus (22/23) and an output serial data bus (24\25), the circuit being selectively operable in a linear mode and a buffer mode, and the circuit comprising: an interface register (12) with parallel bit connections to said parallel data bus, the register comprising at least two flip-flops (28); whereby, with the circuit operating in the linear mode, serial data shifted serially into the interface register on the input serial data bus is transferred in parallel to the parallel data bus and parallel data transferred from the parallel data bus to the interface register is shifted serially from the interface register to the output serial bus, characterised in that the circuit further comprises a temporary register (14) interposed between the interface register and respective inbound (16) and outbound (18) registers, the temporary register and the inbound and outbound registers each comprising at least two flip-flops , the temporary register having respective serial bit connections to a more significant and a less significant flip-flop (28) of the interface register, and having parallel bit connections to the inbound and outbound registers, respectively, the outbound register having a bit serial connection to the output serial data bus, and the inbound register having a bit serial connection to the input serial data bus whereby, with the circuit operating in the buffer mode, serial data shifted into the inbound register from the input serial data bus is transferred in parallel to the temporary register and serially shifted from the temporary register into the interface register for parallel transfer to the parallel data bus, while data transferred to the interface register from the parallel data bus is serially shifted into the temporary register and transferred in parallel to the outbound register for serial transfer on to the output serial data bus. An input/output port according to claim 1 wherein the serial bit connections of the temporary register are formed with the flip-flops in a portion of the interface register to form a circular register whereby data stored in the temporary register is shifted into the said portion of the interface register during the same clock cycle in which data stored in the said portion of the interface register is shifted into the temporary register. An input/output port according to claim 2 wherein the flip-flops of the temporary register comprise master-slave flip-flops (29) whereby transmit data from the interface register is latched into the slave sections of the flip-flops and receive data from the inbound register is latched into the master sections of the flip-flops, or vice-versa. An input/output data port according to any one of the claims 1-3 wherein each of the flip-flops of the interface register has an input connected to an associated multiplexer (32) for selectively switching the flip-flop to receive a first input from another flip-flop or a second input from the parallel data bus. An input/output data port according to any one of the claims 1-4 wherein the output of each of the flip-flops of the interface register is connected to an associated transfer gate (34) for latching data from the flip-flop to the parallel data bus. An input/output data port according to any one of the claims 1-5 wherein each of the flip-flops of the temporary register has an input connected to an associated multiplexer (32) for selectively switching the flip-flop to receive either a first input from the output of another flip-flop in the temporary register or a second input from the output of an associated flip-flop in the inbound register. An input/output data port according to any one of the claims 1-6 wherein each of the registers in the outbound register has an input connected to a multiplexer (32) for selectively switching the flip-flop to receive either a first input from another flip-flop in the outbound register or a second input from the output of an associated flip-flop in the temporary register. An input/output data port according to any one of the preceding claims wherein the input/output data port is an integral part of a digital signal processing integrated circuit and the parallel data bus is an internal data bus in the integrated circuit. A method for transferring a first data from a parallel bus (20) to a first serial bus (25), while transferring a second data from a second serial bus (22/23) to the parallel bus, the method comprising the steps of: (a) latching the first data from the parallel bus to an interface register (12); (b) shifting the second data from the second serial bus to an inbound register (16); (c) latching the second data from the inbound register to the master sections of master-slave flip-flops (29) forming a temporary register (14), the temporary register having respective serial bit connections to a more significant and a less significant flip-flop of the interface register; (d) circularly shifting the first data from the interface register to the slave sections of the master-slave flip-flops of the temporary register; (e) latching the first data from the said slave sections to an outbound register (18); (f) circularly shifting the second data from the said master sections to the interface register; (g) latching the second data from the interface register to the parallel bus; and (h) shifting the first data from the outbound register to the first serial bus.

Inventors: BARTKOWIAK JOHN, HENDRICKSON ALAN F, MULLINS JACQUELINE, PETERSON JOSEPH W, BARTKOWIAK, JOHN, HENDRICKSON, ALAN F., MULLINS, JACQUELINE, PETERSON, JOSEPH W.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES INC.
Application year: 1995
Main classification: H03M9
IPC codes: H03M9, G06F13, G06F5