THIN FILM TRANSISTOR FOR LIQUID CRYSTAL DISPLAY AND METHOD FOR FABRICATING THE SAME

Abstract: A TFT for LCD and a method fabricating the same, characterized by the formation of resistors at the conjunction between each of the outermost branches of a multiple gate electrode made of polysilicon and the gate line, the branches being adjacent to a source electrode and a drain electrode respectively. By virtue of the resistors, the voltage between the branches and the gate line can be lowered. The resistors are the polysilicon itselft or are implanted by impurities at a low concentration. The gate voltage is significantly reduced by the resistors such that the leak current attributable to the voltage applied to the source/drain electrodes can be significantly reduced, thereby improving the reliability of device.

Description: THIN FILM TRANSISTOR FOR LIQUID CRYSTAL DISPLAY AND METHOD FOR FABRICATING THE SAME Technical Field The present invention relates to a thin film transistor (hereinafter referred to as "TFT") for liquid crystal display (hereinafter referred to as "LCD") and a method for fabricating the same. More particularly, the present invention is concerned with the lowering of gate voltage through resistors formed at the conjunction between the outermost branches of a multiple gate electrode and the gate line, thereby reducing the leak current and improving the reliability in device operation. Background Art An LCD, which is a kind of flat panel display, is operated by changing the optical anisotropy of the liquid crystal with the application of an elect-rical field, the liquid crystal having the fluidity of a liquid and the optical properties of a crystal. LCDs consume lower power and have smaller volume than cathode ray tubes. In addition, LCDs can constitute a very large and highly defined screen, which is virtually impossible for cathode ray tubes to accomplish. By virtue of such advantages, LCDs substitute for cathode ray tubes and are increasingly employed in many fields. An LCD comprises liquid crystal sandwiched between a lower liquid crystal plate which is connected with a switching device and has a pixel electrode and an upper liquid crystal plate which has a common electrode. Generally, an LCD is prepared as follows. First, a transparent electrode pattern and a pixel electrode made of indium tin oxide (hereinafter referred to as "ITO") is formed on a transparent substrate, for example, quartz. Then, a passivation film is formed to prevent the short circuit of the transparent electrode pattern, followed by the formation of an alignment film to align the liquid crystal. Thereafter, valleys with an orientation are formed on the alignment film, which is accomplished by rubbing the film with a rubbing roll in which cloth is wound around a cylindrical core. As a result, a lower liquid crystal substrate is obtained. An upper liquid crystal substrate having a common electrode is made. Thereafter , ' the upper liquid crystal substrate and the lower liquid crystal substrate are sealed by forming spacers and seal patterns to provide a certain cell gap therebetween. LCD is completed by injecting liquid crystal into the cell gap and sealing it. Such LCD is typically subgrouped into twisted nematic (TN) , super twisted nematic (STN) , ferroelectric, and TFT LCD, according to the kind and operating manner of the liquid crystal employed. TFT LCD, which employs TFT as a switching device for the operation of pixel, responds more quickly and has wider viewing angle than do other LCDs. In addition, since TFT LCDs can produce a large, highly defined picture, they are extensively used in portable televisions, laptop personal computers and the like. There are two TFT structures that are different in the position of an active layer, a semiconductor layer pattern: Staggered type in which a gate electrode and a source/drain electrode are divided by the semiconductor layer; and Coplanar type in which a gate electrode and a source/drain electrode both are formed at one side of the semiconductor layer . A significant problem of such TFT LCD is that the aperture ratio is low because on the partial area of a pixel a TFT device is formed and gate bus and data bus lines are arranged to operate the device. In order to better understand the background of the invention, a conventional TFT for LCD will be described in conjunction with Fig. l, which is a layout showing a top gate-type TFT in which a gate electrode is formed in the upper side of the channel of a semiconductor layer. As shown in Fig. 1, the top gate-type TFT has a substrate l, made of a transparent material, i.e, quartz, in which a rectangular semiconductor layer pattern 2 of amorphous or polycrystalline silicon is formed as a channel. Over the entire surface of the resulting structure, a gate insulating film, e.g, an oxide film (not shown) is formed. A triple gate electrode 3 is formed on an area of the gate insulating film over the predetermined part of the semiconductor layer pattern 2 to be the channel. The triple gate electrode 3 is made of a polysilicon layer containing a high concentration of impurities. One end of the gate electrode is connected with a gate line 10, which extends in the horizontal direction to the transparent substrate 1. A high concentration N * impurity layer 4 is formed in some areas of the semiconductor layer pattern 2 which are nonoverlapped with the triple gate electrode 3. Following this, a blanket field oxide film (not shown) is formed over the resulting structure. Contact holes 7 are formed to expose the high concentration N * impurity layer 4 partially. Then, a source electrode 5 and a drain electrode 6 are formed to come into contact with the high concentration impurity layer 4 through the contact holes 7. The source electrode 5 and the drain electrode 6 are connected with a data line extending in the vertical direction and a transparent pixel electrode 12, respectively. The described conventional TFT for LCD having such multiple gate electrode is a structure which is capable of scattering the electric field applied to the gate electrode, so as to prevent the increase of leak current caused by grain boundary, a significant disadvantage of polysilicon gate. In spite of this, a leak current occurs in such conventional structure employing the triple gate electrode, degrading the reliability in device, which is attributed to the fact that the two outermost parts of the multiple gate electrode are applied with a large electric field owing to the voltage applied to the source/drain electrode and the gate voltage. Disclosure of Invention Accordingly, it is a principal object of the present invention to provide a TFT for LCD which has a resistance at the conjunction between each of the outermost branches of multiple gate electrode and the gate line, thereby reducing the leak current owing to the voltage applied to the gate electrode and improving the reliability in device operation. It is another object of the present invention to provide a method for fabricating such TFT for LCD. In accordance with an aspect of the present invention, there is provided a TFT for LCD, comprising: a semiconductor layer pattern formed on a transparent substrate,- a blanket gate insulating film formed over the entire surface of the resulting structure; a multiple gate electrode formed on the gate insulating film over the part predetermined as channel of the semiconductor pattern, whose one end contacts with a gate line; resistors formed between each of the outermost branches of the multiple gate electrode and the gate line; high concentration impurity layers formed in the semiconductor layer pattern, which are nonoverlapped with and present outside the multiple gate electrode; a source electrode whose one end is in contact with one of the high concentration impurity layers while the other end is connected with a data line; and a drain electrode whose one end is in contact with the other high concentration impurity layer while the other end is connected with a pixel electrode. In accordance with another aspect of the present invention, there is provided a method for fabricating a TFT for LCD, comprising the steps of: forming a semiconductor layer pattern on a transparent substrate; depositing a blanket gate insulating layer over the resulting structure,* forming a multiple gate electrode extending across the upper part of the semiconductor layer pattern; forming high concentration impurity layers in some areas of the semiconductor layer pattern which are nonoverlapped with the outermost branches of the multiple gate electrode; implanting impurities into the multiple gate electrode lest any impurity is present between each of the outermost branches of the multiple gate electrode and a gate line, so as to form a resistor therebetween; forming a blanket field oxide film on the resulting structure; partially exposing the high concentration impurity layers; and forming a source electrode and a drain electrode in contact with the exposed high concentration impurity layers. Brief Description of Drawings The above objects and other advantages of the present invention will become more apparent by describing in detail the preferred embodiments of the present invention with reference to the attached drawings in which: Fig. l is a layout illustrating a TFT for LCD, according to a conventional technique; and Fig. 2 is a layout illustrating a TFT for LCD, according to the present invention. Best Mode for Carrying Out the Invention Referring to Fig. 2, there is a layout showing a TFT for LCD, according to the present invention. The structure and the fabricating method of the TFT of the present invention will be, in detail, described in conjunction with Fig. 2. First, a rectangular semiconductor layer pattern with a predetermined width, which is made of amorphous or polycrystalline silicon, is formed on a substrate made of a transparent material, for example, quartz or glass, followed by the formation of a blanket gate insulating film (not shown), i.e. an oxide film, over the resulting structure. Next, a triple gate electrode 3 is formed on a part of the gate insulating film which is overlapped with the central part of the semiconductor layer pattern 2. The gate electrode 3 is intrinsic or contains impurities at a low concentration and brings its one end into contact with a gate line 10 which extends in the vertical direction. Then, N or P type ions are implanted into areas of the semiconductor layer pattern 2 which are nonoverlapped with the triple gate electrode 3, so as to form a high concentration impurity layer 4, while they are not allowed to be implanted into the gate electrode 3. Following this, photosensitive film patterns (not shown) are formed between each of the two outermost branches of the triple gate electrode 3 and the gate line 10. N or P type impurities are implanted at a high concentration into the gate electrode 3 and the gate line 10, with the aim of reducing resistance, while the photosensitive film patterns serve as a mask. Removal of the photosensitive film patterns results in resistors 8, which are intrinsic or contain impurities at a low concentration. Subsequently, a blanket field oxide film (not shown) is formed over the resulting structure. Contact holes 7 which partially expose the high concentration N + impurity layer are formed by removing the predetermined parts of the field oxide film and the gate oxide film in sequence. Then, a source electrode 5 and a drain electrode 6 are formed in such a way to come into contact with the high concentration impurity layer 4 through the contact holes 7. While the source electrode 5 is connected with a data line 11 which extends in the vertical direction, the drain electrode 6 is connected with a pixel electrode such as ITO. In the above-described TFT for LCD, the gate voltage can be lowered at the outermost branches of the triple gate electrode 3 by the resistors 8, which allows the electric field to be changed smoothly and thus, results in the reduction of leak current. Although a triple gate electrode is described in this specification, the effect of reduction in leak current could be obtained in any TFT having more multiple gate electrodes provided such that resistors are employed only at the two outermost branches of the multiple gate electrode, in accordance with the present invention. As described hereinbefore, since the gate voltage is lowered by the resistors in the TFT structure of the present invention, the leak current attributable to the voltage applied by the source/drain electrodes can be reduced, which brings about an effect that the reliability in device operation is significantly improved. Other features, advantages and the embodiment of the invention disclosed herein will be readily apparent to those exercising ordinary skill after reading the foregoing disclosures. In this regard, while a specific embodiment of the invention has been described in considerable detail, variations and modifications of this embodiment can be effected without departing from the spirit and scope of the invention as described and claimed.

Claims: Claims : 1. A thin film transistor for liquid crystal display, comprising: a semiconductor layer pattern formed on a transparent substrate; a blanket gate insulating film formed over the entire surface of the resulting structure; a multiple gate electrode formed on the gate insulating film over the part predetermined as channel of the semiconductor pattern, whose one end contacts with a gate line; resistors formed between each of the outermost branches of the multiple gate electrode and the gate line; high concentration impurity layers formed in the semiconductor layer pattern, which are nonoverlapped with and present outside the multiple gate electrode; a source electrode whose one end is in contact with one of the high concentration impurity layers while the other end is connected with a data line; and a drain electrode whose one end is in contact with the other high concentration impurity layer while the other end is connected with a pixel electrode. 2. A thin film transistor in accordance with claim 1, wherein said transparent substrate is comprised of quartz or glass. 3. A thin film transistor in accordance with claim 1, wherein said semiconductor layer pattern is comprised of polysilicon. 4. A thin film transistor in accordance with claim l, wherein said gate electrode is comprised of polysilicon which is intrinsic or has impurities at a low concentration. 5. A thin film transistor in accordance with claim 1, wherein said source electrode and said drain electrode are comprised respectively of any one selected from the group consisting of titanium, chrome and aluminum. 6. A thin film transistor in accordance with claim 1, wherein said gate insulating film is comprised of an oxide. 7. A thin film transistor in accordance with claim 1, wherein said high concentration impurity layers are of N or P type. 8. A method for fabricating a thin film transistor for liquid crystal display, comprising the steps of: forming a semiconductor layer pattern on a transparent substrate; depositing a blanket gate insulating layer over the resulting structure; forming a multiple gate electrode extending across the upper part of the semiconductor layer pattern; forming high concentration impurity layers in some areas of the semiconductor layer pattern which are nonoverlapped with the outermost branches of the multiple gate electrode; implanting impurities into the multiple gate electrode lest any impurity is present between each of the outermost branches of the multiple gate electrode and a gate line, so as to form a resistor therebetween; forming a blanket field oxide film on the resulting structure; partially exposing the high concentration impurity layers; and forming a source electrode and a drain electrode in contact with the exposed high concentration impurity layers.

Inventors: HWANG SEONG YEON, KIM TAE GON, NAM DONG HYUN, SEO YOUNG WOO, YEOM SEON MIN, HWANG, SEONG, YEON, KIM, TAE, GON, NAM, DONG, HYUN, SEO, YOUNG, WOO, YEOM, SEON, MIN
Applicants: HWANG SEONG YEON, KIM TAE GON, NAM DONG HYUN, ORION ELECTRIC CO LTD, SEO YOUNG WOO, YEOM SEON MIN, HWANG, SEONG, YEON, KIM, TAE, GON, NAM, DONG, HYUN, ORION ELECTRIC CO. LTD., SEO, YOUNG, WOO, YEOM, SEON, MIN
Application year: 1995
Main classification: H01L29
IPC codes: G02F1, H01L27, H01L29