Insulated gate semiconductor device and method of manufacturing the same

Abstract: An insulated gate semiconductor device comprises a semiconductor substrate (41, 42) and a first semiconductor layer (43) disposed on the surface of the semiconductor substrate (41, 42). At least two normal trenches (45) are provided in the first semiconductor layer (43) in a vertical direction to the surface of the first semiconductor layer (43) and reach into the semiconductor substrate (42). Between the at least two normal trenches (45) a dummy trench (55) is arranged. Therefore, it is possible to provide an insulated gate semiconductor device of high breakdown voltage and low On-resistance.

Description: The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to a device structure to prevent a reduction in breakdown voltage of a power semiconductor device which has a trench MOS gate where a channel is formed in a surface of a trench buried in a semiconductor substrate and a method of manufacturing the device. Fig. 30 is a cross-sectional view of an insulated gate semiconductor device in a background art. Referring to this figure, now a vertical MOS (metal oxide semiconductor) transistor (hereinafter referred to as "UMOS") of trench-gate structure will be discussed as an example. This UMOS is used for low breakdown voltage of 200 V or below, for example, used for an electrical equipment system of automobile. Fig. 30 shows an N + substrate 1, an N - layer 2, a P base layer 3, an N + source region 4, a trench 5, a gate insulating film 6, a gate 7, an interlayer insulating film 8, a source electrode 9, a drain electrode 10 and a channel region 11. Reference character L represents a spacing between the adjacent trenches. Next, an operation of the UMOS will be discussed. When a prescribed drain voltage V DS is applied across the source electrode 9 and the drain electrode 10 and a prescribed gate voltage V GS is applied across the source electrode 9 and the gate 7, the channel region 11 of the P base layer 3 in the vicinity of the gate insulating film 6 is inverted to N type, thus forming a path for electric charges, i.e., a channel. The channel produces continuity between the source and drain, and the resistance of the UMOS produced at this time is called an ON-resistance. In an On state, that is, a state where there is continuity between the source and drain, if the gate voltage V GS applied across the source electrode 9 and the gate 7 is changed to 0 V or a negative voltage, i.e., reverse bias, the gate is turned off and the channel region 11 of N type is inverted again to P type, entering an OFF state where there is no continuity between the source and drain. Thus, the control over the gate voltage V GS makes it possible to control a current flow between the source and drain, and therefore the UMOS can be used as a power switching device. The drain voltage V DS applied to the UMOS when the gate is in the OFF state is referred to as a breakdown voltage of a device. The breakdown voltage of a device is generally determined by an impurity concentration and thickness of the N - layer 2 and in the case of the UMOS, further depends on a structure of a surface region of the device. Especially in the UMOS of trench structure, since the trench 5 protrudes into the N - layer 2 through the P base layer 3, the breakdown voltage of the device is dependent on the condition of a tip portion of the trench 5 protruding into the N - layer 2. Fig. 31 is a simulation graph showing an electric field of the UMOS of trench structure. In the simulation, it is assumed that the impurity concentration of the N - layer 2 is 1 Ωcm and the thickness from a surface of the P base layer 3 to a bottom surface of the N - layer 2 is 8.5 µm. The upper-left rectangular portion of Fig. 31 represents a portion of trench structure. As can be seen form Fig. 31, when the drain voltage V DS is applied to the UMOS, a depletion region extends from the P base layer 3 to the N - layer 2, but the equipotential lines form loops to be discontinuous at the portion where the trench 5 protrudes into the N - layer 2, indicating that the electric field becomes stronger at the tip end portion of the trench 5. The breakdown voltage of the device depends on the electric field strength at the tip end portion. The breakdown voltage of the device, which is dependent on a condition of the tip end portion of the trench 5, undergoes a more strict situation when the gate voltage V GS is changed into the reverse bias. Specifically, the sum of the drain voltage V DS applied to the UMOS and the reverse-biased gate voltage V GS is applied to the tip portion of the trench 5 protruding into the N - layer 2. Accordingly, the breakdown voltage of the device when the gate voltage V GS is reversely biased is lower by a reverse-bias of the gate voltage V GS as compared with the case where the gate voltage V GS is 0 V. As a countermeasure for reduction in breakdown voltage of the UMOS having trench structure, for example, a proposed device structure is disclosed in USP 5,072,266. Fig. 32 is a cross-sectional perspective view of the device disclosed in USP 5,072,266. The device has a structure in which a central portion of the P base layer 3 extends deeper than the trench 5 does as shown in Fig. 32. Other structure of the device is the same as that of the background-art UMOS of Fig. 30. When the drain voltage V DS is applied to the UMOS of Fig. 32, the depletion region extends from the P base layer 3 to the N - layer 2 in the same manner as the UMOS of Fig. 30. In the UMOS of Fig. 32, however, since the central portion of the P base layer 3 extends deeper than the trench 5, the equipotential lines form fewer loops at the tip end portion of the trench 5 and a gradual change of the equipotential lines can be found, from those which extend to an adjacent trench to those which enclose the trench 5. Accordingly, the discontinuity of the depletion region at the tip end portion of the trench 5 is relieved and the reduction in breakdown voltage of the device at the tip end portion of the trench 5 can be suppressed. Furthermore, since the distance from the central portion of the P base layer 3 to the N + substrate 1 is shorter than that from the tip end portion of the trench 5 to the N + substrate 1, a breakdown occurs at the central portion of the P base layer 3 and the breakdown voltage is dependent on the central portion of the P base layer 3. Accordingly, even if the gate voltage V GS is reversely biased, it is possible to keep the breakdown voltage of the device from becoming lower by the reverse bias of the gate voltage V GS . To ensure the required breakdown voltage of the device, however, in the device structure of the UMOS as shown in Fig. 32, the distance from the central portion of the P base layer 3 to the N + substrate 1 should be long, that is, the N - layer 2 should be thick, since the central portion of the P base layer 3 extends deeper than the trench 5. In the case of the UMOS having a trench structure, a current path is found from the tip end portion of the trench 5 through the channel region 11 to the drain electrode in the ON state, and therefore the N + layer 2 of greater thickness causes a higher On-resistance. In the device structure of the UMOS as shown in Fig. 32, the trench 5 extends deeper than the P base layer 3 at a portion where the trench 5 and the P base layer 3 come into contact although the central portion of the P base layer 3 extends deeper than the trench 5. In order to form the P base layer 3, which is generally obtained by diffusion, the distance between the adjacent trenches 5 requires, at least, the sum of the length of an opening from which the impurity is implanted and twice the depth of the central portion of the P base layer 3, because the impurity is diffused over the same range in vertical and horizontal directions. An evaluation of the spacing between the adjacent trenches on the basis of a commonly-used device size, assuming that the length of the opening at the central portion of the P base layer 3 is 2 µm, the depth of the trench is 2 µm and the depth of the central portion of the P base layer 3 is 3 µm, determines the spacing L between the trenches to be about 8 µm. As the spacing L between the trenches becomes larger than 8 µm, the ON-resistance of the UMOS becomes higher. A test reveals that the ON-resistance becomes higher by about 0.18 Ωcm 2 as a cell pitch (the spacing between the central portions of the adjacent trenches) becomes wider by 1 µm. Document WO 92/14269 A discloses a power MOSFET, which is a conventional insulated gate semiconductor device constructed in a trench configuration comprising a N-type semiconductor substrate, and a P body region, equivalent to a first semiconductor layer, formed thereon. A gate electrode is buried inside a trench formed in said body region with an insulating layer disposed therebetween, the trench reaching to the substrate in a vertical direction. An N + region, equivalent to a second semiconductor layer, is disposed in a portion of the surface of the P body region next to the insulating layer of the trench. A first electrode is formed on the surface of the body region and parts of the second semiconductor layer, while a second main electrode is provided on the lower surface of the substrate. In order to protect the transistor against voltage breakdown a shield region is formed below the bottom side of the trench and the insulating layer, respectively, the shield region being either more lightly doped than, or having a conductivity opposite to, the substrate in which it is formed. Document EP-A 0 583 022 discloses a method of manufacturing an insulated gate field effect device which is constructed of a semiconductor body having a lowly doped N-type first region adjacent an upper major surface of the body. Recesses or trenches are formed in the semiconductor body reaching deep into the first region in a vertical direction. Between respective trenches or, to be more specific, in the center of a field left by four rectangularly crossing trenches, a highly doped P-type second region is provided in a bulge-like shape reaching into the substrate in a vertical direction to a depth comparable with the trenches. A relatively lowly doped P-type third region and a relatively highly doped N-type fourth region extend from side walls of trenches surrounding said second region in a direction of said second region, said fourth region being located at said upper major surface of the semiconductor body and reaching in a lateral direction into the second region, whereas said third trench lying below said fourth region while not reaching the bottom depth of the trench reaches in a lateral direction just the boundary of the second region, providing a conduction channel area between said fourth and first regions. A gate insulating layer is formed in the trenches and on parts of the surfaces of the fourth region and a conductive material is filled in the trenches with the insulating layer interposed therebetween. A second insulating layer covers the filled trench and the first insulating layer extending thereout. Main electrodes are provided on both upper and lower major surfaces of the whole device. Document EP-A 0 345 380 discloses a conventional insulated gate semiconductor device with a semiconductor substrate and a first semiconductor layer disposed thereon, wherein at the surface at least one trench is provided reaching to the surface of the semiconductor substrate in a vertical direction. Over an inside wall of the trench a first insulating film is provided and a conductor is disposed inside the trench which is electrically connected to a control electrode. A further semiconductor layer is disposed in a portion of the surface of the first semiconductor layer next to the insulating film of the trench. A second insulating layer covers the surface of the conductor and a portion of the surface of the second semiconductor layer. Finally, first an second main electrodes are disposed at the main surfaces of the semiconductor device Document IEEE Transactions on Electron Devices, Vol. 41, Nr. 5, pages 800-808 provides a comparison of ACCUFET, INVFET and EXTFET structures with conventional UMOSFET structures. A conventional MOSFET structure according to this paper comprises, from upper to lower main surface of a semiconductor body, a P-base/N - /N + general structure, a trench extending from the upper main surface through the P-base layer in a vertical direction to the N- layer with a polysilicon gate electrode filled in and an insulating oxide film interposed therebetween, an N + source layer disposed in the upper main surface next to the insulating film of the gate trench, a second insulating oxide film covering the gate electrode, and source and drain electrodes provided at upper and lower main surfaces of the device. Alternative structures differ in principle in that the trench gate extends all the way down to the N + substrate. A structure called ACCUFET does not contain a P-base region, and the N - drift region is very lightly doped compared with conventional requirements. In a device called INVFET the N - region of the ACCUFET is replaced by a diffused P-base layer. In a third specimen called EXTFET the N + /N - junction is lifted while the trench is deeper so as to reach down to the N + substrate. Document JP 56-167360 A discloses a diffused resistance element in a semiconductor device, where a P - layer is selectively diffused on an N-- silicon substrate and first and second P + contact diffusion layers are provided on both ends of the diffusion layer. On the surface of the P - diffusion layer located between said P + diffusion layers, a controlling electrode consisting of a polysilocon, for example, is formed through the intermediary of an insulating film to be used for the controlling electrode. On the entire surface of the controlling electrode, another insulating film is deposited and after apertures have been provided in said other insulating film reaching down to the controlling electrode and the P + contact diffusion layers, respectively, first and second metal electrodes are formed and used as a resistance element between repective apertures. The resistance element of the above constitution is used under the condition wherein a negative voltage is applied to the second electrodes as against the first electrode. Through these procedures, the expansion of the depletion layer in the vicinity of a junction J of said N -- silicon substrate and said P - layer due to application of a high tension voltage can be suppressed by the MOS effect of the controlling electrode and the resistance value can be maintained constant. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same showing an improved beakdown voltage. According to the invention this object is achieved by independent claims 1, 7 and 11. Particular embodiments of the invention are defined by the subject-matter of dependent claims 2 to 6, 8 to 10, and 12 to 13. Since the third semiconductor layer of the second conductivity type, the impurity concentration of which is lower than that of the first semiconductor layer, is disposed between the first major surface of the semiconductor substrate and the first semiconductor layer, the depletion layer extends to the third semiconductor layer to relieve the electric field concentration at the tip end portion of the trench when a voltage is applied across the first main electrode and the second main electrode, and therefore an insulated gate semiconductor device of high breakdown voltage can be provided. Moreover, since the third semiconductor layer is disposed facing the trench with a portion of the semiconductor substrate between, the channel region of short length is formed on the first semiconductor layer and accordingly the ON-resistance can be reduced. Therefore, it is possible to provide an insulated gate semiconductor device of high breakdown voltage and low power consumption. Since the fourth semiconductor layers adjoin a plurality of trenches along both the sides of the opening and the two fourth semiconductor layers existing between the adjacent trenches sandwich the first semiconductor layer, a plurality of cell regions are formed and therefore an element of large current capacity can be provided. Since a plurality of fifth semiconductor layers are arranged in parallel, intersecting the openings of a plurality of trenches, a large number of cell regions are obtained and therefore an element of large current capacity can be provided. Since the first trench includes the first conductor electrically connected to the control electrode and the second trench includes the second conductor short circuited to the first main electrode, the spacing between the trenches can be lessened by disposing a second trench between adjacent first trenches, and the interference of electric fields occurs between the respective tip end portions of the first and second trenches, causing the electric fields to draw each other, to relieve the electric fields at the respective tip end portions. Therefore, it is possible to provide an insulated gate semiconductor device of high breakdown voltage. Since the third semiconductor layer of the second conductivity type, the impurity concentration of which is lower than that of the first semiconductor layer, is disposed in a portion of the semiconductor layer facing at least the first or the second conductor at the bottom portion of the trench with the first or second insulating film between, the interference of electric fields easily occurs between the tip end portions of the adjacent trenches to further relieve the electric fields at the tip end portions of the trenches. Therefore, it is possible to provide an insulated gate semiconductor device of higher breakdown voltage. Since the third semiconductor layers are so disposed as to be opposed to only the second conductor in the second trench, the ON-resistance can be suppressed and therefore an insulated gate semiconductor device of high breakdown voltage and low power consumption can be provided. Since the third and fourth trenches are alternately arranged and the second semiconductor layers adjoin the third trenches along both the sides of the third trenches, a wide channel is formed to thereby achieve an element of high current density, thus ensuring an insulated gate semiconductor device of large current capacity. Since the third and fourth trenches are alternately arranged and a plurality of fourth semiconductor layers are disposed in such Stripe shapes as to intersect the third and fourth trenches, a plurality of trenches can be provided with a narrow pitch, thus achieving a cell configuration of high density and large current capacity. Since the method of manufacturing the insulated gate semiconductor device comprises the step of implanting and diffusing the impurity of the second conductivity type in low concentration in the major surface of the semiconductor substrate to form the first semiconductor layer and the step of implanting and diffusing the impurity of the second conductivity type in higher concentration in the surface of the first semiconductor layer, the first semiconductor layer of the second conductivity type, the impurity concentration of which is lower than that of the second semiconductor layer, is formed between the major surface of the semiconductor substrate and the second semiconductor layer. Therefore an insulated gate semiconductor device of high breakdown voltage can be provided. Since the method of manufacturing the insulated gate semiconductor device further comprises, after the step of removing the semiconductor, the step of forming the oxide film over the inside wall of the trench to remove the impurity of the second conductivity type in the surface region of the inside wall of the trench in the first semiconductor layer and the step of removing the oxide film, the third semiconductor layer can be so disposed as to be opposed to the trench with a portion of the semiconductor substrate therebetween. Therefore, it is possible to provide an insulated gate semiconductor device of high breakdown voltage and low power consumption. Since the method of manufacturing the insulated gate semiconductor device comprises the implantation step using the resist pattern with a plurality of third openings arranged in parallel and the removing step using the shield film with a plurality of fourth openings of narrower stripe shape positioned correspondingly to the third openings along the direction of the length, the second semiconductor layer is so formed as to extend along the both sides of a plurality of trenches and two second semiconductor layers between the adjacent trenches sandwich the first semiconductor layer. Therefore, an insulated gate semiconductor device of large current capacity, consisting of elements of high current density, can be provided. Since the method of manufacturing the insulated gate semiconductor device comprises the implantation step using the resist pattern with a plurality of third openings of stripe shape arranged at prescribed pitches and the removing step using the shield film with a plurality of fourth openings of stripe shape in such stripe shapes as to intersect the third openings, it is possible to form the second semiconductor layer including regions which extend in parallel, intersecting the trenches. Therefore, an insulated gate semiconductor device having a cell configuration of high density can be provided. Since the method of manufacturing the insulated gate semiconductor device comprises the step of implanting and diffusing the impurity of the first conductivity type through the first resist pattern formed over the first semiconductor layer with the first opening made by removing a portion of the surface of the first semiconductor layer as a mask to form the second semiconductor layer and the step of removing the semiconductors in a vertical range from the surface of the second semiconductor layer to the semiconductor substrate by using the shield film formed over the second semiconductor layer with the second opening extending on the surface of the first semiconductor layer and the third opening to define a portion of the surface of the second semiconductor layer as a mask, it is possible to form the first semiconductor layer of the second conductivity type over the first major surface of the semiconductor substrate of the first conductivity type, a plurality of trenches consisting of the first trench and the second trench each having an opening at the surface of the first semiconductor layer, arranged in parallel with each other reaching the semiconductor substrate in the vertical direction, the insulating films over the inside walls of the trenches, the conductors inside the trenches so as to be opposed to the first semiconductor layer with the insulating films therebetween and the second semiconductor layer of the first conductivity type on a portion of the surface of the first semiconductor layer so as to be opposed to the conductor in the first trench with the insulating film of the first trench therebetween. Therefore, an insulated gate semiconductor device of high breakdown voltage can be provided. Since the method of manufacturing the insulated gate semiconductor device further comprises, subsequently to the step of removing the semiconductors, the step of implanting and diffusing the impurity of the second conductivity type in low concentration in the semiconductor substrate at the bottom portion of the first and second trench by using the shield film with the second and third openings, it is possible to form the third semiconductor layer of the second conductivity type, the impurity concentration of which is lower than that of the first semiconductor layer in portions of the semiconductor substrate facing the conductors at the bottom portions of the first and second trenches with the insulating films between. Therefore, an insulated gate semiconductor device of higher breakdown voltage can be provided. The method of manufacturing the insulated gate semiconductor device comprises the implantation step using the first resist pattern with a plurality of fifth openings of stripe shape disposed at prescribed pitches to form a plurality of fourth semiconductor layers and the step of removing the semiconductors in a vertical range from the surface of the fourth semiconductor layers to the semiconductor substrate by using the shield film formed on the first semiconductor layer and the fourth semiconductor layers with a plurality of sixth openings each extending on the surface of the first semiconductor layer and a plurality of seventh openings to each define a portion of the surface of the fourth semiconductor layer, and the sixth openings and the seventh openings are alternately arranged in parallel and the seventh openings are disposed on the fourth semiconductor layers along the direction of the length, each being narrower than each of the fourth semiconductor layers. That allows a plurality of cells to be formed and therefore an insulated gate semiconductor device of large current capacity, consisting of elements of high current density, can be provided. Furthermore, assuming that the shield film used in the removing step is put on the first resist pattern, the seventh openings extend correspondingly to the fifth openings along the direction of the length in such stripe shapes as to be narrower than the fifth openings and the sixth openings and the seventh openings are alternately arranged in parallel. The method of manufacturing the insulated gate semiconductor device comprises the implantation step using the first resist pattern with a plurality of fifth openings of stripe shape arranged in parallel to form a plurality of fourth semiconductor layers, and the sixth openings and the seventh openings are arranged in parallel with each other and the seventh openings are disposed in such stripe shapes as to intersect the fourth semiconductor layers. That allows a plurality of cells to be formed and therefore an insulated gate semiconductor device of small size, consisting of densely-arranged elements, can be provided. Furthermore, assuming that the shield film used in the removing step is put on the first resist pattern, the seventh openings extend in such stripe shape as to intersect the fifth openings and the sixth openings and the seventh openings are alternately arranged in parallel. Since the method of manufacturing the insulated gate semiconductor device comprises the step of removing the semiconductor in a vertical range from the surface of the first semiconductor layer to the semiconductor substrate by using the first shield film formed on the surface of the first semiconductor layer and the surface of the second semiconductor layer with a second opening to define a portion of the surface of the first semiconductor layer as a mask to form the first trench having an opening at the surface of the first semiconductor layer, the step of implanting the impurity of the second conductivity type in low concentration in the semiconductor substrate at the bottom portion of the first trench through the first shield film with the second opening, the step of forming the first insulating film over the surface of the first trench, the step of layering the first conductor over the first insulating film to fill the first trench, the step of removing the first conductor to be left in the first trench flatly at the opening portion, the step of forming the second shield film over the surface of the first conductor and the surfaces of the first and second semiconductor layers with the third opening to define a portion of the surface of the second semiconductor layer, the step of removing the semiconductor in a vertical range from the surface of the second semiconductor layer to the semiconductor substrate by using the second shield film with the third opening to form the second trench having an opening at the surface of the second semiconductor layer, the step of forming the second insulating film over the surface of the second trench, the step of layering the second conductor over the second insulating film to fill the second trench, the step of removing the second conductor to be left in the second trench flatly at the opening portion and the step of forming the insulating layer over the first and second semiconductor layers and the first and second conductors buried in the first and second trenches respectively, the third semiconductor layer of the second conductivity type, the impurity concentration of which is lower than that of the first semiconductor layer, is formed on a portion of the semiconductor substrate facing the second conductor at the bottom portion of the second trench with the second insulating film between. Therefore, an insulated gate semiconductor device of high breakdown voltage and low power consumption can be provided. The method of manufacturing the insulated gate semiconductor device comprises the implantation step using the first resist pattern with a plurality of fifth openings of stripe shape arranged at prescribed pitches to form a plurality of fourth semiconductor layers and the step of removing the semiconductors in a vertical range from the surfaces of the first and fourth semiconductor layers to the semiconductor substrate by using the shield film with a plurality of sixth openings extending on the surface of the first semiconductor layer and a plurality of seventh openings to each define a portion of the surface of the fourth semiconductor layer as a mask, and the sixth openings and the seventh openings are alternately arranged in parallel and the seventh openings are disposed on the fourth semiconductor layers along the direction of the length in such stripe shapes as to be narrower than the fourth semiconductor layers. That allows a plurality of cells to be formed and therefore an insulated gate semiconductor device of high current density and large current capacity can be provided. Furthermore, assuming that the second shield film used in the removing step is put on the first resist pattern, the seventh openings extend correspondingly to the fifth openings along the direction of the length in such stripe shapes as to be narrower than the fifth openings, and a plurality of portions corresponding to the sixth openings of the first shield film and a plurality of portions corresponding to the seventh openings of the second shield film are alternately arranged in parallel. The method of manufacturing the insulated gate semiconductor device comprises the implantation step using the first resist pattern with a plurality of fifth openings of stripe shape arranged at prescribed pitches, and the sixth openings and the seventh openings are arranged in parallel with each other and the seventh openings are disposed in such stripe shapes as to intersect the fourth semiconductor layers. That allows a plurality of cells to be formed and therefore an insulated gate semiconductor device of small size, consisting of densely-arranged elements, can be provided. Furthermore, assuming that the second shield film used in the removing step is put on the first resist pattern, the seventh openings extend in such stripe shapes as to intersect the fifth openings and a plurality of portions corresponding to the sixth openings of the first shield film and a plurality of portions corresponding to the seventh openings of the second shield film are alternately arranged in parallel. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of an insulated gate semiconductor device in accordance with the present invention; Fig. 2 is a fragmentary plan view of an insulated gate semiconductor device in accordance with a first preferred embodiment of the present invention; Fig. 3 is a fragmentary cross-sectional view of the insulated gate semiconductor device taken along the section of A-A of Fig. 2; Fig. 4 is a graph showing a relation between a cell pitch and a breakdown voltage of the insulated gate semiconductor device of the present invention; Figs. 5 to 13 are fragmentary cross-sectional views each showing a device in each step of a process of manufacturing the insulated gate semiconductor device of the present invention; Fig. 14 is a fragmentary plan view of an insulated gate semiconductor device in accordance with a second preferred embodiment of the present invention; Fig. 15 is a fragmentary cross-sectional view of a device in a process of manufacturing the insulated gate semiconductor device of the present invention; Fig. 16 is a fragmentary plan view of an insulated gate semiconductor device in accordance with a third preferred embodiment of the present invention; Figs. 17 to 28 are fragmentary cross-sectional views each showing a device in each step of a process of manufacturing the insulated gate semiconductor device of the present invention; Fig. 29 is a fragmentary plan view of an insulated gate semiconductor device in accordance with an fourth preferred embodiment of the present invention; Fig. 30 is a cross-sectional view of an insulated gate semiconductor device in the background art; Fig. 31 is a graph showing an electric field when a drain voltage is applied to the insulated gate semiconductor device in the background art; and Fig. 32 is a fragmentary cross-sectional perspective view of the insulated gate semiconductor device in the background art. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 2 is a fragmentary plan view of a UMOS in accordance with a first preferred embodiment of the present invention. A plan view of the whole device should be like Fig. 1, and the fragmentary plan view of Fig. 2 shows, for example, a portion which corresponds to the fragment 34. Fig. 3 is a fragmentary cross-sectional view taken along the section of A-A of Fig. 2. In Fig. 2, the source electrode 49 and the interlayer insulating film 48 of Fig. 3 are omitted. In Fig. 3, the N - layer 42 is formed over the surface of the N + substrate 41, and the P base layer 43 is formed thereover. The N + source regions 44 of stripe shape are formed in parallel, being spaced, in the surface of the P base layer 43. The trench 45 as a first trench is disposed along the stripe-shaped N + source region 44 in the direction of its length, extending in a vertical direction from the surface of the N + source region 44 to the N - layer 42, and a trench 55 as a second trench is disposed, extending in a vertical direction from the surface of the P base layer 43 exposed between the adjacent N + source regions 44 to the N - layer 42. The insulating films 46 are formed over the respective inside walls of the trenches 45 and 55, and the insulating film 46 formed inside the trench 45 serves as a gate insulating film. The trenches 45 and 55 are filled with polisilicons 47 up to the opening portions of the respective surfaces. The surface of the trench 45 is covered with the interlayer insulating film 48 and a source electrode 49 is disposed over the surface of the device where the interlayer insulating film 48, the surface of the polysilicon 47 in the trench 55, the N + source region 44 and the P base layer 43 are found. The polysilicon 47 in the trench 55, the P base layer 43 and the N + source region 44 are electrically connected by means of the source electrode 49. The drain electrode 50 is disposed over the other surface of the N + substrate 41. A trench structure of the trench 55 will be temporarily referred to as "dummy trench". In a device with a breakdown voltage of 60 V class, for example; when the spacing between the trenches 45 and 55 is about 1.5 µm and a trench width is 1 µm, a cell pitch is about 5 µm where the cell pitch defines a pitch between two normal trenches when a dummy trench is disposed between the normal trenches. Other structural features are the same as those of the first preferred embodiment. And all of the elements are composed of the same materials as discussed in the first preferred embodiment. Furthermore, the dummy trench is insulated from the gate. Now, an operation will be discussed. Fig. 4 is a graph showing a relation between the cell pitch and the breakdown voltage in the UMOS, which is given by simulation. This simulation, using cells of the same configuration as shown in Fig. 30, shows a change of the breakdown voltage as the cell pitch changes. Since the trench width is constant, the change of the cell pitch corresponds to the change of the spacing between the trenches. Fig. 4 shows a change of the breakdown voltage of the device under the application of the drain voltage. When the gate voltage V GS is 0 V, the breakdown voltage little changes and slightly falls as the cell pitch becomes 5 µm or narrower. In contrast, when the gate voltage V GS is reversely biased, the breakdown voltage rises as the cell pitch becomes narrower, getting close to the breakdown voltage when the gate voltage V GS is 0 V. Thus, it can be seen that the breakdown voltage when reversely biased rises as the cell pitch becomes narrower. Accordingly, the breakdown voltage can increase if the spacing between the trenches is set sufficiently narrow even in the background-art device. If the spacing between the trenches is wide, an electric field is generated by a voltage equivalent to the sum of the drain voltage V DS and the reversely-biased gate voltage V GS at the tip end portion of the trench 5 which protrudes in the N - layer 2. When the cell pitch is 5 µm or below, it seems that since an electric field is also generated by the same voltage at the tip end portion of the adjacent trench 5, an interference of the electric fields occurs between the adjacent trenches, mutually drawing the others' potential distributions at the tip end portions, to relieve an electric field concentration at the tip end portion of the trench 45, and as the result the breakdown voltage increases. In the background-art structure, however, it is difficult to lessen the width of the N + source region 44, in consideration of the manufacturing process, because the N + source region, which is usually formed by diffusion, needs a width equivalent to the diffused layer depth in the case where the N + source region is provided for every one trench 5, and an extra width for mask alignment is required in forming the interlayer insulating film to cover the polysilicon in the trench over the exposed surface of the N + source regions since there arises a need for establishing a short circuit between the N + source region and the P base layer. In the fifth preferred embodiment, the dummy trench without the N + source region is provided between the normal trenches 45, and the spacing between the dummy trench and the normal trench 45 is shorten by reduction in extra width for mask alignment, to thereby increase the breakdown voltage. In the device provided with the dummy trenches, when the pitch between the normal trench and the dummy trench is 5 µm or below, since the electric field at the tip end portion of the trench 45 is equivalent to the applied voltage and the electric field at the tip end portion of the adjacent trench 55 (dummy trench) is equivalent to the source voltage, the interference of the potential distributions occurs between the normal trench and the dummy trench, mutually drawing the others' potential distributions at the tip end portions, to relieve the electric field concentration at the tip end portion of the trench 45. As the result, the breakdown voltage increases. Next, a method of manufacturing the UMOS in the first preferred embodiment will be discussed. Figs. 5 to 13 are fragmentary cross-sectional views each showing a device in each step of a process of manufacturing the insulated gate semiconductor device of the present invention. First, the N + substrate 60 is prepared and the N - layer 61 is formed thereon (see Fig. 5). Next, the P-type impurity is implanted into the N - layer 61 and diffused therein to form the P base layer 63 (see Fig. 6). A resist is layered over the surface of the P base layer 63 and then a photolithographic process is performed to form the resist pattern 64 having a plurality of stripe-shaped openings as first openings. The N-type impurity is implanted in high concentration to the surface of the P base layer 63 through the resist patten 64 as a mask and diffused therein to form the N + source regions 65 (see Fig. 7). After that, the oxide film 66 is formed over the surfaces of the P base layer 63 and the N + source region 65. A silicon etching mask is formed of the oxide film 66, having a stripe-shaped opening on the surface of the P base layer 63 as a second opening and a stripe-shaped opening on the surface of the N + source region 65 as a third opening which is narrower in width than the N + source region 65. An etching is performed through RIE (Reactive Ion Etching) by using the silicon etching mask of the oxide film 66 to form the trenches 67 which extend from the surface of the P base layer 63 and the surface of the N + region 65 to the N - layer 61 (see Fig. 8). Next, a thermal oxide film is formed over the surface of the trenches 67. The polysilicon 69 doped with the P-type impurity is layered on the oxide film over the surfaces of the P base layer 63, the N + source region 65 and the trenches 67, to fill the trenches 67. (see Fig. 9). The layered polysilicon 69 is etched back to the opening portion of the trench 67, so as to leave the polysilicon 69 filling the trench 67 (see Fig. 10). After that, the BPSG 70 is layered over the surfaces of the P base layer 63 and the N + source region 65 and the surface of the polysilicon 69 buried in the trench 67 (see Fig. 11). Next, the resist 71 is layered over the BPSG 70 and then a photolithographic process is performed to form a resist pattern having an opening to encircle the surface of the P base layer 63, the opening portion of the trench 67 formed in the surface of the P base layer 63 and some portions of the N + source region 65, to close the remaining portions of the N + source region 65 and the opening portion of the trench 67 formed in the N + source region 65. An etching of the BPSG 70 and the oxide film 68 is performed by using the resist pattern as a mask, to form the interlayer insulating film 70 over the surface of the polysilicon 69 buried in the trench 67. (see Fig. 12). The Al-Si 72 is layered over the surfaces of the P base layer 63 and the portions of the N + source region 65 which are exposed by etching and the interlayer insulating film 70 so that the P base layer 63 and the N + source region 65 may be short circuited. At the same time, the source electrode, the gate interconnection connected to the polysilicon 69 buried in the trench 67 and the gate pad are formed (see Fig. 13). Further, the drain electrode is formed over the other surface of the N + substrate 60. Fig. 14 is a fragmentary plan view of a UMOS in accordance with a second preferred embodiment of the present invention. The UMOS of the second preferred embodiment has an arrangement where a P - region 54 as a third semiconductor layer is formed in the N - layer 42, facing the bottom portions of the trench 45 and the trench 55 of the fifth preferred embodiment. Other structural features are the same as those of the first preferred embodiment. By providing the P - region 54 as above, the potential distributions of the tip end portions of the trenches 45 and 55 extend along the P - region 54 and an interference of the electric fields easily occurs between the adjacent trenches. As a result, the electric fields at the tip end portions of the respective trenches are relieved to achieve a higher breakdown voltage of the device. A method of manufacturing the UMOS of the second preferred embodiment will be discussed. Fig. 15 is a fragmentary cross-sectional view of a device in the manufacturing process. The method of manufacturing the UMOS of the second preferred embodiment is almost the same as that of the first preferred embodiment. Specifically, the manufacturing process goes in a like manner until the step of forming the trench 67 (see Fig. 8), and subsequently the P-type impurity is implanted in low concentration by using the silicon etching mask 66 as a mask and diffused to form a P - region 81 in the N - layer 61, facing the bottom portion of the trench 67 (see Fig. 15). A thermal oxide film is subsequently formed over the surface of the trench 67, and the polysilicon doped with the P-type impurity is layered on the oxide film 68 over the surfaces of the P base layer 63, N + source region 65 and the trench 67, to fill the trench 67 (see Fig. 9). The steps following the above process are the same as those of the first preferred embodiment. Fig. 16 is a fragmentary plan view of a UMOS in accordance with a third preferred embodiment of the present invention. The UMOS of the third preferred embodiment has an arrangement where the P - region 54 is formed in the N - layer 42, facing the bottom portion of the trench 55 of the first preferred embodiment. Other structural features are the same as those of the first preferred embodiment. By providing the P - region 54 as above, the potential distribution of the tip end portion of the trench 55 extends along the P - region 54 and an interference of the electric fields easily occurs between the adjacent trenches. As a result, the electric field at the tip end portion of each of the trenches is relieved to achieve a higher breakdown voltage. Since the P - region 54 is not formed on the current path from the source electrode 49 to the drain electrode 50 via the channel region 52 formed in the vicinity of the trench 45, it is possible to suppress the ON-resistance. A method of manufacturing the UMOS of the third preferred embodiment will be discussed. Figs. 17 to 28 are fragmentary cross-sectional views each showing a device in each step of a process of manufacturing the insulated gate semiconductor device of the present invention. First, the N + substrate 60 is prepared and the N - layer 61 is formed thereon (see Fig. 17). Next, the P-type impurity is implanted into the N - layer 61 and diffused therein to form the P base layer 63 (see Fig. 18). A resist is layered over the surface of the P base layer 63 and then a photolithographic process is performed to form the resist pattern 64 having a plurality of stripe-shaped openings as first openings. The N-type impurity is implanted in high concentration into the surface of the P base layer 63 through the resist patten 64 as a mask and diffused therein to form the N + source regions 65 (see Fig. 19). After that, the oxide film 66 is formed as a shield film over the surfaces of the P base layer 63 and the N + source regions 65. A silicon etching mask is formed of the oxide film 66, having a stripe-shaped opening on the surface of the P base layer 63 as a second opening. An etching is performed through RIE by using the silicon etching mask to form the trench 67 which extends from the surface of the N + region 65 to the N - layer 61. The P-type impurity is implanted in low concentration by using the silicon etching mask as a mask and diffused to form the P - region 81 in the N - layer 61, facing the bottom portion of the trench 67 (see Fig. 20). A thermal oxide film is subsequently formed over the surface of the trench 67, and the polysilicon 69 doped with the P-type impurity is layered over the surface of the device, to fill the trench 67. (see Fig. 21). The layered polysilicon 69 is etched back to the opening portion of the trench 67 so as to leave the polysilicon 69 filling the trench 67 (see Fig. 22). An oxide film is formed over the surface of the polysilicon 69 filling the trench 67 up to its opening portion. A silicon etching mask 84 is formed of the oxide film over the surface of the device, having a stripe-shaped opening as a third opening on the surface of the N + source region 65 along the trench 67 formed on the surface of the P base layer 63. An etching is performed through RIE by using the silicon etching mask 84 as a mask to form a trench 82 which extends from the surface of the N + region 65 to the N - layer 61 (see Fig. 23). A thermal oxide film is subsequently formed over the surface of the trench 82, and a polysilicon 83 doped with the P-type impurity is layered over the surface of the device, to fill the trench 82. (see Fig. 24). The layered polysilicon 83 is etched back to the opening portion of the trench 82 so as to leave the polysilicon 69 filling the trench 82 (see Fig. 25). The steps shown in Figs. 40 to 42 may be performed after the steps shown in Figs. 23 to 25. In the subsequent step, the BPSG 70 is layered over the device (see Fig. 26). Next, a resist is layered over the BPSG 70 and then a photolithographic process is performed to form the resist pattern 71 having an opening to encircle the surface of the P base layer 63, the opening portion of the trench 67 formed in the surface of the P base layer 63 and some portions of the N + source region 65, to close the remaining portions of the N + source region 65 and the opening portion of the trench 82 formed in the N + source region 65. An etching of the BPSG 70 and the oxide film 68 is performed by using the resist pattern 71 as a mask, to form an interlayer insulating film over the surface of the polysilicon 83 buried in the trench 82. (see Fig. 27). The Al-Si 72 is layered over the surfaces of the P base layer 63 and the portions of the N + source region 65 which are exposed by etching and the interlayer insulating film so that the P base layer 63 and the N + source region 65 may be short circuited. At the same time, the source electrode, the gate interconnection connected to the polysilicon 83 buried in the trench 82 and the gate pad are formed (see Fig. 28). Further, the drain electrode is formed over the other surface of the N + substrate 60. Fig. 29 is a fragmentary plan view of a UMOS in accordance with a fourth preferred embodiment of the present invention. The UMOS of the fourth preferred embodiment has an arrangement where a plurality of the stripe-shaped N + source regions 44 are aligned in a row on the surface of the P base layer 43 and the trench 47 is so disposed as to intersect the N + source regions 44. The P base layer 43 existing under the N + source regions 44 is contiguous to the exposed P base layer 43 between the N + source regions 44. Other structural features other than the arrangement of the N + source regions 44 are the same as those of the first to second preferred embodiments. Having such a configuration as above, the UMOS can establish an electrical connection of the P base layer 43 and the N + source region 44 with the source electrode 49 unrestrictedly at the exposed portion of the N + source regions 44 intersecting the trench 47, not covered with the interlayer insulating film 48. Accordingly, the extra width required for the mask alignment can be reduced in forming the interlayer insulating film 48. As a result, it becomes possible to set a shorter spacing between the trench serving as a gate and the dummy trench and obtain a cell configuration of higher density, as compared with the case where the N + source regions 44 extend adjacently to the trench 47 along the direction of its length. Therefore, a device of smaller size can be achieved. Although an N-channel UMOS has been discussed above, the present invention may be naturally applied to an P-channel UMOS. While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.

Claims: An insulated gate semiconductor device, comprising: a semiconductor substrate (42) of a first conductivity type, having a first major surface and a second major surface; a first semiconductor layer (43) of a second conductivity type disposed on said first major surface of said semiconductor substrate (42), having a surface and at least two first trenches (45; 82) with an opening at said surface reaching said first major surface of said semiconductor substrate (42) in a direction vertical to said surface of said first semiconductor layer; an insulating film (46) formed over an inside wall of said at least two first trenches; a conductor (47) disposed inside said at least two first trenches, being opposed to said first semiconductor layer (43) with said insulating film (46) therebetween, and electrically connected to a control electrode; a second semiconductor layer (44; 65) of the first conductivity type disposed in a portion of said surface of said first semiconductor layer (43) being opposed to said conductor (47) with said insulating film (46) therebetween; an insulating layer (48) so disposed as to cover a portion of a surface of said second semiconductor layer (44) and a surface of said conductor (47); a first main electrode (49) disposed on said surfaces of said first and second semiconductor layers (43, 44); and a second main electrode (50) disposed on said second major surface of said semiconductor substrate (42), characterized in that a second trench (55; 67) is arranged between and in parallel to said at least two first trenches (45; 82), said second trench (55; 67) having no conductor connected to a control electrode disposed there inside. The insulated gate semiconductor device of claim 1 characterized in that said second semiconductor layer (44; 65) adjoins said at least two first trenches (45; 82) along both sides. The insulated gate semiconductor device of claim 1 characterized in that said second semiconductor layer (44; 65) is disposed in such stripe shape as to intersect said at least two first trenches (45; 82) and said second trench (55; 67). The insulated gate semiconductor device of any of claims 1 to 3, characterized in that a plurality of third semiconductor layers (54; 81) of the second conductivity type, the impurity concentration of which is lower than that of said first semiconductor layer (43; 63), are disposed in portions of said semiconductor substrate (42; 61) which are opposed to said conductor (47; 69) at a bottom portion of said second trench (55; 67) with said first insulating film (46) therebetween and/or opposed to said conductor (47; 69) at a bottom portion of said at least two first trenches (45; 82) with said insulating film (46) therebetween. The insulated gate semiconductor device of any of claims 1 to 4, characterized in that said insulated gate semiconductor device further comprises another insulating film (46) formed over an inside wall of said second trench (55; 67), and another conductor (47) disposed inside said second trench (55; 67), being opposed to said first semiconductor layer (43) with said other insulating film (46) therebetween. The insulated gate semiconductor device of claim 5, characterized in that said another conductor (47) is electrically connected to said first main electrode (49). A method of manufacturing an insulated gate semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate (61) of a first conductivity type which has a first major surface and a second major surface; (b) implanting and diffusing an impurity of a second conductivity type in said first major surface of said semiconductor substrate (61) to form a first semiconductor layer (63); (c) forming a first resist pattern (64) over a surface of said first semiconductor layer (63) with at least two first openings made by removing a portion of said surface of said first semiconductor layer (63); (d) further implanting and diffusing an impurity of the first conductivity type in said surface of said first semiconductor layer (63) through said first resist pattern with said at least two first openings as a mask, to form a second semiconductor layer (65); (e) forming a shield film (66) over said surface of said first semiconductor layer (63) and a surface of said second semiconductor layer (65) with a second opening extending on said surface of said first semiconductor layer (63) and at least two third openings on a portion of said surface of said second semiconductor layer (65); (f) removing semiconductors in a vertical range from said surface of said first or second semiconductor layer to said semiconductor substrate (61) by using said shield film (66) with said second and third resist as a mask, to form a second trench (67) and at least two first trenches (82) corresponding to said second opening and said at least two third openings, respectively, said second trench (67) being arranged between and in parallel to said at least two first trenches (82); (g) forming an insulating film (68) over a surface of said second trench (67) and a surface of said at least two first trenches (82); (h) layering a first conductor (69) over said insulating film (68) to fill said second trench (67) and said at least two first trenches (82); (i) removing said first conductor (69) to be left in said second trench (67) and said at least two first trenches (82) flatly at opening portions thereof; (j) forming an insulating layer (70) over said shield film and a surface of said first conductor buried in said second trench and said at least two first trenches; (k) forming a second resist pattern (71) over a surface of said insulating layer (70) with a fourth opening to define said surface of said first semiconductor layer (63), a portion of said surface of said second semiconductor layer (65) and said surface of said first conductor buried in said second trench (67); (l) removing said insulating layer (70) by using said second resist pattern (71) with said fourth opening as a mask; (m) layering a second conductor (72) over said surface of said first semiconductor layer (63), said portion of said surface of said second semiconductor layer (65) and said surface of said first conductor (69) buried in said second trench (67) which are exposed by said step (1) to form a first main electrode; (n) layering a third conductor over said second major surface of said semiconductor substrate to form a second main electrode; and (o) forming a control electrode to be electrically connected to said first conductor buried in said first trench said second trench (67) having no conductor connected to a control electrode disposed therein. The method of manufacturing the insulated gate semiconductor device of claim 7, wherein said at least two first openings of said first resist pattern (64) formed in said step (c) includes a plurality of fifth openings of stripe shape arranged at prescribed pitches; said second semiconductor layer (65) includes a plurality of fourth semiconductor layers of stripe shape which are formed through said fifth openings, said second opening and said at least two third openings of said shield film (66) formed in said step (e) include a plurality of sixth and seventh openings, respectively, which are alternately arranged in parallel with each other, and said seventh openings are disposed on said fourth semiconductor layers along the direction of the length in such stripe shapes as to be narrower than said fourth semiconductor layers. The method of manufacturing the insulated gate semiconductor device of claim 7, wherein said at least two first opening of said first resist pattern (64) formed in said step (c) includes a plurality of fifth openings of stripe shape arranged at prescribed pitches; said second semiconductor layer (65) includes a plurality of fourth semiconductor layers of stripe shape which are formed through said fifth openings, said second opening and said at least two third openings of said shield film (66) used in said step (e) include a plurality of sixth and seventh openings, respectively, which are alternately arranged in parallel with each other, and; said seventh openings are arranged in such stripe shapes as to intersect said fourth semiconductor layers. The method of manufacturing the insulated gate semiconductor device of any of claims 7 to 9, further comprising, subsequently to said step (f), the step of: (p) implanting and diffusing an impurity of the second conductivity type in low concentration in said semiconductor substrate (61) at bottom portions of said second and first trenches (67, 82) through said shield film (66) with said second opening and said at least two third openings as a mask. A method of manufacturing an insulated gate semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate (61) of a first conductivity type which has a first major surface and a second major surface; (b) implanting and diffusing an impurity of a second conductivity type in said first major surface of said semiconductor substrate to form a first semiconductor layer (63); (c) forming a first resist pattern (64) over a surface of said first semiconductor layer (63) with at least two first openings made by removing a portion of said surface of said first semiconductor layer; (d) further implanting and diffusing an impurity of the first conductivity type in said surface of said first semiconductor layer (63) through said first resist pattern (64) with said at least two first openings as a mask, to form a second semiconductor layer (65); (e) forming a first shield film (66) over said surface of said first semiconductor layer and a surface of said second semiconductor with a second opening on a portion of said surface of said first semiconductor layer (63); (f) removing semiconductors in a vertical range from said surface of said first semiconductor layer to said semiconductor substrate by using said first shield film (66) with said second opening as a mask, to form a second trench (67) having an opening at said surface of said first semiconductor layer (63); (g) still further implanting and diffusing an impurity of the second conductivity type in low concentration in said semiconductor substrate (61) at a bottom portion of said second trench through said first shield film (66) with said second opening as a mask; (h) forming a first insulating film (68) over a surface of said second trench; (i) layering a first conductor (69) over said first insulating film to fill said second trench; (j) removing said first conductor (69) to be left in said second trench flatly at an opening portion thereof; (k) forming a second shield (84) over a surface of said first conductor buried in said second trench (67) and said surfaces of said first and second semiconductor layers (63, 65) with at least two third openings on a portion of said surface of said second semiconductor layer; (1) removing a semiconductor in a vertical range from said surface of said second semiconductor layer (65) to said semiconductor substrate (61) by using said second shield film (84) with said at least two third openings as a mask, to form at least two first trenches (82) having an opening at said surface of said second semiconductor layer (65); (m) forming a second insulating film over a surface of said at least two first trenches (82); (n) layering a second conductor (83) over said second insulating film to fill said at least two first trenches (82); (o) removing said second conductor (83) to be left in said at least two first trenches (82) flatly at an opening portion thereof; (p) forming an insulating layer (70) over said surfaces of said first and second semiconductor layers (63, 65) and surfaces of said first and second conductors buried in said second and first trenches (67, 82), respectively; (q) forming a second resist pattern (71) over said insulating layer (70) with a fourth opening on said surface of said first semiconductor layer (63), a portion of said surface of said second semiconductor layer (65) and said surface of said first conductor buried in said second trench (67); (r) removing said insulating layer (70) by using said second resist pattern (71) with said fourth opening as a mask; (s) layering a third conductor (72) over said surface of said first semiconductor layer (63), said portion of said surface of said second semiconductor layer (65) and said surface of said first conductor (69) buried in said second trench which are exposed in said step (r) to form a first main electrode; (t) layering a fourth conductor over said second major surface of said semiconductor substrate (61); and (u) forming a control electrode electrically connected to said second conductor buried in said at least two first trenches (82) said second trench (67) having no conductor connected to a control electrode disposed therein. The method of manufacturing the insulated gate semiconductor device of claim 11, wherein said at least two first openings of said first resist pattern (64) formed in said step (c) includes a plurality of fifth openings of stripe shape arranged at prescribed pitches; said second semiconductor layer (65) includes a plurality of fourth semiconductor layers of stripe shape which are formed through said fifth openings, said second opening and said at least two third openings of said shield film formed in said step (e) include a plurality of sixth and seventh openings, respectively, which are alternately arranged in parallel with each other, and said seventh openings are disposed on said fourth semiconductor layers along the direction of the length in such stripe shapes as to be narrower than said fourth semiconductor layers. The method of manufacturing the insulated gate semiconductor device of claim 11, wherein said at least two first opening of said first resist pattern (64) formed in said step (c) includes a plurality of fifth openings of stripe shape arranged at prescribed pitches; said second semiconductor layer (65) includes a plurality of fourth semiconductor layers of stripe shape which are formed through said fifth openings, said second opening and said at least two third openings of said shield film used in said step (e) include a plurality of sixth and seventh openings, respectively, which are alternately arranged in parallel with each other, and said seventh openings are arranged in such stripe shapes as to intersect said fourth semiconductor layers.

Inventors: TAKAHASHI HIDEKI, TAKAHASHI, HIDEKI
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1995
Main classification: H01L29
IPC codes: H01L29, H01L21