A METHOD FOR PROGRAMMING A SINGLE EPROM OR FLASH MEMORY CELL TO STORE MULTIPLE LEVELS OF DATA THAT UTILIZES A PUNCTHROUGH CURRENT

Abstract: Multiple logic levels can be programmed into a single EPROM or FLASH memory cell by applying one of a corresponding number of programming voltages to the control gate of a memory cell that has a punch-through current during programming. During programming, the punch-through current forms substrate hot electrons which, in addition to the channel hot electrons, accumulate on the floating gate. By utilizing the punch-through hot electrons, a much lower control gate voltage can be utilized during programming. More importantly, however, once the channel hot electrons cease to exist, the punch-through hot electrons and holes converge to a stable charge that is related to the control gate voltage used during programming and the programmed threshold voltage of the cell.

Description: A METHOD FOR PROGRAMMING A SINGLE EPROM OR FLASH MEMORY CELL TO STORE MULTIPLE LEVELS OF DATA BACKGROUND OF THE INVENTION 1. Field of the Invention. The present invention relates to floating gate memory cells and, more particularly, to a method for programming a single EPROM or FLASH memory cell to store multiple levels of data, i.e., more than a logic "I " and a logic "0". 2. Description of the Related Art. FIG. 1 shows a cross-sectional drawing that illustrates a conventional n-channel, floating gate memory cell 10. As shown in FIG. 1, memory cell 10 includes an n-type source region 12 and an n-type drain region 14 which are formed a distance apart in a p-type substrate 16. The surface area of substrate 16 between the source and drain regions 12 and 14 defines a channel region 18 which is typically doped with additional p-type dopants (typically boron atoms) to adjust the threshold voltage of the cell. Formed over the channel region 18 of substrate 16 is a stacked gate structure which includes a first insulation layer 20, a floating gate 22 formed over insulation layer 20, a second insulation layer 24 formed over floating gate 22, and a control gate 26 formed over insulation layer 24. With 0.8 micron technology, memory cell 10 is conventionally programmed to store one of the two logic levels, i.e., a logic "1" or a logic "0", by grounding the source region 12 and substrate 16, applying a bias voltage VD in the range of 6-8 volts to the drain region 14, and applying a programming voltage VG of approximately 12 volts to control gate 26. FIG. 2 shows a cross-sectional drawing that illustrates the result of these bias conditions on memory cell 10. As shown in FIG. 2, when the programming voltage is applied to control gate 26, a positive potential is induced on floating gate 22. The positive potential on floating gate 22, in turn, attracts electrons from the doped p-type atoms in the channel region 18 to the surface of substrate 16 to form a channel 30, and also repels holes from the doped p-type impurity atoms to form a depletion region 32. When the bias voltage VD is applied to the drain region 14, an electric field is established between the source and drain regions 12 and 14 in channel region 30 and depletion region 32. The electric field accelerates the electrons in channel 30 which, in turn, have ionizing collisions that form "channel hot electrons". The positive potential of floating gate 22 attracts these channel hot electrons which penetrate insulation layer 20 and begin accumulating on floating gate 22. The negative charge on floating gate 22 that results from the accumulated electrons, in turn, directly corresponds to the threshold voltage required to induce a defined current to flow through memory cell 10. Thus, when a large negative charge has accumulated on floating gate 22, the threshold voltage of the cell is large because a larger positive voltage must be applied to control gate 26 to compensate for the negative charge on floating gate 22. Similarly, if the cell has not been programmed, the threshold voltage is small because a smaller voltage will induce current to flow through the cell. The above-described process is self-limiting because, as the number of electrons on floating gate 22 increases, the potential of floating gate 22 decreases until the potential on floating gate 22 is insufficient to create channel 30. When memory cell 10 is read, a reference threshold voltage is applied to control gate 26 to again induce a potential on floating gate 22. If memory cell 10 has not been programmed, the positive charge on floating gate 22 will cause channel 30 to again be formed. As a result, current flows from the drain region 14 to the source region 12 through channel 30. If memory cell 10 has been programmed, the potential on floating gate 22 is reduced by the accumulated electrons so that a much smaller current flows through channel 30. By then comparing the current to a reference current, the magnitude of the current can be interpreted to be either a logic " 1 " or a logic "0". In other words, if the threshold voltage of the cell is larger than the reference threshold voltage, then one logic level is present, whereas if the threshold voltage of the cell is smaller than the reference threshold voltage, then the other logic level is present. Historically, the higher density of a memory array has been realized by reducing the feature sizes of the cells. As the feature sizes become ever smaller, however, this approach is becoming more costly and more difficult to implement. Another approach to increasing the density of a memory array is to program each cell to store more than two logic levels. As stated above, memory cells are conventionally programmed to store one of two logic levels, i.e., a logic "1" or a logic "0". However, if each memory cell could be programmed to store a logic "00", "01", "10", or "1 1", then the density of an array could be doubled without changing the physical size of the array. In theory, multi-level programming could be accomplished by varying the length of time that the programming voltage is applied to the control gate. Thus, for example, if the programming voltage was applied for a first time period, the floating gate would reach a corresponding first negative charge level. Similarly, if the programming voltage was applied for either a second, third, or fourth time period, the floating gate would reach either a corresponding second, third, or fourth negative charge level. The problem with this type of multi-level programming, however, is that it is difficult to precisely control the number of electrons that accumulate on the floating gate because the reduced floating gate potential that results from the electrons accumulating on the floating gate causes fewer electrons to be attracted to the floating gate, thereby causing the number of electrons accumulated on the floating gate to vary over time. The greater the variation, the more difficult it is to compare current levels during a read operation and determine which logic level is present. As a result, there is a need for a method to accurately program a cell to store multiple logic levels. SUMMARY OF THE INVENTION The present invention provides a method for accurately programming a single memory cell to store one of three or more logic levels. As a result, rather than storing either a logic "1 " or a logic "0", a single memory cell can store, for example, a logic "0-0", a "0-1", a "1-0", or a "1-1 ". A method for programming a single memory cell to store one of three or more logic levels as one of three or more threshold voltages includes the step of providing a floating-gate memory cell that has a source and a drain formed in a substrate, and a control gate. In accordance with the present invention, the floating-gate memory cell is formed to produce a punch-through current during programming. The method continues with the step of selecting one threshold voltage from the three or more threshold voltages that can be stored by the memory cell. In the present invention, each of the three or more threshold voltages corresponds to three or more programming voltages. The selected threshold voltage is programmed into the cell by grounding the source of the memory cell, applying a bias voltage to the drain of the memory cell, and applying the programming voltage that corresponds with the one selected threshold voltage to the control gate of the memory cell for a predetermined time. A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional drawing illustrating a conventional one-micron, n-channel, floating gate memory cell 10. FIG. 2 is a cross-sectional drawing illustrating the bias conditions that result when memory cell 10 is programmed. FIG. 3 is a cross-sectional drawing illustrating an n-channel, floating-gate memory cell 100 in accordance with the present invention. FIG. 4 is a graphical representation illustrating the effect of multi-level programming on cell 100. DETAILED DESCRIPTION FIG. 3 shows a cross-sectional drawing that illustrates an n-channel, floating-gate memory cell 100 in accordance with the present invention. As described in greater detail below, multiple logic levels can be programmed into a memory cell by applying a corresponding number of programming voltages to the control gate of a memory cell that has a punch-through current during programming. As shown in FIG. 3, when formed in a p-type substrate 110, memory cell 100 includes an n-type source region 112, an n-type drain region 1 14, and a channel region 1 16 formed between the source and drain regions 1 12 and 1 14. The channel region 1 16 is doped with p-type impurity atoms to adjust the threshold voltage of the cell. Memory cell 100 also includes a first insulation layer 120 formed over channel region 1 16, a floating gate 122 formed over insulation layer 120, a second insulation layer 124 formed over floating gate 122, and a control gate 126 formed over insulation layer 124. In accordance with the present invention, the channel region 1 16 is sized to form a punch-through current during programming so that, as described in greater detail below, the optimal number of "substrate hot electrons" can be generated. As is well known, punch-through current is the current that flows from the drain region to the source region during programming regardless of the absence or presence of an inversion layer, i.e., a channel. The feature sizes, the doping level of the channel, the drain voltage, and the substrate voltage of cell 100 that are required to produce a punch-through current, or to optimize the substrate hot electrons, are well known in the art. With the use of the punch-through current, memory cell 100 can be programmed to store one of a plurality of logic levels by grounding the substrate 110 and the source region 1 12, applying a bias voltage VD to the drain region 1 14 of approximately 5 volts, and applying one of a corresponding plurality of programming voltages to control gate 126. Alternately, a negative voltage can be first applied to substrate 1 10 for a first period of time, followed by grounding substrate 1 10. In operation, when one of the programming voltages is applied to control gate 126, a positive potential is induced on floating gate 122 which, in turn, attracts electrons from the doped p-type atoms in the channel region 1 16 to the surface of substrate 110 to form a channel 130. As with conventional programming, this potential repels holes from the doped impurity atoms and forms a depletion region 132. The shape of depletion region 132, in turn, is defined by the channel length of memory cell 100, i.e., the distance between the source and drain regions 112 and 1 14. When the length of the channel is sized to optimize the formation of a punch-through current, as shown in FIG. 3, the boundary between depletion region 132 and substrate 1 10 is moved further away from the surface of substrate 1 10 than when the length of the channel is sized to prevent the formation of a punch-through current, as shown in FIG. 1. When the bias voltage VD is applied to the drain region 1 14, an electric field is established between the source and drain regions 1 12 and 114. The electric field, as with conventional programming, accelerates the electrons in channel 130 which, in turn, have ionizing collisions that form "channel hot electrons". The positive potential on floating gate 122 attracts these channel hot electrons which penetrate insulation layer 120 and begin accumulating on floating gate 122. Due to the increased size of the depletion region 132, the electric field established between the source and drain regions 1 12 and 1 14 also induces additional electrons to flow from the source region 1 12 to the drain region 1 14, thereby producing the punch-through current. As the punch-through current generated electrons near the drain region 1 14, the electric field accelerates the punch-through current generated electrons which, in turn, also have ionizing collisions that form "hot" electrons. The positive potential on floating gate 122 also attracts these hot electrons which penetrate insulation layer 120 and begin accumulating on floating gate 122. One significant advantage of the present invention is that since floating gate 122 receives both channel hot electrons and punch-through hot electrons, a significantly lower control gate voltage can be used during programming than is conventionally used to program a cell because fewer of the channel hot electrons need to be directed to floating gate 122. As with conventional, floating-gate, memory cell programming, the positive potential on floating gate 122 is reduced as a result of the accumulating negative charge to the point where channel 130 disappears. However, unlike conventional floating-gate programming, the flow of the punch-through electrons is not dependent on the existence of a channel. As a result, the punch-through current generated electrons continue to accumulate on the floating gate after channel 130 has disappeared and the channel hot electrons are no longer being formed. In addition, also unlike conventional floating-gate programming, when the negative charge on floating gate 122 reaches a "convergence point", hot punch-through holes, which are also formed in the ionizing collisions that form the hot punch-through electrons, are attracted to floating gate 122 by the negative charge. The accumulation of hot holes, in turn, forces the potential on floating gate 122 to converge to a stable value. Experimental results have shown that the stable charge that results from this self-convergence process is related to both the voltage applied to the control gate and the resulting threshold voltage of the cell, i.e., the voltage that is required to induce a defined current flow through a memory cell. FIG. 4 shows a graphical representation that illustrates these experimental results. As shown in FIG. 4, when one volt was applied to the control gate, the charge on the floating gate converged to a threshold voltage of approximately three volts from an initial threshold voltage of 1.5 volts within 50 milliseconds or less. Similarly, when two, three, and four volts were applied to the control gate, the charge on the floating gate converged to threshold voltages of approximately four, five, and six volts, respectively, within 50 milliseconds or less. Although an initial threshold voltage of 1.5 volts was utilized in the above experiment, any initial threshold voltage after erase may be utilized. Since the charge on the floating gate converges to a stable value which corresponds to a defined threshold voltage within 50 milliseconds or less, a single floating gate memory cell can be programmed to have one of a plurality of threshold voltages by applying the corresponding voltage to the control gate during programming. As a result, a single floating gate memory cell can be utilized to store two or more bits of data. For example, a 0-0 could be represented by a threshold voltage of 3 volts, while a 0-1 could be represented by a threshold voltage of 4 volts. Similarly, a 1-0 could be represented by a threshold voltage of 5 volts, while a 1-1 could be represented by a threshold voltage of 6 volts. As further shown in FIG. 4, the experimental results also show that changes in the control gate voltage are linearly related to changes in the threshold voltage, i.e., a one volt increase in the control gate voltage increases the threshold voltage by one volt. As a result, memory cell 100 is not limited to representing two bits, but can represent any number of bits depending on the sensitivity of the current sense detectors utilized to discriminate one threshold voltage from another. Furthermore, even a continuous analog level can be stored in a cell as a threshold voltage. Thus, for example, a 0-0-0 could be represented by a threshold voltage of 3 volts, while a 0-0-1 could be represented by a threshold voltage of 3.5 volts. Similarly, a 0-0-0-0 could be represented by a threshold voltage of 3 volts, while a 0-0-0-1 could be represented by a threshold voltage of 3.25 volts. As stated above, the channel region 116 is sized to optimize the formation a punch-through current. Alternately, the channel region 116 can be sized to form less punch-through current than is optimally obtainable. The result of utilizing less punch-through current, however, is that it takes more time, i.e., greater than 50 milliseconds, for a stable potential to converge on the floating gate. As stated above and as shown in FIG. 4, one significant advantage of the present invention is that each memory cell can be programmed to store multiple levels by utilizing a programming voltage that is considerably less than the programming voltage typically used, i.e., less than five volts in the present invention compared to approximately 13 volts. In addition to providing a substantial power savings for low power applications, such as notebook computers, the present invention eliminates the need for charge pumps on memory chips which are conventionally required to produce the programming voltage, i.e., 12 volts. As is well known, charge pumps can consume a significant area, i.e., up to 30% of the total die area of a memory chip. Thus, by eliminating the need for charge pumps, the present invention significantly reduces the area required for a memory cell, and therefore the cost of a memory. The present invention also leads to an increase in the density of a memory array. Conventionally, punch-through current is considered undesirable. In 0.6 micron technology, the minimum channel length that can be obtained without inducing a punch-through current during normal functioning is approximately 0.6 microns. However, since the present invention utilizes punch-through current, a 0.6 micron channel length limitation no longer applies. In 0.6 micron technology, punch-through current can be obtained without breaking down the cell by utilizing channel lengths in the range of approximately 0.4 to 0.7 microns. In addition, with the elimination of the high programming voltage, less isolation between both memory cells and the peripheral circuitry is required. As a result, the present invention substantially reduces the size of the array and periphery circuits, thereby increasing the density of the array. It should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. For example, although the present invention has been described in terms of an n-channel, floating-gate memory cell, the present invention equally applies to a p-channel, floating-gate memory cell. Thus, it is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims: WHAT IS CLAIMED IS: 1. A method for programming a single floating-gate memory cell to store one of three or more threshold voltages, the memory cell having a source and a drain formed a distance apart in a substrate, and a control gate, the distance between the source and drain defining a channel region, the method comprising the steps of: providing the floating-gate memory cell so that a punch-through current flows from the drain to source through the channel region during programming; selecting one threshold voltage from said three or more threshold voltages, said three or more threshold voltages corresponding to three or more programming voltages; grounding the source of the memory cell; applying a bias voltage to the drain of the memory cell; and applying the programming voltage that corresponds with said one threshold voltage to the control gate of the memory cell for a predetermined time. 2. The method of claim 1 and further comprising the step of grounding the substrate of the memory cell. 3. The method of claim 1 wherein the bias voltage is less than or equal to five volts. 4. The method of claim 1 wherein a maximum programming voltage is less than or equal to five volts. 5. The method of claim 1 wherein the predetermined time is less than or equal to 50 milliseconds. 6. A method for programming a single floating-gate memory cell to store one of three or more threshold voltages, the memory cell having a first implanted region and a second implanted region formed a distance apart in a substrate, and a control gate, the distance between the first implanted region and the second implanted region defining a channel region, the method comprising the steps of: providing the floating-gate memory cell so that a punch-through current flows from the second implanted region to first implanted region through the channel region during programming; selecting one threshold voltage from said three or more threshold voltages, said three or more threshold voltages corresponding to three or more programming voltages; grounding the first implanted region of the memory cell; applying a bias voltage to the second implanted region of the memory cell; and applying the programming voltage that corresponds with said one threshold voltage to the control gate of the memory cell for a predetermined time. 7. The method of claim 6 and further comprising the step of grounding the substrate of the memory cell.

Inventors: BERGEMONT ALBERT, CHI MIN-HWA, BERGEMONT, ALBERT, CHI, MIN-HWA
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1995
Main classification: G11C11
IPC codes: G11C11