Electrically driven switch, integrated circuit and electronic card using the same

Abstract: The switch in accordance with the present invention comprises two MOS transistors (M1,M2) whose main conduction paths are connected respectively upstream and downstream of the terminals (T1,T2) of the network (C2) of which it is desired to control electrically the electrical connection. In this manner current can flow in the network (C2) only if both the transistors (M1,M2) are conducting.

Description: The present invention relates to an electronic card comprising a switching circuit of the type designed to switch variable polarity signals. Switching bipolar electrical signals, especially if no great restrictions are placed on the magnitude of said signals, is not a simple problem to resolve especially if simple circuitry solutions are being sought. The problem becomes more complicated if the switch is to be made in integrated form since the problems tied to the polarity of the substrate and the process wells must be faced at the same time. A switch of this type is necessary e.g. in electronic cards and in particular in those of the type without contact. This type of card and its possible operation are described e.g. in patent application EP 0 602 449. This card calls for switching of a load connected in parallel to a resonating circuit generally provided by connection in parallel of a coil and a capacitor. In patent application EP 0 602 448 linked to the foregoing is illustrated load switching control. A production method for a card of this type is also shown in patent application EP 0 587 011. These electronic cards perform their data memorization, reception and/or transmission function when they are coupled to a base station capable of transmitting and/or receiving radio-frequency signals whether modulated or unmodulated. FIG. 1 shows an entire transmission system where BS indicates the base station and BC a coil used by the station BS as an antenna, SC indicates the electronic card and CC indicates a coil used in the card SC as an antenna, which constitutes together with a capacitor C1 the resonant circuit while the rest of the circuitry is preferably provided in one or more integrated circuits. If the capacitance of the capacitor C1 is not too high, it too can be advantageously integrated. When the two coils BC and CC are very near in comparison with the wavelength of the radio-frequency signal the coil behavior can be assimilated with that of a transformer and it is also possible to transfer electrical signals between the station BS and the card SC. Through the resonant circuit energy is received in the form of an unmodulated radio-frequency signal for operation of the card (this energy must allow operation of the card during a time period sufficient for data reception and/or transmission), a modulated radio-frequency signal bearing data of interest for the card is received and an unmodulated radio-frequency signal for data transmission by the card is received. Transmission by the card takes place in the following manner. The resonant circuit of the card SC is normally tuned on the transmission frequency of the station BS. If the resonant circuit parameters are changed the station BS can notice it because this change will lead to changes in the current circulating and/or in the voltage developed at the ends of the coil BC in a manner similar to what takes place on the primary winding of a transformer when the load connected to its secondary winding changes for example. If the changes in the resonance parameters are made by the circuitry included in the card SC in a rhythmic manner following a data signal the station BS will be able to "receive" these data "transmitted" by the card SC. The purpose of the present invention is to supply an electronic card having an electrically controlled bipolar switch suited in particular for integration. The purpose is achieved by means of an electronic card having the characteristics set fort in claim 1 while further advantageous aspects of the present invention are set forth in the dependent claims. The electronic card in accordance with the present invention comprises a switching circuit having two MOS transistors whose main conduction paths are connected respectively upstream and downstream of the terminals of the network whose electrical connection it is desired to control electrically. In this manner current can flow in the network only if both the transistors are in conduction. The invention is clarified by the description given below considered together with the annexed drawings wherein: FIG. 1 shows a block diagram of a transmission system comprising an electronic card in accordance with the present invention, FIG. 2 shows a circuit diagram of a switching circuit comprised in the electronic card in accordance with the present invention, FIG. 3 shows a circuit diagram of a rectifier to be used in combination with a switching circuit comprised in the electronic card in accordance with the present invention, and FIG. 4 shows a circuit diagram of another switching circuit comprised in the electronic card in accordance with the present invention. The electronic card in accordance with the present invention is the type designed to couple a first and a second terminal of a first electrical network respectively to a first and a second node of a second electrical network. With reference to FIG. 2 the first terminal is indicated by T1, the second terminal by T2, the first node by N1 and the second node by N2. The first electrical network consists of a two-terminal circuit element and specifically a capacitor C2, the second electrical network is not shown. The switch of FIG. 2 comprises basically a first MOS transistor M1 having a main conduction path connected between the node N1 and the terminal T1 and a second MOS transistor M2 having a main conduction path connected between the node N2 and the terminal T2. So that current can flow in the capacitor C2 it is necessary that both the transistors M1 and M2 be conducting independently of the potentials assumed by the nodes N1, N2 and the terminals T1, T2. Consequently their voltages VGS must be higher that the corresponding threshold voltages. So that current may not flow it is sufficient that one of the two transistors M1, M2 be off and naturally better yet if both are off because in this manner any kind of flow even transient of charges from or to the network connected to the switch will be prevented. In the switch of FIG. 2 the transistors M1 and M2 have a channel of the same type of conductivity (N channel) and have their control terminals connected together. In this manner it is possible to control the switch with a single electrical signal of logical type. To determine the potentials corresponding to the high and low logic states which permit correct and optimal operation of the switch it suffices to find the maximum and minimum potentials assumed by the nodes N1, N2 during operation of the system made up of the two networks and the switch, set the high value at least higher than the threshold voltage at the greater of the maxima, and set the smaller low value at the difference between the smaller of the minima and the threshold voltage. With these settings both the transistors are simultaneously in conduction or interdiction. In the circuit of FIG. 2 the transistors M1 and M2 have their body terminals connected to the respective source terminals. Generally the connections of the body terminals are extremely important and indeed it is necessary to avoid occurrence of undesired conduction across the parasitic junctions associated with the MOS transistors and connected to the body terminals. Apart from the type of MOS transistors and how they are connected the switch needs a network for driving them which must be powered. Such a network can be included in the switch control circuitry or in the switch itself. If the control circuitry is included in the first or second network it is very appropriate to power both the drive circuitry and the first and/or second network by means of the same power supply reference. The drive network must generate logical signals of appropriate level. If the positive power supply potential is less that the high level or if the negative power supply potential is higher than the low level it is necessary to provide a voltage booster circuit in the drive network. The drive network of FIG. 2 is very well suited to use in electronic cards as clarified below and consists of a level shifter LS having a logical output U and two mutually reversed logical inputs I and IN, a first inverter P1, a second inverter P2, a storage capacitor CE and a diode D1. The network is connected to a power supply reference VR and a ground reference GND. The inputs of the shifter LS correspond to the inputs of the drive network. Generally it is not necessary to have two mutually reversed logical signals for a level shifter. Naturally if the particular topology of the shifter requires it both signals can be supplied from the outside or one of them can be generated internally from the other using an inverter. A shifter such as that inserted in the circuit of FIG. 2 is illustrated in greater detail in FIG. 4. The output U of the shifter LS is connected to the inputs of the inverters P1 and P2. The output of the inverter P2 corresponds to the output of the drive network. The capacitor CE and the diode are connected in series between the output of the inverter P1 and the reference VR. The intermediate tap of this series connection, which corresponds to a node DUP, is connected to the power supply input of the inverter P2. The shifter LS serves if the levels of the signals available for switch control do not correspond respectively to the reference potentials GND and VR and in particular if the high level is much lower than necessary. The group consisting of the inverter P1, capacitor CE and diode D1 constitutes a simple voltage booster circuit and in particular a duplicator. The duplicated continuous voltage, which corresponds to approximately double the difference in potential between the references VR and GND, is available at the node DUP. But specifically this is true only when the output signal U is at high level while when the output signal U is at low level the voltage at the node DUP corresponds to the power reference potential VR less the voltage drop at the ends of the diode D1. By means of this duplicate voltage, having in reality a variable value, the inverter P2 is powered and acts as an output stage. At the output of this inverter there will thus be a logical signal having low level corresponding to the reference potential GND and high level corresponding to the duplicate voltage. Naturally depending on the levels of the logical input signals the levels required at the logical output signals and the power supply potentials it will be necessary to choose an appropriate topology for the voltage booster circuit from among those known in the prior art. The shifter LS of FIG. 4 is equipped with two mutually inverted logical inputs I and IN, two mutually inverted logical outputs U and UN and two power supply inputs, one to be connected to the power supply reference VR and the other to be connected to the ground reference GND and comprises two n-channel MOS transistors M5 and M6 and two p-channel MOS transistors M7 and M8. In the case of the circuit of FIG. 2 the output UN is not shown because not used. The input I is connected to the control terminal of the transistor M5 which has its source and body terminals connected together to the reference GND and its drain terminal connected to the output UN. The input IN is connected to the control terminal of the transistor M6 which has its source and body terminals connected together to the reference GND and its drain terminal connected to the output U. The transistor M7 has it source and body terminals connected together to the reference VR and its drain terminal connected to the drain terminal of the transistor M6. The transistor M8 has its source and body terminals connected together to the reference VR and its drain terminal connected to the drain terminal of the transistor M5. The transistors M7 and M8 also have their respective control terminals cross connected to the drain terminals. Another switch in accordance with the present invention is shown in FIG. 4. This switch exhibits two symmetrical branches. The first branch A comprises the series connection between the nodes N1 and N2 of a first transistor M1A, a first network C2A-a first capacitor in FIG. 4 -, and a second transistor M2A. The second branch B comprises the series connection between the nodes N1 and N2 of a third transistor M1B, a third network C2B -, a third capacitor in FIG. 4 -, and a fourth transistor M2B. All the transistors are the MOS type. The two networks C2A and C2B are essentially equal and the four transistors must be driven in such a manner that when the switch is closed only one of the two branches conducts depending on the polarity of the signal at the ends of the nodes N1 and N2. Specifically the transistor M1A is p-channel and has its source terminal connected to the node N1 and drain and body terminals connected together to a first terminal T1A of the network C2A, the transistor M2A is n-channel and has its source and drain terminals connected together to the node N2 and drain terminal connected to a second terminal T2A of the network C2A, the transistor M2B is p-channel and has its source terminal connected to the node N2 and drain and body terminals connected together to a fourth terminal T2B of the network C2B, and the transistor M1B is n-channel and has its source and body terminals connected together to the node N1 and drain terminal connected to a third terminal T1B of the network C2B. The connections of the various body terminals are extremely important and indeed it is necessary to avoid occurrence of undesired current conduction along the branches of the switch through the parasitic junctions associated with the MOS transistors and connected to the body terminals. As mentioned above for the switch of FIG. 2, apart from the type of MOS transistors and how they are connected, the switch needs a network which must be powered to drive them. Such a network can be included in the control circuitry of the switch or in the switch itself. If the control circuitry is included in the second network it is appropriate to power the drive circuitry and the second network by means of the same power reference. Choice of the channel type of the various MOS transistors adopted in the circuit of FIG. 4 permits avoiding the use of voltage booster circuits in the drive network if it is powered through the power supply reference of the second electrical network. Again this choice permits connecting together the control terminals of the two p-channel transistors M1A and M2B of the two n-channel transistors M2A and M1B and hence driving them by means of only two logical drive signals. Given the symmetry of the circuit the relationship between the two drive signals is simple. They are mutually reversed. The drive network can be simply and basically made up of the shifter LS which was described above. In FIG. 4 are also used a third inverter P3 connected to the output UN as an output buffer to drive the control terminals of the p-channel transistors and a fourth inverter P4 connected to the output U as an output buffer to drive the control terminals of the n-channel transistors. Operation of the circuit is conceptually similar to that of FIG. 2. But an interesting property was found experimentally when the first and the third networks consist of two preferably equal capacitors. The switch effect of the two capacitors is similar to the switching of a single capacitor having capacitance equal to the sum of the two. Switches such as those described above lend themselves to easy integration. An appropriate choice consists e.g. of connecting the ground reference GND to the substrate of the integrated circuit. An integrated circuit affected at least by variable polarity signals can include advantageously one or more switches in accordance with the present invention for controlled switching thereof. In addition to the switch the integrated circuit will include generally much other circuitry. In integrated circuits of this type it is extremely important to identify the node of the circuitry to which to connect the substrate and indeed, since often electronic components must be inserted in process wells distinct and isolated from each other by the "junction isolation" technique, it is essential that the substrate never be at a potential such that one or more of such junctions be in conduction conditions. In the case of a p-doped substrate it would be desirable to connect the substrate to the node of the circuit which takes on the lower potential during operation. In circuits affected by single-polarity signals this would be ground. In the case of variable polarity signals this is generally not true. If a bridge rectifier, e.g. such as that indicated by BR in FIG. 1, is integrated in the circuit together with the switch in accordance with the present invention, e.g. such as that indicated by SWITCH in FIG. 1, it can be elected to connect the negative terminal TN of the bridge BR to the substrate. In order for this to operate it is appropriate that the potential of the terminal TI2 never be less than approximately -700mV lower than the terminal lTN. This result can be achieved thanks to the circuit shown in FIG. 3. The bridge rectifier of FIG. 3 is equipped with two indifferent terminals TI1 and TI2, a positive terminal TP and a negative terminal TN, and comprises four branches. The two branches connected to the terminal TN comprise respectively two n-channel MOS transistors M3 and M4. The terminal TN is then used as ground potential reference GND. In FIG. 3 the transistor M3 is equipped with a source terminal connected to its body terminal and to the terminal TN, a drain terminal connected to the terminal TI2 and a control terminal connected to the terminal TI1. The transistor M4 is equipped with a source terminal connected to its body terminal and to the terminal TN, a drain terminal connected to the terminal TI1 and a control terminal connected to the terminal TI2. In the circuit of FIG. 3 the other two branches of the rectifier are provided by means of two diodes D3, D4 connected respectively between the terminals TI2, TI1 and TP. The use of the MOS transistors in place of the conventional diodes permits limiting the voltage drop between the terminal TN and the terminal TI2 to 300mV or 400mV provided the transistor M3 is appropriately sized. The maximum voltage drop corresponds to the product of the RDS of the energized transistor M3 and the maximum current supplied by the bridge. The 400mV or 300mV missing from the 700mV constitute a sufficient margin to ensure insulation. Such a polarity of the substrate also permits correct operation of the switch in accordance with the present invention. As mentioned above, an application of the present invention is represented by electronic cards. FIG. 1 shows such an electronic card indicated by SC. The card SC comprises a resonant circuit consisting e.g. of parallel connection of a coil CC and a capacitor C1 between a first node N1 and a second node N2 for reception and/or transmission of signals and an electrical network designed to vary at least one resonance parameter, e.g. resonance frequency or the merit factor of the resonant circuit if coupled thereto. Variation of the resonance frequency can serve as mentioned above for "transmission" of data to the station BS or reception of data from different stations operating at different frequencies. Coupling between the resonant circuit and the network can be done advantageously on command through a switch in accordance with the present invention. Indeed, the switch will switch signals received with variable polarity and not readily predictable amplitude, generally a few volts. In FIG. 1 the electrical network consists simply of a capacitor C2 which is connected on command in parallel with the resonant circuit through the switch SW. Specifically a first terminal T1 of the capacitor C1 is connected to the node N1 while a second terminal T2 of the capacitor C1 is connected to the node N2. As known, to perform its function the card SC needs other circuitry indicated only schematically in FIG. 1. The heart of the card SC consists of the logical network LN which is as known generally made up essentially of a processor and RAM and/or ROM and/or EEPROM and/or FLASH memories. The network LN generally receives at input at least one clock signal CLK and a power signal PS. It can then further receive an input data signal IS and/or generate a data output signal OS. These signals are generated by additional circuitry present in the card. Normally this circuitry comprises at least one rectifier BR, e.g. like that of FIG. 3 which operates well in combination with the switch of FIG. 2. The terminals TI1 and TI2 are connected in parallel with the resonant circuit. The terminal TN of the rectifier BR operates as ground potential reference GND while the terminal TP of the rectifier BR can operate as potential reference VR . In reality it is appropriate to use, as shown in FIG. 1, a capacitor C3 downstream of the rectifier BR in order that the potential reference VR be sufficiently steady in time. For reliable operation of the logical network LN however a steady power supply potential reference not dependent upon the amplitude of the signal at the ends of the resonant circuit is necessary. For this purpose, in FIG. 1 is provided a regulator REG hooked to ground GND, powered by the reference VR and having an output operating as power supply potential reference VDD . The group consisting of the rectifier BR and the capacitor C3 constitutes an unstabilized power supply while the group consisting of the rectifier BR, the capacitor C3 and the regulator REG constitutes a stabilized power supply. As seen, even the switch SW needs power supply and this can be taken advantageously from one of these feeders. Despite the fact that the potential VR is unstabilized, the fact that it is higher - sometimes much higher - than the potential VDD makes it preferable as a power source. Just because of the unpredictability of the value of the potential VR it is advantageous to connect, e.g. in parallel with the capacitor C3 a voltage limiting circuit, termed "clamp", not shown in FIG. 1. This circuit could advantageously be made up of an npn bipolar transistor having a resistor connected between its base and its emitter and having the series connection of a Zener diode and an npn bipolar transistor diode-connected between the collector and its base. Such a circuit has the advantage of having a limit value independent of the current flowing in the bridge BR As mentioned above the circuits of FIG. 2 and FIG. 4 lend themselves particularly well to use in an electronic card. Indeed, the data signal OS generated by the logical network LN is a logical signal having logical levels linked to the potentials of the references VDD and GND. The shifter LS powered by the reference VR permits obtaining a logical signal having logical levels linked to the amplitude of the oscillations present in the resonant circuit. This is sufficient to drive as desired the transistors of the switch of FIG. 4. For the circuit of FIG. 2 the voltage duplicator in combination with the output inverter completes raising of the high logic level. In this manner the signal OS can be sent directly to the switch SW to obtain when desired the transmission effect. The signal CLK can be taken from the potential present at the terminal TI1 of the rectifier BR. The signal IS can be taken from the potential at the terminal TP of the rectifier BR through a peak detector. This detector can consist e.g. of the series connection between the terminal TP and the reference GND of a resistor R4 and a capacitor C4 and a differential amplifier AMP having its input connected to the ends of the resistor R4 and its output connected to the output of the peak detector. It would be advantageous to be able to integrate all the circuitry of the card SC in a single integrated circuit or at least in a few integrated circuits. The greatest difficulties of integration consist of the capacitors C1, C2, C3 but especially the coil CC. If at least the switch SW and the rectifier BR are integrated on the same integrated circuit it is appropriate, as mentioned above, to connect the terminal TN to its substrate which then acts as ground potential reference GND for the rest of the circuitry of the card SC.

Claims: An electronic card comprising: a resonance circuit (CC, C1) for reception and/or transmission of signals and having first and second terminals (N1, N2); an electrical network (C2) having first and second terminals (T1, T2); a switching circuit for connecting said electrical network (C2) to said resonant circuit (CC, C1), characterised in that said switching circuit comprises: a first MOS transistor (M1) switchably connecting said first terminal (T1) of said electrical network (C2) to said first terminal (N1) of said resonant circuit (CC, C1); and a second MOS transistor (M2) switchably connecting said second terminal (T2) of said electrical network (C2) to said second terminal (N2) of said resonant circuit (CC, C1). Electronic card in accordance with claim 1 and characterized in that said first (M1) and second (M2) MOS transistors have a channel of the same type of conductivity and in particular N conductivity and have their control terminals coupled together. Electronic card in accordance with claim 1 or 2 and comprising additionally a drive network designed to drive the control terminals of said first (M1) and second (M2) MOS transistors and powered in particular by the power supply reference (VR) of said first and/or second electrical network. Electronic card in accordance with claim 3 and characterized in that said drive network comprises a voltage booster circuit (P1,CE,D1) designed to power at least its output stage (P2). Electronic card in accordance with claim 1 and characterized in that it comprises in addition to said first (M1A) and second (M2A) transistors a third (M1B) and a fourth (M2B) MOS transistors having main conduction paths respectively coupled between a third terminal (T1B) of a third electrical network (C2B) essentially equal to said first electrical network (C2A) and said first terminal (N1) of said resonant circuit (CC, C1) and between a fourth terminal (T2B) of said third electrical network (C2B) and said second terminal (N2) of said resonant circuit (CC, C1). Electronic card in accordance with claim 5 and characterized in that said first (M1A) and fourth (M2B) transistors are p-channel and have their control terminals coupled together and said second (M2A) and third (M1B) transistors are n-channel and have their control terminals coupled together. Electronic card in accordance with claim 5 or 6 and characterized in that it comprises additionally a drive network designed to drive the control terminals of said first (M1A), second (M2A), third (M1B) and fourth (M2B) transistors and powered in particular by the power supply reference (VR) of said second electrical network. Electronic card in accordance with claim 7 and characterized in that said drive network generates two mutually inverted drive signals (U,UN). Electronic card in accordance with the above claims and characterized in that said transistors (M1A,M2A,M1B,M2B) are connected in such a manner as to not allow conduction in said first network (C2A) and/or third (C2B) network through their parasitic junction. Electronic card in accordance with claim 1 and characterized in that said first network and/or said third network consists of a capacitor (C2) in which said resonant circuit consists of the parallel connection between a first node (N1) and a second node (N2) of a capacitor (C1) and an inductor (CC). Electronic card in accordance with claim 1 and characterized in that in that said switching circuit receives power from a power supply circuit (BR,C3) coupled in parallel to said resonant circuit (CC,C1). Electronic card in accordance with claim 11 and characterized in that said power supply circuit comprises a bridge rectifier (BR) having two indifferent terminals (TI1,TI2), a positive terminal (TP) and a negative terminal (TN) with the two branches connected to its negative terminal (TN) comprising each an MOS transistor (M3,M4) and in which said two indifferent terminals (TI1,TI2) are coupled respectively to said two nodes (N1,N2) and in which said negative terminal (TN) is coupled to the substrate of said integrated circuit.

Inventors: BARDELLI ROBERTO, RICOTTI GIULIO, ROSSI DOMENICO, BARDELLI, ROBERTO, RICOTTI, GIULIO, ROSSI, DOMENICO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: H03K17
IPC codes: H03K17