Timing circuit

Abstract: The current invention provides a timer circuit for timing a plurality of time periods, having: a timing pulse input for receiving timing pulses; a set of state outputs being at a set of logic states, each logic state taking one of two logic values, the logic values of the set of logic states changing at each timing pulse; a plurality of timing outputs, each providing a signal at the expiry of a predetermined time period; and a resetting signal for resetting the timing circuit and for defining an initial set of logic states. The set of logic states follows a first sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within each set are at a first logic value (1) except at least one logic state, which is at a second logic value (0), different state outputs carrying the excepted state(s) in each of the sets of logic values within the first sequence of sets of logic values. A first timing signal generator generates a first timing signal to indicate the expiry of a first time period by detecting the first occurrence of the second logic value (0) in a subset of the set of logic states at the set of state outputs; a second timing signal generator generates a second timing signal to indicate the expiry of a second time period by detecting a predetermined combination of logic values at the set of state outputs.

Description: The present invention concerns timer circuits for timing a plurality of time periods. While the invention may be used in many applications, it has particular advantages when used in integrated circuit memory devices, notably those of the flash variety, having single transistor memory cells, each with a floating gate. Figure 1 shows circuitry for controlling a flash memory cell. The memory cell 2 comprises a single transistor 4, having a control gate CG and a floating gate FG, a source S and a drain D. The source S is connected to a node 10, itself connected to a source voltage switch 14, which permits the source S to be connected either to a ground voltage V GND , or to a programming voltage, V PP , according to a signal applied to an erase control input 28. The drain D of transistor 4 is connected to a bitline 6, itself connected to a bitline switch 31, which permits bitline 6 to be connected either to a sense amplifier circuit 29 or to a programmable load circuit 32, according to a select control signal applied to a select input 21. The programmable load circuit 32 receives as input, load control signals 38. The sense amplifier circuit 29 provides an output to a data line 23. The control gate of transistor 4 is connected via word line 8 to a gate voltage switch 12. This gate voltage switch permits the control gate CG to be connected to the ground voltage V GND , the programming voltage V PP or a supply voltage V' CC , according to control signals applied to program and erase control inputs 30, 28 respectively. V' CC is 5V for a memory device operating with a 5V supply, and about 5V for a memory device operating with a 3V supply. The flash memory cell 2 has three modes of operation. In program mode, the floating gate FG is negatively charged, the transistor 4 becomes less conductive, and a 0 is considered to be written to the cell. In erase mode, the floating gate FG is discharged, the transistor 4 becomes more conductive. A 1 is then considered to have been written to the cell. In read mode, suitable voltages are applied to transistor 4 such that a relatively low current will flow when a 0 is written into the cell, and a relatively high current will flow when a 1 is written into the cell. The contents of each memory cell may thus be determined. To select program mode, the program control signal 30 is set, causing the word line 8 and the control gate CG to be connected to the program voltage V PP . The erase control signal 28 is not set, and the source S of transistor 4 is connected to the ground voltage V GND by source voltage switch 14. The select control signal 21 is set so as to connect the bitline 6 to the programmable load circuit 32. The load control signals 38 are set to place the drain D of transistor 4 at about 5V. This combination of bias voltages on transistor 4 causes the floating gate FG to become negatively charged. This changes the apparent threshold of the transistor, making it less conductive for a given control gate voltage. The charge accumulates during the time that the program control signal is set. A common method of achieving programming is to apply several pulses to the program control signal (program pulses), with a verify step in between each of them, to detect when the cell in question has been properly programmed. In the erase mode, the erase control signal 28 is set to connect the control gate CG of the transistor 4 to the ground voltage V GND , by means of gate voltage switch 12 and wordline 8. The source S is connected to the program voltage V PP by the source voltage switch 14 as controlled by the erase control signal 28. The select control signal 21 is set to control the bitline switch 31 to allow the bitline 6 to float at around 1V. With these bias conditions, the charge on the floating gate FG reduces, the amount of charge removed depending on the duration of the erase control signal. This reduction in stored charge makes the cell more conductive. After a sufficient time, a 1 is written into the cell. A common way of achieving this erasure is to apply several pulses on the erase signal 28 (erase pulses), with a verify signal between each one to determine whether the erase is complete. In read mode, neither the erase control signal 28 nor the program control signal 30 are active. This causes the control gate CG and the wordline 8 to be connected to the supply voltage V' CC by the gate voltage switch 12. The source of the transistor 4 is connected to ground V GND by the source voltage switch 14. Bitline 6 is connected to the sense amplifier circuit 29, which biases the bitline 6 to around 1V. The amount of current flowing through the transistor 4 depends on its programmed or erased state. An erased cell will allow substantially more current to flow than a programmed cell. The sense amplifier 29 detects the level of the current through transistor 4, and places the bitline 23 in a logic state indicative of the state of the cell 2. In a flash memory device, many cells such as that shown in figure 1 are connected together, and provided with addressing circuitry. Each cell, however, functions as described above, in its three possible states. Within such circuits, it is necessary to measure several different time delays, each with equal accuracy. In the example of a flash EPROM memory circuit, very short periods of the order of 10µs may be needed for timing program pulses, whereas much longer periods, of the order of 10ms may be needed for timing erase pulses. A known circuit for timing both long and short time periods uses a linear feedback shift register (LFSR) in an autonomous mode, whereby the LFSR has no data inputs, and is supplied only with a clock signal. A LFSR is a shift register composed of a series of storage elements, such as D-type latches, wherein the outputs of certain latches are combined in a linear manner, and the resulting signal is applied to the input of a first latch. The circuit is very similar to a normal shift register, except that a certain 'linear' function is introduced by including a linear element, for example an exclusive-OR or exclusive-NOR gate, in the circuit. Such gates pass or invert the output (Q) of one latch to the input (D) of the next depending on the output (Q) of another of the latches. Linear feedback shift registers are discussed in "Digital Systems Testing and Testable Design", by Abramovici, Breuer and Friedman, Computer Science Press, 1990; "Shift Register Sequences", by S.W. Golomb, Aegean Park Press, 1982; and "Error Correcting Codes", Peterson & Weldon, MIT Press, 1972. Typically, such LFSR timers are made from a loop comprising a series of latches, supplied with a clock signal input and no data input. This is called the autonomous mode of operation. By supplying a clock signal of sufficiently high frequency, for example 1MHz, and detecting a certain combination of outputs of the latches, a range of periods such as described may be timed. With a 1MHz clock signal, 14 series latches are required to time the 10,000 clock cycles which constitute 10ms. Figure 2 shows an LFSR timer comprising a number of digital storage devices, D0 - D4 connected in a loop. Each digital storage device, which is typically a D-type latch, has a data input D, an output Q, an inverted output Q , a clock input CK and a reset input R. Clock inputs CK and reset inputs R of the D-type latches are respectively connected together and receive timing pulse T and reset R signals respectively from external circuitry. The timing pulse signal T preferably consists of a series of pulses of constant frequency and width. Other types of pulses could, however, be used. The data input D of each D-type latch is connected to the output Q of the respectively preceding D-type latch, the data input of the first latch D0 being connected to the output of the last latch D4 by a feedback path 40, with the exception of the data input of D-type latch D2, which is connected to the output 42 of exclusive-NOR gate 44, which has two inputs 46, 48. The first input 46 is connected to the output Q1 of D-type latch D1, and the second input 48 is connected to the feedback path 40. The inverted and non-inverted outputs of D-type latch D0 are designated Q0 , Q0 respectively, and outputs of the other D-type latches are similarly designated. The truth table of an exclusive-NOR gate with inputs A, B and output N is shown in table 1. A B N 0 0 1 0 1 0 1 0 0 1 1 1. The exclusive-NOR gate 44 therefore outputs the inverse of one input (B; 46) when the other (A; 48) is at 0, and passes the first input (B; 46) when the other (A; 48) is at 1. Comparable functionality is obtained from including an exclusive-OR gate in the circuit instead of an exclusive-NOR. There may be any number of D-type latches in the loop. By using the exclusive NOR gate in the loop, the data input to D-type latch D2 is the inverse of the output of D-type latch D1 whenever the output of D-type latch D4 is zero. Applying a positive pulse to the reset input R to each of the D-type latches causes each of the D-type latches to be placed in the 0 output state. Table 2 shows the sequence of outputs Q4 to Q0 from the D-type latches of the circuit of figure 2, during the clock cycles following a reset to zero of the D-type latches. For each clock cycle where a 0 is present at the output of Q4, the output of Q1 in the same cycle is inverted to become the output of Q2 in the following cycle. The sequence follows through all possible combinations, except '11111', before returning to its original state '00000', 31 clock cycles later, and resuming the same sequence. The state '11111' is excluded, as no change of state in the LFSR would occur with clocking. The LFSR would be stuck at this value. The circuit of figure 2 is thus a special case of LFSR, known as a maximal length shift register, at it cycles though all possible states, being (2 n -1) in number, where n is the number of D-type latches. The positioning of the exclusive-NOR gate 44 in the circuit is critical to achieving a maximal length sequence, in this case 31 cycles. Were a loop of six D-type latches used, a series of 63 different combinations could have been produced, if the exclusive-NOR gate is placed correctly. Other loop sizes could also be chosen, according to the number of clock cycles required to be timed. For the example described above, to time 10ms with a 1MHz clock, 14 latches would be required, giving a maximal length of 16,383 cycles. If an exclusive-OR gate were used instead of the exclusive-NOR, then for each clock cycle where a 1 is present at the output of Q4, the output of Q1 in the same cycle would be inverted to become the output of Q2 in the following cycle. The reset inputs to the D-type latches D0 to D4 would also have to be arranged so that they reset to the 1 state upon application of the signal R, as the state '00000' is excluded, for the reason discussed above for the '11111' state in the case of an exclusive-NOR gate. LFSR timers must detect a certain combination of outputs to determine the expiry of the required time period. With reference to table 2, if the combination 00111 is detected, 6 clock cycles have elapsed since the reset to zero. Similarly, a combination of 01111 represents 20 clock cycles after the reset to zero. By providing a number of detectors, a number of periods may be timed, which can run concurrently from the reset to zero time. Equally, the time elapsed between two detections may be used as a measure of a period of time commencing after the reset to zero, or the counter may be reset to zero after each detection to time independent periods. Such detection requires the use of an n-bit detector for each timing period. A detector may simply be an n-input NAND gate, suitably connected. To detect the occurrence of '00111', a 5-input NAND is required, whose inputs are Q0, Q1, Q2, Q3 , Q4 . In the example given above, where 14 series latches are required to time both 10ms and 10µs, two 14-input gates would be required, which would consume a large amount of surface area in an integrated circuit implementation. A known method enables such LFSR circuits to measure very short periods of time, using simple one bit detectors, by including logic which effectively shorts out the linear (exclusive-OR or exclusive-NOR) function. In figure 3, pass gates 50, 52 are included between the input to D-type latch D2 and: the output 42 of the exclusive NOR gate 44; and the output Q of the D-type latch D1, respectively. The passgates are supplied with command signal SHORT and its inverse, SHORT . The signal SHORT indicates that a short time delay is to be measured. A short delay may be defined as a time period lasting for a number of clock cycles which is less than the number of latches in the circuit. A time period lasting longer than this will be referred to as a 'long' period. The pass gates 50, 52 serve to connect the data input D of D-type latch D2 to the output of the exclusive-NOR gate 44 when SHORT is low, and to connect the data input D of the D-type latch D2 to the output of D-type latch D1 when SHORT is high. An OR gate 53 is included in the feedback path 40, having a first input connected to the output of D4, and a second input receiving a signal RR, which is high at and following the application of reset signal R. Signal RR is reset to a low state at the first clock signal after the reset signal R becomes inactive. Figure 4 shows an alternative circuit for achieving the same result. The circuit is similar to that of figure 3 and identical features have identical reference labels. The reset and timing pulse signals R, T and the associated inputs to each of the latches D0 to D4 are omitted from the diagram for clarity, but should be understood as being included in the circuit as described above. The output 42 of the exclusive NOR gate 44 is connected to an input of NAND gate 54. The output Q1 of D-type latch D1 is connected to an input of NAND gate 56. The outputs of gates 54, 56 are connected to inputs of a further NAND gate, 58. A second input of gate 56 is connected to the signal SHORT; an inverter 60 receives SHORT on an input, and has its output connected to a second input of gate 54. When the signal SHORT is high, gate 56 is enabled, permitting the signal Q1 to be transmitted to the input D of D-type latch D2, via gate 58. The output 42 of the exclusive NOR gate 44 is not transmitted, as gate 54 is held in a high state by a low on its second input. Conversely, when SHORT is low, the output 42 of gate 44 is transmitted via gate 58 to D2, whereas the output Q1 of latch D1 is not transmitted, the gate 56 being held at a high state by the low on its second input. Thus, by setting SHORT high, the exclusive-NOR gate is excluded from the circuit, removing the linear element and causing the circuits of figures 3 and 4 to function as a normal shift register which may be used for timing very short delays. By setting the contents of the register to 00001, and detecting the transition 0 to 1 at Q4, when the LFSR holds 10000, a period of four cycles may be measured, using a single bit detector. The contents of the LFSR may be set to 00001 by applying an active reset pulse R to the reset inputs of the D-type latches, and an active signal RR to the second input of OR gate 53. By setting SHORT low, periods of up to 31 cycles may be measured as described above. This method has the advantage that short time delays need only a single bit detection circuit, but have the drawback that the extra logic circuitry required for operating the two different modes occupies a relatively large surface area. Further, using the circuit in the short delay mode, only short periods may be measured. If both a short delay and a long delay need to be measured concurrently, beginning at the same reset, this circuit cannot be used. This solution applies to cases where several short timings need to be made, as the additional logic circuitry is made up for in the savings made by using smaller decoders. The object of the current invention is to provide a timing circuit for timing a plurality of time periods without adding to the complexity of the timer circuit. The article "More shift registers - ring counters and maximum-length sequence generators"; Wireless World, Vol. 83, No 1503, November 1977 disclosed a ring counter circuit. The ring counter is preset so that all the stages are set to logic zero, except for the first stage which is set to logic one. When a clock signal is applied to the counter the logic one propagates through each stage in turn. Additional logic circuitry is provided for detecting the presence of additional logic one's. US-A-4,839,841 discloses a multiple digital event generator for producing a signal which is indicative that a particular event has occurred. A linear feedback shift register is used to produce an arbitary sequence of non-repeating binary numbers of n bits in length. These numbers are input to one or more digital comparators, each comparator having n inputs, so as to cause the comparator to produce an output when a certain number occurs. According to one aspect of the present invention, there is provided a timing circuit for timing a plurality of time periods, having: a timing pulse input for receiving timing pulses; a set of state outputs each providing a logic state at one of two logic values, the logic values of the set of logic states changing at each timing pulse; a plurality of timing outputs, each providing a signal at the expiry of a predetermined time period; and a resetting signal for resetting the timing circuit and for defining an initial set of logic values, wherein the set of logic states follows a first and a second sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within the initial set and within each set of logic values of the first sequence are at a first logic value except at least one logic state, which is at a second logic value, different state outputs providing the state at the second logic value in each of the sets of logic values within the first sequence of sets of logic values; said timing circuit further comprising a first timing signal generator arranged to receive logic states from a predetermined subset of said set of state outputs for generating a first timing signal at one of said timing outputs to indicate the expiry of a first time period by detecting the first occurrence of the second logic value(s) at said predetermined subset of said state outputs, during the first sequence of sets of logic values; and a second timing signal generator arranged to receive logic states from said set of state outputs for generating a second timing signal at another of said timing outputs to indicate the expiry of a second time period by detecting when each of the logic states are in a predetermined state, during the second sequence of sets of logic values, wherein each timing signal generator is further connected to receive an enable signal to enable the timing signal generator, the timing signal being produced only when the corresponding enable signal is active. In a particular embodiment of the invention, the subset of the set of logic states at the set of state outputs comprises one predetermined state output. Timing circuits according to the invention may advantageously be integrated into a semiconductor memory device, the timing outputs signalling the expiry of time periods required for the programming and erasure of memory cells within the semiconductor memory device. Such an arrangement is particularly advantageous where the semiconductor memory device is a flash EPROM memory device, and the time periods are erase pulse durations and program pulse durations. Such a timing circuit is provided, which contains a loop, comprising a plurality of digital storage devices, each receiving a data input in addition to the timing pulses and the reset signal, and each providing an output which is connected to the data input of the following digital storage device, with the exception of one digital storage device, whose data input is connected to an output of a linear element, the linear element being connected so as to supply at its output a signal which has a linear relationship with a plurality of outputs of digital storage devices in the loop; the outputs comprising the state outputs of the timing circuit. The linear element may supply at its output a signal which has an exclusive-OR or exclusive-NOR logical relationship with the plurality of outputs of the digital storage devices. The first sequence of sets may comprise a number of sets which is one less than the number of digital storage devices in the loop. Preferably, each digital storage device further provides an inverted output, selected outputs and inverted outputs of the digital storage devices being connected to the first and second timing signal generators. The digital storage devices may be D-type latches. According to a second aspect of the present invention there is provided a method for timing a plurality of time periods, comprising the steps of: defining an initial set of logic values setting a circuit including a plurality of digital storage devices, the circuit having a set of state outputs, each digital storage device providing a logic state at one of two logic values, to the initial set of logic values, providing timing pulses, the logic values of the set of logic states changing at each timing pulse; providing a timing signal at the expiry of each predetermined time period; comprising the steps of applying timing pulses to the circuit to cause the set of logic states to follow a first and a second sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within the initial set and within each set of logic values of the first sequence are at a first logic value except at least one logic value, which is at a second logic value, different state outputs providing the state at the second logic value in each of the sets of logic values within the first sequence of sets of logic values; providing an enabling signal to a first timing signal generator; generating a first timing signal to indicate the expiry of a first time period in response to the detection of the first occurrence of the second logic value in a predetermined subset of the set of logic states, during the first sequence of sets of logic values; providing an enabling signal to a second timing signal generator; generating a second timing signal to indicate the expiry of a second time period in response to the detection of when each of the logic states is in a predetermined state, during the second sequence of sets of logic values. The method of timing may particularly be applied to timing erase and programming pulses in a semiconductor memory device, comprising the steps of: enabling a first timing signal generator; supplying a reset signal at the time that a programming pulse is to start; applying the reset signal to a circuit including a plurality of digital storage devices, having a set of state outputs at a set of logic states, each taking one of two logic values, to set the circuit to an initial set of logic values, being a first set of a first sequence of sets of logic values, each set of logic values within such first sequence of sets comprising all logic states at a first logic value, except at least one logic state, which is at a second logic value; applying a programming signal to memory cells of the semiconductor memory device to be programmed; applying timing pulses to the circuit to cause the set of logic states to change to subsequent sets of logic values within the first sequence of sets of logic values; detecting the first occurrence of the second logic value in a predetermined subset of the set of logic states, during the first sequence of sets of logic values; indicating the expiry of a first time period, by the provision of a first timing signal from the first timing signal generator; removing the programming signal from the cells of the semiconductor memory device to be programmed; enabling a second timing signal generator; supplying a reset signal at the time that an erase pulse is to start; applying the reset signal to the circuit including a plurality of digital storage devices to place them in the known set of states; applying an erase signal to memory cells within the semiconductor memory device to be erased; applying timing pulses to the circuit to cause the set of logic states to change to subsequent sets of logic values within and beyond the first sequence of sets of logic values; detecting the occurrence of a certain set of logic values, not within the first sequence of sets of logic values, at the set of state outputs; indicating the expiry of a second time period by the provision of a second timing signal by the second timing signal generator; removing the erase signal from the memory cells of the semiconductor memory device to be erased. The current invention provides a circuit which may time several different periods consecutively or concurrently, chosen from a number of periods, both long and short, which are continually available, the periods available being easily changeable. Particular embodiments of the invention will be described hereinafter, by way of example, in conjunction with the accompanying diagrams, wherein: Figure 1 shows a circuit diagram of a flash memory circuit; Figure 2 shows a circuit diagram of a linear feedback shift register of the prior art; Figure 3 shows a linear feedback shift register of the prior art, operable in both short and long delay modes; Figure 4 shows another linear feedback shift register of the prior art, operable in both short and long delay modes; Figure 5 shows a circuit according to the present invention; Figure 6 shows detection circuitry according to the present invention; and Figures 7 and 8 show further detection circuitry according to the present invention. Provided that they are suitably designed, and initialised into an appropriate state, LFSRs may have the characteristic that they operate in a manner similar to that of a normal shift register, over a limited number of clock cycles. Table 2 lists the outputs Q0 to Q4 for the latches D0 to D4 for a full cycle of a maximal length, 5 stage, LFSR such as that shown in figure 2. Referring to this table, during the time from 16 clock cycles after the reset to zero until 20 cycles after the reset to zero, the LFSR acts as a normal shift register, rotating 11110 until 01111 is achieved. If means be provided for setting all of the D-type latches to any chosen state, use may be made of this property to time short delays. Figure 5 shows an LFSR circuit according to the invention. Features similar to those of figure 2 have similar reference labels. Each of the D-type latches D0 to D4 has two reset inputs, R 0 , R 1 . The output of each latch is set to 0 when a positive pulse is applied to the R 0 input, and the output of each latch is set to 1 when a positive pulse is applied to the R 1 input. The reset input signal R is connected to the input R 1 of D-type latches D1 to D4, and to the R 0 input of the D-type latch D0. By applying a positive pulse on the reset signal R, the outputs of the latches are set to '11110', and by applying a clock signal T, the LFSR will go through the sequence of states listed in table 3. Table 3 shows the outputs of the LFSR of figure 5 during a certain number of clock cycles after it has been initialised to contain 11110. The contents rotate left in the same manner as a normal shift register, until the LFSR contains 01111, four clock cycles later. Afterwards, the LFSR continues on its specific sequence. By detecting a 0 at the output Q3, a period of 3 cycles after reset may be timed. Longer periods may be timed by detecting a specific combination of outputs in the sequence of the LFSR used. With a 5 bit LFSR, a maximum of 31 periods may be measured, but this will depend on the particular design of the LFSR used: many possible designs are non-exhaustive, and cycle through sequences of less than the maximal number (2 n -1) of states. For the LFSR of figure 5, and with reference to table 3, a long period of, for example, 17 clock cycles may be timed by detecting 01100 in the outputs of the LFSR. An n-bit detector is required to detect the end of long periods. Thus, any short delays may be timed with a single bit detector, while long periods require a multiple bit detector. Figure 6 shows detection circuitry connectable to the LFSR of figure 5 to detect the expiry of the required delays. Five detectors 61, 62, 64, 66, 68, have inputs connected to selected ones of the inverted and non-inverted outputs of the LFSR. Each detector has an enable input EN and an output P1 - P5. An enable signal generator circuit 70 is commanded by signals 72 from external circuitry to generate enable signals S1 - S5, connected to the enable inputs EN of detectors 61, 62, 64, 66, 68, respectively. Each detector supplies an output P1, P2, P3, P4, P5, respectively. Each detector is arranged to detect a certain combination of LFSR outputs, by the combination of inverted and non-inverted LFSR outputs Q , Q applied thereto. Selection of which enable signal is active thus selects which combination of inverted and non-inverted outputs will be detected, and hence which period is timed. The enable signal should be active from the time that the LFSR is reset, and begins timing. In the example, when all inputs Q, Q to the enabled detector are high, the detector supplies an output P indicating that the selected time period has elapsed. Detector 61 produces an output signal P1 when its input Q1 is 1, i.e. one cycle after reset, or after an elapsed period of 1 µs, with a 1MHz clock. Similarly, detector 62 produces an output signal P2 when its input Q3 is 1, i.e. three cycles after reset, or after an clapsed period of 3µs; detector 64 produces an output signal P3 when its input Q 4 is 1, i.e. four cycles after reset, or after an elapsed period of 4µs; detector 66 produces an output signal P4 when its inputs Q0 , Q1 , Q2 , Q3 , Q4 are 11111, i.e. twenty-three cycles after reset, or after an elapsed period of 23µs; detector 68 produces an output signal P5 when its inputs Q0 , Q1, Q2 , Q3 , Q4 are 11111, i.e. eight cycles after reset, or after an elapsed period of 8µs. Thus, timing periods up to a number of clock cycles equal to one less than the number of digital storage elements requires a short period (single bit) detector, and other (long) periods require an all bit detector. The periods timed may easily be defined and changed by selecting different inverted and non-inverted outputs Q , Q connected to each of the short and long period detectors. Detectors 61, 62, 64 are short period detectors, and each receive only one inverted LFSR output Q1 , Q3 , Q4 , respectively. They detect the transition of the connected D-type latch output Q from 0 to 1, to time periods of 1, 3 and 4 clock cycles respectively. The output P1, P2, P3 of each short period detector will produce an output upon the expiry of the relevant time period, provided that the relevant enable input EN is activated by the associated enable signal S1, S2, S3. It is possible to time concurrent periods, by placing more than one enable signal in its active state. In this case, care must be taken to ensure that the short period detectors only respond to the first transition on their input. For example, and with reference to table 2, if both the 3µs period detector 62 and the 8µs period detector 68 are enabled, then the short period detector 62 must only respond to Q3=0 at 3 cycles after reset, and not those at 6 and 8 cycles after reset. This may be achieved by simply including a latch either before or within the short period detectors. As shown in figure 7, a short period detector 61, 62, 64 may be a two input NAND gate 74. The application of EN=1 (an active enable signal) and Q =1 (which, when high, indicates the expiry of the timed period) on the inputs supplies a low output P for a single cycle. This low pulse may be applied to a latch or a state machine or any other memory or control circuitry required according to the particular application. Detectors 66, 68 detect long periods. They each receive an output Q or Q from each of the D-type latches D0 to D4. These outputs may be inverted Q or non-inverted Q according to the combination to be detected. When all of the inputs Q, Q to one particular long delay detector are high, and the enable input EN is activated by the relevant enable signal S4, S5, the output P4, P5 of that particular long delay detector changes state to indicate the expiry of the timed delay. Figure 8 shows a possible implementation of such detectors. A multiple input NAND gate 76 receives the outputs Q, Q from the D-type latches D0 to D4, and supplies an output signal P. This NAND gate has six inputs in the example, and this gate is more complex and much larger than the two-input NAND gate used for the short period detector. The enable signal EN is active as described for the short period detector. The output P is normally high, going low for one clock period when the timed period has elapsed. The elapsing of the timed period corresponds to the instant when all inputs Q, Q are high. The number of inputs required to the NAND gate 76 is equal to the number of storage elements in the LFSR, plus one for the enable signal EN. To provide a long period detector for a 14 stage LFSR would require a fifteen-input NAND gate, which is very large. According to the invention, therefore, both a 10µs and a 10ms period may be timed using an LFSR containing 14 digital storage elements, and requiring one fourteen-bit decoder and one one-bit decoder. The benefits of being able to detect the expiry of short periods by detecting a transition on only one LFSR output thus saves a large amount of circuit area when the circuit is implemented as an integrated circuit. A saving in circuit complexity is also made. As, in practice, D-type latches are systematically provided with both reset-to-zero and reset-to-one inputs, the invention fulfils its object by providing a circuit for detecting both short and long time delays using a linear feedback shift register, with no additional circuitry, and minimum sized detection circuitry for short delays, representing a significant saving in surface area over previously known designs, when implemented as an integrated circuit. Although the invention has been described with reference to a number of particular embodiments, it will be understood that the invention applies to any LFSR, not necessarily having a maximal length sequence, and including any appropriate linear element. Cycles after Reset Q4 Q3 Q2 Q1 Q0 0 0 0 0 0 0 1 0 0 1 0 0 2 0 1 1 0 0 3 1 1 1 0 0 4 1 1 0 0 1 5 1 0 0 1 1 6 0 0 1 1 1 7 0 1 0 1 0 8 1 0 0 0 0 9 0 0 0 0 1 10 0 0 1 1 0 11 0 1 0 0 0 12 1 0 1 0 0 13 0 1 0 0 1 14 1 0 1 1 0 15 0 1 1 0 1 16 1 1 1 1 0 17 1 1 1 0 1 18 1 1 0 1 1 19 1 0 1 1 1 20 0 1 1 1 1 21 1 1 0 1 0 22 1 0 1 0 1 23 0 1 0 1 1 24 1 0 0 1 0 25 0 0 1 0 1 26 0 1 1 1 0 27 1 1 0 0 0 28 1 0 0 0 1 29 0 0 0 1 1 30 0 0 0 1 0 Cycles after Reset Q4 Q3 Q2 Q1 Q0 0 1 1 1 1 0 1 1 1 1 0 1 2 1 1 0 1 1 3 1 0 1 1 1 4 0 1 1 1 1 5 1 1 0 1 0 6 1 0 1 0 1 7 0 1 0 1 1 8 1 0 0 1 0 9 0 0 1 0 1 10 0 1 1 1 0 11 1 1 0 0 0 12 1 0 0 0 1 13 0 0 0 1 1 14 0 0 0 1 0 15 0 0 0 0 0 16 0 0 1 0 0 17 0 1 1 0 0 18 1 1 1 0 0 19 1 1 0 0 1 20 1 0 0 1 1 21 0 0 1 1 1 22 0 1 0 1 0 23 1 0 0 0 0 24 0 0 0 0 1 25 0 0 1 1 0 26 0 1 0 0 0 27 1 0 1 0 0 28 0 1 0 0 1 29 1 0 1 1 0 30 0 1 1 0 1

Claims: A timing circuit for timing a plurality of time periods, having: a timing pulse input (CK) for receiving timing pulses; a set of state outputs (Q) each providing a logic state at one of two logic values (0,1), the logic values of the set of logic states changing at each timing pulse; a plurality of timing outputs (P), each providing a signal at the expiry of a predetermined time period; and a resetting signal (R) for resetting the timing circuit and for defining an initial set of logic values, wherein the set of logic states follows a first and a second sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within the initial set and within each set of logic values of the first sequence are at a first logic value except at least one logic state, which is at a second logic value, different state outputs providing the state at the second logic value in each of the sets of logic values within the first sequence of sets of logic values; said timing circuit further comprising a first timing signal generator (61) arranged to receive logic states from a predetermined subset of said set of state outputs for generating a first timing signal (P1) at one of said timing outputs to indicate the expiry of a first time period by detecting the first occurrence of the second logic value(s) at said predetermined subset of said state outputs (Q), during the first sequence of sets of logic values; and a second timing signal generator (66) arranged to receive logic states from said set of state outputs for generating a second timing signal (P4) at another of said timing outputs to indicate the expiry of a second time period by detecting when each of the logic states are in a predetermined state (Q), during the second sequence of sets of logic values, wherein each timing signal generator (61,66) is further connected to receive an enable signal (S1,S4) to enable the timing signal generator, the timing signal (P1,P4) being produced only when the corresponding enable signal is active. A timing circuit according to claim 1, further characterised in that the subset of the set of logic states at the set of state outputs comprises one predetermined state output. A timing circuit according to any preceding claim, integrated into a semiconductor memory device, the timing outputs (P1,P4) indicating the expiry of time periods required for the programming and erasure of memory cells within the semiconductor memory device. A timing circuit according to claim 3 wherein the semiconductor memory device is a flash EPROM memory device, and the time periods are erase pulse durations and programming pulse durations. A timing circuit according to claim 1 containing a loop, comprising a plurality of digital storage devices (D0-D4), each receiving a data input (D) in addition to the timing pulses (CK) and the reset signal (R), and each providing an output (Q) which is connected to the data input (D) of the following digital storage device, with the exception of one digital storage device, whose data input (D) is connected to an output (42) of a linear element (44), the linear element being connected so as to supply at its output a signal which has a logical relationship with a plurality of outputs (Q) of digital storage devices in the loop; the outputs (Q) comprising the state outputs of the timing circuit. A timing circuit according to claim 5 wherein the linear element (44) supplies at its output (42) a signal which has an exclusive-OR logical relationship with the plurality of outputs (Q1,Q4) of the digital storage devices (D1,D4). A timing circuit according to claim 5 or 6 wherein the linear element (44) supplies at its output (42) a signal which has an exclusive-NOR logical relationship with the plurality of outputs (Q1,Q4) of the digital storage devices (D1,D4). A timing circuit according to claim 5, 6 or 7, wherein the first sequence of sets comprises a number of sets which is one less than the number of digital storage devices (D0-D4) in the loop. A timing circuit according to any one of claims 5 to 8, wherein each digital storage device (D0-D4) further provides an inverted output ( Q ), selected outputs (Q) and inverted outputs ( Q ) of the digital storage devices (D0-D4) being connected to the first and second timing signal generators (61,66). A timing circuit according to any of claims 5 to 9 wherein the digital storage devices (D0-D4) are D-type latches. A timing circuit as claimed in any one of the preceding claims wherein the initial set of logic values comprises a number of consecutive states at a first logic value, followed by at least one logic state at a second logic value, the first logic state at the second logic value propagating through the set of logic values by one position per set of logic values during said number of sets of logic values in the first sequence of sets of logic values immediately following the initial set. A timing circuit as claimed in claim 11, wherein said first timing signal generator generates said first timing signal when one particular logic state attains the second logic value. A method for timing a plurality of time periods, comprising the steps of: defining an initial set of logic values setting a circuit including a plurality of digital storage devices (DO-D4), the circuit having a set of state outputs, each digital storage device providing a logic state at one of two logic values, to the initial set of logic values, providing timing pulses, the logic values of the set of logic states changing at each timing pulse; providing a timing signal at the expiry of each predetermined time period; comprising the steps of applying timing pulses (T) to the circuit to cause the set of logic states to follow a first and a second sequence of sets of logic values, beginning at the initial set of logic values, wherein all of the logic states within the initial set and within each set of logic values of the first sequence are at a first logic value except at least one logic state, which is at a second logic value, different state outputs providing the state (s) at the second logic value in each of the sets of logic values within the first sequence of sets of logic values; providing an enabling signal to a first timing signal generator (61); generating a first timing signal to indicate the expiry of a first time period in response to the detection of the first occurrence of the second logic value in a predetermined subset of the set of logic states, during the first sequence of sets of logic values; providing an enabling signal to a second timing signal generator (66) ; generating a second timing signal to indicate the expiry of a second time period in response to the detection of when each of the logic states is in a predetermined state, during the second sequence of sets of logic values. A method as claimed in claim 13 for timing erase and programming pulses in a semiconductor memory device, wherein: an erase signal is applied to memory cells within the semiconductor memory device to be erased, concurrently with the application of the resetting signal; and the erase signal is removed from the memory cells concurrently with the generation of the second timing signal. A method as claimed in claim 13 or 14 for timing programming pulses in a semiconductor memory device, wherein; a programming signal is applied to memory cells of the semiconductor memory device to be programmed, concurrently with the application of the resetting signal; and the programming signal is removed from the memory cells of the semiconductor memory, concurrently with the generation of the first timing signal. A memory device comprising: a plurality of nonvolatile memory cells having at least first and second modes of operation, the first mode of operation having a duration of a first time period and the second mode of operation having a duration of a second time period longer than the duration of the first time period, wherein the first and second time periods are timed with a timing circuit as claimed in any of claims 1-12. A method of timing operational pulses in a memory device, the method comprising the steps of: applying a first operational pulse having a duration of a first time period to memory cells in the memory device; and applying a second operational pulse having a duration of a second time period longer than the first time period to the memory cells, wherein said first and second time periods are timed according to the method of any of claims 13-15.

Inventors: BEAT ROBERT, BEAT, ROBERT
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS LIMITED
Application year: 1995
Main classification: H03K5
IPC codes: G11C16, H03K23, G11C7, G11C17, H03K5