Apparatus and method for detecting motion vectors

Abstract: A motion vector detector includes a first matching operational circuit (3) which detects correlation between an output signal of a reference block memory (1) and a search block memory (2) with integral-pel accuracy. A second matching operational circuit (4) detects correlation between an output signal of a reference block buffer memory (5) and a search block buffer memory (6) with less than or equal to half-pel accuracy. The first matching operational circuit (3) and the second matching operational circuit (4) are operated in parallel.

Description: This invention relates to motion vector detecting devices and methods which are, for example, suitable for use in picture predictive coding devices and methods. It is known to use a predictive coding system, such as the MPEG (Moving Picture Coding Experts Group) system, for encoding a picture by utilizing correlations with other frames. Fig. 1 of the accompanying drawings shows one device for carrying out such predictive coding. In Fig. 1, image data is supplied to an input terminal 101. The image data is supplied to a motion vector detecting circuit 102 and to a subtracter circuit 103. Then, an interframe motion vector is obtained in the motion vector detecting circuit 102. The motion vector thereby obtained is supplied to a motion compensation circuit 104. On the other hand, image data of a reference frame is stored in a frame memory 105. An output from the frame memory 105 is supplied to the motion compensation circuit 104. Image data from the frame memory 105 is motion-compensated in the motion compensation circuit 104 on the basis of the motion vector obtained by the motion vector detecting circuit 102. The motion-compensated image data is supplied to the subtracter circuit 103 and to an adder circuit 106. Image data of a current frame from the input terminal 101 and image data of the reference frame, which has been motion-compensated by the motion compensator circuit 104, are supplied to the subtracter circuit 103. The subtracter circuit 103 executes subtraction between the image data of the current frame and the image data of the reference frame to obtain a differential data of the successive frames. The differential data is supplied to a DCT circuit, and is DCT-converted there. Output from the DCT circuit 107 is supplied to a quantizer 108, and is quantized there. The quantizer 108 exerts its output through an output terminal 109. The differential data, DCT-converted and quantized, is supplied to a inverse quantizer 110 and to a inverse DCT circuit 111, then converted back to the original differential data, and supplied to the adder 106. The adder 106 is supplied with the image data of the inverse frame from the motion compensation circuit 104. The adder 106 adds to the reference frame image data the differential data between the reference frame and the current frame to obtain an image data of the current frame. The image data of the current frame, thus obtained, is stored in the frame memory 105 for use as a next reference frame. In this fashion, the interframe predictive coding process encodes a differential data between a current frame and a reference frame which has been motion-compensated on the basis of a motion vector. Block matching is known as a method for detecting such a motion vector to be used for interframe predictive coding process. Fig. 2 illustrates the block matching method. In Fig. 2, 121 denotes a reference frame, and 122 is a search frame. A reference block 123 is defined in the reference frame 121, and a candidate block 124 is defined in the search frame 122. The candidate block 124 of the search frame 122 is moved over a predetermined search area to determine how much it coincides with the reference block 123 of the reference frame 121. Then a candidate block 124 representing a most coincidence with the reference block is employed as a matching block, and the motion vector is obtained from the matching block. Fig. 3 shows a motion vector detector circuit conventionally available for detecting a motion vector by the block matching method. This circuit is designed to cope with detection of motion vectors at the rate of a half pixel. In Fig. 3, numeral 151 designates a reference frame memory, and 152 designates a search frame memory. The reference frame memory 151 stores data of the reference block. Data of the reference block is read out from the reference frame memory 151 and supplied to an integral-pel matching operational circuit 153. The search frame memory 152 stores pixel data of the search frame, and pixel data of a search area is supplied to the integral-pel matching operational circuit 153 to detect a motion vector there at the rate of integral pixel or pixels. Output from the integral-pel matching operational circuit 153 is supplied to buffer memory 154 and 155, and to an integrating circuit 156. The buffer memory 154 stores pixel data of the reference block. The buffer memory 155 stores pixel data of a search area surrounding the motion vector obtained at the rate of integral pixel or pixels. Outputs from the buffer memory 154 and 155 are supplied to a half-pel matching operational circuit 157 to detect a motion vector there at the rate of a half pixel. The half-pel motion vector is supplied to the integrating circuit 156. The integrating circuit 156 incorporates the integral-pel motion vector obtained by the integral-pel matching operational circuit 153 with the half-pel motion vector obtained by the half-pel matching operational circuit 157. The resulting motion vector is output from an output terminal 158. Detection of the half-pel motion vector is performed by obtaining eight search blocks by interpolation, which are positionally different by a half pixel, then matching-processing the search block and the reference block, then comparing the eight matching errors with the matching error of the one-pixel position at the center, and choosing a point with a smallest error as an optimum motion vector. That is, assume that 3x3 pixels define a block as shown in Fig. 4A. Then, as shown in Fig. 4B, search data necessary for interpolation is 5x5 pixels (s00 to s44). Made from the search data s00 to s44 are diagonally interpolative data d00 to d33, horizontally interpolative data h00 to h32 and vertically interpolative data v00 to v23. For a block of NxM, in general, data necessary for interpolation is (N+2)x(M+2). Interpolation is done by operation as shown in Fig. 5. Fig. 6 shows the center of a block for half-pel vector detection. Circles are pixels. The center point (0, 0) of Fig. 6 represents a one-pixel motion vector MV (mx, my). Matching process is executed at surrounding eight points distant by a half pixel from the center point (0, 0). When the matching error at a point (x, y) in Fig. 6 is named dist(x, y), specific matching errors are as shown in Fig. 7. From these, a block with a smallest matching error is detected, and a final motion vector is obtained. Japanese Patent Applications numbers: 04-163833 (Filing Date: 29.05.92), 05-210996 (Filing Date: 03.08.93), 06-043131 (Filing Date: 17.02.94), 06-022223 (Filing Date: 21.01.94), and US Patent US-A-5 173 771 disclose subject matter related to the MPEG technique disclosed herein. Each of the above applications and patent is owned by the present applicants and is hereby incorporated herein by reference. US patent applications corresponding to the above four Japanese patent applications have been filed. As so far discussed, in the case of obtaining a half-pel motion vector, data necessary for interpolation for a block with the dimension of N x M is (N + 2) x (M + 2). Therefore, for a block with the dimension of (16 x 16), (18 x 18) pixels must be read out from the buffer memory 155. In contrast, a one-pixel motion vector is obtained with (16 x 16 = 256) clocks in the integral-pel matching operational circuit 153. Therefore, data must be read out from the buffer memory 155 with clocks of 1.27 times the clocks ((18 x 18)/(16 x 16) = 324/256 = 1.27) for reading a picture. It is difficult to operate the buffer memory with clocks irrelevant to the data reading clocks. US Patent US-A-4 937 666 discloses a motion vector detecting device in which a motion vector is detected with fractional pel accuracy for a block from a current video signal frame in a search area of a previous frame. A first (integer precision) subcircuit obtains an estimate of the vector with integral pel accuracy and a second (fractional precision) subcircuit obtains a further estimate with fractional pel accuracy. A current frame storage memory receives and stores the current frame and supplies outputs to a previous frame storage memory and to the first subcircuit. The previous frame storage memory supplies outputs to the first subcircuit and to a search area storage memory. The second subcircuit receives inputs from the search area storage memory and a current block storage memory. The current block storage memory receives an input from the current frame storage memory. According to one aspect of the present invention there is provided a motion vector detecting device comprising: a reference block memory for storing image data of a reference block having N x M pixels, where N and M are integers greater than or equal to one; a search block memory for storing image data of a search block having said N x M pixels; a first matching operational circuit connected to said reference block memory for detecting correlation between said N x M pixels of said image data of said reference block stored in said reference block memory and said N x M pixels of said image data of said search block stored in said search block memory with integer-pel accuracy to produce an integral-pel motion vector; a reference block buffer memory connected to said reference block memory for storing said image data of said reference block; a search block buffer memory connected to said search block memory for storing said image data of said search block; a second matching operational circuit for detecting correlation between said N x M pixels of said image data of said reference block stored in said reference block buffer memory and said N x M pixels of said image data of said search block stored in said search block buffer memory with less than or equal to half-pel accuracy to produce a fractional-pel motion vector; and an integration circuit for integrating said motion vectors produced by said first and second matching operational circuits. According to another aspect of the present invention there is provided a motion vector detecting device method comprising the steps of: storing, in a reference block memory, image data of a reference block having N x M pixels, where N and M are integers greater than or equal to one; storing, in a search block memory, image data of a search block having N x M pixels; detecting correlation between said N x M pixels of said image data of said reference block stored in said reference block memory and said N x M pixels of said image data of said search block stored in said search block memory with integer-pel accuracy by a first matching operational circuit, connected to said reference block memory, to produce an integral-pel motion vector; storing, in a reference block buffer memory connected to said reference block memory, said image data of said reference block; storing, in a search block buffer memory connected to said search block memory, said image data of said search block; detecting correlation between said N x M pixels of said image data of said reference block stored in said reference block buffer memory and said N x M pixels of said image data of said search block stored in said search block buffer memory with less than or to equal half-pel accuracy by a second matching operational circuit to produce a fractional-pel motion vector; and integrating said motion vectors produced by said first and second matching operational circuits. A device embodying the invention and described hereinbelow takes the form of a motion vector detecting device comprising an integral-pel matching operational circuit; a circuit for matching operation at the rate of a half or smaller pixel; buffer memory storing data of a reference block; and a FIFO storing data of a search area, output of the buffer memory and output of the FIFO being supplied to the circuit for matching operation at the rate of a half or smaller pixel, and the integral-pel matching operational circuit and the circuit for matching operation at the rate of a half or smaller pixel being operated in parallel. In the device embodying the invention and disclosed hereinbelow, detection of motion vectors at the rate of integral pixel or pixels and detection of motion vectors at the rate of a half pixel proceed in parallel such that half-pel motion vectors are always provided. As a result, the device does not need clocks irrelevant to the reading of data, and its circuit arrangement can be simplified. The invention will now be further described, by way of illustrative and nonlimiting example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram used for explanation of a predictive coding device; Fig. 2 is a schematic diagram used for explaining detection of a motion vector; Fig. 3 is a block diagram of an existing motion vector detecting circuit; Figs. 4A and 4B are schematic views used for explanation of the existing motion vector detecting circuit; Fig. 5 is a schematic view used for explaining the existing motion vector detecting circuit; Fig. 6 is a schematic view used for explaining the existing motion vector detecting circuit; Fig. 7 is a schematic view used for explaining the existing motion vector detecting circuit; Fig. 8 is a block diagram showing a basic structure used in an embodiment of the invention; Fig. 9 is a block diagram of one embodiment of the invention; Fig. 10 is a schematic diagram used for explanation of the embodiment of the invention; and Figs. 11A to 11E are timing diagrams used for explanation of the embodiment of the invention. An embodiment of the invention is described below with reference to the drawings. Fig. 8 is a block diagram for illustrating a basic structure of a motion vector detecting circuit to which the invention is applied. In Fig. 8, numeral 1 denotes a reference frame memory which stores image data of a reference frame, 2 refers to a search frame memory which stores image data of a search frame, 3 refers to an integral-pel matching operational circuit, 4 refers to a half-pel matching operational circuit, 5 refers to buffer memory, and 6 refers to a FIFO. As shown in Fig. 8, the integral-pel matching operational circuit 3 and the half-pel matching operational circuit 4 are operated in parallel. That is, reference block data and search area data are read out from the reference frame memory 1 and the search frame memory 2, respectively. The reference block data and the search area data are input to the integral-pel matching operational circuit 3. At the same time, the reference block data is sent to the buffer memory 5, and the search area data is sent to the FIFO 6. It is thus possible to reduce the frequency of access to the respective memory 1, 2 for reading into once. Output from the FIFO 6 always executes interpolation for pixels at half-pel positions. Matching errors corresponding to positions in the search area are output from the integral-pel matching operational circuit 3 in sequence with every clock. When a matching error is output from the integral-pel matching operational circuit 3, a pixel necessary for interpolation of its position is output from the FIFO 6. The delay of the FIFO 6 corresponds to the time necessary for determining the matching error of a first one-pixel vector position after entry of the search frame into the integral-pel matching operational circuit 3. The half-pel matching operational circuit 4 executes interpolation using output data from the FIFO 6, and makes data of a half-pel position. A matching error is obtained between the value of the interpolation and the data of the reference block read out from the buffer memory 5. If a new matching error with a small value is output from the integral-pel matching operational circuit 3, then the entirety is initialized in the half-pel matching operational circuit 4. Then, operation of matching errors between the data of half-pel position and the data of the reference block is re-done from the beginning. The integrating circuit 7 incorporates the integral-pel motion vector and the half-pel motion vector. Output of the integrating circuit 7 exits from the output terminal 8. Fig. 9 shows a specific embodiment. In Fig. 9, a reference frame memory 11 stores pixel data of a reference frame. The pixel data of the reference block is read out from the reference frame memory 11, and supplied to an integral-pel matching operational circuit 12 and to buffer memory 13. Output of the buffer memory 13 is supplied to a half-pel matching operational circuit 14. The search frame memory 15 stores pixel data of a search frame. Pixel data of a search area is read out from the search frame memory 15, and supplied to the integral-pel matching operational circuit 12 and to a FIFO 16. The delay of the FIFO 16 corresponds to the time necessary for determining the matching error of a first one-pixel motion vector after entry of the search frame into the integral-pel matching operational circuit 12. For example, if the dimension of the block is (16 x 16), the delay corresponds to 256 clocks. Output of the FIFO 16 is supplied to an interpolative circuit 18 which in turn produces interpolative data among respective pixels. Output of the interpolative circuit 18 is supplied to the half-pel matching operational circuit 14. The integral-pel matching operational circuit 12 executes block matching between the reference block and the search block at the rate of one pixel, and obtains a matching error. The integral-pel matching operational circuit 12 outputs matching errors with every clock. Output of the integral-pel matching operational circuit 12 is supplied to a minimum value detecting circuit 17. A search block with a smallest error is detected in the minimum value detecting circuit 17, and a motion vector at the rate of one pixel is obtained, accordingly. The motion vector at the rate of one pixel is supplied to an integrating circuit 20. Once the motion vector at the rate of one pixel is obtained, a control signal is generated from the minimum value detecting circuit 17. The control signal is supplied to the buffer memory 13 and to a minimum value detecting circuit 19. The half-pel matching operational circuit 14 executes block matching of the reference block and the search block at the rate of a half pixel by using the interpolative pixels, and obtains a matching error. Output of the half-pel matching operational circuit 14 is supplied to the minimum value detecting circuit 19. Output of the minimum value detecting circuit 19 is supplied to an integrating circuit 20. Obtained from the output of the minimum value detecting circuit 17 is a motion vector at the rate of one pixel. Obtained from the output of the minimum value detecting circuit 19 is a motion vector at the rate of a half or smaller pixel. The integrating circuit 20 combines the output of the minimum value detecting circuit 17 and the output of the minimum value detecting circuit 19 and finally obtains a motion vector. Output of the integrating circuit 20 exits from an output terminal 21. Fig. 10 and Figs 11A to 11E show the behavior of the embodiment of the invention. As shown in Fig. 10, each reference block contains 16 x 16 pixels. As shown in Fig. 11A, reference blocks RB0, RB1, RB2, ... are input in sequence. As shown in Fig. 11B, search data S0, S1, S2, ... are input in sequence. Each of the search data S0, S1, S2, ... contains 16x31 pixels. In the period from t 0 to t 1 , the reference block RB0 enters with 256 clocks, and the search data S0 also enters. The error RB0(int) of the search data S0 for the reference block RB0 is output from t 1 with every clock, as shown in Fig. 11C. Output of the integral-pel matching error for the reference block RB0 starts at time t 1 . At the same time, data is read out from the FIFO 16 to perform interpolation, and half-pel matching operation is executed by the half-pel matching operational circuit 14, as shown in Fig. 11D. The maximum period for the half-pel matching operation is 256 clocks after completion of integral-pel matching operation of the reference block RB0. Output of a matching error for the reference block RB1 starts at time t 2 . At the same time, data is read out from the FIFO 16 to perform interpolation, and half-pel matching operation is executed by the half-pel matching operational circuit 14, as shown in Fig. 11E. The half-pel matching operational circuit 14 is designed to progress two operations in parallel. The maximum period of this half-pel matching operation is 256 clocks after completion of the integral-pel matching operation of the reference block RB0. These operations are repeated for subsequent reference blocks. Integral-pel motion vectors and half-pel motion vectors, thus obtained, are combined by and output from the integrating circuit 20. The invention is not limited to embodiments where half-pel motion vectors are to be detected, but can be adapted to form embodiments where quarter-pel motion vectors are to be obtained. Having described a specific preferred embodiment of the present invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to that precise embodiment, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims: A motion vector detecting device comprising: a reference block memory (1; 11) for storing image data of a reference block having N x M pixels, where N and M are integers greater than or equal to one; a search block memory (2; 15) for storing image data of a search block having said N x M pixels; a first matching operational circuit (3; 12) connected to said reference block memory (1; 11) for detecting correlation between said N x M pixels of said image data of said reference block stored in said reference block memory (1; 11) and said N x M pixels of said image data of said search block stored in said search block memory (2; 15) with integer-pel accuracy to produce an integral-pel motion vector; a reference block buffer memory (5; 13) connected to said reference block memory (1; 11) for storing said image data of said reference block; a search block buffer memory (6; 16) connected to said search block memory (2; 15) for storing said image data of said search block; a second matching operational circuit (4; 14) for detecting correlation between said N x M pixels of said image data of said reference block stored in said reference block buffer memory (5; 13) and said N x M pixels of said image data of said search block stored in said search block buffer memory (6; 16) with less than or equal to half-pel accuracy to produce a fractional-pel motion vector; and an integration circuit (7;20) for integrating said motion vectors produced by said first and second matching operational circuits. A motion vector detecting device according to claim 1, wherein operation timing of said first matching operational circuit is different from that of said second matching operational circuit. A motion vector detecting device according to claim 2, wherein each of said image data of said reference block and said search block is data of a video frame signal. A motion vector detecting device according to claim 3, wherein said second matching operational circuit performs a matching operation in every odd and even field of said video frame signal. A motion vector detecting device according to claim 4, wherein said second matching operational circuit has an operational period that is no more than twice as long as an operational period of said first matching operational circuit, where each of said operational periods represents the time required to detect the correlation between said image data of said reference block and said image data of said search block. A motion vector detecting device according to claim 5, wherein said operational period of said first matching operational circuit for detecting the correlation between next N x M pixels of said image data of said reference block and next N x M pixels of said image data of said search block begins approximately at the middle of said operational period of said second matching operational circuit for detecting the correlation between current N x M pixels of said image data of said reference block and current N x M pixels of said image data of said search block. A motion vector detecting method comprising the steps of: storing, in a reference block memory (1; 11), image data of a reference block having N x M pixels, where N and M are integers greater than or equal to one; storing, in a search block memory (2; 15), image data of a search block having N x M pixels; detecting correlation between said N x M pixels of said image data of said reference block stored in said reference block memory (1; 11) and said N x M pixels of said image data of said search block stored in said search block memory (2; 15) with integer-pel accuracy by a first matching operational circuit (3; 12), connected to said reference block memory (1; 11), to produce an integral-pel motion vector; storing, in a reference block buffer memory (5, 13) connected to said reference block memory (1; 11), said image data of said reference block; storing, in a search block buffer memory (6; 16) connected to said search block memory (2; 15), said image data of said search block; detecting correlation between said N x M pixels of said image data of said reference block stored in said reference block buffer memory (5; 13) and said N x M pixels of said image data of said search block stored in said search block buffer memory (6; 16) with less than or to equal half-pel accuracy by a second matching operational circuit to produce a fractional-pel motion vector; and integrating (7; 20) said motion vectors produced by said first and second matching operational circuits. A motion vector detecting method according to claim 7, wherein operation timing of said first matching operational circuit is different from that of said second matching operational circuit. A motion vector detecting method according to claim 8, wherein each of said image data of said reference block and said search block is data of a video frame signal. A motion vector detecting method according to claim 9, wherein said second matching operational circuit performs a matching operation in every odd and even field of said video frame signal. A motion vector detecting method according to claim 10, wherein said second matching operational circuit has an operational period that is no more than twice as long as an operational period of said first matching operational circuit, where each of said operational periods represents the time required to detect the correlation between said image data of said reference block and said image data of said search block. A motion vector detecting method according to claim 11, wherein said operational period of said first matching operational circuit for detecting the correlation between next N x M pixels of said image data of said reference block and next N x M pixels of said image data of said search block begins approximately at the middle of said operational period of said second matching operational circuit for detecting the correlation between current N x M pixels of said image data of said reference block and current N x M pixels of said image data of said search block.

Inventors: OGURA EIJI, OGURA, EIJI, OGURA, EIJI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: SONY CORP, SONY CORPORATION
Application year: 1995
Main classification: H04N7
IPC codes: G06T9, G06T7, H04N7, H04N11