Comparator circuit operating on variable current

Abstract: The comparator circuit includes a differential amplifier circuit (5,6 and 7) which receives a first input voltage and a second input voltage, and outputs a comparison result signal by comparing the first and second input voltages, a current circuit (8) which supplies a driving current to activate the differential amplifier circuit, and a current control circuit (2) which is connected to the differential amplifier circuit and the current circuit. The current control circuit is deactivated when the first input voltage is lower than the second input voltage, and is activated when the first input voltage is higher than the second input voltage to reduce the driving current supplied.

Description: BACKGROUND OF THE INVENTION The present invention relates to a comparator circuit and, more particularly, to a comparator circuit comparing first and second input voltages supplied thereto. A typical comparator circuit is shown in FIG. 4 and includes a differential circuit 5 which compares the input signal voltages V IN1 and V IN2 applied to input terminals IN1 and IN2, a current amplifier 6 which amplifies the output of the differential amplifier 5, a driving circuit 7 which outputs an output voltage OUT, and a constant current circuit 8 which supplies operating currents to the differential amplifier 5 and the current amplifier 6. The constant current circuit 8 is equipped with transistors Q5, Q6 and Q7 and a current source I S . The transistors Q5 - Q6 constitute a current mirror circuit. In the differential circuit 5, when the first input voltage V IN1 is lower than the second input voltage V IN2 , transistors Q1 and Q2 are rendered conductive and non-conductive, respectively. Transistors Q3 and Q4, which constitute a current mirror, are thereby operated to pull down the base voltage of a transistor Q8 which is thereby turned OFF. therefore, a transistor Q9 receives a base current from the transistor Q6 to pull down the voltage of an output terminal OUT. In the case where the first input voltage V IN1 is higher than the second voltage V IN2 , on the other hand, the transistors Q1, Q3 and Q4 are turned OFF, whereas the transistor Q2 is turned ON. Accordingly, the transistor Q8 is rendered conductive to turn the transistor Q9 OFF. In the manner as described above, the signal comparison operation is performed on the input signals V IN1 and V IN2 . However, this comparator circuit always consumes an operating current determined the currents I 1 to I 3 irrespective of the levels of the input voltages V IN . Document PATENT ABSTRACTS OF JAPAN, vol.16, no.535 (E-1288), 05 November 1992 & JP-A-4 200 109 discloses a comparator circuit comprising a positive feedback loop with a differential comparison means, a current mirror means and a feedback means and using the feedback means so as to limit a maximum feedback current to an emitter of the differential comparison means] SUMMARY OF THE INVENTION It is an object of this invention to provide a comparator circuit which performs a voltage comparison operation with reduced current consumption. A comparator according to the present invention comprises a current circuit producing a first current at a first node and a second current at a second node, said first current taking in a first state a first value and in a second state a second value that is smaller than said first value, said second current taking in said first state a third value and in said second state a fourth value that is smaller than said third value, a differential circuit coupled to said first node to operate on said first current and having an output node, a first input node supplied with a first input voltage and a second input node supplied with a second input voltage to compare said first input voltage with said second input voltage, a drive transistor coupled to said second node to operate on said second current and having a control electrode coupled to said output node of said differential circuit, said differential circuit producing at said output node an intermediate output voltage which takes a first level that increases a current ability of said drive transistor, when said first input voltage is higher than said second input voltage, and a second level that decreases the current ability of said drive transistor when said first input voltage is lower than said second input voltage, an output transistor having a control electrode coupled to said second node and driven by a voltage at said second node, and means for bringing said current circuit into said second state when said first input voltage is higher than said second input voltage and into a first state when said first input voltage is lower than said second input voltage. Thus, in the comparator according to the present invention, the power current supplied to the comparison circuit is varied in accordance with the relationship in magnitude between the first and second voltages. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a circuit diagram illustrative of a comparator circuit according to a first embodiment of the present invention; FIG. 2 is a circuit diagram illustrative of the current control circuit 2 as shown in FIG. 1; FIG. 3 is a circuit illustrative of comparator circuit according to a second embodiment of the present invention; and FIG. 4 is a circuit diagram illustrative of a prior art comparator circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to Fig. 1, a comparator circuit according to a first embodiment of this invention includes, in addition to a differential circuit 5, a current amplifier 6, a driving circuit 7 and a constant current circuit 8, a current control circuit 2 consisting of a switching circuit 3 and a switching control circuit 4. The circuit parts 5, 6, 7 and 8 are the same as those shown in Fig. 8. The input end of the switching control circuit 4 is connected to the collector of the transistor Q4, and the output end of the switching control circuit 4 is connected to the switching circuit 3 which is in turn connected in parallel to the transistor Q7. The rest of the configuration is the same as the conventional circuit shown in FIG. 4 so that the further description thereof will be omitted. Referring to Fig. 2, the switching control circuit 4 is constituted of a transistor Q11 and a resistor R3, and the switching circuit 3 is constituted of a transistor Q10. The emitter of the transistor Q11 is grounded, and its base is connected to the collector of the transistor Q4. The one end of the resistor R3 is connected to the collector of the transistor Q11, and its the other end is connected to the base of the transistor Q10. The emitter of the transistor Q10 is connected to a power supply V CC (i.e., the emitter of the transistor Q7), and its collector is connected to the collector of the transistor Q7. In operation, when the first input signal voltages V IN1 is larger than the second voltage V IN2 , the transistor Q2 is turned ON and the transistor Q1 is turned OFF. The transistors Q3 and Q4 are thereby rendered non-conductive. The transistor Q2 increases the voltage at its collector, so that the transistor Q8 is turned ON and the transistor Q9 is turned OFF. The increased-collector voltage of the transistor Q2 further turns the transistor Q11 ON. A base current I CTL thus flows into the transistor Q10 to thereby produce its collector current I 4 which is in turn supplied to the constant current source I S . The current I 3 flowing through the transistor Q7 is reduced accordingly. Since the transistors Q5 - Q7 constitutes a current mirror circuit, each of the transistors Q5 and Q6 produces its collector current proportional to the current flowing through the transistor Q7. Thus, the currents I 1 and I 2 , which are produced by the transistors Q5 and Q6 and supplied to the circuit parts 5 and 6, are also reduced. The current I 4 flowing through the transistor Q10 is determined by its base current I CTL which is in turn controlled by the resistor R3. Accordingly, the changes of the currents I 1 - I 3 are controllable by the resistor R3. Since the base current I CTL is representative of I 4 /h FE (h FE being a current gain of the transistor Q10), it is considerably small. Accordingly, the current consumption of the present comparator becomes small as compared to the prior art comparator. When the first input voltage V IN1 becomes lower than the second input voltage V IN2 , the transistors Q1, Q3 and Q4 are turned ON and the transistor Q2 is turned OFF. The voltage at the base of the transistor Q8 is thereby pulled down, so that the transistors Q8 and Q11 are made non-conductive. The transistor Q9 receives the current from the transistor Q6 to drive the output terminal OUT to the low level. At this time, the transistor Q10 is in the cut-off state by the non-conductive state of the transistor Q11, and hence the current I 2 flowing through the transistor Q6 is increased. Accordingly, the transistor Q9 receives the current enough to drive the output terminal OUT at a high speed. As in the above, in the comparator circuit according to this embodiment, the current consumption is ( I 1 + I 2 + I 3 ), the same as in the conventional circuit, when the output voltage OUT is at the low level. However, when the output voltage OUT is at the high level, the current consumption can arbitrarily be set to one part in several, one part in several tens, or the like, of the conventional value by selecting the current supply ratio of the transistors Q7 and Q10 to the current source I S . In other words, it is possible to reduce the current consumption compared with the conventional case. It is to be noted that the currents I 1 - I 3 are reduced when the input voltage I IN1 is larger thans the voltage V IN2 . Specifically, when the output voltage is at the high level, the transistor Q9 is nonconductive, and no current flows in the transistor Q9 in that case. Therefore, no problem will arise unless the conduction states of the transistor Q9 and the transistor Q8 are changed by changing the base potentials of the respective transistors. Accordingly, at that time, a current which can maintain the conduction state of the transistor Q8 suffices, so that the currents I 1 and I 2 can be reduced. However, when the output voltage is at the low level, the transistor Q9 is in the conductive state, and a part of the current I 2 flows into the transistor Q9 as the base current. The collector current of the transistor Q9 is the larger for the larger value of the base current, and it is possible to lower the potential of the output OUT more rapidly for the larger collector current. That is to say, the speed of the shift of the potential of the output OUT from the high level to the low level can be made faster for the larger base current. Accordingly, when the output voltage OUT is at the low level, in order to prevent the drop in the operating speed of the comparator circuit, it is necessary to retain a current which is at least equal to the conventional current I 2 in the transistor Q8, and it is not recommended to reduce the current I 2 . Fig. 3 is a circuit diagram illustrative of a second embodiment of the comparator circuit according to this invention. As shown in FIG. 3, the comparator circuit 1 of this embodiment is set up to control the current circuit by detecting a change in the potential of the two inputs of the differential amplifier, in contrast to controlling the current circuit 8 by detecting the output of the differential amplifier in the first embodiment. For that purpose, this embodiment includes two differential amplifiers 5A and 5B which are connected in parallel to input terminals IN1 and IN2, and separately compare two input signals and output the difference by amplifying the difference, a current amplifier 6 which amplifies the output of one of the differential amplifier, 5A, a driving circuit 7 which is driven by the output of the current amplifier 6, a first current circuit 8A which supplies constant currents I 1 and I 2 to the differential amplifier 5A and the current amplifier 6, respectively, a second current circuit 8B which supplies a constant current to the other differential amplifier 5B, and a current control circuit 2 which controls the first current circuit 8A by detecting the output of the differential amplifier 5B. Among these circuits, the differential amplifier 5A, the current amplifier 6 the driving circuit 7, and the first current circuit 8A have the configuration similar to those circuits described in the first embodiment. The newly added differential amplifier 5B consists of transistors Q12 to Q15, the current circuit 8B consists of the transistors Q16 and Q17, and a current source I S2 , and the current control circuit 2 consists of a transistor Q18 which receives the output of the differential amplifier 5B to its base, a resistor R4 and a switching transistor Q19. Although the differential amplifier 5B and the current circuit 8B are formed separately from the current control circuit 2, the differential amplifier 5B and the current circuit 8B may be formed integrally in the current control circuit 2. The operation of the comparator circuit 1 described above is basically the same as that of the first embodiment so that its description will be omitted, but it should be mentioned that an effect similar to that of the first embodiment can also be obtained by this embodiment.

Claims: A comparator circuit comprising a current circuit (8) producing a first current (I 1 ) at a first node and a second current (I 2 ) at a second node, said first current (I 1 ) taking in a first state a first value and in a second state a second value that is smaller than said first value, said second current (I 2 ) taking in said first state a third value and in said second state a fourth value that is smaller than said third value, a differential circuit (5) coupled to said first node to operate on said first current and having an output node, a first input node (IN 1 ) supplied with a first input voltage and a second input node (IN 2 ) supplied with a second input voltage to compare said first input voltage with said second input voltage, a drive transistor (Q8) coupled to said second node to operate on said second current (I 2 ) and having a control electrode coupled to said output node of said differential circuit (5), said differential circuit (5) producing at said output node an intermediate output voltage which takes a first level that increases a current ability of said drive transistor (Q8), when said first input voltage is higher than said second input voltage, and a second level that decreases the current ability of said drive transistor (Q8) when said first input voltage is lower than said second input voltage, an output transistor (Q9) having a control electrode coupled to said second node and driven by a voltage at said second node, and means (2) for bringing said current circuit into said second state when said first input voltage is higher than said second input voltage and into a first state when said first input voltage is lower than said second input voltage. The comparator circuit as claimed in claim 1, wherein said current circuit includes a current mirror circuit (I 1 , I 2 , I 3 ) having a current input node coupled to a current source (I s ), a first current output node coupled to said first node and a second current node coupled to said second node, said current mirror circuit producing said first and second currents (I 1 , I 2 ) at said first and second current output nodes, respectively, in response to an input current supplied to said current input node, and said means (2) decreases said input current (I 4 ) when said first input voltage is higher than said second input voltage and increases said input current when said first input voltage is lower than said second input voltage. The comparator circuit as claimed in claim 2, wherein said means (2) comprises a first transistor (Q11) having a control electrode coupled to said output node of said differential circuit (5) and a second transistor (Q10) coupled to said first transistor to change said input current (I 4 ) in response to a current flowing through said first transistor. The comparator circuit as claimed in claim 2, wherein said means (2) comprises an additional current circuit (8B) producing a third current (I 4 ), an additional differential circuit (5B) operating on said third current and having an output end, a first input end supplied with said first input voltage and a second input end supplied with said second input voltage, a third transistor (Q18) having a control electrode coupled to said output end of said additional differential circuit, and a fourth transistor (Q19) coupled to said third transistor (Q18) to change said input current.

Inventors: KAWAKAMI NAOMI, KAWAKAMI, NAOMI, Kawakami, Naomi, NEC IC Microcomp.Systems Ltd.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1995
Main classification: H03K5
IPC codes: H03K5, H03F1, H03F3