DELAY UNIT AND TRANSMISSION SYSTEM USING SUCH A DELAY UNIT

Abstract: In a delay element (2) according to the prior art, comprising a FIFO (2) it is only possible to obtain a delay value which is equal to an integer number of symbol periods. By using a phase shifter (8) for obtaining an arbitrary phase shift between a write control signal controlling a write operation of the FIFO memory and a read control signal controlling a read operation of the FIFO memory, a delay value being not an integer value of the symbol period can be obtained.

Description: Delay unit and transmission system using such a delay unit The invention is related to a delay unit for delaying digital symbols, com¬ prising a memory for storing said digital symbols under control of a write control signal and for retrieving said digital symbols under control of a read control signal. The invention is also related to a transmission system and a secondary station for such a transmission system using such a delay unit. A delay unit according to the preamble is known from KOKAI 64-19822, published at January 23, 1989. Such a delay unit can be used in many applications in which a sequence of digital symbols has to be delayed over a certain amount of time. There exist several ways to delay a signal over a certain amount of time. A very well known possibility is the use of analog all pass filters comprising of resistors, capacitors and/or inductors. Such delay units may require the use of precision elements to avoid the inevitable spread of analog components. Furthermore it is difficult to construct such analog delay units which can be easily controlled. To avoid these problems, the delay unit according to the above mentioned KOKAI 64-19822 uses a FIFO memory ( First In First Out ) in which the digital symbols are written under control of a write control signal, and from which the digital symbols are read under control of a read control signal. To obtain a certain delay the read control signal is derived from the write control signal by inhibiting a number of pulses using a gate. The number of pulses inhibited is counted by a (presetable) counter, and if the number of pulses to be inhibited is reached, the write pulses are passed by the gate. In this way it is obtained that the read address differs from the write address by the number of pulses inhibited, causing that the digital symbols are retrieved said number of inhibited clock pulses later than they were written into the FIFO memory, leading to the desired delay. A problem of the known delay unit is that it is only possible to obtain a delay that is equal to an integer number times the symbol period. The reason for this is that the number of pulses to be inhibited can only be integer valued. The object of the present invention is to provide a delay element according to the preamble in which it is also possible to obtain delay values being not an integer number times the symbol period. Therefor the delay unit according to the invention is characterised in that the delay unit comprises phase shift means for introducing an arbitrary phase shift between the read control signal and the write control signal. By using phase shift means for obtaining a phase shift between the write control signal and the read control signal, it is possible to obtain any delay value corresponding to the phase shift introduced between the write control signal and the read control signal. A preferred embodiment of the invention is characterised in that the phas shift means comprise a phase detector for deriving a phase error signal being dependent on the value of the phase shift between the read control signal and the write control signal, a controlled oscillator for generating the read signal or the write signal in dependence on the phase error signal, and means for offsetting the phase error signal with an offset value.. By the introduction of an offset to the phase error signal the phase locked loop comprising of phase detector and controlled oscillator tends to produce a phase error signal which cancels the offset value. This means that an additional phase shift dependent on the offset value is introduced between the input signal and the output signal of the phase locked loop. Use of a phase locked loop is a very easy way to obtain a (variable) phase shift between the write control signal and the read control signal. The use of the introduction of an offset in a phase locked loop for obtaining arbitrary phase shift values between input and output signal as such is disclosed in IBM technical disclosure bulletin, Vol. 19, No. 8, January 1977, pp 3131-3132. A further embodiment of the invention is characterised in that phase shift means comprise a first frequency divider for deriving a first input signal for the phase comparator from the write control signal, and a second frequency divider for deriving a second input signal for the phase comparator from the read control signal. The use of the first and second frequency dividers allows the range of the phase shift value to be larger than the range of the phase error that can be tolerated by the phase detector. If the division factor of the frequency dividers is equal to N, the range of th phase shift is increased with a factor N. The delay unit according to the invention can be advantageously be used in a Transmission system comprising a plurality of secondary stations coupled to a primary station via a transmission channel being at least partial in common for several secondary stations, said secondary stations comprise a delay unit for delaying digital symbols to be transmitted from the secondary stations to the primary station over an adjustable amount of time for preventing collision of data symbols from different secondary stations, said delay unit comprising a memory for storing said digital symbols under control of a write control signal and for retrieving said digital symbols under control of a read control signal, and phase shift means for introducing an arbitrary phase shift between the read control signal and the write control signal. Such transmission systems are used for the communication between several secondary stations to a primary station via a transmission channel being, at least partially, common to some of the secondary stations. Such transmission channel can comprise an optical fibre, a coaxial cable, or a radio link. Application of such transmission systems can be passive optical networks, local area networks, systems for satellite communication and mobile radio systems. In transmission systems utilising a common channel for some secondary stations it must be ensured that no interference is caused by secondary stations simulta¬ neously transmitting information to the primary station. A possibility to prevent such interference, is to allot a predetermined time slot from a number of distinct time slots to each of the secondary stations. Because these time slots are non-overlapping, the primary station can distinguish the signals from different secondary stations. In general said secondary stations have different distances from the primary station. In mobile radio systems these distances are even variable. Due to these different distances the propagation delay between these secondary stations and the primary stations may be different. This results in that signals which are transmitted in non overlapping time slots can collide at arrival at the primary station. To prevent this problem the propagation delay from each secondary station to the primary station is measured, and consequently the transmission instant of each secondary station is adapted to prevent said collision. The delay value of the delay element is set to such a value that the sum of said delay value and the transmission delay value is equal for all secondary stations. In systems in which only a small delay of the transmitted signals can be tolerated the duration of a time slot is only one or a few symbol periods. Having such narrow time slots, only a small overlap between such time slots can be tolerated, because otherwise the data in the time slot will be completely or partly lost. By using guard spaces between the time slots the allowable tolerances of the total transmission delay could be relaxed, but this would lead to a less efficient use of the transmission capacity available. To prevent overlap between time slots without introducing guard spaced, it is required that the delay unit can be adjusted with a resolution being a fraction of the symbol period. Usable prior art delay units for high bit rates are rather expensive, unreliable or even not available at all. The delay unit according to the invention fulfils all requirements, and is very simple to construct. The invention will now be discussed in more detail with reference to the drawings. Herein shows: Fig. l a block diagram of the delay unit according to the invention; Fig. 2 an embodiment of the phase shift means 8 to be used in the delay unit according to fig. 1 ; Fig. 3 a first embodiment of the FIFO memory 4 in Fig. 1; Fig. 4 a second embodiment of the FIFO memory 4 and the phase shift means 8 in Fig. 1; Fig. 5 a timing diagram of some signals in the delay unit according to Fig. 4. Fig. 6 a transmission network in which the delay unit according to the invention can be used; Fig. 7 a secondary station for use in the transmission system according to Fig. 6. In the delay unit 2 according to Fig. 1 digital symbols to be delayed are applied in serial form to an input of a FIFO memory 4. An output of a clock generator 6 carrying as ouφut signal the write control signal is connected to a write control input of the FIFO memory 4 and to an input of the phase shifting means 8. The output of the delay unit 2 is constituted by an output of the FIFO memory 4. The ouφut of the phase shift means 8 carrying the read control signal is connected to a read control input of the FIFO memory 4. The phase shifting means 8 has a further input to receive a control signal specifying the value of the phase shift. The FIFO memory 4 is arranged to receive the data symbols to be delayed at the input. This data is stored in the FIFO memory 4 during a clock pulse generated by the clock generator 6. The frequency of the clock signal generated by the clock generator 6 is equal to the symbol frequency. At the ouφut of the FIFO memory the stored symbols are retrieved in response to the read control signal at the ouφut of the phase shifting means 8. The stored symbols are retrieved in the same order as they were written in the FIFO memory 4. Due to the arbitrary value of the phase shift between the write control signal and the read control signal it is possible to obtain a delay value which comprises a fraction of the symbol period. In the phase shift means 8 according to Fig. 2, the input signal is applied to an input of a first frequency divider 10. The ouφut of the frequency divider 10 is connected to a first input of a phase comparator 12. An ouφut of the phase comparator 12 is connected to a first input of an adder 16. An offset signal is applied to a second input of the adder 16. An ouφut of the adder 16 is connected to an input of a low pass filter 18. An ouφut of the low pass filter 18 is connected to a control input of a controllable oscillator 20. An ouφut of the controllable oscillator, carrying the read control signal, is connected to an input of a second frequency divider 14. The ouφut of the second frequency divider 14 is connected to a second input of the phase comparator 12. The phase locked loop constituted by the first and second frequency dividers 10 and 14, the phase comparator 12 the adder 16 the low pass filter 18 and the controllable oscillator 20 will cause the input signal of the low pass filter to be equal to zero. If no offset signal is applied at the second input of the adder 16, the average value of the ouφut signal of the phase comparator is also equal to zero. This is in general the case at a phase shift of 90 ° between the write control signal and the read control signal. If an offset value is applied at the second input of the adder 16 the phase locked loop will keep the average value of the ouφut signal of the adder 16 equal to zero. This is only possible if the average value of the ouφut signal of the phase detector 12 differs from zero. This can only be caused by an additional phase shift between write control signal and read control signal, said phase shift being dependent on the offset value. The possible value of the additional phase shift is determined by the range of the phase comparator 12. In order to increase the range of possible values of the additional phase shift, the first and second frequency dividers are introduced. The introduction of the frequency dividers 10 and 14 results in an N fold increase of the range of the additional phase shift. In the implementation of the FIFO memory 4 according to Fig. 3, the signal to be delayed is applied to a data input of a dual port RAM 22. A number of ouφuts of a programmable counter 24 is coupled to corresponding address inputs of the dual port RAM 22. The write control signal is applied to a clock input of the programmable counter 24. The counters 24 and 26 comprise parallel inputs for enabling the transfer of a preset value into said counter 24 or 26 under control of a parallel load signal. The ouφut of the FIFO memory 4 comprises a data ouφut of the dual port RAM 22. A number of ouφuts of a programmable counter 26 is coupled to corresponding address inputs of the dual port RAM 22. The read control signal is applied to a clock input of the programmable counter 26. The counter 26 comprises parallel inputs for enabling the transfer of a preset value into said counter 24 under control of a parallel load signal. At the start of the operation of the FIFO memory according to Fig. 3, a number is loaded into counter 24 and 26 under control of the corresponding parallel load input. The delay value is determined by the difference between the numbers loaded in the counters 24 and 26 respectively. After the initialisation of the counters 24 and 26 an input symbol is written into the dual port RAM 22 at the address indicated by the counter 24 at every pulse of the write control signal. After the write operation the count of the counter 24 is increased. An ouφut symbol is read from the dual port RAM 22 at the address indicated by the counter 26 at every pulse of the read control signal. After the read operation the count of the counter 26 is also increased. The difference D between the contents of the counters 24 and 26 determines a coarse delay value expressed in a number of symbol periods. Said coarse delay is obtained because the ouφut symbols is read from the dual port RAM 22 D symbol periods later than said symbols were written to the dual port RAM 22. It is possible that the delay of the delay unit according to Fig. 3 shows an ambiguity of the delay value of one symbol period. This ambiguity is caused by the unknown phase relationship between the read control signal and the write control signal during loading the counters 24 and 26. Such ambiguity can be avoided by setting the phase difference between the read control signal and the write control signal to a predetermined value during loading the counters 24 and 26. By introducing an arbitrary phase shift between the read control signal and the write control signal the delay value has not to be equal to an integer number of symbol periods. In the delay unit according to Fig. 4 the signal to be delayed is applied to an input of the FIFO memory 4, which input is constituted by an input of a series to parallel converter 30. N parallel ouφuts of the series to parallel converter 30 are coupled to N parallel inputs of a latch 31. N parallel ouφuts of the latch 31 are connected to N parallel inputs of a parallel to series converter 32. An ouφut of the parallel to series converter 32 constitutes the ouφut of the FIFO memory 4 and of the delay unit 2. A clock signal CLK is applied to an input of the phase shifting means 8, which input is constituted by a clock input of a frequency divider 34 and to a clock input of the series to parallel converter 30. A first ouφut of the frequency divider 34, carrying ouφut signal CLK8, is coupled to a reference input of a phase locked loop. A second ouφut of the frequency divider 34, carrying an ouφut signal BYTE, is connected to a clock input of the latch 31. An ouφut of the phase locked loop 38, carrying an ouφut signal PCLK, is connected to a clock input of a frequency divider 36 and to a clock input of the parallel to series convener 32. A first ouφut of the frequency divider 36, carrying an ouφut signal PCLK8, is coupled to a second input of the phase locked loop 38. A second ouφut of the frequency divider 36, carrying an ouφut signal PLOAD, is connected to an parallel load input of the parallel to series converter 32. The phase locked loop 38 has further a control input to receive a signal φ representing the desired phase shift. The operation of the delay unit 2 according to Fig. 4 is explained with reference to Fig. 5 presenting some signals present in the delay unit according to Fig. 4. In Fig. 5 it is assumed that the value of N is equal to 8. The frequency of the clock signal CLK applied to the delay unit 2 is equal to the symbol period. This clock signal is displayed in Fig. 5a. The symbols applied at the input of the series to parallel converter are clocked into said series to parallel converter in response to the clock signal CLK and are available in parallel format at the ouφuts of the series to parallel converter 30. The frequency divider 34 derives an ouφut signal BYTE having a pulse width equal to the symbol period and a repetition period of N ( = 8 ) symbol periods. At each falling edge of the signal BYTE the data present at the ouφuts of the series- parallel converter 30 are taken over by the latch 31. This can be seen from Fig. 5c. The parallel data remains available at the ouφuts of the latch 31 during 8 subsequent symbol periods. A signal CLK8 ( Fig. 5d ) having a duty cycle of 50 % is applied to the phase locked loop 38. The phase locked loop 38 generates an ouφut clock signal PCLK having a frequency equal to the frequency of the clock signal CLK, but being phase shifted. The ouφut signal PCLK8 is phase shifted with respect to the clock signal CLK8 by the phase locked loop 38, due to the presence the signal φ. The signal PLOAD having a width of one symbol period and a repetition period of N (=8) symbol periods, is applied to a parallel load input of the parallel to series converter 32. At the falling edge of the signal PLOAD the signals at the ouφuts of the latch 31 are transferred into the parallel series converter 32. The delay value D of the delay element 2 is determined by the relative position of the falling edge of the signal PLOAD and the falling edge of the signal BYTE. By changing the position of the signal PLOAD by the introduction of the signal φ into the phase locked loop 38 it is possible to obtain a variable delay value D. Said value delay is not restricted to inter symbol periods, because the phase shift between the signals CLK8, and PCLK8 can have any value between 0 and 8 symbol periods. In the transmission system according to Fig. 6 a primary station 40 is coupled via a channel 54 to a number of secondary stations 42 • • • 52. Parts of the transmission channel 54 are in common for some of the substations. The transmission channel can be a passive optical network for a local loop transmission system, a cable for a local area network or the free space for a mobile radio system. If the so-called Time Division Multiple Access method is used, some or all of the active stations have to transmit its data on a corresponding time slot in a predetermined frame. Due to the difference in propagation delay between the several secondary stations and the primary stations, it may occur that signals which are transmitted at the correct time by said secondary stations collide on their arrival at the primary station. To prevent this collision the secondary stations are provided with delay means to delay their transmitted signals by such an amount that no collision occurs at arrival of said signals from several secondary stations at the primary station. If the size of the time slots is only one or a few symbol periods to limit the signal delay in the transmission system, it is required to be able to delay a signal over a non integer number of symbol periods if a guard space is not used due to efficiency reasons. To that end the delay unit according to the invention provides a simple and effective solution. In the primary station according to Fig. 7, the transmission channel can be coupled to an input/ouφut of a duplexer 60. The ouφut of the duplexer 60 is coupled to an input of a receiver 62. An ouφut of the receiver is coupled to an input of a decoder 64. The ouφut of the decoder 64 is coupled to a n input of a frame disassembler 66. At a first ouφut a signal representing the useful data is available. The data to be transmitted is applied to an input of a delay element 2. A second ouφut signal of the disassembler 66, carrying a signal representing the desired delay value is coupled with a second input of the delay element 2. an ouφut of the delay element is coupled to an input of a coder 70. An ouφut of the coder 70 is coupled to an input of a transmitter 72. An ouφut of the transmitter 72 is coupled to an input of the duplexes 60. A signal from the transmission channel is applied to the receiver 62 by the duplexes 62. The receiver 62 processes the received signals and presents a base band signal representing the ouφut symbols at its ouφut. The operations of the receiver 62 can comprise demodulation, equalisation, timing recovery and detection. The ouφut symbols of the receiver 62 are decoded by the decoder 64. The received signal may be encoded for error protection or for secrecy reasons. In the disassembler the frame comprising the symbols is separated into useful data and control data. The useful data is made available at the ouφut of the secondary station. A part of the control signals that determines the desired delay of the data transmitted in the time slot corresponding to said secondary signal. A signal to be transmitted by the secondary station is delayed with the desired value and applied to the coder 70 for encoding. The encoded signal is transformed into a signal that is suitable for transmission via the transmission channel by the transmitter 72. This transformation may include modulation and amplification to a desired signal level. The duplexes 60 applies the ouφut signal of the transmitter 72 to the transmission channel and prevents cross talk of the signal to be transmitted to the input of the receiver 62. The delay value applied to the control input of the delay element 2 can comprise an integer part representing the integer number of symbol periods of the delay value and a fractional part representing the fraction of the symbol period of the delay value. The delay element according to Fig. 3 is suitable for application with such control signals. The integer part determines the difference between the numbers with which the counters are loaded at initialisation, and the fraction part determines the value of the phase shift.

Claims: CLAIMS 1. Delay unit for delaying digital symbols, comprising a memory for storing said digital symbols under control of a write control signal and for retrieving said digital symbols under control of a read control signal, characterised in that the delay unit comprises phase shift means for introducing an arbitrary phase shift between the read control signal and the write control signal. 2. Delay unit according to claim 1, characterised in that the phase shift means comprise a phase detector for deriving a phase error signal being dependent on the value of the phase shift between the read control signal and the write control signal, a controlled oscillator for generating the read signal or the write signal in dependence on the phase error signal, and means for offsetting the phase error signal with an offset value. 3. Delay unit according to claim 2, characterised in that phase shift means comprise a first frequency divider for deriving a first input signal for the phase comparator from the write control signal, and a second frequency divider for deriving a second input signal for the phase comparator from the read control signal. 4. Transmission system comprising a plurality of secondary stations coupled to a primary station via a transmission channel being at least partial in common for several secondary stations, said secondary stations comprise a delay unit for delaying digital symbols to be transmitted from the secondary stations to the primary station over an adjustable amount of time for preventing collision of data symbols from different secondary stations, said delay unit comprising a memory for storing said digital symbols under control of a write control signal and for retrieving said digital symbols under control of a read control signal, and phase shift means for introducing an arbitrary phase shift between the read control signal and the write control signal. 5. Transmission system according to claim 4, characterised in that the phase shift means comprise a phase detector for deriving a phase error signal being dependent on the value of the phase shift between the read control signal and the write control signal, a controlled oscillator for generating the read signal or the write signal in dependence on the phase error signal, and means for offsetting the phase error signal with an offset value. 6. Transmission system according to claim 5, characterised in that the phase shift means comprise a first frequency divider for deriving a first input signal for the phase comparator from the write control signal, and a second frequency divider for deriving a second input signal for the phase comparator from the read control signal. 7. Secondary station for a multiple access transmission system, said secondary station comprising a delay unit for delaying digital symbols to be transmitted from the secondary stations to a primary station over an adjustable amount of time for preventing collision of data symbols from different secondary stations, said delay unit comprising a memory for storing said digital symbols under control of a write control signal and for retrieving said digital symbols under control of a read control signal, and phase shift means for introducing an arbitrary phase shift between the read control signal and the write control signal. 8. Secondary station according to claim 7, characterised in that phase shift means comprise a phase detector for deriving a phase error signal being dependent on the value of the phase shift between the read control signal and the write control signal, a controlled oscillator for generating the read signal or the write signal in dependence on the phase error signal, and means for offsetting the phase error signal with an offset value. 9. Secondary station according to claim 8, characterised in that phase shift means comprise a first frequency divider for deriving a first input signal for the phase comparator from the write control signal, and a second frequency divider for deriving a second input signal for the phase comparator from the read control signal.

Inventors: PENNING DE VRIES HENDRICUS THE, PENNING DE VRIES, HENDRICUS, THEODORUS, GERARDUS,
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1995
Main classification: H03K5
IPC codes: H03K5, H04J3