Semiconductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed

Abstract: In a semiconductor memory, a plurality of semiconductor memory modules (21, ....2n) are connected through a common clock signal line and one or more other signal lines to an accessing circuit. The accessing circuit has a timing information storage unit (3A, 3B) for storing beforehand access timing information associated with the respective semiconductor memory modules and a timing varying unit (6A, 6B) for varying a data receiving timing at a transfer destination in compliance with a semiconductor memory module to be accessed, on the basis of the access timing information stored in the timing information storage unit.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory which is applicable to, for example, a semiconductor disk device fabricated with a plurality of semiconductor memories, which is used in a similar fashion to a hard disk device. Description of the Background Art For example, a book type of personal computers includes a memory space which can be extended by connecting a card-like semiconductor disk device to an extended connector slot which is adapted for connecting thereto a hard disk drive. FIG. 2 shows an example of semiconductor disk device which is used as an auxiliary memory device as mentioned above. In FIG. 2, the semiconductor disk device 1 comprises one or more memory module groups 2, a microcomputer 3, a host interface 4, a buffer memory 5 and a memory controller 6. Each of the memory module groups 2 comprises a plurality of memory modules 21-2n, each of which is constituted of a single chip of serial memory, such as flash memory, and has the same speed capability as each other. The memory modules 21-2n in the memory module group 2 are connected in common with a bidirectional data line LDAT and a clock signal line LCLK. It is assumed that the memory module group 2 corresponds to a header in a hard disk device; each of the memory modules 21-2n to a cylinder in the hard disk device; and an internal storage area of each of the memory modules 21-2n to a predetermined number of sectors from one sector address to another, where n is a natural number. The memory modules 21-2n are provided for the semiconductor disk device 1, and upon receipt of serial data for control, including an address and a sort of access, for example, they continuously write thereinto or read out thereof data corresponding to a sector, e.g. 536 bytes of data. To effect a writing operation on the semiconductor disk device 1, there is a need to supply from a host computer, not shown, thereto a command including information such as a header number, a cylinder number, the first sector number, the number of writing sectors and the like, and an additional command for instructing a writing operation. After issuance of these commands, data are transferred after the lapse of a predetermined time corresponding to the seek time, the rotation time and the like. Upon receipt of the commands through the host interface 4, the microcomputer 3 decodes and converts the commands into control information accessible to a memory module 2i, the control information including an indication designating a memory module 2i and an address designating a sector in that memory module 2i, into which data is to be written, where i is a natural number between 1 and n , inclusive. The control information thus converted is supplied to the memory controller 6. On the other hand, transmitted data for writing is fed through the host interface 4 to the buffer memory 5. The memory controller 6 sends out serial data for control, which consists of an address, a control signal for instructing writing and the like, over the bidirectional data line LDAT to a predetermined memory module group 2 in accordance with the control information outputted from the microcomputer 3, and then sends out a sector of data from the buffer memory 5 through a parallel-to-serial conversion on the bidirectional data line LDAT to the predetermined memory module group 2. This transfer is repeated on a sector-by-sector . basis. When the serial data for control is sent out to the bidirectional data line LDAT, and when data to be written is sent out to the bidirectional data line LDAT, the memory controller 6 sends out, of course, a clock signal to the clock signal line LCLK in synchronism with those sending operations, so that data supplied from the host computer is written into the predetermined memory module 2i of the memory module group 2. On the other hand, to effect a reading operation on the semiconductor disk device 1, there is a need to supply from a host computer, not illustrated, to the semiconductor disk device 1 a command including information such as a header No., a cylinder No., a top sector No., the number of writing sectors and the like, and an additional command for instructing a reading operation. Upon receipt of the commands through the host interface 4, the microcomputer 3 decodes and converts the commands into control information accessible to a memory module 2i, the control information including an indication designating a memory module 2i and an address designating a sector in that memory module 2i, from which data is to be read out. The control information thus converted is supplied to the memory controller 6. The memory controller 6 sends out serial data for control, which consists of an address, a control signal for instructing writing and the like, over the bidirectional data line LDAT to a predetermined memory module group 2 in accordance with the control information outputted from the microcomputer 3, and sends out a clock signal on the clock signal line LCLK to the predetermined memory module group 2 in synchronism with the serial data sending operation. Also after sending the serial data for control, the memory controller 6 continuously sends out the clock signal on the clock signal line LCLK to the predetermined memory module group 2 and receives data read out from a predetermined memory module 2i of the memory module group 2 in response to the clock signal. The received data are converted into parallel data and stored in the buffer memory 5 through the host interface 4. In this manner, the data stored in the buffer memory 5 are transferred via the host interface 4 to the host computer. However, the semiconductor disk device 1 involves such a drawback that a timing relation between transfer data and the clock signal deviates from a predetermined timing relation at a transfer destination (a memory module when writing, or a memory controller when reading) by the reasons as set forth below: (1) It is difficult to avoid such a situation that the timing of the clock signal with respect to the timing of outputting data is out of an intended value owing to an irregularity caused by manufacturing the memory controller; (2) There exists a difference in performance between the memory modules owing to an irregularity caused by manufacturing the memory modules; (3) The lengths of the signal line and the bidirectional data line, which are connected to a memory module, are varied in dependence upon the position in which the memory module is loaded, and parasitic capacitance and resistance are varied in dependence upon a path. These cause a delay in transferring the signals and data to be varied; and (4) The signal lines are mutually different in length, which are connected to associated memory modules even in the same memory module group in dependence upon the position in which the memory module is loaded, and parasitic capacitance and resistance are varied depending upon a path. These also cause a delay in transferring the signals to be varied; and (5) It is difficult to avoid the skew of the delay in transferring the signals and data. Consequently, when the transfer is effected in a certain timing, some memory module will encounter critical set-up and hold timings. Thus, there is a large possibility of malfunctions in writing and reading. If the whole memory modules were involved in the same timing deviation, it would be possible to avoid the above-mentioned inconvenience through, for example, regulating the phase of the clock signal outputted from the memory controller. However, for example, as shown in parts (a) and (b) of FIG. 3, while there is obtained a good timing on the memory module 2n which is located nearest to the memory controller 6, the memory module 21, which is located farthest from the memory controller 6, will encounter severe set-up and hold timing, as shown in parts (c) and (d) of FIG. 3. Therefore, in such a case, it is impossible to apply the above-mentioned measure. There is a way to prevent malfunctions at the time of writing and reading by means of providing a large margin of the set-up time and the hold time through elongating a cycle time or clock period. However, according to this way, there will occur another problem such that the transfer rate at the time of transfer from and to the memory module is reduced, and as a result it is obliged to decrease the operational speed of the semiconductor disk device. This problem occurs on not only with the semiconductor disk device, but also the various kinds of semiconductor memories in which a plurality of memory modules own the data line and the clock signal line jointly with each other. It is therefore an object of the present invention to provide a semiconductor memory capable of operating at high speed such that sufficient set-up time and hold time are ensured even in the case where any of the memory modules, which own the data line and the clock signal line jointly with each other, is accessed. It is disclosed in EP-A-619546 that a programmable memory controller and method for configuring the memory controller provide a way to program or configure the memory controller for varying types, speeds, and sizes of memory devices without physically changing the hardware of the memory controller. The memory controller can also be programmed or configured to select bus control, timing, and address signals of the memory controller for accessing memory devices. EP-A-379772 discloses a method and apparatus for providing asynchronous communication between at least one central processing unit (CPU) and at least one associated memory unit with specially programmed timing signals to latch, select and transmit data between them. SUMMARY OF THE INVENTION Present invention is defined in the independent claim. Preferred embodiments are described in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS The objects and features of the present invention will become more apparent from consideration of the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 is a schematic block diagram of a semiconductor disk device according to an embodiment of the present invention; FIG. 2 is a schematic block diagram of a conventional semiconductor disk device; FIG. 3 is a time chart useful for understanding the semiconductor disk device shown in FIG. 2; FIG. 4 is a schematic block diagram of a semiconductor disk device wherein a plurality of memory module groups are provided, which is a modification from the embodiment shown in FIG. 1; FIG. 5 is a time chart useful for understanding the semiconductor disk device according to the embodiment; FIG. 6 is a schematic block diagram of a semiconductor disk device according to an alternative embodiment of the present invention; FIG. 7 is a time chart useful for understanding the semiconductor disk device shown in FIG. 6; DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) First embodiment The first embodiment, in which the present invention is applied to a semiconductor disk device, will be described in conjunction with the accompanying drawings. It is noted that the first and second embodiments are involved in the case where all the memory modules in a semiconductor disk device are of the same operational speed. In this respect, these embodiments are different from the third and fourth embodiments, which will be described later. An aspect of the semiconductor disk device according to the first embodiment resides in writing data into the memory modules. In order to simplify the understanding of the aspect, FIG. 1 shows the use of a single memory module group. In FIG. 1, the like components are denoted by the same reference numerals or marks as those of FIG. 2. In FIG. 1, the semiconductor disk device 1A according to the first embodiment also comprises a memory module group 2, a microcomputer 3A, a host interface 4, a buffer memory 5 and a memory controller 6A. However, the microcomputer 3A and the memory controller 6A are different from those of the semiconductor disk device 1 shown in FIG. 2. The microcomputer 3A stores delay information 3Aa for each of the memory modules 21, ..., 2n in the case where data are transferred to the memory modules 21, ..., 2n. For example, the delay information 3Aa is stored in the form of a microprogram. When the microcomputer 3A recognizes the memory module 2i into which data is to be written, the microcomputer 3A feeds the delay information 3Aa and the associated writing signal to the memory controller 6A, prior to starting of data transfer to the memory module group 2 by a memory control circuit 10 which will be described later. The memory controller 6A comprises the memory control circuit 10, which corresponds to the control circuit of the memory controller 6 in the semiconductor disk device 1 shown in FIG. 2, and in addition a plurality of delay devices 11, 12 and 13, a selector 14 and a delay information register 15. In the specific embodiment, three delay devices 11, 12 and 13 are exemplarily provided. The memory control circuit 10 serves to output the serial data for control to the memory module 2i to be accessed in synchronism with the clock signal, convert the transfer data read out from the buffer memory 5 via the host interface 4 into the serial data, and output the data thus converted to the memory module 2i to be accessed in synchronism with the clock signal, in accordance with control information outputted from the microcomputer 3A. Three delay devices 11-13 are connected with each other in a cascade fashion as shown. This cascade connection is arranged so as to receive the serial data outputted from the memory control circuit 10. Thus, four serial data, which are mutually different in phase by a predetermined unit of delay time, are obtained from the front and back stages of the cascade connection and the middle taps. These data are fed to the selector 14 as a selection input. The selector 14 receives a delay device selection signal from the delay information register 15 and selects the serial data according to the delay device selection signal. The serial data thus selected is sent out to the data line LDAT connected to the memory module group 2. The unit delay time is set up to such a degree that even the time difference between non-delayed serial data and the most delayed serial data is shorter than, for example, the half of the period of the clock signal. The delay devices 11-13 may be implemented as a plurality of inverter devices connected in series, or a plurality of latch circuits which are connected in series and each adapted to latch data in response to a clock signal of higher speed than the clock signal (writing clock signal) to be supplied to the memory module group 2. The delay information register 15 receives the delay information 3Aa, which was outputted from the microcomputer 3A prior to starting of the data transfer by the memory control circuit 10, and the writing signal as well. Thus, the delay information register 15 holds the delay information in accordance with the writing signal. The delay information thus held is fed to the selector 14 in the form the delay device selection signal. It is practical that the memory controller 6A is solely mounted on a single semiconductor chip, or mounted together with the host interface 4 and the buffer memory 5 on a single semiconductor chip. This involves no problem as to the transfer delay not intended in the memory controller 6A, but involves problems as to a deviation of transfer delay on the data line LDAT and the clock signal line LCLK connected to the memory modules 21, ..., 2n, a variation of the transfer delay, and the like. The delay information 3Aa involved in the memory modules 21,..., 2n, which is stored beforehand in the microcomputer 3A, is determined taking into consideration a deviation of transfer delay on the data line LDAT and the clock signal line LCLK connected to the memory modules 21, ..., 2n, which lines are formed on a printed circuit board, a variation of the transfer delay, and the like. For example, it is acceptable that the delay information is uniquely determined depending upon where the memory modules 21, ..., 2n are located, for example, the length of the signal lines of the memory modules 21, ..., 2n. Alternatively, the optimum delay information is determined through an experiment after the memory modules 21, ..., 2n are mounted. In FIG. 1, for the purpose of simplification of the explanation of the structure, there is shown the use of a single memory module group 2. However, actually, a plurality of memory module groups 2 may often be provided. FIG. 4 shows an embodiment in which a plurality of memory module groups 2 are provided, and the memory controller 6A in FIG. 1 is supplemented. In the memory controller 6A, at the output side of the selector 14 for selecting serial data which are mutually different in delay time, there is provided another selector 16 for selecting memory module groups 2-1, ..., 2-x, where x is a natural number. Also, at the sending out side of the clock signal of the memory control circuit 10, there is provided a further selector 17 for selecting memory module groups 2-1, ..., 2-x. These selectors 16 and 17 are arranged to receive on a common basis module group selection signal from a module group information register 18 which serves to hold module group information supplied from the microcomputer 3A, so as to select a data line LDAT-j and a clock signal line LCLK-j to a desired memory module group 2-j, where j is an integer 1 to x . In the case where a plurality of memory module groups 2-1, ..., 2-x are provided, a plurality of data lines LDAT-1 to LDAT-x and a plurality of clock signal lines LCLK-1 to LCLK-x may be connected into a star connection, respectively. To effect a writing operation on the semiconductor disk device 1A mentioned above, there is a need to supply from a host computer, not shown, to the semiconductor disk device 1A a command including information such as a header No., a cylinder No., a top sector No., the number of writing sectors and the like, and an additional command for instructing a writing operation. After issuance of these commands, data are transferred after the lapse of a predetermined time corresponding to the seek time, the rotation period and the like. Upon receipt of the commands through the host interface 4, the microcomputer 3A decodes and converts the commands into control information accessible to a memory module 2i-j, the control information including an indication designating a memory module 2i-j and an address designating a sector in that memory module 2i-j, into which data is to be written, where i is a natural number between 1 and n , inclusive, and j is a natural number between 1 and x , inclusive. The control information thus converted includes delay information 3Aa as to the memory module 2i-j and module group information. On the other hand, transmitted data is fed through the host interface 4 to the buffer memory 5. The microcomputer 3A first feeds delay information 3Aa and the associated writing signal to the delay information register 15 within the memory controller 6A to hold the same therein so as to define the selection state of the selector 14, and on the other hand, feeds module group information and the associated writing signal to the module group information register 18 within the memory controller 6A to hold the same therein so as to define the selection states of the selectors 16 and 17, thereby setting up a transfer pulse to a desired memory module 2i-j. Thereafter, the microcomputer 3A feeds control information to the memory control circuit 10 within the memory controller 6A to start the transfer. Upon receipt of the control information, the memory control circuit 10 outputs serial data for control, which consists of an address, a control signal for instructing writing and the like, in synchronism with the clock signal. The serial data for control outputted from the memory control circuit 10 is phase-shifted through variable phase shift means comprising the delay stages 11-13 and the selector 14, and then outputted via the selector 16 to a desired data line LDAT-j. On the other hand, the clock signal outputted from the memory control circuit 10 is outputted via the selector 17 to a desired clock signal line LCLK-j. Thus, a desired memory module 2i-j recognizes that a sector of data will be transferred thereto and waits for the transferred data. Subsequent to sending out the controlling serial data, the memory control circuit 10 is operative to read a sector of data out of the buffer memory 5 and practice a parallel-to-serial conversion to the data thus read out. The data subjected to parallel-to-serial conversion are outputted in synchronism with the clock signal. Also at that time, the serial data for control outputted from the memory control circuit 10 is phase-shifted through variable phase shift means comprising the delay stages 11-13 and the selector 14, and then outputted via the selector 16 to desired data line LDAT-j. On the other hand, the clock signal outputted from the memory control circuit 10 is outputted via the selector 17 to a desired clock signal line LCLK-j. The memory module 2i-j, which recognizes that data will be transferred thereto, receives the transferred serial data in synchronism with the clock signal. Such a transfer on a sector-by-sector basis is repeated by the corresponding number of sectors instructed from the host computer. When the memory module to be destined is altered, while transferring, from the memory module 2i-j to the the memory module 2k-j, k is a positive integer between 1 and n , inclusive, the microcomputer 3A temporarily interrupts the data transfer to feed the delay information 3Aa and the associated writing signal to the delay information register 15 within the memory controller 6A so as to alter the selection state of the selector 14, and thereafter resume the data transfer. Also when the memory module group to be destined is altered, the similar control for adjusting the amount of phase shift of the serial data is performed. FIG. 5 is a time chart showing an example of timing of writing data from the memory controller 6A into the memory module in the semiconductor disk device according to the first embodiment. With respect to the memory module 2n-1 nearest to the memory controller 6A in the memory module group 2-1 (refer to parts (a) and (b) of FIG. 5) and up to the memory module 21-1 farthest from the memory controller 6A in the memory module group 2-1 (refer to parts (c) and (d) of FIG. 5), the phase of the transfer data is regulated in compliance with the associated memory module. Consequently, even if a deviation in timing were induced during taking the clock signal and data into the respective memory modules owing to the various kinds of causes as described earlier in connection with the background art, such a deviation will be suppressed through the above-mentioned phase regulation. Thus, as seen from FIG. 5, it is possible for the respective memory modules to receive the transferred data in a suitable timing, thereby providing sufficient set-up time and hold time. As mentioned above, according to the first embodiment, there is stored beforehand in the microcomputer 3A delay information 3Aa according to a difference in transfer timing of the clock signal and the data for each memory module 2i-j at the time of writing data from the memory controller 6A into the memory module 2i-j, and when the data is written, the delay information 3Aa is written from the microcomputer 3A into the delay information register 15 to regulate the phase of the transferred data. Thus, it is possible to provide optimum set-up time and hold time during writing of data into the memory module 2i-j. Therefore, there is no need to adapt the clock period and the like for the worst timing of memory module, thereby enabling a high speed writing of memory data. As mentioned above, the writing of data into the memory module 2i-j involves the problem in a phase relation between data and the clock signal. Since the phase relation is relative, there is a way in which the phase of the clock signal is controlled without altering the phase of data. This way may be considered as a modification of the first embodiment of the present invention. However, the clock signal is utilized throughout the semiconductor disk device, and there is frequent such a case that it is not preferable that the phase of the clock operative inside the memory controller 6A is different from that outputted to the exterior. Thus, in view of the above, it is preferable that the phase of data is controlled. (B) Second embodiment The second embodiment, in which the present invention is applied to a semiconductor disk device, will be described in conjunction with other figures of the accompanying drawings. An aspect of the semiconductor disk device according to the second embodiment resides in reading out of the memory modules. In order to simplify the explanation of the aspect, FIG. 6 shows the use of a single memory module group. In an application using a plurality of memory module groups, the FIG. 6 embodiment is not directly applicable but may be modified as seen from FIG. 4. In FIG. 6, the like elements are denoted by the same reference numerals or marks as those of FIG. 2. In FIG. 6, the semiconductor disk device 1B according to the second embodiment also comprises a memory module group 2, a microcomputer 3B, a host interface 4, a buffer memory 5 and a memory controller 6B. However, the microcomputer 3B and the memory controller 6B are different from those of the semiconductor disk device 1 shown in FIG. 2. The microcomputer 3B stores delay information 3Ba for each of the memory modules 21, ..., 2n in the case where data are transferred to the memory modules 21, ..., 2n. For example, the delay information 3Ba is stored in the form of a microprogram. When the microcomputer 3B recognizes the memory module 2i out of which data is read, the microcomputer 3B feeds the delay information 3Ba and the associated writing signal to the memory controller 6B, prior to starting of data transfer from the memory module group 2 by a memory control circuit 30 which will be described later. The memory controller 6B comprises the memory control circuit 30, which corresponds to the control circuit of the memory controller 6 in the semiconductor disk device 1 shown in FIG. 2, and a circuit 31 for receiving read data, which may comprise flip-flops, and in addition a plurality of delay devices 32, 33 and 34, a selector 35 and a delay information register 36. In the specific embodiment also, three delay devices 32, 33 and 34 are exemplarily provided. The memory control circuit 30 serves to output the serial data for control to the memory module 2i to be accessed in synchronism with the clock signal, convert the transfer data read out from the memory module 2i by the receiving circuit 31 in synchronism with the clock signal, and stores the data thus converted in the buffer memory 5 via the host interface 4, in accordance with control information outputted from the microcomputer 3B. According to the second embodiment of the semiconductor disk device, the clock signal outputted to the memory module 2i to read data out of the memory module 2i and the clock signal to cause the receiving circuit to receive data read out of the memory module 2i are different in phase from each other. Specifically, according to the second embodiment, the phase of the clock signal with which the receiving circuit receives data read out of the memory module 2i is varied from memory module by memory module. To implement such a function, there are provided three delay devices 32-34, the selector 35 and the delay information register 36. Three delay devices 32-34 are connected with each other in a cascade fashion. This cascade connection is arranged so as to receive the clock signal outputted from the memory control circuit 30, which clock signal is also sent out to the clock signal line LCLK. Thus, four clock signals, which are mutually different in phase by a predetermined unit of delay time, are obtained from the front and back stages of the cascade connection stages and the middle taps. These clock signals are fed to the selector 35 as a selection input. The selector 14 receives a delay device selection signal from the delay information register 36 and selects the clock signal according to the delay device selection signal. The clock signal thus selected is sent out to the receiving circuit 31 as a receiving clock signal. While there is no need that the unit delay time is the same as that of the first embodiment, the unit delay time is set up to such a degree that even the time difference between non-delayed clock signal and the most delayed clock signal is shorter than, for example, the half of the period of the clock signal. The delay information register 36 receives the delay information 3Ba, which was outputted from the microcomputer 3B prior to starting of the data transfer from the memory module 2i by the memory control circuit 30, and the writing signal as well. Thus, the delay information register 36 holds the delay information in accordance with the writing signal. The delay information thus held is fed to the selector 35 as the delay device selection signal. In order to read data out of the memory module 2i, the clock signal is applied to the memory module 2i. The memory controller 6B receives the data thus read. This involves problems as to a deviation in timing, which will be more severe than that of writing operation. The delay information 3Ba involved in the respective memory modules 21,..., 2n, which is stored beforehand in the microcomputer 3B, is determined taking into consideration a deviation of transfer delay on the data line LDAT and the clock signal line LCLK connected to the memory modules 21, ..., 2n, which lines are formed on a printed circuit board, a variation of the transfer delay, and the like. For example, the delay information may uniquely be determined in dependence upon where the the memory modules 21, ..., 2n are located, for example, the length of the signal lines and the like. Alternatively, the optimum delay information is determined through a measurement performed after the memory modules 21, ..., 2n are mounted. In FIG. 6, for the purpose of simplification of the explanation of the structure, there is shown the use of a single memory module group 2. However, actually, a plurality of memory module groups 2 may often be provided. While an illustration is omitted, in an application where a plurality of memory module groups are provided, there may be provided a selector or the like to select a clock signal line and a data line to which a desired memory module is coupled (refer to FIG. 4). To effect a reading operation on the semiconductor disk device 1B mentioned above, there is a need to supply from a host computer side, not illustrated, to the semiconductor disk device 1B a command including information such as a header No., a cylinder No., the top sector No., the number of reading sectors and the like, and an additional command for instructing a readout operation. Upon receipt of the commands through the host interface 4, the microcomputer 3B decodes and converts the commands into control information accessible to a memory module 2i, the control information including an indication designating a memory module 2i and an address designating a sector in that memory module 2i, from which data is to be read out. The control information thus converted includes delay information 3Ba as to the memory module 2i. The microcomputer 3B first feeds delay information 3Ba and the associated writing signal to the delay information register 36 within the memory controller 6B to hold the same therein so as to define the selection state of the selector 35, thereby setting up a clock phase to receive data from a desired memory module 2i. Thereafter, the microcomputer 3B feeds control information to the memory control circuit 30 within the memory controller 6B to start the readout transfer. Upon having received the control information, the memory control circuit 30 outputs serial data for control, which consists of an address, a control signal for instructing writing and the like, in synchronism with the clock signal which is not subjected to a phase control. This operation can be implemented with, for example, the structure of the first embodiment. The memory control circuit 30 sends out, even after sending out the controlling serial data, subsequently the clock signal not subjected to a phase control over the clock signal line LCLK to the memory module group 2. A desired memory module 2i recognizes on the basis of the controlling serial data that itself ought to perform a readout operation, and takes a standby state. Thereafter, the memory module 2i sends out data to the data line LDAT in synchronism with the incoming clock signal. The data read from the desired memory module 2i onto the data line LDAT are received by the receiving circuit 31 in repsonse to the phase-controlled clock signal outputted from the selector 35, and thereafter converted by the memory control circuit 30 into a parallel data, in the memory controller 6B. The data thus obtained are stored in the buffer memory 5 through the host interface 4. The readout data stored in the buffer memory 5 are sent out through the host interface 4 to the host computer. When data are read out of another memory module 2n within the memory module group 2, the similar processing is also effected. FIG. 7 is a time chart showing an example of a timing for reading data from the memory module in the memory controller 6B in the semiconductor disk device according to the second embodiment. With respect to the memory module 2n nearest to the memory controller 6B in the memory module group 2 (refer to parts (a) and (b) of FIG. 7) and up to the memory module 21 farthest from the memory controller 6B in the memory module group 2 (refer toparts (c) and (d) of FIG. 7), the phase of the clock signal to receive the transfer data is regulated in compliance with the associated memory module. Consequently, even if a deviation in timing for taking data into the receiving circuit 31 were induced owing to the various kinds of causes as described in connection with the background art, such a deviation will be suppressed through the above-mentioned phase regulation. Thus, as seen from FIG. 7, it is possible for the memory controller 6B (the receiving circuit 31) to receive the transferred data at a suitable timing, thereby providing sufficient set-up time and hold time. As mentioned above, according to the second embodiment, there is stored beforehand in the microcomputer 3B delay information 3Ba according to a difference in transfer timing, depending on where each memory module 2i is located, at the time of reading out data from the memory module 2i into the memory controller 6B, and when the data is read out, the delay information 3Ba is written from the microcomputer 3B into the delay information register 36 to regulate the phase of the receiving clock signal. Thus, it is possible to receive the readout data from the memory module at a suitable timing, and also to provide suitable set-up time and hold time even in the case of readout from any memory module. Therefore, there is no need to control the clock signal of the apparatus taking into consideration the worst timing of memory module, thereby enabling a high speed readout of memory data. The second embodiment may be modified such that the phase-controlled clock signal is applied to the memory modules and non-phase-controlled clock signal is applied to the receiving circuit 31. However, in view of a consistency with the situation in which non-phase-controlled clock signal is applied to the memory modules during writing data into the memory module, and also a possibility that a period from the time point when the clock signal is send out to the time point when data is received is elngated, it is preferable that as in the second embodiment, non-phase-controlled clock signal is applied to the memory modules and the phase-controlled clock signal is applied to the receiving circuit 31. In a similar fashion to that of the first embodiment, it may be also a modification that the readout data is controlled in phase and the clock signal from the memory control circuit 30 is directly applied to the receiving circuit 31. Other embodiments While the above-mentioned embodiments are to use the memory modules intending the flash type of memory, other kinds of memory are applicable. It is noted that, for example, in an application in which data writing is accomplished by means of an address line and a data line which are separately provided, there will be needed additionally means for shifting the phase of address data. Further, according to the above-described embodiments, information for timing control, such as delay information and timing information, is stored beforehand in the microcomputer. However, the system may be designed so as to store such information in the memory controller from the beginning. It is noted that the present invention is not restricted in application to the semiconductor disk device, but widely applicable to the semiconductor memory having a portion in which a plurality of memory modules are connected to a common signal line. For example, the present invention is also applicable to an apparatus in which memory module groups are directly accessed by the microcomputer, a CPU or the like. While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by those embodiments.

Claims: A semiconductor memory comprising: at least one memory module group (2) comprising a plurality of memory modules (21, 22, ... 2n); a memory controller (6A, 6B) coupled with said memory module group through a data line (LDAT) and a clock signal line (LCLK); and a microcomputer (3A, 3B) coupled with said memory controller, CHARACTERIZED IN THAT said microcomputer stores delay information (3Aa) for each of said memory modules, outputs the delay information and a writing signal to said memory controller, said memory controller having a plurality of delay devices (11, 12, 13), said memory controller selecting one of said delay devices in accordance with the delay information. A semiconductor memory according to claim 1, characterized in that said memory controller is adapted to phase-shift data, which are output to one of said semiconductor memory modules, to be accessed in synchronism with a clock signal.

Inventors: MIYATA MANABU, OHNO YASUHIRO, MIYATA, MANABU, OHNO, YASUHIRO, Miyata, Manabu, c/o Oki Elec. Ind. Co. Ltd., Ohno, Yasuhiro, c/o Oki Elec. Ind. Co. Ltd.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1995
Main classification: G06F13
IPC codes: G06F12, G06F13, G06F1, G11C11