Monolithic semiconductor device having an edge structure and method for producing said structure

Abstract: A monolithic semiconductor device having an edge structure, which comprises, on a substrate of a first type of doping, a control region (1) of a second type of doping, which is provided with an edge region (2), and a power region of a second type of doping, the particularity whereof resides in that in the edge region at least one channel (8, 9, 10, 11) is provided which is adapted to divide the edge region (2) into regions that are electrically isolated from each other (2, 2a, 2b; 2c, 2d), the region at the channel being covered with a field plate (6). A method for producing the edge structure in combination with the execution of the monolithic device is also disclosed herein.

Description: The present invention relates to a monolithic semiconductor device having an edge structure and to a method for producing said structure. In integrated circuits wherein a power device and a logic controller are integrated in the same chip, the need arises to arrange, inside the control region (linear region), for a division of the substrate voltage, for example to obtain a power supply from said voltage. The voltage divider used for this purpose is provided by means of a resistor connected between the substrate and the control part. If the device operates at medium to low substrate voltages, the divider is provided easily, since either edge structures are not required or flat termination structures are required. The problem instead arises when the device operates at high substrate voltages (>600V) and it is therefore indispensable to use as edge a high-resistivity ring that surrounds the entire device. Figure 1 shows the associated problems. This figure shows a P-type region that provides the resistor, the control region with its edge structure, and the equipotential ring that is at the potential of the substrate. The edge structure of the control region is provided by means of a P-type ring that is in contact with the isolation region between the linear region and the power region. Since the high-voltage resistance is of the same type as the edge (P type), the problem arises of passing through said edge without altering the features of said divider. This is due to the fact that in electrical terms, edge crossing is equivalent to placing a resistor between the end of the high-voltage resistor and the ground (since the edge is usually ground-biased). Figure 2 shows this problem in the case in which one wishes to obtain a power supply from the substrate voltage. This figure shows that the voltage at the node A is not produced by the voltage across the Zener diode but by a division of the voltage between the high-voltage resistor and the edge resistor, and this is not desirable. To avoid affecting the value of the voltage on the node A, the edge ring should have an extremely high resistivity, which is obtained by acting on the doping of the ring to avoid current losses, but this is not possible, since its value determines the amount of the depletion of the annular region and therefore of its operation. There are therefore two distinctly contrasting requirements: to provide a very high resistivity of the ring without at the same time altering the doping level of the ring. Junctions produced in planar technology have, in inverse biasing conditions, a different distribution of the electric field between the bulk region and the edge region. In this last region, the electric field can be reached at a biasing voltage that is lower than the breakdown voltage in the bulk. Various technological solutions have been used to reduce the high electrical field value in the edge region, all having the purpose of appropriately controlling the depletion of the doped region that is adjacent to the junction to be protected, so as to avoid local increases in the electrical field from causing early breakdowns with respect to the breakdown in the flat junction region. The various solutions include so-called field plates which, if sized appropriately above the edge region, allow to guide the depletion region gradually from the bulk of the device towards the surface regions. Biplanar or triplanar structures can improve the extension of the depletion region. Other methods for guiding the depletion region reside in using high-resistivity rings to be placed in contact with the main junction to be protected, so as to force said depletion region to extend over wider regions and thus expand spatial charge distribution. These structures become necessary for devices that must withstand high voltages, where a plurality of rings, arranged in order of increasing resistivity, can be used for this purpose. In monolithic semiconductor devices, the isolation of the components that constitute the driver circuits and of the power components can be provided with the junction isolation method. The isolation region delimits and isolates the wells for containing low- and high-voltage components. For integrated structures that must withstand high substrate voltages, the edge structure is provided in a position that is adjacent to the outer isolation region. The termination region surrounds the isolation region and delimits the entire structure inside which the low- and high-voltage components are integrated. The production of a high-voltage resistor entails the occupation of a large silicon area since, in order to avoid the above mentioned drawbacks, it is necessary to terminate the resistor outside the P region used for termination. This requires the provision of an edge that is similar to the one used to terminate the device, and the two terminations must be at such a distance as to ensure electrical isolation at the operating voltage. Furthermore, the connection between the resistor and the control region must be performed by means of a field plate that passes through a high-voltage epitaxial region. Voltage withstanding ability is therefore determined by the thickness of the underlying oxide. Another drawback entailed by the use of the P-type edge ring is that it places a resistor between the P-type region that provides the control region and the P-type region that provides the base of the power device. In other words, since the isolation region is normally connected to the ground, a resistor is placed between the base of the power device and the ground, with consequent loss of current. This drawback is shown in figure 5. US-A-4,567,502 discloses a planar type semiconductor device with a high breakdown voltage in which the edge region is made of floating rings in order to protect the device at high voltages. EP-A-307032 discloses a manufacturing process for a monolithic semiconductor device having multiple epitaxial layers with a low concentration of impurities in which however the edge region is not affected by channels and a voltage divider is not integrated while preserving the electrical characteristics of the edge region. EP-A-632503 discloses an integrated edge structure for high voltage semiconductor devices wherein no voltage divider is integrated while preserving the electrical characteristics of the edge region of the device. The principal aim of the present invention is therefore to provide a monolithic semiconductor device having an edge structure, which allows to divide the substrate voltage even in case of high operating voltages. Within the scope of this aim, an object of the present invention is to provide a monolithic semiconductor device having an edge structure, which allows to give the edge ring an infinite resistivity without affecting the doping of said ring. Another object of the present invention is to provide a monolithic semiconductor device having an edge structure, which allows to reduce silicon area occupation. Another object of the present invention is to provide a monolithic semiconductor device having an edge structure, which allows to eliminate current losses. Another object of the present invention is to provide a method for producing an edge structure according to the invention for integrating low-voltage and high-voltage components in monolithic semiconductor devices. Another object of the present invention is to provide a monolithic semiconductor device having an edge structure and a method for producing said structure that are highly reliable, relatively easy to provide, and at competitive costs. This aim, these objects, and others which will become apparent hereinafter are achieved by a monolithic semiconductor device having an edge structure, as defined in claim 1. figure 1 is a view of a voltage divider for a monolithic semiconductor device, in the case of a high operating voltage, executed according to a conventional method used in the case of a medium-low operating voltage; figure 2 is an electrical diagram of the embodiment shown in figure 1, which also applies to the solution according to the invention; figure 3 is a sectional view of a conventional solution for integrated structures that must withstand high substrate voltages; figure 4 is a view of a conventional solution for a power device, illustrating a first drawback thereof; figure 5 is a plan view of the integrated device, according to the conventional solution, illustrating a second drawback; figure 6 is a view of a first embodiment of the monolithic semiconductor device having an edge structure according to the invention, the circuital embodiment whereof is similar to the one shown in figure 2; and figure 7 is a view of a second embodiment of the monolithic semiconductor device having an edge structure, not forming part of the claimed invention. Figures 1 to 5 show conventional arrangements. In particular, figure 1 shows a voltage divider executed by connecting a high-voltage resistor 4 between a control region 1 provided with an edge 2 and an equipotential ring 5, which is at the same potential as the substrate. Figure 2 is a view of the circuit embodiment of figure 1, if a supply voltage is drawn from the substrate of the device, by means of a voltage division. In this figure, the reference numeral 4 designates the high-voltage resistor, the reference numeral 102 designates the edge resistor, 103 designates the Zener diode, 104 designates the substrate voltage division, and 105 designates the connection to the substrate. To avoid affecting the value of the voltage at the node A, the edge resistor 102 should have an extremely high resistivity, but this contrasts with the need to avoid modifying the doping level that determines the operation of the device. Figure 3 is a view of an integrated structure adapted to withstand high substrate voltages. In this case, the edge region 2 is connected to the P-type control region 1. The reference numeral 3 again designates an N-type region that provides the collector of a power device. Figure 4 is a view of the necessary connection, according to a conventional solution, between the high-voltage resistor 4 and the linear region 1, which is provided by means of a field plate 106, in order to avoid the above mentioned drawbacks; however, this entails the problem of a considerable silicon area occupation. Figures 5 shows a drawback, described earlier, that arises from using the P-type ring as an edge. This drawback consists in placing a resistor 110 between the P-type linear region 1 and the P-type base region 7 of the power device, with consequent loss of current. The edge region in this figure is designated by the reference numeral 2. Figure 6 shows a preferred embodiment of the present invention. In this figure and in figure 7, elements that are identical to those shown in the preceding figures are given the same reference numerals. In this figure, the reference numeral 1 designates a linear region that provides the control part of the device, the reference numeral 3 designates a region that provides the collector of the power device, which coincides with the substrate of the silicon plate and in which the potential can reach high voltage values, and the reference numeral 2 designates the edge region. The high-voltage resistor 4 is integrated in the device by making it penetrate inside a U-shaped recess 12 formed in the control region 1. This recess has an N-type doping, since it is the same substrate region 3. In this manner it is not necessary to produce an edge for the terminal part of the resistor as well, as instead indicated in figure 4. The opposite end of the high-voltage resistor 4 is connected to the equipotential ring 5, which is at the same potential as the substrate. The edge region is cut in two points, forming two channels 8 and 9 so as to form three contiguous edge regions 2, 2a, and 2b. The edge regions 2 and 2b (of the P type) are at the same potential as the control region 1, since they are still connected thereto, whereas the region 2a, which is also of the P type, is at the same potential as the high-voltage resistor 4 but is no longer connected to the ground. A ground-biased field plate 6 covers the N-type region 3 formed between the regions 1, 2a, and 4, so as to ensure its voltage withstanding ability. The field plate 6 is also arranged at the channels (cuts) 8 and 9 formed in the edge region 2 (2, 2a, and 2b) so as to avoid the escape of field lines at a high potential through the slits thus formed, with consequent increase of the electrical field at the surface and possibility of reaching the critical value. The cuts 8 and 9 formed in the edge region, thus forming the regions 2, 2a, and 2b, allow to avoid electrical continuity between the different regions, thus isolating the regions from each other but maintaining the structure functionality. N-type regions, i.e., regions having the same doping as the region 3, are provided inside the cuts 8 and 9. Circuitally, the two cuts 8 and 9 formed in the edge region are equivalent to causing the edge resistor, shown in figure 2, to have an infinite value, without however modifying the doping of said edge. Figure 7 is a view of a second embodiment not forming part of the claimed invention, which is adapted to overcome the above mentioned drawback, which relates to the use of the P-type edge ring. This use in fact entails the drawback of placing a resistor between the P-type region that provides the control region and the P-type region that provides the base of the power device, with consequent loss of current. With the second embodiment, shown in figure 7, the isolation between the control region (linear region) 1 and the base region 7 of the power device is achieved by providing cuts on the region that forms the edge at the separation channel between the regions 1 and 7, so as to divide the edge into two regions 2c and 2d that are adjacent but electrically isolated. In this second embodiment, too, a field plate has been used at the cuts 9, 10, and 11. By using the same process sequence used to integrate high- and low-voltage components in power structures with vertical integration, it is possible to provide an open edge structure, as explained earlier, without introducing any additional operating stage. In detail, the stages of the process are the following. First of all, the isolation region is formed; then the edge region is produced by implanting and diffusing P-type dopant together with the isolation. The configuration of the edge region is provided by producing cuts having appropriately chosen sizes. In particular, the width of each one of the cuts must be negligible with reference to the dimensions of the edge region. The region that is opaque to the P-type implanting must have such dimensions as to prevent the occurrence of the electrical continuity of the edge ring by lateral diffusion, but at the same time must not allow the field lines to affect the surface regions. Therefore, the cut must be more than twice as large as the lateral diffusion of the edge layer. An N-type implanting stage, performed in the region that is opaque to the P-type edge implanting and before forming the region 1, improves the isolation between the edge regions 2, 2a, and 2b. This N-type implanting also reduces the depletion in the cutting region along the junction between the regions 2 and the region 3, preventing lateral punch-through phenomena from altering the operation of the structure. In practice it has been observed that the edge structure according to the invention and the method for producing said structure fully achieve the intended aim, since said structure, executed with the method described above, allows to give the edge resistor an infinite value without altering the doping level of said edge, thus allowing to provide a division of the substrate voltage even when the operating voltages are very high. As shown, the method for providing said edge structure can also be easily executed, since it is possible to perform the above mentioned cuts in the edge structure without having to resort to additional stages with respect to those normally used. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: A monolithic semiconductor device having an edge structure, the device comprising, on a substrate (3) of a first type of doping, a control region (1) of a second type of doping which is provided with an edge region (2) having the second type of doping, and a power region disposed externally to said control region; characterized in that in said edge region at least two channels (8, 9; 10, 11) are provided, said edge region being thereby adapted to form a central edge region and two lateral regions to divide said edge region into regions that are electrically isolated from each other (2, 2a, 2b; 2c, 2d), at least said two channel regions being covered with a field plate (6) and in that a voltage dividing resistor (4) passes through said control edge region, said resistor being connected to said power region by means of a first end and to said control region (1) by means of a second end, said second end being inserted in a recess (12) formed in said control region (1), said recess having a first type of doping, said resistor (4) having a second type of doping. The device according to claim 1, characterized in that said first and second types of doping are respectively an N-type doping and a P-type doping. The device according to claim 1, characterized in that when the device is in use said field plate (6) is ground-biased. A method for producing a monolithic semiconductor device having an edge structure and integrating low- and high-voltage components, as claimed in claim 2, characterized in that it comprises the steps of: forming an isolation region adapted to delimit a region for containing high-voltage components and a region for containing low-voltage components; providing an edge region (2) by implanting and diffusing P-type dopant, forming at least two channels (8, 9; 10, 11) wherein said P-type dopant is not implanted and diffused; implanting N-type dopant in the region of said at least two channels; and forming a control region (1), said region of said at least two channels being covered by a field plate.

Inventors: AIELLO NATALE, LA BERBERA ATANASIO, LEONARDI SALVATORE, AIELLO, NATALE, LA BERBERA, ATANASIO, LEONARDI, SALVATORE
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO - CORIMME
Application year: 1995
Main classification: H01L27
IPC codes: H01L21, H01L27