Memory device having improved yield and reliability

Abstract: The present invention relates to a memory device of the type comprising: at least one first (M1) and one second (M2) memory cell array for storage respectively of a first plurality of user data and a second plurality of error identification and correction data, first (D1) and second (D2) decoding means connected respectively to the first (M1) and second (M2) memory cell array for selection and reading respectively of the first and second pluralities of data, error identification means (L1) coupled to said first (D1) and second (D2) decoder means, and error correction means (C1,C2,EN) operationally connected to said first (D1) and second (D2) decoder means and to said error identification means (L1), and characterized in that it comprises at least one logical control unit (L2) operationally connected to the second decoder means (D2), to error identification means (L1) and to the error correction means (C1,C2,EN) to enable said second decoder means (D2) and said error correction means (C1,C2,EN) if an error is detected by the error identification means (L1).

Description: The present invention relates to a memory device and in particular the EEPROM flash type with improved output and reliability. As known, the main problems encountered in the production of a flash EEPROM memory device concern production process output and reliability of the final product. By the term 'yield' is indicated a parameter which specifies quantitatively the number of memory devices produced which operate in a manner conforming to design specifications when subjected to electrical testing. The causes which lead to less yield of memory devices are mainly defects in the so-called cell array comprising a plurality of memory cells in which are stored binary data. This matrix occupies a large part of the area of the integrated memory device. The defects which decrease the yield of the device can be divided in two main classes: defects due to pairs of rows included in the cell array whose metallizations are short-circuited among them, and defects due to individual cells having electrical characteristics incompatible with those necessary to have correct operation of the device containing them. To remedy the malfunctions caused by the defects belonging to the first class there is used the so-called 'row redundancy', which uses supplementary rows inside the cell array. To remedy the malfunctions caused by the defects belonging to the second class there is used the so-called 'column redundancy', which uses supplementary columns inside the above mentioned array. The principle on which is based row and column redundancy is essentially the same, i.e. replacement of the damaged element by a corresponding redundant element. The 'replacement' takes place by using a logical circuitry having a great variety of different diagrams which are considerably affected by the decisions made concerning the architecture of the entire device. Although advantageous in some ways, row and column redundancy has a serious shortcoming due to the every greater complexity of the logical networks which manage them as the size of memory devices increases. The reasons for this are understandable when it is recalled that selection of a redundant element must be done by comparing row and column address signals supplied at input to the device with row and column address signals memorized in a special register within the device. The latter signals correspond to the locations of the rows or columns of the array which it is intended to replace. To obviate the same type of defects which are presently remedied through the use of column redundancy there can be used the so-called error correction codes. In this case, if p indicates the probability that an individual memory cell will be defective it is possible to plot a curve representing the behavior of the probability of the events not reparable for a device containing this cell, as a function of the parameter p. In FIG. 1, for example, are shown two curves representing the behavior of the probability of the irreparable events for a memory device. The first curve was obtained by utilizing a redundancy system using four additional columns for each memory block comprising 2 10 rows and 2 10 columns. The second curve was obtained utilizing an error correction code of the so-called Hamming type with 2 7 bits of user data and 2 3 bits of parity control capable of correcting an individual error. It is specified that point A shown in FIG. 1 relates to a situation in which the value of the probability p is approximately 0.8*10 -5 . To a probability of this value corresponds a yield of 20% produced by the column redundancy while the yield obtainable utilizing the error correction code is practically 100%. It is appropriate to state that this comparison is correct if the assumption of defects uniformly distributed on the cell array is correct. It is also true that the term 'reliability' indicates the ability of a device to remain in conformity with the design specifications in time. In the case of flash EEPROM memory devices reliability is particularly important because these devices must be able to keep the binary data stored in them whole over long periods of time. At the same time it must be possible to perform an adequate number of write and delete operations on the cells. It is also appropriate to recall that the memory cell comprises an individual floating-gate MOS transistor of which it is possible to control the threshold voltage by injection of charges through a gate oxide. On the basis of the above remarks it is understandable how over time there will be dispersion of the characteristics of the memory cell and hence increase in the probability of committing errors by the device. Indeed, the currents traversing the gate oxide produce the effect of worsening its dielectric characteristics with the result that the size of the interval separating the threshold voltage of a programmed cell from that of an unprogrammed cell tends to diminish. In practice, the situation found is the type shown in FIG. 2. In this FIG. are shown the behaviors of the threshold voltages (V TLP and V TLV ) respectively of a programmed cell and an unprogrammed cell as a function of the number of deletion-programming cycles to which the memory device was subjected. It is specified that the point of intersection B between the two behavior curves corresponds to the number of deletion-programming cycles beyond which the programmed memory cell loses its ability to be used as a memorization element. Point B corresponds therefore to the limit of usability of the memory devices in which is included this cell. An aspect which it is appropriate to recall concerns distribution of the memory cells which lose their data storage ability in the array. Indeed, it has been found that this distribution is uniform with good approximation. This is coherent with the interpretation which can be given of the aging process of the gate oxides produced by the current transport phenomena. An error correction code acting downstream of the circuits which read the data in the memory devices is capable of remedying this situation within the limits of the protection ability given it during design and is thus usable for increasing the reliability of the device. A memory device according to the preamble of claims 1 and 6 is disclosed in US-A-5,063,565 which has a service processor including a local memory. The service processor performs error correction to write corrected data in the data memory after discovering an error. Further memories including error correction solutions are disclosed in EP-A-0 381 405, US-A-5,056,095 and US-A.4,612,640. The technical problem underlying the present invention is to provide a memory devices having high yield and reliability. The technical problem is solved by a device of the type indicated above and defined in independent claim 1. Further enhancements are provided by the subclaims 2 to 5. A corresponding method is defined in independent claim 6. The characteristics and advantages of the device in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of non-limiting example with reference to the annexed drawings. In the drawings: FIGS. 1 and 2 show the behavior of characteristic magnitudes of a memory devices, and FIG. 3 shows a block diagram of a memory device provided in accordance with the present invention. With reference to the FIGS., FIG. 1 indicates schematically as a whole a memory device with improved yield and reliability and provided in accordance with the present invention. With reference to FIG. 3 the memory device comprises at least one first cell array M1 and one second cell array M2 organized in rows and columns. In these first arrays M1 and M2 are stored respectively a first plurality of user data organized in memory words comprising e.g. 4 bits and a second plurality of identification and error correction data organized in memory words comprising e.g. 3 bits while each bit is memorized in a different memory cell. With each user data word is associated an identification and error correction word. These first and second cell arrays M1 and M2 respectively are connected to first and second decoding means D1 and D2 respectively which select the individual memory cells on the basis of row and column address signals which they receive at input. Specifically the first decoder means D1 comprise a first row address signal decoder circuit RD1 and a first and second column address signal decoder circuits CD1 and CD2 respectively. The second decoder means D2 comprise a second row signal address decoder circuit RD2 and a third column signal address decoder circuit CD3. The first decoder means D1 are also connected to a signal generator GEN which receives at input the user data and generates at output parity bits which are associated each with an individual memory word included in the first array M1. These parity bits have the purpose of allowing detection of an individual error which could occur in the user data word. The first D1 and second D2 decoder means are also cascade connected respectively to a first S1 and a second S2 sense amplifier designed to amplify and read the bits stored in the memory cells selected by the decoder means. In turn, the first S1 and second S2 sense amplifiers are cascade connected to a parity control circuit L1. Again with reference to FIG. 3 the memory device comprises also a first C1 and a second C2 error correction code cascade connected together and to the parity control block L1. The second error correction circuit C2 is also equipped with a first input terminal connected to an output terminal of the first sense amplifier S1. In the memory device is also included at least one logical control unit L2 having at least one input terminal and at least one first, one second and one third output terminals. Specifically the first input terminal of the logic unit L2 is connected to an output terminal of the parity control block L1. The first and second output terminals of the logical control unit L2 are connected respectively to a second input terminal of the error correction circuit C2 and to inputs of the second decoder means D2. Lastly the memory device comprises a coder circuit EN capable of generating an error correction code and having a first and a second input terminals and a first and second output terminals. The first and second input terminals of the coder circuit EN are connected respectively to the third output terminal of the logical control unit L2 and to an output terminal of the error correction circuit C2. The first and second output terminals of this coder circuit EN are connected respectively to an input terminal of the signal generator circuit GEN and to another input terminal of the second decoder means D2. There is now described operation of the memory device in accordance with the present invention with reference to an initial state in which the logical control unit L2 keeps disabled the coder circuit EN, the second error correction circuit C2, the second decoder means D2 and the second sense amplifier S2, whose outputs must remain constantly at low logical level to avoid altering the parity control done by the block L1. In this manner the cells included in the second array M2 are protected from all those gate and drain stress phenomena which alter their functionality. It is also specified that during memorization in the first array M1 of the parity bit supplied by the generator GEN the inputs of the coder circuit EN must all be kept at low logic level so as not to influence the generator. During reading of the memory device the parity control block L1 provides only for parity control. If the parity is respected this block generates a digital signal S3 which is at low logical level. In this case the logical control unit L2 continues to keep disabled the coder circuit EN, the second correction circuit C2, the second decoder means D2 and the second sense amplifier S2. When an individual error is verified the parity of the memory word which is read at that moment is violated and the digital signal S3 goes to a high logic level. This transition is received by the logical control unit L2 which thenceforth activates the portion of the memory device designed to perform error correction. Once this portion has been activated the digital signal S3 assumes the meaning of double-error detector, meaning that it derives from the structure of the error correction code used and which responds to a logic of the type illustrated below. It is specified that the problem of recovering the memory word which first exhibited an error can be solved only outside the memory device because the data memorized up to occurrence of the error are only sufficient for detection of the error. Concerning the error correction code to use, a reasonable compromise between protective ability of the memory device and incidence of the parity bits can be found by choosing e.g. a code of the so-called Hamming type. This code uses 136-bit memory words of which 128 are user bits and 8 are parity bits and is capable of correcting individual errors. In the device described here this code is used to complete in succession the two operations of detection and correction of the errors, having memorized initially together with each user data word a parity control digital signal allowing detection of individual errors. In this manner all the memory cells included in the second array M2 are protected from aging. Indeed, these cells are employed only after an individual error has been detected. When the first individual error has occurred the parity control digital signal together with the other error identification and correction digital signals serves as a double-error detector. This can be extremely useful for having data on the time interval beyond which the memory device loses its reliability characteristics. To better clarify the above remarks it is appropriate to analyze a numerical example having recourse to the Hamming code C(7.4) where 7 is the length of the complete memory word (excluding the parity control digital signal) and 4 is the length of the user data word. This code is represented by a generating matrix G and a parity matrix H as follows. and The correspondence between the user data words and the code words obtained by the coding operation can also be represented in table form as follows. The distance of this code, i.e. the length of the error identification and correction words is 3. The code is thus able to correct individual errors. If to the user data word is added another parity control digital signal (even parity) on the code words there is obtained a correspondence such as that shown in the following table. In this case the new parity matrix assumes the expression: which gives rise to the following form of a vector denominated 'syndrome' which is calculated by the parity control block L1. An individual error necessarily alters the parity and hence produces a syndrome vector characterized in that it has the component S3 equal to 1. In this type of case the data associated with the remaining components of the syndrome vector allows making the error correction by using appropriate algorithms whose structure depends on how the code is generated. In the case in point the coding has been done so as to generate the code in a systematic and cyclic form. A double error on the other hand leaves the component S3 of the syndrome vector at zero but produces at least a 1 on the remaining components so that the error can be detected but not corrected. Supposing it is wanted to memorize the user data word u =(0101), the identification and error correction word associated therewith is u ceck =(100), to which corresponds a code word w =0101100). Adding the overall parity control digital signal we find w * R =(10101100). If a modellable error occurs with the so-called 'error pattern' of the type e =(00001000) the reconstructed word is w * R = (10100100) which produces the syndrome vector s =(1011). The first component of the vector informs that an individual error has occurred while the remaining three components allow its correction. If on the other hand the error pattern associated with the error has for example the form e =(01000001), the syndrome vector is s =(0100). In this case the first component of the vector informs that an incorrigible double error has occurred. Indeed, proceeding with the same algorithm employed for correcting the individual error one would reach the word (1101001) which belongs to the code but is not the starting word.

Claims: A memory device comprising: at least one first (M1) and one second (M2) memory cell array for storage respectively of a first plurality of user data and a second plurality of error identification and correction data; first (D1) and second (D2) decoding means connected respectively to the first (M1) and second (M2) memory cell array for selection and reading respectively of the first and second pluralities of data; error identification means (L1) coupled to said first (D1) and second (D2) decoder means; at least one logical control unit (L2) connected to the error identification means (L1) and receiving a digital signal (S3) from said error identification means (L1) if an error is detected by the error identification means (L1); characterized in that said logical control unit (L2) is connected to the second decoder means (D2) and in that it further comprises: first error correction means (C1) connected to said error identification means (L1) ; second error correction means (C2) having a first and second input connected to said first error correction means (C1) and said logical control unit (L2) and enabled after an error has been detected by the error identification means (L1), said second error correction means (C2) having an output connected with a data input/output; and a coder circuit (EN) enabled by said logical control unit (L2) and having an output connected to said second decoder means (D2), said coder circuit (EN) generating an error correction code. Device in accordance with claim 1 and characterized in that the logical control unit (L2) comprises at least one input terminal and at least one first, one second and one third output terminals. Device in accordance with claim 2 and characterized in that the first input terminal of the logical control unit (L2) is connected to at least one output terminal of the error identification means (L1). Device in accordance with claim 2 and characterized in that the first and third output terminals of the logical control unit (L2) are connected to inputs of the error correction means (C1,C2,EN). Device in accordance with claim 2 and characterized in that the second output terminal of the logical control unit (L2) is connected to inputs of the second decoder means (D2). A method for error identification and correction in a memory device comprising: at least one first (M1) and one second (M2) memory cell array for storage respectively of a first plurality of user data and a second plurality of error identification and correction data; first (D1) and second (D2) decoding means connected respectively to the first (M1) and second (M2) memory cell array for selection and reading respectively of the first and second pluralities of data; error identification means (L1) coupled to said first (D1) and second (D2) decoder means; first error correction means (C1) connected to error identification means (L1); at least one logical control unit (L2) connected to the second decoder means (D2) and the error identification means (L1) and receiving a digital signal (S3) from said error identification means (L1) if an error is detected by the error identification means (L1); characterized by the steps of: enabling a second error correction means (C2) through said first error correction means (C1) and said logical control unit (L2) after an error has been detected by the error identification means (L1), connecting said second error correction means (C2) with a data input/output; and enabling with said logical control unit (L2) a coder circuit (EN) to generate an error correction code and connecting the coder circuit (EN) to said second decoder means (D2).

Inventors: BRANCHETTI MAURIZIO, CAMPARDO GIOVANNI, GOLLA CARLA, BRANCHETTI, MAURIZIO, CAMPARDO, GIOVANNI, GOLLA, CARLA
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: G06F11
IPC codes: G06F11