A COMPUTER SYSTEM HAVING A BRIDGE BETWEEN BUSES

Abstract: A computer system having an ISA bus (32) and a PCI bus (30) is provided with a PCI to ISA bridge (34) having certain imbedded functions performed by PCI slaves (64-68) on the bridge. In order to implement the bridge in slow CMOS technology, the PCI control signals are latched on the bridge. Since the PCI slaves on the bridge cannot respond with control signals on the PCI bus fast enough to satisfy the PCI bus protocol due to this latching, a logic device (70) is provided on the bridge. The logic device monitors the unlatched master-slave control signals carried on the PCI bus, and in appropriate situations, drives the control signals on the PCI bus (within the time specified by the PCI bus protocol) that the PCI slaves would normally drive but are unable to within the time necessary to meet the PCI bus protocol.

Description: A COMPUTER SYSTEM HAVING A BRIDGE BETWEEN BUSSES BACKGROUND OP THE INVENTION Field of the Invention The present invention relates to digital computer systems, and in particular to a bus interface (a bridge) between two busses. Description of Related Art In computer systems, electronic chips and other components are connected with one another by buses. A variety of components can be connected to the bus providing intercommunication between all of the devices that are connected to the bus. One type of bus which has gained wide industry acceptance is the industry standard architecture (ISA) bus. The ISA bus has twenty-four (24) memory address lines which therefore provides support for up to sixteen (16) megabytes of memory. The wide acceptance of the ISA buβ haβ resulted in a very large percentage of devices being designed for use on the ISA bus. However, higher-speed input/output devices commonly used in computer systems require faster buses. A solution to the general problem of sending and receiving data from the processor to any high-speed input device is a local bus. Unlike the ISA bus, which operates relatively slowly with limited bandwidth, a local bus communicates at system speed and carries data in 32-bit blocks. Local bus machines remove from the main system bus those interfaces that need quick response, such as memory, display, and disk drives. One such local bus that is gaining acceptance in the industry is the peripheral component interconnect (PCI) buβ. The PCI buβ can be a 32 or 64-bit pathway for high-speed data transfer. Essentially, the PCI bus is a parallel data path provided in addition to an ISA bus. The system processor and memory can be attached directly to the PCI bus, for example. Other devices such as graphic display adapters, disk controllers, sound cards, etc. can also attach directly or indirectly (e.g., through a host bridge) to the PCI bus. A bridge chip is provided between the PCI bus and the ISA bus in order to provide communication between devices on the two buses. The bridge chip eβsentially translates the ISA bus cycles to PCI buβ cycles, and vice versa. Many of the devices attached to the PCI bus and the ISA bus are "master" devices that can conduct processing independently of the bus or other devices. Certain devices coupled to the buses are considered to be "slaves" or "targets" that accept commands and respond to requests of a master. Many devices are able to serve as both a master and a slave in certain circumstances. It is desirable to provide the bridge chip between the PCI bus and the I S A buβ with certain functionality, such as scatter/gathering, integrated drive electronics (IDE) interfacing, PCI arbitration, etc. For at least some of these purposes, the bridge chip contains slaves. These slaves need to respond to the PCI buβ according to the PCI bus protocol, set forth in the PCI Specification, herein expressly incorporated by reference. However, to provide the desired functionality in the bridge chip within the specified response time required by the PCI bus is problematical if the bridge chip is implemented in a relatively inexpensive and slower technology, such as a 0.8 micron CMOS technology. The problem arises due to the need to latch the signals that are received from the PCI bus as inputs to the bridge chip as well as those signals sent to the PCI bus from the bridge chip to allow the slaves implemented in the slower technology to make use of the signals. The two clock latency created by the latching is incompatible with the PCI bus protocol. SUMMARY OP THE INVENTION There is a need for a computer system which uses a bridge chip that provides desired functionality, which can be implemented in a relatively slower technology, but is able to maintain the PCI bus protocol. Accordingly, the invention provides a computer system comprising a first bus, a second buβ carrying master-slave control signals and having a specified bus protocol, at least one master coupled to the βecond buβ, and a bridge coupled between the firβt and βecond buses, the bridge including an internal latched third bus carrying latched master-slave control signals, at leaβt one slave, a latch coupled between the second and third buses for latching the master-βlave control signals received from the βecond bus and the latched master-slave control signals received from the third bus, and a logic device coupled between the second and third buses, the logic device monitoring the states of the control signals on the βecond buβ and driving at leaβt one of the control signals on the second buβ according to the buβ protocol in response to certain predetermined states of the monitored control signalβ. In a preferred embodiment of the invention the βecond bus is a peripheral controller interconnect (PCI) buβ, and the buβ protocol is a PCI bus protocol. The present invention provides the cost advantages of a bridge that can be implemented in, for example, 0.8 micron CMOS technology, since the control signals to and from the PCI bus are latched for the PCI slaves on the bridge. At the same time, however, PCI buβ protocol is maintained by t h e logic device that monitors the unlatched control signals and responds to predetermined states of the control signalβ according to the PCI bus protocol. This frees the PCI slaves from having to respond under certain circumstances with control signals on the PCI bus within the time periods specified by the PCI bus protocol. An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: BRIEF DESCRIPTION OP THE DRAWINGS Figure 1 is a perspective view of a computer system which may embody the present invention. Figure 2 is a block diagram of an embodiment of the invention contained within the computer system of Figure 1. Figure 3 is a block diagram of the bridge chip in the embodiment of the present invention. Figures 4a-f are timing diagrams of exemplary βignal transfers between the PCI bus and the bridge chip of the present embodiment for different situations. DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENTS) With reference now to the Figures and in particular with reference to Figure 1, a conventional computer, or PC, designated 10, is of the type to which the invention has particular utility. Computer 10 which preferably, but not necessarily, iβ of a type utilizing an IBM personal computer or a similar system, includes a console housing 12 in which a circuit board containing the necessary circuitry including a microprocessor and BIOS chips, controllers, random access memory and other hardware are arranged. The computer will also include a video diβplay 14 and a keyboard 16 connected to the housing 12 through cable 18. Mass storage media includes a hard disk drive within the housing and is non-accessible to the user, and user-accessible floppy disks, aβ well aβ, optionally, CD-ROM driveβ 20 and 22. Figure 2 is a block diagram of a computer system constructed in accordance with an embodiment of the present invention. The system includes a PCI bus 30, an ISA bus 32, with a plurality of ISA masters 36 and ISA slaves 38. A plurality of PCI memory slaves 40 (known as "targets" in the PCI protocol, but henceforth referred to as slaves) and PCI masters 42 are coupled to the PCI bus 30. The bridge chip 34 contains an ISA interface 44 coupled between the ISA bus 32 and an internal system bus 46. A PCI interface 48 is provided between the PCI buβ 30 and the system bus 46. The bridge chip 34 also has a DMA controller 50 and programmable I/O (PIO) registers 52. Among other functions, the bridge chip 34 provides an interface between the PCI bus 30 and the ISA bus 32. The ISA interface 44 translates ISA bus cycles into a system bus cycle for use by the bridge chip 34. Among other functions, the PCI interface 48 converts PCI bus cycles from the PCI buβ 30 into system bus cycles for the bridge chip 34. The DMA controller 50 provides DMA control of memory accesses within the system. Figure 3 is a block diagram of elements of the PCI interface 48 that allow the bridge chip 34 to be implemented in a slow technology and still respond according to the PCI protocol. It will be understood by those of ordinary skill in the art that the PCI interface 48 includes other elementβ for performing the PCI cycleβ/internal system bus cycles translation, but these other elements are not illustrated so as not to obscure the present embodiment. The PCI interface 48 iβ coupled to a plurality of PCI slaves 64, 66, 68 located on the bridge chip 34. These PCI slaves 64 - 68 perform the various desired functions that can be imbedded in the bridge chip 34, such as scatter/gather, IDE interfacing, PCI arbitration, etc. Since the bridge chip 34 iβ implemented in slow technology to provide a reasonable cost chip, the PCI slaveβ 64 - 68 are also implemented in the slow technology and cannot normally detect and respond to unlatched control signalβ on the PCI buβ 30. The PCI slaves 64 - 68 on the bridge chip 34 therefore require that the control signalβ to and from the PCI bus 30 be latched. The latching of the signals by the PCI interface 48 to and from the PCI buβ 30 is provided by a PCI latch 60, formed by conventional latches. The latch 60 iβ coupled to the PCI buβ 30 to receive a frame βignal (FRAME#), an initiator ready βignal (IRDYf); and to βend a target ready βignal (TRDYI), a βtop βignal (STOP#), and a device select βignal (DEVSELf). The latch 60 iβ alβo coupled to an internal, latched PCI bus 62 and provideβ latched versions of the above signals on the latched PCI bus 62. The latched signalβ are designated aβ L_FRAME#, L_IRDY#, L_TRDY#, L_DEVSEL# and L_STOP#. The latching of the signals in both directions adds a two clock latency to the communication cycles between the PCI master 42 and the PCI slaves 64 - 68. The PCI bus 30 is not designed to have a two clock latency and maintain the protocol. In order to overcome the latency problem brought about by the need to latch the signals in both directions, the PCI latch 48 of the present embodiment is provided with a PCI interface logic device 70 that is coupled to the PCI buβ 30. Aβ will be deβcribed in more detail in the following, the PCI interface logic device 70 monitors the external PCI control signals and the slave control signalβ and driveβ the control signals on the PCI buβ 30 according to the PCI bus protocol. The configuration of the logic device 70 is βpecific to the particular bus with which the logic device 70 is being used, βuch aβ the example of the PCI buβ 30 in thiβ illustrative embodiment. A state machine is provided for each of the STOP#, DEVSELi, and TRDY! signalβ for maintaining the PCI buβ protocol. The configuration of the state machines to perform the functions of monitoring and driving the control signalβ according to the PCI bus protocol is readily accomplished by one of ordinary skill in the art. Some of the problems that may arise due to the interfacing of the slaves 64 - 68 to the latched PCI buβ 62 include: (1) slaves stopping attempted bursts when βlave TRDYl is aββerted with external FRAME! deasβerted; (2) non-burst transfers; and (3) βlaves stopping attempted bursts when slave TRD prior to external FRAME! deaββerted, etc. Although the PCI signals and buβ protocol are well-known to those of ordinary βkill in the art, the meaning of the signals that are shown in the timing diagrams of Figures 4a-f will be briefly described. The FRAME! βignal iβ aββerted by a maβter (or "initiator") to indicate to the slaves that the maβter iβ starting a transaction. The IRDY! βignal (Initiator Ready) iβ asserted by a maβter to indicate that the master is ready to send or receive data. The DEVSEL! (Device Select) signal is asserted by a βlave to acknowledge to the maβter that the βlave iβ aware that it iβ the device βelected to perform the tranβaction with the master. The TRDY! (Target Ready) βignal iβ aββerted by a slave to indicate that the βlave (or "target") iβ ready to send or receive data. The STOP# signal is asβerted by a slave to indicate to a master that it is not able to handle a transaction. In the exemplary embodiment of the present invention, the logic device 70 takes over control of the DEVSEL!, STOP!, and TRDY! signals (those signals sent from a slave) under six different circumstances. The firβt of these is when a master 42 tries to burst to a non-bursting slave (such as PCI slave 64) with a late IRDY!. The timing diagram for this situation is provided in Figure 4a. (In all of the timing diagrams, the prefix "L_" means latched signals internal to the bridge chip 34, whereas no prefix indicates an unlatched signal external to the bridge chip 34. Also, a dashed line indicates a signal that has been driven by the logic device 70.) Since the PCI slave 64 does not know whether the transfer is a burst transfer or a non-burst transfer, the PCI slave 64 asserts L_STOP! in the fourth clock of the cycle. The STOP! βignal is sent off chip to the PCI buβ 30 in the fifth clock of the cycle. In order to βend data, the maβter 42 drives the IRDY! signal active. The maβter 42 alβo sees the asβerted STOP! on the sixth clock and therefore drives FRAME! inactive to terminate the cycle. The signal TRDY! must only be asβerted for one clock βince the PCI βlave 64 does not support a burβt tranβaction. Therefore, the PCI interface logic device 70 deasserts TRDY! on the sixth clock. After the FRAME! is deasβerted, the PCI protocol requires that DEVSEL!, TRDY! and STOP! (the βlave signals) all be deasβerted. The PCI protocol therefore requires that the STOP! and DEVSEL! signals be deasβerted in the clock after the deaββertion of FRAME!, i.e. in the seventh clock. Without the PCI interface logic device 70 of the present embodiment, these signals would not be driven inactive until the ninth clock, βince the latched L_FRAME# βignal is not seen by the PCI βlave 64 until the seventh clock, responded to in the eighth clock, and sent off chip in the ninth clock. The PCI βlave 64 thus does not become aware that the cycle haβ to be terminated in βufficient time to respond according to the PCI bus protocol. The PCI interface logic device 70, which iβ monitoring the unlatched (external) control signals, recognizes the inactive FRAME! βignal aβ a circumβtance requiring termination of the cycle. Accordingly, the PCI interface logic device 70 driveβ the STOP!, DEVSEL! and TRDY! inactive in the βeventh clock thereby maintaining the PCI buβ protocol. The operation of the PCI interface logic 70 to drive the control βignals in the other five circumstances should now be apparent from the above description and the remaining timing diagrams. The situation in Figure 4b, for example, occurs when a maβter 42 tries to burβt to a non-bursting βlave 64 with late IRDY! and the cycle must be terminated with a target abort. A target abort is defined by the slave deasserting L_DEVSΞL! and aββerting L_STOP!. After receiving the STOP! signal in the fifth clock, the FRAME! signal is driven inactive by the maβter. The STOP! βignal must be driven inactive by the PCI interface logic device 70 in the next clock (DEVSEL! and TRDY! are already inactive) to maintain the buβ protocol. The third circumstance (Figure 4c) occurs when the maβter 42 is bursting with an immediate IRDY!, and the PCI slave 64 performs a target abort by driving L_DEVSEL! inactive and L_STOP! active. In thiβ case, the PCI bus protocol requires that the FRAME! signal be driven active (performed by the master 42) and the STOP! signal be driven inactive (by the PCI interface logic device 70) one clock after the FRAME! βignal is driven inactive after the target abort. The PCI interface logic device 70, which has been monitoring the unlatched signals, needs to drive only the STOP! signal to inactive βince the DEVSEL! and TRDY! are already inactive. The fourth circumstance (Figure 4d) occurs when the maβter 42 performs a non-bursting transfer with a late IRDY! signal and there is a target abort. In thiβ caβe, the FRAME! βignal iβ driven inactive by the maβter 42 after the maβter 42 eeeβ the STOP! βignal active. Once again, the STOP! βignal is driven inactive by the PCI interface logic device 70 one clock after the FRAME! iβ deasβerted in order to maintain the buβ protocol. Otherwise, the L_STOP! signal would not be driven inactive on the PCI buβ 30 for another two clock cycles, which would violate the PCI buβ protocol. The fifth circumβtance (Figure 4β) occurβ when the maβter 42 performs a non-burβting transfer and there is no target abort. In thiβ caβe, the PCI βlave 64 asserts L_STOP! in the fourth clock, seen by the master 42 as STOP! in the fifth clock. The maβter 42 responds by deasserting FRAME! in the sixth clock. The STOP!, TRDY! and DEVSEL! signalβ must all be deasβerted in the seventh clock since the FRAME! βignal was deaβserted in the sixth clock. Since the PCI slave 64 cannot drive these βignals inactive soon enough, due to the latching of the signals, the PCI interface logic device 70 drives the signals inactive to maintain the PCI buβ protocol. The β xth circumβtance (Figure 4f) occurβ when the maβter performs a bursting tranβfer to a non-burβting βlave 64, with an immediate IRDY! βignal. The L_STOP! βignal iβ aββerted by the PCI βlave 64 in the fourth clock, seen by the master 42 in the fifth clock which cauβeβ the maβter to deaββert FRAME!. After FRAME* haβ been deaβserted, the DEVSEL! and STOP! have to be driven inactive in the βixth clock to maintain the PCI buβ protocol, the TRDY! βignal already being inactive in thiβ caβe. As can be appreciated by the above examples, the present embodiment provides a PCI interface logic device 70 that monitors the unlatched, external control signals and under certain circumstances, takes over the task of driving the external slave signals on the PCI bus 30 according to the PCI bus protocol. This allows the bridge chip 34, containing the PCI slaves 64 - 68, to be implemented in a slow, relatively inexpensive technology using latched signals, while maintaining the PCI bus protocol.

Claims: CLAIMS 1. A computer system comprising a first bus (32), a second bus (30) carrying master-slave control signalβ and having a specified bus protocol, at leaβt one maβter (42) coupled to the βecond bus (30), and a bridge (34) coupled between the first and second buses, the bridge including an internal latched third bus (62) carrying latched maβter-slave control signals, at least one slave (64 - 68), a latch (60) coupled between the second and third buses for latching the master-slave control signals received from the second bus (30) and the latched master-βlave control signals received from the third bus (62), and a logic device (70) coupled between the second and third buseβ, the logic device monitoring the βtateβ of the control βignalβ on the βecond buβ (30) and driving at leaβt one of the control signals on the second bus according to the bus protocol in response to certain predetermined βtateβ of the monitored control βignalβ. 2. The computer system claimed in claim 1, wherein the second bus is a peripheral controller interconnect (PCI) bus, and the buβ protocol iβ a PCI buβ protocol. 3. The computer system claimed in claim 2, wherein the slave is a PCI slave. 4. The computer system claimed in claim 3, wherein the third bus is an internal latched PCI bus. 5. The computer system claimed in claim 4, wherein the control signalβ include a target ready βignal, a device select βignal and a βtop signal, the logic device driving at least one of these control βignalβ in reβponβe to the certain predetermined βtateβ of the monitored control signalβ. 6. The computer system claimed in claim 5, wherein the monitored control βignalβ include a frame βignal and an initiator ready βignal. 7. The computer system claimed in claim 6, wherein the predetermined βtare includeβ a deaββertion of the frame βignal, the logic device driving any active target ready, device select and stop signalβ inactive in reβponβe to the deaββertion of the frame βignal. 8. The computer system claimed in claim 5, 6 or 7, wherein the logic device includes a separate state machine for each of the respective target ready, device select and βtop βignalβ. 9. The computer system claimed in any preceding claim, wherein the bridge is formed by slow CMOS technology. 10. A bridge for coupling first and second buses in a computer system as claimed in any preceding claim.

Inventors: CRONIN DANIEL RAYMOND III, KATZ SAGI, KULIK AMY, WALL WILLIAM ALAN, CRONIN, DANIEL, RAYMOND, III, KATZ, SAGI, KULIK, AMY, WALL, WILLIAM, ALAN
Applicants: IBM, IBM UK, IBM UNITED KINGDOM LIMITED, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1995
Main classification: G06F13
IPC codes: G06F13