A method for fabricating BiCMOS semiconductor devices

Abstract: A BiCMOS device 10 having a bipolar transistor 60, a PMOS transistor 64 and a p-type polysilicon resistor 70. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. PMOS transistor 64 comprises source/drain regions 52, gate electrode 40, and gate oxide 28. PMOS transistor 64 may also comprises LDD regions 44. The emitter electrode 30 and gates 40 are formed out of the same polysilicon layer and thus have the same thickness. If desired, the emitter electrode 30 and gate electrodes 40 may be silicided.

Description: This invention generally relates to semiconductor devices and processes and more specifically to BiCMOS processes with surface channel PMOS transistors. BACKGROUND OF THE INVENTION The integration of MOSFET structures and bipolar transistors on a single substrate has become very desirable. As is well known in the art, digital and linear functions are often performed by integrated circuits using either bipolar or metal-oxide semiconductor (MOS) technology. Bipolar integrated circuits, of course provide higher speed operation and greater drive currents than the MOS circuits, at the cost of higher power dissipation, especially when compared against complementary MOS (CMOS) circuits. Advances in manufacturing technology have allowed the use of both bipolar and CMOS transistors in the same integrated circuit. These are commonly referred to as BiCMOS devices. In a BiCMOS device, bipolar transistors are typically formed by using a moat region for the base of the bipolar transistor, doped polysilicon for the emitter, and a well region for the collector. Resistors typically comprise either a diffused region or polysilicon which is doped n-type. CMOS circuits comprise both NMOS and PMOS transistors. An example of a BiCMOS device including a bipolar transistor, an NMOS transistor, a PMOS transistor and a resistor is disclosed in U.S. Patent No. 5,107,321. That document reports that n-type dopants are preferred in the PMOS gate because n+ will provide a burried channel device, having a higher carrier mobility. In order to scale the PMOS transistor and provide low threshold voltages, it is desirable to use a surface channel PMOS transistor. Thus, NMOS and PMOS transistors use doped polysilicon for the gates and diffused regions for the source/drain regions. This complicates the process by requiring both n+ and p+ polysilicon gates that are typically doped by the source/drain implants. The source/drain implants, however, may not provide adequate doping through the polysilicon gates to the gate oxide. Adequate doping of the NMOS gates can be achieved by implanting the NMOS gates during the bipolar emitter implant. Improved doping of the PMOS gates may be achieved by scaling the polysilicon thickness. However, scaling the polysilicon thickness is undesirable in a BiCMOS process that uses the same polysilicon layer for the emitter and the NMOS and PMOS gates. Accordingly, there is still a need for adequate doping through the polysilicon to the gate oxide in a PMOS transistor that does not require the polysilicon thickness to be scaled. SUMMARY OF THE INVENTION According to the present invention there is provided a method for forming a semiconductor device comprising the steps defined in claim 1. The method extends to the implanting of a third area of the conductive layer in a region in which a plurality of NMOS transistors are to be formed with an n-type dopant. An NMOS gate is formed for each NMOS transistor by etching the conductive layer. A pair of NMOS source/drain regions is formed in the semiconductor body for each NMOS transistor. The method further extends to the implanting of a fourth area in which a plurality of bipolar transistors are to be formed with an n-type dopant. An emitter electrode is formed for each bipolar transistor by etching the conductive layer. The method also extends to forming a plurality of NMOS and bipolar transistors as defined in claim 4. The advantages of the invention will be apparent to those of ordinary skill in the art having reference to this specification in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: FIG. 1 is a cross-sectional diagram of a BiCMOS device according to a preferred embodiment of the invention; and FIGs. 2a-g are cross-section diagrams showing various stages of fabrication of the BiCMOS device of figure 1. Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The invention will be described herein as incorporated into a BiCMOS structure having a bipolar transistor, an NMOS transistor, a PMOS transistor, and a p-type resistor. Figure 1 illustrates, in cross-section, bipolar transistor 60, PMOS transistor 64, NMOS transistor 68, and resistor 70. The structure is formed into a substrate 12 which, in this embodiment is p-type silicon. Buried n+ region 14 in bipolar transistor 60 serves as a subcollector, in the conventional manner, with n+ region 25 providing a surface contact thereto. N region 18a serves as the collector region in bipolar transistor 60. Intrinsic base 26 is a p-type region disposed within n region 18a. P+ region 50 serves as extrinsic base region of bipolar transistor 60. Emitter electrode 30 may be a doped polysilicon layer which extends through an opening in insulator layer 24 to intrinsic base region 26. Silicide layer 56 may cover emitter electrode 30. N region 18b is the well region for p-channel transistor 64. It should be noted that PMOS transistor 64 may alternatively be formed in well region 18a as described in U.S. Patents No. 5,441,903, issued 8/15/95, and No. 5,334,549, issued 8/2/94, both assigned to Texas Instruments, Incorporated. P+ regions 52 serve as the source/drain regions for PMOS transistor 64. N+ regions 54 serve as the source/drain regions for NMOS transistor 68. Gate oxide 28 is disposed between gates 40 and n regions 18b and p region 20. Doped polysilicon may be used to form gates 40 of transistors 64 and 68. Gates 40 may optionally be silicided to form silicide layer 56. Resistor 70 comprises p-type doped polysilicon and is disposed over field insulating region 22. The advantage of having a p-type resistor instead of a n-type resistor is that the PMOS gates can be implanted both at the same time as the resistor and during the source/drain implants. Thus, adequate doping of the PMOS gates can be achieved without scaling the polysilicon thickness. Field insulating regions 22 isolate intrinsic base region 26 from collector contact 25, transistors 64 and 68 from each other, and p-channel transistor 64 from bipolar transistor 60. N+ regions 14 below transistor 60 and 64 is separated by buried p+ region 16 and n regions 18a-b are separated by p region 20 to allow the n-type regions 18a-b of the two transistors to be at different potentials. Figure 2a illustrates structure 10 after the formation of n+ buried layers 14, p+ buried layers 16, n-type regions 18a-b, p-type regions 20, field insulating regions 22, and insulator layer 24. Methods for forming the buried layers are described in U.S. Patent No. 4,958,213, issued September 18, 1990 and assigned to Texas Instruments Incorporated. A method for forming field insulating regions 22 is described in U.S. Patent No. 4,541,167, issued September 17, 1985 and assigned to Texas Instruments Incorporated. Insulator layer 24 may be a dummy gate oxide formed via an Anti Kooi oxidation followed by a deglaze to a depth of less than 20 A followed by a thermal oxidation to a depth on the order of 300 A. The formation of a BiCMOS device according to the invention into the structure of Figure 2a will now be described. The surface of structure 10 is patterned and implanted using a n-type dopant to form a deep n-type region (collector contact 25) that extends through n region 18a to contact the subcollector, n+ region 14, as shown in Figure 2b. Next, the V t adjust implants may be performed: one for NMOS transistor 68 and one for PMOS transistor 64. Still referring to Figure 2b, the base region 26 is patterned and implanted with a p-type dopant (e.g. boron 7.0E13 cm -2 at 10Kev). Referring to Figure 2c, dummy oxide layer 24 is then removed using a deglaze and replaced with an insulator layer such as gate oxide layer 28. Gate oxide layer 28 is formed by thermal oxidation and has a thickness on the order of 100 A. Masking layer 27 is used to expose a region of gate oxide layer 28. The exposed oxide is then etched to expose a portion of base region 26. Masking layer 27 is then removed and a deglaze is performed (e.g., 10% HF for 10 seconds) to minimize the interfacial oxide. Referring to Figure 2d, a layer of conductive material, such as polysilicon layer 29, is deposited by way of LPCVD over the surface of structure 10. Polysilicon layer 29 has a thickness on the order of 3500 A. Still referring to Figure 2d, masking layer 31 is used to expose the areas of polysilicon layer 29 where the PMOS gate and the p-type resistor are to be formed. The exposed areas are then implanted with a p-type dopant such as Boron (eg., 2E15 at 20KeV). Referring to Figure 2e, masking layer 31 is removed and replaced with masking layer 32 which exposes the areas where the emitter and NMOS gate are to be formed. The exposed areas are then implanted with an n-type dopant such as arsenic or a combination of arsenic and phosphorous (eg. 1E16 at 100KEV for arsenic). Masking layer 32 is then removed. After the resistor 70 and emitter electrode 30 have been adequately doped, polysilicon layer 29 is patterned and etched as shown in Figure 2f to form emitter electrode 30, gates 40, and resistor 70. Referring to Figure 2g, conventional techniques are then used to implant lightly doped drains (LDDs) 44 and 46, form sidewall spacers 48, and form source/drain regions 52 and 54. It should be noted that LDDs 44 are optional and need not be formed. Sidewall spacers 48 are formed by depositing a dielectric layer and anisotropically etching the dielectric layer. Sidewall spacers 48 preferably comprise nitride on a thin oxide but could be oxide only. After sidewall spacers 48 are formed, source/drain regions 52 and 54 are implanted with p-type and n-type dopants, respectively and annealed. The gates 40 are also implanted during the source/drain implants. Thus, the NMOS transistor gates are implanted during both the emitter implant and the NMOS source/drain 54 implant and the PMOS transistor gates are implanted during both the resistor implant and the PMOS source/drain 52 implant. Accordingly, adequate doping can be achieved in both the NMOS and PMOS transistors. Subsequent to the completion of the methods described above, the gates 40, source/drain regions 52 and 54, and the emitter electrode 30 may be silicided followed by the formation of the interconnecting metallization for making contact to the active regions of Figure 1. Methods for forming such interconnections are well known in the art. Individual circuits are then separated from portions of substrate 12 and external connections made thereto by way of wire bonding, direct bump bonding, or the like, as is well known in the art. The individual circuits may then be packaged into a dual-in-line package, a chip carrier, or another type of package. An example of such a package is described in U.S. Patent No. 4,495,376 issued January 22, 1985 and assigned to Texas Instruments, Inc. While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments such as performing the above-described process steps in a different order, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims: A method for forming a semiconductor device comprising the sequence of steps of: a. forming a conductive layer (29) over a surface of a semiconductor body; b. simultaneously implanting a first area and a second area of the conductive layer with a p-type dopant, said first area corresponding to where a plurality of PMOS transistors (64) are to be formed, and said second area corresponding to where a resistor (70) is to be formed; c. etching said conductive layer to form a PMOS gate (40) for each of said plurality of PMOS transistors; and d. forming a plurality of PMOS source/drain regions (52) in said semiconductor body. The method of claim 1, further comprising the steps of: a. implanting a further area of the conductive layer (29) in a region in which a plurality of NMOS transistors (68) are to be formed with an n-type dopant, wherein the step of etching the conductive layer (29) also forms an NMOS gate (40) for each of said plurality of NMOS transistors (68); and b. forming a pair of NMOS source/drain regions (54) in said semiconductor body for each of the plurality of NMOS transistors (68). The method of claim 1, further comprising the steps of: a. implanting a further area of the conductive layer (29) in a region in which a plurality of bipolar transistors (60) are to be formed with an n-type dopant, wherein said step of etching said conductive layer (29) also forms an emitter electrode (30). The method of claim 1, further comprising the steps of: a. implanting a third area and a fourth area of the conductive layer with an n-type dopant, said third area corresponding to a region in which a plurality of bipolar transistors (60) are to be formed, and said fourth area corresponding to a region in which a plurality of NMOS transistors (68) are to be formed, wherein said step of etching said conductive layer (29) also forms an emitter electrode (30) and an NMOS gate (40) for each of said plurality of NMOS transistors (68); and b. forming a pair of NMOS source/drain regions (54) in said semiconductor body for each of said plurality of NMOS transistors (68). The method of claims 2 - 4, further comprising the step of siliciding said NMOS and PMOS gates (40), and said NMOS and PMOS source/drain regions (54 and 52). The method of claims 1 - 5, wherein said step of forming said PMOS source/drain regions comprises the steps of: a. implanting said PMOS source/drain regions (52) and said PMOS gate (40) with said p-type dopant; and b. annealing said PMOS source/drain regions (52). The method of claims 1 - 6, wherein the step of etching the conductive layer (29) also forms said resistor (70). The method of claims 2, 4, 5 and 6, further comprising the steps of: a. implanting lightly doped drains on opposite sides of each of said PMOS and NMOS gates (40) after said step of etching said conductive layer; and b. forming sidewall oxides (48) adjacent to each of said PMOS and NMOS gates (40), said resistor (70) and an emitter electrode (30).

Inventors: EKLUND ROBERT H, EKLUND, ROBERT H.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1995
Main classification: H01L21
IPC codes: H01L27, H01L21