Multiplication circuit

Abstract: A multiplication circuit comprising a plurality of weighting circuit serially connected which comprises a plurality of switching means to which a common analog input voltage in inputted, the switching means being controlled by digital signals, a capacitive coupling with a plurality of capacitances each of which is connected to one of the switching means, an amplifier with high open gain to which an output of the amplifier is connected and a feedback capacitance connecting an output of the amplifier to an input.

Description: Field of the Invention The present invention relates to a multiplication circuit for generating an analog voltage as a multiplication result for an analog computation. Background of the Invention The inventers of the present invention have proposed a multiplication circuit in Japanese Application No. Hei 05-020676 and US-A-5,420,676. This multiplication circuit, as shown in Figure 2, generates an analog voltage corresponding to a multiplication of a digital multiplier and an analog input voltage by a capacitive coupling. The output of the capacitive coupling is inputted to two stages inverted amplifiers INV1 and INV3, or INV2 and INV3 so that the output is kept stable and accurate. These amplifiers consist of MOS inverters of 3 stages, the outputs of which are connected through a feedback capacitances to their inputs. The inverted amplifier keeps linearity and stability in the relationship between the input and output by a large open gain of a multiplication gains of MOS inverters of three stages. This multiplication circuit performs multiplication of digital multiplier and analog data, however it can not execute multiplication of digital data and digital data. US-A-4,654,815 describes a multiplying digital to analog converter comprising switching means and capacitor array means for converting the digital input voltage. Summary of the Invention The present invention is invented so as to solve the conventional problems and has a purposes to provide a multiplication circuit for outputting an analog data as a multiplication result of a multiplication of digital data and digital data. Multiplication circuit according to the present invention performs weighting of an analog input voltage by capacitive couplings of two stages or more. The capacitive coupling is controlled in weight according to the digital data to be multiplied. According to the present invention, a digital data is multiplied by a digital data and the calculation result is outputted as an analog data which can be used in another analog calculation or other usages. Detailed Description of the Drawings Figure 1 is a circuit diagram of the first embodiment of a multiplication circuit according to the present invention, and Figure 2 is a circuit diagram showing a multiplication circuit to be compared with the present invention. Preferred Embodiment of the Present Invention Hereinafter an embodiment of the present invention is described with referring to the attached drawings. In Figure 1, a multiplication circuit has a plurality of the first switching circuits SW11, SW12, SW13 and SW14 which are connected to capacitances C11, C12, C13 and C14, respectively, of a capacitive coupling CP1. The capacitive coupling has further capacitance C10 grounded. An output of capacitive coupling CP1 is inputted to an inverting amplifier INV1 consisting of MOS inverters I1, I2 and I3 of 3 stages, and an output of inverting amplifier INV1 is connected to its input through feedback capacitance Cf1. INV1 keeps a linearity and stability between the input and output by a large gain as multiplication of triple gain of MOS inverters. Switching means SW11, SW12, SW13 and SW14 are switches of two inputs and one output for alternatively connecting a common analog input voltage Vd or the ground to the capacitances C11, C12, C13 and C14. Switching means SW11, SW12, SW13 and SW14 are controlled by digital signal A with 4 bits. When ai (i =1 to 4) is "1", then Cli is connected to Vd and when ai is "0", then Cli is grounded, when each bit of signal A is designated as a1, a2, a3 and a4. When output of INV1 is Vo, then formula 1 is defined. Switching means SW21, SW22, SW23 and SW24 are switches of two inputs and one output and are controlled by digital signal B of 4 bits. When each bit of signal B is designated as b1, b2, b3 and b4, Vo is connected when bi is "1" and the ground is connected when bi is "0". An output Vout of INV2 is defined as in formula 2. Formula 3 is obtained when formula 1 is taken in formula 2. When formula 4 is defined, then formula 5 is obtained. Formula 5 Vout=Vd(A/16)(B/16) By enlarging a circuit size of capacitive couplings CP1 and CP2, multiplication of large digital data is possible. By increasing number of stages of inverting amplifiers, a multi-steps multiplications of digital variables is realized. According to the inventor's experience, enough linearity characteristic can be obtained by inverters of three stages. In order to minimize the circuit of sufficient performances, the inverting amplifier type multiplication is preferable. Multiplication circuit according to the present invention performs weighting of an analog input voltage by capacitive couplings of two stages or more and the capacitive coupling is controlled in weight according to the digital data to be multiplied, so that it can provide a multiplication circuit for outputting an analog data as a multiplication result of a multiplication of digital data and digital data.

Claims: A multiplication circuit comprising a plurality of weighting circuit serially connected which comprises, i) a plurality of first switching means (SW11, ..., SW14) to which a common analog input voltage (Vd) is inputted, said switching means being controlled by digital signals; ii) a first capacitive coupling (CP1) with a plurality of capacitances each of which is connected to one of said first switching means; characterized in that the multiplication circuit further comprises iii) a first amplifier (INV1) with high open gain to which an output of said first capacitive coupling (CP1) is connected; iv) a first feedback capacitance (Cf1) connecting an output of said first amplifier (INV1) to its input. v) a plurality of the second switching means (SW21, ..., SW24) connected to the output of said first amplifier (INV1); vi) a second capacitive coupling (CP2) connected to an output of said second switching means; vii) a second amplifier (INV2) connected an output of said second capacitive coupling (CP2); viii) a second feedback capacitance (Cf2) for connecting an output of said second amplifier (INV2) to its input. A multiplication circuit according to claim 1 wherein i) the first capacitive coupling (CP1) comprises a plurality of capacitances (C10, ..., C14) each of which is connected to one of said first switching means (SW11, ..., SW14); ii) said first amplifier (INV1) comprising MOS inverters of stages of odd number; iii) said second inverting amplifier (INV2) comprising MOS inverters of stages of odd number; iv) said second amplifier (INV2) serially connects an odd number of MOS inverters; and v) said first and second amplifiers (INV1, INV2) are inverting amplifiers.

Inventors: MOTOHASHI KAZUNORI, SHOU GUOLIANG, TAKATORI SUNAO, YAMAMOTO MAKOTO, MOTOHASHI, KAZUNORI, SHOU, GUOLIANG, TAKATORI, SUNAO, YAMAMOTO, MAKOTO
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1995
Main classification: G06J1
IPC codes: G06J1, G06G7