PROCESSOR CORE WHICH PROVIDES A LINEAR EXTENSION OF AN ADDRESSABLE MEMORY SPACE

Abstract: A processor core for providing a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. An N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2<x> times more memory locations than 2<N>. Two other registers each hold a portion of a data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

Description: PROCESSOR CORE WHICH PROVIDES A LINEAR EXTENSION OF AN ADDRESSABLE MEMORY SPACE COPYRIGHT NQΗCE A portion of the disclosure of this patent document contains material which is subject to copyπght protection The copyπght owner National Semiconductor Corporation has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyπght πghts whatsoever TECHNICAL FIELD OF THE INVENTION The present invention relates to microprocessor architectures and, in particular to a processor core which provides a linear extension of an addressable memory space BACKGROUND OF THE INVENTION With microprocessor architectures, the number of memory space locations which a particular processor can address is limited by a number of factors One limiung factor is the number of bits available (typically 16 bits) within the processor s internal registers where memory space addresses are stored Since the processor s stack is used for temporary storage of memory space location addresses the bit-width (typically 16 bits) of the processor s stack is also a limiung factor Another limiting factor is the width of the processor s Aπthmeuc Logic Unit ("ALU") which calculates memory space addresses Where storage of addresses is to be in 16 bits, the processor has a limited addressable linear memory space of 2**16 = 256k locauons A first pπor an attempt to overcome these limiting factors is known as the Harvard Architecture, which employs separate code and data memory spaces, effectively doubling the number of addressable memory locations This architecture has the disadvantage that it makes inefficient use of memory Available memory, once allocated to either data or code, can not be reallocated Furthermore, a particular data structure is limited in size to the amount of memory actually allocated to data, and no more A second pπor art attempt to overcome the limiting factors makes use of software overlays, where code is stored on a secondary storage device, such as a disk dπve, during execution of a program, and pieces of the program code are retπeved, as they are needed, from the secondary storage device into the memory This method does not extend the linearity of the memory space An architecture which employs software overlays also has the disadvantage of requiring a secondary storage device Furthermore, the use of overlays adds significant program execuuon overhead to both manage the overlays and to retπeve the pieces of program code from the external storage device A third pπor art attempt to overcome the limiting factors employs memory segmentation For example, the Intel 8086 microprocessor, manufactured by Intel Coiporadon of Santa Clara, California, employs memory segmentanon The Intel 8086 has 16-bit segment registers which provide base addresses for addressing memory segments For each memory access, a 20-bit address is calculated bv adding the contents of the appropnate segment register, multiplied by 16, to an offset specified in the instruction or in another register The memory segmentanon approach has the disadvantage that it increases both software and hardware complexity It also has the disadvantage that data structures are limited m size and/or must be located near the beginning of a segment, or addiuonal software complexity is required to traverse segment boundaries Furthermore, the use of more than one register, where it is necessary to perform aπthmetic on the contents of the registers to form an address, is relauvelv slow A fourth pπor art attempt to overcome the limiting factors uses bank switching In one implementanon of bank switching, bits from a microprocessor s output port are used to enable separate memory banks or are decoded as the most significant address bits A problem with the use of bank switching to overcome memory space limiting factors is that bank switching adds significant hardware and software complexity The bank switching implementations also limit the size of a particular data structure to the size of a memory bank SUMMARY OF THE INVENTION The present invention is a processor core which provides a linear extension of an addressable memory space of a microprocessor with minimal addmonal hardware and software complexity In accordance with a first embodiment of the present invention, an N + x bit pomter register (e.g. a program counter) means of the processor core holds an N + x bit address The N + x bit address is a pomter to an mformaπon entrv m the memorv which is to be processed by an execution unit of the processor core An encoder encodes the N + x bit address into an N bit encoding of die N + x bit address As a result of the address encoding, the limiting factors of processor core general register width and stack width are overcome, such that the processor core can address 2 X times more memory space locations than 2 N In accordance with a further embodiment of the present invenuon, a processor core compπses at least two register means Each register means is for holding a portion of an address, where the address is used to form a pomter to a datum in memory to be operated on An address forming means concatenates the portions of the address in the register means to form the address Therefore, the address is formed from portions of the address stored in mulπple registers without performing any aπthmetic on the portions A better understanding of the features and advantages of the invention will be obtained by reference to the following detailed descπpuon and accompanying drawings which set forth an illustrauve embodiment in which the principles of the invention are utilized BRIEF DESCRIPTION OF THE FIGURES Fig. 1 is a block diagram lllustraung a processor core embodying the present invenuon Fig. 2 illustrates the program counter register of the processor core of Fig 1. Fig 3 is a table that provides sample assembly language instructions utilizable m accordance with the present vennon Figs 4A-4E illustrate an embodiment of the present invention in the context of the sample assembly language lnst ucnons in Fig. 3. Fig. 5 illustrates the format for encoding a BAL instruction to be executed by the processor core of Fig. 1. Fig 6 illustrates a pair of registers for holding a pomter to a datum in memory Fig. 7 illustrates the format for encoding a LOAD/STORE instruction to be executed by the processor core of Fig 1. Fig 8 illustrates the general purpose registers of the register file of the processor core of Fig. 1 DETAILED DESCRIPTION OF THE INVENTION Fig. 1 shows a processor core 28 in accordance with the present invention, interfaced to an external memory 30. Many of the elements shown m Fig. 1 are convenuonal microprocessor components arranged in a convenuonal manner. Those convennonal components are not descπbed in detail since both their structure and operanon are well-known to those skilled in the an. Linear Extension of Instrucnon Space The processor core 28 includes an 18 bit address bus 34, which allows addressing of 2 1B = 256k memory locations. The processor core 28 further includes a 17 bit (i.e. N+x bit, where N is 16 and x is 1) program counter register 32, which contams a 17 bit (i.e. N+x bit) address in the memory 30 of the next instruction to be executed. To fetch an instruction to be executed from the memory 30, the contents of the program counter register 32 are padded with a constant zero as a most significant bit and placed onto the 18 bit address bus 34, and the instruction is loaded into an instruction loader 36 via a 16 bit data bus 35 The program counter register 32 is shown in detail in Fig 2. The N bit portion of the register is bits 2-17, with bit 2 being die least significant bit of the N bit portion and bit 17 being the most significant bit of the N bit pomon. The x bit portion of the register is bit 1. When the to be executed mstmcnon is a jump/branch instruction, the aπthmetic logic unit ("ALU") 38 computes, in N + x bit (i.e 17 bit) precision, the target address at which instruction execution is to continue and wπtes the target address to the program counter register 32 via a MUX 42 and a RESULT bus 44. In cases of execuung jump/branch instructions with linkage (i.e for funcuon or subroutine calls), a shifter 40 encodes a copy of the 17 bit 0 e N + x bit) address of the next sequenual instruction (i.e the "return address", which is the contents of the program counter) into a 16 bit d e N bit) encoded address by shifting off the x bit poπion of the N + x bit address such that the N bit portion remains The N bit d e 16 bit) encoded return address is saved to an N bit (i e 16 bit) wide stack space, which may be. for example, either in the external memory 30 or internal to the processor core 28 Altemanvely, the encoded return address may be saved to one of the general registers in the register file 38, which are also N bits (i.e. 16 bits) wide. As compared to a convennonal processor core which has a 16 bit (i.e N bit) program counter register and a 16 bit (i.e N bit) address bus, the processor core 28 in accordance with the present invention can address 2 times (i.e 2 times) as many memory locanons (i.e 2 X nmes 2 N ) -but the components of the processor core 28 which are used to store addresses (i.e general purpose registers in the register file 31, stack areas m memory 30 or m the register file 31, etc) need to be only 16 bits (i.e. N bits) By aligning all instructions stored in the memory 30 on addresses divisible by 2 (i.e. 2 X ), it can be ensured that the address of any instruction to be executed by the processor core 28 has least significant 1 bit (i.e. x bits) of zero. As another, hypothetical, example, in a byte-addressable architecture, the lnstmcnons can be aligned on double-word boundaries Thus, in such an operauon of the present invenuon, whenever a copy of a return address is saved, the address is encoded by saving only the most sigmficant 16 bits (i.e. N bits) of the 18 bit (i.e. N+x bit) address That is. since the least sigmficant 2 bits (i.e x bits) of the 18 bit (i.e. N +x bit) address are always zero, the least sigmficant 2 bits (i.e x bits) need not be represented m the encoded address In a complementary fashion, when the 17 bit (i.e N + x bit) program counter register 32 contents is restored from a 16 bit (i.e. N bit) encoded representation, the instruction address wπtten to the program counter register 32 is shifted to the left, resulting in a least sigmficant 1 bit (i.e. x bits) of zero. Altemanvely, uistrucnons can be aligned on addresses that, although not divisible by 2 X , have idenucal remamders when divided by 2 X , thus ensuπηg that the address of any instruction to be executed has idenucal least sigmficant x bits. In this case, also, a return address is encoded by saving only the most sigmficant N bit of the N+x bit address. However, when the N + x bit program counter register 32 contents is restored from an N bit encoded representaαon, the return address wπtten to the program counter register 32 is assumed to have least sigmficant bits equal to the aforemenαoned idenncal remainders. With reference to Figs. 4A-4E, the instmcαon address store/restore mechanism, in accordance with the above-descπbed preferred embodiment, is illustrated in the context of several jump/branch with linkage instiucuons, shown in assembly language form in Fig. 3. The foregoing illustranons assume that the lnstrucuons stored in the memory 30 are all aligned on address boundaπes divisible by 2 (i.e. by 2 ) such that the address of any mstnicuon to be executed by the processor core 28 has least sigmficant 1 bit (i.e. x bits) of zero. First, a branch and link lnstrucuon 50, which is of the form "BAL link, dest." provides an dlustranon of the address store mechanism. The 17 bit (i.e. N+x bit) return address is stored, from the ALU 38, in encoded form, into the 16 bit (i.e. N bit) register specified by the link field in the mstnicuon 50. The displacement to the mstnicuon at which program execunon is to continue may be up to 17 bits (i.e. N+x bits). Fig. 5 shows the encoding of a BAL mstnicuon. As shown m Fig. 5, only the most sigmficant 16 bits (i.e. N bits) of the displacement are encoded directly into the lnstnicnon. The actual displacement is obtained by shifting the encoded 16 bit (i.e. N bit) portion of the displacement left by 1 bit (i.e. x bits). The address at which program execuuon is to continue is obtained by adding the actual displacement to the address contained m the program counter register. Fig. 4A illustrates an execunon of the BAL mstnicuon. Referring to the "bal rl5, L" instruction 50 shown in Fig. 4A, the return address is 2909C 16 , which is the address of the current (bal) mstnicuon, 29098-^. plus four, the number of bytes m the current uistnicnon. Bits 2-17 of the return address (i.e. the most sigmficant N bits) are saved in the 16 bit (i.e. N bit) link register R15. and execunon control is passed to the dest uistnicnon, labelled L, by adding 00F6C 16 , which is the offset to L from the address of die BAL lnstrucuon 50, to the current PC. An EXCP instruction 52. which is of the form "EXCP vector." also provides an illustration of the address store mechanism. Before the EXCP mstnicuon activates the trap specified by the vector operand, the return address, m encoded form, is pushed onto the 16 bit (i.e. N bit) wide interrupt stack The Jcond mstnicuon 54 which is of the form Jcoπd dest provides an lllustranon of the address restore mechanism A two character condition code that descπbes a flag or flags in a processor status register whose state is to be tested is specified in die cond field of the instruction 54 If the condiπon specified bv the cond field is true, program execution contmues at a destination address specified in encoded form in the 16 bit (i e N bit) dest register by restoπng the encoded address from die dest register into the most sigmficant 16 bits (i e N bits) of the program counter register The least sigmficant bit d e x bits) of the program counter register are cleared to zero Fig 4B illustrates an execuuon of die Jcond instruction Refernng to the "jlo r3" (jump if lower than) instruction shown in Fig 4B. which checks the state of the processor status register flags PSR.Z and PSR L If die processor status register flags PSR Z and PSR L are zero, this instruction restores the destination address held in R3 (19004 16 , encoded as OC802 16 ) into bits 2-17 of the program counter register, dealing bit 1 of the program counter register Program execuuon then contmues at the destinaαon address The JAL instruction 56 which is of die form "JAL link, dest.' provides illustrations of both the store and restore mechamsms Program execuuon contmues at die destination address encoded in the 16-bit dest register, by restoπng the encoded desπnation address from the dest register into the program counter register and cleanng the least significant bit of the program counter register The return address is stored in encoded form in die link register Fig 4C illustrates an example of the JAL instruction Refemng to the "jal rl5, r3" uistnicnon shown in Fig 4C, this example loads die destination address held in register R3 (19004 16 . encoded as C802 16 ) into bits 2-17 of the program counter register and clears bit 1 of the program counter register The return address is 0909A 16 , which is the address of die current instruction (JAL), 09098 16 , plus two, die number of bytes in the current lnstrucuon Bits 2-17 of the return address are saved in register R15 Finally, execution control is passed to die mstnicuon at 19004-^ The JUMP instruction 58, which is of the form "JUMP dest," provides an illustrauon of the restore mechanism Execuuon contmues at the encoded desunauon address held in die dest register by restoπng die encoded address from the dest register into the program counter register and cleanng the least sigmficant bit of the program counter register Fig 4D shows an example of die JUMP instruction Referring to the jump r3 mstnicuon shown in Fig 4D, dns example loads die desunauon address, held in encoded form in register R3. into bits 2-17 of the program counter register, cleanng bit 1 of die program counter register Program execution then contmues at die destmanon address The RETX mstnicuon 60 provides an example of die restore mechanism The RETX instruction returns control from a nap service procedure bv conunuing execution contmues at the return address held in encoded form at the top of die interrupt stack When the RETX instruction is executed, die encoded return address is popped from the interrupt stack and loaded it into the 16 most sigmficant bits of the program counter register The least sigmficant 1 bit of the program counter register are cleared Execuuon contmues at die return address Fig. 4E shows an example of die RETX instruction Refernng to die retx mstnicuon shown in Fig 4E, this example loads me return address (19004 16 , encoded as C802 16 ), from its encoded form on die interrupt suck into bits 2-17 of die program counter register, cleanng bit 1 of the program counter register Program execunon dien contmues at 19004-^, die return address Linear Extension of Data Space In accordance with a further embodiment of the present invention, two general registers within the register file 31 (two are shown m Fig 6, RO and Rl) are concatenated to form a pomter to a datum in memory from the concatenated contents of the two registers That is. RO holds 16 bits (i.e N bits, bits 1, 2 N) and Rl holds 2 bits (t e y bits, bits N + l , N+y) To form an 18 bit (i.e N+y bit) pomter to a data item, a programmer wπtes bits 1, 2 N (i e N bits) of the 18 bit (i.e N+y bit) address to RO and bits N+ l, N+y (i.e. y bits) of the 18 bit (i.e N+y bit) address to Rl Then, to form an 18 bit address, the 16 bits (i.e N bits) from RO are put onto the least sigmficant 16 bits of the ADDRESS bus 34, and the 2 bits (i.e y bits) from Rl are put onto the most sigmficant 2 bits of the ADDRESS bus 34 That is. the 18 bit address is formed by concatenating die contents of RO and Rl Fig 7 dlustrates the format or an instruction (LOAD/STORE) which uαlizes an 18 bit (i e N+y bit) data reference Bit 14 of the instruction indicates whether the instrucπon is a "Load or a "Store instruction Bits 5-8 indicate a register which holds die 16 bit (i e N bit) poπion of die base address of a pomter to a data reference the next consecunvely numbered register holds the 2 bit (I e y bit) poruon of die base address of die pomter to die data reference Bits 9-10 and 16-31 hold die 18 bits d e N+y bits) of the displacement of the pomter The complete address of the pointer is formed by addmg die base address to the displacement Fig 8 shows a preferred embodiment of die present mvenπon register concatenation embodiment of Fig 6 In accordance widi die preferred embodiment while to a programmer it appears that the registers RO and Rl are each 16 bits (I e N bits), register RO acmally has 18 bits, the two most sigmficant bits are inaccessible to the programmer direcdy As with the previously descnbed embodiment, the 16 bit (i e N bit) poπion of die address is wππen to RO (l e die least significant 16 bits of RO) via the wπte bus 50 When the 2 bit d e y bit) portion of the address is wππen mto Rl via the wπte bus 50, the 2 bits are also wπtten mto die most sigmficant 2 bits of RO via a 2-bit ponion 54 of die wπte bus 50 Thus. RO contams the complete 18 bit (l e N+y bit) pomter value When an indirect memory reference is made by the programmer designating the R0/R1 pair as contammg the pointer value, the 18-bit pointer value is read direcdy out of the 18-bιt register RO on an 18- bit read bus 52 There is no need to access Rl at all, nor is diere need to combine die contents of muluple registers to form the 18-bit pomter value It should be understood diat vaπous alternatives to the embodiments of the invention descnbed herein mav be employed in pracncuig the invenuon It is intended diat the following claims define die scope of the invention and diat methods and apparatus within the scope of these claims and their equivalents be covered thereby

Claims: WHAT IS CLAIMED IS 1 A processor core that retπeves information from a memorv and processes the information compπsing (a) an execuuon unit mat processes information (b) an N + x bit pointer register means for holding one of a plurahtv of N + x addresses wherein said N + x bit address provides to the execuuon unit a pointer to an information entry in the memory to be processed by the execution unit and (c) an encoding means for encodmg said N + x bit address mto an N bit encodmg of said N +x bit address whereby the processor core can address 2 times more memory locanons than 2 2 A processor core as in claim 1, further compπsmg (d) a linkage register means for holding said N bit encodmg of said N +x bit address 3 A processor core as in claim 2, further compπsmg (e) a decoding means for decoding said N + x bit address from said N bit encoding of said N + x bit address 4 A processor core that processes information retπeved from a memorv compπsing (a) an execution unit diat processes information (b) a decoding means for decoding an N bit encoding of one of a plurality of N + x bit addresses into said N + x bit address, (c) an N + x bit pointer register means for holding said N + x bit addresses wherein said N + x bit address provides to the execution unit a pomter to an information entry in die memory to be processed by the execuuon unit whereby the processor core can address 2 umes more memory locauons than 2 5 A processor core that executes lnstrυcuons retπeved from a memory, compπsmg (a) an execuuon unit that executes instrucnons, (b) an N + x bit program counter register for holdmg one of a plurality of N + x bit addresses, wherein said N + x bit address provides to said execunon unit a pointer to an mstnicuon in the memory to be executed by the execunon umt, and (c) an encodmg means for encoding said N + x bit address into an N bit encoding of said N + x bit address whereby the processor core can address 2 X umes more memory locauons man 2 6 A processor core as in claim 5. further compπsmg (d) a linkage register means for holdmg said N bit encodmg of said N + x bit address 7 A processor core as in claim 6, further compπsmg (e) a decodmg means for decodmg said N+x bit address from said N bit encodmg of said N+x bit address 8 A processor core as m claim 7, wherein said N bit encodmg of said N+x bit address is die N most sigmficant bits of said N+x bit address 9 A processor core as in claim 8 wherein the least significant x bits of said N-bit address is a pπoπ determined to be zero 10 A processor core that executes instrucnons retπeved from a memory compπsmg (a) an execunon unit that processes lnstmcuons (b) a decodmg means for decoding an N bit encodine of one of a plurality of N+x bit addresses mto said N+x bit address. (c) an N + x bit pomter register means for holding said N + x bit address wherein said N+x bit address provides to d e execunon unit a pomter to an instruction in the memory to be retπeved from memory and executed by die execunon unit whereby the processor core can address 2 X times more memory locauons than 2 11 A method of retrieving informauon from a memory to a processor core, to be processed by an execution unit of die processor core, compπsmg (a) holdmg one of a plurality of N + x bit addresses in an N+x bit pomter register, wherein said N + x bit address provides to die execunon unit a pointer to an information entry in the memory to be processed by die execunon umt; and (b) encodmg said N + x bit address into an N bit encodmg of said N+x bit address whereby the processor core can address 2 times more memory locauons than 2 . 12 The method of claim 11, further compπsmg' (c) holding said N bit encoding of said N+x bit address 13 The method of claim 12, further compπsing' (d) decoding said N + x bit address from said N bit encodmg of said N+x bit address 14 A mediod of retπevmg information from a memory to a processor core, to be processed by an execution unit of die processor core, compnsmg (a) decodmg an N bit encodmg of one of a plurality of N+x bit addresses into said N+x bit address, wherem said N + x bit address provides to the execution unit a pomter to an information entry m the memory to be processed by the execunon umt, and (b) holdmg said N+x bit address whereby die processor core can address 2 times more memory locanσns man 2 15 A processor core that operates on data retπeved from a memory, compπsing- a) at least two register means, each register means for holdmg a poruon of an address, die address being used to form a pomter to a datum in memory to be operated on; and b) an address forming means for concatenating die portions of the address m die register means to form the address whereby the address is formed from portions of the address stored tn muluple registers without performing any aπthmetic on the portions 16 A processor core as in claim 15, further compnsmg - c) wntmg means for wnαng the portions of die address to die register means. 17. A processor core that operates on data retπeved from a memory, compπsmg: a) a first register means for holdmg an N bit poruon of an N+y bit address, the N+y bit address being used to form a pomter to a datum in memory to be operated on; b) a second register means for holdmg a y bit poruon of the N+y bit address; and c) a wntmg means for wntmg die N bit portion of the N+y bit address to die first register means and for wntmg the y bit portion of die N+y bit address to die second register means; and d) an address forming means for concatenanng die N bit portion in die first register means and die y bit portion die second register means to form the N+y bit address whereby die N+y bit address is formed from portions of the N+y bit address stored muluple registers widiout performing any andimenc on the portions and die processor core can address 2 y umes more memory locanons than 2 . 18 A processor core that operates on data retπeved from a memory, compπsmg a) a first register means for holding an N+y bit address, die address being used to form a pomter to a datum m memory to be operated on; b) a second register means for holding a copv of a y-bit poπion of die address; and c) a wπung means for wπung an N bit poruon. other than die y bit portion, of the address to the first register means, for wntmg the y bit portion to the second register means, and for also wπung the y bit portion to the first register means whereby the complete address can be accessed from the first register means and the processor core can address 2 y umes more memory locauons than 2 N .

Inventors: BENDELAC CHAIM, BIRAN DAN, ERLICH GADI, FALIK OHAD, INTRATER GIDEON, LEVY JONATHAN, BENDELAC, CHAIM, BIRAN, DAN, ERLICH, GADI, FALIK, OHAD, INTRATER, GIDEON, LEVY, JONATHAN
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1995
Main classification: G06F9
IPC codes: G06F9