CIRCUIT AND METHOD FOR GENERATING ACCURATE QUADRATURE SIGNALS

Abstract: An input signal is fed into a comparator which compares the input signal to a reference voltage VR. The output of the comparator is then connected to a divider circuit, which produces the quadrature signals, each signal at one-half the frequency of the signal input thereto. Both signals are then input to a phase detector, which outputs a pulse train correlated to the phase difference if the two signals are not exactly 90 DEG out of phase. The pulse train is then passed through a low-pass filter, and through an integrator, to obtain an adjusted reference voltage VR. VR adjusts the zero crossing of the comparator to bring the two signals into quadrature relationship.

Description: Circuit and method for generating accurate quadrature signals This invention relates to electronic circuits for broadband quadrature signal generation, and specifically to correcting phase error between two signals that are approximately in quadrature to make the phase difference between the two signals exactly 90° by adjusting a control signal used in the quadrature signal generation. In the past few years, the advantages of digital modulation for efficient use of personal communication systems have become apparent. Various forms of Quadrature Phase Shift Keying (QPSK) modulation require local oscillators which are in quadrature, i.e. which output two signals 90° out of phase with each other, over a wide bandwidth. Generation of such signals at low frequencies is accomplished by a simple divide-by-two flip- flop. In the related art, an input signal is first fed to a comparator, the negative input of which is connected to a voltage reference V R . The output of the comparator is then provided to a divider circuit, which produces two signals, each at one-half the frequency of the input signal. If the input signal to the system is a symmetric square wave, this method and apparatus will result in very good performance at low frequencies. However, at high frequency (frequencies above 100MHz), generating a fully-symmetric waveform (even with no harmonic content) is very difficult. Further, unequal propagation delays can cause further phase errors. For example, with an 800MHz input signal, which should produce two 400MHz quadrature signals, a seven pico-second mismatch and propagation delay occurs between the in-phase signal and the quadrature signal, which will cause the foregoing signals to be 89° out of phase, instead of being 90° out of phase. In addition, if the incoming signal at 800MHz has any second order harmonic content, which makes the distance between zero crossings unequal, additional phase error will also result. Also, with high frequency input signals, account must be taken of the harmonic effect. Therefore, the input signal must be filtered to eliminate the harmonic effect, or when the unfiltered input signal is being demodulated, the harmonic content of the input signal could interfere with the demodulated signal and produce a dispersed signal. At high frequencies, and over a bandwidth of less than an octave, the phase difference between an RC and CR network or the phase difference between two all- pass phase shift networks can be used to output two signals in quadrature. In addition, another recently-developed method uses the sum and difference of two equal amplitude signals having unequal phase to generate two ill-quadrature signals. Although the latter technique can be used over a wide bandwidth, the latter technique does not work for square wave signals. Therefore, its use is limited. What is needed is a system that will generate quadrature signals based on a high frequency input signal, and maintain the phase difference between the signals. An object of the present invention is to produce two signals exactly 90° out of phase from each other, based on an input signal. The present invention is an apparatus and method for broadband quadrature signal generation. In the method and apparatus of the present invention, the phase error between two signals that are approximately in quadrature, i.e. 90° out of phase, is measured and fed back to correct the phase difference between the two signals approximately in-quadrature, and make the phase difference of the two signals exactly 90° by adjusting the duty cycle of the first signal applied by the divide-by-two circuit. In a first embodiment of the present invention, an input signal is input to the positive terminal of a comparator, the output of which is coupled to a divide by two flip- flop circuit and which produces two output signals, an in-phase signal (I) and an in quadrature signal (Q). The I and the Q signals are input to a phase detector, which outputs narrow pulses, the duration of which are indicative of the error between the I and Q signals. If the I and the Q signals are exactly 90° out of phase, there is no phase error in the quadrature output between the I and the Q signals, and the output of the phase detector is zero. The output of the phase detector is fed to a low-pass filter, the output of which is then fed to an integrator, whose output is in turn fed to the negative terminal of the comparator. This adjusts the reference level the comparator uses to trigger the switching of the flip-flops. Therefore, the error between the I signal and the Q signal is fed back to the comparator and is used to make the I signal and the Q signal exactly 90° out of phase. An additional advantage of the present invention is the possibility to determine and adjust the phase difference between the two signals, even when the input signal is modulated. A further advantage of the present invention the reduction or the elimination of the harmonic content of the signal being demodulated, to reduce the need for filtering. These together with other objects and advantages which will be subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals refer to like parts throughout. Further details of the present invention are explained below, with the aid of the attached drawings in which: Figure 1 is a block diagram of a level-locked loop, according to the present invention; Figures 2A-2C are timing diagrams demonstrating that a perfect sinusoid produces I and Q signals with 90° phase difference, at a low frequency; Figures 3A-3C are timing diagrams showing that second order harmonic content in the input signal causes error in the I and Q phase difference; Figure 4 is a diagram showing a typical input signal to the present invention; and Figures 5A-5E are timing diagrams showing the system timing of the operation of the present invention. The present invention performs phase tracking by adjusting the zero crossing level set for an input signal used to generate quadrature output signals. As the zero crossing reference level is adjusted the duty cycle and thus the phase difference between the quadrature signals changes. The change in phase difference is detected and used to adjust the reference level to maintain a constant 90° phase difference between the quadrature ouφut signals. In Figure 1 in the present invention, an input signal V j , which could be a high frequency sinusoidal signal, for example a sinusoidal signal having a frequency of 800 megahertz (MHz), is input to a level locked loop 4, according to the present invention. The level locked loop 4 is divided into a quadrature signal generation circuit 6 and a phase detection and reference level adjustment circuit 8. In this embodiment of the level locked loop 4, the input signal is coupled to the positive terminal of a conventional comparator 10. The comparator 10 compares the input signal to a reference level signal V r provided at the negative input. As the input signal crosses the level of the reference signal the comparator 10 changes the binary value of its ouφut signal CD. The ouφut of the comparator 10 is coupled to a conventional divide-by-two circuit 12. The divide-by-two circuit 12 divides the frequency of the signal CD in half, and ouφuts two signals, divide-by-two ouφut 1 (DBTOl) and divide-by-two ouφut 2 (DBTO2). These two signals DBTOl and DBT02 are the ouφut quadrature signals that are kept exactly 90° out of phase and are the in-phase (I) signal or the quadrature (Q) signal, respectively. Each of the ouφut signals DBTOl and DBTO2 have a frequency of one-half of the input frequency signal CD and are approximately 90° out of phase with each other. In a preferred embodiment, the divide-by-two circuit 12 shown in Figure 1 can be implemented in various forms of logic, or is a travelling wave divider. The divide- by-two circuit 12 is preferably, formed from two flip-flops. Since the flip-flops are triggered by the leading and trailing edges of the signal CD, the ouφuts of the flip-flops will be 90° out of phase. DBTOl and DBTO2 are then input to a conventional phase detector 14 that detects a phase difference between the two signals. Phase detector 14 ouφuts the phase tracking error signal (PTE). Signal PTE is a pulse train representing an "error" between the phase difference between DBTOl and DBTO2 and 90°. If DBTOl and DBTO2 are exactly 90° out of phase with each other, there is no phase error between DBTOl and DBTO2, and PTE is a constant voltage ouφut as PTE, with no pulses. If DBTOl is more than 90° ahead of DBT02 the phase detector 14 ouφuts pulses of a first polarity and if DBT02 is less than 90° ahead of DBT02 the phase detector produces pulses of a second polarity opposite to the first polarity. The duration, or width, of a pulse of signal PTE corresponds to the amount of the error between DBTOl and DBTO2 being exactly 90° out of phase. The more narrow the pulses of PTE, the more closely DBTOl and DBTO2 are to being exactly 90° out of phase. The phase detector 14 of Figure 1 is coupled to a conventional low-pass filter 16 and the signal PTE is input to the low-pass filter 16. Low-pass filter 16 ouφuts D.C. level signal (DCL), which is the DC level of the input signal PTE. In the present invention, the closer DBTOl and DBT02 are to being exactly 90° out of phase, the more narrow are the pulses of PTE, and the smaller is the DC level of DCL. Low-pass filter 16 is coupled to a conventional integrator 18, as shown in Figure 1. DCL is input to integrator 18, which ouφuts reference voltage V r . V r , in the present invention, is a reference voltage representing the voltage level which is the zero crossing level of the sinusoid SD. V r is related to the duty cycle of the pulse train PTE, and is the DC voltage of phase tracking error signal PTE. V r is input to the negative terminal of the comparator 10, in the present invention. The level of the reference level signal V r changes as the phase difference changes, which in this feedback arrangement causes the phase difference to be adjusted toward exactly 90°. Therefore, the present invention, as shown in Figure 1, is a circuit detecting and "locking" on the voltage level V r necessary to produce a 90° phase difference. V r is the reference voltage level at which the input sinusoidal signal has a 50% duty cycle in crossing V The level locked loop of the present invention, once V r is detected and "locked", then ouφuts two signals I and Q which are 90° out of phase, with less than one degree of error. Figures 2A-2C are timing diagrams showing that a perfect 2f input sinusoid produces I and Q signals which are exactly 90° out of phase. A "zero crossing" is an arbitrary voltage level at which a signal, such as signal 2f, "crosses" following a sinusoidal path. In Figure 2A, signal 2f has a 50% duty cycle and crosses the "zero crossing" at evenly-spaced intervals. In Figures 2A-2C, when signal 2f crosses from below the zero crossing to above the zero crossing, I goes from logic state 0 to logic state 1 and Q remains in logic state 0. Then, in Figures 2A-2C, when signal 2f crosses from above the zero crossing to below the zero crossing I remains in logic state 1 and Q goes from logic state 0 to logic state 1. When signal 2f goes from below the zero crossing to above the zero crossing, i.e. completes one cycle, signal I goes from logic state 1 to logic state 0, and signal Q remains in logic state 1. Therefore, signals I and Q are 90° out of phase with each other. Figures 3A-3C are timing diagrams showing an input signal 2f having a second order harmonic content, which causes an error in the phase difference between the I signal and the Q signal, if the threshold of the comparator 10 is set at V 0 . As shown in Figures 3A-3C, signal Q goes from logic state 0 to logic state 1 more than 90° after signal I goes from logic state 0 to logic state 1, based on input signal 2f transitioning from a positive state to a negative state by crossing the zero crossing line of V 0 . Also as shown in Figures 3A-3C, in accordance with die present invention, if the comparator threshold is set to V r , then input signal 2f transitions from the positive state to the negative state 90° after input signal 2f has transitioned from the negative state to the positive state, by crossing V r as the zero threshold crossing. In the situation of a waveform as in Figure 3A, the present invention adjusts the zero crossing to V r as shown. Therefore, in the present invention, I and Q are 90° out of phase, when the zero crossing line is moved from the level of V 0 to the level of V r . Therefore, the level locked loop of Figure 1 determines, and "locks on", voltage level V r , which is the voltage at which signal 2f has a 50% duty cycle. Further, V r is the voltage level at which the zero voltage crossings of signal 2f are equally spaced. Figure 4 is a diagram of an input signal W Input signal V j is a combination of signal L j , which has a frequency of ω 2 , and input signal V j , which has a frequency of ω j and is superimposed on signal L j . Therefore, input signal V j does not have a constant voltage input. The level-locked loop of Figure 1 is also designed to be used with an input signal V , as shown in Figure 4. In this case, the voltage level of the input signal V, is not constant, and is superimposed over signal L j , as shown in Figure 4. As described previously for a different signal, in Figure 1, V j (of Figure 4) is input to me comparator 10, which ouφuts a signal CD. The comparator 10, shown in Figure 1, is coupled to the divide- by-two circuit 12. The divide-by-two circuit 12 ouφuts two signals, DBTOl and DBT02. DBTOl and DBT02 are then input to the phase detector 14, which ouφuts signal PTE. PTE is input to low-pass filter 16, which then ouφuts signal DCL, also as previously described. Signal DCL is equivalent to V out , which is described herein below. Signal DCL is then input to the integrator 18, which has a transfer function of , where B is a constant, R and C are values of resistance and capacitance, respectively, and S is a complex frequency jω. ω is equal to 2τf. Integrator 18 ouφuts signal L f , which is analogous to V r and is input to the negative terminal of comparator 10. The level locked loop of Figure 1 operates on the input signal V j illustrated in Figure 4, as the level locked loop described in Figure 1 operates on the 800MHz sinusoid input signal, as previously described. The equations for the level locked loop of Figure 1 are described herein below. If V I =A 1 Sinω 1 t+A 2 Sintύ 2 t , (1) where 0 < A 2 <A j , then L j = A 2 Sin ω 2 t (2) then, for a small range of input signal L j , Figures 5A-5E show the relationship between L j , L f , CD, I, Q, and V out . In Figure 5A, Lf is at a higher voltage level than L j . Input signal A ] Sin ω } t, is input to the level locked loop of Figure 1. CD is men ouφut, as a pulse train, driven by A j Sin ω j t crossing Lf. The width of me pulse for CD is x , as shown in Figure 5B. As shown in Figure 5C, when A j Sin ω t crosses L f , going from a negative value to a positive value, I goes from logic state 0 to logic state 1. Then, as shown in Figure 5D, when A t Sin ω ] t crosses Lf going from the positive to a negative value, Q goes from logic state 0 to logic state 1, phase shifted from I by the width of one pulse of signal CD, which is φx L . Accordingly, as shown in Figure 5E, signal PTE is ouφut, as previously described. V out retains a constant level. V out max is the height of me pulse train PTE. Then, letting V l equal L f , Lf - L j = A j Sin ω j t (3) Solving for then, where --? <ω, t 1 <-5. 2 2 Therefore, Then, V out — V^Si -H ^^ ) (6) Therefore, in the frequency domain, L ' ls) * ττitcs v -< <s CT where B is a low frequency gain of the integrator 18, R is me resistance of the integrator 18, and C is the capacitance of the integrator 18. For * J <1 , * oouutt = π _ " * aanmιwwrr * » ; ' (8) In the frequency domain, then V out (S) = VoaΛX (L f (S) -L ± (S) ) (9) Then, by inserting the value of L f (S) and solving for V out (S), the transfer function of the level locked loop shown in Figure 1 is: V out (S) ^ 2 V omax ( l +BRCS) (10) Lt S) 2 V oαax B-ιιA 1 ( 1 +BRCS) In the present invention, for the incoming signal equal to Sin (ωt) + A cos (ωt), where A represents a small second harmonic component, Sin (ωt) + A cos (2ω) = 0 to determine the 0 crossing points, which is the voltage level at which the input signal has a 50% duty cycle. Therefore, -2A Sin 2 (ωt) + Sin (ωt) + A = 0. Then, Sin (ωt) = (1-(1 +8A 2 ) 0 5 )/4A, which can be approximated as Sin (ωt) = -A. Assuming that A< < 1, then ωt = -A. For ωt = 1°, then A = 0.0174, or - 35.2dB. Therefore, to obtain less than one degree of phase error in the quadrature signals I and Q, the second harmonic content of the 800MHz sinusoid input is less than 35dBc, under worst case conditions. As described herein above, the level locked loop of the present invention, is a highly non-linear circuit with a behavior that depends on the shape of the input signal. If the input signal is sinusoidal with a frequency of ω l t which rides on a low frequency sinusoid ω 2 , as shown in Figures 4 and 1, the level of equally-space zero crossings is defmed as L^. The feedback signal provided by the level locked loop of Figure 1 is L f , and the final ouφut of me level locked loop of Figure 1 is V out , which is the ouφut of the low-pass filter, after being phase detected. As shown above the present invention tracks the reference level necessary to maintain a quadrature phase relationship between quadrature signals when the reference level is used as a zero crossing for quadrature signal generation. The many features and advantages of the invention are apparent from the detailed specification and, thus, it is intended by the appended claims to cover all such features and advantages of the invention which fall within the true spirit and scope of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.

Claims: CLAIMS 1. A circuit for generating a quadrature signal comprising an oscillator for generating an oscillator signal, characterised in that the circuit comprises a duty cycle modulator for deriving from the oscillator signal, a first signal having a duty cycle determined by a control signal, a divide-by-two circuit, for generating a second signal and a third signal having a mutual phase difference of 90°, a phase detector for generating a quadrature error signal representative of a quadrature error between the second and the third signal, and control means for deriving the control signal from the quadrature error signal. 2. The circuit as claimed in claim 1, characterised in that the duty cycle modulator comprises a comparator for deriving the first signal in dependence on the difference between the input signal and the control signal. 3. Circuit according to one of the previous claims, characterised in that the oscillator signal is a sinewave. 4. Circuit according to claim 3, characterised in that the sinewave has a frequency greater tiian or equal to 800 MHz. 5. The circuit as according to claim 1 or 2, characterised in that the oscillator signal is a sum of two signals at different frequencies. 6. A circuit for generating a quadrature signal from an input signal, characterised in that the circuit comprises a duty cycle modulator for deriving from the input signal a first signal having a duty cycle determined by a control signal, a divide-by-two circuit, for generating a second signal and a third signal having a mutual phase difference of 90°, a phase detector for generating a quadrature error signal representative of a quadrature error between the second and the third signal, and control means for deriving the control signal from the phase error signal. 7. The circuit as claimed in claim 1 , characterised in that the duty cycle modulator comprises a comparator for deriving the first signal in dependence on the difference between the input signal and the control signal. 8. Method for generating a quadrature signal from an input signal, characterised in that the method comprises deriving a first signal having a duty cycle determined by a control signal from the input signal, generating from the first signal a second signal and a third signal having a mutual phase difference of 90°, generating a quadrature error signal representative of a quadrature error between the second and the third signal, and control means for deriving the control signal from the quadrature error signal. 9. The method as claimed in claim 8, characterised in that the method comprises deriving the first signal in dependence on the difference between the input signal and the control signal.

Inventors: BEHBAHANI FARBOD BEHBAHANI, FOTOWAT-AHAMDY ALI, HAJIMIRI ALI, NAVID NASROLLAH SAEED, BEHBAHANI, FARBOD, BEHBAHANI, FOTOWAT-AHAMDY, ALI, HAJIMIRI, ALI, NAVID, NASROLLAH, SAEED
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1995
Main classification: H03B27
IPC codes: H03B27, H04L27