Normally off-static induction thyristor

Abstract: A normally-off semiconductor device with gate regions formed in a high-quality base is manufactured by forming a P+ layer (12) in a lower surface of an N - substrate (10), selectively forming P+ gate regions (42) in an upper surface (14) of the N - substrate (10), forming intergate P+ regions (46) in the upper surface (14) of the N - substrate (10) between the P+ gate regions (42), forming an N+ layer (22) in an upper surface of an N - substrate (20), joining the N - substrate (10) and the N - substrate (20) to each other by heating them at about 800°C in a hydrogen atmosphere while the upper surface (14) of the N - substrate (10) and a lower surface (24) of the N - substrate (20) are being held against each other, and forming an anode electrode (92) and a cathode electrode (94).

Description: BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates to a semiconductor device, and more particularly to a normally-off static induction thyristor. Description of the Related Art: FIGS. 1 through 3 of the accompanying drawings are illustrative of a conventional static induction thyristor 300 and a method of manufacturing the conventional static induction thyristor 300. Heretofore, the conventional static induction thyristor 300 has been manufactured as follows: First, as shown in FIG. 1, a P-type impurity is selectively diffused into one principal surface, i.e., an upper surface, of an N - substrate 310 to selectively form P + gate regions 314. Then, as shown in FIG. 2, an N- epitaxial layer 320 is deposited on the N - substrate 310 by chemical vapor deposition. At this time, P + gate regions 314 are also formed in the N - epitaxial layer 320 by automatic doping. Thereafter, as shown in FIG. 3, a P layer 312 is formed in a lower surface of the N - substrate 310 by diffusing an impurity therein, and an N + layer 322 is formed in the upper surface of the N - epitaxial layer 320 by diffusing an impurity therein. Then, an anode electrode 340 is deposited on a lower surface of the P layer 312, and a cathode electrode 350 is deposited on an upper surface of the N + layer 322. In the static induction thyristor 300 thus formed, the P layer 312 functions as an anode, the N + layer 322 as a cathode, both the N - substrate 310 and the N - epitaxial layer 320 as an N base 360, and the P + gate regions 314 as a gate for controlling an anode current flowing between the anode electrode 340 and the cathode electrode 350. In order to increase a maximum cutoff current, the conventional static induction thyristor 300 has the P + gate regions 314 of a high impurity concentration embedded in the N base 360. To embed the P + gate regions 314 in the N base 360, it is necessary to selectively form P + gate regions 314 in one principal surface of the N - substrate 310, as shown in FIG. 1, and thereafter to form the N - epitaxial layer 320 on the N - substrate 310 by way of chemical vapor deposition. Since the N - epitaxial layer 320 is formed on the N - substrate 310 after the P + gate regions 314 have selectively been formed in the N - substrate 310, the N - epitaxial layer 320 grown on the P + gate regions 314 tend to suffer crystal defects such as stacking faults. Therefore, it has been difficult to produce an N - epitaxial layer 320 of high quality, and hence it has also been difficult to produce an N base 360 of high quality. Inasmuch as the impurity of the P + gate regions 314 affects the crystallinity of the N - epitaxial layer 320, a certain limitation is posed on the impurity concentration of the P + gate regions 314. As a result, it has not been possible to increase the maximum cutoff current beyond a certain limit. To manufacture a conventional normally-off static induction thyristor 400 (see FIG. 6 of the accompanying drawings) from the conventional static induction thyristor 300 according to the method of manufacturing the conventional static induction thyristor 300, it is proposed to form P + regions 315 (see FIG. 4 of the accompanying drawings) between the P + gate regions 314. FIGS. 4 through 6 of the accompanying drawings are illustrative of a method of manufacturing such a conventional normally-off static induction thyristor 400 according to the method of manufacturing the conventional static induction thyristor 300. First, as shown in FIG. 4, a P-type impurity is selectively diffused into one principal surface, i.e., an upper surface, of an N - substrate 310 to selectively form P + gate regions 314. A P-type impurity is also selectively diffused into the principal surface of the N - substrate 310 to form P + regions 315 between the P + gate regions 314. Then, as shown in FIG. 5, an N - epitaxial layer 320 is deposited on the N - substrate 310 by chemical vapor deposition. At this time, P + gate regions 314 and P + regions 315 are also formed in the N - epitaxial layer 320 by automatic doping. Thereafter, as shown in FIG. 6, a P layer 312 is formed in a lower surface of the N - substrate 310 by diffusing an impurity therein, and an N + layer 322 is formed in the upper surface of the N - epitaxial layer 320 by diffusing an impurity therein. Then, an anode electrode 340 is deposited on a lower surface of the P layer 312, and a cathode electrode 350 is deposited on an upper surface of the N + layer 322. In the static induction thyristor 400 thus formed, the P layer 312 functions as an anode, the N + layer 322 as a cathode, both the N - substrate 310 and the N - epitaxial layer 320 as an N base 360, and the P + gate regions 314 as a gate for controlling an anode current flowing between the anode electrode 340 and the cathode electrode 350. Since the P + regions 315 are formed between the P + gate regions 314, a depletion layer is formed contiguously between the P + gate regions 314 even when no bias is applied to the gate. Therefore, the static induction thyristor 400 functions as a normally-off static induction thyristor. The normally-off static induction thyristor 400 manufactured according to the above process suffers problems, described below, in addition to the problems posed by the manufacture of the conventional static induction thyristor 300. In the normally-off static induction thyristor 400, not only the P + gate regions 314 of high impurity concentration, but also the P + regions 315 are embedded in the N base 360. To embed the P + gate regions 314 and the P + regions 315 in the N base 360, it is necessary to selectively form P + gate regions 314 and P + regions 315 in one principal surface of the N - substrate 310, as shown in FIG. 4, and thereafter to form the N - epitaxial layer 320 on the N - substrate 310 by way of chemical vapor deposition. Since the N - epitaxial layer 320 is formed on the N - substrate 310 after the P + gate regions 314 and the P + regions 315 have been formed in the N - substrate 310, the N - epitaxial layer 320 grown on the P + gate regions 314 and the P + regions 315 tend to suffer crystal defects such as stacking faults. Therefore, it has been difficult to produce an N - epitaxial layer 320 of high quality not only on the P + gate regions 314 but also between the P + gate regions 314, and it has also been difficult to produce an N base 360 of high quality. Inasmuch as the P + gate regions 314 are formed by diffusing an impurity into one principal surface of the N - substrate 310, the P + gate regions 314 have sound side edges. Consequently, depletion layers extending between the P + gate regions 314 doe no extend parallel to the direction of the anode current flowing between the anode and the cathode, with the result that a large current cannot be controlled by the gate. EP-A-22483 (corresponding to the preamble of claim 1), JP-A-62-62558 and US-A-4 198 645 show semiconductor devices having gate regions between two substrate bodies. SUMMARY OF THE INVENTION It is a general object of the present invention to provide a normally-off static induction thyristor having gate regions formed in a high-quality base. Another object of the present invention to provide a normally-off static induction thyristor capable of controlling a large current. Still another object of the present invention to provide a normally-off static induction thyristor which has uniform and high-quality crystallinity, allows gate regions to be doped with an impurity of high concentration, and is almost free of impurity diffusion. Yet still another object of the present invention to provide a semiconductor device which has a high dielectric strength when turned off, suffers a low leakage current, has an excellent cutoff capability, and is capable of controlling a large current. A further object of the present invention to provide a semiconductor device which can operate in a high frequency range, permits a carrier drawing current to be increased, and is capable of high-speed switching operation. According to the present invention, there is provided a semiconductor device as set out in claim 1. The above and other objects, features, and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 3 are fragmentary perspective cross-sectional views showing a conventional static induction thyristor and a method of manufacturing it; FIGS. 4 through 6 are fragmentary perspective cross-sectional views showing a conventional normally-off static induction thyristor and a method of manufacturing it; FIGS. 7A through 7D are fragmentary cross-sectional views showing a static induction thyristor which is a first embodiment of the present invention and a method of manufacturing it; FIGS. 8A through 8D are fragmentary cross-sectional views showing a static induction thyristor which is a second embodiment of the present invention and a method of manufacturing it; FIGS. 9A through 9D are fragmentary cross-sectional views showing steps in the manufacture of the static induction thyristors of the third and fourth embodiments of the present invention; FIGS. 10A and 10B are fragmentary cross-sectional views showing a static induction thyristor which is a third embodiment of the present invention and a method of manufacturing it; and FIGS. 11A and 11B are fragmentary cross-sectional views showing a static induction thyristor which is a fourth embodiment of the present invention and a method of manufacturing it. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 1st Embodiment:- FIGS. 7A through 7D are illustrative of a static induction thyristor which is a first embodiment of the present invention and a method of manufacturing it. First, N - substrates 10, 20 having respective mirror-finished surfaces to be joined to each other are prepared. Then, as shown in FIG. 7A, recesses 52 each having a width of about 50 µm and a depth of about 20 µm are defined at a pitch or spacing of about 70 µm in an upper surface 14 of the N - substrate 10 according to photolithography, leaving lands 54 between the recesses 52. Each of the recesses 52 has side walls 51 extending substantially perpendicularly to the upper surface 14 of the N - substrate 10. Then, as shown in FIG. 7B, a P + layer 12 is formed in a lower surface of the N - substrate 10 by diffusing an impurity therein. Then, a P-type impurity of boron is diffused into the N - substrate 10 from its upper surface 14, forming a P + region 60 in the entire upper surface 14 of the N - substrate 10. When the P + region 60 is formed in the entire upper surface 14, P + side gate regions 64, P + bottom gate regions 66, and intergate P + regions 62 are simultaneously formed. Specifically, the P + side gate regions 64 and the P + bottom gate regions 66 are formed in exposed regions of the N - substrate 10 on the side walls 51 and bottoms 53 of the recesses 52, and the intergate P+ regions 62 are formed in exposed regions of the N - substrate 10 on upper surfaces 56 of the lands 54. The P + bottom gate regions 66, the P + side gate regions 64, and the intergate P+ regions 62 are contiguous to each other. The P + side gate regions 64 and the P + bottom gate regions 66 jointly constitute P + gate regions 65. The boron is diffused into the N - substrate 10 at a temperature ranging from about 1050 to 1200°C in an atmosphere of BBr 3 + O 2 . When the boron is diffused, oxide films (not shown) are formed on the side walls 51 and bottoms 53 of the recesses 52 and also on the upper surfaces 56 of the lands 54. As shown in FIG. 7C, an N + layer 22 is formed in an upper surface of the N - substrate 20 by diffusing an impurity therein. Then, the N - substrates 10, 20 are ultrasonically cleaned with an aqueous solution of sulfuric acid and hydrogen peroxide, thereby removing organic substances and metals. Thereafter, the N - substrates 10, 20 are cleaned with pure water, and dried by a spinner at room temperature. As shown in FIG. 7D, while the upper surfaces 56 of the lands 54 of the N - substrate 10 between the recesses 52 and a lower surface 24 of the N - substrate 20 are being held against each other, and the N - substrate 10 and the N - substrate 20 are joined to each other by being heated at about 800°C in a hydrogen atmosphere. Then, an anode electrode 92 and a cathode electrode 94 are formed respectively on a lower surface of the P + layer 12 formed in the lower surface of the N - substrate 10 and an upper surface of the N - layer 22 formed the upper surface of the N - substrate 20, thus producing a static induction thyristor 100. In the static induction thyristor 100, the P + layer 12 functions as an anode, the N + layer 22 as a cathode, both the N - substrates 10, 20 as an N base 30, and the P + gate regions 65 as a gate for controlling an anode current flowing between the anode electrode 92 and the cathode electrode 94. In this embodiment, since the N base 30 in which the P + gate regions 65 and the intergate P+ regions 62 are embedded is formed by joining the N - substrates 10, 20 to each other, the N base 30 has uniform, high-quality crystallinity. It is possible to make the P + gate regions 65 of high concentration for increasing a maximum cutoff current. According to this embodiment, the intergate P+ regions 62 are formed between the P + gate regions 65 contiguously thereto. Therefore, even when no bias is applied to the gate, a depletion layer is continuously spread between the P + gate regions 65, especially between the side gate regions 64, so that the static induction thyristor 100 functions as a normally-off static induction thyristor. The recesses 52 defined in the upper surface 14 of the N - substrate 10 and the lower surface 24 of the N - substrate 20 jointly create cavities in the N base 30, and the side gate regions 64 are formed on exposed regions of the N - substrate 10 at the side walls 51 of the recesses 52. Since the anode current flows along the side walls 51 of the recesses 52, the side gate regions 64 formed along the side walls 51 of the recesses 52 increase a channel width, so that the length of the depletion layer which extends from the gate regions 65 when the static induction thyristor is turned off is increased in the direction in which the anode current flows. Therefore, the static induction thyristor 100 has a high dielectric strength when turned off, suffers a low leakage current, has an excellent cutoff capability, and is capable of controlling a large current. Because the channel width is increased, the static induction thyristor 100 is given desired turn-off characteristics even if the distance between the gate regions 65 is not reduced, and hence it is not necessary to reduce the distance between the recesses 52 in the N - substrate 10. As a consequence, a yield can be increased at the time the recesses 52 are defined in a fine pattern in the upper surface of the N - substrate 10. Since it is not necessary to reduce the distance between the recesses 52 in the N - substrate 10, the cross-sectional area of the N - substrate 10 between the recesses 52 is prevented from being reduced, and the resistance of the N - substrate 10 between the recesses 52 is lowered, with the results that the voltage across the static induction thyristor 100 when it is turned on is lowered, and the static induction thyristor 100 can handle a large current. With the side walls 51 of the recesses 52 extending substantially parallel to the direction of the anode current flowing between the anode electrode 92 and the cathode electrode 94, the side gate regions 64 extend also substantially parallel to the direction of the anode current. As a result, the depletion layer formed at the time the static induction thyristor 100 is turned off extends uniformly the fully length of the channel between the gate regions 65. Consequently, the static induction thyristor 100 has a higher dielectric strength when turned off, suffers a lower leakage current, has a more excellent cutoff capability, and is capable of controlling a larger current. 2nd Embodiment :- FIGS. 8A through 8D are illustrative of a static induction thyristor which is a second embodiment of the present invention and a method of manufacturing it. First, as shown in FIGS. 8A and 8B, recesses 52 are defined in an upper surface 14 of the N - substrate 10, leaving lands 54 between the recesses 52, a P + layer 12 is formed in a lower surface of the N - substrate 10 by diffusing an impurity therein, a P + region 60 is formed in the entire upper surface 14 of the N - substrate 10, whereupon P + side gate regions 64 and P + bottom gate regions 66 are formed in exposed regions of the N - substrate 10 on side walls 51 and bottoms 53 of the recesses 52, and intergate P+ regions 62 are formed in exposed regions of the N - substrate 10 on upper surfaces 56 of the lands 54, in the same manner as with the first embodiment. The P + bottom gate regions 66, the P + side gate regions 64, and the intergate P+ regions 62 are contiguous to each other. The P + side gate regions 64 and the P + bottom gate regions 66 jointly constitute P + gate regions 65. As shown in FIG. 8C, an N + layer 22 is formed in an upper surface of the N - substrate 20 by diffusing an impurity therein, and a P + layer 26 is formed in an entire lower surface 24 of the N - substrate 20 by diffusing an impurity therein. Then, the N - substrates 10, 20 are ultrasonically cleaned with an aqueous solution of sulfuric acid and hydrogen peroxide, thereby removing organic substances and metals. Thereafter, the N - substrates 10, 20 are cleaned with pure water, and dried by a spinner at room temperature. As shown in FIG. 8D, while the upper surfaces 56 of the lands 54 of the N - substrate 10 between the recesses 52 and a lower surface 24 of the N + substrate 20 are being held against each other, and the N - substrate 10 and the N - substrate 20 are joined to each other by being heated at about 800°C in a hydrogen atmosphere. Then, an anode electrode 92 and a cathode electrode 94 are formed respectively on a lower surface of the P + layer 12 formed in the lower surface of the N - substrate 10 and an upper surface of the N + layer 22 formed the upper surface of the N - substrate 20, thus producing a static induction thyristor 100. In the static induction thyristor 100, the P + layer 12 functions as an anode, the N + layer 22 as a cathode, both the N - substrates 10, 20 as an N base 30, and the P + gate regions 65 as a gate for controlling an anode current flowing between the anode electrode 92 and the cathode electrode 94. In this embodiment, since the N base 30 in which the P + gate regions 65 and the intergate P+ regions 62 embedded is formed by joining the N - substrates 10, 20 to each other, the N base 30 has uniform, high-quality crystallinity. Because the P + region 26 is formed in the lower surface 24 of the N - substrate 20, the N - substrate 20 is well electrically connected to the N - substrate 10. It is possible to make the P + gate regions 65 of high concentration for increasing a maximum cutoff current. According to this embodiment, the intergate P+ regions 62 are formed between the P + gate regions 65 contiguously thereto, and the P + region 26 is disposed on the intergate P+ regions 62. Therefore, even when no bias is applied to the gate, a depletion layer is continuously spread between the gate regions 65, especially between the side gate regions 64, so that the static induction thyristor 100 functions as a normally-off static induction thyristor. 3rd Embodiment :- FIGS. 9A through 9D and 10A, 10B are illustrative of a static induction thyristor which is a third embodiment of the present invention and a method of manufacturing it. First, as shown in FIGS. 9A and 9B, recesses 52 are defined in an upper surface 14 of the N - substrate 10, leaving lands 54 between the recesses 52, a P + layer 12 is formed in a lower surface of the N - substrate 10 by diffusing an impurity therein, a P + region 60 is formed in the entire upper surface 14 of the N - substrate 10, whereupon P + side gate regions 64 and P + bottom gate regions 66 are formed in exposed regions of the N - substrate 10 on side walls 51 and bottoms 53 of the recesses 52, and intergate P+ regions 62 are formed in exposed regions of the N - substrate 10 on upper surfaces 56 of the lands 54, in the same manner as with the first embodiment. The P + bottom gate regions 66, the P + side gate regions 64, and the intergate P+ regions 62 are contiguous to each other. The P + side gate regions 64 and the P + bottom gate regions 66 jointly constitute P + gate regions 65. As shown in FIG. 9C, a gate electrode film 72 of tungsten having a film thickness of 0.3 µm is deposited on the entire upper surface 14 of the N - substrate 10 by chemical vapor deposition. Then, as shown in FIG. 9D, the gate electrode film 72 is patterned into gate electrodes 74, each having a width of about 25 µm, in the respective recesses 52 on the bottom gate regions 66 according to photolithography. Thereafter, as shown in FIG. 10A, an N + layer 22 is formed in an upper surface of the N - substrate 20 by diffusing an impurity therein. Then, the N - substrates 10, 20 are ultrasonically cleaned with an aqueous solution of sulfuric acid and hydrogen peroxide, thereby removing organic substances and metals. Thereafter, the N - substrates 10, 20 are cleaned with pure water, and dried by a spinner at room temperature. As shown in FIG. 10B, while the upper surfaces 56 of the lands 54 of the N - substrate 10 between the recesses 52 and a lower surface 24 of the N - substrate 20 are being held against each other, and the N - substrate 10 and the N - substrate 20 are joined to each other by being heated at about 800°C in a hydrogen atmosphere. If the gate electrodes 74 are made of aluminum, then the N - substrate 10 and the N - substrate 20 are joined to each other at about 400°C. Then, an anode electrode 92 and a cathode electrode 94 are formed respectively on a lower surface of the P + layer 12 formed in the lower surface of the N - substrate 10 and an upper surface of the N + layer 22 formed the upper surface of the N - substrate 20, thus producing a static induction thyristor 100. In the static induction thyristor 100, the P + layer 12 functions as an anode, the N + layer 22 as a cathode, both the N - substrates 10, 20 as an N base 30, and the P + gate regions 65 as a gate for controlling an anode current flowing between the anode electrode 92 and the cathode electrode 94. In this embodiment, since the N base 30 in which the P + gate regions 65 and the intergate P+ regions 62 embedded is formed by joining the N - substrates 10, 20 to each other, the N base 30 has uniform, high-quality crystallinity. It is possible to make the P + gate regions 65 of high concentration for increasing a maximum cutoff current. According to this embodiment, the intergate P+ regions 62 are formed between the P + gate regions 65 contiguously thereto. Therefore, even when no bias is applied to the gate, a depletion layer is continuously spread between the gate regions 65, especially between the side gate regions 64, so that the static induction thyristor 100 functions as a normally-off static induction thyristor. According to this embodiment, since the gate electrodes 74 of tungsten are disposed on the bottom gate regions 66, the resistance of the gate in a lateral direction is reduced to increase the maximum cutoff current, and a carrier drawing current is increased for higher-speed switching. Because the gate electrodes 74 are already accommodated in the recesses 52 in the N - substrate 10 before the N - substrates 10, 20 are joined to each other, it is not necessary to define grooves of a large aspect ratio in the N + layer 22 and the N - substrate 20 for the formation of the gate electrodes 74 therein. The N + layer 22 and the N - substrate 20 do not have a high resistance which would otherwise result if they were divided into small strips by such grooves. Since the recesses 52 defined in the upper surface of the N - substrate 10 are small enough to accommodate the gate electrodes 74, it is not time-consuming to define the recesses 52 in the upper surface of the N - substrate 10. The gate electrodes 74 are accommodated in the recesses 52 in the N - substrate 10. Therefore, it is not necessary to define recesses in the lower surface 24 of the N - substrate 20 which is joined to the lands 54 on the upper surface of the N - substrate 10, and hence the lower surface 24 may remain flat. Consequently, no special registration process is required for joining the lands 54 on the upper surface of the N - substrate 10 and the lower surface 24 of the N - substrate 20 to each other, and the static induction thyristor 100 can be manufactured relatively easily. 4th Embodiment :- FIGS. 9A through 9D and 11A, 11B are illustrative of a static induction thyristor which is a fourth embodiment of the present invention and a method of manufacturing it. First, as with the third embodiment shown in FIGS. 9A through 9D, recesses 52 are defined in an upper surface 14 of the N - substrate 10, leaving lands 54 between the recesses 52, a P + layer 12 is formed in a lower surface of the N - substrate 10 by diffusing an impurity therein, a P + region 60 is formed in the entire upper surface 14 of the N - substrate 10, whereupon P + side gate regions 64 and P + bottom gate regions 66 are formed in exposed regions of the N - substrate 10 on side walls 51 and bottoms 53 of the recesses 52, and intergate P+ regions 62 are formed in exposed regions of the N - substrate 10 on upper surfaces 56 of the lands 54. The P + bottom gate regions 66, the P + side gate regions 64, and the intergate P+ regions 62 are contiguous to each other. The P + side gate regions 64 and the P + bottom gate regions 66 jointly constitute P + gate regions 65. Gate electrodes 74 of tungsten are selectively formed on the bottom gate regions 66 in the recesses 52. Thereafter, as shown in FIG. 11A, an N + layer 22 is formed in an upper surface of the N - substrate 20 by diffusing an impurity therein, and a P + layer 26 is formed in an entire lower surface 24 of the N - substrate 20 by diffusing an impurity therein. Then, the N - substrates 10, 20 are ultrasonically cleaned with an aqueous solution of sulfuric acid and hydrogen peroxide, thereby removing organic substances and metals. Thereafter, the N - substrates 10, 20 are cleaned with pure water, and dried by a spinner at room temperature. As shown in FIG. 11B, while the upper surfaces 56 of the lands 54 of the N - substrate 10 between the recesses 52 and a lower surface 24 of the N - substrate 20 are being held against each other, and the N - substrate 10 and the N - substrate 20 are joined to each other by being heated at about 800°C in a hydrogen atmosphere. Then, an anode electrode 92 and a cathode electrode 94 are formed respectively on a lower surface of the P + layer 12 formed in the lower surface of the N - substrate 10 and an upper surface of the N + layer 22 formed the upper surface of the N - substrate 20, thus producing a static induction thyristor 100. In the static induction thyristor 100, the P + layer 12 functions as an anode, the N + layer 22 as a cathode, both the N - substrates 10, 20 as an N base 30, and the P + gate regions 65 as a gate for controlling an anode current flowing between the anode electrode 92 and the cathode electrode 94. In this embodiment, since the N base 30 in which the P + gate regions 65 and the intergate P+ regions 62 embedded is formed by joining the N - substrates 10, 20 to each other, the N base 30 has uniform, high-quality crystallinity. Because the P + region 26 is formed in the lower surface 24 of the N - substrate 20, the N - substrate 20 is well electrically connected to the N - substrate 10. According to this embodiment, the intergate P+ regions 62 are formed between the P + gate regions 65 contiguously thereto, and the P + region 26 is disposed on the intergate P+ regions 62. Therefore, even when no bias is applied to the gate, a depletion layer is continuously spread between the gate regions 65, especially between the side gate regions 64, so that the static induction thyristor 100 functions as a normally-off static induction thyristor. According to this embodiment, since the gate electrodes 74 of tungsten are disposed on the bottom gate regions 66, the resistance of the gate in a lateral direction is reduced to increase the maximum cutoff current, and a carrier drawing current is increased for higher-speed switching. While the gate electrodes 74 are made of tungsten in the third and fourth embodiments, the gate electrodes 74 may be made of a metal of high melting point, such as molybdenum or the like, or polycrystalline silicon doped with an impurity of boron or the like, or aluminum or the like. In the methods herein illustrated, first and second semiconductor substrates of one conductivity type are prepared, gate regions of a semiconductor of another conductivity type are formed in one principal surface of the first semiconductor substrate, then first semiconductor regions of the other conductivity type are formed on the one principal surface of the first semiconductor substrate between the gate regions, after which the one principal surface of the first semiconductor substrate between the gate regions and one principal surface of a second semiconductor substrate are joined to each other. With this arrangement, a base having uniform, high-quality crystallinity is obtained. Since the first semiconductor regions of the same conductivity type as the gate regions are formed between the gate regions, a normally-off static induction thyristor is easily manufactured. If the gate regions are disposed in regions of the first semiconductor substrate which are exposed on side walls of recesses defined in the one principal surface of the first semiconductor substrate, then a semiconductor device is manufactured which has a high dielectric strength when turned off, suffers a low leakage current, has an excellent cutoff capability, and is capable of controlling a large current. As a result, a yield can be increased at the time the recesses are defined in a fine pattern in the one principal surface of the first semiconductor substrate. The cross-sectional area of the first semiconductor substrate between the recesses is prevented from being reduced, lowering the resistance of the first semiconductor substrate between the recesses. As a result, the voltage across the semiconductor device when it is turned on is lowered, allowing the semiconductor device to handle a large current. If the gate regions of the other conductivity type are also disposed in regions of the first semiconductor substrate which are exposed on bottoms of recesses defined in the one principal surface of the first semiconductor substrate, then the resistance of the gate in a lateral direction is reduced to increase the maximum cutoff current, and the semiconductor device can operate in a high frequency range. If a second semiconductor region of the other conductivity type is formed on the one principal surface of the second semiconductor substrate and thereafter the one principal surface of the first semiconductor substrate between the gate regions and the one principal surface of the second semiconductor substrate are joined to each other, then they are well electrically connected to each other. If gate electrodes of a good conductor electrically connected to the gate regions are disposed in the recesses defined in the one principal surface of the first semiconductor substrate and thereafter the one principal surface of the first semiconductor substrate and the one principal surface of the second semiconductor substrate are joined to each other, then the resistance of the gate in a lateral direction is reduced to increase the maximum cutoff current, and a carrier drawing current is increased for higher-speed switching. Since the gate electrodes are already accommodated in the recesses in the first semiconductor substrate before the one principal surface of the first semiconductor substrate and the one principal surface of the second semiconductor substrate are joined to each other, it is not necessary to define grooves of a large aspect ratio in the semiconductor substrate for the formation of the gate electrodes therein. The semiconductor substrate above the gate electrodes does not have a high resistance which would otherwise result if it were divided into small strips by such grooves. Since the recesses defined in the one principal surface of the first semiconductor substrate are small enough to accommodate the gate electrodes, it is not time-consuming to define the recesses according to a dry etching process with a low etching rate. The gate electrodes are accommodated in the recesses in the one principal surface of the first semiconductor substrate. Therefore, it is not necessary to define recesses in the one principal surface of the second semiconductor substrate which is joined to the one principal surface of the first semiconductor substrate, and hence the one principal surface of the second semiconductor substrate may remain flat. Consequently, no special registration process is required for joining the one principal surface of the first semiconductor substrate and the one principal surface of the second semiconductor substrate to each other, and the semiconductor device can be manufactured relatively easily. The semiconductor device according to the present invention having a gate structure according to claim 1 is disposed in a semiconductor substrate between anode and cathode electrodes for controlling a current flowing between the anode and cathode electrodes, the semiconductor substrate having cavities defined therein and gate regions of a semiconductor which are disposed in regions exposed on side walls of the cavities. Consequently, the semiconductor device has a high dielectric strength when turned off, suffers a low leakage current, has an excellent cutoff capability, and is capable of controlling a large current. Even if the interval between the gate regions is not reduced, the semiconductor device is given desired characteristics, and it is not necessary to reduce the distance between the cavities in the semiconductor substrate. As a consequence, a yield can be increased at the time the cavities are defined in a fine pattern in the semiconductor substrate. Since it is not necessary to reduce the distance between the cavities, the cross-sectional area of the semiconductor substrate between the cavities is prevented from being reduced, and the resistance of the semiconductor substrate between the cavities is lowered, with the results that the voltage across the semiconductor device when it is turned on is lowered, and the semiconductor device can handle a large current. The semiconductor device has a semiconductor region of the same conductivity type as the gate regions, which is disposed between the gate regions such that a depletion layer is continuously spread between the gate regions when no bias is applied to the gate. The semiconductor device thus arranged functions as a normally-off semiconductor device. With the semiconductor region being contiguous to the gate regions, a depletion layer is more reliably continuously spread between the gate regions when no bias is applied to the gate. If the side walls of the cavities extend substantially parallel to the direction of the current flowing between the anode and cathode electrodes, then the semiconductor device has a higher dielectric strength when turned off, suffers a lower leakage current, has a more excellent cutoff capability, and is capable of controlling a larger current. Inasmuch as the distance between the cavities in the semiconductor substrate can be increased, a yield can be increased to a greater degree at the time the cavities are defined in a fine pattern in the semiconductor substrate. The cross-sectional area of the semiconductor substrate between the cavities can be increased, and the resistance of the semiconductor substrate between the cavities can be further lowered, with the results that the voltage across the semiconductor device when it is turned on can be further lowered, and the semiconductor device can handle a larger current. If the gate regions are also disposed on regions exposed on bottoms of the cavities in the semiconductor substrate, then the resistance of the gate in a lateral direction is reduced to increase the maximum cutoff current, the semiconductor device can operate in a high frequency range. If gate electrodes of a good conductor electrically connected to the gate regions are disposed in the cavities defined in the semiconductor substrate, then the resistance of the gate in a lateral direction is reduced to increase the maximum cutoff current, and a carrier drawing current is increased for higher-speed switching.

Claims: A semiconductor device comprising: an anode electrode (92); a cathode electrode (94); a semiconductor substrate (30) disposed between said anode electrode (92) and said cathode electrode (94); and a gate (64,65,66,74) disposed in said semiconductor substrate for controlling a current flowing between said anode electrode (92) and said cathode electrode (94); said semiconductor substrate having cavities (52) defined therein; said gate having gate regions (64) of semiconductor material disposed at regions of said semiconductor substrate which are exposed at side walls of said cavities; characterised by : there being semiconductor regions (62) of the same conductivity type as said gate regions (64), which are disposed between said gate regions (64) such that a depletion layer is continuously spread between said gate regions (64) when no bias is applied to said gate; said gate regions (64) and said semiconductor regions (62) between said gate regions are of conductivity type opposite that of adjacent portions of the semiconductor substrate (30); and said gate regions (64) and said semiconductor regions (62) between said gate regions are doped layer portions of said semiconductor substrate (30). A semiconductor device according to claim 1, wherein said semiconductor regions (62) between said gate regions are contiguous to said gate regions. A semiconductor device according to claim 1 or 2, wherein said side walls of said cavities extend substantially parallel to the direction in which the current flows between said anode electrode and said cathode electrode. A semiconductor device according to claim 1, 2 or 3, wherein said gate further comprises gate regions (66) disposed on regions of said semiconductor substrate which are exposed at bottoms of said cavities (52). A semiconductor device according to any one of claims 1 to 4, wherein said gate further comprises gate electrodes (74) of a good conductor which are electrically connected to said gate regions (64), said gate electrodes (74) being disposed in said cavities (52). A semiconductor device according to any one of claims 1 to 5, wherein said semiconductor substrate (30) comprises a first semiconductor layer (12) of a first conductivity type, a second semiconductor layer (10,20) of a second conductivity type disposed on said first semiconductor layer, and a third semiconductor layer (22) of the second conductivity type having a higher impurity concentration than said second semiconductor layer, one of said anode electrode (92) and said cathode electrode (94) being electrically connected to said first semiconductor layer (12), the other of said anode electrode and said cathode electrode being electrically connected to said third semiconductor layer (22), said gate regions (64) and said semiconductor regions (62) between said gate regions being made of said first conductivity type, said cavities (52), said gate regions (64), and said semiconductor regions (62) being disposed in said second semiconductor layer (10,20).

Inventors: TERASAWA YOSHIO, TERASAWA, YOSHIO
Applicants: NGK INSULATORS LTD, NGK INSULATORS, LTD.
Application year: 1995
Main classification: H01L29
IPC codes: H01L29, H01L21