Structure and method for shifting and reordering a plurality of data bytes

Abstract: A shifter circuit and method for simultaneously and independently shifting and reordering a plurality of data bytes. The shifter circuit includes first and second registers which each receive a plurality of data bytes. The first register is coupled to a plurality of first buses, with each of the first buses receiving a data byte from the first register. Similarly, the second register is coupled to a plurality of second buses, with each of the second buses receiving a data byte from the second register. A multiplicity of third buses are coupled to the first and second buses. A byte shifting multiplexer is coupled to each of the third buses. A plurality of bit shifting multiplexer are coupled to the byte shifting multiplexers, with each bit shifting multiplexer being coupled to a pair of byte shifting multiplexers. A control circuit is coupled to the byte shifting and bit shifting multiplexers. The control circuit provides for independent control of each of the byte shifting multiplexers. The control circuit also provides for independent control of each of the bit shifting multiplexers.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to shifter circuitry for use in a data processing system. In particular, the present invention relates to a structure and method for independently shifting a plurality of bytes in a data processing system. Description of the Prior Art A shifter circuit employing an array of barrel shifters for shifting data is disclosed in European Patent EP-A-0-122-016 issued to Phelps et al. The shifter circuit of Phelps et al, is composed of an array of barrel shifter circuits arranged into N groups of M shifter circuits per group wherein each shifter circuit has P data input terminals, P controls input terminals and P output terminals. Each of the P output terminals of each M shifter circuits in a group are coupled to one another, respectively, so as to form N x P output terminals of the array. Real time digital signal processing in applications such as video signal processing requires high computational rates. To help achieve these rates, shifter circuitry has been used to shift a plurality of data bytes. Prior art shifters typically utilize barrel shifter circuitry to allow a plurality of bytes to be shifted by a fixed number of bits. That is, all bytes are shifted in the same direction by the same number of bits. In addition to byte shifting, certain data processing operations require byte reordering. This reordering is typically performed by separate multiplexer circuitry. As a result of the separate byte shifting and reordering circuitry, the speed of prior art video signal processing has been limited. In addition, the prior art byte shifting and reordering circuitry consumes a relatively large area on the video signal processing chip. It is therefore an object of the present invention to provide a shifter circuit which exhibits a reduced layout area and allows data bytes to be independently shifted and reordered on the same clock cycle. This object is achieved by a shifter circuit having the features of claim 1 and a method for reordering data bytes as claimed by claim 8. Preferred embodiments of the present invention are claimed by the subclaims. The present invention will be more fully understood in view of the following drawings taken together with the detailed description. Brief Description of the Drawings Fig. 1 is a block diagram of a shifter circuit in accordance with one embodiment of the present invention; Fig. 2 is a block diagram of one of the bit shifting multiplexers of the shifter circuit of Fig. 1. Fig. 3 is a schematic diagram illustrating the control of bit shifting multiplexers and bit shifting multiplexers in accordance with one embodiment of the present invention; and Fig. 4 is a schematic diagram of a shifter circuit in accordance wiht an alternate embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION Fig. 1 is a block diagram illustrating one embodiment of shifter circuit 100 in accordance with one embodiment of the present invention. Shifter circuit 100 has two 72-bit input registers 101 and 102. Input register 101 receives a 72-bit input IL[71:0] which includes eight 9-bit bytes. Input IL [71:0] is ordered from a most significant byte, IL[71:63], to an intermediate significance byte, IL[8:0]. Input register 102 receives a 72-bit input IR[71:0] which also includes eight 9-bit bytes. Input IR[71:0] is ordered from an intermediate significance byte IR[71:63], to a least significant byte, IR[8:0]. Input register 101 is coupled to eight output buses 111-118. Each of buses 111-118 carries a 9-bit byte. Nine-bit bus 111 carries most significant byte IL[71:63] and 9-bit bus 118 carries intermediate significance byte IL[8:0]. Similarly, input register 102 is coupled to eight output buses 121-128. Each of buses 121-128 carries a 9-bit byte. Nine-bit bus 121 carries intermediate significance byte IR[71:63] and 9-bit bus 128 carries least significant byte IR[8:0]. Nine-bit buses 111-118 and 121-128 are coupled to multiplexers 11-26 through buses 131-146. Bus 131 couples each of 9-bit buses 111-118 to multiplexer 11. Multiplexer 11 is an 8-to-1 multiplexer which passes one of the bytes from 9-bit buses 111-118. Multiplexers 12-26 are 8-to-1 multiplexers similar to multiplexer 11. Buses 132 and 133 couple 9-bit buses 112-118 and 121 to multiplexers 12 and 13, respectively. Buses 134 and 135 couple 9-bit buses 113-118 and 121-122 to multiplexers 14 and 15, respectively. Buses 136 and 137 couple 9-bit buses 114-118 and 121-123 to multiplexers 16 and 17, respectively. Buses 138 and 139 couple 9-bit buses 115-118 and 121-124 to multiplexers 18 and 19, respectively. Buses 140 and 141 couple 9-bit buses 116-118 and 121-125 to multiplexers 20 and 21, respectively. Buses 142 and 143 couple 9-bit buses 117-118 and 121-126 to multiplexers 22 and 23, respectively. Buses 144 and 145 couple 9-bit buses 118 and 121-127 to multiplexers 24 and 25, respectively. Bus 146 couples 9-bit buses 121-128 to multiplexer 26. Each of multiplexers 11-26 pass a 9-bit byte, thereby creating two 72-bit outputs, OL[71:0] and OR[71:0]. Each byte of OL[71:0] is selected from one of eight adjacent bytes of the 16-byte concatenation of inputs IL[71:0] and IR[71:0]. Thus, the most significant byte OL[71:63] of output OL[71:0] is selected from one of the 8 bytes on buses 111-118. The second most significant byte OL[62:54] is selected from one of the eight bytes on buses 112-118 and 121. The least significant byte OL[8:0] is selected from one of the eight bytes on buses 118 and 121-127. In a similar manner, the most significant byte OR[71:63] of output OR[71:0] is selected from one of the eight bytes on buses 112-118 and 121 and the least significant byte OR[8:0] is selected from one of the eight bytes on buses 121-128. Each of multiplexers 11-26 is independently controlled. As a result, bytes from registers 101 and 102 can be reordered and shifted to perform data packing and unpacking. In one embodiment, the sixteen input bytes in registers 101 and 102 are packed into and out of two dimensional formats. Shifter circuit 100 optionally employs multiplexers 1-8 to perform a bit shifting operation. Multiplexers 1, 2, 3, 4, 5, 6, 7 and 8 receive inputs from multiplexer pairs 11-12, 13-14, 15-16, 17-18, 19-20, 21-22, 23-24 and 25-26, respectively. Fig. 2 is a block diagram of multiplexer 1 in accordance with one embodiment of the present invention. In this embodiment, multiplexers 2-8 are similar to multiplexer 1. Multiplexer 1 receives the 9-bit output OL[71:63] from multiplexer 11 and the 9-bit output OR[71:63] from multiplexer 12. The 9-bits of output OL[71:63] are provided from multiplexer 11 on buses 201-209, with bus 201 carrying the most significant bit and bus 209 carrying the least significant bit. The 9-bits of output OR[71:63] are provided from multiplexer 12 on buses 211-219, with bus 211 carrying the most significant bit and bus 219 carrying the-least significant bit. Multiplexers 31-39 are 10-to-1 multiplexers. Multiplexer 31 is coupled to buses 201-209 and 211. Multiplexer 32 is coupled to buses 202-209 and 211-212. Multiplexer 33 is coupled to buses 203-209 and 211-213. Multiplexer 34 is coupled to buses 204-209 and 211-214. Multiplexer 35 is coupled to buses 205-209 and 211-215. Multiplexer 36 is coupled to buses 206-209 and 211-216. Multiplexer 37 is coupled to buses 207-209 and 211-217. Multiplexer 38 is coupled to buses 208-209 and 211-218. Multiplexer 39 is coupled to buses 209 and 211-219. Each of multiplexers 31-39 receives a 4-bit control signal C[3:0] on bus 230 to select the bits of output byte OUT[71:63]. Output byte OUT[71:63] consists of 9 consecutive bits of the 18-bit concatenation of OL[71:63] and OR[71:63]. Multiplexers 2, 3, 4, 5, 6, 7 and 8 operate in a manner similar to multiplexer 1 to create outputs OUT[62:54], OUT[53:45], OUT[44:36], OUT[35:27], OUT[26:18], OUT[17:9] and OUT[8:0], respectively. Fig. 3 is a schematic diagram of a control circuit for controlling multiplexers 1, 11 and 12 in accordance with one embodiment of the present invention. In this embodiment, a 9-bit control signal, CTRL[71:63] and multiplexers 300 and 301 are used to control the operation of multiplexers 1, 11 and 12. To select bytes OL[71:63] and OR[71:63] for output, control bits CTRL[71:68] are provided to multiplexer 11. In response, multiplexer 11 passes the desired byte (i.e., OL[71:63]) from bus 131 through multiplexer 11. Control bit CTRL[63] is provided to multiplexer 301, such that multiplexer 301 passes control bits CTRL[67:64] to multiplexer 12. In response, multiplexer 12 passes the desired byte (i.e., OR[71:63]) from bus 132 through multiplexer 12. Control bit CTRL[63] is also provided to multiplexer 300. In response, multiplexer 300 passes the output of multiplexer 11 (i.e., OL[71:63]) through multiplexer 300. To select byte OUT[71:63] for output, control bits CTRL[71:68] are provided to multiplexer 11. Control bit CTRL[63] is selected such that multiplexer 301 transmits control bits CTRL[71:68] to multiplexer 12. Thus, multiplexers 11 and 12 receive the same four control bits. Because the eight bytes input to multiplexers 11 and 12 are offset by one byte, the application of the same control bits to multiplexers 11 and 12 results in the selection of consecutive bytes. Table 1 below sets forth one embodiment of the consecutive bytes which can be selected by control bits CTRL[71:68]. Control Bits CTRL[71:68] OL[71:63] From MUX 11 OR[71:63] From MUX 12 0000 IL[8:0] IR[71:63] 0001 IL[17:9] IL[8:0] 0010 IL[26:18] IL[17:9] 0011 IL[35:27] IL[26:18] 0100 IL[44:36] IL[35:27] 0101 IL[53:45] IL[44:36] 0110 IL[62:54] IL[53:45] 0111 IL[71:63] IL[62:54] The bytes passed through multiplexers 11 and 12 are provided to multiplexer 1. Multiplexer 1 receives control bits CTRL[67:64] and in response, performs the bit shifting function previously described in connection with Fig. 2. The bits passed through multiplexer 1 (i.e., OUT[71:63]) are provided to multiplexer 300. In response to control bit CTRL[63], multiplexer 300 passes the output byte OUT[71:63]. Multiplexers 2-8 and 12-26 are controlled in a manner similar to multiplexers 1, 11 and 12. In the embodiment previously described, multiplexers 2, 13 and 14 are controlled by control bits CTRL[62:54], multiplexers 3, 15 and 16 are controlled by control bits CTRL[53:45], multiplexers 4, 17 and 18 are controlled by control bits CTRL[44:36], multiplexers 5, 19 and 20 are controlled by control bits CTRL[35:27], multiplexers 6, 21 and 22 are controlled by control bits CTRL[26:18], multiplexers 7, 23 and 24 are controlled by control bits CTRL[17:9] and multiplexers 8, 25 and 26 are controlled by control bits CTRL[8:0]. Thus, multiplexers 1-8 and 11-26 are controlled by a 72-bit control signal CTRL[71:0]. Because multiplexers 1-8 and 11-26 are operated from the same control signal, the byte shifting and reordering functions performed by multiplexers 11-26 and the bit shifting function performed by multiplexers 1-8 can be executed in one clock cycle. This advantageously increases the speed of shifter circuit 100. Shifter circuit 100 also eliminates the need for separate byte shifting and reordering circuitry, thereby reducing the layout area of shifter circuit 100. In an alternate embodiment of the present invention, the control circuit is modified to allow for independent control of the bytes passed through multiplexers 11-26 during a bit shifting operation. That is, any of the bytes applied to multiplexers 11-26 (not just consecutive bytes) can be passed through multiplexers 11-26 during a bit shifting operation. The modified control circuit requires eighty bits: three bits to control each of multiplexers 11-26 and four bits to control each of multiplexers 1-8. Fig. 4 is a schematic diagram of a shifter circuit 400 in accordance with an alternate embodiment of the present invention. Because shifter circuit 400 is similar to shifter circuit 100 (Fig. 1), similar elements in shifter circuits 100 and 400 are labeled with similar numbers. Each of buses 431-446 receive all sixteen 9-bit bytes from registers 101 and 102. Hence, each of buses 431-446 is 144 bits wide and carries sixteen bytes of information. Multiplexers 41-56 are 16-to-1 multiplexers. In one embodiment, the same decoder circuitry illustrated in Fig. 3 is utilized in shifter circuit 400. For example, multiplexers 41 and 42 can be substituted for multiplexers 11 and 12 in Fig. 3. Because multiplexers 11 and 12 (Fig. 3) are controlled with four control bits CTRL[71:68], the associated control circuitry is capable of decoding up to sixteen combinations of consecutive bytes. Table 2 below sets forth one embodiment of the consecutive bytes which can be passed through multiplexers 41 and 42 in response to control bits CTRL[71:68] in shifter circuit 400. Because each of multiplexers 41-56 in shifter circuit 400 receive the same sixteen bytes from registers 101 and 102, Table 2 is applicable to each of multiplexers 41-56. Control Bits CTRL[71:68] OL[71:63] From MUX 41 OR[71:63] From MUX 42 0000 IR[17:9] IR[8:0] 0001 IR[26:18] IR[17:9] 0010 IR[35:27] IR[26:18] 0011 IR[44:36] IR[35:27] 0100 IR[53:45] IR[44:36] 0101 IR[62:54] IR[53:45] 0110 IR[71:63] IR[62:54] 0111 IL[8:0] IR[71:63] 1000 IL[17:9] IL[8:0] 1001 IL[26:18] IL[17:9] 1010 IL[35:27] IL[26:18] 1011 IL[44:36] IL[35:27] 1100 IL[53:45] IL[44:36] 1101 IL[62:54] IL[53:45] 1110 IL[71:63] IL[62:54] Like shifter circuit 100, shifter circuit 400 is capable of performing the byte shifting and reordering functions and the bit shifting function in the same clock cycle. As previously discussed, this increases the speed and reduces the layout area of shifter circuit 400. While the present invention has been described in connection with a particular embodiment, it is understood that invention is not limited to the embodiment disclosed, but is capable of various modifications which would be apparent to one of ordinary skill in the art. Thus, the present invention is limited only by the following claims. A shifter circuit and method for simultaneously and independently shifting and reordering a plurality of data bytes. The shifter circuit includes first and second registers which each receive a plurality of data bytes. The first register is coupled to a plurality of first buses, with each of the first buses receiving a data byte from the first register. Similarly, the second register is coupled to a plurality of second buses, with each of the second buses receiving a data byte from the second register. A multiplicity of third buses are coupled to the first and second buses. A byte shifting multiplexer is_coupled to each of the third buses. A plurality of bit shifting multiplexer are coupled to the byte shifting multiplexers, with each bit shifting multiplexer being coupled to a pair of byte shifting multiplexers. A control circuit is coupled to the byte shifting and bit shifting multiplexers. The control circuit provides for independent control of each of the byte shifting multiplexers. The control circuit also provides for independent control of each of the bit shifting multiplexers.

Claims: A shifter circuit (100) comprising: a plurality of first buses (111-118), each carrying a data byte; a plurality of second buses (121-128), each carrying a data byte; a first multiplexer (11) coupled to each of said first buses (111-118), for receiving data therefrom; a second multiplexer (26) coupled to each of said second buses (121-128), for receiving data therefrom; a multiplicity of intermediate multiplexers (12-25), each coupled to at least one of said first buses (112-118) for receiving data therefrom and at least one of said second buses (121-127), for receiving data therefrom; and a control circuit coupled to said first (11), second (26) and intermediate multiplexers (12-25), wherein said control circuit independently controls each of said first (11), second (26) and intermediate (12-25) multiplexers to selectively reorder the data bytes carried by said first and second buses. The shifter circuit of claim 1, wherein there are N first buses (111-118), N second buses (11-128) and (2xN)-2 intermediate multiplexers (12-26), N being an integer greater than one. The shifter of claim 2, wherein N is equal to eight. The shifter of claim 3, wherein said intermediate multiplexers comprise: third (12) and fourth (13) multiplexers, each coupled to one (121) of said second buses (121-128) and seven (112-118) of said first buses (111-118); fifth (14) and sixth (15) multiplexers, each coupled to two (121-122) of said second buses (121-128) and six (113-118) of said first buses (111-118); seventh (16) and eight (17) multiplexers, each coupled to three (121-123) of said second buses (121-128) and five (114-118) of said first buses (111-118); ninth (18) and tenth (19) multiplexers, each coupled to four (121-124) of said second buses (121-128) and four (115-118) of said first buses (111-118); eleventh (20) and twelfth (21) multiplexers, each coupled to five (121-125) of said second buses (121-128) and three (116-118) of said first buses (111-118); thirteenth (22) and fourteenth (23) multiplexers, each coupled to six (121-126) of said second buses (121-128) and two (117-118) of said first buses (111-118); and fifteenth (24) and sixteenth (25) multiplexers, each coupled to seven (121-127) of said second buses (121-128) and one (118) of said first buses (111-118). The shifter circuit of claim 1, wherein each of the data bytes includes a plurality of bits, the shifter circuit further comprising a plurality of bit shifting multiplexers coupled to said first, second and intermediate multiplexers and to said control circuitry, wherein each of said bit shifting multiplexers is independently controlled by said control circuitry to selectively pass a plurality of adjacent bits form said first and second registers. The shifter circuit of claim 5, wherein each of said bit shifting multiplexers is coupled to two of said first, second and intermediate multiplexers. The shifter circuit of claim 1, wherein said control circuit reorders and shifts data bytes carried by the first and second buses (111-118) during a clock cycle. A method for reordering data bytes comprising the steps of: applying a first plurality of ordered data bytes (111-118) to a first byte shifting multiplexer (11); applying a second plurality of ordered data bytes (121-128) to a second byte shifting multiplexer (26); applying at least one of the first plurality of ordered data bytes (111-118) and at least one of the second plurality of ordered data bytes (121-128) to each of a multiplicity of intermediate byte shifting multiplexers (12-25); arranging the first (11), intermediate (12-25) and second (26) byte shifting multiplexers to have a particular order; passing a first data byte through the first byte shifting multiplexer (11), said first data byte selected from the data bytes (111-118) applied to the first byte shifting multiplexer (11); passing a second data byte through the second byte shifting multiplexer (26), said second data byte selected from the data bytes (121-128) applied to the second byte shifting multiplexer (26); passing a third data byte through an intermediate byte shifting multiplexer (12-25), said third data byte selected from the data bytes applied to said intermediate byte shifting multiplexer (12-25), wherein at the end of the passing steps, the data bytes (111-118; 121-128) passed through said first multiplexer (11), said second multiplexer (26) and said intermediate multiplexer (12-25) are reordered. The method of claim 8, wherein the step of passing a data byte (112-118; 122-128) trough an intermediate multiplexer (12-25) further comprises a step of passing a data byte (112-118; 122-128) through each of the intermediate byte shifting multiplexers (12-25), further comprises the step of passing a data byte (112-118; 122-128) through each of the intermediate bytes shifting multiplexers (12-25) passes a data byte (111-118; 121-128) selected from the data bytes (112-118; 122-128) applied thereto. The method of claim 9, wherein each data byte (111-118, 121-128) includes a plurality of data bytes, further comprising the steps of: passing adjacent pairs of the ordered data bytes (111-118; 121-128) through corresponding adjacent pairs of the ordered first (11) intermediate (12-25) and second (26) byte shifting multiplexers; passing each of the adjacent pairs of the ordered data bytes to a corresponding bit shifting multiplexer (1-8); and passing a data byte (111-118; 121-128) through each of the bit shifting multiplexers (1-8), wherein the data byte passed through each bit shifting multiplexer (1-8) includes a plurality of adjacent bits from the adjacent pair of data bytes (111-118; 121-128) received by the bit shifting multiplexer (1-8). The method of claim 8, wherein at the end of the passing steps, the data bytes (111-118, 121-128) passed through said first multiplexer (11), said second multiplexer (26) and said intermediate multiplexer (12-25) are reordered and shifted.

Inventors: PURCELL STEPHEN C, PURCELL, STEPHEN C.
Applicants: ATI INT SRL, ATI INTERNATIONAL SRL
Application year: 1995
Main classification: G06F5
IPC codes: H03K19, G06F7