Analog memory for storing a QCIF image or the like as electric charge

Abstract: The speed of a capacitive cell RAAM used for storing an optical image as electric charge is greatly enhanced by presampling the serial analog input signal on two rows or lines of presampling capacitors, each composed of the same number of capacitors as the number of columns of the capacitive cell RAAM and by "writing" in a parallel mode the selected row of said memory. The values stored in the capacitors of one of said two presampling rows are transferred (written) in the corresponding cells of the selected row of the memory while presampling continues on the other row of presampling capacitors.

Description: The present invention relates to a storing analog device (buffer) for fast analog signal frames. The device is particularly suitable for early vision processing in neuronal networks, as an intelligent sensor for the transmission of images on ISDN networks, in intelligent motion sensors and in other alike systems. A novel and important frontier in the development of analog signal processing systems consists in realizing high density algorithms that do not require high precision; this with an aim of using analog circuits rather than digital circuits for improving performances. A possible application of this technique is the use of analog circuits for solving computational requirements of an intelligent visual sensing device ( early vision processing), in order to realize, for example, an intelligent motion sensor. An appropriate solution of the technical and technological problems of such systems would allow to integrate on the same chip both the photosensor and the processing circuit required to fulfill the most compelling requirements of miniaturization of such structures. An important function of the implemented algorithms is the estimate of the motion vectors. This type of processing requires a high computational parallelism that, if realized by exclusively employing digital circuits, would require a remarkable area of integration. Typically the algorithm that estimates the motion vectors requires the realization of four fundamental blocks: an array of photodiodes, a computational array for estimating the motion and two memories for realizing a raster or frame of the current image and of the preceding image, respectively. Due to the fact that the computational array requires an analog input signal, the use of conventional digital memories requires a digital-analog converter. Instead, by employing an analog memory, the analog signal to be supplied to the computational array would be directly available from the memory. The article entitled "Random Access Analog Memory for Early Vision" by Eleonora Franchi, Marco Tartagni, Roberto Guerrieri and Giorgio Baccarani (University of Bologna), published on the IEEE Journal Solid-State Circuits, Vol. 37, No. 7, July 1992, describes the realization of an analog memory realized according to the CMOS technology with a line width of 1.6 micrometers and constituted by 176x144 capacitive cells. The analog memory (RAAM) used has a charge retention time sufficiently long to satisfy the minimum requirement of retention of 1/30 th of a second for each frame. During this retention period, the memory can be read several times without destroying the information, according to the requirements of the computational algorithm. The writing of the cells takes place by activating all the cells of one line of the array at the same time, while the columns of the array are activated sequentially in accordance with the arrangement of the input data that are usually supplied by a line by line scanning system of an image. The document EP-A-0 317 236 discloses an analog memory composed of an array of capacitive cells, organized in rows and columns, individually writable and readable in a nondestructive way wherein a first presampling capacitor is associated to each column of the array such to constitute a row of presampling capacitors. Configuration means permit to store instantaneous values of analog input signal. In well known capacitive cells analog memories (RAAM), the writing of data in the memory occurs in a sequential mode. The analog input is serial and is stored in the selected capacitive cell of the memory array each time said analog serial signal is present at the input. This situation limits the writing speed and is also incompatible with an hypothesis of implementing a parallel transfer of data coming from a corresponding (176x144) matrix of photodiodes. According to the present invention, the performance of an analog memory of capacitive cells (RAAM) in terms of speed and energy consumption, can be remarkably improved by introducing a presampling of the input analog signal on two presampling lines or rows or arrays of capacitors, with a number of capacitors equal to the number of columns of the memory cells of the matrix, and by writing in parallel all the cells of an entire row of the memory matrix, transferring in them the charge presampled stored in the respective presampling capacitors of one of said two lines, while the input analog serial signal continues to be presampled on the other row of presampling capacitors. In practice, one row or array of presampling capacitors is used for writing even numbered rows of the memory and the other presampling row is used for writing odd numbered rows of the memory. According to another important aspect of this invention, the transfer of the charge from one presampling capacitor to the corresponding capacitive cell of the memory matrix, during a writing phase of an entire row of cells in a parallel way, is carried out by way of an integrating stage (amplifier), preferably constituted by a single branch cascode circuit, having an integrating capacitor feedback. In this way, current absorption is greatly reduced if compared to the use of a common buffer stage instead of an integrator. Of course, the memory can have a parallel output of eight or more channels. According to the invention, the analog memory writing speed is limited in practice only by the time necessary for presampling an analog signal on the input presampling capacitors and therefore can be very high. In many applications, this architecture of capacitive cell analog memory, can allow a parallel transfer of data coming from a corresponding matrix of photodiodes with a further increment of the system speed. The increased speed of the storing system promotes size reduction of the device through the use of more advanced fabrication technologies, for an enhanced integrability of the entire system on a single chip. The various aspects and relative advantages of this invention will be even more evident by way of the following description of some important embodiments and reference to the attached drawings, wherein: Figure 1 is a high-level block diagram of a RAAM realized according to the invention; Figure 2 illustrates the electric scheme of a single cell of the memory matrix; Figure 3 is a layout of a single memory cell; Figure 4 is an electric diagram of the writing circuit of a memory cell according to the invention; Figures 5 and 6 partially and schematically highlight the circuit configuration of Fig. 4 during a reset phase and during a phase of integration (transfer); Figures 7 , 8 , 9 and 10 illustrate operating characteristics of a memory realized according to the present invention. In order to verify the effectiveness of the novel architecture object of the present invention, a random access analog memory with dimensions: 176 (columns) by 144 (lines), capable of managing the corresponding 176x144 pixels of an image frame in a QCIF format has been realized. By way of example, the computational algorithm used (H262) establishes as appropriate a precision of 6 bits, whereas the real time operating requirement of the system requires an ability of storing an image (frame) for a minimum retention time of 1/15 th of a second, during which each capacitive cell of the RAAM memory may be read five times. The memory was realized in CMOS technology with a line width of 0.7 micrometers. A high-level block diagram of the memory device is shown in Fig. 1. The depicted memory has a serial input and a parallel output. During a reading phase the memory provides at its output the analog values of eight adjacent cells belonging to one preselected row. Fig. 2 illustrates the electric scheme of a single memory cell. The storing capacitor, in which electric charge, for example the electric charge corresponding to the current photogenerated by a photoconductive diode of a QCIF sensor is stored, is realized in the form of an MOS capacitor structure C s . The MOS transistor M w constitutes the cell's select switch for the writing of the cell, the MOS transistor M wt constitutes a second select switch of the cell, used during both the writing and the reading phases. The switch M ef constitutes a decoupling switch of the capacitance C s during the reading phase in order to avoid destruction of the information stored in the capacitive cell C s during the repeated readings that take place within the retention interval of the current frame. Leakage currents flowing through the P + /Nwell junction of the drain region of the transistor M w degrade the information stored on C s in the form of an electric charge according to the following expression: Erv = (I leakage /C s )T storage (volts) As it can be appreciated, a high capacitance value of C s reduces this degradation mechanism. The opening of the "write" switch, that is the switching off of the MOS transistor M w causes the integration in the capacitance C s of a so-called "clockfeedthrough" electric charge whose value can vary from cell to cell, thus introducing an error in the analog value stored in the capacitance C s . Even in this case, the error can be reduced by increasing the value of the capacitance C s . Therefore, an attendant objective is that of designing a cell in such a way of maximizing the value of the capacitance C s while fulfilling the specified maximum dimensions of the cell. Fig. 3 is the layout of a RAAM memory cell. The dimensions of the unit cell are 22 micrometers by 21.2 micrometers. The darkened area represents the area of the capacitor C s . The reading of the state of charge of the capacitive cells C s occurs via the reading amplifier M ef , which is enabled by the switch M wt , in a substantially not destructive way of the information stored in the form of an electric charge in the capacitor C s . By referring to the block diagram of Fig. 1, according to the present invention, the analog input signal is presampled on two lines or rows of presampling capacitors. Each line or row being constituted by a number of presampling capacitors is equal to the number (176) of the matrix columns. Writing of the analog memory occurs by whole selected rows of cells, by transferring in a parallel way the electric charges stored in the presampling capacitors, of one of the two lines or rows, in the memory cells of the selected row of the addressable memory matrix. At the same time, the presampling of the analog input signal continues to be carried out on the other line or row of presampling capacitors, whose charge levels will be subsequently transferred in the successively selected row of memory cells of the matrix and so forth. The architecture of the writing system, according to a preferred embodiment of the invention, is shown in Fig. 4. Each column of the matrix is substantially independent from the others. In Fig. 4 only one cell of a column is depicted, but in the case considered above, there exist 144 alike cells for each column. The reading of any of the selected cells of the column is carried into effect via a unique reading amplifier, as it will be later on described with more details. Each memory cell is selected by closing the switches M w and M wt . One cell alone per column can be selected at any one time. The labels used in Fig. 4 indicate the following. n index Indicates the progressive number of the rows of the memory matrix. j index Indicates the progressive number of the columns of memory matrix. Where the index J is not present, this means that the logic signal is common for the entire memory and, if only the index n is present, this means that the logic signal is common only for all the cells of a single row of the matrix. N When shown, it indicates that the logic signal is inverted. C1 j , C2 j Indicate the presampling capacitors. Ci j Indicates an integrating capacitor. Coff j Indicates an offset compensation capacitor. SC j Indicates a column select transistor. This transistor serves for biasing the column. L wn Active when in a low logic state; it attends to the selection of a cell during a writing phase. L wm Active when in a high logic state; it attends to the selection of a cell during both a writing phase and a reading phase. The "cell input" and the "cell output" wires of the diagram of Fig. 4 represent the 176x2 wires coming from the amplifier array that is, of the array of charge integrators of the diagram of Fig. 1. The integrating stage (amplifier) used for writing the memory cells of the respective column of the matrix is constituted by a single branch cascode stage, whose is realized by an integrating capacitor Ci j . The amplifier's input is selectively driven by the electric charge stored in either one or the other presampling capacitor, C1 j , C2 j , each of which belongs respectively to one of the two lines or rows of 176 presampling capacitors of the serial analog input signal (analog input). The configuration schemes of the integrating stage, during a reset phase and during an integration phase or in other words a writing phase of a selected cell of the relative column (j) are shown in Figures 5 and 6, respectively. During a presampling phase of the analog input signal, the switches driven by the logic signals S1 j C1 for a first line or row of presampling capacitors C1 j or S1 j C2 for the other line or row of presampling capacitors C2 j , are sequentially opened or closed at every clock front. This operation continues until sequentially storing the relative instantaneous values of the analog input signal on all the presampling capacitors of an entire line or row. While the presampling of the analog input signal continues in a similar way on the second line or row of presampling capacitors, the values stored in the presampling capacitors of the first line are "written" in a parallel mode in the capacitive memory cells of a selected row of the memory matrix. The capacitors C1 j are used for writing on odd numbered rows of the memory matrix, whereas the presampling capacitors C2 j are used for writing on even numbered rows of the memory. In the considered example, presampling of a signal on an entire presampling line or row requires 176 clock cycles and an interval of four clock cycles before the presampling is resumed on the other line or row of presampling capacitors. If we consider a sampling clock frequency of the analog input signal equal to 2.5MHz, the "writing" amplifier associated with each column of the memory matrix has at its disposal 72µs for executing the writing of the cell of the corresponding selected memory row. As it can be observed, from this information, the speed performance of the "write" amplifier (integrator) does not constitute a particularly critical parameter. The input writing speed may even be increased well beyond 2.5MHz because it is exclusively limited by the time required by the signal presampling on the capacitors of one presampling line. An integrating stage (charge amplifier) may be used as the "write" amplifier for each column of the memory matrix. The feedback integrating capacitor of the charge amplifier Ci j may have the same value of the presampling capacitors, C1 j and C2 j , which alternatively drive the amplifier input so as to make the gain of the stage equal to one. The use of an integrating stage rather than a unit gain buffer provides for a remarkable reduction of current consumption. In particular, in the case of the example shown, where the integrating stage is composed of a single branch cascode circuit, each cascode may be biased with a current of 1 µA. WRITING The analog signal that corresponds to the scanning of a row of a photodiode optic sensor is stored on the presampling capacitors C1 j (or C2 j ) by closing S1 j C1 (or S2 j C2). The analog value pertaining to the scanning of the successive row of photodiodes will be stored on the capacitors C2 j (or C1 j ) of the other presampling row, As it can be noted from the diagrams of Figures 5 and 6, during a reset phase the initial conditions of the charge amplifiers (integrators) are reestablished while during an integration phase the presampled signal stored on an input capacitor C1 j is transferred (written) in the respective capacitive cell of the selected row of the memory matrix. During the integration phase, supposing that the value Vin of the input analog signal was previously presampled on the capacitor C1 j , the logic signals S2C1, S2, SC j (where 1 ≤ J ≤ 176) and L wm assume a high logic value, while the signal L wn assumes a low logic value. In this situation and taking into account a starting condition whereby the node "A" of Fig. 4 is preloaded with a Vref1 voltage (4 volts) and the node "B" with a Vref2 voltage (1 volt), the integrating capacitor Ci j charges to a voltage given by the difference between the Vref1 and Vref2 voltages, that is up to about 3 volts. The writing starts when the switches S2C1, S2, SC j , L wr and L w are closed and the switch S2N is opened. The loop closes and the node "A" assumes a low impedance. An electric charge whose value is equivalent to (Vref1-Vint)•C1 j flows in the integration capacitors CI j . At the end of the writing phase the capacitor C1 j charges itself up to the Vref1 voltage and the output voltage Vout assumes the following value: Vout = (Vref1 + Vref2 - Vin) In this way, even if there were some threshold differences amongst the different MOS transistors M ef , they would be in any case compensated by the feedback loop. Indeed, a charge information (Vout) equal to the result of the aforementioned equation incremented by the value of the gate/source voltage Vgs of the transistor M ef on Cs is stored. The reading of the stored information is carried out by biasing the respective column with a current identical to that used in the writing phase, therefore on the source node of M ef the above indicated equation remains verified. According to preestablished conditions, the integration phase has 51.2µs at its disposal for reaching completion. During a reset phase, the above mentioned digital signals are inverted, the loop of the integrating stage opens and the information is retained in the capacitive cell C s in the form of an electric charge. On the contrary, the integrating capacitor Ci j and the presampling capacitor C1 j are reset to the initial state of charge. READING Reading may be carried out by stimulating eight adjacent columns (8 adjacent switches SC j being closed) and by selecting one row (high L wm ). By referring again to the diagram of Fig. 4, when a reading is being performed, the respective row SC j and the respective line L wm are in a high logic state, the j column is biased and the bias current flows through the reading amplifier constituted by the M ef transistor. The analog value stored in the selected capacitive cell, less the emitter/gate voltage of the M ef transistor, is reproduced on the cell output node. This analog value can be readily made available externally through a normal analog buffer, capable of driving a relatively high (30 pf) capacitive load. The output node (cell output) may normally be charge by a parasitic capacitance of about 1pF. It is possible that during the reading of a cell, the output be precharged to a higher value than that of the selected cell. As a consequence, the current that was supposed to bias M ef is instead used for discharging the output. In case the difference between the voltage relative to the information stored in the selected cell and the precharge value is rather large, an excessive reading delay may result. This drawback may be overcome by discharging the output node prior to each reading by means of an appropriate reset switch. In this way, the current necessary to charge the parasitic capacitance of the output node will be supplied by M ef with the resulting effect of increasing the reading speed. In the example considered, the I/O characteristic of the memory is substantially linear within an output dynamic range comprised between 1 and 3 volts. This corresponds to an input dynamic range comprised approximately between 2 to 4 volts. Fig. 7 shows the I/O characteristic of the memory. The data shown in the diagram of Fig. 5 refer to the average value calculated by taking into account all the memory cells. There exists a difference between the theoretical characteristic and the measured one. This is due to the phenomenon known with the name of "chargefeedthrough" that occurs during opening and closing of the cell select switches M w . Moreover, offset and gain errors are introduced but these do not constitute a problem in view of the computational algorithm used. Fig. 8 shows the I/O characteristics of the memory when writing the same analog input value on all the memory cells and thereafter reading all the cells. The output value was determined by calculating the average of all the readings. By referring to the described embodiment, another important verification carried out was that of determining the effect of the temperature on the leakage current through the drain and source (P + -Nwell) junction of the M w switch. This effect is shown in the diagram of Fig. 9 and can be evaluated in terms of a voltage error of less than 6mV for a temperature that remains lower than 65°C. In terms of voltage, the error introduced by the leakage current after a retention period of 66ms at a temperature of 27°C is less than 1mV and thus may be considered substantially negligible. The output dynamic range is another parameter of importance. This is determined by writing the same analog value in all the memory cells and by reading the output value considering the cells as belonging to different windows, each of 16x16 pixels. In the sample realization of the memory of this invention a precision of 7 bits has been detected. The detected data are diagrammatically shown in Fig. 10.

Claims: An analog memory comprising an array (Cell Array) of capacitive cells (Mw, Cs, Mef, Mwr), organized in rows (n) and columns (i), individually writable and readable in a nondestructive way of the stored information, characterized in that it comprises a pair of presampling capacitors (C1j, C2j) associated to each column of said array, first capacitors (C1j) of said pairs constituting a first presampling row and second capacitors (C2j) of said pairs constituting a second presampling row; configuration means (S1jC1N, S1jC1, S1jC2N, S1jC2, S2C1N, S2C1, S2C2N, S2C2) for storing instantaneous values of an analog input signal at successive presampling instants on the capacitors of one of said rows of presampling capacitors (C1j,C2j) during the time interval in which presampled values stored in the capacitors of the other presampling row (C2j, C1j) are written in a parallel mode in the corresponding cells (Mw, Cs, Mef, Mwr) of a selected row of said memory array. The analog memory according to claim 1, characterized in that it comprises a resettable charge integrating stage having an output coupled to a respective column of said array, constituted by a differential amplifier feedback by an integrating capacitor (CIj) and whose input is selectively driven by the charge stored either in one or the other capacitor (C1j) of a respective pair of presampling capacitors (C1j, C2j), during a writing phase of a cell of said array. The analog memory according to claim 2, characterized in that said charge integrating stage comprises a one branch cascode circuit. The analog memory according to claim 2, characterized in that said integrating capacitor (CIj) has the same capacitance of said presampling capacitors (C1j, C2j). A method of writing in a parallel mode a capacitive cell analog memory, organized in rows and columns, characterized in that comprises the following steps: presampling an analog input signal on two rows of presampling capacitors (C1, C2) each composed of the same number of capacitors of the columns of said array; writing each row of said array in a parallel mode, by transferring in the respective capacitive cells of the row the electric charge stored in corresponding presampling capacitors of one of said two rows (C1j, C2j) while the input signal continues to be presampled on the other row of capacitors. The method according to claim 1, characterized in that the writing in a parallel mode of each capacitive cell of one row is performed by means of a single branch cascode integrating stage, feedback by an integrating capacitor (CIj), associated to each column (j) of said array and selectively driven by the electric charge stored in the presampling capacitors (C1j, C2j) of said two rows. An optical sensor device comprising an array of photodiodes arranged in rows and columns and individually addressable during a scan reading of the current photogenerated in each photodiode (pixel) and at least a storing analog memory of a scanned image comprising an array of capacitive cells, arranged in rows and columns, and individually writable and readable in a nondestructive way, characterized in that said array of photodiodes and said array of capacitive cells of said analog memory have an identical arrangement in the number of rows and columns, said analog memory comprising a pair of presampling capacitors associated to each column of said array, first capacitors of said pairs constituting a first presampling row and second capacitors of said pairs constituting a second presampling row; configuration means for storing instantaneous values of an analog input signal, at successive presampling instants, on the capacitors of one of said rows of presampling capacitors during an interval of time in which presampled values stored in the capacitors of the other presampling row are written in the respective cells of one selected row of said memory array; the succession of detected analog values at the completion of the scanning of one line of said array of photodiodes being stored in one of said two rows of presampling capacitors and written in a parallel mode in a corresponding row of said analog memory during the scanning and the presampling of the analog values relative to a successive row of said array of photodiodes in the other row of said presampling capacitors.

Inventors: GERNA DANILO, MARCHESE STEFANO, PASOTTI MARCO, GERNA, DANILO, MARCHESE, STEFANO, PASOTTI, MARCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: G11C27
IPC codes: G11C27