PROGRAMMABLE CONTROL STORE FOR SYNCHRONOUS SYSTEM TIMING AND CONTROL

Abstract: A control store provides device control signals to a device controller. The device controller controls each selected operations of a device connected thereto. The control store comprises a programmable front end logic for generating a first plurality of operations control signal in response to a requested operation. Each operation control signal defines a type of control cycle desired to be performed by the device. A control store block stores a second plurality of information. The second plurality of information defines a predetermined condition of each of the device control signals in a timed sequence of a selected control cycle such that the device performs the requested operation. Both the programmable front end logic and the control store block are programmable permitting modifications to the control store to be made easily.

Description: PROGRAMMABLE CONTROL STORE FOR SYNCHRONOUS SYSTEM TIMING AND CONTROL BACKGROUND OF THE INVENTION The present invention relates to a controller, and more particularly, to a programmable control store associated with a micro processor (MP) for providing control signals utilized in the control of a memory unit coupled to the micro processor. Presently, control stores and the logic associated with the control stores are essentially fixed. Thus, changes generally are accomplished by a "re-wire". It is desirable to have the control store and the associated logic to be more flexible (i.e., programmable), and in addition helps reduce the debug effort. Further, once the wiring is fixed in a gate array, changes require generating a new mask thereby making changes very difficult, costly, and time consuming. Thus there is a need to have a control store and the associated logic which is more programmable which results in a more flexible system and reduces the fixed logic of the current systems. SUMMARY OF THE INVENTION Therefore, there is provided by the present invention a programmable control store for synchronous system timing and control. A control store provides device control signals to a device controller. The device controller controls each selected operations of a device connected thereto. The control store comprises a programmable front end logic for generating a first plurality of operations control signal in response to a requested operation. Each operation control signal defines a type of control cycle desired to be performed by the device. A control store block stores a second plurality of information. The second plurality of information defines a predetermined condition of each of the device control signals in a timed sequence of a selected control cycle such that the device performs the requested operation. Both the programmable front end logic and the control store block are programmable permitting modifications to the control store to be made easily. Accordingly, it is an object of the present invention to provide a programmable control store. It is another object of the present invention to provide a programmable control store and associated logic. It is still another object of the present invention to provide a programmable control store and associated logic for synchronous system timing and control. These and other objects of the present invention will become more apparent when taken in conjunction with the following description and attached drawings, wherein like characters indicate like parts, and which drawings form a part of the present application. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a block diagram of a microprocessor operatively connected to a memory unit in accordance with the preferred embodiment of the present invention; Figure 2 shows a block diagram of a control store function of the preferred embodiment of the present invention; Figure 3 shows an organization of the control store of the preferred embodiment of the present invention; Figure 4 shows a logic diagram for selecting the control store address; and Figure 5 shows a partial block diagram of the front end logic. DETAILED DESCRIPTION Referring to Figure 1, there is shown a micro processor 10 and a memory unit 12 in the preferred embodiment the micro processor being a Motorola 68000 family micro processor and the memory unit being a random access memory (RAM). Data to be transferred to/from the memory unit 12 is performed in conjunction with the address lines (20 lines in the preferred embodiment), and in conjunction with the data lines and the various control signals, such as read enable, transfer start,... required to accomplish the transfer. Although the memory unit 12 is shown as a single block, the memory unit 12 includes some control logic which performs the function of a memory controller (not shown) and the actual storage device array (not shown). The present invention relates to the memory controller, some times denoted herein as a control store function. Referring to Figure 2, there is shown a block diagram of the control store function of the preferred embodiment of the present invention. The control store function consists of two parts. The first is a programmable logic block, the preferred embodiment of the present invention having eight programmable logic blocks 20-1,..., 20-8, sometimes referred to herein as a front end. Each of the eight blocks is programmed to output a true state when a predetermined number inputs are in the desired state, the input logic levels of the desired inputs being programmable. The output of each of the logic blocks 20-1, ..., 20- 8 is coupled to an 8:3 encoder 30. The encoder outputs a three bit number which is a binary representation of which of the inputs of the programmable logic blocks 1-8 is true. In the preferred embodiment if two inputs to the encoder 30 are true, the encoder performs a priority encoder function with the higher numbers having the priority. (It will be recognized by those skilled in the art that a "non-priority" encoder can be utilized if the inputs are such that at most only one input to the encoder can be true.) The encoder of the preferred embodiment also has an "all zero" state output which indicates none of the inputs of the respective programmable logic blocks is true. The output of the encoder defines the type of memory control cycle to be performed. A partial list of memory control cycles of the preferred embodiment of the present invention is shown in Table 1. Valid Encoder Outputs (digital) 0 Read Burst 1 Read 2 Write 3 Read Modify Write 4 Refresh 5 6 7 TABLE 1 The output of the encoder 30 also indicates a starting address for a selected control store sequence. As indicated above the encoder 30 outputs an address of zero when there is no valid output from any of the eight programmable logic blocks 20-1 through 20-8. The control store (40) utilizes a control store address of zero as the rest state address. When there is a valid output from the encoder 30, the encoder outputs the lower three bits of the control storage address as a result of which input is valid. These 3 lower bits in combination with 3 upper bits make up the address of the control store 40. In the preferred embodiment, the all zero output of the encoder then changes state and the new state causes the upper bits of the control storage address to be forced to a preselected logic level, such that the upper eight locations in the control store 40 are the starting locations of the control store 40. Referring to Figure 3, there is shown an organization of the control store 40 of the preferred embodiment of the present invention. The address 40 through 47 correspond to the test bit cycle, to the first state of the read cycle, the first state of the write cycle, the first state of the read modify write cycle..., respectively (consistent with the encoder output as shown in Table 1). Location 40 corresponds to the output of the eighth front end (i.e., front end 20-8) and a valid output of the encoder 30, causing the output of the MUX 45 to indicate address 40 as will be discussed hereinunder. The writable control store 40 forms the second part of the memory controller of the present invention. Control store block 40 is essentially a RAM having 48 addresses and a register 42. Interposed between the control store block 40 and the encoder 30 is a multiplexer (MUX) 45. The address of the control store block 40 is then selectable from multiple sources, the first source being the output of the encoder 30 and the second source is from the next address field from latch 42. Referring to Figure 4, there is shown the logic by which the address of the control store block 40 is chosen. The encoder 30 includes the eight inputs from the Front End units 20-1 through 20-8. Three (3) output lines are provided which encodes the input in a binary form as indicated in Table 2. Also provided by encoder 30 is an AND-gate 31 which provides a valid/invalid signal. When all the inputs are zero, the invalid signal is generated and coupled to AND-gates 32, 33, 34 such that the address zero (0) of control store block 40 is chosen which defines a REST state. Front End Output Encoder Output (Bit) 1 2 3 4 5 6 7 8 0 1 2 Valid/Not Valid 0000 0000 000 0(NotValid) 1000 0000 001 1 (Valid) 0100 0000 010 0010 0000 011 0001 0000 100 0000 1000 101 0000 0100 110 0000 0010 111 0000 0001 000 TABLE 2 The output data of the control store block 40 contains several fields including the state fields and the next address field. The state fields indicates the states of the various control signals required of the memory unit and include a write enable (WE), row address strobe (RAS), column address strobe output enable (OE), (CAS),.... The next address field indicates the next address in the control store block 40 which contains the next state configuration (state 2) of the various control signals, WE, OE, CAS, RAS,.... That word in the control store block contains information relating to the control signals of state 2 and the next address field points to the word defining the control signals for state 3, and so on, until the memory operation is completed. The last state utilizes the next address of zero, causing the MUX 45 to switch back to the "A" inputs (from encoder 30) looking at a new starting address from the encoder. If the inputs to the front end have changed yielding a non valid state, the encoder will be outputting zero for the starting address, and the system is back to the stable "rest state". If the inputs are indicating a new valid state, a non-zero starting address is selected and a new cycle begins again. The control signals from the state field are operatively coupled to the devices such as the memory unit 12 (and in particular to the memory controller not shown) of the present invention. Referring to Figure 5, there is shown a partial block diagram of the front end 20- 1 , which is a programmable logic array (or sometimes referred to as programmable and or logic), all eight (8) of the front ends 1-8, 20-1 through 20-8, being the same. However, each front end is programmed differently to indicate a redetermined control memory cycle. Generally, a processor initiates an I/O (input/output operation) in response to the program being executed, such as a read from memory operation. Associated with the I/O command is an external function code indicating a read of memory along with other information including the address to be read, ... which is then executed by some I/O logic (of the processor, IOP, or...). The decode (by the processor, IOP) initiates a TS (transfer start) control signal. The TS signal, along with additional logic of the processor which decodes the function code, causes a control signal such as a read cycle to be generated. The front end 20-1 includes D-type F/F 21, 22 which are latched in a predetermined state to select the event (read cycle, write cycle,...). Thus, F/F 21 is latched to enable NAND-gate 23 such that the read cycle signal will be selected when generated by the processor 10, the read cycle signal being inputted to the encoder 30. The F/F 22 is programmed such that the write cycle signal is disabled, i.e., is inhibited and not outputted from NAND-gate 24. Also, according to Table 1, front end 2, 20-2, has its F/F 26 programmed to enable NAND-gate 28 such that when the write cycle signal is generated by the μp 10, input 2 to the encoder 30 has the write cycle control signal generated (i.e., the output of AND-gate 29). F/F 25 disables the read cycle signal inputted by μp 10 to Front End 2, 20-2. Each of the front ends 1-8 are programmed utilizing a μp data bus during a startup of the μp 10 in conjunction with a latch enable (LE) control signal and an address defining the F/F from the μp, and remain in the programmed configuration during the execution of any programs within the μp 10. The control store block 40 is programmed at startup in a similar manner well known to those skilled in the art. The specific programming of each of the front ends 1-8, 20-1 through 20-8, varies according to the μp and the PLA (programmable logic arrays) utilized, and is well known to those skilled in the art. In the preferred embodiment of the present invention only one output generally occurs from each of the front ends at a given time. However, as has been mentioned above, should two (2) outputs occur, the encoder of the preferred embodiment is a priority encoder, thereby selecting an input with a higher priority. If the outputs of the front ends are such that only one output will be generated at a particular time, a encoder of a non priority type can be utilized. In an alternative embodiment, another field of the information from the control store block 40 can include a dwell count. These bits in combination with some control logic allow the control store block 40 to dwell at the current address for a predetermined number of system clock cycles indicated by the dwell count. The dwell can be enabled or disabled based on the state of two input signals, and can also be enabled by another bit in the dwell field which activates the dwell control logic irrespective of the state of the two input signals. Although there has been described a control store for a memory unit in the preferred embodiment of the present invention, it will be recognized by those skilled in the art that the control store can be applied to any device controller, including print controller, disk controller,... the control store block and front end being programmed to generate the desired control signals. While there has been shown what is considered the preferred embodiment of the present invention, it will be manifest that many changes and modifications can be made therein without departing from the essential spirit and scope of the invention. It is intended, therefore, in the annexed claims to cover all such changes and modifications which fall within the true scope of the invention.

Claims: CLAIMS Claim 1. A control store for providing device control signals to a device controller, the device controller controlling each selected operation of the device connected thereto, the control store comprising: a) a programmable front end logic for generating a first plurality of operations control signal in response to a requested operation, each operation control signal defining a type of control cycle desired to be performed by he device; and b) a control store block, operative connected to the programmable front end logic, for storing a second plurality of information, the second plurality of information defining a predetermined condition of each of the device control signals in a timed sequence of a selected control cycle such that the device performs the requested operation. Claim 2. A control store according to Claim 1 , wherein the control store block comprises: a) storage unit, having a plurality of addressable locations, each addressable location containing a next address field and the predetermined condition of each of the device control signals for a predetermined time interval of the timed sequence, the next address field pointing to the next addressable location such that the condition of the device control signals conform to a desired time sequence to perform a predefined operation; and b) latch, for holding the information read from the addressable location to couple the condition of the device control signal to the device controller during the time interval, the time interval being defined by a predetermined clock time. Claim 3. A control store according to Claim 2 wherein the control store block further comprises: a multiplexer for providing an address to the storage unit, the address being selectable from the next address field of the latch or from the programmable front end logic in response to a select control signal. Claim 4. A control store according to Claim 3, wherein the programmable front end logic comprises: a plurality of programmable and/or logic arrays, each programmable and/or logic array being programmed to output the type of control cycle to be performed by the device in response to a predetermined plurality of operation codes inputted to the plurality of programmable and/or logic arrays. Claim 5. A control store according to Claim 4, wherein the programmable front end logic further comprises: an encoder for encoding a plurality of type of control cycle signals outputted from the programmable front end logic into a binary representation of type of control cycle signals being operatively connected the multiplexer to define a starting address of the storage unit, the starting address defining a first condition of the device control signals of the request operation. Claim 6. A control store according to Claim 5, wherein the storage unit of the control store block is programmable. Claim 7. A control store according to Claim 6, wherein the plurality of programmable and/or logic arrays of the programmable front end logic is programmable. Claim 8. A control store according to Claim 7, wherein the device is a memory storage unit. Claim 9. A control store according to Claim 8, wherein the device controller is a memory controller.

Inventors: GUSTIN JAY W, GUSTIN, JAY, W.
Applicants: HONEYWELL INC, HONEYWELL INC.
Application year: 1995
Main classification: G06F9
IPC codes: G06F9