Digital coding/decoding apparatus using variable length codes

Abstract: In a digital coding apparatus or a digital coding and decoding apparatus for image data compression and expansion by means of Huffman coding, a Huffman coding circuit converts a combination of ZERO RUN and VALUE into a variable-length code. A code length calculation circuit has an AC code length table for prestoring variable-length codes and their code lengths in corresponding relationship. The code length calculation circuit inputs not a ZERORUN-VALUE combination but a variable-length code from the Huffman coding circuit, thereby calculating from the variable-length code inputted its code length according to the AC code length table.

Description: This invention relates generally to a digital coding apparatus and to a digital coding/decoding apparatus. More specifically the present invention pertains to a technique of reducing the size of logical tables for use by these apparatus. Japanese Patent Application, published under Pub. No. 6-165112, shows a digital coding/decoding apparatus for image data compression and expansion. FIGURE 10 shows a conventional digital coding/decoding apparatus. 14 is a discrete cosine transform circuit (DCT). 15 is a quantizer. 16 is a variable-length coder (VLC). 17 is an inverse discrete cosine transform circuit (IDCT). 18 is an inverse quantizer. 19 is a variable-length decoder (VLD). 20 is a circuit made up of the VLC 16 and the VLD 19 . The DCT 14 receives either an image data luminance signal or an image data chrominance signal and performs a discrete cosine transform on the received signal, a result of the discrete cosine transform operation being put out in the form of an AC coefficient. The quantizer 15 quantizes an output of the DCT 14 , a result of the quantization operation being put out. The VLC 16 transforms an output of the quantizer 15 into a variable-length Huffman code for further data compression. This variable-length AC code is padded to a fixed-length code. This fixed-length code is put out to a recording device (not shown) located outside the apparatus. The VLD 19 receives a fixed-length AC code (i.e., a Huffman code) from a recording device (not shown in the figure) located outside the apparatus, extracts a variable-length AC code from the received fixed-length AC code, and decodes and expands the variable-length Huffman code to put out an AC coefficient. The inverse quantizer 18 inverse-quantizes an output of the VLD 19, a result of the inverse-quantization operation being put out. The IDCT 17 performs an inverse discrete cosine transform on an output of the inverse quantizer 18 , to obtain either an image data luminance signal or an image data chrominance signal. Such an obtained signal is fed to an image display unit (e.g., a CRT) located outside the apparatus. FIGURE 7 schematically shows a circuit organization of the VLC 16 of FIGURE 10. 1 is a decision circuit. 2 is a run length counter. 3 is an AC code table. 4 is a two-dimensional Huffman coding circuit. 7 is a padding circuit. 12 is a code length calculation circuit. 13 is an AC code length table. As shown in FIGURE 11 , the decision circuit 1 receives a sequence of AC coefficients each of which has either a value of zero (zero value) or a value other than zero (nonzero value). Upon receipt of an AC coefficient the decision circuit 1 determines whether the AC coefficient received has a zero value or a nonzero value. The run length counter 2 counts the number of times the decision circuit 1 successively receives a zero-valued AC coefficient (i.e., the number of consecutive AC coefficients that are all determined by the run length counter 2 having a zero value). Whereas a nonzero-valued AC coefficient is defined as VALUE, the number of consecutive zero-valued AC coefficients is defined as ZERO RUN (ZERORUN). ZERORUN and VALUE combinations are shown in FIGURE 11 . The AC code table 3 prestores ZERORUN-VALUE combinations and variable-length AC codes in corresponding relationship. Additionally the AC code length table 13 prestores the ZERORUN-VALUE combinations and code lengths of the variable-length AC codes in corresponding relationship. Each ZERORUN-VALUE combination is fed to the two-dimensional Huffman coding circuit 4 and to the code length calculation circuit 12 . Based on the AC code table 3 , the Huffman coding circuit 4 puts out a variable-length AC code corresponding to the ZERORUN-VALUE combination received. Based on the AC code length table 13 , the code length calculation circuit 12 puts out a code length of a variable-length AC code corresponding to the ZERORUN-VALUE combination received. The padding circuit 7 receives the variable-length AC code from the two-dimensional Huffman coding circuit 4 and the code length from the code length calculation circuit 12. Then the padding circuit 7 pads these data items, received from the Huffman coding circuit 4 and the calculation circuit 12 , to a fixed-length AC code (see FIGURE 12 ). FIGURE 12 depicts an example of padding thirteen variable-length AC codes A to M into three fixed-length codes. A part of the variable-length AC code E, i.e., E1, is padded to the first of the three fixed-length codes, and the remaining part of the variable-length AC code E, i.e., E2, is padded to the head end of the second of the three fixed-length codes. FIGURE 8 illustrates a circuit organization of the VLD 19. 5 is a code length calculation circuit. 6 is an AC code length table. 9 is a two-dimensional Huffman decoding circuit. 10 is an extraction circuit. 11 is an inverse AC code table. When the VLD 19 receives a fixed-length code, the code length calculation circuit 5 finds from the fixed-length AC code a code length of a variable-length AC code contained in the fixed-length AC code, according to the AC code length table 6 . The extraction circuit 10 receives a fixed-length AC code and the code length found by the code length calculation circuit 5 and extracts a variable-length AC code from the fixed-length code. Based on the inverse AC code table 11 , the two-dimensional Huffman decoding circuit 9 transforms the extracted variable-length AC code into a ZERORUN-VALUE combination. FIGURE 9 is a list of different types of logical tables for use by the VLC 16 and the VLD 19 of FIGURE 10 , namely a variable-length-code encode table T1, a code length table T2, a code length table T3, and a variable-length-code decode table T4. TABLE T1, which corresponds to the AC code table 3 , takes in a ZERORUN-VALUE combination and puts out a variable-length code. TABLE T2, which corresponds to the AC code length table 13, takes in a ZERORUN-VALUE combination and puts out a code length. TABLE T3, which corresponds to the AC code length table 6 , takes in a variable-length code and puts out a code length thereof. TABLE T4, which corresponds to the inverse AC code table 11 , takes in a variable-length code and puts out a ZERORUN-VALUE combination. The above-described conventional coding/decoding apparatus, however, presents some problems. For the case of a code length table (maximum ZERORUN: 63; maximum VALUE: 255; maximum code length: 16), such a code length table, when formed by RAMs or ROMs, requires a structure of 64 × 256 = 16384 words including AC codes without ZERORUN and AC codes without VALUE. If one word is made up of five bits on the average, then a total of 16384 × 5 = 81920 bits is required. This increases the table size, resulting in increasing the size of peripheral circuits of a code length table. Much more power is dissipated. There is a conventional way of reducing the size of logical tables which can be expressed as follows: (z, v) = (z - 1, 0) + (0, v) where z = ZERORUN and v = VALUE. For example, as shown in FIGURE 13 , if z = 10 and v = 2, then division is made as follows. (10, 2) = (9, 0) + (0, 2) This method can provide a logical table of 62 + 255 = 317 words. 317 words is still large for the size of logical tables. Another conventional data compression and decompression system is known from EP-A2-0 447 203. For data compression, digital video input data are subjected to a two-dimensional DCT. The DCT transformed data are applied to a quantizer unit. The quantitized data are formed into a data stream by a zig-zag conversion. The data steam is compressed by run-length coding which removes long runs of zeros. The resulting data are compressed using Huffman codes stored in Huffman code tables. During compression, a coder unit translates the run-length coded data into Huffman codes using the Huffman code tables. The Huffman code is designed such that length information of the code is embedded in the most significant five bits. During coding, the code length is extracted from the variable length Huffman codes and accumulated in order to transmit the total length to the host computer. These Huffman tables are shared between the coding and decoding unit. EP-A2-0 383 678 describes a method and system for writing and reading coded data. Variable length coded image data are stored in a memory together with a fixed length header and the VLC data are structured based on a plurality of hierarchical coding stages. During decoding, the coded data are read out from the memory by means of a "coded data extraction means". In order to calculate read addresses of further data, the code length of the read data is calculated. The code length calculation uses a code length table to detect the coded data and its code length. The detected code length is accumulated for each coding stage. In Article "A Complete Single-Chip Implementation of the JPEG Image Compression Standard", published by M. Bolton et al. in Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, San Diego, May 12-15, 1991, describes a still-picture compression chip for the JPEG compression standard. For JPEG applications the Huffman codec encodes and decodes frequency domain components of the compressed data stream wherein the same hardware is used for the encoding and decoding procedure. It is the object of the invention, to provide a digital coding apparatus and a digital coding and decoding apparatus comprising a variable-length coder (VLC) using a code length table of smaller size. This is achieved by the features of claim 1 for digital coding apparatus and by the features of claim 4 for digital coding and decoding apparatus. It is preferable that in the above-described digital coding and decoding apparatus the code length calculation circuit of the variable-length coding circuit serves also as the code length calculation circuit of the variable-length decoding circuit and the second logical table serves also as the third logical table. In accordance with the present invention, the second logical table (the code length table) stores variable-length codes encoded by the coding circuit and code lengths thereof in corresponding relationship. Accordingly this makes the second logical table of the present invention small in size in comparison with a conventional one that stores ZERORUN-VALUE combinations and code lengths in corresponding relationship. Additionally the size of peripheral circuits of a logical table can be reduced and less power consumption is achieved. In accordance with the present invention, the VLC and the VLD share a code length calculation circuit, and a logical table for use by the code length calculation circuit is also shared between the VLC and the VLD. This provides a smaller logical table. Accordingly the size of peripheral circuits of a logical table can be reduced and less power consumption is achieved. These and other objects and advantages of the present invention will become apparent to those skilled in the art upon consideration of the accompanying specification, claims and drawings. FIGURE 1 is a block diagram showing an entire organization of a digital coding/decoding apparatus in accordance with the present invention. FIGURE 2 is a diagram showing a variable-length coding circuit in accordance with a first embodiment of the present invention. FIGURE 3 is a diagram showing a variable-length coding circuit and a variable-length decoding circuit in accordance with a second embodiment of the present invention. FIGURE 4 is a diagram useful in understanding individual logical tables for use by variable-length coding and decoding circuits in accordance with the present invention. FIGURE 5 is a diagram useful in understanding corresponding relationships of variable-length codes versus code lengths thereof, in a variable-length coding circuit. FIGURE 6 is comprised of 6a-6d, wherein FIGURE 6a is a diagram showing an embodiment of an AC code length table in accordance with the present invention, and FIGURE 6b shows corresponding relationships of low-order parts of variable-length codes versus code lengths thereof, and FIGURE 6c shows corresponding relationships between input and output terminals of an AC code length table, low-order parts of variable-length codes, and code lengths thereof, and FIGURE 6d is a logical formula showing corresponding relationships between low-order parts of variable-length codes and code lengths thereof. FIGURE 7 is a diagram showing a conventional variablelength coding circuit. FIGURE 8 is a diagram showing a conventional variablelength decoding circuit. FIGURE 9 is a diagram useful in understanding logical tables for use by conventional variable-length coding and decoding circuits. FIGURE 10 shows an entire organization of a conventional digital coding/decoding apparatus. FIGURE 11 shows corresponding relationships between AC coefficients, ZERORUN-VALUE combinations, variable-length AC codes, and code lengths thereof. FIGURE 12 is a diagram useful in understanding fixed-length AC codes. FIGURE 13 is a diagram describing a conventional way of reducing the size of logical tables. Preferred embodiments of the present invention are described by making reference to the accompanying drawing figures. EMBODIMENT 1 A first digital coding apparatus of the present invention capable of performing image data compression is now described by making reference to FIGURES 1 and 2 . 14 is a discrete cosine transform circuit (DCT) that is an orthogonal transform circuit for reducing the amount of information by making use of signal power distribution bias. 15 is a quantizer. 25 is a variable-length coder (VLC). 17 is an inverse discrete cosine transform circuit (IDCT) which is an inverse orthogonal transform circuit. 18 is an inverse quantizer. 26 is a variable-length decoder (VLD). 27 is a circuit made up of the VLC 25 and the VLD 26 . The DCT 14 receives either an image data luminance signal or an image data chrominance signal and performs a discrete cosine transform on the received signal, a result of the discrete cosine transform operation being put out in the form of an AC coefficient. The quantizer 15 quantizes such an output of the DCT 14 , a result of the quantization operation being put out. The VLC 25 transforms such an output of the quantizer 15 into a variable-length Huffman code for further data compression. This variable-length AC code is padded to a fixed-length code. This fixed-length code is put out to a recording device (not shown) located outside the apparatus. The VLD 26 receives a fixed-length AC code (i.e., a Huffman code) from a recording device (not shown in the figure) located outside the apparatus, extracts a variable-length AC code from the received fixed-length AC code, and decodes and expands the variable-length Huffman code to put out an AC coefficient. The inverse quantizer 18 inverse-quantizes such an output of the VLD 26, a result of the inverse-quantization operation being put out. The IDCT 17 performs an inverse discrete cosine transform on an output of the inverse quantizer 18 , to obtain either an image data luminance signal or an image data chrominance signal. Such an obtained signal is fed to an image display unit (e.g., a CRT) located outside the apparatus. The digital coding apparatus of the present embodiment comprises the DCT 14, the quantizer 15 , and the VLC 25. FIGURE 2 is a diagram showing an internal organization of the VLC 25 . 1 is a decision circuit. 2 is a run length counter. 3 is an AC code table acting as a first logical table. 4 is a two-dimensional Huffman coding circuit. 7 is a padding circuit. 5 is a code length calculation circuit. 6 is an AC code length table acting as a second logical table. The decision circuit 1 receives from the quantizer 15 of FIGURE 1 an AC coefficient. Then the decision circuit 1 determines whether an AC coefficient received has a value of zero (zero value) or a value other than zero (nonzero value). The run length counter 2 counts the number of times the decision circuit 1 successively receives a zero-valued AC coefficient (i.e., the number of consecutive AC coefficients that are all determined by the run length counter 2 having a zero value). Whereas a nonzero-valued AC coefficient is defined as VALUE, the number of consecutive zero-valued AC coefficients is defined as ZERO RUN (ZERORUN). When ZERORUN-VALUE combinations are obtained as shown in FIGURE 11 , each ZERORUN-VALUE combination is fed to the two-dimensional Huffman coding circuit 4 . The AC code table 3 (i.e., the first logical table) prestores ZERORUN-VALUE combinations and variable-length AC codes in corresponding relationship (see FIGURE 11 ). The AC code table 3 corresponds to the variable-length-code encode table T1. Upon receipt of a certain ZERORUN-VALUE combination the two-dimensional Huffman coding circuit 4 provides a corresponding variable-length AC code according to the AC code table 3 . The AC code length table 6 (i.e., the second logical table) prestores variable-length AC codes and code lengths thereof in corresponding relationship (see FIGURE 11 ). More specifically the AC code length table 6 prestores decoded values of only plural low-order bits of variable-length AC codes and code lengths thereof in corresponding relationship (see FIGURE 5 ). The AC code length table 6 corresponds to the code length table T3 of FIGURE 4 . Upon receipt of a certain variable-length AC code from the two-dimensional Huffman coding circuit 4 , the code length calculation circuit 5 provides a corresponding code length according to the AC code length table 6 . The padding circuit 7 receives a variable-length AC code from the two-dimensional Huffman coding circuit 4 and a code length from the code length calculation circuit 5 and pads these data items received to a fixed-length AC code (see FIGURE 12 ). In accordance with the present embodiment, the AC code length table 6 , which is used when the code length calculation circuit 5 calculates a code length, is a table for storing variable-length AC codes and code lengths thereof in corresponding relationship (see the FIGURE 4 code length table T3). In comparison with a conventional code length table that stores ZERORUN-VALUE combinations and code lengths in corresponding relationship, the AC code length table 6 is smaller in size. As a result, the size of peripheral circuits of the AC code length table 6 can be reduced to a greater extent, and unnecessary access is no longer made, and less power is consumed. The above-noted effects of the present embodiment are explained in detail. A conventional VLC uses a ZERORUN-VALUE combination as an input signal of a code length calculation circuit, so that such a VLC requires a code length table that takes in a ZERORUN-VALUE combination and puts out a code length. For the case of a code length table (maximum ZERORUN: 63; maximum VALUE: 255; maximum code length: 16), this code length table, when formed with RAMs or ROMs, requires a size of 64 × 256 = 16384 words including AC codes without ZERORUN and AC codes without VALUE. If one word is made up of five bits on the average, then a total of 16384 × 5 = 81920 bits is required. This increases the table size. As described previously, there is a conventional method of reducing the size of logical tables which can be expressed as follows: (z, v) = (z - 1, 0) + (0, v) where z = ZERORUN and v = VALUE. This method can provide a logical table of 62 + 255 = 317 words. However, 317 words is still large for the size of logical tables. The present embodiment provides a code length table capable of downsizing circuits and accomplishing less power dissipation. Additionally the code length table T3 used by the code length calculation circuit 5 is a table capable of storing parts of variable-length codes and code lengths thereof in (18) corresponding relationship. This can downsize a code length table and provide fast calculations. The effects of the present invention are explained in detail. For example, in FIGURE 5 a maximum code length is sixteen bits and a minimum code length is three bits. In order to find the code length of an AC code, there is no need to decode the entire AC code. Decoding only the low-order five bits of the AC code is sufficient to find the code length. In this case, a code length table requires a 32-word size at most. In other words, the present invention can provide a 32-word code length table versus a 16384-word code length table for the prior art technique when a code length table is not divided (i.e., a reduction in size of about 99.8%). Further the present invention can provide, when a code length table is divided, a 32-word code length table versus a 317-word code length table for the prior art technique (i.e., a reduction in size of about 90%). Theoretically the number of words required should be equal to the number of code length types. In an example of FIGURE 5 there are fourteen types of code lengths (from a 3-bit code length to a 16-bit code length). Therefore the number of words required is fourteen. With the present code length table added to the output of the variable-length encode table T1, a code length can be found. This eliminates the need for providing peripheral circuits of a code length table, thereby reducing the entire circuit size. Referring now to FIGURE 6a, therein is illustrated an embodiment of the AC code length table 6 (the second logical table). FIGURE 6a is an organization with respect to ZERORUN-VALUE combinations of FIGURE 5 , i.e., (0,1) and (0,2). As can be seen from FIGURE 6b and from FIGURE 5, the ZERORUN-VALUE combination (0,1) corresponds to [00] while the ZERORUN-VALUE combination (0,2) corresponds to [010], and corresponding code lengths are [3] and [4]. As shown in FIGURE 6c, the AC code length table 6 has input terminals A3, A2, and A1 at which variable-length codes are applied and output terminals Y3, Y2, and Y1 at which code lengths are put out. The input terminals A3, A2, A1 and the output terminals Y3, Y2, Y1 are shown in corresponding relationship by logical formulas of FIGURE 6d. If these logical formulas are constructed by means of a random logic of logical circuits, this results in the FIGURE 6a organization. If, as described above, the AC code length table 6 is constructed using a random logic, this not only provides fast table reference operations but also contributes to reducing the size of logical tables. The AC code length table 6 may be formed by RAMs or ROMs. EMBODIMENT 2 FIGURE 3 shows main parts of a digital coding/decoding apparatus in accordance with a second embodiment of the present invention. The entire organization of the present digital coding/decoding apparatus is identical with the one shown in FIGURE 1 , therefore the description thereof being omitted here. 25 is a VLC identical in configuration with the one described in the first embodiment VLC. 26 is a VLD. FIGURE 3 is a diagram showing an internal organization of the VLC 25 as well as an internal organization of the VLD 26. 9 is a two-dimensional Huffman decoding circuit. 10 is an extraction circuit. 11 is an inverse AC code table (the fourth logical table). 5 is a code length calculation circuit. 6 is an AC code length table (the third logical table). The code length calculation circuit 5 and the AC code length table 6 are shared between the VLD 26 and the VLC 25. In other words, the code length calculation circuit 5 takes in a Huffman code at the coding time and at the decoding time, to calculate its code length with the aid of the AC code length table 6 . Arranged at a preceding stage to the code length calculation circuit 5 is a selector 30 . The selector 30 is operable to select between a variable-length AC code from the two-dimensional Huffman coding circuit 4 of the VLC 25 and a fixed-length AC code taken in from outside the apparatus, thereafter providing a code selected to the code length calculation circuit 5 . More specifically, the selector 30 selects a variable-length AC code from the two-dimensional Huffman coding circuit 4 at the coding time while it selects a fixed-length AC code taken in from outside the apparatus at the decoding time. In the VLD 26 , the code length calculation circuit 5 performs a calculation, to find a code length of a variable-length AC code contained in an external fixed-length AC code according to the AC code length table 6 . The extraction circuit 10 accepts a fixed-length AC code and the code length thus found by the code length calculation circuit 5 , to extract a variable-length AC code. The two-dimensional Huffman decoding circuit 9 is operable to transform such an extracted variable-length AC code into a ZERORUN-VALUE combination according to the inverse AC code table 11 (the fourth logical table). In the present embodiment, the code length calculation circuit 5 and the AC code length table 6 are shared between the VLC 25 and the VLD 26 . Therefore the present embodiment, compared with the first embodiment, can reduce the entire circuit size to a further extent and provides a low-power-dissipation digital coding/decoding apparatus. The description has been made taking an example case where a DCT circuit as an orthogonal transform circuit and an IDCT as an inverse orthogonal transform circuit are used. However, any transform circuit capable of performing a Fourier transform, a discrete Fourier transform, an Hadamard transform, a Karhunen-Loeve transform, a discrete sine transform, a slant transform, or a Haar transform may be used as an orthogonal transform circuit, and any transform circuit capable of performing an inverse Fourier transform, an inverse discrete Fourier transform, an inverse Hadamard transform, an inverse Karhunen-Loeve transform, an inverse discrete sine transform, an inverse slant transform, or an inverse Haar transform may be used as an inverse orthogonal transform circuit. The inverse quantizer 18 and the quantizer 15 each have irreversibilities. In other words, the inverse quantizer 18 is unable to completely restore the post-quantization data into the original one by means of inverse quantization. Therefore the inverse quantizer 18 and the quantizer 15 may be omitted in a digital coding/decoding apparatus giving importance to reversibility. In the description, the coding circuit is formed by the Huffman coding circuit 4 . However, the coding circuit may be formed by a calculation coding circuit. The decoding circuit is formed by the Huffman decoding circuit 9 in the description. However, the decoding circuit may be formed by a calculation decoding circuit. The present invention finds applications in DVC and MPEG (the image processing standards specification).

Claims: A digital coding apparatus comprising: an orthogonal transform circuit (14) for performing an orthogonal transform on data to find a great number of transform coefficients, each of said transform coefficients having either a value of zero or a value other than zero, a variable-length coding circuit (25) for converting transform coefficients from said orthogonal transform circuit (14) into a variable-length code, for padding said variable-length code to a fixed-length code, and for providing said fixed-length code to outside said digital coding apparatus, said variable-length coding circuit (25) including: a first logical table (3) for storing, in corresponding relationship, combinations of the numbers of consecutive zero-valued transform coefficients and non zero-valued transform coefficients, and variable-length codes, a coding circuit (4) for receiving in sequence transform coefficients from said orthogonal transform circuit, and for converting, based on said first logical table (3), a combination of the number of consecutive zero-valued transform coefficients and a nonzero-valued transform coefficient of said received transform coefficients, into a variable-length code, and a padding circuit (7) for receiving a variable-length code from said coding circuit (4) and for padding said received variable-length code to a fixed-length code characterized in that said variable-length coding circuit (25) further including: a second logical table (6) for storing variable-length codes and code lengths thereof in corresponding relationship, a code length calculation circuit (5) for receiving a variable-length code from said coding circuit (4), and for calculating, based on said second logical table (6), a code length of said received variable-length code, and said padding circuit (7) further receiving a code length from said code length calculation circuit (5)and padding said received variable-length code to a fixed-length code based on said received code length. A digital coding apparatus according to claim 1, wherein said second logical table (6) being formed by means of logical circuits connected together. A digital coding apparatus according to claim 1, wherein said second logical table (6) prestoring, in corresponding relationship, parts of variable-length codes and code lengths thereof. A digital coding and decoding apparatus comprising: an orthogonal transform circuit (14) for performing an orthogonal transform on data to find a great number of transform coefficients, each of said transform coefficients having either a value of zero or value other than zero, a variable-length coding circuit (25) for converting transform coefficients from said orthogonal transform circuit (14) into a variable-length code, for padding said variable-length code to a fixed-length code, and for providing said fixed-length code to outside said digital coding and decoding apparatus, a variable-length decoding circuit (26) for receiving a fixed-length code from outside said digital coding and decoding apparatus, and for converting said received fixed-length code into a great number of transform coefficients, each of said transform coefficients having either a value of zero or a value other than zero, an inverse orthogonal transform circuit (17) for performing an inverse orthogonal transform on a zero-valued transform coefficient or a nonzero-valued transform coefficient from said variable-length decoding circuit (26), said variable-length coding circuit (25) including: a first logical table (3) for storing, in corresponding relationship, combinations of the numbers of consecutive zero-valued transform coefficients and nonzero-valued transform coefficients and variable-length codes, a coding circuit (4) for receiving in sequence transform coefficients from said orthogonal transform circuit (14), and for converting, based on said first logical table (3), a combination of the number of consecutive zero-valued transform coefficients and a nonzero-valued transform coefficient of said received transform coefficients, into a variable-length code, and a padding circuit (7) for receiving a variable-length code from said coding circuit (4) and for padding, said received variable-length code to a fixed-length code; said variable-length decoding circuit (26) including: an extraction circuit (10) for receiving a fixed-length code from outside said digital coding and decoding apparatus and for extracting a variable-length code from said received fixed-length code, a fourth logical table (11) for storing, in corresponding relationship, variable-length codes and combinations of the numbers of consecutive zero-valued transform coefficients and nonzero-valued transform coefficients, and a decoding circuit (9) for converting, based on said fourth logical table (11), a variable-length code from said extraction circuit (10) into zero-valued and nonzero-valued transform coefficients characterized in that said variable-length coding circuit (25) further including; a second logical table (6) for storing variable-length codes and code lengths thereof in corresponding relationship, and a code length calculation circuit (5) for receiving a variable-length code from said coding circuit (4), and for calculating, based on said second logical table (5), a code length of said received variable-length code, and said padding circuit (7) further receiving a code length form said code length. calculation circuit (5) and padding said received variable-length code to a fixed length code based on said received code length, said variable-length decoding circuit (26) further including; a third logical table (6) for storing variable-length codes and code lengths thereof in corresponding relationship, a code length calculation circuit (5) for receiving a fixed-length code from outside said digital coding and decoding apparatus, and for calculating, based on said third logical table (5), a code length of a variable-length code contained in said received fixed-length code, and said extraction circuit (10) further receiving a code length from said code length calculation circuit (5) and extracting a variable-length code from said fixed-length code based on said received code length, said code length calculation circuit (5) of said variable-length coding circuit (25) serving also as said code length calculation circuit (5) of said variable-length decoding circuit (26), and said second logical table (6) serving also as said third logical table (6). A digital coding and decoding apparatus according to claim 4, wherein said second logical table (6) being formed by a means of logical circuits connected together. A digital coding and decoding apparatus according to claims 4 or 5, wherein said second logical table (6) prestoring, in corresponding relationship, parts of variable-length codes and code lengths thereof.

Inventors: OHARA KAZUTAKE, OHARA, KAZUTAKE
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1995
Main classification: H04N7
IPC codes: H04N7, G06T9