Voltage generator-booster for supplying an approximately constant voltage level

Abstract: A generator-booster (1) comprising a bootstrap capacitor (2) with a first terminal (3) connected to the supply line (14), and a second terminal (4) constituting a pull-up node (4); a bootstrap control stage (7) connected to the pull-up node (4) and receiving a pump signal (V PN ) with two states determining the precharge step and the pull-up step of the bootstrap capacitor; a precharge limiting transistor (13) supplied with a precharge reference signal (V UP ) and connected to the first terminal (3) of the bootstrap capacitor (2) to prevent the capacitor (2) from being charged in excess of the value determined by the precharge reference signal; and a limiting stage (8) connected to the first terminal (3) of the bootstrap capacitor to prevent the voltage of the first terminal from exceeding the value determined by the limiting stage (8). The bootstrap control stage (7) also provides for decoupling the pull-up node (4) from the pump signal (V PN ) during the pull-up step, after the limiting stage (8) has been turned on.

Description: The present invention relates to a voltage generator-booster for supplying an approximately constant voltage level. Integrated circuits currently demand voltage levels that remain substantially constant alongside a variation in supply voltage. The voltage levels may be higher than the supply voltage, in which case a voltage generator (booster) for increasing the supply voltage is called for, or they may be lower, in which case the voltage generator provides for limiting the supply voltage. Generation of the high voltage is important, for example, in the case of nonvolatile memories with a 3 V supply voltage, the cells of which must therefore be read at a higher gate voltage; whereas, in the presence of a high supply voltage, this must be limited to prevent the reading of programmed cells. If a circuit capable of operating at both high and low supply voltages is required, with a voltage generator for supplying an approximately constant voltage level alongside a variation in supply voltage, the generator must be capable of operating as both a voltage booster and limiter, depending on the supply voltage. At present, known voltage boosters (see US-A-5,132,895) substantially comprise a charge pump circuit in turn comprising a bootstrap capacitor and pull-up circuit, and which operates in two steps: a first step to precharge the capacitor, wherein a first terminal of the capacitor is grounded and a second terminal is connected to the supply voltage to precharge the capacitor to roughly the supply voltage; and a second step wherein the first terminal of the capacitor is pulled up to the supply voltage, and the second terminal (which is therefore at nearly twice the supply voltage) is connected to an output. Even though the actual output voltage depends on the charge distribution between the bootstrap capacitor and the capacitance of the load supplied by the booster, so that the final output voltage is less than twice the supply voltage, the output voltage of known boosters is highly dependent on supply voltage, thus preventing them from being employed in devices operating within a wide range of different supply voltages (e.g. 3 to 7 V). It is an object of the present invention to provide a voltage generator-booster for supplying, alongside a variation in supply voltage, an approximately constant voltage level higher or lower than the supply voltage itself. According to the present invention, there is provided a voltage generator-booster for supplying an approximately constant voltage level, and as claimed in Claim 1. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a block diagram of the generator-booster according to the present invention; Figure 2 shows a simplified circuit diagram of the Figure 1 generator-booster; Figure 3 shows a graph of the output voltage of the Figure 2 generator-booster alongside a variation in supply voltage; Figures 4 to 6 show the plot of the voltages measured at nodes of the Figure 2 diagram, for three different supply voltage values. The voltage generator-booster 1 in Figure 1 comprises a bootstrap capacitor 2 in turn presenting a first and second terminal 3, 4; terminal 3 defining the output node presenting bootstrap voltage V B ; and terminal 4 defining the pull-up node which is brought alternately to low and high voltage (control voltage V BOT ) during precharge and pull-up. Nodes 3 and 4 are connected to a bootstrap control stage 7 for controlling pull-up of node 4 and hence of output node 3, and the input terminal 6 of which is supplied with a pump signal V PN oscillating between 0 V and supply voltage V DD , and which determines the precharge and pull-up sequence of capacitor 2. A clipping stage 8 is connected to nodes 3 and 4, and cooperates with bootstrap control stage 7 so as to lock bootstrap voltage V B at output node 3 in controlled manner and at a predetermined value, and block pull-up of node 4 by bootstrap control stage 7 when clipping stage 8 is turned on during pull-up. Blocking is preferably achieved by disconnecting voltage V BOT at node 4 during pull-up, and locking it to voltage V B at output node 3, so that clipping of V B automatically also clips V BOT . A pulse amplitude preset stage 10 provides for generating a precharge reference voltage V UP and a turn-on reference voltage V LC for respectively determining the charge voltage of capacitor 2 during precharge, and the turn-on value of clipping stage 8. For which purpose, stage 10 presents two output terminals 11 and 12 (presenting reference voltages V UP and V LC ) respectively connected to the gate terminal of a MOS transistor 13, and to clipping stage 8. Transistor 13 is interposed between output node 3 and a supply line 14 at voltage V DD , so as to permit charging of capacitor 2 during the precharge step. In other words, transistor 13 provides for limiting the precharge voltage of capacitor 2 to the value set by precharge reference voltage V UP , minus the voltage drop V GS between its source and gate terminals, and is turned off during pull-up so as to disconnect output node 3 from supply line 14. The Figure 1 generator-booster operates as follows. During the precharge step determined by a high value (V DD ) of pump signal V PN , pull-up node 4 is maintained at a low voltage (V BOT = 0 V) to enable capacitor 2 to be charged to the value set by precharge reference voltage V UP minus V GS . Typically, precharge reference voltage V UP is roughly 3 V, and bootstrap voltage V B at output node 3 during precharge is roughly 2 V. During pull-up, as pump signal V PN falls to ground voltage (0 V), this is accompanied by an inverse increase in potential V BOT at pull-up node 4 and hence in potential V B at output node 3; and, upon potential V BOT at pull-up node 4 reaching the predetermined value set by turn-on reference voltage V LC , clipping stage 8 is turned on to lock bootstrap voltage V B and block pull-up of node 4 by stage 7, so that bootstrap voltage V B is locked to the value determined by clipping stage 8. Typically, turn-on reference voltage V LC is roughly 1.5 V; the turn-on voltage of clipping stage 8 (control voltage V BOT ) ranges between 2.5 and 3 V; and bootstrap voltage V B , during pull-up, ranges between roughly 3.9 and 4.6 V, depending on supply voltage V DD . In other words, bootstrap voltage V B is basically clipped in two ways: by preventing capacitor 2 from being charged to a high level; and by preventing output node 3 from exceeding the predetermined value. In addition to which, pull-up node 4 is clipped by disconnecting it from the pumping action of signal V PN to prevent unnecessary consumption. Figure 2 shows one embodiment of the Figure 1 generator-booster. In Figure 2, pulse amplitude preset stage 10 comprises the series connection of three P-channel transistors 20, 21, 22 between supply line 14 and ground line 15. More specifically, transistor 20 is a resistive type (low width/length W/L ratio) with its source terminal connected to supply line 14, its drain terminal defining output terminal 11 of stage 10, and its gate terminal connected to output terminal 12; transistor 21 is a diode-connected native transistor (with no alteration in its threshold voltage during fabrication, and therefore presenting a high threshold voltage) with its source terminal connected to output terminal 11, and its drain and gate terminals connected to each other and to output terminal 12; and transistor 22 is also a diode-connected native transistor with its source terminal connected to output terminal 12, and its gate and drain terminals connected to each other and to ground line 15. A preferably 0.5 pF capacitor 23 is interposed between ground line 15 and output terminal 12; the body region of transistor 22 is connected to output terminal 12; and the body region of transistor 21 is connected to output terminal 11 and, via a capacitor 24 of, say, 0.5 pF, to ground line 15. Clipping stage 8 comprises a P-channel MOS transistor 25 with its drain terminal connected to ground line 15, its gate terminal connected to output terminal 12, and its source terminal connected to the source terminal of an N-channel transistor 26 (presenting voltage V SB ). The gate terminal of transistor 26 is connected to pull-up node 4, and its drain terminal to the drain terminal of a diode-connected P-channel transistor 27 which therefore presents its gate terminal connected to its drain terminal, and its source terminal connected to output node 3. The body regions of transistors 25 and 27 are both connected to output node 3. Transistor 13 here comprises an N-channel native transistor with a low threshold voltage; and the capacitor is preferably 2 pF. Bootstrap control stage 7 comprises an N-channel transistor 30 with its source terminal connected to ground line 15, its gate terminal connected to input terminal 6, and its drain terminal connected to pull-up node 4; and an inverter 31 with its input connected to input terminal 6, and its output connected to the drain terminal of a low-threshold N-channel native transistor 32 with its gate terminal connected to output node 3, and its source terminal connected to pull-up node 4. The output of inverter 31 therefore presents an inverted pump signal V P opposite to signal V PN at input terminal 6. The generator-booster in Figure 2 operates as follows. When pump signal V PN is high, transistor 30 is on and keeps pull-up node 4 grounded; at the same time, the output of inverter 31 is low (V P = 0 V) and transistor 32 is off; output terminal 12 presents a voltage V LC of roughly 1.5 V given by the voltage drop across the gate and source terminals of transistor 22; output terminal 11 presents a voltage V UP of roughly 3 V given by the sum of V LC and the voltage drop across the gate and source terminals of transistor 21; transistor 13 is on, thus permitting capacitor 2 to be charged to the specified V UP value minus V GS , i.e. to roughly 2 V (which therefore also represents the value of voltage V B during precharging); and clipping stage 8 is off, by virtue of the voltage V BOT at the gate terminal of transistor 26 being lower than the voltage V SB at its source terminal, so that transistor 26 is off. When pump signal V PN switches to low and its inverted signal V P increases, the voltage V BOT at pull-up node 4 also begins increasing, "drawn" by transistor 32 which has come on; and, at the same time, bootstrap voltage V B also increases. Upon voltage V BOT reaching the value specified by turn-on reference voltage V LC plus the difference in potential between the drain and gate terminals of transistor 25, and the difference in potential between the gate and source terminals of transistor 26 (total 2.5-3 V), transistor 26 comes on, thus turning on clipping stage 8 which clips the voltage V B at output node 3 to a value equal to the sum of the voltage drops across transistors 25-27. Which value varies little alongside supply voltage V DD : between 3.94 V when V DD = 3 V, and 4.59 V when V DD = 7 V. Clipping of V B automatically results in clipping of V BOT via transistor 32 which, despite even a high increase in inverted pump voltage V P (to 7 V in the case of a 7 V supply voltage), prevents its source terminal from following the course of the drain voltage. Clipping and blocking voltage V BOT at the gate terminal of transistor 26 confirms the clipping action of stage 8, so that bootstrap voltage V B is blocked to the predetermined value. In the Figure 2 circuit, the clipping voltage imposed by stage 8 depends both on the turn-on value V LC imposed by pulse amplitude preset stage 10, and on the voltage values of transistors 25-27, so that the maximum value of bootstrap voltage V B may be adjusted by simply acting on turn-on reference voltage V LC . Figures 4-6 show graphs of voltages V P , V BOT , V B , V SB , V LC , V UP in the Figure 2 circuit for three different supply voltage V DD values. Each graph shows the gradual, nonimpulsive pattern of the voltages due to the delays involved; the gradual turn-on of the various components; the very small variation in bootstrap voltage V B in each case; and the manner in which V B differs in each case in relation to inverted pump voltage V P , i.e. is higher than the pump voltage when the supply voltage is low (3 V), is only slightly lower than the pump voltage when the supply voltage is medium (5 V), and differs considerably from the pump voltage when the supply voltage is high (7 V). The advantages of the generator-booster described are as follows. Firstly, as shown, it provides for supplying a bootstrap voltage that varies very little, even in the presence of widely differing supply voltages. Secondly, it provides for considerably reducing consumption, in that the only part supplied with current is pulse amplitude preset stage 10 via resistive transistor 20, which draws different current levels depending on the supply voltage. The other stages in fact consume and are supplied with no current, except for small capacitive peaks when switching from one step to the other. Thirdly, it is extremely straightforward in design, reliable, and easy to integrate. And fourthly, the bootstrap, turn-on and clipping voltage values may be set as required by simply sizing the transistors accordingly, or using different types of transistors (e.g. other than native). Clearly, changes may be made to the generator-booster as described and illustrated herein without, however, departing from the scope of the claims. For example, the Figure 1 stages may be formed differently from those shown in Figure 2, providing they perform the clipping functions as indicated; changes may be made to the components shown, using other than native transistors for the references, or other elements capable of ensuring predetermined voltages; the capacitors may be formed using integrated capacitors, appropriately connected MOS transistors, or any existing technique; and changes may be made to the component and voltage values shown, which are purely indicative.

Claims: A voltage generator-booster (1) for supplying an approximately constant voltage level, comprising a bootstrap capacitor (2) with a first terminal (3) connected to a first reference potential line (14), and a second terminal (4) connected to a pull-up node (4); and a bootstrap control stage (7) connected to said pull-up node (4) and presenting a pump input (6) supplied with a pump signal (V PN ) switchable between two different states defining a precharge step and a pull-up step of said bootstrap capacitor; characterized in that it comprises precharge limiting means (13) connected to said first terminal (3) of said bootstrap capacitor (2) and supplied with a precharge reference signal (V UP ), and which, at said precharge step, provide for limiting the charge of said bootstrap capacitor (2) to a limitation value related to said precharge reference signal; and a limiting stage (8) connected to said first terminal (3) of said bootstrap capacitor (2), so as to limit the potential at said first terminal of said bootstrap capacitor at said pull-up step. A generator-booster as claimed in Claim 1, characterized in that said bootstrap control stage (7) comprises decoupling means (30, 32) located between said pump input (6) and said pull-up node (4), and which provide for decoupling said pump input from said pull-up node when the pull-up node reaches a predetermined voltage value. A generator-booster as claimed in Claim 1 or 2, characterized in that it comprises a pulse amplitude preset stage (10) for generating said precharge reference signal (V UP ), and a turn-on reference signal (V LC ) supplied to said limiting stage (8). A generator-booster as claimed in any one of the foregoing Claims, characterized in that said precharge limiting means comprise a precharge transistor (13) with a first terminal connected to said first reference potential line (14), a second terminal connected to said first terminal (3) of said bootstrap capacitor (2), and a control terminal supplied with said precharge reference signal (V UP ). A generator-booster as claimed in Claim 4, characterized in that said precharge transistor (13) is a native MOS transistor. A generator-booster as claimed in one of the foregoing Claims from 3 to 5, characterized in that said limiting stage (8) comprises a limiting branch (25-27) connected between said first terminal (3) of said bootstrap capacitor (2) and a second reference potential line (15); an input terminal (12) supplied with said turn-on reference signal (V LC ); and a turn-on element (25, 26) interposed along said limiting branch; said turn-on element being connected to said second terminal (4) of said bootstrap capacitor and to said input terminal (12) of said limiting stage; and said turn-on element (25, 26) turning on said limiting branch when the voltage at said second terminal (4) of said bootstrap capacitor (2) reaches a value determined by said turn-on reference signal. A generator-booster as claimed in Claim 6, characterized in that said turn-on element (25, 26) comprises a first (26) and second (25) turn-on transistor interposed along said limiting branch (25-27); said first turn-on transistor (26) presenting a control terminal connected to said second terminal (4) of said bootstrap capacitor (2); and said second turn-on transistor (25) presenting a control terminal defining said input terminal (12) of said limiting stage (8). A generator-booster as claimed in any one of the foregoing Claims, characterized in that said bootstrap control stage (7) comprises a first (30) and second (32) decoupling transistor operating in push-pull manner; said first decoupling transistor (30) being interposed between said second terminal (4) of said bootstrap capacitor (2) and a second reference potential line (15), and presenting a control terminal connected to said pump input (6); and said second decoupling transistor (32) being interposed between said pump input (6) and said second terminal of said bootstrap capacitor, and presenting a control terminal connected to said first terminal (3) of said bootstrap capacitor (2). A generator-booster as claimed in Claim 8, characterized in that said first and second decoupling transistors (30, 32) are the same type; and an inverting element (31) is interposed between said pump input (6) and said second decoupling transistor (32). A generator-booster as claimed in Claim 9, characterized in that said first and second decoupling transistors (30, 32) are N-channel MOS transistors. A generator-booster as claimed in any one of the foregoing Claims from 3 to 10, characterized in that said pulse amplitude preset stage (10) comprises a voltage setting branch (20-22) interposed between said first reference potential line (14) and a second reference potential line (15); said voltage setting branch comprising a number of constant-voltage-drop elements (21, 22) connected in series, and resistance means (20) interposed between said constant-voltage-drop elements and said first reference potential line (14). A generator-booster as claimed in Claim 11, characterized in that said constant-voltage-drop elements (21, 22) comprise diode-connected transistors; and said resistance means (20) comprise a MOS transistor.

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: B66B1
IPC codes: H03K19, G05F3, H03K5, G11C11, H02M3