Voltage-level shifter

Abstract: In a voltage-level shifter, a P-channel MOS transistor (Qp1603) (early cut-off circuit) is interposed between a voltage source (Vpp) of the voltage-level shifter and a source of a P-channel MOS transistor (Qp1602) which tends to be turned on when a voltage of a voltage source of an input signal supplies a low voltage or a large potential difference exists between the voltage source of the input signal (Vcc) and the voltage source of the voltage-level shifter (Vpp), and is supplied on its gate with the input signal of the voltage-level shifter. Accordingly, the interposed P-channel MOS transistor (Qp1603) is turned off prior to the P-channel MOS transistor (Qp1602) having a tendency of being turned on, so that the voltage level of the output signal of the voltage-level shifter can be rapidly fixed at the "L" level.

Description: The invention refers to a voltage-level shifter as set forth in the preamble of claim 1. A voltage-level shifter of this kind is known form US-A-5,276,366. The afore-mentioned document discloses a digital voltage-level translator circuit for interfacing circuitry operating at different voltages. A voltage-level shifter in the prior art similar to that of US-A-5276366 above will be described below. Fig. 12 shows a circuit structure of a conventional voltage-level shifter in the prior art, and Fig. 13 shows an operation timing of the conventional voltage-level shifter. In these figures, I30 indicates an input signal, 030 indicates an output signal, VCC indicates a first voltage source, VPP indicates a second voltage source, VSS indicates a ground voltage source, 3001 indicates a voltage-level shifter, Qn3001 and Qn3002 indicate N-channel MOS transistors, Qp3001 and Qp3002 indicate P-channel MOS transistors, and N3001 indicates a node name. A circuit structure in Fig. 12 will be described below. The input signal I30 is connected to the source of the N-channel MOS transistor Qn3001 and the gate of the N-channel MOS transistor Qn3002. The gate of the N-channel MOS transistor Qn3001 is connected to the first voltage source VCC, and the source of the N-channel MOS transistor Qn3002 is connected to the ground voltage source VSS. The source of the P-channel MOS transistor Qp3001 and the source of the P-channel MOS transistor Qp3002 are connected to the second voltage source VPP. The drain of the N-channel MOS transistor Qn3001, the drain of the P-channel MOS transistor Qp3001 and the gate of the P-channel MOS transistor Qp3002 are connected together. The output signal 030 is connected to the drain of the N-channel MOS transistor Qn3002, the gate of the P-channel MOS transistor Qp3001 and the drain of the P-channel MOS transistor Qp3002. Fig. 14 shows a basic structure of the voltage-level shifter in Fig. 12. The structure in Fig. 14 differs from that in Fig. 12 in that an N-channel MOS transistor Qn3001' is supplied on its gate with a signal formed by inverting the input signal by an inverter INV32, has its source connected to the voltage source VSS of the input signal, and has its drain connected to the P-channel MOS transistor Qp3202. In other words, the structure in Fig. 12 eliminates the inverter circuit INV32 by employing the appropriate connection structure of the N-channel MOS element Qn3001, but performs the same operation as the basic structure in Fig. 14. Accordingly, the operation will be described below only in connection with the structure in Fig. 12. Referring to the operation timing diagram of Fig. 12, the operation will be described below. When the input signal I30 is at the "L" (Low) level, the node N3001 is at the "L" level, the N-channel MOS transistor Qn3002 is off, P-channel MOS transistor Qp3002 is on, output signal 030 is at the "H" level set by the second voltage source VPP, and the P-channel MOS transistor Qp3001 is completely off. When the input signal I30 transits from the "L" level to the "H" level, the N-channel MOS transistor Qn3002 is completely turned off, the node N3001 attains a potential (VCC-Vtn) which is lower than the potential of the first voltage source VCC by a threshold voltage (Vtn) of the N-channel MOS transistor Qn3001, and the P-channel MOS transistor Qp3002 is substantially turned off. Then, the output signal 030 attains the "L" level, the P-channel MOS transistor Qp3001 is completely turned off, the node N3001 attains the potential of the second voltage source VPP, and the p-channel MOS transistor Qp3002 is completely turned off. However, in the voltage-level shifters of the conventional structures shown in Figs. 12 and 14, when the input signal I30 transits from the "L" level to the "H" level, the N-channel MOS transistor Qn3002 is completely off, and the P-channel MOS transistor Qp3002 is substantially off as already described. In particular, if the first voltage source VCC supplies a low voltage, and/or a large potential difference exists between the first and second voltage sources VCC and VPP, the P-channel MOS transistor Qp3002 is on. Therefore, a through current flows from the second voltage source VPP to the ground voltage source VSS via the N-channel MOS transistor Qn3002 and the P-channel MOS transistor Qp3002, which causes a disadvantage that the voltage level of the output signal 030 cannot fixed at the "L" level. SUMMARY OF THE INVENTION An object of the invention is to provide a voltage-level shifter which can operate as follows if a voltage source of an input signal supplies a low voltage and/or a large potential difference exists between a voltage source of an input signal and a voltage source of a voltage-level shifter; When the input signal transits from an "L" level to the "H" level, a MOS transistor to be turned off is surely controlled to be turned off, and the voltage level of an output signal of the voltage-level shifter is surely fixed at the "L" level while surely preventing flow of a through current, and wherein Another object of the invention is to provide a voltage-level shifter, in which both maximum and minimum values of an input signal are amplified by level shift at one stage, so that a speed for the level shift can be improved, and component transistors are reduced in number to simplify the structure. In order to achieve the above objects, a voltage-level shifter according to the invention comprises the features of the independent claims. Preferred embodiments of the invention are subject matter of the dependent claims. According to the voltage-level shifter of the invention, when the input signal transits from the "L" level to the "H" level, the early cut-off circuit is turned off at a timing earlier than the off timing of the second MOS transistor. Therefore, even if the second MOS transistor is not surely turned off when the voltage source VCC of the input signal supplies a low voltage, and/or a large potential difference exists between the voltage source VCC of the input signal and the voltage source VPP of the level shifter, the output signal is surely fixed at the "L" level. Also, it is possible to restrict effectively a through current flowing from the voltage source VPP of the level shifter to the ground VSS. Further, according to an embodiment of the voltage-level shifter of the invention, since multiple voltage level shifter units connected in series are used to change the potential-of the input signal to the potential of the voltage source VPP in stepwise fashion, the voltage level of the output signal of the voltage-level shifter can be fixed even when a large potential difference exists between the voltage source VCC of the input signal and the voltage source VPP of the voltage-level shifter. Furthermore, according to the voltage-level shifter of the invention, the amplitude of the input signal is increased by the level shift at a single stage for outputting the signal of a large amplitude, so that the operation of shifting the voltage level can be performed fast, and required transistors can be reduced in number. Other objects, features and advantages of the invention will appear more fully from the following detailed description thereof taken in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings showing preferred embodiments of the invention: Fig. 1 shows a structure of a first embodiment of a voltage-level shifter of the invention; Fig. 2 shows a structure of a second embodiment of the voltage-level shifter of the invention; Fig. 3 shows a structure of a third embodiment of the voltage-level shifter of the invention; Fig. 4 shows a structure of a fourth embodiment of the voltage-level shifter of the invention; Fig. 5 shows a structure of a fifth embodiment of the voltage-level shifter of the invention; Fig. 6 shows a structure of a sixth embodiment of the voltage-level shifter of the invention; Fig. 7 shows a structure of a seventh embodiment of the voltage-level shifter of the invention; Fig. 8 shows a structure of an eighth embodiment of the voltage-level shifter of the invention; Fig. 9 shows the operation timing of the eighth embodiment of the voltage-level shifter of the invention; Fig. 10 shows a structure of a ninth embodiment of the voltage-level shifter of the invention; Fig. 11 shows the operation timing of the ninth embodiment of the voltage-level shifter of the invention; Fig. 12 shows a structure of a voltage-level shifter in the prior art; Fig. 13 shows an operation timing of the voltage-level shifter in the prior art; and Fig. 14 shows a basic structure of a voltage-level shifter in the prior arts DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the invention will be described below with reference to the drawings. A voltage-level shifter of a first embodiment of the invention will now be described below. Fig. 1 shows a circuit structure. In Fig. 1, I16 indicates an input signal, 016 indicates an output signal, VCC indicates a first voltage source, VPP indicates a second voltage source, and VSS indicates a ground voltage source. 1601 indicates a voltage-level shifter, Qn1601 indicates an N-channel MOS transistor (first N-channel MOS switch element) and Qn1602 indicates an N-channel MOS transistor (second N-channel MOS switch element). Qp1601 indicates a P-channel MOS transistor (first P-channel MOS transistor) and Qp1602 indicates a P-channel MOS transistor (second P-channel MOS transistor). Qp1603c indicates a P-channel MOS transistor (third P-channel MOS transistor). N1601 indicates a node name. The circuit structure in Fig. 1 will be described below. In the voltage-level shifter 1601, the input signal I16 is connected to the source of the N-channel MOS transistor Qn1601, the gate of the N-channel MOS transistor Qn1602 and the gate of the P-channel MOS transistor Qp1603. The gate of the N-channel MOS transistor Qn1601 is connected to the first voltage source VCC. The source of the N-channel MOS transistor Qn1602 is connected to the ground voltage source VSS. The node 1601 is connected to the drain of the N-channel MOS transistor Qn1601, the drain of the P-channel MOS transistor Qp1601 and the gate of the P-channel MOS transistor Qp1602. The source of the P-channel MOS transistor Qp1601 and the source of the P-channel MOS transistor Qp1603 are connected to the second voltage source VPP. The drain of the P-channel MOS transistor Qp1603 is connected to the source of the P-channel MOS transistor Qp1602. Further, the output signal O16 is connected to the drain of the N-channel MOS transistor Qn1602, the gate of the P-channel MOS transistor Qp1601 and the drain of the P-channel MOS transistor Qp1602. Owing to the connection structure of the N-channel MOS transistor Qn1601, as already described, the circuit serves also as a signal inverter circuit for inverting the input signal I16. Further, owing to the provision of the third P-channel MOS transistor Qp1603, an early cut-off circuit 160 is formed. The voltage-level shifter in Fig. 1 has such a feature that the P-channel MOS transistor Qp1603 is connected between the source of the P-channel MOS transistor Qp1602 and the second voltage source VPP, and the gate of the P-channel MOS transistor Qp1603 receives the input signal I16, so that, when the input signal I16 is at the potential of the first voltage source VCC, the node N1601 is at the potential of (VCC-Vtn), the P-channel MOS transistor Qp1603 attains the off state to a higher extent than the off state of the P-channel MOS transistor Qp1602, and the voltage level of the output signal O16 can be rapidly fixed at the "L" level. For example, if VCC is 3V and VPP is 12V, a time required for the fixing is reduced substantially by half. Owing to the rapid fixing of the voltage level, the current consumption can be reduced. A voltage-level shifter of a second embodiment of the invention will now be described below. Fig. 2 shows a circuit structure. I17 indicates an input signal, 017 indicates an output signal, VCC indicates the first voltage source, VPP indicates the second voltage source, and VSS indicates the ground voltage source. 1701 indicates a voltage-level shifter, Qn1701 and Qn1702 indicate N-channel MOS transistors. Qp1701 and Qp1702 indicate P-channel MOS transistors, Qp1703 indicates a P-channel MOS transistor (third P-channel MOS transistor), and N1701 indicates a node name. The circuit structure in Fig. 2 will be described below. In the voltage-level shifter1701, the input signal I17 is connected to the source of the N-channel MOS transistor Qn1701, the gate of the N-channel MOS transistor Qn1702 and the gate of the P-channel MOS transistor Qp1703. The gate of the N-channel MOS transistor Qn1701 is connected to the first voltage source VCC. The source of the N-channel MOS transistor Qn1702 is connected to the ground voltage source VSS. The node 1701 is connected to the drain of the N-channel MOS transistor Qn1701, the drain of the P-channel MOS transistor Qp1701 and the gate of the P-channel MOS transistor Qp1702. The source of the P-channel MOS transistor Qp1701 and the source of the P-channel MOS transistor Qp1702 are connected to the second voltage source VPP. The drain of the P-channel MOS transistor Qp1702 is connected to the source of the P-channel MOS transistor Qp1703. Further, the output signal 017 is connected to the drain of the N-channel MOS transistor Qn1702, the gate of the P-channel MOS transistor Qp1701 and the drain of the P-channel MOS transistor Qp1703. Owing to the provision of the third P-channel MOS transistor Qp1703, an early cut-off circuit 170 is formed. The voltage-level shifter 1701 in Fig. 2 has a feature similar to that of the first embodiment, and more specifically has such a feature that the P-channel MOS transistor Qp1702 is connected between the source of the P-channel MOS transistor Qp1703 and the second voltage source VPP, and the gate of the P-channel MOS transistor Qp1703 receives the input signal I17, so that, when the input signal I17 is at the potential of the first voltage source VCC, and the node N1701 is at the potential of (VCC-Vtn), the P-channel MOS transistor Qp1703 is set to the off state to a higher extent than the off state of the P-channel MOS transistor Qp1702. Thereby, the voltage level of the output signal O17 can be rapidly fixed at the "L" level. In the first and second embodiments, the third P-channel MOS transistors Qp1603 and Qp1703 are connected in series to the second P-channel MOS transistors Qp1602 and Qp1702, respectively. Alternatively, although not shown, the third P-channel MOS transistors Qp1603 and Qp1703 may be connected in series to the first P-channel MOS transistors Qp1601 and Qp1701, respectively, in which case a similar effect can also be achieved. A voltage-level shifter of a third embodiment of the invention will now be described below. The third embodiment corresponds to composition of the first embodiment. Fig. 3 shows a circuit structure. I18 indicates an input signal, 018 indicates an output signal, VCC indicates the first voltage source, VPP indicates the second voltage source, and VSS indicates the ground voltage source. 1801 indicates a voltage-level shifter, Qn1801-Qn1803 indicate N-channel MOS transistors, and Qp1801-Qp1806 indicate P-channel MOS transistors. N1801-N1803 indicate node names. The circuit structure in Fig. 3 will be described below. In the voltage-level shifter 1801, the input signal I18 is connected to the source of the N-channel MOS transistor Qn1801, the gate of the N-channel MOS transistor Qn1802 and the gate of the P-channel MOS transistor Qp1806. The node N1802 is connected to the gate of the N-channel MOS transistor Qn1801, the drain of the P-channel MOS transistor Qp1804 and the drain of the P-channel MOS transistor Qp1805. The source of the N-channel MOS transistor Qn1802 is connected to the ground voltage source VSS, and the sources of the P-channel MOS transistors Qp1801, Qp1803, Qp1805 and Qp1806 are connected to the second voltage source VPP. The source of the P-channel MOS transistor Qp1804 is connected to the first voltage source VCC, and the node N1801 is connected to the drain of the N-channel MOS transistor Qn1801, the drain of the P-channel MOS transistor Qp1801 and the gate of the P-channel MOS transistor Qp1802. The source of the P-channel MOS transistor Qp1802 and the drain of the P-channel MOS transistor Qp1806 are connected together. The output signal O18 is connected to the drain of the N-channel MOS transistor Qn1802, the gate of the P-channel MOS transistor Qp1801, the gate of the P-channel MOS transistor Qp1804, the drain of the P-channel MOS transistor Qp1802, the gate of the P-channel MOS transistor Qp1803 and the gate of the N-channel MOS transistor Qn1803. The node 1803 is connected to the drain of the P-channel MOS transistor Qp1803, the drain of the N-channel MOS transistor Qn1803 and the gate of the P-channel MOS transistor Qp1805. The source of the N-channel MOS transistor Qn1803 is connected to the ground voltage source VSS. In addition to the features of the first embodiment, the voltage-level shifter 1801 of this embodiment has such a feature that the voltage level of the output signal O18 can be fixed further rapidly at the "L" level when the input signal I18 transits from the "L" level to the "H" level. A voltage-level shifter of a fourth embodiment of the invention will now be described below. The fourth embodiment corresponds to the composition of the second embodiment. Fig. 4 shows a circuit structure. I19 indicates an input signal, 019 indicates an output signal, VCC indicates the first voltage source, VPP indicates the second voltage source, and VSS indicates the ground voltage source. 1901 indicates a voltage-level shifter, Qn1901, Qn1902 and Qn1904 indicate N-channel MOS transistors. Qp1901-Qp1903 indicate P-channel MOS transistors. N1901 indicates a node name. The circuit structure in Fig. 4 will be described below. In the voltage-level shifter 1901, the input signal I19 is connected to the source of the N-channel MOS transistor Qn1901, the source of the N-channel MOS transistor Qn1904, the gate of the N-channel MOS transistor Qn1904, the gate of the N-channel MOS transistor Qn1902 and the gate of the P-channel MOS transistor Qp1903. The source of the N-channel MOS transistor Qn1902 is connected to the ground voltage source VSS. The source of the P-channel MOS transistor Qp1901 and the source of the P-channel MOS transistor1902 are connected to the second voltage source VPP. The node N1901 is connected to the drain of the N-channel MOS transistor Qn1901, the drain of the N-channel MOS transistor Qn1904, the drain of the P-channel MOS transistor Qp1901 and the gate of the P-channel MOS transistor Qp1902. The drain of the P-channel MOS transistor Qp1902 and the source of the P-channel MOS transistor Qp1903 are connected together. The output signal 019 is connected to the drain of the N-channel MOS transistor Qn1902, the gate of the P-channel MOS transistor Qp1901, the drain of the P-channel MOS transistor Qp1903 and the gate of the N-channel MOS transistor Qn1901. In addition to the feature of the first embodiment, the voltage-level shifter 1901 of this embodiment has such a feature that the voltage level of the output signal 019 can be fixed further rapidly at the "L" level when the input signal I19 transits from the "L" level to the "H" level. A fifth embodiment of a voltage-level shifter of the invention will be described below. This fifth embodiment is formed of a plurality of voltage-level shifter units. Fig. 5 shows a circuit structure. In the figure, I21 indicates an input signal, 021 indicates an output signal, VCC indicates the first voltage source, VPP indicates the second voltage source, and VSS indicates the ground voltage source. 2111-2113 indicate voltage-level shifter units, 2114 and 2115 indicate NOT circuits (logical circuits), 2101 indicates a voltage-level shifter, Qn2101-Qn2151 indicate N-channel MOS transistors, Qp2111-Qp2151 indicate P-channel MOS transistors, and N2101-N2106 indicate node names. In the voltage-level shifter unit 2111, the P-channel MOS transistor Qp2113 and the N-channel MOS transistor Qn2113 form a potential fixing unit 211. In the voltage-level shifter unit 2112, the P-channel MOS transistor Qp2123 and the N-channel MOS transistor Qn2123 form a potential fixing unit 212. In the voltage-level shifter unit 2113, the P-channel MOS transistor Qp2133 and the N-channel MOS transistor Qn2133 form a potential fixing unit 213. The circuit structure in Fig. 5 will be described below. The voltage-level shifter 2101 is formed of the voltage-level shifter units 2111-2113, the NOT circuits 2114 and 2115 and the MOS transistors. The voltage-level shifter unit 2111 shifts the potential of the first voltage source VCC of the input signal to the voltage level (VPP-2xVtn) of the node N2101, the voltage-level shifter unit 2112 shifts the voltage level (VPP-2xVtn) of the node N2101 to the voltage level (VPP-Vtn) of the node N2102, and the voltage-level shifter unit 2113 shifts the voltage level (VPP-Vtn) of the node N2101 to the second voltage source VPP of the output signal. The circuit structure of the voltage-level shifter units 2111-2113 shown in the figure will now be described below. Since all the voltage-level shifter units 2111-2113 have the same circuit structure, the following description will be given on only the voltage-level shifter unit 2113. The node 2104 supplying the first input signal is connected to the source of the N-channel MOS transistor Qn2131 and the gate of the N-channel MOS transistor Qn2132. The gate of the N-channel MOS transistor Qn2131 is connected to the node 2102 at the voltage level of the first input signal. The node 2106 supplying the second input signal is connected to the gate of the N-channel MOS transistor Qn2133 and the gate of the P-channel MOS transistor Qp2133. The drain of the N-channel MOS transistor Qn2131, the gate of the P-channel MOS transistor Qp2132 and the drain of the P-channel MOS transistor Qp2131 are connected together, and the drain of the P-channel MOS transistor Qp2132 and the source of the P-channel MOS transistor Qp2133 are connected together. The output signal 021 is connected to the drain of the N-channel MOS transistor Qn2133, the drain of the P-channel MOS transistor Qp2133 and the gate of the P-channel MOS transistor Qp2131. The source of the N-channel MOS transistor Qn2132 and the source of the N-channel MOS transistor Qn2133 are connected to the ground voltage source VSS. The source of the P-channel MOS transistor Qp2131 and the source of the P-channel MOS transistor Qp2132 are connected to the second voltage source VPP, i.e., the voltage level of the output signal. The NOT circuits 2114 and 2115 use the first voltage source VCC as their voltage sources. The structure of the voltage-level shifter 2101 will be described below. The node N2102 is a drain of the N-channel MOS transistor Qn2102 of which gate and source are connected to the second voltage source VPP. The node N2101 is a drain of the N-channel MOS transistor Qn2101 of which gate and source are connected to the node N2102. In the voltage-level shifter unit 2111, the input signal I21 is connected for supplying the first and second input signals. The gate of the N-channel MOS transistor Qn2111 is connected to the first voltage source VCC at the voltage level of the input signal. The sources of the P-channel MOS transistors Qp2111 and Qp2112 are connected to the node N2101 at the voltage level of the output signal, and the potential of the node N2103 is output as the output signal. In the NOT circuit 2114, the input signal I21 is connected to supply the input signal, and the potential of the node 2105 is outputted as the output signal. The voltage-level shifter unit 2112 is connected to the input signal I21 for receiving it as the first input signal and is also connected to receive the potential of the node N2105 as the second input signal. The gate of the N-channel MOS transistor Qn2121 is connected to the node 2101 at the potential of the voltage level of the first input signal. The sources of the P-channel MOS transistors Qp2121 and Qp2122 are connected to the node 2102 at the voltage level of the output signal, and the potential of the node 2104 is outputted as the output signal. The NOT circuit 2115 is connected to receive the potential of the node N2105 as the input signal, and is also connected to output the potential of the node N2106 as the output signal. In the voltage-level shifter unit 2113, the node N2104 is connected for receiving the first input signal, the node N2106 is connected for receiving the second input signal, and the gate of the N-channel MOS transistor Qn2131 is connected to the node 2102 at the voltage level of the first input signal. The sources of the P-channel MOS transistors Qp2131 and Qp2132 are connected to the second voltage source VPP at the voltage level of the output signal. Further, the output signal 021 is outputted. Instead of the above circuit structure, the voltage level shifter units 211-2113 in this embodiment may be formed of appropriate composition of the voltage-level shifters of the first to fourth embodiments of the invention. The voltage-level shifter of this embodiment has such a feature that, since the multiple voltage-level shifter units are used to shift the first voltage source VCC of the input signal to the potential of the second voltage source VPP of the output signal forming the output signal through multiple voltage levels, the voltage level of the output signal can be surely fixed even if there is a large potential difference between the first and second voltage sources VCC and VPP. For example, even if the voltage level of the voltage-level shifter unit 2111, i.e., the voltage level of the output signal of the node N2101 is low, and the potential of the node N2103 forming the output signal, i.e., the voltage level at the "H" level is insufficient, the signal at the voltage level of the first voltage source VCC is inputted as the second input signal to the voltage-level shifter unit 2112, whereby the voltage-level shifter 2112 can be surely operated, and the voltage level of the output signal of the voltage level shifter 2101 can be fixed. A sixth embodiment of a voltage-level shifter of the invention will be described below. Fig. 6 shows a circuit structure. This embodiment corresponds to composition of the first embodiment. 2401 indicates a voltage-level shifter, I24 indicates an input signal of the voltage-level shifter 2401, 024 indicates an output signal, VSS indicates the ground voltage source (first voltage source), VCC indicates the second voltage source, VPP indicates a third voltage source, and VBB indicates a fourth voltage source. Qn2400-Qn2402 indicate N-channel MOS transistors, Qn2403 indicates an N-channel MOS transistor (third N-channel MOS transistor), Qp2400-Qp2402 indicate P-channel MOS transistors, Qp2403 indicates a P-channel MOS transistor (third P-channel MOS transistor), and N2401 and N2402 indicate node names. The circuit structure in Fig. 6 will be described below. In the voltage-level shifter 2401, the input signal I24 is connected to the source of the N-channel MOS transistor Qn2400, the source of the P-channel MOS transistor Qp2400, the source of the P-channel MOS transistor Qp2400, the gate of the P-channel MOS transistor Qp2403 and the gate of the N-channel MOS transistor Qn2403. The node N2401 is connected to the drain of the N-channel MOS transistor Qn2400, the drain of the P-channel MOS transistor Qp2401 and the gate of the P-channel MOS transistor Qp2402, and the node N2402 is connected to the drain of the P-channel MOS transistor Qp2400, the drain of the N-channel MOS transistor Qn2401 and the gate of the N-channel MOS transistor Qn2402. The output signal 024 is connected to the gate of the P-channel MOS transistor Qp2401, the drain of the P-channel MOS transistor Qp2402, the gate of the N-channel MOS transistor Qn2401 and the drain of the N-channel MOS transistor Qn2402. The sources of the P-channel MOS transistors Qp2401 and Qp2402 are connected to the third voltage source VPP. The sources of the N-channel MOS transistors Qn2401 and Qm2403 are connected to the fourth voltage source VBB. The source of the P-channel MOS transistor Qp2402 and the drain of the P-channel MOS transistor Qp2403 are connected together, and the source of the N-channel MOS transistor Qn2402 and the drain of the N-channel MOS transistor Qn2403 are connected together. The third P-channel MOS transistor Qp2403 forms a first early cut-off circuit 251, and the third N-channel MOS transistor Qn2403 forms a second early cut-off circuit 252. The voltage-level shifter circuit 2401 operates to shift the input signal of the amplitudes of the ground voltage source (first voltage source) VSS and the second voltage source VCC to the amplitudes of the third voltage source VPP and the fourth voltage source VBB. Owing to the provision of the P-channel MOS transistor Qp2403 and the N-channel MOS transistor Qn2403, the output signal 024 can be set rapidly to the potential of the voltage source VPP or VBB. A seventh embodiment of a voltage-level shifter of the invention will be described below. Fig. 7 shows a circuit structure. This embodiment corresponds to composition of the second embodiment. In the figure, 2501 indicates a voltage-level shifter, I25 indicates an input signal of the voltage-level shifter 2501, 025 indicates an output signal, VCC indicates the first voltage source, VPP indicates the second voltage source, VSS indicates the ground voltage source, and VBB indicates a third voltage source. Qn2500-Qn2502 indicate N-channel MOS transistors, Qn2503 indicates an N-channel MOS transistor (third N-channel MOS transistor), Qp2500-Qp2502 indicate P-channel MOS transistors, Qp2503 indicates a P-channel MOS transistor (third P-channel MOS transistor), and N2501 and N2502 indicate node names. The circuit structure in Fig. 7 is similar to that of the sixth embodiment except for that the P-channel MOS transistors Qp2402 and Qp2403 are connected in series in the opposite order, and the N-channel MOS transistors Qn2402 and Qn2403 are connected in series in the opposite order. The third P-channel MOS transistor Qp2503 forms a first early cut-off circuit 261, and the third N-channel MOS transistor Qn2503 forms a second early cut-off circuit 262. The voltage level converter circuit 2501 functions similarly to the sixth embodiment, and specifically operates to shift the input signal of amplitudes of the ground voltage source VSS and the second voltage source VCC to the amplitude of the third voltage source VPP and the fourth voltage source VBB. Owing to the provision of the P-channel MOS transistor Qp2503 and the N-channel MOS transistor Qn2503, the output signal 025 can be set rapidly to the potential of the voltage source VPP or VBB. An eighth embodiment of a voltage-level shifter of the invention will be described below. Fig. 8 shows a circuit structure. In the voltage-level shifter of this embodiment, there are provided first, second and third voltage sources, the input signal is inputted with the voltages of the first and second voltage sources, the output signal is outputted with the voltages of the second and third voltage sources, and the voltage of the second voltage source is intermediate the voltages of the first and second voltage sources. 2601 indicates a voltage-level shifter, 2610 indicates a NOT circuit, I26 indicates an input signal of the voltage-level shifter 2601, 025 indicates an output signal of the NOT circuit 2610, VCC indicates the first voltage source, VSS indicates the ground voltage source, and VBB indicates the second voltage source. Qn2601-Qn2610 indicate N-channel MOS transistors, Qp2601-Qp2610 indicate P-channel MOS transistors, and N2601 and N2602 indicate node names. The circuit structure in Fig. 8 will be described below. In the voltage-level shifter 2601, the input signal I26 is connected to the source of the P-channel MOS transistor Qp2601, the gate of the P-channel MOS transistor Qp2602 and the gate of the N-channel MOS transistor Qn2603. The node 2601 is connected to the drain of the transistor Qn2603. The node 2601 is connected to the drain of the P-channel MOS transistor Qp2601, the drain of the N-channel MOS transistor Qn2601 and the gate of the P-channel MOS transistor Qp2602. The node 2602 is connected to the drain of the P-channel MOS transistor Qp2602, the drain of the N-channel MOS transistor Qn2602 and the gate of the N-channel MOS transistor Qn2601. The source of the P-channel MOS transistor Qp2602 is connected to the second voltage source VPP. The sources of the N-channel MOS transistors Qn2601 and Qn2602 are connected to the third voltage source VBB. The source of the N-channel MOS transistor Qn2602 and the drain of the N-channel MOS transistor Qn2603 are connected together. The NOT circuit 2610, which is formed of the P-channel MOS transistor Qp2610 and the N-channel MOS transistor Qn2610, receives the input signal from the node N2602 and outputs the signal 026. In the NOT circuit 2610, the source of the P-channel MOS transistor Qp2610 is connected to the ground voltage source VSS, and the source of the N-channel MOS transistor Qn2610 is connected to the third voltage source VBB. As shown in an operation timing diagram of Fig. 8, the voltage-level shifter of the eighth embodiment shifts the input signal of the amplitudes of the first voltage source VCC and the ground voltage source VSS to the amplitudes of the ground. A ninth embodiment of a voltage-level shifter of the invention will be described below. Fig. 10 shows a circuit structure. In this embodiment, there are provided first, second and third voltage sources VSS, VCC and VPP, the input signal is inputted with voltages of the first and second voltage sources VSS and VCC, the output signal is outputted with voltages of the third and second voltage sources VPP and VCC, and the voltage of the third voltage source VPP is higher than the voltage of the second voltage source VCC. In Fig. 10, 1701 indicates a voltage-level shifter, 2810 indicates a NOT circuit, I28 indicates the input signal of the voltage-level shifter 2801, 017 indicates the output signal of the voltage-level shifter 1701 which is also used as the input signal of the NOT circuit 2810. 028 indicates the output signal of the- NOT circuit 2810. VSS indicates the ground voltage source (first voltage source), VCC indicates the second voltage source, and VPP indicates the third voltage source. Qn2801-Qn2810 indicate N-channel MOS transistors, Qp2801-Qp2810 indicate P-channel MOS transistors, and N1701 indicates a node name. The circuit structure in Fig. 10 will be described below. The voltage-level shifter 1701 is the same as that in the second embodiment. The NOT circuit 2810, which is formed of the P-channel MOS transistor Qp2810 and the N-channel MOS transistor Qn2810, receives the signal 017, and outputs the signal 028. In the NOT circuit 2810, the source of the P-channel MOS transistor Qp2810 is connected to the third voltage source VPP, and the source of the N-channel MOS transistor Qn2810 is connected to the second voltage source VCC. As shown in an operation timing diagram of Fig. 11, the voltage-level shifter of the ninth embodiment shifts the input signal of the amplitudes of the second voltage source VCC and the ground voltage source VSS to the amplitudes of the third voltage source VPP and the second voltage source VCC. The embodiments described above are merely examples, and the invention as defined in the Claims, may be applied to combinations of two or more of these embodiment and other circuits.

Claims: A voltage-level shifter comprising: a pass gate circuit (Qn1601) for passing an input signal (I16); said level shifter (1601) using as its power source a voltage source (VPP) supplying a potential higher than a potential of said input signal (I16) sent to said pass gate circuit (Qn1601); said level shifter including first and second MOS transistors (Qp1601, Qp1602) of the same conductivity type, first and second MOS switch elements (Qn1601, Qn1602) of a conductivity type opposite to that of said first and second MOS transistors (Qp1601, Qp1602); said first MOS transistor (Qp1601) having a source connected to said voltage source (VPP); said first MOS transistor (Qp1601) having a drain connected to a gate of said second MOS transistor (Qp1602) and to said first MOS switch element (Qn1601); said second MOS transistor (Qp1602) having a drain connected to a gate of said first MOS transistor (Qp1601) and to said second MOS switch element (Qn1602); said first MOS switch element (Qn1601) being operable to supply the input signal (I16) to the gate of said second MOS transistor (Qp1602); said second MOS switch element (Qn1602) being grounded; said second MOS switch element (Qn1602) being controlled by said input signal (I16) sent to said pass gate circuit (Qn1601), and said second MOS transistor (Qp1602) being controlled by said output signal of said pass gate circuit (Qn1601); the potential of the drain of said second MOS transistor (Qp1602) being the output signal (O16) of said level shifter; characterized in that said level shifter (1601) includes early cut-off circuit (160) being disposed between said voltage source (VPP) and the source of said second MOS transistor (Qp1602), and being turned off at a timing earlier than an off timing of said second MOS transistor when said input signal sent to said signal inverter circuit transits from the "L" level to the "H" level. A voltage-level shifter comprising: a pass gate circuit (Qn1701) for passing an input signal (117); said level shifter (1701) using as its power source a voltage source (VPP) supplying a potential higher than a potential of said input signal (I17) sent to said pass gate circuit (Qn1701); said level shifter including first and second MOS transistors (Qp1701, Qp1702) of the same conductivity type, first and second MOS switch elements (Qn1701, Qn1702) of a conductivity type opposite to that of said first and second MOS transistors (Qp1701, Qp1702); both of said MOS transistors (Qp1701, Qp1702) having a source connected to said voltage source (VPP); said first MOS transistor (Qp1701) having a drain connected to a gate of said second MOS transistor (Qp1702) and to said first MOS switch element (On1701); said first MOS switch element (Qn1701) being operable to supply the input signal (I17) to the gate of said second MOS transistor (Qp1702); said second MOS switch element (Qn1702) being grounded; said second MOS switch element (Qn1702) being controlled by said input signal (I17) sent to said pass gate circuit (Qn1701), and said second MOS transistor (Qp1702) being controlled by said output signal of said pass gate circuit (Qn1701); the potential of the drain of said second MOS transistor (Qp1702) being the output signal (O17) of said level shifter; characterized in that said level shifter (1701) includes early cut-off circuit (170) being disposed between the drain of said second MOS transistor (Qp1702) and said second MOS switch element (Qn1702) and being turned off at a timing earlier than an off timing of said second MOS transistor when said input signal sent to said signal inverter circuit transits from the "L" level to the "H" level. A voltage-level shifter comprising: a pass gate circuit (Qn1601) for passing an input signal (I16); said level shifter (1601) using as its power source a voltage source (VPP) supplying a potential higher than a potential of said input signal (I16) sent to said pass gate circuit (Qn1601); said level shifter including first and second MOS transistors (Qp1601, Qp1602) of the same conductivity type, first and second MOS switch elements (Qn1601, Qn1602) of a conductivity type opposite to that of said first and second MOS transistors (Qp1601, Qp1602); said second MOS transistors (Qp1602) having a source connected to said voltage source (VPP); said first MOS transistor (Qp1601) having a drain connected to a gate of said second MOS transistor (Qp1602) and to said first MOS switch element (Qn1601); said second MOS transistor (Qp1602) having a drain connected to a gate of said first MOS transistor (Qp1601) and to said second MOS switch element (Qn1602); said first MOS switch element (Qn1601) being operable to supply the input signal (I16) to the gate of said second MOS transistor (Qp1602); said second MOS switch element (Qn1602) being grounded; said second MOS switch element (Qn1602) being controlled by said input signal (I16) sent to said pass gate circuit (Qn1601), and said second MOS transistor (Qp1602) being controlled by said output signal of said pass gate circuit (Qn1601); the potential of the drain of said second MOS transistor (Qp1602) being the output signal (O16) of said level shifter; characterized in that said level shifter (1601) includes early cut-off circuit (160) being disposed between said voltage source (VPP) and the source of said first MOS transistor (Qp1601), and being turned off at a timing earlier than an off timing of said second MOS transistor when said input signal sent to said signal inverter circuit transits from the "L" level to the "H" level. A voltage-level shifter comprising: a pass gate circuit (Qn1701) for passing an input signal (I17); said level shifter (1701) using as its power source a voltage source (VPP) supplying a potential higher than a potential of said input signal (I17) sent to said pass gate circuit (Qn1701); said level shifter including first and second MOS transistors (Qp1701, Qp1702) of the same conductivity type, first and second MOS switch elements (Qn1701, Qn1702) of a conductivity type opposite to that of said first and second MOS transistors (Qp1601, Qp1602); both of said MOS transistors (Qp1701, Qp1702) having a source connected to said voltage source (VPP); said second MOS transistor (Qp1702) having a drain connected to said second MOS switch element (Qn1702); said first MOS switch element (Qn1701) being operable to supply the input signal (I16) to the gate of said second MOS transistor (Qp1702); said second MOS switch element (Qn1702) being grounded; said second MOS switch element (Qn1702) being controlled by said input signal (I17) sent to said pass gate circuit (Qn1701), and said second MOS transistor (Qp1702) being controlled by said output signal of said pass gate circuit (Qn1701); the potential of the drain of said second MOS transistor (Qp1702) being the output signal (O17) of said level shifter; characterized in that said level shifter (1701) includes early cut-off circuit (160) being disposed between the drain of said first MOS transistor (Qp1701) and the gate of said second MOS transistor (Qp1702), and being turned off at a timing earlier than an off timing of said second MOS transistor when said input signal sent to said signal inverter circuit transits from the "L" level to the "H" level. The voltage-level shifter according to anyone of claims 1-4, wherein said first MOS switch element (Qn1601) receives on its source the input signal (I16) sent to said pass gate circuit, and serves also as said signal pass circuit. The voltage-level shifter according to claim 5, wherein each of said first and second MOS transistors (Qp1601, Qp1602; Qp1701, Qp1702) is formed of a P-channel MOS transistor, and each of said first and second MOS switch elements (Qn1601, Qn1602; Qn1701, Qn1702) is formed of an N-channel MOS transistor. The voltage-level shifter according to claim 6, wherein said early cut-off circuit (160; 170) includes a P-channel MOS transistor (Qp1603; Qp1703), and said P-channel MOS transistor (Qp1603; Qp1703) receives on its gate the input signal sent to said pass gate circuit (Qn1601). The voltage-level shifter according to anyone of claims 1-4, further comprising a NOT circuit (2810) producing a NOT signal of the output signal (O17) of said level shifter; and said NOT circuit (2810) uses as its power sources a second voltage source (VCC) of a potential not lower than a potential of the voltage source of the input signal (I17) sent to said pass gate circuit (Qn1701) and a third voltage source (VPP) of a potential higher than the potential of said second voltage source (VCC), and is operable to output a signal of the potential of said third voltage source (VPP) when the output signal (O17) of said level shifter is at the "L" level.

Inventors: HIRANO HIROSHIGE, HIRANO, HIROSHIGE
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1995
Main classification: H03K19
IPC codes: H03K19