A thin-film transistor and method for forming the same

Abstract: A transistor is formed on a substrate of dielectric material. The transistor includes a layer of semiconductor material that is formed on the substrate and has a source region and a drain region. The layer also has a channel region that is in a recess of the substrate and adjacent to the source and drain regions. The channel is self-aligned, as are the light doped source and drain regions.

Description: The present invention relates generally to semiconductor devices and more specifically to a transistor formed from a film of semiconductor material on a dielectric substrate for use in an SRAM memory cell. Thin-film transistors (TFTs) are often used to produce integrated circuits having reduced areas. For example, a TFT may be used as the P-channel transistor in a six 6-transistor static random access memory (SRAM) cell. A P-channel polysilicon transistor in a six transistor SRAM cell is well known in the prior art, see U.S. Patent No. 5,135,888; 5,187,114; and 5,204,279; each of which are incorporated herein by reference. Typically, a TFT is a field-effect transistor (FET) having its channel, drain, and source regions formed from a strip of semiconductor material, such as polysilicon, that has been formed on a dielectric substrate, such as SiO 2 , quartz or glass. Thus. unlike a conventional FET that is formed in a semiconductor substrate, a TFT may be formed in a stacked arrangement, above a semiconductor structure, such as the other transistors in an SRAM cell. Such stacking of integrated-circuit components often provides a significant reduction in the area of the integrated circuit. Murakami et al. teach a stacked transistor SRAM cell in their article titled "A 21 mW CMOS SRAM for Battery Operation," ISSCC, pg. 46 (1991) presented on behalf of Mitsubishi Electric. However, a TFT is often larger than its single-crystal counterparts, i.e., transistors in a single-crystal semiconductor subsrate. Additionally, the switching speed of a TFT is often too slow for certain applications. European patent application EP-A-0401577 discloses a semiconductor transistor having a semiconductor-on-insulator structure and comprising a layer of semiconductor on an insulator substrate, source and drain regions formed in the semiconductor layer, a channel region also formed in the semiconductor layer between the source and drain regions, and a gate electrode in correspondence to the channel region and insulated from the channel region by a gate insulator film. French Patent Application FR-A-2698210 corresponding to the preamble of claim 1 discloses a Thin Film Transistor (TFT) structure having an insulator substrate with a recess formed therein and the channel region of the TFT formed within the recess. European Patent Application EP-A-0578926 discloses a Thin Film Transistor formed by forming an opening in a dielectric layer overlying a substrate and forming a semiconductor sidewall spacer around the perimeter of the opening, the sidewall spacer acting as the channel region of the transistor. A control electrode is formed substantially in the opening, insulated from the sidewall spacer by a dielectric layer. According to the present invention there is provided a semiconductor structure comprising a dielectric substrate having a surface and having a recess formed therein, characterised in that a layer of semiconductor material is positioned on said surface and in said recess and has within said recess a channel region, said layer of semiconductor material also having source and drain, regions; a gate electrode formed overlying said surface and having an end portion extending over only a portion of said recess to overlap said channel region; and an insulator positioned between said channel region and said end portion of said gate electrode. According to the present invention there is also provided a method for forming a transistor, comprising forming a recess in a dielectric substrate such that said recess and a surface of said substrate are contiguous, characterised by forming a gate electrode on said surface of said dielectric substrate, said gate electrode having an end portion that extends over only a portion of said recess; forming an insulator on exposed portions of said gate electrode; forming a layer of semiconductor material on said surface and in said recess such that said gate electrode overlays said semiconductor layer; forming a channel region in said semiconductor material within said recess; and forming drain and source regions in said semiconductor material adjacent opposing ends of said channel to provide a transistor. Thus, a transistor is formed on a dielectric layer. The dielectric layer is preferably an oxide layer overlaying integrated circuit elements in a silicon substrate. Preferably, the channel region is within a recess of the substrate, below the surface. A gate electrode is in substantial alignment with the channel. Because the gate electrode and the channel are self-aligned, the channel length can be precisely formed and is less than gate electrode width and twice the insulator thickness. Preferably, the source region includes lightly doped source and drain regions that are adjacent to the channels that are automatically formed without additional process steps and with one less step that is normally required in the prior art. One advantage of the invention is that the transistor is smaller than existing TFTs. Another advantage is that it is easier to manufacture than existing TFTs. Some embodiments of the invention will now be described by way of example and with reference to the accompanying drawings in which: Figure 1 is a cut-away end view of a semiconductor structure formed according to the present invention. Figure 2 is a top view of a portion of the structure of Figure 1. Figure 3 is a cut-away side view of the structure of Figure 2 taken along lines A-A of Figure 2. Figure 4 is a top view of a semiconductor structure that has been etched. Figure 5 is a cut-away end view of the structure of Figure 4 taken along lines B-B of Figure 4. Figure 6 is the structure of Figure 5 after a dielectric and a semiconductor layer have been formed. Figure 7 is a view of the structure of Figure 6 taken along lines positioned at C-C of Figure 4. Figure 8 is a top view of the structure of Figure 7 with a mask layer in place and after an etch step. Figure 9 is a partial cross-sectional view of Figure 8, taken along lines C-C. Figure 10 is an end view of the structure of Figure 9 taken along lines C-C of Figure 4. Figure 11 is a view of the structure of Figure 10 after the removal of the mask layer and the addition of a dielectric layer. Figure 1 is a cut-away cross-sectional view of a semiconductor structure 10, which in the illustrated embodiment includes a thin-film transistor (TFT) 11. As shown, TFT 11 has a channel region 12 that has a length L and is self-aligned with the gate electrode 14. That is, channel region 12 has substantially the same length as the width w of gate electrode 14. Such self-alignment both reduces the size of TFT 11 over existing TFTs, and reduces parasitic capacitances, such as the Miller capacitance, that may be caused by gate electrode 14 extensively overlapping the source and drain regions 18 and 20, as may occur in existing devices. Thus, self-alignment of gate electrode 14 and channel region 12, as incorporated into the structure of the polysilicon transistor of the present invention, reduces the size of TFT 11. As shown, TFT 11 is formed on a substrate 22, which is typically formed from a dielectric material, such as SiO 2 , a glass layer, or quartz. A layer 24 of semiconductor material, typically polysilicon, is formed over substrate 22 and includes channel region 12 and drain and source regions 18 and 20. An insulating dielectric layer 26 may be formed above the polysilicon layer 24 to insulate polysilicon layer 24 from later layers, such as a gate-electrode contact 28. In one aspect of the invention, source region 18 may include a lightly doped source region 30 and drain region 20 may include a lightly doped drain region 32. These LDD regions are formed in a single implant step with the drain and source regions according to one embodiment of the present invention, as explained herein. In one embodiment of the invention, semiconductor structure 10, which includes TFT 11 and substrate 22, may be formed over a SRAM cell 34. In such an embodiment, the TFT 11 is the P-channel device for a six transistor SRAM cell. By forming TFT 11 vertically above rather than in the substrate with other transistors in the SRAM cell, the area of the SRAM cell may be greatly reduced over existing cells that use P-channel transistor devices that are formed on the same horizontal plane as the SRAM cell. This P-channel transistor may directly replace the P-channel transistors of current six-T SRAM design, such as those previously cited herein and provide an overall smaller area memory cell size than these prior art devices. Figure 2 is a top view of the semiconductor structure 10 of Figure 1. For clarity, contact 28 and insulating layer 26 are omitted from Figure 2. This shows the polysilicon layer 24 having the source/drain 18 and 20 and the channel 12 formed therein. The gate 14 overlays the channel region 12. Figure 3 shows a cut-away side view of semiconductor structure 10 taken along lines A-A of Figure 2. Again for clarity, insulator 26 and contact 28 are omitted from Figure 3. As shown, channel region 12 is formed in a portion of recess 36 in substrate 22. An oxide layer 38 is formed between channel 12 and the gate electrode 14. A portion 39 of the recess 36 does not have a channel region therein. As shown, a portion 41 of gate electrode 14 extends beyond an edge 41 over the recess 36 to overlay and be contiguous with channel region 12. This portion 39 is filled with the same polysilicon layer 24 in one embodiment, but because of its spacing from the gate electrode 14, it does not effectively function as a part of channel region 12. Alternatively, the portion 39 may be void or filled with an insulating structure such as SiO 2 or the like. Figures 4-11 together illustrate a method for forming semiconductor 10, which includes TFT 11 formed on substrate 22. For clarity, SRAM 34 is not shown, it being understood that structure 10 may be formed over SRAM 34 or may be formed independently thereof, the design rules and SRAM cell layout being design choices by those of skill in the art of the many possible choices. Referring to Figure 4, after the formation of dielectric substrate 22 usually formed of an SiO 2 layer over a silicon substrate, gate electrode 14 is formed thereon. In one aspect of the invention, a film of polysilicon having a thickness of approximately 0.5 µm is deposited upon substrate 22 by a low-pressure chemical vapor deposition (LPCVD). The polysilicon film is then doped according to existing methods to become more conductive. For example, the polysilicon film may be doped N+. After the film is doped, it is formed into a gate electrode 14 using existing photolithographic techniques. In one aspect of the invention, width W is approximately 4λ, where λ is the minimum process dimension. Next, a mask layer 60, which in one embodiment of the invention is a layer of photoresist film, is deposited over strips 14. An opening 62 is formed in layer 60 such that it provides an opening over an end portion of the strip 14. Next, the exposed regions of substrate 22 are isotropically etched to give an undercut region as shown by dotted line 64. For example, where substrate 22 is SiO 2 , this isotropic etch is performed using an aqueous solution of dilute hydrogen fluoride (HF), such as buffered oxide etch (BOE), and is continued until the exposed regions of substrate 22 are etched to a desired depth r. In one embodiment, this depth r is approximately λ, though any depth that gives suitable etching below the poly gate electrode 14 to provide an undercut is acceptable. It may, for example, be approximately .5 µm or, in the case illustrated where w = 4λ, to a depth of approximately 1λ to provide an undercut distance d of approximately λ, as shown in Figures 5 and 9. Alternatively, d could be smaller, such as λ/2 if desired. Figure 5 shows a view of the structure of Figure 4 taken along lines B-B. As shown in Figure 5, the structure includes photoresist 60, strip 14, and recess 36, which has been formed by the isotropic etch described above in conjunction with Figure 4. The etch produces an undercut of distance d under the gate electrode 14. Next, referring to Figure 6, photoresist 60 is removed according to existing techniques and gate insulator 16 is formed. The gate insulator is formed by any acceptable technique. In one aspect of the invention, gate insulator 16 is an oxide that is grown in dry O 2 over the exposed surface portions of strip 14, or other thermal oxidation techniques, as are known. Gate oxide 16 may have a thickness in a range of approximately 100-500 Å. The oxide 16 is formed on all exposed portions of the gate electrode in a single step. The oxide layer on the top of the gate electrode 14, on the sidewalls, and on the bottom, are all formed simultaneously. A process advantage is obtained by forming a gate sidewall oxide in the same step as the top oxide layer and the lower gate oxide on the bottom side of the gate electrode. Still referring to Figure 6, a semiconductor film 66 is formed on insulator 16 and on the exposed surface regions of substrate 22, including those within recess 36. In one aspect of the invention, semiconductor film 66 is formed from a layer of amorphous silicon that is deposited over substrate 22 and insulator 16 to a thickness of approximately 7,000 Å. Alternatively, the layer 66 is polysilicon of a suitable thickness. A variety of techniques for forming amorphous silicon and polysilicon are known in the art and any suitable techniques may be used as selected by the process designs as being compatible with the process. Figure 7 is a view of the structure of Figure 6 taken along lines C-C of Figure 4. As shown, the gate electrode 14 extends over the recess 36 to overlay a portion of film 66 that is within recess 36. This will later form the channel region 12 of the transistor. Referring to Figure 8, a second mask layer 68 is formed over film 66 to permit etching of strip 24 using standard, existing photolithographic process. The photoresist 68 is partially removed to create an aperture 69 and leave a layer 68 on top of the portions of the semiconductor layer 66 that will become the source and drain region of the semiconductor strip 24. Next, the exposed portions of semiconductor film 66 are anisotropically etched to form channel region 12 in recess 36 as shown in Figure 9. In one aspect of the invention, the exposed portions of film 66 are etched using an ion-assisted plasma etching process. Where the resulting TFT 11 is to be used as a load device, channel 12 should be made to provide a sufficiently high resistance when TFT 11 is in an off state, i.e., when channel region 12 is in a nonconductive state. In the embodiment in which the device 11 is used as an active P-channel transistor in a six-T SRAM cell, the off-resistance is extremely high, at or above the teraohm 50 range, that from a practical circuit view it approaches infinity and the on-resistance is quite high, usually in the mega-ohm or higher range. As a P-channel transistor, it does switch on, but is not designed to be a high current carrying member when on; rather, it is designed to be conductive but to have a very low current, because of a very high channel resistivity when on. Figure 9 shows the device partially formed with the channel region 12 having a dimension d corresponding to the undercut depth d and a total maximum height equal to the depth r of recess 36. The channel region 12 is thus a narrow strip having a length L approximately equal to width of the gate electrode 14, a depth that can be, at maximum, the depth of the recess 36, and thickness that is, at maximum, the undercut distance d. The distance d and recess depth r may be less than the minimum feature size λ because they are formed from etch steps and undercut etches, not by standard photolithographic techniques. The channel 12 can thus be very small in these critical dimensions, as compared to prior art devices, and yet the forming steps insure that the channel 12 itself will not be overetched or discontinuities occur because the poly layer 14 protects the channel 12 from an anisotropic etch. Overetching of the film 24 will not risk harming the channel 12 because it is under the overhang 41 of the gate electrode 14. This can produce significant advantages in the process control steps not possible with prior art polysilicon film transistors, particularly if the end use is for an SRAM. Figure 10 is as view of the structure of Figure 8 taken along line C-C of Figure 4 after the above-described anisotropic etching process. After channel region 12 has been formed, it is ion-implanted to adjust the threshold voltage and form the desired type of device, i.e., either P-channel or N-channel. For example, in one aspect of the invention, a P-channel device is formed by phosphorous-ion implanting channel 12 in a range of approximately 10 12 atoms/cm 2 . The energy of this ion implant is selected such that it can penetrate the overlying strip 14. An adequate implant energy for this is approximately 300 KeV. Alternately, one may use a much lower energy and ion implant channel 12 at an angle, such as by using a rotating wafer technique or another equivalent technique that will provide access to the exposed boundary or edge 37 (Figure 3) of channel region 12. By having the same mask in place for both the etch of the channel region 12 and the implant of the channel, self-alignment of the channel is obtained. Alternatively, one could remove the photoresistor 68 and perform a blanket implant of a light dose of a first conductivity type and overcome this by counter doping the source and drain regions. Still referring to Figure 10, after the implant of dopants into the channel region 12, photoresist layer 68 is removed according to existing techniques and if the layer 66 is amorphous silicon, it is crystallized, i.e., converted into polysilicon strip 24 (Figure 1). In one aspect of the invention, layer 66 is exposed to a long, low temperature anneal in N 2 or Ar in order to convert the amorphous silicon into strip 24 of large grained polysilicon. Such an anneal is typically performed within a temperature of approximately 475-600°C for a time period in a range of approximately 20-100 hours. The anneal temperature should be low enough so that additional nucleation sites or small crystals are not generated in the amorphous silicon, but high enough so that existing crystallites may grow through solid state diffusion to produce grain sizes of approximately 5 µm and larger. Alternatively, layer 66 may be converted into strip 24 of large grain polysilicon using existing laser techniques. It is known that larger crystal grains within polysilicon layer 24 often produce improved TFTs, because larger grains reduce the number of charges that may be stored at carrier traps, which are primarily located at the grain boundaries. Alternatively, the layer 24 can be formed initially of acceptable polysilicon and the process continue without need for a long-term anneal. Referring to Figure 11, an oxide 72 is formed over the exposed portions of strip 24. In one aspect of the invention, the Figure 11 structure is lightly oxidized in steam at a temperature of approximately 850°C to grow a layer 72 of silicon dioxide that is approximately 200 Å thick. Next, structure 10 is blanket ion implanted to form drain and source regions 20 and 18. In one aspect of the invention, where TFT 11 is to be a P-channel device, structure 10 is ion implanted with boron using a dose of approximately 10 15 atoms/cm 2 at an energy of approximately 150 KeV or possibly an even higher dose. Such an implant is made in an substantially perpendicular direction to the surface of structure 10, as shown by the multiple arrows in Figure 11. Furthermore, such an implant provides a sufficient heavy dopant concentration for good conductivity in the portions of source 18 and drain 20 outside lightly doped regions 30 and 32 an impurity concentration of approximately 10 19 atoms/cm 3 . Immediately after the implant process, very little boron is present in LDD regions 30 and 32. This is because it has a larger volume and also because it is protected in part from the thickness of the poly two layer, the poly one layer and the sidewalls of the gate oxide 16. Structure 10 is then submitted to a heat treatment of approximately 1 hr in a temperature range between 900-925°C to drive a light concentration of the implanted boron into regions 30 and 32 such that near the boundaries with channel region 12 (which in this aspect of the invention is doped N-) the impurity concentration is in the range to 10 17 -10 18 atoms/cm 3 or even less in some embodiments. Such a heat treatment forms LDD regions 30 and 32 of the P- type. Alternatively, RTA methods may be used for the boron drive-in step. The lightly doped source and drain regions are advantageously created without an additional ion implant step. This is possible because, among other things, the layer 24 is thicker at the source/drain regions immediately adjacent the channel and also because the source/drain regions are much deeper adjacent the channel, the channel 12 being in a recess below the surface. Thus, for the same implant dose, the ions are spread over a larger volume when diffused and the final impurity concentration is less. Further, for an ion dose at the surface, the ions diffuse downward. The deeper regions of the poly layer 24 can have a lower final concentration of dopants by selective control of the thermal steps occurring after the ion implant, taking into account the impurities' diffusion characteristics. This is to be compared to prior art LDD structures that have the channel at the surface and the same volume in the source/drain regions near the channel as spaced from the channel. Such prior art devices require a separate ion implant step to create the LDD structures, but, according to this invention, the LDD structure is self-created. The source/drain and LDD structure are automatically self-aligned to the channel 12 because the poly one layer 14 and gate oxide 16 having sidewalls surrounding this layer will act as a self-aligning edge stop to the ion implant that, when diffused, creates the LDD structure. The oxide sidewalls provide a stop for the vertical ion dose implant, being a good mask edge and the gate oxide prevents later diffusions from placing excessive counter dopants in respective polysilicon layers. While one embodiment relies on both increased volume and greater depth of the channel to self-create the LDD structures, either could be present alone and be useful to achieve this purpose. The self-alignment of the LDD structure is also attainable by use of either of these techniques alone, or in combination. Still referring to Figure 11, TFT 11 may be hydrogen passivated to reduce the trap density at the grain boundaries within layer 24. Such a reduction often reduces the threshold voltage and subthreshold leakage currents. This hydrogen passivation may be performed using a long bake in forming gas or hydrogen (H), applying plasma etch chemical vapor deposition (PECVD) silicon nitrite layers, immersing structure 10 in a hydrogen plasma at a temperature of approximately 300°C, or by high dose ion implantation with protons. Still referring to Figure 11, in one aspect of the invention the ratio of the width to the length (W/L) of channel region 12 is approximately equal to λ ÷ 2λ = ½. TFT 11 may now be completed and integrated with other devices by adding appropriate insulating layers, contacts, vias and metal films, as is known in the art, a final product being shown in Figure 1. From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims. Although a method for forming a P-channel TFT 11 is disclosed, one may form TFT 11 as an N-channel without departing from the spirit and scope of the invention. While gate electrode 14 and film 66 have been described as poly one and poly two, this does not require a particular sequence of these two layers, unless the claims so specify. Further, the layers may be poly two, three or four, the particular level of polysilicon not being critical to the invention. Additionally, strip 14, which forms the gate electrode of TFT 11, may be formed from an electrically conductive material other than polysilicon.

Claims: A semiconductor structure comprising: a dielectric substrate (22) having a surface and having a recess (36) formed therein, characterised in that ; a layer of semiconductor material (24) is positioned on said surface and in said recess (36) and has within said recess a channel region (12), said layer of semiconductor material (24) also having source and drain regions (18, 20); a gate electrode (14) formed overlying said surface and having an end portion (41) extending over only a portion of said recess (36) to overlap said channel region (12); and an insulator (16) positioned between said channel region (12) and said end portion (41) of said gate electrode (14). The structure of claim 1 wherein a portion of said source region (18) and a portion of said drain region (20) are within said recess (36) and a portion of each are on said surface of said the dielectric substrate (22) outside of said recess (36). The structure of claims 1 or 2 wherein said source region (18) includes a lightly doped source region (30) adjacent said channel (12) and a further source region spaced from said channel, and wherein said drain region comprises a lightly doped drain region (32) adjacent said channel (12) and a further drain region spaced from said channel. The structure of claim 3 wherein at least a portion of said lightly doped source region (30) and a portion of said lightly doped drain region (32) are within said recess (36). The structure of claims 1 or 2 wherein said gate electrode (14) has a pair of opposing sidewalls having an oxide layer thereon, wherein a portion of said source region (18) is adjacent a first of said sidewalls and a portion of said drain region (20) is adjacent a second of said sidewalls, and wherein said insulator (16) separates said source region (18) from said first sidewall and separates said drain region (20) from said second sidewall. The structure of claim 5 wherein said source region (18) comprises a lightly doped source region (30) adjacent said channel (12) and said first sidewall and a further source region spaced from said channel, and wherein said drain region (20) comprises a lightly doped drain region (32) adjacent said channel (12) and said second sidewall and a further drain region spaced from said channel. The structure according to any of claims 3, 4 or 6 in which the lightly doped source and drain regions (30, 32) immediately adjacent the channel (12) have a greater volume than the further source and drain regions (18,20) spaced from the channel (12). The structure according to any preceding claim wherein said layer of semiconductor (24) overlays a portion of said gate electrode (14), is adjacent said gate electrode (14) and underlies said end portion (48) of said gate electrode (14). The structure according to any preceding claim wherein said insulating layer (16) overlies two sidewall portions, a top wall portion, and a bottom wall portion of said gate electrode (14). A method for forming a transistor, comprising: forming a recess (36) in a dielectric substrate (22) such that said recess (36) and a surface of said substrate are contiguous, characterised by forming a gate electrode (14) on said surface- of said dielectric substrate (22), said gate electrode having an end portion (41) that extends over only a portion of said recess (36); forming an insulator (16) on exposed portions of said gate electrode (14) ; forming a layer of semiconductor material (24) on said surface and in said recess (36) such that said gate electrode (14) overlays said layer of semiconductor material (24) ; forming a channel region (12) in said semiconductor material within said recess (36); and forming drain and source regions (18, 20) in said semiconductor material (24) adjacent opposing ends of said channel (12) to provide a transistor. The method of claim 10 wherein said step of forming said gate electrode (14) comprises: depositing a film of polysilicon on said surface; forming a mask layer over said film; etching exposed portions of said film to form said gate electrode (14); and removing said mask layer. The method of claims 10 or 11 wherein said step of forming a recess (36) comprises: forming after the gate electrode (14) is formed, a mask layer (60) that exposes said end portion (41) of said gate electrode (14) and an area of said substrate surface adjacent said end portion; and isotropically etching the exposed substrate area so as to undercut said end portion (41) of the gate electrode (14). The method of any of claims 10 to 12 wherein said steps of forming a layer of semiconductor material and forming a channel region together comprise: depositing a film of amorphous silicon (66) on said surface of said substrate (22) and in said recess (36) ; forming a mask layer (68) over said film of amorphous silicon; anisotropically etching said film of amorphous silicon to leave a strip within said recess; implanting with a dopant a portion of said strip remaining in said recess to form said channel (12); removing said mask layer; and converting said strip to polysilicon (24). The method of any of claims 10 to 12 wherein said step of forming the semiconductor layer includes: forming a layer of silicon overlying the gate electrode and in the recess overlaid by the gate electrode to provide some of the semiconductor layer above the gate electrode, some to the side of the gate electrode and some below the gate electrode.

Inventors: CUNNINGHAM JAMES A, CUNNINGHAM, JAMES A.
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1995
Main classification: H01L29
IPC codes: H01L21, H01L29, H01L27