Noise-insensitive device for bias current generation

Abstract: A device for generating a bias current, comprising: a reference voltage source (2) for supplying a reference voltage between a first reference terminal (4) and a second reference terminal (6); a bias current generator (8) for generating the bias current in response to the reference voltage, comprising: a first (10) and a second (12) input terminal coupled to the first (4) and the second (6) reference terminal (6) via connecting wires for receiving the reference voltage; a first (16) and a second (18) transistor arranged as a differential pair, the gate of the first transistor (16) being coupled to the first input terminal (10) and the gate of the second transistor (18) being coupled to the second input terminal (12), the source of the first transistor (16) and the source of the second transistor (18) being coupled to one another in a common terminal (20) for receiving a common current, each of said transistors having a drain for supplying a first transistor current and a second transistor current, respectively, whose difference decreases when the common current increases; a converter (22) coupled to the first (16) and the second (18) transistor and having an output terminal (24) for supplying a current which is proportional to the difference between the first transistor current and the second transistor current; a first current mirror (32) having an input branch (34) coupled to the output terminal (24) of the converter (22); a second current mirror (40) having an input branch (42) coupled to an output branch (36) of the first current mirror (32), and an output branch (46) coupled to the common terminal (20). The connecting wires (14) are not current-carrying and interference as a result of cross-talk from other circuits to the connecting wires is suppressed by the differential pair (16, 18).

Description: The invention relates to a device for generating a bias current, comprising: a reference voltage source having a first reference terminal and a second reference terminal for supplying a reference voltage between the first reference terminal and the second reference terminal; a bias current generator for generating the bias current in response to the reference voltage, the bias current generator comprising: a first input terminal and a second input terminal coupled to the first reference terminal and the second reference terminal for receiving the reference voltage. Such a device is known from inter alia United States Patent No. 3.982.172. Figure 1 shows the circuit diagram of this known device. The reference voltage source of the known device is formed by a diode-connected bipolar or unipolar transistor through which a reference current is passed. The base-emitter voltage or the gate-source voltage of the transistor functions as the reference voltage. The bias current generator is formed by one or more current source transistors which are of the same type as the diode-connected transistor and have their base-emitter junctions or gate-source junctions arranged in parallel with the junction of the diode-connected transistor. The diode-connected transistor and the current source transistors are arranged as a current mirror, so that there is a fixed relationship between the reference current through the diode-connected transistor and the output currents of the current source transistors. A disadvantage of this known device is that one of the connecting wires between the reference voltage source and the bias current generator is current-carrying and that a voltage drop may be produced in this wire. This applies in particular to the connecting wire between the emitter or source of the diode-connected transistor and the emitters or sources of the current source transistors. In the prior-art device this wire also corresponds to a supply line, which gives rise to additional noise voltages across the wire. The voltage drop in the current-carrying wire introduces an undesired error voltage in the base-emitter voltage or gate-source voltage of the current source transistors and eventually also an undesired error component in the bias currents supplied by the current source transistors. The undesirable error can be considerable, particularly in the case of comparatively large integrated circuits. Figure 2 shows an alternative known solution to this problem. The diode-connected transistor and the current source transistors are arranged near one another and the bias currents are applied from the current source transistors to the current-consuming elements by means of separate connecting wires. A disadvantage of this solution is that as many wires are required as there are elements receiving bias current. This requires a large area on an integrated circuit and is undesirable. It is an object of the invention to provide a device for generating bias current which is immune to noise and which requires a minimal number of connecting wires. To this end, according to the invention, the device of the type defined in the opening sentence is characterised in that the bias current generator further comprises: a first transistor and a second transistor which are arranged as a differential pair and which each have a control electrode and a first main electrode, the control electrode of the first transistor being coupled to the first input terminal and the control electrode of the second transistor being coupled to the second input terminal, the first main electrode of the first transistor and the first main electrode of the second transistor being coupled to one another in a common terminal for receiving a common current, each of said transistors having a second main electrode for supplying a first transistor current and a second transistor current, respectively, whose difference decreases when the common current increases; a converter coupled to the first transistor and the second transistor and having an output terminal for supplying a current which is proportional to the difference between the first transistor current and the second transistor current; a first current mirror having an input branch coupled to the output terminal of the converter, and having an output branch; a second current mirror having an input branch coupled to the output branch of the first current mirror, and an output branch coupled to the common terminal. The proposed solution provides a two-wire distribution system for a reference voltage which is converted into a bias current at the location of the current-consuming element. The two connecting wires are not current-carrying and can be arranged close to one another on a chip. Extraneous influences such as cross-talk from other signals on the chip will then appear as a common-mode signal but the differential pair is immune to such a signal. This results in a high noise immunity. At option, the first current mirror and the second current mirror may be provided with a plurality of output branches, so that for each bias current generator one or more bias currents are available which refer to the positive or the negative supply voltage. The differential pair, the converter for supplying the difference current, the first current mirror and the second current mirror form a loop whose steady state loop gain is unity at a given reference voltage between the control electrodes of the differential pair. In order to prevent the loop currents from constantly increasing the difference between the currents in the first and the second transistor should decrease as the common current of the first and the second transistor increases. This can be achieved in a first variant, which is characterised in that the first transistor and the second transistor are unipolar field effect transistors each having a gate, a source and a drain, which correspond to the control electrode, the first main electrode and the second main electrode, respectively, the drains of the first and the second transistor being connected to the common terminal. In the case of unipolar (MOS) transistors the transconductance of a differential pair is proportional to the root of the common current, so that the increase in current difference decreases automatically as the common current increases. This is not the case with bipolar transistors, so that other measures are required. To this end a second variant is characterised in that the first transistor and the second transistor are bipolar transistors each having a base, an emitter and a collector, which correspond to the control electrode, the first main electrode and the second main electrode, respectively, the emitter of the first transistor being connected to the common terminal via a resistor and the emitter of the second transistor being connected directly to said common terminal. When the common current increases the resistor in the emitter lead of the first transistor will ensure that a comparatively larger portion flows through the second transistor and the difference in collector currents consequently decreases. The reference voltage is generated centrally and is conveyed to the local bias current generators, where the reference voltage is converted into bias currents. The reference voltage source may be of any type, for example a voltage divider with two taps, which is connected to a supply voltage. An embodiment which is very suitable for this purpose is characterised in that the reference voltage source comprises: a further first transistor and a further second transistor which are arranged as a differential pair and which each have a control electrode and a first main electrode, the control electrode of the further first transistor being coupled to the first input terminal and the control electrode of the further second transistor being coupled to the second input terminal, the first main electrode of the further first transistor and the first main electrode of the further second transistor being coupled to one another in a further common terminal for receiving a further common current, each of said further transistors having a second main electrode for supplying a further first transistor current and a further second transistor current, respectively, whose difference decreases when the further common current increases; a further converter coupled to the further first transistor and the further second transistor and having a further output terminal for supplying a further current which is proportional to the difference between the further first transistor current and the further second transistor current; a further first current mirror having an further input branch coupled to the further output terminal of the further converter, and having a further output branch; a further second current mirror having a further input branch coupled to the further output branch of the further first current mirror, and a further output branch coupled to the common terminal, the further second current mirror having a further second output branch coupled to the first input terminal; a reference current source coupled to the further second output branch of the further second current mirror connected between the second input terminal and a terminal at a fixed potential; the first reference terminal being connected to the first input terminal and the second reference terminal being connected to the second input terminal. With this construction it is achieved that the relationship between the bias currents in the local bias current generator and the reference current in the central reference voltage source is only determined by the geometry proportions of the current mirror transistors. This makes it possible to generate bias currents of accurately defined magnitudes during the design of the entire circuit. It is to be noted that European Patent Application EP-A-0 531 615 discloses a temperature sensor circuit comprising a differential pair loaded with a current mirror for supplying a current which is proportional to the difference between the currents in the transistors of the differential pair and feedback from the output branch of the current mirror to the control electrode of one of the transistors of the differential pair for obtaining equal currents in the differential pair transistors. These and other aspects of the invention will be described and elucidated with reference to the accompanying drawings, in which Figure 1 a shows a first prior-art device for generating bias currents; Figure 2 shows a second prior-art device for generating bias currents; Figure 3 shows a first variant of a device for generating bias currents in accordance with the invention; Figure 4 shows a second variant of a device for generating bias currents in accordance with the invention; and Figure 5 shows a reference voltage source for use in a device for generating bias currents in accordance with the invention. In these Figures like parts or elements bear the same reference signs. Figure 3 shows an embodiment of a device for generating bias currents in accordance with the invention. A reference voltage source 2 has a first reference terminal 4 and a second reference terminal 6, between which a reference voltage Ur is produced. The bias currents are generated in a bias current generator 8 having a first input terminal 10 connected to the first reference terminal 4 and having a second input terminal 12 connected to the second reference terminal 6 for receiving the reference voltage Ur from the reference voltage source 2. Likewise, a plurality of bias current generators, referenced 8A and 8B, can be connected to the reference voltage source 2. The reference voltage source 2 is suitably positioned relative to the local bias current generators and is connected to these generators by a two-wire lead 14. The bias current generator 8 comprises an NMOS transistor 16 arranged as a differential pair and having its control electrode or gate connected to the first input terminal 10, and an NMOS transistor 18 having its gate connected to the second input terminal 12. The first main electrodes or sources of the transistor 16 and the transistor 18 are both connected to a common terminal 20 to receive a common current I2. The second main electrodes or drains of the transistor 16 and the transistor 18 are coupled to a converter 22 having an output terminal 24 for supplying a current I3 which is proportional to the difference between the drain currents of the transistor 16 and the transistor 18. The present converter 22 is constructed, by way of example, as a 1:1 current mirror having an input branch formed by a PMOS transistor 26 having its drain and gate short-circuited, having its source connected to a positive supply terminal 28, having its drain connected to the drain of the transistor 18 and to an output branch formed by a PMOS transistor 30 having its source, gate and drain connected to the positive supply terminal 28, the gate of the transistor 26 and the drain of the transistor 16, respectively. The output terminal 24 is connected to the drains of the transistor 16 and the transistor 30 and carries a current I3 equal to the difference between the drain currents of the transistor 16 and the transistor 18. The bias current generator 8 further comprises a B: 1 current mirror 32 having an input branch formed by a PMOS transistor 32 having its drain and gate short-circuited, having its source connected to the positive supply terminal 28 and having its drain connected to the output terminal 24 and to an output branch formed by a PMOS transistor 36 whose source and gate are connected to the positive supply terminal 28 and the gate of the transistor 34, respectively. The dimensions of the transistors 34 and 36 have been selected in such a manner that the drain current I1 of the transistor 36 is B times as large as the drain current I3 of the transistor 34. If desired, the current mirror 32 may be provided with at least one additional PMOS transistor 38 whose gate and source are arranged in parallel with the gate and the source of the transistor 36. The bias current generator 8 further comprises an A:1 current mirror 40 having an input branch formed by an NMOS transistor 42 having its drain and gate short-circuited, having its source connected to a negative supply terminal 44 and its drain to the drain of the transistor 36 and to an output branch formed by an NMOS transistor 46 having its source, gate and drain connected to the negative supply terminal 44, the gate of the transistor 42 and the common terminal 20, respectively. The dimensions of the transistors 42 and 46 have been selected in such a manner that the drain current I2 of the transistor 46 is A times as large as the drain current I1 of the transistor 42. If desired, the current mirror 40 may also be provided with at least one additional NMOS transistor 48 whose gate and source are arranged in parallel with the gate and the source of the transistor 46. The current gain A of the current mirror 40 and the current gain B of the current mirror 32 are linear. However, the current gain I3/I2 is not linear because the transconductance of the NMOS differential pair is proportional to the root of the current I2. The currents flowing in the bias current generator 8 will now be so large that the loop gain is equal to unity. The values of these currents can be adjusted with the reference voltage Ur. The relationship between the current I1 and the reference voltage Ur can be calculated as follows. I1 = B · I3 and I2=A ·I1 From the quadratic relationship between the drain current Id and the gate-source voltage Vgs in accordance with: Id = β 2 ( Vgs - Vt ) 2 where Vt is the threshold voltage and β is a transconductance parameter dictated by the geometry and by material constants of the MOS transistor, the following relationship can be derived: I3 = Ur β( I2 -(β/4) Ur 2 ) Substitution of equations (1) and (2) in equation (4) then yields the following expression for the current I1: I1 = β 2 Ur 2 B { AB + (( AB ) 2 -1) } The circuit is self-starting if AB > 1 but when necessary a starting circuit may be provided. The current I1 can now be mirrored further by means of the additional transistors 38 and 48 in order to provide further circuits, not shown, with bias current. From equation (5) it follows that the current I1 is dependent on the reference voltage Ur, on the parameter β and on the current gain factors A and B, which factors are only determined by geometry proportions of transistors. The two-wire lead 14 picks up interference, which appears as a common mode signal on the gates of the transistors 16 and 18 of the differential pair which is insensitive to such a signal. The gates of the differential pair present hardly any load to the two-wire lead 14, so that there is no voltage drop between the reference voltage source 2 and the bias current generator 8. Figure 4 shows the arrangement of Figure 3 with bipolar transistors, the control electrode, the first main electrode and the second main electrode now corresponding to the base, the emitter and the collector, respectively. PMOS transistors are replaced by PNP transistors and NMOS transistors by NPN transistors. In order to obtain a non-linear current gain I3/I2 a resistor 50 is arranged in series with the emitter of the bipolar transistor 16. When the current I2 increases an comparatively larger portion of the current I2 will flow through the bipolar transistor 18, so that the difference current I3 will increase to a decreasing extent. It will be evident that the combined use of unipolar transistors and bipolar transistors is also possible. For example, the transistors 16 and 18 of the differential pair may be NMOS transistors and the current mirrors 22, 32 and 40 may comprise bipolar transistors. The reference voltage source 2 can be constructed by means of any suitable direct voltage source, for example by means of a voltage divider having two taps, which form the first reference terminal 4 and the second reference terminal 6. A very suitable reference voltage source is shown in Fig. 5. The reference voltage source comprises a bias current generator 8 which is similar to the bias current generator 8 in Figure 3 but which has the drain of the additional transistor 48 connected to the first input terminal 10 and which further comprises a reference current source 52 connected between the positive supply terminal 28 and the first input terminal 10, and a direct voltage source 54 connected between the second input terminal 12 and the negative supply terminal 44. The first input terminal 10 is connected to the first reference terminal 4 and the second input terminal 12 is connected to the second reference terminal 6. The reference current source 52 supplies a reference current Ir to the transistor 48 and thereby fixes the value of the current I1 not only in the reference voltage source itself but also in all the reference generators connected via the two-wire lead 14. The reference voltage source 54 provides the second reference terminal 6 with a suitably selected bias voltage. The voltage on the first reference terminal 4 automatically assumes a value for which the reference current Ir can maintain itself in the transistor 48. The bias current generator 8 in Figure 5 and the bias current generator 8 in Figure 3 are of similar design and structure and like parts of these generators may be similar to one another. In that case the currents I1, I2 and I3 in the bias current generator 8 of the reference voltage source will be copied to the bias current generators connected via the two-wire lead. When bipolar transistors are used the bias current generator 8 in the reference voltage source shown in Figure 5 should also be equipped with bipolar transistors.

Claims: A device for generating a bias current, comprising: a reference voltage source (2) having a first reference terminal (4) and a second reference terminal (6) for supplying a reference voltage between the first reference terminal (4) and the second reference terminal (6); a bias current generator (8) for generating the bias current in response to the reference voltage, the bias current generator (8) comprising: a first input terminal (10) and a second input terminal (12) coupled to the first reference terminal (4) and the second reference terminal (6) for receiving the reference voltage, characterised in that the bias current generator (8) further comprises: a first transistor (16) and a second transistor (18) which are arranged as a differential pair and which each have a control electrode and a first main electrode, the control electrode of the first transistor (16) being coupled to the first input terminal (10) and the control electrode of the second transistor (18) being coupled to the second input terminal (12), the first main electrode of the first transistor (16) and the first main electrode of the second transistor (18) being coupled to one another in a common terminal (20) for receiving a common current, each of said transistors having a second main electrode for supplying a first transistor current and a second transistor current, respectively, whose difference decreases when the common current increases; a converter (22) coupled to the first transistor (16) and the second transistor (18) and having an output terminal (24) for supplying a current which is proportional to the difference between the first transistor current and the second transistor current; a first current mirror (32) having an input branch (34) coupled to the output terminal (24) of the converter (22), and having an output branch (36); a second current mirror (40) having an input branch (42) coupled to the output branch (36) of the first current mirror (32), and an output branch (46) coupled to the common terminal (20). A device as claimed in Claim 1, characterised in that it comprises: a further first transistor (16) and a further second transistor (18) which are arranged as a differential pair and which each have a control electrode and a first main electrode, the control electrode of the further first transistor (16) being coupled to the first input terminal (10) and the control electrode of the further second transistor (18) being coupled to the second input terminal (12), the first main electrode of the further first transistor (16) and the first main electrode of the further second transistor (18) being coupled to one another in a further common terminal (20) for receiving a further common current, each of said further transistors having a second main electrode for supplying a further first transistor current and a further second transistor current, respectively, whose difference decreases when the further common current increases; a further converter (22) coupled to the further first transistor (16) and the further second transistor (18) and having a further output terminal (24) for supplying a further current which is proportional to the difference between the further first transistor current and the further second transistor current; a further first current mirror (32) having an further input branch (34) coupled to the further output terminal (24) of the further converter (22), and having a further output branch (36); a further second current mirror (40) having a further input branch (42) coupled to the further output branch (36) of the further first current mirror (32), and a further output branch (46) coupled to the common terminal (20), the further second current mirror (40) having a further second output branch (48) coupled to the first input terminal (10); a reference current source (52) coupled to the further second output branch (48) of the further second current mirror (40; a direct voltage source (54) connected between the second input terminal (12) and a terminal (44) at a fixed potential; the first reference terminal (4) being connected to the first input terminal (10) and the second reference terminal (6) being connected to the second input terminal (12). A device as claimed in Claim 1 or 2, characterised in that the converter (22) comprises a current mirror (26, 30) having an input branch (26) coupled to the second main electrode of the second transistor (18) and having an output branch (30) coupled to the second main electrode of the first transistor (16) and to the output terminal (24) of the converter (22). A device as claimed in Claim 1, 2 or 3, characterised in that the first transistor (16) and the second transistor (18) are unipolar field effect transistors each having a gate, a source and a drain, which correspond to the control electrode, the first main electrode and the second main electrode, respectively, the drains of the first and the second transistor being connected to the common terminal (20). A device as claimed in Claim 1, 2 or 3, characterised in that the first transistor (16) and the second transistor (18) are bipolar transistors each having a base, an emitter and a collector, which correspond to the control electrode, the first main electrode and the second main electrode, respectively, the emitter of the first transistor (16) being connected to the common terminal (20) via a resistor (50) and the emitter of the second transistor (18) being connected directly to said common terminal.

Inventors: BULT KLAAS, GEELEN GODEFRIDUS JOHANNES GER, BULT, KLAAS, GEELEN, GODEFRIDUS JOHANNES GERTRUDIS MARIA
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1995
Main classification: G05F3
IPC codes: H03F3, G05F3, H03M1