A four-region (PNPN) semiconductor device

Abstract: The invention relates to a four-region (PNPN) semiconductor device including an additional N-type body (6,7) at the junction between the inner N-type region (2) and the inner P-type region (3), the additional N-type body (6,7) including a first part (6) adjacent to a second part (7), the first and second parts being of different conductivities from one another, both being of higher conductivity than the inner N-type region (2) and of lower conductivity than the inner P-type region (3).

Description: The present invention relates to a four-region (PNPN) semiconductor device. A four-region (PNPN) semiconductor device may be used as a voltage-transient suppressor since the junction between the inner N-type region and the inner P-type region breaks down, in reverse, at a voltage dependent on the conductivities of the regions forming that junction, the inner N-type region of the device being the lowest-conductivity region of the device. Following junction breakdown, the device switches to and remains in a low impedance state for as long as the available current exceeds some set value which is the holding current for the device. British Patent Application No. 2205685 (GB 2205685 A) discloses a four-region (PNPN) semiconductor device including an additional N-type body at the junction between the inner N-type region and the inner P-type region providing, through the effect of the additional N-type body, a device especially suited for use as a voltage-transient suppressor. British Patent Application No. 2208257 discloses an arrangement including two four-region (PNPN) semiconductor devices formed in parallel and facing in opposite senses sharing a common inner N-type region, for use as a bi-directional voltage-transient suppressor. The inner P-type region of each four-region (PNPN) device forms a junction with the common inner N-type region and, at each of those junctions, there is an additional N-type body serving substantially the same purpose as the additional N-type body included in the device disclosed in GB 2205685 A. European Patent Application No. 0552905 discloses an arrangement including two four-region (PNPN) devices formed in parallel, facing in opposite senses, sharing a common inner N-type region and in which each of two additional N-type bodies, at the junctions between the common inner N-type region and the inner P-type regions, is divided into a plurality of parts. European Patent Application No. 0542648 discloses a thyristor, that is, a four-region (PNPN) device, including an additional N-type body at the junction between the inner N-type region and the inner P-type region. An object of the present invention is the provision of a four-region (PNPN) semiconductor device structure that permits greater flexibility in the setting of the breakdown conditions than is possible with existing four-region (PNPN) devices. The invention provides a four-region PNPN semiconductor device including an additional N-type body at the junction between the inner N-type region and the inner P-type region, the additional N-type body including at least one first part lying adjacent to a second part, the or each first part being of different conductivity from the second part, the or each first part and the second part being of higher conductivity than the inner N-type region and of lower conductivity than the inner P-type region Preferably, the or each first part of the additional N-type body is of higher conductivity than the second part of the additional N-type body. Preferably, the second part of the additional N-type body substantially surrounds the or each first part of the additional N-type body, the second part forming one part of a junction with the inner N-type region and the or each first part forming the remainder of the junction with the inner N-type region. Preferably, the thickness of the or each first part is greater than the thickness of the second part in the direction of current flow through the device. Preferably, the inner P-type region penetrates the outer N-type region at a plurality of locations and contacts a conductive contact region disposed on the outer N-type region. Preferably, the area of the first part or first parts of the additional N-type body is such that the switching current of the device is low compared with the surge current capacity of the device, the size of the first part or parts of the additional N-type body determining the switching current of the device and the area of the outer N-type region determining the surge current capacity of the device. Preferably, the additional N-type body is co-extensive with the outer N-type region of the device. The invention provides a method of fabricating a four-region PNPN semiconductor device including the steps of forming an additional N-type body at the junction between the inner N-type region and the inner P-type region, by so forming the additional N-type body as to include at least one first part lying adjacent to a second part, the or each first part being of different conductivity from the second part, the or each first part and the second part being of higher conductivity than the inner N-type region and of lower conductivity than the inner P-type region. The method may include a first ion implantation of a dopant to form the or each first part of the additional N-type body followed by a second ion implantation of a dopant, over the or each first part as well as adjacent to the or each first part, to form the second part of the additional N-type body. The method may, alternatively, include an ion implantation of a dopant to form the or each first part of the additional N-type body followed by the diffusion of the implanted dopant to form the second part of the additional N-type body. Preferably, in the method including a second ion implantation of a dopant, an oxide mask is used for performing the first ion implantation and the oxide mask is modified for performing the second ion implantation. Four forms of four-region (PNPN) semiconductor device in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Fig. 1 represents a transverse cross-section of a first example of a unidirectional four-region (PNPN) semiconductor device in accordance with the invention, Fig. 2 represents a transverse cross-section of a bidirectional four-region (PNPN) semiconductor device in accordance with the invention Fig. 3 represents a transverse cross-section of a second example of a unidirectional four-region (PNPN) device in accordance with the invention and Fig. 4 represents a transverse cross-section of a unidirectional four-region (PNPN) semiconductor device in accordance with the invention incorporating a parallel diode. Referring to Fig. 1 of the accompanying drawings, the first example of a unidirectional four-region (PNPN) semiconductor device represented therein includes a P-type anode region 1 providing a first junction with an N-type substrate region 2, a P-type base region 3 which provides a second junction with the N-type substrate region 2 and an N-type emitter region 4 which provides a third junction with the P-type base region 3. An additional N-type body lying in the substrate region 2 consists of a first part 6 that is surrounded by second part 7 and both the first part 6 and the second part 7 lie at the second junction, that is, the junction between the P-type base region 3 and the substrate region 2. The conductivity of the first part 6 of the additional N-type body is higher than the conductivity of the second part 7 of the additional N-type body. The conductivity of the substrate region 2 is lower than the conductivity of each part of the additional N-type body 6,7 and the conductivity of the P-type base region 3 is higher than the conductivity of each part of the additional N-type body 6,7. The emitter region 4 of the semiconductor device is penetrated at a plurality of locations 5 by the base region 3. A conductive contact layer 9 makes contact with one surface of the emitter region 4 and makes contact with the base region 3 where the base region 3 penetrates the emitter region 4. The four-region (PNPN) semiconductor device includes an N-type channel stopper ring 8 at its upper edge (as viewed in the drawing) and a conductive contact layer 10 on the surface of its anode region 1. The additional N-type body 6,7 beneath the region 3 defines the breakdown voltage of the device. Ion implantation is relied on to give good control of the breakdown voltage. At voltage breakdown, current passes vertically through the junction of the P-type base region 3 and the additional N-type body 6,7. The current then passes through the P-type base region 3 and out through the locations 5 to the terminal 9. The current flow in the P-type base region 3 causes a voltage drop which eventually forward biasses the emitter junction and initiates conduction into the on state. Switching occurs at a critical current density flow through the breakdown junction. The current surge rating of the four-region (PNPN) device is approximately proportional to the area of its emitter region 4. The device may be made larger to increase the surge rating and the current at which switching occurs may also be expected to increase. The provision of a two-part additional N-type body 6,7 serves to maintain the switching current at a relatively low value set by the size of the first part 6 of the two-part additional N-type body 6,7. In the four-region (PNPN) device with a two-part additional N-type body 6,7, the switching current is proportional to the size of the first part 6, the higher conductivity part, of the additional N-type body 6,7. In the fabrication of the four-region (PNPN) device, the first part 6 of the additional N-type body 6,7 is implanted first using an oxide mask and then the oxide mask is recut to allow implantation in the second part and also in the first part. This means that the second part 7 of the additional N-type body 6,7 always has a lower impurity concentration than does the first part 6. The switching current is defined by the area of the most highly doped part of the additional N-type body 6,7 and by making the additional N-type body 6,7 substantially the same size as the emitter region 4 of the device there is no reduction in the surge capacity of the device. Under the influence of a rapidly rising energy surge, the device will begin to break down first in the first part 6 of the additional N-type body 6,7, and the voltage will overshoot due to the series resistance associated with the small breakdown region. However, as the voltage rises above the breakdown of the second part of the additional N-type N-type body 6,7, the second part 7 starts to break down and both parts of the additional regions 6,7 contribute towards switching on the device. That initiates switching over all of the device area. The device has a switching current dependent on the area of the first part 6 of the additional N-type body 6,7 and a surge current capacity dependent on the whole area of the additional N-type body 6,7 which is substantially equal to the area of its emitter region 4. If the N-type substrate region 2, the P-type base region 3 and the N-type emitter region 4 are regarded as acting as an NPN transistor, then the gain of the transistor is relatively constant across its width because the additional N-type body is co-extensive with its emitter. Referring to Fig. 2 of the accompanying drawings, a bidirectional four-region (PNPN) semiconductor device in accordance with the invention includes a lightly doped N-type substrate region 22 in which there is a first additional N-type body having a first part 26 and a second part 27, both more doped than the substrate region 22 and the first part 26 being more highly doped than the second part 27, adjacent to a P-type base region 23 which has a junction with a highly doped N-type emitter region 24 which is penetrated at a plurality of locations by the P-type base region 23. A P-type anode region 21 has a junction with the lightly doped N-type substrate region 22. The N-type substrate region 22, the P-type anode region 21, the P-type base region 23, the N-type emitter region 24 and the additional N-type body 26,27 form a first four-region (PNPN) semiconductor device. The N-type substrate 22, the P-type region 23 and the P-type region 21 are shared by a second four-layer (PNPN) semiconductor device for which the P-type region 23 serves as an anode region and the P-type region 21 serves as a base region. The second four-layer (PNPN) semiconductor device includes a second additional N-type body 206,207 in which a first part 206 is more doped than a second part 207 and an N-type emitter region 204 which is penetrated by the P-type region 21 at a plurality of locations, offset from the corresponding elements of the first four-layer (PNPN) device. Terminal contacts 28 and 29 complete the devices. Referring to Fig. 3 of the accompanying drawings, the second example of a unidirectional four-region (PNPN) device represented therein includes a P-type anode region 31 providing a first junction with an N-type substrate region 32, a P-type base region 33 which provides a second junction with the N-type substrate region 32 and an N-type emitter region 34 which provides a third junction with the P-type base region 33. So far, the device is the same as the first example of a unidirectional four-region (PNPN) device shown in Fig. 1. The device shown in Fig. 3 includes an additional N-type body lying in the substrate region 32 and consisting of a plurality of first parts 36 and a second part 37. The first parts 36 and the second part 37 lie at the second junction , that is, the junction between the P-type base region 33 and the substrate region 32. The conductivities of the first parts 36 of the additional N-type body are higher than the conductivity of the second part 37 of the additional N-type body. The conductivity of the substrate region 32 is lower than the conductivity of each part of the additional N-type body 36,37 and the conductivity of the P-type base region 33 is higher than the conductivity of each part of the additional N-type body 36,37. The plurality of first parts 36 of the additional N-type body are implanted as a plurality of "dots" and the second part 37 is formed by diffusing impurities from the first parts 36 until the diffused regions merge. The emitter region 34 of the device shown in Fig. 3 is penetrated at a plurality of locations 35 by the base region 33. A conductive contact layer 39 makes contact with one surface of the emitter region 34 and makes contact with the base region 33 where that region penetrates the emitter region 34. The four-region (PNPN) semiconductor device includes an N-channel stopper ring 38 at its upper edge (as viewed in the drawing) and a conductive layer 30 on the surface of its anode region 31. Referring to Fig. 4 of the accompanying drawings, a unidirectional four-region (PNPN) semiconductor device shares a substrate region 41,410 and a P-type region 42,411 with a PN diode. The four-region (PNPN) device includes a P-type anode region 44 forming a first junction with the part 41 of the N-type substrate region 41,410, an additional N-type body 46,47 in the part 41 of the N-type substrate region 41,410, the part 42 of the P-type region 42,411 and an N-type emitter region 45 which is not penetrated by the adjacent P-type region 42. The PN diode includes the part 410 of the N-type substrate region 41,410 and the part 411 of the P-type region 42,411. The part 410 of the N-type substrate region 41,410 is of reduced thickness compared with the part 41 of that region, the reduction in thickness being effected by a highly doped N-type region 43. Terminal contacts 48,49 complete the device. The effects of the additional N-type bodies included in a device represented by Fig. 2 or by Fig. 3 or by Fig.4 on those devices are substantially the same as the effects of the additional N-type body included in a device represented by Fig. 1 on that device. The penetration of the N-type emitter regions, in a device represented by Fig. 1 or Fig. 2 or Fig. 3, by the adjacent P-type region provides a means of controlling the holding current of the device and is not an essential feature of the device.

Claims: A four-region PNPN semiconductor device (1,2,3,4) including an additional N-type body at the junction between the inner N-type region (2) and the inner P-type region (3), characterised in that the additional N-type body (6,7) includes at least one first part (6,36) lying adjacent to a second part (7), the or each first part (6,36) being of different conductivity from the second part (7), the or each first part (6,36) and the second part (7) being of higher conductivity than the inner N-type region (2) and of lower conductivity than the inner P-type region (3). A device as claimed in claim 1, wherein the or each first part (6,36) of the additional N-type body (6,7) is of higher conductivity than the second part (7) of the additional N-type body. A device as claimed in claim I or claim 2, wherein the second part (7) of the additional N-type body (6,7) substantially surrounds the or each first part (6,36) of the additional N-type body (6,7), the second part (7) forming one part of a junction with the inner N-type region (2) and the or each first part (6,36) forming the remainder of the junction with the inner N-type region (2). A device as claimed in any one of claims 1 to 3, wherein the thickness of the or each first part (6,36) is greater than the thickness of the second part (7) in the direction of current flow through the device. A device as claimed in any one of claims 1 to 4, wherein the inner P-type region (3) penetrates the outer N-type region (4) at a plurality of locations and contacts a conductive contact region (9) disposed on the outer N-type region (4). A device as claimed in any one of claims 1 to 5, wherein the area of the first part (6) or parts (36) of the additional N-type body (6,7) is such that the switching current of the device is low compared with the surge current capacity of the device, the size of the first part (6) or parts (36) of the additional N-type body (6,7) determining the switching current of the device and the area of the outer N-type region (4) determining the surge current capacity of the device. A device as claimed in any one of claims 1 to 6, wherein the additional N-type body (6,7) is co-extensive with the outer N-type region (4) of the device. A method of fabricating a four-region PNPN device including the steps of forming an additional N-type body at the junction between the inner N-type region (2) and the inner P-type region (3), characterised by the steps of so forming the additional N-type body as to include at least one first part (6,36) lying adjacent to a second part (7), wherein the or each first part (6,36) is of different conductivity from the second part (7), the or each first part (6,36) and the second part (7) being of higher conductivity than the inner N-type region (2) and of lower conductivity than the inner P-type region (3). A method as claimed in claim 8, including a first ion implantation of a dopant to form the or each first part (6,36) of the additional N-type body followed by a second ion implantation of a dopant, over the or each first part (6,36) as well as adjacent to the or each first part (6,36), to form the second part (7) of the additional N-type body. A method as claimed in claim 8, including an ion implantation of a dopant to form the or each first part (6,36) of the additional N-type body followed by the diffusion of the implanted dopant to form the second part (7) of the additional N-type body. A method as claimed in claim 9, wherein an oxide mask is used for performing the first ion implantation and the oxide mask is modified for performing the second ion implantation.

Inventors: BYATT STEPHEN WILTON, BYATT, STEPHEN WILTON
Applicants: POWER INNOVATIONS LIMITED
Application year: 1995
Main classification: H01L29
IPC codes: H01L29