OUTPUT CONTROL CIRCUIT FOR A VOLTAGE REGULATOR

Abstract: The preferred embodiment shows a stabilized voltage regulator (figure 2) which offsets changes in the output impedance of the regulator due to changes in load current. The output capacitor (C) is selected primarily based upon filtering requirements rather than on frequency compensation requirements. A depletion mode pass transistor (MD2, figure 3) is used as the output transistor. A PMOS transistor (MP9) on/off switch is connected between the source of the pass transistor (MD2) and the output terminal (VREG) which allows for the regulator to be turned off or on without shutting down the depletion mode pass transistor (MD2). Output voltage affected by process variations of transistors is corrected by a beta factor in a band gap voltage reference generator (figure 4).

Description: OUTPUT CONTROL CIRCUIT FOR A VOLTAGE REGULATOR FIELD OF THE INVENTION This invention relates to voltage regulators, and in particular to an improved output stage of a voltage regulator. BACKGROUND OF THE INVENTION Fig. 1 is a block diagram illustrating the general configuration of a linear-type voltage regulator whose output voltage V^ is regulated using a feedback loop. A battery or other unregulated power supply voltage V+ is applied to an input terminal of an output amplifier 10. Output amplifier 10 includes a pass transistor connected between V+ and V ^ ,,. A resistor-divided output voltage V„, t is fed back into an error amplifier 12, and this feedback voltage is compared to a reference voltage generated by a reference voltage generator 14. The error amplifier 12 generates an error signal which controls the pass transistor in output amplifier 10 to have a conductivity such that the divided V ^ , voltage matches the reference voltage despite changes in load current. Output capacitor C is used for both filtering V^ and for frequency compensation to improve the stability of the circuit when transients are created at the V,,,, terminal. Such transients may be created by varying load conditions. As would be understood by those skilled in the art, the proper selection of the output capacitor C value is dependent upon the impedance of the pass transistor in output amplifier 10. The impedance of the pass transistor (and thus the output impedance of the regulator) changes as the load current varies. This impedance change can occur even before the feedback circuit reacts to the changed load condition. For example, if the pass transistor were an MOS device having its source coupled to V^, or if the pass transistor were a bipolar transistor having its emitter coupled to V^, a sudden drop in load resistance would reduce the source or emitter voltage and instantaneously increase the V^ or V BE of the pass transistor. This, in turn, decreases the output impedance of the regulator. Conversely, the output impedance increases when less current is drawn through the load. This change in output impedance affects the frequency compensation requirements, and the designer must select a value of capacitor C taking this into account. Thus, the capacitor value is selected with worse case conditions in mind. What is needed is a circuit and method for improving the compensation of a voltage regulator output. In many types of low dropout voltage regulators, a high voltage depletion mode NMOS device is used as the pass element in output amplifier 10. If it were desired to turn the voltage regulator off, the gate of the depletion mode NHOS device must then be driven to a voltage below its source, which usually means that a negative voltage supply is required to pull the gate below ground. Creating a negative voltage source requires additional complexity and silicon real estate. What is needed is a circuit and method to turn off a voltage regulator having a depletion mode pass transistor without requiring the creation of a negative voltage supply. The reference voltage generator 14 in Fig. l is typically a band gap reference type, whose characteristics are well known. Band gap voltage generators produce a relatively constant voltage over a range of temperatures by combining a voltage having a positive temperature coefficient with a voltage having a negative temperature coefficient. These voltages are related to the V BE of bipolar transistors used in the reference voltage generator and are affected by process variations. The typical band gap reference will have a voltage verses temperature characteristic that peaks at some nominal temperature and decreases in voltage as temperature is increased above or decreased below this nominal temperature. This decrease lowers the reference voltage by a small amount (e.g., up to 5 mV) . Part of this decrease is proportional to (kT/q) In (beta) , where beta is the current gain of the bipolar transistors used in the reference voltage generator. It is important that the reference voltage remain relatively constant throughout a wide range of temperatures and be predictable despite process variations since the ability of the voltage regulator of Fig. 1 to output a constant V ^ , is directly dependent upon the ability of the reference voltage generator 14 to output a constant reference voltage. Thus, what is needed is a reference voltage generator whose output is less affected by process dependent beta variations and temperature variations. SUMMARY OF THE INVENTION The preferred embodiment voltage regulator exhibits improved stability by offsetting changes in the output impedance of the regulator due to changes in load current. This compensation occurs virtually instantaneously with a change in load current. This enables an output capacitor to be selected primarily based upon filtering requirements rather than on frequency compensation requirements. In the preferred embodiment, a depletion mode pass transistor is used as the output transistor. In prior circuits, a negative voltage supply was required to pull the gate of the depletion mode device below the source voltage in order to completely turn off the pass transistor. In the preferred circuit, a PMOS transistor on/off switch is connected between the source of the pass transistor and the output terminal of the regulator to effectively turn the regulator on or off without shutting down the depletion mode pass transistor. This avoids the need to form a negative supply voltage generator. An improved band gap voltage reference generator is also described which introduces a beta correction factor into the output voltage which offsets changes in beta due to process variations and other conditions. Thus, the output voltage of the reference generator is not affected by variations in the beta of transistors forming the reference generator. BRIEF DESCRIPTION OF THE DRAWINGS Fig. l illustrates a prior art voltage generator. Fig. 2 illustrates one embodiment of the voltage generator in accordance with the present invention. Fig. 3 is a schematic diagram of the error amplifier, output amplifier circuitry, current detection circuity, and current feedback circuitry shown in Fig. 2 Fig. 4 is a simplified schematic diagram of the pertinent portions of Fig. 3. Fig. 5 is a Bode plot of the output amplifier stage illustrating its improved performance. Fig. 6 illustrates the voltage regulator's response to output current steps. Fig. 7 is a simplified schematic diagram of the preferred embodiment band gap voltage reference regulator which introduces a beta compensation signal into the reference voltage generator output. Fig. 8 is a schematic diagram of an actual circuit incorporating the band gap voltage reference generator of Fig. 7. Fig. 9 is a high level block diagram of the various functional blocks and interconnections between these blocks in one embodiment of a voltage regulator. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 2 illustrates one embodiment of a voltage regulator 16 incorporating the inventive circuits. Portions of the voltage regulator which may be conventional will not be described herein in detail. In Fig. 2, reference voltage generator 20 provides a stable reference voltage despite changes in temperature. This reference voltage, which is about 1.25 volts in one embodiment, is compared by an error amplifier 22 to a voltage, taken at the junction of resistors Rl and R2, related to the output voltage V^. The resistor divider is not needed if a gain stage is used at the output of the reference voltage generator to output the desired V,,,,, voltage. The error signal is applied to an output amplifier 24 for controlling a pass transistor to supply more or less current to a load (R L ) to keep V ^ ,, constant despite changes in R L . Output control circuit 30 controls the output amplifier 24 to be on or off and provides a current limiting function. A current detector 32 detects an output current of the pass transistor and applies a feedback signal, related to the current, to the elements controlling the pass transistor. The current detector 32 and feedback circuitry operate rapidly to cause the impedance of the pass transistor to not substantially change with rapid fluctuations of the load R L . A bias circuit 28 provides various bias voltages to the circuitry in blocks 20, 22, 24, and 32. Capacitor C provides filtering and frequency compensation to improve the stability of the regulator in response to transient conditions at V^. The feedback provided by the current detector 32 to stabilize the output impedance of the regulator enables the designer to select the value of capacitor C based primarily upon the filtering requirements rather than on frequency compensation requirements. Fig. 3 is a schematic diagram of error amplifier 22, output amplifier 24, and current detector 32, along with some biasing and output control circuitry, in accordance with the preferred embodiment voltage regulator. NMOS transistor MD2 is a high voltage/high current depletion mode transistor, acting as a pass transistor, having a drain connected to a positive power supply terminal VPLUS. VPLUS may be an automobile battery or another voltage source generating up to 60 volts. The gate of transistor MD2 is controlled to supply a current through PMOS transistor MP9 such that the output voltage at the output VREG of the voltage regulator remains at 5 volts despite the changing current needs of a load (not shown) connected between VREG and ground. Transistor MP9 acts as an on/off switch and receives either a high signal or a low signal at its gate, via terminal PG, for connecting the source of transistor MD2 to the VREG terminal. By controlling the on/off state of PMOS transistor MP9, the output voltage at VREG is turned on or off without having to turn off depletion mode transistor MD2. This avoids the need for a negative voltage supply to apply a negative voltage to the gate of transistor MD2 to turn off transistor MD2. This results in a considerable savings of silicon area and complexity. PMOS transistor MP9 may be a 5 volt device. Other types of suitable switches may be substituted for transistor MP9. A 5 volt reference voltage, generated by an amplified output of a band gap reference generator (to be described later) , is applied to input terminal V5 and applied to the input of bipolar transistor QN1. The voltage drops across bipolar transistors QN1, QP1, QP2, and QN2 are maintained such that the output voltage at VREG is the same voltage as applied to pin V5. The V os of pass transistor MD2 is automatically adjusted up or down to cause the voltage drops across N1 and P1 to equal the voltage drops across QN2 and QP2. This then balances the transistor bridge and causes the voltage at VREG to be at 5 volts. Depending on the matching of voltage drops across the transistor bridge, the gate voltage of transistor MD2 is either pulled down by transistor QN5 or pulled up by transistor QN4 controlling MOS transistors MP4, MP5, and MP8 to pull up the gate of transistor MD2 to the source voltage of NMOS transistor MD1. Other types of push/pull stages may also be used. Using transistor MD1 to power the gate drive circuitry for transistor MD2 allows the gate of transistor MD2 to be raised nearly 1 volt above the source of transistor MD2 at high currents, providing an increased maximum output current for the regulator. A fixed bias current is applied to input terminals C, D, and D2. The VN terminal is connected to ground. The PB terminal is connected to a bias voltage to cause transistors MN1, MP3, and MP7 to properly bias transistor MN2 and the transistor bridge. Current flowing into terminal ZOUT can be used for adjusting the gain of the error amplifier. Compensating the output stage is accomplished with two capacitors, Cl and C2. The main gain roll-off capacitor is C2. The dominant parasitic pole in the circuit is generated by the gate of the pass transistor MD2 and the output impedance of the push-pull amplifier. If the pole due to a load capacitor connected to VREG occurs while the gain of the circuit is greater than one, oscillations will occur. Capacitor Cl is introduced as a zero in the circuit to cancel out the dominant parasitic pole. The effect of Cl is to lower the output impedance of the regulator. Capacitor Cl is a pole cancellation capacitor to extend the operating range to lower values of output capacitance. Typically, the poles of the load capacitance will be on the order of hundreds of kilohertz. The compensation capacitance C2 is placed in the current loop of the amplifier. Changes in output current are slowed by the operation of this capacitor C2. Further, a zero is introduced into this circuit by the operation of resistors Rl and R2. A portion of the circuit of Fig. 3 which is used to improve the stability of the regulator by offsetting changes in output impedance due to transients at the VREG terminal will now be described. The feedback loop which compares the reference voltage at terminal V5 to the voltage at VREG and adjusts the gate voltage of transistor MD2 is relatively slow and does not react to high frequency transients at the VREG terminal. These transients change the conductivity of transistor MD2, making compensation difficult. Without proper compensation, the regulator may be unstable in response to these transients. In order to maintain the output impedance of the voltage regulator relatively constant despite transients on VREG, a fast feedback loop is provided primarily consisting of depletion mode transistor MD1, PMOS transistors MP6 and MP2, resistors Rl and R2, capacitor C2, and bipolar transistor QN5. This feedback loop reacts to the current through transistor MD2 rather than voltage fluctuations at the VREG terminal. Since MOS devices are square law devices, if the threshold voltage of pass transistor MD2 is subtracted from its V QS voltage, this resulting voltage is proportional to the square root of the current through transistor MD2. The difference between nodes VP and P in Fig. 3 represents this voltage. A PMOS threshold is added by the operation of transistor MP6. The V^ of PMOS transistor MP2 generates a current proportional to the current through pass transistor MD2, and a voltage proportional to this current is generated across Rl. This voltage at resistor Rl is then used to generate the compensation gate voltage for pass transistor MD2. This scheme allows the amplifier to anticipate overshoot in the load by slowing changes in current under conditions which generate high rates of change of current such as step loads and startups. A simplified version of this fast feedback loop portion of Fig. 3 is shown in Fig. 4. The current source II connected to the source of transistor MD1 is formed in part by PMOS transistors MP3 and MP7 in conjunction with NMOS transistor MN1 in Fig. 3. A second current source 12 shown in Fig. 4 is provided by a bias circuit (not shown) connected to terminal PB in Fig. 3. Transistors MD1 and MD2 are similar depletion mode NMOS transistors except that MD1 is much smaller than MD2 and hence carries a low current and provides a low voltage drop. Transistors MD1 and MD2 have their gates connected together so that the current through transistor MD1 somewhat tracks the current through MD2. The voltage at the source of transistor MD1 reflects the gate voltage of transistor MD2 minus the threshold voltage of transistor MD2 (the V TO of MD1 and MD2 are equal) at a given instant. This V G -V JH voltage is applied at the source of transistor MP2. The source of transistor MD2 is connected to the source of transistor MP6. The gate and drain of MP6 are connected together so that the voltage drop (i.e., a threshold voltage) across transistor MP6 is constant. The voltage at the drain of transistor MP6 is coupled to the gate of transistor MP2 so that the V^ of transistor MP2 is related to the V as "V TtI of transistor MD2. Thus, the current through transistor MP2 will track the current through transistor MD2. The current through transistor MP2 is reflected as a voltage drop across resistor Rl, where an increased current through MP2 (or MD2) raises the voltage at resistor Rl. This voltage is coupled to the base of NPN bipolar transistor QN5, via resistor R2 and capacitor C2. Transistor QN5 is coupled between the common gate of MD1 and MD2 and ground such that an increased voltage at resistor Rl lowers the gate voltage of transistor MD2. This, in turn, quickly lowers the current through transistor MD2 in response to an increase in load current. Conversely, a drop in load current causes the gate voltage of transistor MD2 to be raised accordingly. As an example, if the load connected to the VREG terminal attempts to draw more current, the source of transistor MD2 will be pulled down. This would normally raise the V os of MD2 and thus rapidly decrease the output impedance of the voltage regulator. In response, transistor MP2, in conjunction with resistor Rl and transistor QN5, pulls down the gate of transistor MD2 so that the resulting V αs of MD2 will remain relatively constant even in light of this fast transient on the VREG terminal. The voltage at resistor Rl is also coupled to the emitter of transistor QN4, comprising part of the gate pull-up circuitry. If the voltage at resistor Rl were to decrease, then the gate of transistor MD2 would be pulled up to achieve a constant V^. Transistor MP1 in Fig. 3 provides a capacitance across transistor MP2 to improve stability. Diode Dl conducts when the voltage at terminal VP exceeds a certain level in order to limit voltage excursions on VREG. This conduction of diode Dl turns on transistor QN5 to pull the gate of transistor MD2 low. As seen, this fast feedback circuit provides current feedback compensation rather than output voltage compensation in response to a transient on the VREG terminal. This unique compensation scheme incorporating the fast feedback loop makes the output stage stable into almost any capacitive or resistive load by design from 0.1 microfarads to 100 microfarads and nearly independent of ESR (Equivalent Series Resistance of the capacitor) . With a 10 microfarad output capacitance, there is an 89° phase margin and nearly two decades of gain margin. This makes the circuit useful over almost any reasonable capacitive load. In addition, the push- pull amplifier design makes the circuit very responsive to steps in the load current. It can be seen from the Bode plot of Fig. 5 for the amplifier that the output has three decades of gain margin and 90 degrees of phase margin. This allows the regulator to be stable into a wide variation of capacitive loads. The low output impedance insures that step changes will not perturb the output voltage severely and the current compensation acts to limit overshoot. The output stage was designed to be stable into capacitive loads from 0.1 μf to 100 μf and to be very inventive to capacitor ESR. To be stable, the amplifier requires a few tens of milliohms of ESR. The zero in the output impedance makes the circuit very responsive to current steps. Fig. 6 is a plot of the output voltage as current is ramped exponentially from near zero to 500 a with positive going 100 ma current steps. The load is a "worst case" type load with low capacitance and high ESR. The output capacitor is 2 μF and the ESR is 10 ohms. The ESR resistor should produce 1 volt steps. It is apparent that the excursions are small and fast due to the low output impedance and high frequency response of the output stage. The nominal output voltage steps is only 50 mV positive and -250 mV negative on the short spikes due to the ESR of the capacitor. A small parallel capacitor with low ESR should remove the fast spikes. It is important here to note the stability and lack of oscillation. The band gap reference generator 20 in Fig. 2 will now be described. It is standard observation in the industry that the product of beta and Gummel number is constant for normal NPN transistors. This fact was used to generate a beta compensation circuit. The three main sources of error in a band gap voltage reference are resistor sheet resistance, V BE variation, and resistor variation due to low spatial frequency geometric variations of photoresist and etch. The first two errors are related because the resistor is built from the base sheet implant. As the resistor sheet resistance decreases, the V BE will rise in a correlated fashion through variations in the Gummel number, N b . The circuit of Fig. 7 makes the band gap reference independent of V BE differences due to process variations and relatively independent of temperature. The fundamental relationship utilized is the high degree of correlation between Gummel number and beta, such that the product of the Gummel number and beta is constant. Beta is assumed to be only a function of Gummel number. A term proportional to (kT/q) In beta is introduced into the band gap reference to cancel out the changes in implant dose which will shift the basic band gap compensation. Fig. 7 illustrates a preferred embodiment of a circuit 50 for compensating the output of a band gap reference generator 52 for changes in the performance of generator 52 with process variations and temperature. In the preferred embodiment, the output of generator 52 at node 54 is about 1.25 volts. This voltage is level shifted to 5 volts, using well known circuit techniques, for use as a voltage reference in the regulator of Fig. 2. In Fig. 7, a voltage proportional to (kT/q) In beta appears between points A and B. A portion of this voltage is then added to the band gap voltage to cancel out variations in V BE . Also, since the Gummel number is strongly correlated to the resistor sheet rho, errors in the resistor sheet rho can also be compensated by this beta correction circuit. The resulting band gap reference circuit produced only a few tenths of a millivolt variation from minus 50°C to 150°C. To compensate for low spatial frequency geometric variations, a resistor width variation was introduced. In the band gap resistor bridge, if resistor width increases, current density in the transistors will increase, causing an increasing V BE . The resistor width variation reduces the gain of the resistor bridge to restore the band gap voltage. More specifically, in the circuit of Fig. 7, Ml and M2 are current mirrors, which may be conventional. For example, a current mirror can consist of two transistors having their emitters or sources connected to VDD and their bases or gates coupled together. The current flowing through one transistor will thus be the same as the current flowing through the other transistor since they have identical V BE or V αs voltages. The current through transistors Q3 and Q4 are equal. The bases of transistors Q3 and Q4 are connected together. The emitter area of transistor Q4 is formed to be eight times as large as the emitter area of transistor Q3. Therefore, the V BE of transistor Q4 will be less than the V BE of transistor Q3. This creates a voltage difference across resistor R3 equal 1,8 to (kT/q) In (-=?-) or (kT/q) In 8. This delta V BE has -!-4 a positive temperature coefficient, while the V BE of transistor Q3 has a negative coefficient (around - 2mV/°C) . The positive temperature coefficient of the voltage across resistor R3 is selected so that the change in voltage at node B with temperature sets off the change in the V BE of transistor Q3 with temperature. As a result, the voltage at output terminal 54 will remain fairly constant over temperature. The delta V BE is equal to R 3 I 4 and, therefore, I 4 = (kT/qR 3 ) In 8. The output voltage at terminal 54 is equal to the V BE of Q3 plus I 4 (R 4 +Rj) , where the first term has a negative temperature coefficient and the second term has a positive temperature coefficient. For the best performance, the resistor values are chosen such that the output voltage is about 1.25 volts. In the beta compensation circuit 50, the current in transistor Ql is determined by the band gap voltage at output terminal 54 minus the V BE of transistor Q2 divided by the equivalent resistance to ground formed by Rl, R2 and R5. (The current in R4 is also taken into account) . The current mirror Ml forces the transistor Q2 collector current to operate at the transistor Ql base current. Since base current is related to collector current by beta (i.e., beta = Ic/Ib) , then the transistor Q2 collector current will be a function of beta. The voltage between the emitters of transistors Q2 and Q3 will be proportional to kT/q In (beta) . The voltage at the emitter of transistor Q2 is divided by the resistor network comprising resistors R2 and R5 so that the change in beta of the compensation circuit 50 due to process and temperature variations will vary the voltage at node B in a manner opposite to the change in voltage at node B due to changes in beta of the band gap voltage reference circuit 52. Thus, the output voltage at terminal 54 will be more constant and predictable using compensation circuit 50. Other switchable circuits may be used for introducing a voltage related to (kT/q) In (beta) into any band gap voltage reference to improve its performance. Amplifier G forms a local feedback loop to raise the band gap output voltage at terminal 54 to the exact voltage (around 1.25 volts) where I 3 equals I 4 . Figure 8 shows the complete circuit of the band gap reference as implemented in the IC voltage regulator. The current mirror for Ml is within circle 56 and consists of MOS transistors MP16 through MP20. The beta correction transistors are QN2 and QN3 within circle 58. The band gap transistors are QN4 and QN5. Fig. 9 is a high level block diagram illustrating one embodiment of a voltage regulator incorporating the novel circuits described in detail herein. Shown is the reference voltage generator 20 and the combined error amplifier 22, output amplifier 24, and current detector 32. Also shown is a control circuit 62 for controlling the on/off state of the PMOS transistor MP9 in Fig. 3. An optional reset circuit 64 senses when the output voltage falls below the regulated output voltage, such as resulting from a loss in regulation by exceeding the current or thermal limit, or due to a low input voltage. In response to this lowering of the output voltage a reset signal is generated. An optional watchdog circuit 66 detects a periodic pulse outputted by an external microprocessor to make sure the microprocessor is functioning. If the pulse is not detected, the watchdog circuit 66 outputs a reset signal which is ORed with the reset signal outputted by reset circuit 64. Block 68 contains trim pads for trimming the reference voltage, as would be well known While particular embodiments of the present invention have been shown and described, it would be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.

Claims: ______ i_s What is claimed is: 1. A voltage regulator comprising: an MOS transistor connected between a power supply terminal and a load terminal for providing an output current to said load; a voltage feedback loop comprising an error amplifier for comparing a feedback voltage to a reference voltage and outputting an error signal to control said output current of said MOS transistor; a current feedback loop comprising a current detector for detecting said output current and, in response to said detecting, generating a compensation gate voltage for said MOS transistor to stabilize the impedance of said MOS transistor, as seen at said load terminal, as said load fluctuates, said current feedback loop having a faster response to load fluctuations than said voltage feedback loop. 2. The voltage regulator of Claim 1 wherein said MOS transistor is an NMOS transistor and said current feedback loop lowers a gate voltage of said NMOS transistor when an increased current through said NMOS transistor is detected. 3. The voltage regulator of Claim 1 wherein said current feedback loop substantially prevents rapid changes in current through said MOS transistor due to load fluctuations. 4. The voltage regulator of Claim 1 further comprising a frequency compensation capacitor connected to said load terminal. 5. The voltage regulator of Claim 1 wherein said MOS transistor is a first NMOS transistor having a drain electrically coupled to a first voltage and a gate connected to a controller for controlling the current flow between said drain and a source of said first NMOS transistor, and wherein said current feedback loop comprises: a second NMOS transistor having a gate electrically coupled to said gate of said first NMOS transistor, a drain electrically coupled to said first voltage, and a source electrically coupled to a first current source, said second NMOS transistor having a threshold voltage approximately equal to a threshold voltage of said first NMOS transistor, whereby a voltage produced at said source of said second NMOS transistor is approximately equal to a voltage at said gate of said first NMOS transistor minus said threshold voltage; a first PMOS transistor having a source connected to said source of said second NMOS transistor and a drain connected to a second voltage through a first resistance, a gate of said first PMOS transistor being connected to said source of said first NMOS transistor through a level shifter which develops a voltage drop approximately equal to a threshold voltage of said first PMOS transistor; and a third transistor having a control terminal electrically connected to said drain of said first PMOS transistor, a first current carrying terminal of said third transistor connected to said gate of said first NMOS transistor and a second current carrying terminal of said third transistor connected to said second voltage. 6. The voltage regulator of Claim 5 wherein said level shifter is a second PMOS transistor having a source connected to said source of said first NMOS transistor, a drain connected to a second current source, and a gate connected to said drain of said second PMOS transistor, said second PMOS transistor having a threshold voltage substantially equal to a threshold voltage of said first PMOS transistor. 7. The voltage regulator of Claim 5 wherein said control terminal of said third transistor is connected to said drain of said first PMOS transistor through a resistor and capacitor in series. 8. The voltage regulator of Claim 5 wherein said third transistor is a bipolar transistor. 9. A method for generating a regulated voltage and stabilizing an output impedance of a voltage regulator comprising the steps of: controlling an MOS transistor connected between a power supply terminal and a load terminal to provide an output current to said load; comparing a feedback voltage at said load terminal to a reference voltage and outputting an error signal to control said output current of said MOS transistor, said step of comparing being performed by a voltage feedback loop; and detecting said output current and, in response to said detecting, generating a compensation gate voltage for said MOS transistor to stabilize the impedance of said MOS transistor, as seen at said load terminal, as said load fluctuates, said step of detecting being performed by a current feedback loop, said current feedback loop having a faster response to load fluctuations than said voltage feedback loop. 10. The method of Claim 9 wherein said MOS transistor is an NMOS transistor and said current feedback loop lowers a gate voltage of said NMOS transistor when an increased current through said NMOS transistor is detected. 11. The method of Claim 9 wherein said current feedback loop substantially prevents rapid changes in current through said MOS transistor due to load fluctuations. 12. An output control circuit for a linear voltage regulator comprising: a depletion mode NMOS transistor having a drain, a source, and a gate, said drain being electrically coupled to a first supply voltage, said gate being coupled to a signal for controlling the current flow between said source and drain, said NMOS transistor being controlled by said signal to supply a current to a load at a regulated voltage; a transistor switch having a first current handling terminal connected to said source of said NMOS transistor and a second current handling terminal connected to an output terminal of said voltage regulator, said transistor switch having a control terminal coupled to receive a control signal; and a controller connected to said control terminal of said transistor switch for turning said switch on and off so that said regulated voltage may be selectively applied to said output terminal of said voltage regulator without turning off said NMOS transistor. 13. The circuit of Claim 12 wherein said transistor switch is a PMOS transistor. 14. The circuit of Claim 12 further comprising a feedback circuit for receiving a voltage proportional to said regulated voltage and providing an error signal for controlling the conductivity of said NMOS transistor to adjust said regulated voltage. 15. A method for selectively applying an output voltage to an output terminal of a voltage regulator having a depletion mode pass transistor connected between said output terminal and a voltage source, said pass transistor for conducting current to a load connected to said output terminal, said method comprising the steps of: controlling a transistor switch connected between a current output terminal of said pass transistor and said output terminal of said voltage regulator to selectively apply said current output of said pass transistor to said output terminal of said voltage regulator as said switch is turned on and off, such that said output current is decoupled from said output terminal without turning off said depletion mode pass transistor. 16. The method of Claim 15 wherein said switch is a PMOS transistor and said pass transistor is an NMOS transistor. ™>96/12996 AMENDED CLAIMS PCT/US95 / 12548 [received by the International Bureau on 9 April 1996 (09.04.96); original claims 1 and 9 amended; remaining claims unchanged (4 pages)] What is claimed is: 1. A linear voltage regulator comprising: an MOS transistor connected between a power supply terminal and a load terminal of said linear voltage regulator for providing an output current to said load, said MOS transistor being continually in a conductive state while said output current is being provided to said load; a voltage feedback loop comprising an error amplifier for comparing a feedback voltage to a reference voltage and outputting an error signal to control a magnitude of a gate voltage of said MOS transistor so as to control said output current of said MOS transistor; a current feedback loop comprising a current detector for detecting said output current and, in response to said detecting, generating a compensation gate voltage for said MOS transistor to stabilize the impedance of said MOS transistor, as seen at said load terminal, as said load fluctuates, said current feedback loop having a faster response to load fluctuations than said voltage feedback loop. 2. The voltage regulator of Claim 1 wherein said MOS transistor is an NMOS transistor and said current feedback loop lowers a gate voltage of said NMOS transistor when an increased current through said NMOS transistor is detected. 3. The voltage regulator of Claim 1 wherein said current feedback loop substantially prevents rapid changes in current through said MOS transistor due to load fluctuations. - 22 - 4. The voltage regulator of Claim 1 further comprising a frequency compensation capacitor connected to said load terminal. 6. The voltage regulator of Claim 5 wherein said level shifter is a second PMOS transistor having a source connected to said source of said first NMOS transistor, a drain connected to a second current source, and a gate connected to said drain of said second PMOS transistor, said second PMOS transistor having a threshold voltage substantially equal to a threshold voltage of said first PMOS transistor. 7. The voltage regulator of Claim 5 wherein said control terminal of said third transistor is connected to said drain of said first PMOS transistor through a resistor and capacitor in series. 8. The voltage regulator of Claim 5 wherein said third transistor is a bipolar transistor. 9. A method for generating a regulated voltage and stabilizing an output impedance of a linear voltage regulator comprising the steps of: controlling an MOS transistor connected between a power supply terminal and a load terminal of said linear voltage regulator to provide an output current to said load, said MOS transistor being continually in a conductive state while said output current is being provided to said load; comparing a feedback voltage at said load terminal to a reference voltage and outputting an error signal to control a magnitude of a gate voltage of said MOS transistor so as to control said output current of said MOS transistor, said step of comparing being performed by a voltage feedback loop; and detecting said output current and, in response to said detecting, generating a compensation gate voltage for said MOS transistor to stabilize the impedance of said MOS transistor, as seen at said load terminal, as said load fluctuates, said step of detecting being performed by a current feedback loop,

Inventors: FRANCK STEVEN J, WRATHALL ROBERT S, FRANCK, STEVEN, J., WRATHALL, ROBERT, S.
Applicants: SILICONIX INC, SILICONIX INCORPORATED
Application year: 1995
Main classification: G05F3
IPC codes: G05F3