Gray scale driving device for an active addressed liquid crystal display panel

Abstract: A fluctuation of optical response is restrained and a gray shade display drive is facilitated in a multiple line section method, and the device comprises first means for applying a plurality of row signals represented by a set of orthonormal functions to a group of row electrodes 2 throughout one frame by set sequential scanning for each of selecting periods and second means for sequentially carrying out a dot product computation between the set of orthonormal functions and a set of pixel data, and applying a column signal having a voltage level corresponding to a result of the computation, to each of a group of column electrodes 3 in synchronization with the set sequential scanning for each of the selecting periods. The first means has a vertical driver for applying the row signal, by doubling the rate thereof, to the group of row electrodes and repeating the same set sequential scanning at least for two frames of foregoing and next frames. The second means has a frame memory 6 for holding the pixel data in each frame while dividing it according to a significance of each bit and dot product computing means 8 for reading out the set of held pixel data per significance of each bit and carrying out the dot product computation to generate a column signal component corresponding to the significance of each bit. A horizontal driver 5 divides the column signal components into a significant bit component and a less significant bit component, and distributes one component to the foregoing one frame and the other to the next one frame to compose a column signal which is applied to the group of column electrodes 3.

Description: The present invention relates to a device for driving a plain matrix liquid crystal display panel using STN liquid crystal or the like. More specifically, the present invention relates to a driving device suitable for a multiple line selection method and more particularly to a driving circuit structure suitable for gray shade display (half-tone display) by means of the pulse width modulation and a frame thinning modulation. A plain matrix type liquid crystal display panel is composed of a liquid crystal layer interposed between a group of row electrodes and a group of column electrodes thereby providing pixels in a matrix. Conventionally, such liquid crystal display panel are driven by a voltage averaging method. In this method, the respective row electrodes are sequentially selected one by one, and data signals corresponding to ON/OFF status are supplied to the column electrodes in synchronisation with that timing. Consequently, each pixel receives a high applied voltage for one time slot (1/N of a time interval) within one frame period, during which all of (N number of) the row electrodes are selected, while the same pixel receives a constant bias voltage in the remaining time interval ((N-1)/N of the time interval). If the liquid crystal material used has a slow response, then there can be obtained a brightness corresponding to an effective value of the applied voltage waveform during one frame period. However, if a frame frequency is lowered as the multiplexing number increases, the difference between the one frame period and a liquid crystal response time is reduced, so that the liquid crystal responds to each applied pulse to thereby causing a brightness flicker called a "frame response" phenomenon which degrades the contrast. As means to deal with such a problem of the frame response phenomenon in the voltage averaging method, a "high frequency method" by which a width of pulses of the applied voltage is reduced has been proposed. The frame frequency increases as the pulse width is reduced. Because a voltage pulse during selection is applied in a short period, the next voltage pulse is applied before a transmittance drops, thereby increasing the transmittance of the whole. However, this high frequency method is limited as an increase of strain of waveforms of the applied voltage remarkably damages the uniformity of an image. EP 0507061A describes a LCD addressing system in which the row electrodes are addressed by orthonormal row signals independent of the data to be displayed. The column signals are generated from the collective information state of the pixels in the columns of the display. As a result, the ratio of the peak amplitude to the rms amplitude seen by each pixel is significantly reduced. Hence, the pixels of the display are perceived as having brighter bright states and darker dark states and, therefore, a higher contrast ratio. Recently, a "multiple line selection method" has been proposed as more effective means in dealing with the above-mentioned problem of the frame response phenomenon and is disclosed in Tokkai Hei. 5-100642 for example. In this multiple line section method, each of the row electrodes is not selected one by one in the conventional manner, but a plurality of row electrodes are simultaneously selected to achieve the same effect as the high frequency drive, thereby reducing the above-mentioned problem of the frame response. Being different from single line selection, the multiple line selection requires a specific technique for realising a flicker free display. Namely, it is necessary to arithmetically process original pixel data and supply the processed data to a column electrode. Practically, a plurality of row signals represented by a set of orthonormal functions are applied to the group of row electrodes in sequence of the set during each selecting period. On the other hand, a dot product computation is carried out sequentially between the set of orthonormal functions and a set of selected pixel data, and then a column signal that has a voltage level corresponding to a result of the computation is applied to the group of column electrodes in synchronisation with the set sequential scanning during each selecting period. EP 0604226A describes a liquid crystal display device in which a set of orthonormal row signals are sequentially fed to groups of row electrodes. The driver signals for the row electrodes are computed from a set of dot data and the set of orthonormal signals. The group sequential scanning is repeated several times within one cycle to display a picture, with the orthonormal signals being shifted horizontally or vertically to improve the quality of the displayed picture. The above-mentioned multiple line selection can be also extended for use with a gray shade display. There are a variety of methods for providing a gray shade display. For example, a pulse width modulation and a frame thinning modulation can be easily combined with the multiple line section as disclosed in the above-mentioned Tokkai Hei. 5-100642. In this method, a given pixel data has a plurality of bits and gray shading is displayed therewith. When the dot product computation is carried out between the set of orthonormal functions and the set of pixel data, the set of pixel data is divided by the bits to carry out the computation and to generate a column signal component corresponding to a significance of each bit. Further, the column signal components corresponding to the significance of each bit are arranged in order during each selecting period to compose a column signal, which is applied to a group of column electrodes. At this time, a predetermined gray shade display may be obtained by applying the pulse width modulation or the frame thinning modulation per significance of each bit. In the multiple line section method, basically row signals applied to the group of row electrodes may have any orthonormal waveform; however, all the concurrently selected row electrodes are necessarily scanned by a voltage pulse of the same polarity once within one frame. Meanwhile, the waveform of the column signal applied to each column electrodes is obtained by the dot computation of the pixel data set and the orthonormal signal set as described before. Accordingly, as long as the pixel data represents a random gray shade picture pattern, the bias voltage is randomly distributed throughout the nonselection period within one frame. However, in case when the picture pattern is turned to either of a total white state (all ON) or total black state (all OFF), the bias voltage of the nonselection period is intensively applied at a time slot when all the concurrently selected row electrode are scanned by the voltage pulse of the same polarity. For this, optical response is fluctuated, causing contrast variation dependent on the picture pattern. Other methods have also been disclosed for reducing flicker in display devices having display elements which respond to driver signals to provide a displayed image. For example, WO 94/09473A describes a system for achieving gray scales in a display device including an array of deformable mirrors. The bit weight sequences of the driver signals are split into first and second parts and these parts are then balanced, as symmetrically as possible, about the centre of illumination of a frame period to minimise flicker in the displayed image. Thus, it is an object of the present invention to eliminate the fluctuation of the optical response dependent on the gray shade picture pattern. The following measures have been taken in order to solve the above-mentioned problems of the prior art and to achieve the object of the present invention. According to a first aspect of the present invention there is provided a liquid crystal display panel gray shade driving device in accordance with that claimed in claim 1. Advantageously, the horizontal driving means is arranged to divide the most significant bit column signal component and the one or more remaining bit column signal component(s) into half, respectively, and to distribute each half selected from said most significant bit component and said one or more remaining bit component(s) to the first half frame and the remaining each half to the second half frame to compose a column signal to apply to said group of column electrodes. Preferably, the remaining bit components comprise at least one less significant bit component and said horizontal driving means applies the column signal components using both pulse width modulation and frame thinning modulation with respect to the one or more less significant bit component(s) while it applies the column signal components by pulse width modulation with respect to the most significant bit component. Embodiments of the present invention will now be described with reference to the accompanying drawings, of which: Fig. 1 is a schematic block diagram showing a liquid crystal display panel gray shade driving device of the present invention; Fig 2 is a timing chart for explaining an operation of the gray shade driving device of the present invention; Fig. 3 is a waveform chart of Walsh function for explaining the operation of the same; Figs. 4A and 4B are optical response diagrams for explaining the operation of the same; Figs. 5A through 5E are double-rate waveform charts for explaining the operation of the same; FIG. 6 is a timing chart for explaining the operation of the same; FIG. 7 is a schematic drawing for explaining the operation of the same; FIG. 8 is a table for explaining an operation of the gray shade display of the present invention; FIG. 9 is a waveform chart for explaining the operation of the gray shade display of the same; and FIGs. 10A through 10C are schematic diagrams for explaining the gray shade display adapted to the double-rate driving. According to the present invention, the rate of the row signal is doubled and it is applied to the group of row electrodes and the same set sequential scanning is repeated at least for two frames of foregoing and next frames. Thereby, the rate of the frame frequency is apparently doubled, thus allowing the frame response phenomenon to be restrained. Accordingly, the fluctuation of the optical response may be improved even when the gray shading display patterns are all ON or all OFF. By the way, when the rate of the frame frequency is increased, the selection period is also shortened accordingly. When the gray shade display is carried out, the pulse width modulation is used and the column signal waveform is composed of a set of column signal components having different pulse widths throughout the significant bit to less significant bit components. Because the selection period is shortened along the doubling of the rate of the row signal, the pulse width of the column signal is also reduced. When the column signal is applied while reducing the pulse width thereof, the uniformity of an image is damaged by the increase of distortion of the pulse waveform. Then, according to the present invention, the column signal is composed by dividing column signal components into significant bit and less significant bit components and by distributing one component to the foregoing one frame and the other to the next one frame. Thereby, it becomes possible to accommodate with the doubling of the rate of the row signal without reducing the pulse width of each column signal component. Or, the same effect can be obtained by dividing the significant bit column signal component and the less significant bit column signal component into half, respectively, and by distributing each half selected from the significant bit and less significant bit column signal components into the foregoing one frame and the remaining each half into the next one frame. EMBODIMENT A preferred embodiment of the present invention will be explained below in detail with reference to the drawings. FIG. 1 is a schematic block diagram showing an inventive gray shade driving device of a liquid crystal display panel. As shown in the figure, the inventive gray shade driving device is connected with a plain matrix type liquid crystal display panel 1. The liquid crystal display panel 1 has a flat panel structure in which a liquid crystal layer is interposed between a group of row electrodes 2 and a group of column electrodes 3. STN liquid crystal, for example, can be used as the liquid crystal layer. The gray shade driving device drives in a gradation the liquid crystal display panel 1 having such a structure by using both pulse width modulation and frame thinning modulation methods according to pixel data composed of a plurality of bits. The gray shade driving device is equipped with a vertical driver 4 which is connected with the group of row electrodes 2 to drive them. The gray shade driving device is also equipped with a horizontal driver 5 which is connected with the group of column electrodes 3 to drive them. The gray shade driving device further has a frame memory 6, orthonormal function generating means 7 and dot product computing means 8. The frame memory 6 holds pixel data input in each frame. It is noted that the pixel data represents the density of pixels provided at cross sections of the group of row electrodes 2 and the group of column electrodes 3. The pixel data is composed of a plurality of bits which enables pixel density to be displayed with gray shading in the present invention. In relation to this, the frame memory 6 has a bit plane corresponding to the significance of each bit. The orthonormal function generating means 7 generates a plurality of orthonormal functions which are orthonormal to each other, and supplies sequentially the orthonormal functions in appropriate set patterns to the vertical driver 4. The vertical driver 4 applies a plurality of row signals represented by the sets of orthonormal functions to the group of row electrodes 2 by a set sequential scanning for each selecting period. At this time, the vertical driver 4 applies the row signals to the group of row electrodes 2 by doubling the rate the signal and repeats the same set sequential scanning at least for two frames of foregoing and next frames. As it may be apparent from the above description, the orthonormal function generating means 7 and the vertical driver 4 correspond to the above-mentioned first means. The gray shade driving device further comprises the dot product computing means 8 and a voltage level circuit 12, in addition to the frame memory 6 and the horizontal driver 5, as second means. The second means sequentially carries out a dot production computation of a set of the orthonormal functions and a set of the pixel data and applies a column signal having a voltage level corresponding to that computation result to the group of column electrodes 3 per selection period in synchronization with the set sequential scanning. In concrete, the dot product computing means 8 carries out the predetermined dot product computation by sequentially reading out the set of pixel data stored in the frame memory 6 and forms a column signal component corresponding to a significance of each bit. The horizontal driver 5 composes a column signal which is applied to the group of column electrodes 3 by adequately arranging a column signal component with a significance of bit to which the pulse width modulation is performed and a column signal component with a significance of bit to which the frame thinning modulation is performed. The voltage level necessary for composing the column signal is supplied from the voltage level circuit 12 in advance. It is noted that the voltage level circult 12 supplies a predetermined voltage level also to the vertical driver 4. The vertical driver 4 adequately selects a voltage level in accordance to the orthonormal function and supplies it to the group of row electrodes 2 as the row signal. The gray shade driving device includes memory control means 10 for controlling read/write of pixel data into the frame memory 6. That is, it executes writing per all frame for bits for which the pulse width modulation is performed and executes writing per necessary frame in response to the frame thinning for bits for which the frame thinning modulation is performed. The gray shade driving device has a synchronizing circuit 9 and drive control means 11, in addition to the memory control means 10. The synchronizing circuit 9 makes a pixel data read timing from the frame memory 6 and a signal transfer timing from the orthonormal function generating means 7 synchronize with each other. A desired image is displayed by repeating the set sequential scanning in a frame time interval. The synchronizing circuit 9 controls the timing of the memory control means 10. The memory control means 10 controls read/write of pixel data into the frame memory 6 by each bit plane as described above. The drive control means 11 is controlled by the synchronizing circuit 9 and supplies a predetermined clock signal to the vertical driver 4 to realize the doubling of the rate of the row signal as described above. The drive control means 11 also controls the horizontal driver 5 in response to the doubling of the rate of the row signal. The present invention is characterized in that the vertical driver 4 doubles the rate of the row signal which is applied to the group of row electrodes 2 and repeats the same set sequential scanning at least for two frames of foregoing and next frames under the control of the drive control means 11. In contrast, the horizontal driver 5 divides the column signal component into the significant bit and less significant bit components, distributes one component to the foregoing one frame (hereinafter called the first half frame) and the other component to the next one frame (hereinafter called the second half frame) to compose a column signal which is applied to the group of column electrodes 3. Or, it is possible to arrange it so as to divide the significant bit column signal component and the less significant bit column signal component into half, respectively, and to distribute each half selected from the significant bit and less significant bit column signal components into the first half frame and the other half into the second half frame to compose the column signal which is applied to the group of column electrodes. At this time, the pulse width modulation is applied to the significant bit column signal component and the frame thinning modulation is applied to the less significant bit row signal component. An operation of the gray shade driving device shown in FIG. 1 will be explained below in detail. In order to make it easy to understand the present invention, the principle thereof will be explained at first by exemplifying a case when four lines of row electrodes are concurrently selected with respect to the multiple line section. In order to simplify the explanation, the doubling of the rate of the row signals and the gray-shading of the column signals will not be mentioned here in the discription of the principle. FIG. 2 is a waveform chart of the four-line concurrent driving. F 1 (t) - F 8 (t) denotes row signals applied to respective row electrodes and G 1 (t) - G 3 (t) denotes column signals applied to respective column electrodes. The row signal F is set according to Walsh function which is one of the complete orthonormal functions in (0, 1). The scanning waveform is set to "-Vr" corresponding to "0", set to "+Vr" corresponding to "1" and set to V 0 during a nonselection period. The voltage level V 0 for the nonselection period is set to 0 V. Four lines are selected concurrently as a set such that each set is sequentially scanned from top to bottom. One frame which corresponds to one period of the Walsh function is finished by four times of the set sequential scanning. In a next period, a set sequential scanning is carried out four times while the polarity of the signal is inverted to thereby remove a DC component. The inversion of the polarity is repeated per every two frames, thus completing one cycle. This cycle frequency is set to 30 Hz in accordance to TV standard for example. Accordingly, the frame frequency is doubled to 60 Hz. That is, each frame is repeated 60 times in one second. On the other hand, the column signal applied to each group of column electrodes are dealt with by predetermined dot product computation in which each pixel data is I ij (where "i" denotes a row number of the matrix, and "j" denotes a column number of the matrix). Supposing a case in which pixel data includes not a plurality of bits but a single bit and I ij is set to "-1" when the pixel is ON and is set to "+1" when it is OFF, then the column data signal Gj(t) applied to each column electrode is basically set by carrying out the following dot product computation process: In the above computation, the summation is effected only for the selected rows since the row signal is set to "0" level in the nonselection period. Accordingly, in the concurrent selection of the four lines, the column signal can take five voltage levels. Namely, the column signal requires a certain number of voltage levels equal to "concurrently selected line numbers + one". This potential level is supplied from the voltage level circuit 12 shown in FIG. 1 as described above. FIG. 3 is a waveform chart showing the Walsh function. In the case of the concurrent four-line selection, for example, four Walsh functions from the top are used to form the waveform of the row signals. As can be understood from a comparison between FIG. 2 and FIG. 3, for instance, the row signal F 1 (t) corresponds to the first walsh function. Because the function has a high level across one period, the four pulses of F 1 (t) are arranged in a sequence of (1, 1, 1, 1). F 2 (t) corresponds to the second Walsh function. The function has a high level in a first half of one period and a low level in a second half of one period. Accordingly, the pulses contained in F 3 (t) are arranged in a sequence of (1, 1, 0, 0). Likewise, the signal F 3 (t) corresponds to the third Walsh function, so that the pulses are arranged in a sequence of (1, 0, 0, 1). Further, F 4 (t) corresponds to the fourth Walsh function, so that the pulses are arranged in a sequence of (1, 0, 1, 0). As can be understood from the above description, the set of the row signals applied to one set of the row electrodes are represented by an adequate combination pattern (1, 1, 1, 1), (1, 1, 0, 0), (1, 0, 0, 1) or (1, 0, 1, 0) based on the orthonormal relationship. In the case of FIG. 2, the second set receives the orthonormal signals F 6 (t) - F 8 (t) in accordance to the same combination pattern. In a similar manner, the third and further sets receive the predetermined row signals corresponding to the same combination pattern, thus completing one set sequential scanning. One frame is finished by repeating the set sequential scanning by four times. As long as the orthonormal relation is maintained in the multiple line section method, the voltage waveforms applied to the row electrodes may have various combination patterns. However, in the combination pattern indicated in FIG. 2, all of the concurrently selected lines are scanned by +Vr or -Vr once in one frame. For example, in the first set sequential scanning shown in FIG. 2, all the concurrently selected lines are applied with +Vr. Meanwhile, the voltage waveforms applied to the column signal electrodes are computed according to the predetermined dot product equation based on the pixel data. Accordingly, if the matrix pixel data represents a random picture pattern, the bias voltage in the nonselection period is randomly applied in one frame. However, if the picture pattern is placed in either of the all ON state and all OFF state, the bias voltage of the nonselection period is concentrated into a certain period in which all the concurrently selected lines are scanned by +Vr or -Vr. For this, the optical response is fluctuated to cause contrast variation dependently on the picture pattern. FIG. 4 illustrates how the contrast variation occurs dependently on the picture pattern. These graphs schematically represent the optical response and the voltage waveform actually applied to the liquid crystal in the four- line concurrent selection mode. FIG. 4A illustrates a case when a random pattern is represented and FIG. 4B illustrates a case when an all ON pattern is represented. As seen from these graphs, the bias voltage is concentrated into the first set sequential scanning period to thereby generate contrast fluctuation in the all ON pattern. The row signal double-rate drive adopted in the present invention to restrain the fluctuation of optical response will be explained below with reference to FIG. 5. FIG. 5A shows liquid crystal applied voltage levels during the nonselection period in the four-line concurrent selection. In the first set sequential scanning, all four row signals F 1 through F 4 have +1 level. In the all ON state, all the pixel data T ij take -1 level. Accordingly, when the above- mentioned dot product computation is carried out, the row signal takes a level of absolute value 4, which is applied during the nonselection period. In the second set sequential scanning, F 1 and F 2 take +1 level and F 3 and F 4 take -1 level. Accordingly, in the all ON state, the plus and minus parts are canceled, so that a voltage applied during the nonselection period is zero level. Similarly, the voltage applied during the nonselection period is zero level also in the third and fourth set sequential scanning. A waveform chart in FIG. 5C represents it as a graph. In the first set sequential scanning and during the nonselection period ΔT, the voltage of level of absolute value 4 is applied and in the second, third and fourth set sequential scanning, the voltage of level of absolute value 0 is applied during the nonselection period ΔT. One frame is finished by four times of set sequential scanning. When the frame period is 60 Hz as described before, the applied voltage is concentrated into the first set sequential scanning period, so that the frequency component of 60 Hz is intensified as a whole and the frame response becomes conspicuous. Three-line concurrent selection is effective by a certain degree in dealing with this problem. In an example shown in FIG. 5B, three-line concurrent selection drive is carried out using three row signals F 2 through F 4 , except of F 1 . In the first set sequential scanning, a voltage of level of absolute value 3 is applied during the nonselection period. In the second set sequential scanning, there is a difference between the plus and minus parts, so that a voltage of level of absolute value 1 is applied during the nonselection period. Similarly, the voltage of level of absolute value 1 is applied during the nonselection period in the third and fourth set sequential scanning. A waveform chart shown in FIG. 5D represents it as a graph. The voltage of level of absolute value 3 is applied during the nonselection period ΔT in the first set sequential scanning and the voltage of level of absolute value 1 is applied during the nonselection period in the second, third and fourth set sequential scanning. Because the difference of the voltages applied during the nonselection period in the first set sequential scanning and the second through fourth set sequential scanning is reduced to the level of absolute value 2 in the three-line concurrent selection as described above, the 60 Hz component is weakened as a whole and the frame response becomes inconspicuous. The odd-line concurrent selection is generally more effective as compared to the even-line concurrent selection because the voltage applied during the nonselection period can be spread out to each set sequential scanning. Accordingly, the present invention also adopts the odd-line concurrent selection method. However, the 60 Hz component still remains as shown in FIG. 5D even in the odd-line concurrent selection. Then, the rate of the row signal is doubled as shown in FIG. 5E and it is applied to the row electrode in the present invention. That is, the same set sequential scanning is repeated at least for two frames of foregoing and next frames. Consequently, the frame frequency is increased to 120 Hz. The totally same drive is repeated in the first half frame and the second half frame. However, because the rate of the row signal is doubled, the selection period Δt is also reduced to half in the same time. By doubling the rate as described above, the 60 Hz component is eliminated and 120 Hz component appears instead. The frame response can be restrained by increasing the rate of the frame frequency. It should be noted that a horizontal shift drive method has been proposed in order to deal with the above-mentioned fluctuation of the optical response. In the multiple line section method, each group of the multiple lines is sequentially selected to scan the display face from top to bottom. At this time, the phase of the scanning signal waveforms applied to the row electrodes is shifted from that of the row signal waveforms selected just before it. By such an operation, the bias voltage applied to the liquid crystal during the nonselection period is spread out without being concentrated into one frame interval within one frame when all ON or all OFF display is made. This phase difference is effected such that the combination pattern of the waveform applied to the row electrode is phase-shifted at least by one period within the one set sequential scanning period. In the conventional multiple line selection, although the contrast fluctuation is caused as described before when the combination pattern of the orthonormal function is fixed, the optical response is uniformed by shifting the phase of the voltage waveforms of the row signal, thus allowing the frame response to be restrained and the contrast to be improved when all ON or all OFF state. FIG. 6 shows one example of the horizontally phase-shifted driving waveforms. In the concurrent selection of four lines, the voltage waveforms of the row signals are arranged based on the Walsh function such that one phase is shifted every time when four lines are concurrently selected as a set. In FIG. 6, F 1 (t) denotes each scan signal waveform and each set of four lines is selected in set sequential manner to scan the liquid crystal display panel from top to bottom. In the first set sequential scanning, F1, F2, F3 and F4 are set to +Vr, +Vr, +Vr and +Vr, respectively. The next set of F5, F6, F7 and F8 are set to +Vr, +Vr, -Vr and -Vr, respectively, which are shifted by one phase from the preceding set. In similar manner, the row signals after F8 also phase-shifted sequentially are applied to the row electrodes. On the other hand, the respective column signal electrodes are applied with the column signals G 1 (t, G 2 (t) and G 3 (t), which are computed according to the afore- mentioned dot product equation. In contrast to G 2 (t) in the all ON state and G 3 (t) in the all OFF state shown in FIG. 2, the voltage, applied to the column electrode, which has been concentrated into the first set sequential scanning period is generated once per four times of selection and is spread out uniformly throughout the whole one frame. Although the horizontal shift method is effective in restraining the frame response, it has a problem that in the case of video image in which all ON state picture pattern moves in the horizontal direction in contrary, the response speed differs per group of row electrodes concurrently selected, thus deforming the displayed image. FIG. 7 illustrates it schematically. When all ON state picture pattern 21 displayed on a screen 20 moves in the horizontal direction, differences of levels are brought about in a unit of selected number of lines, thus disturbing the uniformity of the image. Accordingly, although the horizontal shift method is effective by a certain degree, it has a drawback in that the discrepancy of the response speeds in the vertical direction appears. On the other hand, the frame response can be restrained and no discrepancy of the response speeds in the direction appears by adopting the odd-line concurrent selection method and by driving by doubling the rate of the row signal in accordance to the present invention. The driving method in which the row signal double rate drive and the column signal gray shade drive are combined, the main subject of the present invention, will be explained below. When the gray shade display is carried out in accordance to the present invention, each pixel data has a structure of a plurality of bits. The dot product computation in this case will be explained below. FIG. 8 shows a case when eight gradation level display is made by inputting pixel data composed of three bits for example. As shown in FIG. 8, each pixel data has a first bit which corresponds to a significant bit, a second bit which corresponds to a less significant bit and a third (zero-th) bit which corresponds to a least significant bit. Each bit can take a binary value of 0 or 1. When the three bits are all 0, it represents the lowest 0-th gradation and when the three bits are all 1, it represents the highest seventh gradation. A desirable half-tone display may be obtained depending on the value which each bit takes. The dot product computation described above is carried out to the pixel data having such three-bit structure by dividing per significance of bit. This is, the dot product computation is carried out initially to the set of the first bits with the set of the orthonormal functions to generate a column signal component corresponding to the most significant bit. Next, the similar dot product computation is carried out between the set of the second bits and the set of the orthonormal functions to generate a column signal component corresponding to the less significant bit. Finally, the similar dot product computation is carried out between the set of the zero-th (third) bits and the set of the orthonormal functions to generate a column signal component corresponding to the least significant bit. FIG. 9 illustrates a case when the column signal components generated as described above are arranged plainly to make a column signal. In the graph in FIG. 9, the horizontal axis represents an elapsed time t and the vertical axis represents a voltage level of a column signal G(t). As described before, the column signal G(t) takes a predetermined voltage level according to the result of the dot product computation. The column signal G(t) contains three column signal components g2, g1 and g0 corresponding to three bits contained in the pixel data within one selection period Δt. The first column signal component g2 is what has been dot-product computed by using the set of first bits shown in FIG. 8 and corresponding to the most significant bit. The next column signal component g1 corresponds to the less significant bit, i.e. the second bit shown in figure 8. The final column signal component g0 corresponds the least significant bit, i.e. the third bit shown in figure 8. In the present invention, the pulse width modulation is applied to the most significant bit and the less significant bit and the frame thinning modulation is applied to the least significant bit. Due to that, a pulse width P2 of the column signal component g2 which corresponds to the most significant bit is the largest. A pulse width P1 of the next column signal component g1 which corresponds to the less significant bit is half of P2. As for the column signal component g0 which corresponds to the least significant bit, its pulse width P0 becomes half of P1 if the pulse width modulation is applied. However, because the frame thinning modulation is applied to the column signal component g0 corresponding to the least significant bit of the pixel data, the pulse width P0 of the column signal component g0 is equal with the pulse width P1 of the column signal component g1 of the less significant bit of the pixel data which is above that by one. By actually outputting the column signal component g0 once per two frames in the arrangement described above, the effective pulse width thereof becomes half of P0 and ½ gradation may be realised when it is averaged throughout each frame. The extreme reduction of the pulse width may be prevented and the burden in designing the circuit may be reduced by applying the frame thinning modulation to the column signal component g0 corresponding to the least significant bit as described above. It should be noted that the present invention is not confined only to the arrangement described above. For example, the significance of bit to which the frame thinning modulation is applied is freely selected and ¼ gradation may be realized, not only the ½ gradation. In the case of the ¼ gradation, the frame thinning is carried out once per four times. By the way, the selection period Δt becomes half when the rate of the row signal is doubled. Accordingly, the pulse width P of each column signal component is also divided into half, respectively. When the column signal shown in FIG. 9 is used as it is in such a states, the pulse width of the less significant bit becomes extremely narrow, thus increasing the burden in designing the circuit. Then, the column signal is also adequately processed in accordance to the doubling of the rate of the row signal to prevent the pulse width from being extremely reduced. This point will be explained in detail with reference to FIG. 10. FIG. 10A schematically shows a rate of the pulse width of each column signal component taking in one selection period Δt. P2 takes a half of Δt. P1 also takes a quarter of Δt and P0 also takes a quarter of Δt. Accordingly, if P2 is divided into P21 and P22, each divided part takes a quarter of Δt. In other words, P21, P22, P1 and P0 all have the same pulse width. The pulse width is dispersed using that. FIG. 10B shows a first example of the dispersion. As described before, when the rate of the row signal is doubled and it is applied to the group of row electrodes, the same set sequential scanning is repeated at least two times for the first and second half frames. The selection period of both the first half frame and the second half frame becomes a half of the original selection period Δt. In this example, the original column signal is divided into a significant bit side (P2) and less significant bit side (P1, P0) and one component (P2) is distributed to the first half and the other (P1, P0) to the second half frame to compose a column signal which is then applied to the group of column electrodes. Thereby, it becomes possible to accommodate with the double-rate drive of the row signal without reducing the pulse width of each column signal component. FIG. 10C shows another example. In this case, the significant bit column component (P2) is divided into P21 and P22. Similarly, the less significant bit column signal components (P1 and P0) are divided into P1 and P0. Then, each half component (P21 and P1) is selected from the significant bit and less significant bit components to distribute to the first half frame and to distribute the remaining each half (P22 and P0) to the second half frame to compose a column signal which is then applied to the group of column electrodes. Thereby, it becomes possible to accommodate with the double-rate drive of the row signal without reducing the pulse width of each column signal component. As described above, according to the present invention, the row signal is applied to the group of row electrodes by doubling the rate thereof and the same set sequential scanning is repeated at least for two frames of foregoing and next frames. Thereby, the rate of the frame frequency can be increased, thus allowing the frame response to be restrained. Further, the column signal is distributed to the first half frame and the second half frame in response to the doubling of the rate of the row signal to allow the gray shade display without reducing the pulse width.

Claims: A liquid crystal display panel gray shade driving device for driving, according to given pixel data composed of a plurality of bits, a liquid crystal display panel having pixels in a matrix and comprising a liquid crystal layer interposed between a group of row electrodes and a group of column electrodes, said device comprising: first means for applying a plurality of row signals having a frame frequency and being represented by a set of orthonormal functions to said group of row electrodes (2) throughout a number of frame periods by set sequential scanning for each frame period; and second means for sequentially carrying out a dot product computation between said set of orthonormal functions and a set of pixel data, and applying a column signal having a voltage level corresponding to a result of the computation, to each of said group of column electrodes (3) in synchronization with the said sequential scanning for each frame period; and wherein said first means has orthonormal function generating means (7) for forming said plurality of row signals and vertical driving means (4) for doubling the frame frequency of said row signal to apply to said group of row electrodes (2) and repeating the same set sequential scanning at least twice during each frame period, thereby to provide, for each frame period, a first half frame and a second half frame; and said second means has: a frame memory (6) for holding the pixel data in each frame period while dividing it according to the significance of each bit; dot product computing means (8) for reading out the set of held pixel data per significance of each bit and carrying out the dot product computation to generate a column signal component (g0, g1, g2) corresponding to the significance of each bit; and horizontal driving means (5) for; dividing said column signal components (g0, g1, g2) into a most significant bit component (g2) and one or more remaining bit components (g0, g1) and including a least significant bit component (g0); distributing the most significant bit component (g2) to the first half frame and the one or more remaining bit component(s) (g0, g1) to the second half frame to compose a column signal to apply to said group of column electrodes; and subjecting the least significant bit component (g0) to frame thinning modulation wherein said least significant bit component (90) is output once per plurality of frames . A liquid crystal display panel gray shade driving device according to claim 1, characterised in that the horizontal driving means (5) is arranged to divide the most significant bit column signal component (g2) and the one or more remaining bit column signal component(s) (g0, g1) into half, respectively, and to distribute each half selected from said most significant bit component (g2) and said one or more remaining bit component(s) (g1) to the first half frame and the remaining each half to the second half frame to compose a column signal to apply to said group of column electrodes. The liquid crystal display panel gray shade driving device according to claim 1 or 2, characterized in that the remaining bit components comprise at least one less significant bit component (g1) and said horizontal driving means (5) applies the column signal components using both pulse width modulation and frame thinning modulation with respect to the one or more less significant bit component(s) (g1) while it applies the column signal components by pulse width modulation with respect to the most significant bit component (g2).

Inventors: HOSHINO MASAFUMI, MATSU FUJIO, YAMAMOTO SHUHEI, HOSHINO, MASAFUMI, MATSU, FUJIO, YAMAMOTO, SHUHEI, HOSHINO, MASAFUMI, C/O SEIKO INSTRUMENTS INC., MATSU, FUJIO, C/O SEIKO INSTRUMENTS INC., YAMAMOTO, SHUHEI, C/O SEIKO INSTRUMENTS INC.
Applicants: SEIKO INSTR INC, SEIKO INSTRUMENTS INC.
Application year: 1995
Main classification: G09G3
IPC codes: G09G3, G02F1