Interface between a cpu and an interrupt controller

Abstract: A data processor comprises a CPU (100) and an interruption controller (200) connected with control signal lines (201, 101, 102). The CPU (100) changes signal level at a control signal line in response to an interruption request. The interruption controller (200) executes the interruption control at the timing of rising or falling of the level with detecting a change of the signal level at said control signal line.

Description: BACKGROUNDS OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a data processor used in a microcomputer, and particularly relates to a data processor for interrupt processing between the central processing unit (CPU) and the interrupt controller. DESCRIPTION OF THE RELATED ART A data processor of this kind for interrupt processing between the CPU and the interrupt controller is usually provided with several control signal lines connecting the CPU and the interrupt controller. Fig. 3 is a block diagram to show the configuration of a conventionally used typical data processor. In the data processor shown in the figure, instructions are executed under the control by a microprogram, which is a kind of software. The microprogram is at the memory space called a micro ROM (not shown) in a CPU 300. Various control signals are generated by execution of the microprogram. Specifically, the instruction codes read from an internal ROM are stored in the instruction queue (not shown) in the CPU 300. The output from the instruction queue specifies a certain address and the data for it in the micro ROM. When the specified data is active, the control signal corresponding to that data is controlled to be "1". Similarly, control signals from the CPU 300 to an interruption controller 400 are generated according to the microprogram. In the data processor shown in the figure, the CPU 300 generates control signals including interrupt scanning signal (CLRIP) 301 and interrupt scanning signal (CLRMS) 302, interrupt flag clear signal (CLRIF) 303, execution address acceptance signal (OEVC) 304 and interrupt priority re-judgment signal (RESCAN) 305 and sends them to the interrupt controller 400 at a certain timing via applicable control signal lines. Fig. 4 is an output timing chart of the control signals in a conventional data processor of Fig. 3. Referring to this figure, the operation of the data processor shown in Fig. 3 is described below. The interrupt controller 400 firstly outputs an interrupt request signal (INTRQ) 401 to the CPU 300. Upon receipt of the interrupt request, the CPU 300 generates the interrupt flag clear signal (CLRIF) 303 to clear up the interrupt flag (not shown) in the interrupt controller 400 corresponding to the received interrupt request and outputs such signal to the interrupt controller 400. To receive the execution address of the interrupt routine from the interrupt controller 400, the CPU 300 generates the applicable control signal (OEVC) 304 to be output to the interrupt controller 400. The interrupt controller 400 outputs, at the same timing as the input of the control signal OEVC 304, the applicable execution address to the CPU 300 via the internal bus (not shown). After the interrupt controller 400 has its interrupt flag cleared or otherwise changes its status, the CPU 300 generates the interrupt priority re-judgment signal (RESCAN) 305 to be output to the interrupt controller 400. Finally, the CPU 300 generates, for output to the interrupt controller 400, the interrupt scanning signal (CLRIP) 301 upon completion of interrupt by a user program and the interrupt scanning signal (CLRMS) 302 upon completion of interrupt by the microprogram respectively and returns to the ordinary processing. Thus, the interrupt processing is executed. Considering the recent situation where a higher operation speed is desired in various electronic devices, instruction execution speed in a data processor as described above may be improved by changing its configuration. Instead of the microprogram method controlling the instruction execution by the microprogram, the hard wired method having signal lines for each of the control signals may be adopted for a higher speed. If such a method is adopted, it generates the control signal by, for example, decoding the instruction codes. However, a conventional data processor as above uses many control signals sent from the CPU to the interrupt controller as described above. If it adopts the hard wired method, it requires increased hardware to decode all instruction codes, which may result in massive equipment. There has been a prior art suggested to eliminate the above drawback in a conventional data processor, which relates to a data processor with reduced control signal lines using the signal level change at the signal lines as the control signals. Such a data processor is, for example, disclosed in the Japanese Unexamined Patent Publication (Kokai) No. Showa 63-126035, "Semiconductor Integrated Circuit Device". Fig. 5 is a block diagram to show the configuration of a data processor disclosed in the above laid-open print and Fig. 6 is a timing chart to show the operation at the data processor of Fig. 5. Referring to the figures, the operation of the data processor is described below. Suppose an interrupt request from a peripheral circuit I/O to the CPU first. Upon generation of an interrupt request, the peripheral circuit I/O charges up a control signal line for IRQ/Reverse ACK so that the signal level changes from low to high synchronizing with the clock signal 2 among the dual system clock signals 1 and 2, and sends the signal as the interrupt request signal IRQ to the CPU 500. The CPU 500 fetches the signal level change at the timing of the clock signal 1 and judges whether to accept the interrupt. If it determines to accept the interrupt, synchronizing with the clock signal 1, changes the level at the above control signal line IRQ/Reverse ACK from high to low and sends the acknowledge signal to the peripheral circuit I/O. Thus, by utilizing the signal level change as the interrupt request signal and the acknowledge signal, the number of signal lines can be reduced. However, a conventional data processor as shown in Fig. 5 operates with the two-phase system clock signal. It involves technical problems such as clock skew adjustment and it is difficult to satisfy the recent wish for a higher operation speed. "Der lnterrupt-Controller-ein Baustein, der für Ordnung sorgt", in Elektronik, Vol. 28, No. 10, 1979, München, pages 73 to 80 by Horst Wältring discloses the operation of a conventional interrupt controller. The article "High Performance Peripherals for the M68000 Family", published in Mini-Micro Conference Record, Nov. 8, 1983, San Francisco, CA, pages 1 to 17 by Robert Beims discloses the operation of an interrupt controller being a member of the Motorola M68000. EP-A-426 331 discloses an interrupt control system, wherein a programmable interrupt controller having a plurality of interrupt request inquest inputs and an interrupt request output for connection to a central processing unit (CPU) includes means for interrupting the CPU over the interrupt request output responsive to an interrupt request from any one of the interrupt request inputs and a priority resolver for assigning a priority position to each of the interrupt request inputs to create an interrupt priority hierarchy. The interrupt controller is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive. SUMMARY OF THE INVENTION It is a first object of the present invention to provide a data processor which can facilitate the adoption of the hard wired method by reducing the number of control signal lines for interrupt processing with solving the conventional problem above. It is a second object of the present invention to provide a data processor which can, in addition, easily realize a higher operation speed. According to one aspect of the invention, a data processor as defined in claim 1 is provided. Preferred constructions are defined in claims 2-6. According to a further aspect of the invention, a data processing method as defined in claim 7 is provided. Preferred embodiments are defined in claims 8 and 9. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to be limitative to the invention, but are for explanation and understanding only. In the drawings: Fig. 1 is a block diagram to show the configuration of a data processor according to an embodiment of the present invention; Fig. 2 is a time chart to show the operation of the above embodiment; Fig. 3 is a block diagram to show the configuration of a conventional data processor; Fig. 4 is a time chart to show the operation of the data processor shown in Fig. 3; Fig. 5 is a block diagram to show the configuration of another conventional data processor; and Fig. 6 is a time chart to show the operation of the data processor shown in Fig. 5. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the attached figures, a preferred embodiment of the present invention is described in details. Fig. 1 is a block diagram showing the configuration of a data processor according to an embodiment of the present invention. As shown in the figure, a data processor of this embodiment has a CPU 100 and an interrupt controller 200 connected with three control signal lines. Among the three control signal lines, the first signal line transmits an interrupt request signal (INTRQ) 201 from the interrupt controller 200 to the CPU 100, the second signal line sends an acknowledge signal (INTAK) 101 from the CPU 100 to the interrupt controller 200 and the third signal line sends a scanning signal (CLRIP) 102 from the CPU 100 to the interrupt controller 200. The interrupt scanning signal here is a control signal to activate, upon completion of the interrupt, the re-judgment process for interrupt priority at the interrupt controller 200. Re-judgment of the interrupt priority is executed upon any change of status at the interrupt controller 200 including execution of an interrupt registered to the interrupt controller 200. The data processor of this embodiment has a configuration according to the hard wired method. Thus, these signal lines connect the CPU 100 and the interrupt controller 200 physically and electrically. Note that this figure shows only the characteristic configuration of this embodiment and omits other sections. It is needless to say that the processor actually has busses for data and address transmission between the CPU 100 and the interrupt controller 200 and peripheral circuit I/O to connect the interrupt controller 200 and various peripheral circuits. When an interrupt request signal is input from the interrupt controller 200, the CPU 100 receives the interrupt request and outputs the acknowledge signal (INTAK) 101 at a predetermined timing. The acknowledge signal (INTAK) 101 changes the signal level at the second signal line and by that rising or falling of the level, sends acknowledgement to the interrupt controller 200. The interrupt controller 200 is provided, as shown in the figure, with an interrupt request output section 210 to output the interrupt request signal (INTRQ) 201 to the CPU 100, an interrupt flag clear section 220 to receive the acknowledge signal (INTAK) 101 from the CPU 100 and execute certain processing, an interrupt vector output section 230 and a priority judgment activate section 240. The interrupt request output section 210 represent functional means to realize a function similar to the interrupt request signal output function in a conventional interrupt controller 200. It outputs the interrupt request signal (INTRQ) 201 to have the CPU 100 execute the interrupt at a predetermined timing via the first signal line. The interrupt flag clear section 220 clears the interrupt flag 221 upon receipt of the acknowledge signal from the CPU 100. In other words, when the CPU 100 changes the signal level at the second signal line, the interrupt flag clear section 220 detects the rising or falling of the level and clears the interruption flag 221. The interrupt vector output section 230 outputs an interrupt vector, which is the address of the interrupt routine, upon receipt of the acknowledge signal from the CPU 100 via an address bus (not shown). In other words, when the CPU 100 changes the signal level at the second signal line, the interrupt vector output section 230 detects the rising or falling of the level and outputs an interrupt vector. The priority judgment activate section 240 activates, upon receipt of the acknowledge signal from the CPU 100, the priority re-judgment process as a step of the procedure to return to the ordinary processing. Specifically, the priority judgment activate section 240 activates the priority re-judgment process upon any change of status at the interrupt controller 200 including clearance of the interruption flag 221. It does not activate the process at the same timing as the interrupt flag clear section 220 and the interrupt vector output section 230, but after the activation of the interrupt flag clear section 220 and the interrupt vector output section 230 in response to a first change of the signal level at the second signal line. Upon a second change of the signal level at the second signal line, it detects the falling or rising of the signal level and activates the priority re-judgment process. The priority judgment activate section 240 also activates the priority re-judgment process when an interrupt scanning signal (CLRIP) 202 is input from the\ CPU 100 via the third signal line. Fig. 2 is a time chart to show how the control signals are transmitted in a data processor with the configuration as described above. Referring to this figure, the operation of this embodiment is described below. First of all, the interrupt request output section 210 in the interrupt controller 200 outputs the interrupt request signal (INTRQ) 201 via the first control signal line, synchronizing with the clock signal . The CPU 100, upon input of the interrupt request signal (INTRQ) 201, determines whether to accept the interrupt request or not. When it determines to accept the interrupt request, it changes, synchronizing with the clock signal , the level of the acknowledge signal (INTAK) 101 at the second control signal line 32 from low (initial setting) to high. The interrupt flag clear section 220 of the interrupt controller 200 detects the rising of the level for the acknowledge signal (INTAK) 101 and clears the interrupt flag 221 synchronizing with the clock signal . At the same time, the interrupt vector output section 230 detects the rising of the level for the acknowledge signal (INTAK) 101 and, synchronizing with the clock signal , outputs the interrupt vector, which is the address of the applicable interrupt routine, via the address bus not shown. Next, the CPU 100 changes, at a certain timing such as upon acknowledgement of interrupt vector input, the level of the acknowledge signal (INTAK) 101 from high to low synchronizing with the clock signal . The priority judgment activate section 240 of the interrupt controller 200 detects the falling of the acknowledge signal (INTAK) 101, and activates the priority judgment process (interrupt scanning) synchronizing with the clock signal . Upon completion of interrugt processing, the CPU 100 outputs the interrupt scanning signal (CLRIP) 102 via the third control signal line when the instruction to return from the interrupt routine is executed so as to return to the ordinary processing. The priority judgment activate section 240 of the interrupt controller 200 detects the falling of the interrupt scanning signal (CLRIP) 102 and activates the priority judgment process (interrupt scanning) synchronizing with the clock signal . Thus, in a data processor according to the present invention, the number of signal lines are reduced by utilizing level changes at the signal lines as the control signals. In the above embodiment, three control signal lines are sufficient to transmit all control signals. This facilitates adoption of the hard wired configuration, which leads to a higher speed data processor. Further, a data processor according to the present invention is characterized by the single-phase synchronization signal. It is free from technically difficult problems such as clock skew adjustment, which is observed in a data processor using the two-phase clock signal. This enables a data processor operating at a sufficiently high speed. Still further, a data processor according to the present invention does not use a dynamic charge-up circuit to change the signal level. This reduces the hardware for charging up, which results in a smaller size and a lower cost.

Claims: A data processor having a CPU (100) and an interrupt controller (200) which are electrically interconnected by control signal lines wherein said interrupt controller comprises means for maintaining an interrupt flag, outputting an interrupt vector, determining priority of registered interrupts and request output means (210) for outputting an interrupt request to said CPU; said CPU outputting an interrupt acknowledge signal to said interrupt controller in response to an interrupt request signal from said interrupt controller; characterized in that said interrupt controller (200) comprises first means (220) for clearing said interrupt flag at a level change of said interrupt acknowledge signal to an active level, second means (230) for outputting said interrupt vector at a level change of said interrupt acknowledge signal to an active level and third means (240) for determining priority of registered interrupts at a level change of said interrupt acknowledge signal to an inactive level. A data processor as set forth in claim 1, wherein said CPU (100) and said interrupt controller (200) synchronize with the single phase clock signal. A data processor according to claim 1 or 2, wherein said first means (220) further comprises means for checking for any level change of the signal at the signal lines output from said CPU (100) in response to said interrupt request and for clearing interrupt flag corresponding to the interrupt routine for which the signal is sent at the timing of rising or falling of the signal level. A data processor according to claim 1 or 2, wherein said second means (230) further comprises means for checking for any level change of the signal at the signal lines output from said CPU (100) in response to said interrupt request and for sending interrupt routine address at the rising or falling timing of said signal level. The data processor according to claim 1 or 2, wherein said third means (240) further comprises means for checking for any level change of the signal at the signal lines output from said CPU (100) in response to said interrupt request and for determining priority of registered interrupts at the falling or rising of said signal level after sending of said interrupt routine address. A data processor according to claim 1 or 2, wherein said control signal lines comprise; a first signal line (201) to send the interrupt request signal from said interrupt controller to said CPU, a second signal line (101) to send the control signal, which is ckecked for any level change by said first means (220), said second means, for instructing interrupt processing execution from said CPU to said interrupt controller in response to said interrupt request, and a third signal line (102) to send the control signal for instructing execution of the processing after completion of interrupt from said CPU to said interrupt controller, said CPU (100) changing the signal level at said second signal line (101), and said interrupt controller (200) executing the interrupt control upon detection of a signal level change at said second signal line (101). A data processing method for interrupt control between a CPU (100) and an interrupt controller (200), which are electrically interconnected by control signal lines wherein said interrupt controller (200) comprises a first means (220) for clearing an interrupt flag, a second means (230) for outputting an interrupt vector and a third means (240) for activating an interrupt scanning signal, comprising the steps of: outputting an interrupt request signal (INTRQ) from said interrupt controller (200) to said CPU (100) via said signal lines; determining by said CPU (100) whether to accept said interrupt request or not; if said interrupt request is accepted by said CPU (100), changing to and outputting an active level of an interrupt acknowledge signal (INTAK) from said CPU (100) to said interrupt controller (200) via said signal lines; detecting changes of said level of said interrupt acknowledge signal at said signal lines, output from said CPU (100) in response to said interrupt request by said interrupt controller (200); characterized in that if any level change of said interrupt acknowledge signal is detected by said interrupt controller (200): clearing said interrupt flag at a level change of said interrupt acknowledge signal to an active level by said first means (220), and outputting said interrupt vector at a level change of said interrupt acknowledge signal to an active level by said second means (230); and after sending said interrupt vector and detecting a further change of said level of said interrupt acknowledge signal to an inactive level activating a priority judgement process by said third means (240). A data processing method according to claim 7, wherein the method further comprises a step of also activating a priority judgement process by said third means (240), if an interrupt scanning signal (CLRIP) is input from said CPU (100) via said signal lines. A data processing method according to claim 7 or 8, wherein said CPU (100) and said interrupt controller (200) are synchronizing with a single phase clock signal.

Inventors: NAGASAKI KAZUNORI, NAGASAKI, KAZUNORI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1995
Main classification: G06F13
IPC codes: G06F9, G06F13