Multiplication circuit

Abstract: A multiplication circuit comprises a plurality of the first switching means for receiving a common analog input voltage and a reference voltage and for alternatively outputting the input voltage or the reference voltage, the first capacitive coupling with a plurality of capacitances for receiving outputs of the first switching means are inputted, the first inverted amplifier for receiving an output of the first capasitive coupling, an output of the first inverted amplifier being fed back to its input; the second inverted amplifier for receiving the output of the first inverted amplifier, an output of the second inverted amplifier being fed back to its inputand characterized in that one or more of the capacitances in the first capacitive coupling is connected to the second capacitive coupling with a plurality of capacitances and that a plurality of the second switching means are connected to each capacitances of the second capacitive coupling, the second switching means alternatively outputting the analog input voltage or the reference voltage.

Description: Field of the Invention The present invention relates to a multiplication circuit for multiplying an analog voltage by a multiplier so as to output an analog voltage as a multiplication result. Background of the Invention The inventors of the present invention have proposed a multiplication circuit for analog voltage in Japanese Patent Application Hei No. 04-357672 and US-A-5,381,352. As shown in Figure 2, this multiplication circuit includes a) a plurality of switching means SW1 to SW8 to which an analog input voltage is inputted, b) a capacitive coupling CP for integrating outputs of the switching means with weighting and c) 2 stages inverted amplifier for stabilizing an output of the capacitive coupling. The capacitive coupling consists of a plurality of capacitances with capacities corresponding to weights of bits of binary number, and the switching means are controlled by signals corresponding to bits of the multiplier. In order to improve the resolution of the multiplier in the multiplication circuit, a lot of levels of capacities are necessary for the capacitances in the capacitive coupling. In a large scale integrated circuit, a capacitance is usually shaped by a plurality of unit capacitances parallelly connected, so a large number of unit capacitance are needed for the capacitances in the capacitive coupling. Then, the circuit size becomes large. US-A-4,654,815 describes a multiplying digital to analog converter means using switching means and capacitive coupling means. Summary of the Invention The present invention is invented so as to solve the above problems and has the object to provide a multiplication circuit in which a multiplier of high resolution is easily defined without increasing the circuit size. According to the present invention, a plurality of capacitive couplings are sequentially provided for defining a multiplier so that the weighting by the capacitive coupling is performed a plurality of times for one input voltage. Brief Description of the Drawings Figure 1 is a circuit diagram of a multiplication circuit of the first embodiment according to the present invention. Figure 2 is a block diagram showing a conventional multiplication circuit. Preferred Embodiment of the Invention Hereinafter, an embodiment of a multiplication circuit according to the present invention is described with referring to the attached drawings. In figure 1, a multiplication circuit M has sequential inverted amplifiers INV1 and INV2 of 2 stages to which feedback capacitances Cf1 and Cf2 are connected for feeding outputs of INV1 and INV2 back to inputs, respectively. A capacitive coupling CP1 with capacitances C4, C5, C6 and C7 is connected to an input terminal of INV1, and an analog input voltage Vin is commonly parallelly connected to each capacitance C4, C5, C6 and C7 through switching means SW4, SW5, SW6 and SW7. A coupling capacitance C01 is connected to an input terminal of INV2 and the output of INV1 is connected to INV2 through C01. Capacitances C7, C6, C5 and C4 of capacitive coupling CP1 have capacities corresponding to weights of bits of binary number of 4 bits, from MSB to LSB. These capacitances are shaped in a LSI ( large scale integrated circuit ) by a plurality of unit capacitances which is the minimum capacitance practically available in the LSI. When a capacity of the unit capacitance is Cu, the capacitances are defined as follows. C7=8Cu, C6=4Cu, C5=2Cu, C4=Cu. The capacitive coupling CP1 further includes a capacitance Cb0 with a capacity of Cu through which CP1 is connected to the second capacitive coupling CP2. Capacitive coupling CP2 is composed of capacitances C3, C2, C1 and C0 which have capacities equal to the weights of the binary bits from MSB to LSB. Here, the capacities are defined as follows. C3=8Cu, C2=4Cu, C1=2Cu, C0=Cu. The input voltage Vin is connected to C3, C2, C1 and C0 through switching means SW3, SW2, SW1 and SW0. INV1 and INV2 are composed of inverters I1, 12 and I3, and I4, I5 and I6 of 3 stages, respectively. INV1 and INV2 have a large gain given by a multiplication of open gains of the 3 stages inverters. Then, the outputs of INV1 and INV2 are stabilized inversion of the inputs of high accuracy. The switching means SW0 to SW7 alternatively outputs the input voltage Vin or a reference voltage Vstd so that Vin is outputted by a switching means when a bit corresponding to the switching means is "1" and Vstd is outputted when the bit is "0". The following formulas (1) and (2) are defined when the bits corresponding to SW0, SW1, SW3, SW4, SW5, SW6 and SW7 are b0, b1, b2, b3, b4, b5, b6 and b7, an output voltage of CP2 (input voltage of Cb0) is Vx, an output voltage of CP1 (input voltage of INV1) is Vb, an output voltage of INV1 (input voltage of C01) is Vo and an output voltage of INV2 is Vout. Vx in formula (1) is substituted by Vx introduced from the formula (2). Then, the following formula (3) is obtained. Capacitances in CP1 and CP2 have capacities shown in formula (4) and (5). The formula (3) is rewritten to be formula (6) according to the relationships of formula (4) and (5). C7:C6:C5:C4:C3:C2:C1:C0:Cb0=8:4:2:1:8:4:2:1:1 The above reference voltage Vstd is a voltage equal to Vd or to the ground voltage, and the output voltage Vo of INV1 is defined as in formulas 7 and 8 in response to the definition of Vstd. i) When Vstd=Vb, then ii) When Vstd=0, then Furthermore, a formula of output Vout from INV2 is calculated in formula 9. Formulas 10 and 11 are obtained by inputting formulas 7 and 8 to formula 9. Cf 2( Vout - Vb ) = - Co 1( Vo - Vb ), Cf 2 = Co 1 Here, generally 2Vb=Vdd. It is a multiplication result of an analog input voltage Vin by a digital multiplier of 8 bits, and an offset of inverter circuits are negligible when the final output is measured based on the reference voltage Vstd. When 0[V] is a reference voltage, it is necessary to consider a minute offset term of a order of (Vb/16 2 ). In the circuit in Figure 2, at least 256 unit capacitances are needed for the capacitive coupling much more than the above embodiment. The first embodiment uses only 32 units capacitances. It is possible to realize multiplication of higher resolution by more stages of capacitive couplings than 2 stages. As mentioned above, a plurality of capacitive couplings are sequentially provided for defining a multiplier so that the weighting by the capacitive coupling is performed a plurality of times for one input voltage, and a multiplication circuit in which a multiplier of high resolution is easily defined without increasing the circuit size.

Claims: A multiplication circuit comprising; a plurality of first switching means (SW4, ... SW7) for receiving a common analog input voltage (Vin) and a reference voltage (Vstd) and for alternatively outputting said input voltage or said reference voltage; a first capacitive coupling (CP1) with a plurality of capacitances (C4, ..., C7) in parallel for receiving outputs of said first switching means (SW4, ..., SW7); each of said plurality of capacitances (C4, ..., C7) being shaped by one or more unit capacitances; a first inverted amplifier (INV1) for receiving an output of said first capacitive coupling (CP1) an output of said first inverted amplifier being fed back to its input; and a second inverted amplifier (INV2) for receiving said output of said first inverted amplifier (INV1), an output of said second inverted amplifier being fed back to its input, characterized in that said first capacitive coupling (CP1) and said first switching means (SW4, ..., SW7) is connected in parallel to a second capacitive coupling (CP2), second switching means (SW0, ..., SW3) and one further capacitance (Cb0); said second capacitive coupling (CP2) having a plurality of capacitances (C0, ..., C3); said second capacitive coupling (P2) being connected to said second switching means (SW0, ..., SW3) alternatively outputting said analog input voltage or said reference voltage; each of said plurality of capacitances (C4, ..., C7) of said first capacitive coupling (CP1) being shaped by the same number of unit capacitances as the respective capacitance (C0, ..., C3) of said second capacitive coupling (CP2). A multiplication circuit as claimed in Claim 1, wherein said second capacitive coupling is connected to a capacitance corresponding to the LSB of the first capacitive coupling.

Inventors: MOTOHASHI KAZUNORI, SHOU GUOLIANG, TAKATORI SUNAO, YAMAMOTO MAKOTO, MOTOHASHI, KAZUNORI, SHOU, GUOLIANG, TAKATORI, SUNAO, YAMAMOTO, MAKOTO, Motohashi, Kazunori, c/o Yozan Inc., Shou, Guoliang, c/o YOZAN Inc., TAKATORI, SUNAO, C/O YOZAN INC., YAMAMOTO, MAKOTO, C/O YOZAN INC.
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1995
Main classification: G06J1
IPC codes: G06G7, G06J1