MOS inverter circuit

Abstract: MOS inverter forming method within a large scale integrated circuit (LSI) for providing a pair of circuits with the same performance each of which comprise a plurality of MOS inverters serially connected from the first stage to the last stage, each the MOS inverters being provided with an input, characterized in that, the input of the MOS inverters of the first stage are adjacently positioned with facing to each other.

Description: The present invention relates to a MOS inverter forming method, especially to a MOS inverter forming method for forming a circuit of a plurality of MOS inverters with the same characteristics serially connected, for example, when a plurality of inverter amplifiers are formed in a large scale integrated circuit (LSI). The inventors of the present invention have proposed a circuit including an inverter amplifier of a MOS inverter in Japanese Patent Application 05-020676 (JP-A-6 215 164) and US Patent Application No. 08/181,118 (US-A-5 420 806). The circuit has a capacitive coupling for multiplying an analog voltage by a digital multiplier by each capacitance of the capacitive coupling. The capacitive coupling outputs an analog voltage to two stages sequential inverter amplifiers INV1 and INV2, or to inverter amplifiers INV3 and INV2 so that the output is stable and high in accuracy. Each inverter amplifier is composed of sequential MOS inverters of 3 stages an output of which is connected through a feedback capacitance to its input. The inverter amplifier keeps stability and linearity of the output by its large open gain as a multiplication of gains of three MOS inverters. However, MOS inverters have some dispersions in the offset voltages, which increase as the distance among MOS inverters extended within the LSI. The offset dispersion influences the output accuracy, especially the first stage inverter among three stages has great influences on the output. US-A-5,306,967 discloses an apparatus for improving signal transmission along parallel lines. Electrical signals propagate uni-directionally along sections of the lines between identical inverter circuits. The inverters are arranged in a staggered fashion. IEEE Trans. Electron Devices, Vol. 39, No. 2, Feb. 1992, pp 275-282 is focused on fabricating matched devices in integrated circuit technologies. Circuits such as operational amplifiers demand well-matched input and load transistors in order to minimize output-voltage offsets. This paper mainly considers mismatch in either the channel lengths or the threshold voltages. It is the object of this invention to provide a MOS inverter circuit with a reduced dispersion of the offset voltages of the MOS inverters. This object is achieved by a MOS inverter circuit according to claim 1. Preferred embodiments are the subject matters of the dependent claims. In the following, preferred embodiments of this invention are described referring to the accompanying figures. The present invention is invented so as to solve the conventional problems and has a purpose to provide a method of forming MOS inverter for controlling the dispersion of offset voltage of MOS inverters to be minimum. According to the present invention, the first stage MOS inverters of two inverted amplifiers are formed adjacent so as to face at their input sides to each other. Figure 1 is a plan view showing the first embodiment of MOS inverter forming method according to the present invention, Figure 2 is a circuit diagram showing the circuitry embodiment suitable for the present invention, Figure 3 is a plan view showing the second embodiment of a MOS inverter circuit, Figure 4 is a circuit diagram showing the third embodiment, Figure 5 is a graph showing a simulation result of the third embodiment, Figure 6 is a circuit diagram showing the fourth embodiment, and Figure 7 is a circuit diagram showing the fifth embodiment. Preferred Embodiment of the Present Invention Hereinafter, an embodiment of MOS inverter forming method according to the present invention is described with referring to the attached drawings. Figure 1 shows a LSI pattern of two inverter amplifiers consisting of three MOS inverters connected in series. The first inverter amplifier INV1 consists of inverters I1, I2 and I3, and the second inverted amplifier INV2 consists of inverters I4, I5 and I6. For each of inverters I1, I2, I3, I4, I5 and I6, there are shaped areas PL and NL made of p-Layer and n-layer, respectively, an input and output lines PS1 and PS2 made of poly-silicon. The voltage Vdd and Vss of the power source and the ground are connected through metal lines M1 and M2 to the area PL and NL, respectively. In figure 1, I1, I2 and I3 are arranged from the right to the left, and I4, I5 and I6 are arranged from the left to the right. The first stage inverter I1 and I4 are shaped at the adjacent positions to each other. This positioning make the offset voltage of the inverters I1 and I4 substantially equal, because adjacent inverters are similar in characteristics according to experiences. In order to realize the adjacent positioning, an output. of the inverter I3 is introduced through a metal line M3 to a position rightward from I1, and is connected to I4. As mentioned above, dispersion of characteristic of the inverter amplifier is controlled to be minimum, and the accuracy is improved. The present invention can be applied not only to the above inverter amplifier but to any circuits including a plurality of MOS inverters connected in series and having the same characteristics. Hereinafter, the second embodiment of MOS inverter according to the present invention is described with referring to the attached drawings. Figure 3 shows a LSI pattern of inverter amplifier INV consisting of 3 stages MOS inverters, I1, I2 and I3. For the inverters I1 and I2, there are shaped a common P-type semiconductor layer PL1 and a common N-type semiconductor layer NL1. P-type semiconductor layer PL2 and N-type semiconductor layer NL2 are shaped for I3. Drain voltage Vdd and source voltage Vss are connected to PL1 and NL1 through contacts C1 and C2. A contact is a metal part for electrical connection passing through an insulating layer. The drain voltage Vdd and source voltage Vss are connected to PL2 and NL2 through contacts C7 and C8. The semiconductor layers PL1 and NL1 are provided with contacts C3 and C4 for an output from the first stage, respectively, and are provided with contacts C5 and C6 for an output from the second stage, respectively. The semiconductor layers PL2 and NL2 are provided with contacts C9 and C10 for an output from the third stage, respectively, from which an output is introduced through a poly-silicon portion PS toward the next stage. A strangulation portion S1 is provided between the contacts C1 and C5 in the semiconductor layer PL1, and a strangulation portion S3 is provided between the contacts C2 and C6 in the semiconductor layer NL1. A strangulation portion S2 is provided between contacts C7 and C9 in the semiconductor layers PL2, and a strangulation portion S4 is provided between contacts C8 and C10 in the semiconductor layer NL2. These strangulation portions S1 and S3 limit an electric current of the output of inverter I2, and it simultaneously decreases parasitic capacity of a transistor included in the inverter I2 by decreasing electric current. A delay of I2 due to the parasitic capacity is diminished, so the responsibility is highly improved. Usually, the strangulation portion causes an instability of output due to strangulated-channel-effects and increase of input side parasitic capacitance. However, these disadvantageous effect are not so influential in the second stage. The above advantageous effect is much more influential than the disadvantageous. On the other hand, the strangulation portions S2 and S4 limit an output electric current of the inverter I3 of the final stage, and it is possible to save electrical power. Also at this stage, there is a possibility of the disadvantageous effect described above. The size of the strangulation portion should be designed so that the advantages are superior to the disadvantages. The present invention is not limited to the circuit of three stage MOS inverters, but can be adopted to a circuit including serially connected MOS inverters for which one common semiconductor layer with the same polarity is formed. Hereinafter, the third embodiment of the present invention is described with reference to the attached drawings. Figure 4 shows an inverter circuit INV1 for summation with weighting. This circuit includes input capacitances C1 and C2 parallelly connected to an input of a MOS inverter I1 of one stage. This embodiment is an embodiment with the capacitance C2 parallel to the capacitance C1. An inverted summation is performed on weighted input voltages inputted to the first and the second capacitances. An output of the MOS inverter I1 is connected through a feedback capacitance Cf to its input. Input voltage (aIN1) and V(aIN2) are connected to input capacitances C1 and C2, and V(OUTp) is generated as an output voltage. A mathematically ideal value V' of inversion of weighted summation is defined in formula 1. Formula 1 V' = Vdd - { C 1 V ( aIN 1) + C 2 V ( a 1 N 2)} / Cf Figure 5 shows a practical output V(OUTp) simulated by Hspice, comparing with V'. In figure 5, V(aIN1), V(aIN2), V(OUT p ) and V' are marked by "□ ", "⋄", "▿", and "▵", respectively. As will be understood from figure 5, when Vdd is equal to 3 V, V(OUT) is a good approximation of V(OUT) in the range of the following formulas 2 and 3. Formula 2 1 V ≦ V(a1N1) ≦ 2 V Formula 3 1 V ≦ V (a1N2) ≦ 2 V As mentioned above, sufficiently high accuracy can be obtained by a one stage MOS inverter. Figure 6 is a circuit of the fourth embodiment. An inverter circuit INV1 has MOS inverts I1 and I2 connected in series each of which is one stage MOS inverter. Parallel input capacitances C1 and C2 are connected to an input of inverter I1. An output of the inverter I1 is connected to its input through a feedback capacitance Cf1, and the output is connected to an input of the inverter I2 through connecting capacitance C4. An input capacitance C3 is further connected to the input of I2, in parallel to the capacitance C4. An output of inverter I2 is connected to the input through feedback capacitance Cf2. Input voltages V(1), V(2) and V(3) are connected to capacitances C1, C2 and C3. Inverter circuit INV1 consists of one stage MOS inverter I1, capacitances C1, C2 and Cf1, and inverter circuit INV2 consists of one stage MOS inverter I2, capacitances C4 and C3. The inverter circuit INV1 generates inverted output of summation of weighted voltages of V(1) and V(2). On the other hand, inverter circuit INV2 generates inverted output V(OUT) of weighted summation of an output from INV1 and the input V(3). A mathematical output of inverted summation with weighting is shown by formula 4 as V'. Formula 4 V' = C 1 C 4 Cf 1 Cf 2 V (1)+ C 2 C 4 Cf 1 Cf 2 V (2)- C 3 Cf 2 V (3)- C 1 C 4 + C 2 C 4 - C 1 C 3 Cf 1 Cf 2 Vb V(OUT) is a good approximation. A simulation result neglected. Figure 7 is a circuit diagram showing the fifth embodiment. A plurality of input capacitances C1 to C4 are connected in parallel to a MOS inverter I1 of one stage. These capacitances are connected to an input voltage V(1) through multi-plexers MUX1, MUX2, MUX3 and MUX4, respectively. The multiplexers connect either the input voltage V(1) or the ground to the capacitances. An output of the inverter I1 is connected to its input through feedback capacitance Cf. By switching the multi-plexers MUX1, MUX2, MUX3 and MUX4, a weight for V(1) is controlled so that an effect of multiplication is obtained. The multiplication result is generated as an output V(OUT) from INV1. Capacity ratio of C1, C2, C3 and C4 and Cf is defined as in formula 5. Formula 5 C1:C2:C3:C4:Cf=1:2:4:8:16 When switching positions of MUX1, MUX2, MUX3 and MUX4 are represented by b0, b1, b2 and b3, which correspond to 0/1 (0:ground side, 1:V(1) side), A mathematically ideal output V' of the circuit is shown in formula 6. Formula 6 V ' = ( b 0 C 1 + b 1 C 2 + b 2 C 3 + b 3 C 4) V (1)/ Cf This is a normalized multiplication result of V(1) multiplied by a binary number consisting of bits b0 to b3. A simulation result is omitted, but V(OUT) is a good approximation of V'.

Claims: A MOS inverter circuit within a large scale integrated circuit, said inverter circuit comprising a pair of inverter sub-circuits (INV1, INV 2) having the same electrical characteristics, each inverter sub-circuit comprising a plurality of MOS inverters (I1, I2, I3, I4, I5, I6) connected in series from a first stage (I1, I4) through a higher stage (I2, I5) to a last stage (I3, I6), each of said inverter sub-circuits having an input, characterized in that said inverter sub-circuits in said pair form a mirror-image of each other and said MOS inverters of said first stages (I1, I4) are positioned adjacent to each other and closer to the mirror plane than said MOS inverters of the higher (I2, I5) and the last (I3, I6) stages. The MOS inverter circuit according to claim 1, characterized by common semiconductor layers (PL1, NL1) elongating across two transistors of said MOS inverters (I1, I2), and in that at least one of said semiconductor layers is provided with a strangulation portion (S1, S2, S3, S4) such that the respective transistor channel width is reduced. The MOS inverter circuit according to claim 1 or 2, wherein the output of one of said inverter circuits (INV1, INV2) is connected through a feedback capacitance to its input.

Inventors: MOTOHASHI KAZUNORI, SHOU GUOLIANG, TAKATORI SUNAO, YAMAMOTO MAKOTO, MOTOHASHI, KAZUNORI, SHOU, GUOLIANG, TAKATORI, SUNAO, YAMAMOTO, MAKOTO
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1995
Main classification: H01L27
IPC codes: H01L27, H03K19