Decentralized system and multiprocessor system

Abstract: The disclosed system comprises a plurality of controlling and calculating devices, each controlling and calculating device has a single common bus that is common to all the controlling and calculating devices and two individual buses, and the respective controlling and calculating devices are connected in series by the respective individual buses, whereby each individual bus is commonly shared by respective two of the plurality of controlling and calculating devices and therefore, input and output circuits to an object system are connected to the individual buses thereby performing the control.

Description: The present invention relates to a system having a plurality of computers and to connection systems in various controlling and calculating devices such as network systems connecting various computers in a traffic system, a general industry system, an in-house information communication system and the like, as well as in a multiprocessor system in a control device digitally controlled by a plurality of microcomputers, etc. Conventionally, a number of network systems and controlling devices using a plurality of computers have been disclosed. Among them, there have been disclosed Japanese Unexamined Patent Publication No. 36854/1992, Japanese Unexamined Patent Publication No. 369069/1992 and the like as examples each achieving a construction having a common bus for connecting a plurality of processors and common resources such as a common memory as well as an individual bus for connecting individual resources to each processor. In the conventional technology, common resources such as a common memory, a disk device or an input and output circuit are connected to a common bus for performing information communication among respective microcomputers, and peripheral input and output circuits inherent to each microcomputer for controlling a control object can be connected to individual buses for each microcomputer. Further, the amount of communication on the common bus can be restricted and the function of a multiprocessor system can be prevented from lowering, by connecting an exclusive communication path communicatable only between respective two microcomputers, to the individual bus interface of each microcomputer to thereby perform information communication between the two microcomputers. However, when one microcomputer is in failure, there has been no device in which the other microcomputer can access to a peripheral input and output circuit connected to the individual bus of the failed microcomputer, and therefore, the processings assigned to the failed computer must be interrupted. That is, in a system dividedly executing processings by a plurality of microcomputers, a total of the system must be stopped. Conversely, a system is well known in which a redundant system is constructed by a multiplication of microcomputers and redundant microcomputers take over the processings of a failed microcomputer when a working microcomputer is in failure, to prevent the system from stopping even if the microcomputer is in failure. However, in this case, it is necessary to prepare redundant microcomputers which are not ordinarily used and accordingly, and the scale of system is magnified. According to the present invention there is provided a decentralized system in which distributed processings are executed by a plurality of controlling and calculating means, each controlling and calculating means being provided with a common bus interfacing means and a first and a second individual bus interfacing means, said common bus interfacing means being connected to a common bus capable of being commonly used by the plurality of controlling and calculating means, wherein the first individual bus interfacing means of each controlling and calculating means is connected to one individual bus interfacing means of one of other controlling and calculating means through a first individual bus, and said second individual bus interfacing means is connected to one of the first or the second individual bus interfacing means of one of the other controlling and calculating means through a second individual bus, whereby said plurality of controlling and calculating means are connected in series through a plurality of the individual buses and expansion of the system is facilitated by providing dual buses of the individual buses and the common bus. With the present invention it is then possible to provide a system having a plurality of large scale computers and microcomputers which are provided with controlling and calculating functions, of which hardware comprises a necessary minimum construction, which may prevent lowering of functions due to an increase in the controlling and calculating function by restricting the amount of communication on buses, which does not stop even when the controlling and calculating function fails and which is also highly expandable. Each individual bus may be accessed from respective two of the controlling and calculating devices by directly connecting the individual bus interfaces of the respective two controlling and calculating devices through a single individual bus, whereby input and output circuits connected to the respective individual buses can be commonly used by the respective two controlling and calculating devices. When communication of information among the respective controlling and calculating devices and that of an input and output information inherent to each controlling and calculating device, are achieved by using only a single common bus, the amount of communication of data on the common bus is increased and bus conflict among the respective controlling and calculating devices is increased which gives rise to the lowering of processing functions. As a counter measure therefor, the common bus may be used for the communication of information among the respective controlling and calculating devices or the communication of the input and output information common to the respective controlling and calculating devices and the individual buses are provided for respective controlling and calculating devices, to thereby achieve doubling of buses, whereby the amount of communication of data on the common bus can be prevented from increasing and the function of the system can be prevented from lowering. Further, the expansion of the controlling and calculating device is facilitated in the construction in which two of the individual bus interfaces are provided to each controlling and calculating device and contiguous controlling and calculating devices are connected in series. Further, by the construction in which two of the individual bus interfaces are provided to each controlling and calculating device and contiguous controlling and calculating devices are connected in series, as stated above, a single individual bus may be commonly shared by respective two controlling and calculating devices. That is, an input and output circuit connected to each individual bus may be commonly owned by the respective two controlling and calculating devices. Accordingly, even in a case where a failure is caused when the operation is being performed by making a single controlling and calculating device access to a peripheral circuit via an individual bus, the operation may be continued without stopping the system since a controlling and calculating device that is connected to a failed controlling and calculating device via the individual bus can access to the same input and output circuit that is connected to the individual bus, in place of the failed controlling and calculating device. In the drawings: Fig. 1 is a structure view of an example of a network system to which the present invention is applied. Fig. 2 is a flowchart explaining processings when an arithmetic and logic unit of the example of Fig. 1 is a microcomputer. Fig. 3 is a flowchart explaining other processings when the arithmetic and logic unit of the example of Fig. 1 is a microcomputer. An explanation will be given of an example of a network system using the present invention in reference to Fig. 1 as follows. In Fig. 1, processings of an object system are distributedly executed by a plurality of arithmetic and logic units 11 through 1n. In this system, the communication of information necessary among the plurality of arithmetic and logic units 11 through In is performed by using a common bus 2. Further, arbitration circuits preventing bus conflict on the common bus 2 from occurring, are included in the arithmetic and logic units 11 through 1n or other circuit connected to the common bus 2, although they are not shown in Fig. 1. Each of the arithmetic and logic units 11 through in is provided with two individual bus interfaces other than the common bus 2, which connect contiguous two arithmetic and logic units in series through individual buses(local buses) 30 through 3n. These individual buses 30 through 3n are connected by input and output circuits (I/O circuit) 40a through 4nn which are necessary for the arithmetic and logic units to which the respective buses are connected, in performing controlling and calculating processings. Thereby, all the input and output circuits 40a through 4nn are accessible by any two of the arithmetic and logic units. Here, there is a arbitration circuit for each individual bus such that conflict of access on the individual bus does not occur between two arithmetic and logic units connected to each individual bus. That is, each of two individual bus interfaces provided to each of the arithmetic and logic units 11 through in, includes the mediating circuit for each individual bus. Accordingly, when all the arithmetic and logic units 11 through In are normally operated, each arithmetic and logic unit executes the controlling and calculating processing in accordance with assigned work based on information from the input and output circuits connected to the individual bus. In such a distributed processing, when a certain arithmetic and logic unit is in failure, other arithmetic and logic units connected in series to the failed arithmetic and logic unit through the individual buses, take over and execute the processing which has been assigned to the failed arithmetic and logic unit. That is, the arithmetic and logic units connected to the failed arithmetic and logic unit through the individual buses, are accessible to the input and output circuits which have been accessed by the failed arithmetic and logic unit in normal operation, and therefore, they can take over the processing of the failed arithmetic and logic unit, and a continuous operation is possible without stopping the system irrespective of the failure of the arithmetic and logic unit. The arithmetic and logic unit in the above example can be realized not only by a general purpose or dedicated computer but also a device having various calculating functions such as a microcomputer. Further, it is clear that the common bus or the individual buses are applicable to either of a parallel communication method and a serial communication method. Further, it is possible to connect information communicating means such as a lower controlling and calculating means or a storing means other than the input and output circuits, to each individual bus. This example is provided with two kinds of buses of the common bus and the individual buses and accordingly, even when abnormality is caused to either one of these buses, the information communication can be performed by other normal buses which amounts to an effect of promoting the reliability. Further, when information communicating means is provided to each individual bus, information which is used only in respective two arithmetic and logic units connected by the individual bus, can be communicated without detouring through the common bus and therefore, the amount of data on the common bus is reduced and accordingly, the function of the system can be prevented from lowering. Next, an explanation will be given of an example of a backup method when the arithmetic and logic unit is in failure in the above example in reference to a flowchart of Fig. 2. In this example, a microcomputer is used as the arithmetic and logic unit, and calculating processings are executed by making two microcomputers access to a single individual bus, and a common memory is used in the common bus as information communicating means of the respective microcomputers. As the content of processing by the microcomputer n, firstly, the microcomputer n executes calculating processing assigned to itself in step 200, and stores the work data of the microcomputer n to the common memory such that other microcomputer n-1 or microcomputer n+1 can perform a backup operation when the microcomputer n is in failure, in step 201. Thereafter, the operation performs a processing with respect to the microcomputer n-1 shown in step 202 to step 207. In step 202, the operation determines whether the microcomputer n-1 has already been in failure by a flag, proceeds to step 203 when it is not in failure and determines whether a failure detection signal is inputted from the microcomputer n-1, and when it is not inputted, the microcomputer n-1 is normally operated and therefore the operation proceeds to a processing with respect to the microcomputer n+1 shown in step 208 and later steps. Meanwhile, when the failure detection signal is inputted in step 203, it is immediately after the failure of the microcomputer n-1 and therefore the operation reads the work data of the microcomputer n-1 from the common memory and prepares to execute the processing of the microcomputer n-1 in step 204. Thereafter, the operation sets the flag showing that the microcomputer n-1 is in failure, in step 205 and proceeds to step 206. In step 206, the microcomputer n executes the calculating processing assigned to the microcomputer n-1 in place of the microcomputer n-1 and stores the work data to the common memory, in step 207. Further, when the microcomputer n-1 has already been in failure in which the flag is set, in step 202, the operation similarly executes the processings of step 206 and later steps. Thereafter, the operation executes processings in case where the microcomputer n +1 is in failure from step 208 through step 213 as in the processing of the microcomputer n-1 shown by steps 202 through 207, by which the backup operation of the microcomputer n+1 can be performed and the processing is finished. As is apparent from the above explanation, when a certain microcomputer is in failure, other two microcomputers connected through two individual buses provided to the failed microcomputer, that is, microcomputers contiguous to both sides of the failed microcomputer are assigned with the processing of the failed microcomputer and execute it. According to this example, the processing of the failed microcomputer can be assigned to the two microcomputers, and therefore, compared with a case where the backup operation is performed by a single microcomputer, the increase in the processing of microcomputer can be halved and accordingly, this example is provided with an effect in which the function of the microcomputers performing the backup operation as well as the function of the system can be prevented from lowering. Next, an explanation will be given of other example of a backup method when a microcomputer is in failure as in the above example in reference to a flowchart of Fig. 3. In this example, each microcomputer executes calculating processing by occupying only a single individual bus among respective two individual buses and accessing thereto in normal operation. That is, in normal operation, the other individual bus is occupied by the other microcomputer and each microcomputer takes over the processing of the failed microcomputer when the other microcomputer is in failure by occupying also the other individual bus. In normal operation, each microcomputer performs the backup operation only with respect to the other microcomputer connected to an individual bus to which the microcomputer does not access. Further, a common memory is used in the common bus as in the above example in the information communication among the respective microcomputers. As the content of processing by the microcomputer n, firstly, the microcomputer n executes calculating processing assigned to itself in step 300, and stores the work data of the microcomputer n to the common memory such that the other microcomputer (microcomputer n-1 in this example) can perform a backup operation when the microcomputer n is in failure, in step 301. Next, the operation investigates an input state of a failure detection signal of a microcomputer n+1 in step 302, and proceeds to step 303 if it is inputted and determines whether the microcomputer n+1 has already been in failure. That is, when the failure detection flag is not set in step 303,the operation determines that it is immediately after the failure of the microcomputer n+1 and sets the failure detection flag in step 304. Next, the operation takes over and executes the processing of the microcomputer n+1 in which, when each microcomputer is processed by sampling, the processing time is increased by an increase due to the processing of the failed microcomputer. Therefore, the operation changes the sampling period of the microcomputer n+1 in compliance with the increase in the processing time in step 305 and thereafter the operation reads the work data of the microcomputer n+1 to prepare to take over the processing in step 306. In step 307, the operation executes the processing of the failed microcomputer n+1, stores the work data to the common memory in step 308 and finishes the processing of the microcomputer n. Further, when the failure detection flag is set in step 303, the operation proceeds to step 307 since the processings immediately after the detection of failure (step 304 to step 306) is not necessary. Meanwhile, when the failure detection signal of the microcomputer n+1 is not inputted in step 302, the operation proceeds to step 309 and determines the failure detection flag. When the failure detection flag. is set in step 309, the operation determines that the microcomputer n+1 has been in failure until that time (that is, recover from failure), and resets the failure detection flag in step 310. The operation recovers the sampling period which has been changed in compliance with the increase in the processing burden during the failure of the microcomputer n+1, to the normal state in step 311 and finishes the processing. Further, when the failure detection flag is in a reset state in step 309, the operation finishes the processing as it is since the microcomputer n+1 is operating normally. In this example, only one individual bus is accessed in the normal operation of microcomputers, and two individual buses are in an accessible state in failure thereof. Accordingly, no bus conflict occurs in the respective two individual buses provided to each microcomputer, and no arbitration circuit for bus is necessary to an individual bus interfacing circuit, which simplifies the hardware. Further, when the processing of the failed microcomputer is assigned to other computers, the system can be operated stably since the sampling period is changed in compliance with the increase in the processing time accompanied by the increase in the burden. Thus the network system has a plurality of controlling and calculating functions and is of a doubled bus construction- having the common bus and the individual buses, a high -speed system can be made possible in which the conflict on the buses is reduced by connecting the input and output circuits inherent to the respective controlling and calculating function to the individual bus, and the respective individual buses are connected to and shared by the two controlling and calculating functions. Therefore, even when one controlling and calculating function is in failure, the input and output circuits connected to each individual bus can be accessed from the other controlling and calculating function. Accordingly, with respect to the failure of the controlling and calculating function, the normal controlling and calculating function connected to the individual bus can take over the controlling processing of the failed controlling and calculating function, which achieves an effect wherein a nonstop operation of the system can be performed with a minimum construction without the multiplication or redundancy of the controlling and calculating functions. Further, each controlling and calculating function is provided with two individual bus interfaces and the respective individual bus interfaces are connected in series to other controlling and calculating units, which provides an effect in which the construction of all the controlling and calculating units can be standardized and the expansion of the controlling and calculating functions in compliance with the scale of the system can easily be achieved. Further, each individual bus is preferably accessible only by two controlling and calculating functions, which achieves an effect in which the processing capability of each controlling and calculating function can be prevented from lowering and a highly efficient system can be realized even when the scale of the system is magnified and the number of controlling and calculating functions is increased.

Claims: A decentralized system in which distributed processings are executed by a plurality of controlling and calculating means (11, 12 ... 1n), each controlling and calculating means being provided with a common bus interfacing means and a first individual bus interfacing means, said common bus interfacing means being connected to a common bus (2) capable of being commonly used by the plurality of controlling and calculating means, characterised in that the first individual bus interfacing means of each controlling and calculating means is connected to one individual bus interfacing means of one of other controlling and calculating means through a first individual bus, and each controlling and calculating means has a second individual bus interfacing means connected to one of the first or the second individual bus interfacing means of one of the other controlling and calculating means through a second individual bus, whereby said plurality of controlling and calculating means are connected in series through a plurality of the individual buses (30, 31, 32 ... 3n) and expansion of the system is facilitated by providing dual buses of the individual buses and the common bus. The decentralized system according to Claim 1, wherein said common bus (2) connected to common storing means communicating information among said plurality of controlling and calculating means (11, 12 ... 1n) and resources commonly used by said plurality of controlling and calculating means, and said plurality of individual buses (30, 31, 32 ... 3n) connected to peripheral inputting and outputting means (40a, 40n, 41a ... 4nn) each performing an input and output processing of information mutually necessary for said plurality of controlling and calculating means or to lower controlling and calculating means. The decentralized system according to Claim 2, wherein each of said plurality of individual buses (30, 31, 32, ... 3n) is connected to storing means or information communicating means along with the peripheral inputting and outputting means (40a, 40n, ... 4nn) necessary for said plurality of controlling and calculating means (11, 12, ... 1n) in calculating processings, said storing means or said information communicating means storing or communicating information used only between respective two of the plurality of controlling and calculating means connected by said individual bus, whereby said plurality of controlling and calculating means transfer information through a communication path doubled by the common bus (2) and said individual buses. The decentralized system according to Claim 1, wherein communication is achieved through said common bus (2) and said plurality of individual buses (30, 31, 32 ... 3n) by using a parallel communication method or a serial communication method. The decentralized system according to Claim 1, wherein in normal operation, said plurality of controlling and calculating means (11, 12 ... 1n) are accessible randomly to the first and the second individual buses connected to the first and the second individual bus interfacing means provided to each of the plurality of controlling and calculating means, and execute controlling and calculating processings by information from peripheral inputting and outputting means connected to said first and said second individual buses, and when one of said plurality of controlling and calculating means is in failure, said one failed controlling and calculating means is separated from said first and said second individual buses by rendering the first and the second individual bus interfacing means provided to said failed controlling and calculating means in a nonoperating state, the first and the second other controlling and calculating means connected to said failed controlling and calculating means through said first and said second individual buses respectively occupy the first and the second individual buses so as to be accessible to said peripheral inputting and outputting means, and said first and said second other two controlling and calculating means dividedly take over the calculation processings of said failed controlling and calculating means thereby enabling to make the controlling and calculating processings continue even when one controlling and calculating means is in failure. The decentralized system according to Claim 1, wherein in normal operation, either one of the first and the second individual bus interfacing means provided to each of said plurality of controlling and calculating means, for example, the first bus interfacing means is rendered in an operating state and connected to the first individual bus, the other one thereof, for example, the second bus interfacing means is rendered in a nonoperating state and connected to the second individual bus, one bus interfacing means provided to the first other controlling and calculating means connected to said first individual bus in an operating state is rendered in a nonoperating state, and one bus interfacing means provided to the second other controlling and calculating means connected to said second individual bus in a nonoperating state is rendered in an operating state, whereby said plurality of controlling and calculating means each performs accessing by occupying only one individual bus and executes the controlling and calculating processings by information from peripheral inputting and outputting means connected to said occupied individual bus, and when one of said plurality of controlling and calculating means is in failure, the individual bus interfacing means in an operating state provided to said failed controlling and calculating means is rendered in a nonoperating state thereby separating said failed controlling and calculating means from said first and said second individual buses, the first and the second other controlling and calculating means connected to said first and said second individual buses which have been accessed by said failed controlling and calculating means in normal operation render individual bus interfacing means which has been in a nonoperating state in normal operation, in an operating state, whereby the first and second other controlling and calculating means occupy the first and second individual buses, access to said peripheral inputting and outputting means and take over the calculating processings of said failed controlling and calculating means thereby enabling to make the controlling and calculating processings continue even when one controlling and calculating means is in failure. A multiprocessor system, wherein microcomputers are used as said controlling and calculating means (11, 12 ... 1n) in Claim 1, a plurality of microcomputers are connected to a single common bus (2), each of said plurality of microcomputers is provided with two individual buses and said plurality of microcomputers are connected in series through said respective two individual buses whereby duality of buses is achieved and expansion of said plurality of microcomputers is facilitated.

Inventors: MOROOKA YASUO, WATANABE MASAHIKO, MOROOKA, YASUO, WATANABE, MASAHIKO
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1995
Main classification: G06F15
IPC codes: G06F15