A solar cell with integrated bypass function

Abstract: A solar cell with integrated bypass function includes: a first conducting type substrate 1 selected from P-type and N-type substrates; a region 2 of a second conducting type which is different from the first conducting type, the region 2 being formed on a light receiving side of the substrate; a third region 4 of the first conducting type, having a higher impurity concentration than the substrate 1 and being formed in part on the light receiving side of the substrate 1 so as to be in contact with both the substrate 1 and the region 2 of the second conducting type; an insulator film 9 formed on all or part of the third region 4; and a light receiving side electrode 7 formed on the insulator film 9 so as to be in partial contact with the region 2 of the second conducting type.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention The present invention relates to a solar cell which converts light energy into electric energy and, in particular, relates to a solar cell with integrated bypass function in which functions of bypass diode for protecting the solar cell from a reverse bias voltage are added. (2) Description of the Prior Art A solar cell module is typically composed of a large number of solar cells connected in parallel and/or in series in order to obtain a desired output voltage with a desired output current. If part of the solar cell or some of the cells are shaded, voltages generated by the other cells are applied to the shaded cells as a reverse bias voltages. If a reverse bias voltage exceeding the peak inverse voltage of a shaded cell (breakdown voltage) is applied to the cell, the cell may be short-circuited and damaged, whereby the output characteristics of the whole solar cell module could be degraded. In a case of the solar cell module for space applications such as to a satellite, part of the satellite body or construct elements such as antennas etc., could shade the solar cell module while the satellite is controlled on its attitude. For terrestrial uses, a neighboring buildings, for example, would shade the solar cell, or birds would come flying to the solar cell and eliminate fecal matter thereon which shades the solar cells. As an example of such cases, discussion will be made on a case where a solar cell module consisting of a number of solar cells connected in parallel is shaded in part on its surface. In a shunt mode as shown in Fig.4A where a solar cell module M is substantially short-circuited between both terminals thereof, when a submodule 11 is shaded, a reverse bias V 12 generated across the submodule group 12 which remains unshaded is applied to the submodule 11. If the voltage across the submodule 11 is V 11 , it can be expressed as V 11 = -V 12 . When an external power source V B is connected to the solar cell module M as illustrated Fig.4B, V 11 is represented by V 11 = V B - V 12 . That is, when a positive voltage is applied to the N-electrode of the shaded submodule 11; if the reverse bias voltage is greater than the peak inverse voltage of the solar cells constituting the submodule 11, the solar cells are short-circuited and may be damaged, whereby the submodule 11 shaded and consequently the whole solar cell module M may become degraded in output characteristics. In order to avoid hazards of this kind due to the reverse bias voltage, a bypass diode is provided for each solar cell or for every certain solar cell module; alternatively, a so-called diode integrated solar cell is used in which bypass diodes are integrated in solar cells. Other than these, there also is a solar cell with integrated bypass function. Next, a configurational example of a conventional solar cell with integrated bypass function will be explained with reference to drawings. Fig.1 is a plan view showing a structure of a solar cell with integrated bypass function proposed by the present applicant (EP-A-0 537 781 and Japanese Utility Model Application Hei 3 No.102,749) and Fig.2 is a sectional view taken on a line 20-21 in Fig.1. As illustrated in Fig.1, a light receiving face of the solar cell is covered with a transparent antireflection coating 8. Under the coating 8, strip N-electrodes 7 connected together in the ends with a bar-shaped N-electrode connecting portion 5 are arranged like a comb over an N-type region 2. As shown in Fig.2 where a vertical structure of the solar cell is illustrated on a line 20-21 in Fig.1, the cell is composed of a P-type silicon substrate 1, the N-type region 2 formed on the light receiving face of the substrate 1, a P + -type region 3 formed beneath the substrate 1 for the BSF effect, P + -type islands 4 partially formed on the light receiving face of substrate 1, the N-electrode 7 formed on the surface of the N-type region 2, the antireflection coating 8 approximately entirely covering the N-type region 2 and a P-electrode 6 approximately entirely covering the underside of the P + -type region 3 and the like. The solar cell thus configurated is produced in the procedures shown in step-order sectional views shown in Figs.3A through 3F. In the beginning, the whole surface of the P-type silicon substrate 1 shown in Fig.3A is subjected to the thermal oxidation or the like so that an oxide film 10 is formed as shown in Fig.3B. Subsequently, as shown in Fig.3C, the oxide film 10 on the underside is removed, and holes 14, 14, ··· are formed on the surface of the oxide film 10 by the photolithographic or any other technique. These holes 14, 14, ··· correspond to P + -type islands 4, 4, ··· which will be formed next. Then, a P + -type impurity is diffused into the wafer to an impurity concentration of 1 × 10 20 cm -3 , for instance. Thereafter, the remaining oxide film 10 on the top and side faces is removed so as to produce a wafer shown in Fig.3D. This wafer has a number of P + -type islands 4, 4, ··· formed on the top surface thereof and the P + -type region 3 formed throughout the undersurface thereof. Subsequently, as shown in Fig.3E, the N-type region 2 is formed on the top and side faces by the thermal diffusion technique or the like. Since the P + -type islands 4, 4, ··· are protected by the boron glass remaining on the topmost layer thereof, these regions are unaffected and kept in the forms of islands in the N-type region 2. Next, as shown in Fig.3F, the comb-shaped N-electrodes 7 and the N-electrode connecting portion 5 (not shown in the figure) are formed on the top surface. Then, the antireflection coating 8 is formed on the top of the wafer while the P-electrode 6 is vacuum evaporated on the undersurface thereof. The thus formed wafer is cut in both ends indicated by broken lines, whereby a solar cell shown in Figs.1 and 2 is obtained. A large number of the thus prepared solar cells are connected in series and in parallel as shown in Fig.4A to output a desired voltage and a desired current. The thus formed assembly is used as a typical solar cell module M. External attachment of bypass diodes to the solar cell for the purpose of preventing the solar cell from being damaged by the reverse bias voltage, needs increased cost for bypass diodes as well as the manufacturing cost for the attachment. Further, this method suffers from another problem that the packaging density of solar cells is decreased. Since, in the conventional diode integrated solar cell, a bypass diode and a solar cell should be put together onto a silicon substrate, the manufacturing process becomes complicated, resulting in increased production cost. Further, the conventional solar cell with integrated bypass function has islanded P + regions that occupies part of the cell surface, so that the effective area of the solar cell is decreased therefore the converting efficiency is lowered. SUMMARY OF THE INVENTION In view of what has been discussed above, it is therefore an object of the present invention to provide a solar cell with integrated bypass function in which high converting efficiency is obtained without reducing the effective area of the solar cell. To attain the above object, the present invention is configurated as follows: That is, a solar cell with integrated bypass function comprises: a first conductivity type substrate selected from P-type and N-type substrates; a region of a second conductivity type opposite to said first conductivity type, the region being formed on a light receiving side of the substrate; a third region of the first conductivity type, having a higher impurity concentration than the substrate and being formed in a part of the light receiving side of the substrate so as to be in contact with both the substrate and the region of the second conductivity type; an insulator film formed on all or part of the third region; and a light receiving side electrode formed on the insulator film so as to be in partial contact with the region of the second conductivity type and insulated from said third region. In the present invention, quality of the insulator film may be improved by effecting a heat treatment after the formation of the film. In the present invention, the third region of the first conductivity type is formed of a plurality of islands. In the present invention, the density of the islands as the third region of the first conducting type is made large as the position of islands becomes close to the surface electrode connected to an external terminal. When a reverse bias voltage is applied to the thus configurated solar cell of the present invention, the reverse bias voltage is adapted to be applied to a P + N junction formed of the receiving side region of the second conducting type (N-type, for example) and the region of the first conducting type (P + , for example) which has a higher impurity concentration and is formed in contact with the region of the aforementioned second conducting type. This part more easily causes breakdown due to the Zener effect or avalanche effect than the PN junction formed between the substrate of the first conducting type (P-type, for example) and the diffused layer of the second conducting type (N-type, for example). In a state where a relatively low reverse bias voltage is applied to the part, a reverse current is flowed in the region. Further, when the reverse bias becomes higher, the part causes breakdown due to the Zener effect or avalanche effect, whereby the solar cell can be prevented from being applied by the reverse bias voltage. Describing the above effect using an equivalent circuit as shown in Fig.12, the solar cell of the present invention is constructed so that an NP + diode is connected in parallel with a solar cell made of a NP junction. When a reverse bias voltage is applied to, current flows through the NP + diode which allows a greater leaking current in the reverse direction, whereby the solar cell of the NP junction can be protected from breakdown. Since, in the present invention, the P + -region forming the aforementioned NP + diode is formed right under the N-electrode with the insulator film therebetween, no reduction of the power-generating area (effective light receiving area) may occur, unlike the prior art solar cell of this kind. Since, in the present invention, the P + -region forming the aforementioned NP + diode is formed right under the N-electrode with the insulator film therebetween, it is possible to make short the distance between the N-electrode to which a reverse bias voltage is applied and the P + -region. Therefore, it is possible to reduce the equivalent series resistance, and therefore to further improve the protecting function against applications of the reverse bias voltage. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a plan view showing a prior art example of a solar cell; Fig.2 is a sectional view taken on a line 20-21 in Fig.1; Fig.3A is a sectional view illustrating a first step of a producing process of the solar cell shown in Fig.1; Fig.3B is a sectional view illustrating a second step of the solar cell shown in Fig.1; Fig.3C is a sectional view illustrating a third step of the solar cell shown in Fig.1; Fig.3D is a sectional view illustrating a fourth step of the solar cell shown in Fig.1; Fig.3E is a sectional view illustrating a fifth step of the solar cell shown in Fig.1; Fig.3F is a sectional view illustrating a final step of the producing process of the solar cell shown in Fig.1; Fig.4A is an illustrative view for explaining a reverse bias voltage applied to a solar cell, based on a configurational example of a solar cell module; Fig.4B is an illustrative view for explaining a reverse bias voltage applied to a solar cell, when a solar cell module is connected to an external power supply; Fig.5 is a schematic sectional view showing a first embodiment of a solar cell with integrated bypass function in accordance with the present invention; Fig.6 is a plan view showing the solar cell shown in Fig.5; Fig.7 is a sectional view taken on a line 30-31 in Fig.6; Fig.8A is a sectional view illustrating a first step of a producing process of the solar cell shown in Fig.5; Fig.8B is a sectional view illustrating a second step of the solar cell shown in Fig.5; Fig.8C is a sectional view illustrating a third step of the solar cell shown in Fig.5; Fig.8D is a sectional view illustrating a fourth step of the solar cell shown in Fig.5; Fig.8E is a sectional view illustrating a fifth step of the solar cell shown in Fig.5; Fig.8F is a sectional view illustrating a final step of the producing process of the solar cell shown in Fig.5; Fig.9 is a plan view showing a second embodiment of a solar cell with integrated bypass function in accordance with the present invention; Fig.10 is a sectional view taken on a line 40-41 in Fig.9; Fig.11A is a sectional view illustrating a first step of a producing process of the solar cell shown in Fig.9; Fig.11B is a sectional view illustrating a second step of the solar cell shown in Fig.9; Fig.11C is a sectional view illustrating a third step of the solar cell shown in Fig.9; Fig.11D is a sectional view illustrating a fourth step of the solar cell shown in Fig.9; Fig.11E is a sectional view illustrating a fifth step of the solar cell shown in Fig.9; Fig.11F is a sectional view illustrating a final step of the producing process of the solar cell shown in Fig.9; Fig.12 is a diagram showing an equivalent circuit to a solar cell with integrated bypass function; Fig.13 is a chart showing data of the reverse current when a solar cell of the present invention is applied with a reverse bias of 20 V; and Fig.14 is a chart showing data of the reverse current when a solar cell of the present invention is applied with a reverse bias of 5 V. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig.5 is a schematic sectional view showing an embodiment of a solar cell with integrated bypass function in accordance with the present invention. In the following description of the embodiment, the same components with those in the conventional example shown in Figs.1 and 2 are designated with the corresponding reference numerals. Fig.5 shows an example in which a plurality of P + -type islands 4 are formed inside an N-type regions 2 formed on the surface of a P-type substrate 1. These P + -type islands 4 are formed under an N-electrode 7 with an insulator film 9 therebetween. Fig.6 is a plan view of a solar cell shown in Fig.5 and Fig.7 is a schematic sectional view taken on a line 30-31 in Fig.6. Figs.8A thorough 8F are step-order sectional views showing an example of the producing process for the solar cell. In Figs.6 and 7, similarly to the conventional example, an N-type region 2, an N-electrode connecting portion 5, strip N-electrodes 7 arranged like a comb and an antireflection coating 8 are formed on the top surface of a P-type substrate 1 while a P + -type region 3, a P-electrode 6 etc., are formed on the underside of the P-type substrate 1. Difference of the solar cell of this embodiment from the conventional configuration is that plural, locally formed small P + -type islands 4, 4,··· are scattered as a third region inside the N-type region 2 under the comb-shaped electrodes 7, 7,··· with the insulator film 9 therebetween. The third region, or the small P + -type islands 4, 4,··· are also formed inside the N-type region 2 under the N-electrode connecting portion 5 with the insulator film 9 therebetween. These P + -type islands 4, 4,··· have higher impurity concentration as compared to the P-type silicon substrate 1 and forms a PN junction structure in cooperation with the N-type region 2 so as to cause breakdown due to the Zener effect or avalanche effect. The impurity concentration in the P + -type islands 4 may and should be set to be 1 × 10 18 cm -3 or more to make the breakdown occur. The solar cell thus configurated is produced, for example, as follows. Initially, a P + -type impurity is diffused to an impurity concentration of about 1 × 10 19 to 5 × 10 22 cm -3 into the P-type silicon substrate 1 as shown in Fig.8A, so that a P + -type region 3 as to be the third region is formed on the whole surface as shown in Fig.8B. Then, an acid-proof resin 11 for photoresist or the like, for example, is applied on the whole undersurface as well as part of the top surface (where desired high-concentration regions are formed). This stage is shown in Fig.8C. An acid-proof tape may be applied on the undersurface of the substrate. Then the substrate thus covered is immersed in the etchant consisting of a mixed acid, or a mixture of hydrofluoric acid and nitric acid to etch it. Thereafter the aforementioned acid-proof resin or the tape is removed. This stage is shown in Fig.8D. Subsequently, the N-type region is formed as shown in Fig.8E on the top surface of the substrate by the thermal diffusion process. The P + -type islands 4, 4,··· will be protected by the layer of boron glass or the like which has been formed when the P + -impurity was diffused and remains in the top-most layer. In this N-type thermal diffusing process, there is a fear that the N-type impurity penetrates into the P + -type islands 4, 4, ··· too deeply from the side thereof and breaks the P + -type islands. To avoid this, the diffusing depth must be set up carefully. Subsequently, a similar treatment to be described later with reference to Figs.11B and 11C is done, so that the insulator film 9 is formed on the top of the P + -type islands 4, 4,···. After the formation of the insulator film 9 on the top of the P + -type islands 4, the comb-shaped N-electrodes 7 with the N-electrode connecting portion 5 are formed on the top surface, as shown in Fig.8F. Further, the antireflection coating 8 is formed on the top and the P-electrode 6 is vacuum-evaporated on the undersurface. The thus formed wafer is cut in both ends indicated by broken lines, whereby a solar cell shown in Figs.6 and 7 is obtained. This producing process does not become so much complicated as compared to that of the conventional method shown in Figs.3A through 3F, therefore the production cost will not be increased very much. In this case, the P + -type islands 4, 4,··· as to be the third region must be adjusted as to size, number and geometry, depending on the size, type etc., of each solar cell and the module. Typically, a solar cell having an area of 2 cm × 4 cm should have about 5 to 10,000 islands having a diameter of from 10 µm to 200 µm or the equivalent area. As the total area of the P + -type islands 4, 4,··· becomes large, the output power from the solar cell becomes decreased. Therefore, the total area of the P + -type islands 4, 4,··· needs to be designed as small as possible within a range in which Zener breakdown or avalanche breakdown may arise and still the solar cell will not break. To meet this condition, the islands should be formed densely in the areas close to the N-electrode connecting portion 5 so that the breakdown may easily arise while the P'-type islands 4, 4,··· should be suppressed in size and number. Figs.13 and 14 are charts showing behaviors of reverse current in different reverse bias voltages in which the reverse current caused by the reverse bias voltage becomes large as the site of the P + -type islands 4, 4, ··· become close to the N-electrode connecting portion 5 (bar electrode). Here, Figs.13 and 14 show cases in which reverse bias voltages of 20 V and 5 V are applied respectively to a solar cell with five P + -type islands 4, 4,··· having a diameter of 50 µm scattered thereon. Figs.9 and 10 show a second embodiment of a solar cell with integrated bypass function in accordance with the present invention. Fig.9 is a plan view and Fig.10 is a schematic sectional view taken on a line 40-41 in Fig.9. In Figs.9 and 10, similarly to the conventional example, the N-type region 2, an N-electrode connecting portion 5, strip N-electrodes 7 arranged like a comb and an antireflection coating 8 are formed on the top surface of a P-type substrate 1 and a P-electrode 6 etc., are formed on the underside of the P-type substrate 1. Further, as in the first embodiment, plural, locally formed small P + -type islands 4, 4,··· are scattered as a third region inside the N-type region 2 under the comb-shaped electrodes 7, 7,··· with the insulator film 9 therebetween. In the second embodiment, the feature of P + -type islands 4, 4,··· differs from that in the first embodiment. That is, the surface of the N-type region 2 is formed in flush with that of the P + -type islands 4, 4,···. The P + -type islands 4, 4,··· in this third region have higher impurity concentration as compared to the P-type region 1 in the substrate and forms a PN junction structure in cooperation with the N-type region 2 so as to cause breakdown due to the Zener effect or avalanche effect. The impurity concentration in the P + -type islands 4 may and should be set to be 1 × 10 18 cm -3 or more to make the breakdown occur. These conditions are the same with those in the first embodiment. The solar cell thus configurated is produced, for example, as follows. Fig.11A to Fig.11F show schematic sectional views of each production step, respectively. Initially, the whole surface of the P-type silicon substrate 1 shown in Fig.11A is subjected to the thermal oxidation or the like so that an oxide film 10 is formed as shown in Fig.11B. Subsequently, as shown in Fig.11C, the oxide film 10 on the underside is removed, and holes 14, 14, ··· are formed on the surface of the oxide film 10. These holes 14, 14, ··· correspond to P + -type islands 4, 4, ··· which will be formed later. Then, a P + -type impurity such as boron is diffused into the substrate to an impurity concentration of 1 × 10 20 cm -3 , thereafter, the oxide film 10 is removed from the top, underside and side surfaces. Thus, the substrate shown in Fig.11D is obtained. Plural P + -type islands 4, 4, ··· are formed on the top surface. Subsequently, as shown in Fig.11E, the N-type region 2 is formed on the top and side faces by the thermal diffusion technique or the like. Since the P + -type islands 4, 4, ··· are protected by the boron glass remaining on the topmost layer thereof, these regions are unaffected and kept in the forms of islands in the N-type region 2. Then, an acid-proof resin for photoresist or the like is applied on the surface and the underside is removed by etching in, for example, a mixed acid of hydrofluoric acid and nitric acid. Subsequently, a similar treatment effected as to Figs.11B and 11C is done, so that the insulator film 9 is formed on the top of the P + -type islands 4, 4,···. Next, after the formation of the insulator film 9 on the top of the P + -type islands 4, the comb-shaped N-electrodes 7 with the N-electrode connecting portion 5 are formed on the top surface, as shown in Fig.11F. Further, the antireflection coating 8 is formed on the top and the P-electrode 6 is vacuum-evaporated on the undersurface. The thus formed wafer is cut in both ends indicated by broken lines, whereby a solar cell shown in Figs.9 and 10 is obtained. This producing process does not become so much complicated as compared to that of the conventional method shown in Figs.3A through 3F, therefore the production cost will be increased very much. The size, number and geometry as to the P + -type islands 4, 4, ··· are the same with those in the first embodiment. In the above producing processes, the formation of the insulator film 9 can be formed by, for example, a CVD process employing SiH 4 gas and oxygen as starting materials or by a CVD process using decomposition of TEOS (tetraethoxysilane). Because the N-side electrode is formed on the top of the insulator film, the film is naturally required to be fine and highly insulating. Accordingly, it is effective that the film is subjected to a short-time heat treatment such as the RTA (Rapid Thermal Anneal), after the formation of the insulator film by the aforementioned CVD process. In each of the embodiments described above, although no reference has been made to whether the solar cell belongs to the BSF type or the BSFR type, the difference between the two is only the metal composition of the P-electrode, therefore, this does not make any practical difference in the feature of the present invention. Although, the above description has been made on only the solar cells using a P-type silicon substrate, for convenience of description, the present invention can be applied to solar cells using an N-type silicon substrate or solar cells using a substrates of other than silicon monocrystal such as GaAs etc. The present invention can be applied to both the solar cells for space applications and for terrestrial applications. As has been described heretofore, according to the present invention, a solar cell which is hardly short-circuited and broken due to reverse bias voltages can be produced at low cost. Particularly, in a case where the solar cell array is used under such circumstances where the maintenance is difficult to be done, as in the space, the present invention presents markedly effective protection against the reverse bias voltages and therefore improves the reliability of the whole array. Since no externally attached bypass diode is needed, the producing cost of the solar cell can be reduced. Further, in accordance with the present invention, since conductive regions for providing bypass diode functions are formed right under the light receiving side electrode with an insulator film therebetween, it is possible to provide bypass diode facilities without reducing the effective area of the light receiving surface of the solar cell. This contributes to the prevention of reduction in the photovoltaic converting efficiency. In accordance with the present invention, conductive regions for providing bypass diode functions are integrally formed close to the light receiving side electrode, it is possible to reduce the equivalent series resistance. Therefore, this is effective to further improve the protecting function against applications of the reverse bias voltage.

Claims: A solar cell with integrated bypass function comprising: a first conductivity type substrate (1) selected from P-type and N-type substrates; a region (2) of a second conductivity type opposite to said first conductivity type, said region being formed on a light receiving side of said substrate; a third region (4) of the first conductivity type, having a higher impurity concentration than said substrate and being formed in a part of the light receiving side of said substrate so as to be in contact with both said substrate and said region of the second conductivity type; an insulator film (9) formed on all or part of said third region; and a light receiving side electrode formed on said insulator film so as to be in partial contact with said region of the second conductivity type and insulated from said third region. A solar cell with integrated bypass function according to Claim 1 wherein said third region of the first conductivity type is formed of a plurality of islands. A solar cell with integrated bypass function according to Claim 2 wherein the density of said islands forming said third region of the first conductivity type is made large as the position of islands becomes close to the surface electrode connected to an external terminal. A method of manufacturing a solar cell with integrated bypass function according to Claim 1 wherein a heat treatment is carried out after the formation of the insulator film (9) so as to improve the quality of said insulator film.

Inventors: HISAMATSU TADASHI, YOSHIOKA HIDEKI, HISAMATSU, TADASHI, YOSHIOKA, HIDEKI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1995
Main classification: H01L27
IPC codes: H01L31, H01L27