Residual charge elimination for a memory device

Abstract: A circuit and method is provided for addressing memory cells in a memory device, including two series connected select gates having a node between them. A switching element is connected between the node and a ground voltage. A control signal is applied to a control input of the switching element to render it conductive while both of the select gates are non-conductive, so as to eliminate charge stored at a node between the two select gates. A particular application to an addressing circuit for use in a flash EPROM memory device is described.

Description: The present invention concerns a circuit and method for addressing memory cells in a memory device. While the current invention finds application in many fields, it has particular advantages when used in memory devices such as flash EPROM memory devices. EP 0572240 A2 describes a known non-volatile memory device which has three different modes: a read mode, an erase mode and a program mode. EP 0317236 A describes a system that comprises an analogue integrated circuit using integrated field effect transistor technology using a plurality of sampling and storage cells, the system being capable of improved sampling of fast pulse signals. Figure 1 shows circuitry for controlling a flash EPROM memory cell. The memory cell 2 comprises a single N-channel transistor 4, having a control gate CG and a floating gate FG, a source S and a drain D. The source S is connected either to a ground voltage V GND , or to a programming voltage, V PP , by a source voltage switch 8, according to a signal applied to an erase control input 10. The drain D of transistor 4 is connected to a bitline 12, which may be connected either to a sense amplifier circuit 14 via dataline DB or to a programmable load circuit 16 by bitline switch 18, according to a select signal 20. Select signal 20 is provided by a decoding circuit (not illustrated), according to applied column address signals. The programmable load circuit 16 is controlled by load control signals 22. The sense amplifier circuit 14 has an output to an output data line 24. The control gate of transistor 4 is connected through wordline 26 to a gate voltage switch 28. This permits the control gate CG to be connected to the ground voltage V GND , the programming voltage V PP or a supply voltage V' CC , according to control signals applied to program and erase control inputs 30, 10 respectively. V' CC is 5V for a memory device operating with a 5V supply, and about 5V for a memory device operating with a 3V supply. The flash memory cell 2 has three modes of operation. In program mode a 0 is written to the cell. The control gate CG is connected to the program voltage V PP . The source S of transistor 4 is connected to the ground voltage V GND . The drain D is connected to the programmable load circuit 16, programmed to place the drain of transistor 4 at about 5V. Thus, the floating gate FG is negatively charged, making the transistor less conductive for a given control gate voltage. In erase mode a 1 is written to the cell. In the erase mode, the control gate CG of the transistor 4 is connected to the ground voltage V GND . The source S is connected to the program voltage V PP . The bitline switch 18 is set to allow the bitline 12 to float at around 1V. The charge on the floating gate FG is reduced, making the cell more conductive. After a sufficient time, a 1 is written into the cell. In read mode, voltages are applied to transistor 4 such that a relatively low current will flow when a 0 has been written into the cell, and a relatively high current will flow when a 1 has been written into the cell. The contents of each memory cell may thus be determined. The control gate CG and wordline are connected to the supply voltage V' CC by the gate voltage switch 28. The source is connected to ground V GND . Bitline 12 is connected to the sense amplifier circuit 14, which provides a bias of around 1V. The sense amplifier 14 detects the level of the current and places the output dataline 24 in a logic state indicative of the state of the cell 2, by comparing the level of current with a reference level REF, 32. In a flash memory device, many cells such as that shown in figure 1 are connected together, and provided with addressing circuitry. Each cell, however, functions as described above, in its three possible states. Figure 2 shows a typical arrangement of M×N memory cells FM 00 to FM ( M -1)( N -1) within a flash EPROM memory device. Features identical to those in figure 1 have identical reference labels. Voltage supplies V GND , V PP , V' CC are not shown for clarity, but should be understood as being connected as in figure 1. Each cell may be identical to that discussed above. The cells are arranged in M rows and N columns. The control gates of all cells in a row are connected together to one of M wordlines WL 0 to WL ( M -1) . A row line decode circuit 40 selectively addresses the wordlines in response to applied row address signals 42, to connect the required wordline 44 to the gate voltage switch 28. All cells in a column have their drains connected together, to one of N common bitlines, BL0 to BL( N -1). These common bitlines are connected to a column line decode circuit 46 which selectively addresses the bitlines in response to applied column address signals 48. The column line decode circuit comprises a plurality N of bit line switches 18, one connected to each bitline as in figure 1, plus decoding circuitry which applies select signals 20 to each of the bitline switches in response to the applied column address signals 48. Sense amplifier and programmable load circuits 14, 16 are connected to the bitline switches as in figure 1, and receive their respective reference and load control signals 32, 22. The sense amplifier again applies its output to output dataline 24. When a particular memory cell is to be programmed, the address corresponding to the particular cell is applied in a suitable fashion to the row address signals 42 and the column address signals 48. The programmable load 16 will be applied to a selected column only, so that only the particular cell is programmed, although the programming voltage V PP be applied to the control gates CG of all the cells in a selected row. During program and read operations, certain signals are often applied to other cells in the array which are not selected, to improve the performance of the selected cell. During erase operations, every cell in the array is erased, or the array may be designed to allow certain portions only of the array to be erased. In currently available flash EPROM memory devices, several select gates are used in the row line decode circuit 40 and the column line decode circuit 46. Such select gates may simply be MOS transistors. Use of several select devices in series allows the row line decode circuitry 40 and the column line decode circuitry 46 to be simplified significantly, as several small decoders may be used, each one controlling one of the series select gates. This results in a smaller, simpler design than would the use of a single large decoder controlling a single select gate per bitline. The row address signals 42 and column address signals 48 are supplied by an address buffer 15 which receives an address input 16. An ATD circuit 17 is connected to the address input 16, preferably prior to the address buffer 15, and generates a low pulse on line ATD responsive to detecting a transition in the address input. The ATD signal is passed to the column line decode circuit and may be used as hereunder described in relation to figure 5. No chip enable signal is required for the production of an ATD pulse. Figure 3A shows a column decode sub-circuit as used in current flash EPROM devices. Column address signals Y are split into two sets of address signals, bitline select signals Y A and group select signals Y B . The bitlines BL0 to BL( N -1) are split into a number of groups, each containing p bitlines. Illustrated in figure 3A are bitlines BL0 to BL( p -1), corresponding to a first group of p bitlines. N-channel transistors 70-0, 70-1, 70-2 represent select gates connected to bitlines BL0, BL1, BL2. N-channel transistor 70-( p -1) represents a select gate on a final bitline BL( p -1) of the group. The source terminals of all transistors 70 in a group are connected together at a node 80. Their drain terminals are respectively connected to bitlines BL0, BL1, BL2, BL( p -1). Gate terminals of transistors 70 receive bitline select signals Y A0 , Y A1 , Y A2 , Y A( p -1) , respectively. These are normally LOW, but change to a HIGH state for a period of time (the select period), during which conduction is required. Each of these select signals Y A thus selects one bitline from the group BL0 to BL( p -1). An N-channel transistor 82 has its drain terminal connected to node 80 and its gate terminal connected so as to receive a group select signal Y B0 . Its source terminal is connected to dataline DB, which corresponds to the input to the sense amplifier 14 of figures 1 and 2. This transistor 82 represents a select gate for selecting the group of bitlines BL0 to BL( p -1). The number of groups of bitlines will be N / p , so N / p group select signals, Y B0 to Y B( N / p -1) are required. In a flash EPROM circuit, many circuits such as that shown in figure 3A are connected to one data line DB in a data bus. Each will have a transistor 82 to select a group of p bitlines, supplied with a different group select signal Y B applied to a gate terminal. Figure 3B shows the arrangement. Many circuits 84, 86, 88, each identical to the circuit of figure 3A, are connected to have an output (the source of transistor 82) connected to the dataline DB, inputs (drains of transistors 70) connected to bitlines BL and bitline select inputs connected to the bitline select signals Y A0 to Y A( p -1) . Each circuit 84, 86, 88 has a group select input connected to a corresponding one of the second set of column address select signals Y B0 , Y B1 , Y B2 . The first circuit 84 has inputs connected to receive the first group of p bitlines, BL0 to BL( p -1). Similarly, the second circuit 86 has inputs connected to receive the second group of p bitlines in address order, BL p to BL(2 p -1); the third circuit 88 being connected to receive a third group of p bitlines BL(2 p ) to BL(3 p -1). Further circuits may be connected in like manner to further bitlines. The selection as to which bitline BL is connected to the dataline DB is made by a combination of first Y A and second Y B sets of column address select signals. A bitline to be connected to the dataline DB may be referenced by an eight bit address such as 0000 0010. Two four bit decoders may be used to decode the address, the first four bit decoder decoding a first set of four bits (0000) to provide a high group select signal on Y B0 , and the second four bit decoder decoding a second set of four bits (0010) to produce a high bitline select signal on Y A2 . Similar arrangements may be made for other address lengths. This is the preferred decoding method, as addressing decoding circuitry may be made of two small decoders, one decoding the first set Y A ; one decoding the second set Y B . This occupies less semiconductor surface area and consumes less power than a large, e.g. eight-bit, decoder which could select bitlines BL with a single select gate per bitline. An active signal on Y B2 will render conductive transistors 70-2 in sub-circuits 84, 86, 88, connected to bitlines BL2, BL( p +2), BL(2 p +2), but only one circuit 84 at a time will receive an active group select signal Y B0 , connecting bitline BL2 to the data line DB, leaving nodes 80 and the parasitic capacitances associated therewith in circuits 86, 88 holding residual charges at the voltages of bitlines BL( p +2), BL(2 p +2), respectively Similarly, while both select signals Y A2 and Y B0 are at a HIGH state, the node 80 of circuit 84 and any parasitic capacitance associated therewith will be charged to the signal level of bitline BL2. At the end of the select period, select signals Y A2 and Y B0 return to their LOW state. Transistors 70-2 and 82 cease to be conductive. Node 80 of circuit 84 is isolated, and hence also retains a residual charge, as no electrical conduction path is available for the charge to be eliminated. Suppose that a subsequent select period begins, with select signals Y A1 and Y B0 being HIGH, and bitline BL1 LOW. (Corresponding to address 0000 0001.) Transistors 70-1 and 82 of circuit 84 become conductive. The bitline BL1 being at a LOW state, the node 80 and its associated parasitic capacitance must discharge the residual charge before a valid LOW signal is presented at DB. This means that a delay is introduced into the transmission of the bitline signal to dataline DB, slowing down operation of the memory device. Also, the data lines DB are charged to the value of the bitline signal and retain this charge when the select transistors become inoperative. At the next address cycle, this residual charge must be discharged if the next bitline accessed has a different state from the precedent. In current flash EPROM devices, an address transition detect signal is generated, which produces a pulse at each change on the address bus. For the duration of this pulse, the address indicated in the address bus is changing, and so cannot be regarded as valid. No read or write operations are allowed during this time. An object of the invention as defined in appended claims is to enable faster operation of memory devices. Another object of the invention is to ensure that access times are substantially constant, independently of the previously accessed data. According to a first aspect the invention provides a memory device including memory cells and a circuit for addressing the memory cells, wherein the addressing circuit comprises two series connected select gates having a node between them, the addressing circuit comprising: a switching element connected between the node and a ground voltage; and a control input to the switching element, wherein means for applying a control signal apply the control signal to the control input every time that a different memory cell is to be addressed to render the switching element conductive while both of the select gates are non-conductive to permit residual charge on the node between the select gates to be discharged. The invention is particularly applicable to flash memory devices including an array of single transistor memory cells, notably wherein each of the single transistor memory cells has a floating gate. According to a second aspect the invention provides a circuit for addressing memory cells in a memory device including a plurality of subcircuits, each containing: series connected first and second select gates having a node between them, each select gate providing a conductive path between two main terminals when means for applying a first or a second control signal are adapted to apply the first or the second control signal to a control terminal of the respective gate, the main terminals of the first select gate being connected to the node and a common data line, a switching element is connected between the node and a ground voltage, and that means for applying a third control signal are adapted to apply the third control signal to a control input of the switching element to render it conductive, wherein the second control signal is present on the control terminal of the second select gate of at least one subcircuit and the third control signal is applied to the control input of the switching element of each subcircuit each time that a different memory cell is addressed, in order to establish a conductive path between the ground voltage, the node of each subcircuit, and the common data line. The invention provides also a method of addressing memory cells in a memory device, including the steps of applying inactive control signals to control inputs of series connected select gates of an addressing circuit of the memory device, said select gates having a node between them; applying active control signals to the control inputs of chosen select gates connected to respective bit lines so as to render the chosen select gates conductive; causing the voltages present on bitlines to be conducted through the select gates which are receiving an active control signal, towards a dataline; returning at least one of the chosen select gate control signals to an inactive state; applying a control signal to a control input of a switching element every time that a different memory cell is to be addressed to render the switching element conductive, wherein an electrically conductive path is provided from the node between the chosen select gates to a ground voltage via the switching element to permit residual charge at the node to be discharged; and removing the electrically conductive path. A particular embodiment of the current invention will be described, by way of example, with reference to the accompanying diagrams, wherein: figure 1 shows circuitry for controlling a memory cell, according to the prior art; figure 2 shows a circuit diagram of a memory device incorporating a plurality of cells such as that in figure 1; figure 3A is a circuit diagram of a part of a known memory device addressing circuit; figure 3B is a circuit diagram of a larger part of the known memory device addressing circuit, including several circuits such as that of figure 3A; figure 4 is a circuit diagram of a part of a memory device addressing circuit according to a first embodiment of the invention; figure 5 is a circuit diagram of a part of a memory device addressing circuit according to a second embodiment of the invention; figure 6A is a timing diagram showing signals used in a first subcircuit according to the second embodiment of the invention; and figure 6B is a timing diagram showing signals used in a second subcircuit according to the second embodiment of the invention. Figure 4 shows the circuit of figure 3 adapted according to the invention. N-channel transistor 92 is connected between node 80 and a ground voltage GND. This transistor 92 receives a signal Y B0 on its gate terminal, this signal being the inverse of the signal Y B0 applied to the gate terminal of transistor 82. During a select period where both Y B and one of Y A0 to Y A( p -1) are active, node 80 will be charged to the voltage of the logic level on the associated bitline. During this time, Y B0 will be HIGH, to render transistor 82 conductive. The transistor 92 will be non-conductive, as its gate receives a LOW signal, Y B0 . At the end of the select period, the signal Y B0 will become LOW, transistor 82 will become non-conductive and the electrical conduction path between the bitline BL and dataline DB is interrupted. At the same time, signal Y B0 will become HIGH, and transistor 92 will become conductive. This will cause any residual charge stored at node 80 to be conducted to ground, GND. Node 80 will then be at a fixed voltage, GND, by the time that the next select period begins. No residual charge will be present at the next select period, so no delay is introduced by the need to discharge a residual charge. Access time is thus reduced. An improvement may be made by ensuring that the transistor 82 is rendered conductive at every address transition. Figure 5 shows the improved circuit. NAND gate 94 has an output Dis connected to the gate of transistor 92. The NAND gate 94 has two inputs, the first of which receives the signal Y B0 ; the second receives an active-LOW address transition detect signal, ATD , which is generated asynchronously at every address transition. When at least one bit of an address changes state there is a period during which the address cannot be regarded as valid. During this period the ATD signal is HIGH and the ATD signal is LOW. The discharging transistor 92 receives an active gate signal, and is thus rendered conductive, when either Y B0 is inactive (LOW), or when address transition detect signal is active (LOW). Therefore, the improved circuit reacts immediately to an address transition to discharge the node 80. Such use of the address transition detect signal ensures that residual charge is not a problem between two access cycles which both have Y B0 active. The access time in such situations is thus rendered more constant. During the time that ATD is active, no access is possible, as the new address is valid only at the end of the ATD pulse. Thus, the period may be used for ensuring that node 80 is in a known state, even if Y B0 remains active through consecutive address cycles. Figure 6A shows a timing diagram for the derivation of the signal Dis from the group select signal Y B0 and the address transition detect signal ATD . The Dis signal is HIGH, rendering the transistor 92 conductive and discharging any charge stored at node 80 whenever either Y B0 or ATD is LOW, i.e. during any time that the node 80 may be isolated, and at any time that an address change is detected. The circuit of figure 5 when operated according to the timing diagram of figure 6A has the added advantage that, at times such as t db , when both Y B0 and Dis are high, a conduction path exists between the data line DB and ground GND, via transistors 82, 92. Both node 80 and data line DB are thus discharged between successive addressing cycles. During such times as t d0 to t d1 , another subcircuit is connected to the dataline, for example circuit 86 may be enabled by signal Y B1 . Figure 6B shows a timing diagram, similar to that of figure 6A, for the operation of the residual charge elimination transistor of circuit 86. The enable signal Y B1 is active from time t d0 to time t d1 . During this time, two address changes occur, indicated by two pulses on ATD . At each of these times t db , a conductive path is open between the data line DB and the ground voltage GND. As one of the enable signals Y B0 -Y B( p -1) is active at each transition, the data line is discharged after each addressing cycle. The discharging of the data line also means that no stored charge needs to be conducted to ground before a low value on an addressed bit line is properly transferred to the data line, again meaning a more regular and quicker transmission time, itself leading to a reduced access time of the memory device as a whole. When a conduction path is established between a bitline BL and dataline DB, at the next select period, the access time will not be affected by the need to discharge any residual charge remaining at node 80, as this node is always at ground voltage whenever a new select period begins. The access time is thereby reduced, and rendered constant. The invention thus achieves its objective by providing a circuit and method enabling faster operation of the memory device, ensuring that access times are substantially constant, regardless of the value of previously accessed data. The charge elimination is performed asynchronously, so that a next clock pulse is not awaited, allowing fastest possible operation. In the addressing circuit of a memory, the invention also provides for the discharging of data lines between addressing cycles, further contributing to improving the speed of operation of the memory device. Although the invention has been described in relation to the specific example of an addressing method for use in electronic memory devices, the invention finds application in all circuits where charge may inadvertently be stored at a node by disconnection of all conductive paths to that node.

Claims: A memory device including memory cells and a circuit for addressing the memory cells, wherein the addressing circuit comprises two series connected select gates (70, 82) having a node (80) between them, and a switching element (92) connected between the node (80) and a ground voltage (GND); characterised in that the addressing circuit further comprises : a control input to the switching element (92), wherein means for applying a control signal ( Y B0 , Dis) apply the control signal to the control input every time that a different memory cell is to be addressed to render the switching element (92) conductive while both of the select gates (70, 82) are non-conductive to permit residual charge on the node (80) between the select gates to be discharged. A circuit according to claim 1, wherein the control signal ( Y B0 ) applied to the control input of the switching element (92) is the inverse of a control signal (Y B0 ) applied to the control input of one of the select gates (82). A circuit according to claim 1, wherein the memory device is a flash memory device including an array of single transistor memory cells (2). A circuit according to claim 3, wherein each of the single transistor memory cells (2) has a floating gate (FG). A circuit as claimed in any of the preceding claims, comprising an address transition detection circuit (17) for provision of said control signal (Dis) every time an address transition is detected. A circuit for addressing memory cells in a memory device, the circuit including a plurality of subcircuits, each containing: series connected first and second select gates (82, 70) having a node (80) between them, each select gate providing a conductive path between two main terminals when means for applying a first or a second control signal (Y B , Y A ) are adapted to apply the first or the second control signal to a control terminal of the respective gate, the main terminals of the first select gate (82) being connected to the node (80) and a common data line (DB), a switching element (92) is connected between the node (80) and a ground voltage (GND), characterised in that means for applying a third control signal (Dis) are adapted to apply the third control signal to a control input of the switching element (92) to render it conductive, wherein the second control signal (Y A ) is present on the control terminal of the second select gate (70) of at least one subcircuit and the third control signal (Dis) is applied to the control input of the switching element of each subcircuit each time that a different memory cell is addressed, in order to establish a conductive path between the ground voltage (GND), the node (80) of each subcircuit, and the common data line (DB). A method of addressing memory cells in a memory device, including the steps of: applying inactive control signals to control inputs of series connected select gates (70, 82) of an addressing circuit of the memory device, said select gates having a node (80) between them; applying active control signals to the control inputs of chosen select gates connected to respective bit lines so as to render the chosen select gates conductive; causing the voltages present on bitlines (BL) to be conducted through the select gates (70, 82) which are receiving an active control signal, towards a dataline (DB); returning at least one of the chosen select gate control signals to an inactive state; characterised by the steps of applying a control signal ( Y B0 , Dis) to a control input of a switching element every time that a different memory cell is to be addressed to render the switching element (92) conductive, wherein an electrically conductive path is provided from the node (80) between the chosen select gates to a ground voltage (GND) via the switching element (92) to permit residual charge at the node (80) to be discharged; and removing the electrically conductive path. A method according to claim 7, wherein said step of returning at least one the chosen select gate control signals to an inactive state follows an address transition. A method according to claim 7 or 8, wherein said step of returning at least one the chosen select gate control signals to an inactive state comprises returning of both select gates (70, 82) to an inactive state. A method according to any of claims 7 to 9, wherein the memory cells comprise single transistor floating gate memory cells (2) and the memory device comprises a flash EPROM memory device.

Inventors: FERRIS ANDREW, FERRIS, ANDREW
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS LIMITED
Application year: 1995
Main classification: G11C8
IPC codes: G11C7, G11C8, G11C16