RADIX 2 ARCHITECTURE AND CALIBRATION TECHNIQUE FOR PIPELINED ANALOG TO DIGITAL CONVERTERS

Abstract: In a pipelined radix 2 analog to digital converter, a method of analog residue formation uses an overflow reduction stage which takes an analog input and outputs a digital value of +2, 0, or -2 and an analog residue which is twice the analog input minus the digital output value times a reference voltage. A calibration technique allows a pipelined analog to digital converter using the overflow reduction stages to produce a corrected output requiring one addition per pipeline stage. The residue portion of the overflow reduction stage can be constructed using an operational amplifier, two capacitors, one of which has twice the capacitance of the other, and three on-off type switches. A radix 2 pipelined converter is constructed using a combination of standard 1-bit stages and overflow reduction stages. The analog residue is passed from stage to stage as an amplifier remainder as the digital codes are extracted in a pipelined analog to digital converter. The overflow reduction stage reduces out-of-range residues back to in-range residues. Using three digital output values where the difference between any two is greater than one raw output code prevents the possibility of multiple representations of the same code and thus allows for the prevention of non-monotonic input-output transfer functions. The self-calibration and raw output code correction schemes prevent non-monotonicities and missing codes in the input-output transfer functions.

Description: RADIX 2 ARCHITECTURE AND CALIBRATION TECHNIQUE FOR PIPELINED ANALOG TO DIGITAL CONVERTERS BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION The present invention relates to pipelined analog to digital converters. Particularly, this invention discloses a new pipelined stage design which has a different scheme for producing the digital outputs and the analog residue. 2. DESCRIPTION OF RELATED ART In the field of analog to digital (A D) conversion, increasing the speed and precision of the conversions is desirable. For example, 5 MHz sampling rates are needed in hand-held CCD document scanners; high-end scanners and low-end video applications require 10 MHz sampling rates; and standard- broadcast video camcorders need 20 MHz sampling. Furthermore, high-end video applications take advantage of over-sampling at 25 MHz; automotive collision-avoidance radar receivers undersample at 25 MHz. and medical ultrasound scanners and professional broadcast-studio video equipment want 40 MHz sampling rates. In addition, digital communication applications undersample in the 20-to-25 MHz range. Today A D converters need to produce as much as 40 Megasa ples per second (MS sec) at 12 bits per sample while still providing a reasonably low latency. There are several techniques currently used to achieve the speeds. For example, parallel-encoded flash, multi-step, pipeline, and time-interleaved successive approximation are some of the techniques. Flash A/D encoding is the fastest method of conversion, because it is essentially performed in a single step. Figure 1 shows a typical flash A/D structure. For an N-bit encoded output, the input voltage is sent to 2 comparators which each compare the input to a different reference voltage. All of the comparators whose reference voltage is higher than the input voltage will produce a logical true output. A priority encoder then generates a digital output corresponding to the lowest comparator whose output was activated. The delay time from input to output equals the sum of comparator plus encoder delays. Although this latency does not increase significantly with the size of the encoded output, the sheer size of the circuit essentially doubles with each additional output bit desired. Thus, the size of flash aVD makes that approach prohibitively expensive for many modem applications. Multi-step encoding is a variant on the simple parallel flash encoding. A three-step twelve bit A/D is shown in Figure 2. In the first stage, the four most significant bits are generated by a standard four bit flash circuit similar to the one discussed above. A four-bit digital to analog (D/A) converter then converts the output of the first stage back to analog. The difference in voltage between the input and the output of the converter is then fed into a second stage. The second stage has a reference voltage which is 2 times (one sixteenth) the reference voltage used in the first stage. The second most significant four bits are produced by the second stage, and another four bit D/A converts the value back into an analog signal, which is subtracted from the difference obtained from the subtracter of the previous stage. Finally, the last stage has a reference voltage which is 2 times the voltage of the previous stage, or 2 " (one two-hundred-fifty-sixth) times the original reference voltage. This stage produces the four least significant bits of the result. All twelve bits are then latched, and the output is available for use. Successive approximation is a prior art method of producing the output bits in order of descending significance. Figure 3 is an example of a successive approximation circuit. In one implementation, all bits of the register are initially set to zero, then the most significant bit is set to a one, thus forming an initial guess. This guess is converted to analog by a D/A, and the output of the D/A is compared to the input voltage using a standard comparator. If the input voltage is higher than the analog guess, the most significant bit remains a one, otherwise, the most significant bit is set to back to zero. In the next steps, the next most significant bits are provisionally set to one, and comparisons are similarly done to determine each bit. Essentially, an iterative binary search is performed until the least significant bit is determined. There are several other types of popular aVD converters which use charge balancing on a capacitor to facilitate a D conversion. Some of those methods including voltage to frequency conversion, single- slope integration, dual-slope integration, delta-sigma converters, and switched capacitor converters. See, for example, Horowitz, P., and Hill, W., The Art of Electronics. 2nd Ed., Cambridge University Press. 1989, pp. 621-629. Several of the above-mentioned aVD converter strategies can be pipelined. A typical N-bit pipelined A/D converter consists of J, K-bit stages, where J * K = N. For example, five stages (J = 5) each producing 2 bits (K = 2) would result in a 10 bit converter. Figure 4A shows a single stage of a pipelined A/D converter. Figure 4B shows a multistage pipeline architecture using the single stage of Figure 4A. In Figure 4A, the analog input is sampled and held. The result is converted to a K-bit digital code by a analog to digital subconverter. If this is the first stage, the K-bits produced are the most significant bits of the final output. This digital code is used by a local digital to analog converter to create the analog equivalent of the K-bit digital code. This estimate is then subtracted from the original analog input to create a residue, which is essentially the analog remainder. The resulting analog residue is then multiplied by 2 and sent to the next stage. The resulting residue can be calculated from the following formula. Vres t = 2 K * (Kr« ( ., - Vdac) U) Each stage can be identically designed, unlike the multistage flash encoding discussed earlier, in which each successive stage has a lower reference voltage. In the pipelined A D converter, because the residues are multiplied by 2 , each successive stage has the same range of input voltages, rather than having that range geometrically decreasing toward zero. If the D/A converter in each stage is linear, the D/A converter output will be represented as follows. Vdac l = D, * 2 K * Vref (2) In Equation 2, D- is the binary representation of the K-bit digital code determined in each stage. D- * 2 _I merely represent the fraction of V rc f which has already been encoded and is to be subtracted from the analog remainder Vres^ j . V f ^ is set such that the input voltage Vres- will always be less than V re ^. The remainder is multiplied by 2 K before being sent to the next stage. The central problem with this scheme, however, is that the overall linearity of the total converter is dependent upon all the digital to analog conversions being linear. For a digital to analog conversion to be linear, the differences in output voltage Vdac* for each one bit increment of the input D- must all be equal. There are two ways in which this problem has been attacked. The first way involves setting K = 1. Thus, each stage produces only one bit. In this case, the analog to digital subconverter produces only a one bit code. If K = 1, the digital to analog converter in each stage only has two possible output voltages. This D/A conversion will always be linear, since there is always a straight line that can be drawn between two points. In this case, the ideal gain of each converter stage is two. By substituting K = 1, Equations 1 and 2 produce the following residue equation. Vres,. = 2 * Vns,_. - D i * Vref (3) It is helpful to think of D- as representing either of the two values -1 or +1. A simple circuit such as the one shown in Figure 5 is typically used to generate the residue. Operation of this circuit is simple. A two-phase non-overlapping clock is used to generate control of the circuit. Figure 5A shows the circuit in its sampling phase. During the sampling phase, switches S ] A , S j g, and Si are all closed, and switches S 7 A and S2g are open. Switch Si holds the operational amplifier as a follower. Switches S j ^ and S j g cause the input voltage Vres* , j t0 be sampled on both capacitors Capl and Cap2, respectively. Thus, both capacitors are charged to a voltage of Vres- , j . A one-bit analog to digital converter is just a comparator. At this time, the comparator compares Vres j . ■ with ground, producing the digital output D j as follows. £>. = 1 if Vres i > 0, and Z>, = -1 if Vns, . . < 0 Figure 5B shows the circuit in its output phase. During the second phase of the non-overlapping clock, switches $2^ and S2J3 are closed, while switches S , Si g, and S- are open. Capacitor Capl is connected to the output of the operational amplifier by Switch S R, while Cap2 is connected by Switch ^2 A t0 e * t * ιer + ^ref or -V re f depending on the digital output code D:. Assuming that Capl and Cap2 have equal capacitances C, by connecting Capacitor Cap2 to either + V re f or -V τe f, the output of the operational amplifier is forced to the desired residue given by Equation 3. However, in the non-ideal real world it is impossible to exactly realize the transfer function of Equation 3. First, it is impossible to make the capacitances of Capl and Cap2 exactly the same. The variable α j represents the capacitor mismatch for stage i. Capl has a capacitance of C, while Cap2 has a capacitance of (1+α-) * C. Second, a real operational amplifier does not have infinite gain and does not settle instantaneously, but rather has a finite gain and non-zero settling time. Errors due to the finite gain and non-zero settling time in stage i are represented by ε-. Another source of error is charge injection onto the capacitors due to Switch S- c . Furthermore, an ideal operational amplifier has a zero output when the inputs are shorted together; in contrast, an actual operational amplifier has a non-zero output voltage when the inputs are shorted together due to imperfect matching of components within the operational amplifier. Vofs- represents the total offset in stage i due to the sum of charge injection effects and operational amplifier offset. When the three error factors α*, ε*. and Vofs- are introduced into the derivation, the real world transfer function is as follows. Vres. = [(2+ ?)*Vres i _ l -( -. D i *Vref {\ -*YVofi: i (5) Figure 6A shows the ideal one bit per stage residue transfer function. The x-axis shows the range of input residues while the y-axis shows the resulting output residues. Note that the slope from (- v re f - V re f) to (0-+V re f) and from (0,-V ref ) to ( + V re f,+V ref ) is two; therefore, this stage has an ideal gain of t o. Figure 6B shows the effect of capacitor mismatch d j . Capacitor mismatch errors do not shift the endpoints of the transfer characteristic, but they shift the slope and thus the residue at the transition points. If α- is negative, Cap2 is less than Capl, the slope of the transfer function is less than two, and the Vres j output range is less than -V re f to +V rc f. On the other hand, if is positive, Cap2 is greater than Capl, d e slope of the transfer function is greater than two, and the Vres- output range is greater than -V^ to +V^. Figure 6C shows the effect of errors due to finite operational amplifier gain and/or incomplete operational amplifier settling (ε*). Error due to ε- shifts the endpoints as well as introducing errors in the residue transfer characteristic at the transition points, while preserving the correct output only at the points (-V ref 0) and (+V ref 0). Figure 6D shows the effect of errors due to charge injection and operational amplifier offset (Vofs;). These eirors shift the whole characteristic vertically. This does not introduce a gain error but the end points and the residue transfer characteristic at the transition point is shifted. Figure 6E shows the effect of errors due to comparator offset. These errors essentially just change input voltage Vres-. j at which the transition from D: = -1 to D: = 1 occurs. Instead of occurring at = 0, this transition will occur at some higher or lower input voltage. This does not introduce a gain error, but the end points and the residue transfer characteristic at the transition point is shifted. Errors due to comparator offset alter the Equations 4 governing the determination of the Din bits as follows. D i = 1 if Vres^. Vco, > 0, and Z = -1 if Vres i _ l *Vco i < 0 Gain variances are created by capacitor mismatch and by finite operational amplifier gain and settling. Any of the above errors which affect the gain, such as those depicted in Figures 6B and 6C, will cause differential nonlinearity problems with the converter. If the cascade of N converters has a gain larger than 2 and the overall error is more than 1 least significant bit, then at least one A/D converter output code will correspond to a range of input voltages greater than the minimum required resolution of the converter. On the other hand, if the gain of the cascade is less than 2 by at least one least significant bit. then missing output codes will result since some output codes will be skipped as the input changes incrementally. Moreover, if the output residue of a stage happens to be above +V re f or below -V re f for any reason, then the output bits of remaining subsequent stages will all latch to +1 or -1 respectively. This can occur as a consequence of any of the previously mentioned sources of error, such as too large a gain or vertical or horizontal shifting, if the input voltage just happens to place the output of that stage outside the acceptable range. The phenomenon occurs because an output above +V f or below -V n f necessarily supplies the next stage with an input which is outside its intended range. That stage will supply the following stage with an output which is twice is far out of range as its input was. Essentially, once the output of one stage goes out of range, that excess is multiplied by the gain factor for each additional stage. After very few stages, all the remaining stages are outputting residues that are essentially either the positive or negative supply voltage, and all the remaining coded bits coming out after that stage reaches the power supply limitation are meaningless. The typical way that has been used to protect against this very catastrophic situation is to introduce an intentionally reduced gain. (Radix 1.95 is typical.) Figure 7 shows the transfer function of a Radix < 2 stage. The range of possible outputs is less than -V fef to +V ref . This allows for a margin of error which can be designed large enough so that it is extremely unlikely that any of the errors will put the output voltage outside the acceptable input range. If any of the above-mentioned errors significantly affect the shape of the transfer curve, they can be accommodated by the built-in safety zone. Unfortunately, however, the reduced gain necessitates the use of more stages to encode the overall output. Since the output bits now are essentially base 1.95 rather than base 2 numbers, and a complex correction equivalent to a series of nested multiplications is required to do the final conversion. TTie major drawback with all of the systems using radix less than two techniques is that they require this large complex conversion circuit to transform the number from a radix less than 2 representation into a true binary base 2 representation. In many systems, this final translation is so complex that it is performed in software, greatly adding to the latency of the corrected output. If the final translation is implemented in hardware, and especially if that hardware is designed to run at frequencies as high as 40 MHz, this final conversion uses an inordinately large amount of power, silicon area, and generates noise which interferes with the performance of the analog sections of the A/D converter system. The proposed architecture of the present invention eliminates the need for a radix conversion circuit. A second pipelined converter evolutionary path has developed independently which utilizes large amount of redundancy. The technique has been referred to as a "1.5 bit per stage pipelined" architecture. The 1.5 bit stage derives its name from the fact that each stage has three possible outputs, rather than only two in 1 bit stages. This amount of redundancy, which asymptotically approaches 100% as the number of output bits N increases, eliminates the effects of comparator offset errors up to rej 4. This technique appears to be manufacturable up to the 10-bit level, at 20 MS/sec. For accuracies greater than 10-bits, calibration becomes necessary to compensate for the other errors due to capacitor mismatch, operational amplifier offset, charge injection, and finite operational amplifier gain and settling. The 1.5 bit per stage architectures derive their insensitivity to analog to digital subconverter offsets by reducing their gain by a factor of two. The most typical configurations detect two bits per stage but with an interstage gain of two instead of four. Then it was realized that the two bits per stage could be achieved with only two comparators per stage, thereby reducing power. See S. Lewis, et al., "A 10-bit 20 Msample/s Analog-Digital-Converter", IEEE J. Solid State Circuits, vol. SC-27, no.3, pp. 351-358, March 1992. The two comparators per stage only realize three states instead of four, but the fourth state can be inferred by carry overflow in the final arithmetic. Because there are three states, requiring two bits, detected per stage but the interstage gain is two, a redundancy level of almost 100% is realized. A N-stage A/O converter, with no non linearities, has 2 N+ ' output codes but has 2 2( N+ , )-N-2) unique states. Some of the unique states represent the same output codes. Thus, two or more unique states may represent the same output code. So an 1 1 stage converter ideally has 4096 output codes but 8166 states. In other words, 4070 states are redundant in that they represent the same output codes which are already represented by some other state. The residue of the 1.5 bit per stage converter is shown in Figure 8. In the middle portion of the transfer function the ideal peaks at the transitions are only +V ej 2 and -V re ^/2. This residue design solves the problem of errors due to charge injection and offset in that there is room for ±V fe f 2 error due to incorrect decision levels or charge injection. The equation of the transfer characteristic is the same as that for the one bit per stage design— Equation 3. However, the equation for the data bits detected at each stage is different. The digitized representation of the input voltage is as follows. At this point it is useful to consider a numerical example. Consider a converter with N = 7; this produces an 8 bit output code. The output sequence in Table 1 was generated through simulation given an increasing analog input voltage with large random gain errors on the order of 5%. The first noteworthy observation is that several of the codes are represented by more than one set of output bit sequences. For instance, 29, 30, 31, 32, and 33, are each non-uniquely represented in Table 1. For each of these redundancies, one of the following two relations holds true. 2 * D, * D i = -1 (9A) D (9B) What this means, for example, is that 3 can be represented as 1(4) + -1(2) + 1(1) or as 1(4) + 0(2) + -1(1). In this example D- is the second least significant bit, and D j+j is the least significant bit. such that 2 * D j + D j+ 1 = -1 since 2 * -1 + 1 and 2 * 0 + -1 both equal - 1. To illustrate the other situation, 5 can be represented as 1(4) + 0(2) + 1(1) or as 1(4) + 1(2) + - 1(1 ). Here, D j is the second least significant bit, and D j+ - is the least significant bit, such that 2 • D j + D ]+ . = 1 since 2 * 0 + 1 and 2 * 1 + -1 both equal +1. The second noteworthy observation is that the output codes are non-monotonic. Since the analog input voltage increased steadily throughout the table, a proper A/D coding would have produced a monotonic output. This means that the output code should either increase or remain the same at each subsequent sample, but it should never decrease. Here, the output code jumps from 32 back to 30 in the middle of the table. This is a perfect example of a non-monotonic output. Figures 9A, 9B, and 9C show an analog input and two A/D converted output codes as an illustration of the difference between monotonic and non-monotonic outputs. Figure 9A shows the analog input; Figure 9B shows a non-monotonic output; Figure 9C shows a monotonic output. The 1.5 bit per stage structure is extremely insensitive to offsets due to the operational amplifier, charge injection, and the a*VD subconverter comparator. However, it does not correct for linearity errors due to finite operational amplifier gain and/or capacitor mismatch. Several implementations exist that provide a "self-calibration" scheme. See S.H. Lewis, H.S. Fettermaπ, G.F. Gross, Jr., R. Ramachandran, And T.R. Viswanathan, "A 10-bit 20 Msample/s Analog-to- Digital Converter," IEEE J. Solid-State Circuits, vol. SC-27, pp. 351-358, March 1992; B. Ginetti, P.G.A. Jespers, and A. Vandemeulebroecke, "A CMOS 13-b Cyclic RSD A D Converter," IEEE J. Solid-State Circuits, vol. SC-27, pp. 957-965, July 1992; H.S. Lee, "A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC," IEEE J. Solid-State Circuits, vol. SC-29, pp. 509-515, April 1994. None of these schemes can guarantee a monotonic characteristic after correction. Self-calibration uses the converter, in a calibration configuration, to measure the capacitor mismatch, and then forms a digital correction value based on the raw code. The monotonicity problem occurs for the very large class of A/D converter architectures in which multiple representations of the same output codes occur. To illustrate the idea, a n-stage (n+1 bits) A/D converter with a 1.5 bit per stage implementation is considered. Each data bit D j can take three different values: -1, 0, +1. The digital representation of the input is given by the following equation. "-- D V = V . y — (10) The self-calibrating correction algorithm adds a correction term to this digital representation. Very generally, this correction term is of the form below. n-l e , " ∑ D,*Φ J ( β v o 1 ,... β J ) (11) 1-0 In Equation 1 1, φ j (α 0 ,α j ,...α j ) is a function of the capacitor mismatches for stage i and all preceding stages. If α j represents the capacitor mismatches, the functions φ j (α 0 ,α j ,...α j ) are given below. φ/o 0 ,o 1 ,... 1 ) = 2-» * *»<α β *«,*α M -α.) (12) In the ideal case when there are no gain errors, the total number of states in the converter can be calculated as 2 n - 2 * (n + 2). As n gets larger, the average number of representations for each output code approaches two asymptotically. These multiple internal states occur at the common transition points of data bits D j and D + , with the rest of the data bits unchanged. From residue considerations, the following multiple representations appear in sequence for increasing input values. D, = -1, D„. - 1 (13a) D, = 0, D i = -1 (13b) Equations 13a and 13b are the solutions to Equation 9A. If all other raw output data bits are the same, and if one output satisfies Equation 13a while the other satisfies Equation 13b, both outputs represent the same code and thus are dual representations of the same code. However, the analog input that generated the raw output corresponding to Equation 13a was lower than the other by an amount less than 1 least significant bit of precision. Similarly, the following equations are the solutions to Equation 9b. D, = 0, D„ χ = 1 (14a) D t = 1, D„. = -1 (14b) It is also true that the analog input that produced the raw output corresponding to Equation 14a was lower than the other by an amount less than 1 least significant bit of precision. Therefore, a necessary condition for monotonicity is that whenever multiple representations of the form 13a and 13b occur, the correction term (Equation 1 1) calculated for the representation 13a is less than the corresponding correction term for 13b. The same must be valid for multiple representations of the forms 14a and L4b. For any stage that has only two non-zero output values which are negatives of each other, such as a 1.5 bit per stage converter or a 1-bit per stage converter, a linear correction algorithm is one that assumes that the correction value for the positive output is the negative of the correction value for the negative output. Using any linear correction algorithm, the necessary conditions for monotonicity become the following. for all i = 0,l,...n-2, φ(α 0 ,α,,...α ( ) ≥ 2φ j ,,(c* 0 ,α 1 ,...α, < ,) (15) Substituting the relations of Equation 9, into the constraints in Equations 12, the monotonicity conditions are as follows. α„, ≥ 2* p for i = 0,l,...π-2 (16) The constraints in 16 are equivalent to a reduced nominal gain for each calibrated stage. Equation 16 established restrictions on the gain mismatches, which are not apriori satisfied. This further implies that non-monotonic behavior may occur even after the digital correction, or, equivalently, the correction algorithm can not guarantee the converter's monotonicity. In the example shown in Table 1, the non-monotonic behavior of the raw output code is generated by the interstage gain errors. The correction algorithm should be able to identify all possible multiple representations and correctly resolve the monotonicity conditions. However, since the gain mismatches are essentially random, it is impossible to guarantee the satisfaction of the constraints in 16. The powerful conclusion that can be drawn from Equation 15 is that monotonicity can not be guaranteed in general for arbitrary gain mismatches for any A D converter architecture that generates multiple representations of the same output code. This conclusion is valid for any linear correction algorithm that computes an error term as a function of stored self-calibrating data and raw data bits. SUMMARY OF THE INVENTION In pipelined analog to digital conversion, many converters have the problems of missing digital output codes, non-monotonic digital output, overflow amplification error, and complicated radix conversions. Missing digital output codes occur when not all of the possible digital output codes can be produced by the converter and thus some codes are skipped. A non-monotonic digital output occurs when a smooth analog increasing "ramp" input produces a digital output which does not steadily increase, but rather decreases or jumps backwards at times. Overflow amplification error occurs when a stage of a pipelined analog to digital converter produces an analog remainder or residue which is outside the intended input range for the next stage, such that the next stage amplifies the amount that the residue is out of range, and within a few stages, the remaining stages hit the power supply voltage, so that the converter no longer is in a linear range and is thus no longer converting. Radix conversion is necessary when the average gain of each stage significantly and substantially departs from 2, so that the final output must be adjusted using a calculation which can be as difficult as a series of nested multiplications in order to convert the output. The present invention solves all of the above problems. In a pipelined radix 2 analog to digital converter, a method of analog residue formation uses an overflow reduction stage which takes an analog input and outputs a digital value of +2, 0, or -2 and an analog residue which is twice the analog input minus the digital output value times a reference voltage. This digital output leads to raw code outputs which all represent different corrected output codes so that no multiple representations exist. A calibration technique allows a pipelined analog to digital converter using the overflow reduction stages to produce a corrected output requiring one addition per pipeline stage. Calibration of such raw codes allows a monotonic corrected output to be produced. Instead of amplifying interstage analog overflow, the analog residue scheme of the present invention prevents the occurrence of overflow amplification since any analog input to an overflow reduction stage which is out of range will be brought back into range. This overflow elimination property is a consequence of the shape of the input/output characteristic; out-of-range inputs are mapped to in-range outputs near zero. Specifically, the overflow reduction stage has its lowest output levels at the extremes of its input range, so that gaining up of interstage errors does not exceed the input range of subsequent stages. The residue portion of the overflow reduction stage can be constructed using an operational amplifier, two capacitors, one of which has twice the capacitance of the other, and three on- off type switches. An overall pipelined converter design uses a combination of standard 1-bit stages and overflow reduction stages to perform a radix 2 analog to digital conversion. A radix 2 pipelined converter is constructed using a combination of standard 1-bit stages and overflow reduction stages. The analog residue is passed from stage to stage as an amplifier remainder as the digital codes are extracted in a pipelined analog to digital converter. The overflow reduction stage reduces out-of-range residues back to in-range residues. Using three digital output values where the difference between any two is greater than one raw output code prevents the possibility of multiple representations of the same code and thus allows for the prevention of non-monotonic input-output transfer functions. The self-calibration and raw output code correction schemes prevent non-monotonicities and missing codes in the input-output transfer functions. Since the converter is radix 2, no radix conversion is necessary because the result is already a valid binary representation. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a prior art flash-type N-bit analog to digital convener. Figure 2 shows a prior art multi-step 12-bit analog to digital converter. Figure 3 illustrates a prior art successive approximation N-bit analog to digital converter. Figure 4A shows a single K-bit converter stage of a prior art pipelined analog to digital converter. Figure 4B depicts a prior art N-bit pipelined analog to digital converter using J separate instances of the K-bit converter stages shown in Figure 4 A. Figure 5 shows a prior art circuit implementing a 1-bit converter stage using a two-phase non- overlapping clock. Figure 5 A shows the state of the prior art circuit of Figure 5 during phase 1 of the non-overlapping clock. Figure 5B shows the state of the prior art circuit of Figure 5 during phase 2 of the non-overlapping clock. Figure 6 A shows the ideal residue transfer characteristic of a 1-bit radix 2 converter stage such as the one shown in Figure 5. Figure 6B shows the effect of capacitor mismatch on a 1 -bit converter stage such as the one shown in Figure 5. Figure 6C shows the effect of finite amplifier gain and settling error on a 1-bit converter stage such as the one shown in Figure 5. Figure 6D shows the effect of charge injection or amplifier offset errors on a 1-bit converter stage such as the one shown in Figure 5. Figure 6E shows the effect of analog to digital subconverter comparator offset errors on a 1-bit converter stage such as the one shown in Figure 5. Figure 7 shows the ideal residue transfer characteristic of prior art radix < 2 converter stage. Figure 8 shows the ideal residue transfer characteristic of a prior art 1.5-bit converter stage. Table 1 shows the simulated digital output for a prior art analog to digital converter having an a monotonically increasing analog input and random gain errors on the order of 5% per stage. Figure 9A illustrates a typical monotonically increasing analog input for an analog to digital converter. Figure 9B illustrates digital converter output for an input such as Figure 9A where the output has missing codes and non-monotonicities. Figure 9C illustrates digital converter output for an input such as Figure 9A where the output does not have missing codes and non-monotonicities. Figure 10 shows the ideal residue transfer characteristic for the overflow reduction stage of the present invention. Figure 1 1 depicts a pipelined 1 1-bit converter using overflow reduction stages according to the present invention. Figure 11A depicts a recirculating algorithmic implementation of a converter using an overflow reduction stage of the present invention. Figure 12 shows a circuit implementing an overflow reduction stage according to the present invention. Figure 13 A illustrates the input/output transfer characteristic of a prior art analog to digital converter having non-monotonicities and missing codes. Figure 13B illustrates the input/output transfer characteristic of an ideal analog to digital converter. Figure 14 depicts the self-calibration of a pipelined 5-bit analog to digital converter according to the present invention. Figure 15 depicts a self-calibrated, pipelined 5-bit analog to digital converter that performs pipelined correction according to the present invention. DETAILED DESCRIPTION OF THE INVENTION A major goal of analog to digital converter design of the present invention is to maintain the mathematical elegance of a self-calibration algorithm, but in such a way as to not require a complex digital radix conversion circuit. As discussed above, previous schemes do not guarantee monotonicity because of the presence of redundant states. The present invention solves both of these problems by first maintaining a radix 2 gain structure throughout the entire gain path of the converter. Since the gain in each stage varies from two only by the amount due to circuit imperfections, which is usually a small amount, the interstage gain error is on the order of 0.4%. The reduced radix circuits purposefully introduced gain variations on the- order of 5% or more. These interstage gain errors multiply as they pass through the converter, thus the overall gain error for an N-stage converter is as follows: The ideal gain is 2 . Therefore, if it is assumed that each stage has an average gain error of α, the actual total gain is wrong by the factor of (1 — )" . For levels of α near zero, this is approximated by the following. (1 --)" = l -N- for small a ( 18) In the present invention, each stage is designed to have a gain of two, any gain errors will be uncorrelated and, therefore, the overall gain is likely to be very close to two. This means that if the error per stage α is small enough and the number of stages N is small enough, the output can be adjusted simply by multiplying the output by (l +N— ) . This is true because 2 of the following: for small x, — = 1 +x ( 19) l -x The actual non-approximated correction value is the following expression: 1 (19A) ϊ However, the approximation multiplication operation can actually be simplified significantly from a full-blown multiplication if the design has been done carefully so that it is possible to insure that the accumulated error AT— is small enough. The reason the correction can be simplified is that if N— is small, then 1 + N— has at most a few least significant fraction bits that are non-zero. Almost all of the fraction bits are zero. Therefore, the "multiplication" becomes merely at most a few shifted additions. Since the preferred embodiment of the radix 2 system of the present invention is implemented in VLSI, it is possible to lay out the converter so that any process variations that might cause gain errors are negatively correlated with each other. For instance, if there is a doping gradient on the chip, some convener stages might have a positive error while others would have a negative error of an equal and offsetting magnitude. This means that process variations will not cause overall gain error, and that any overall gain variation is essentially random and is very small. For example, assume the average per stage error α is on the order of 0.4%, which is estimated as being more than three standard deviations from die mean of zero in a typical layout and process. Being three standard deviation from the mean, 99.9% of the conveners will have a lower average α. If the number of stages N is 11, and an eight bit output is desired, the actual correction factor is 2.226630408%, whereas the error as determined by approximations 18 and 19 is 2.2%. The most significant 12 bits of the approximation and the true value of the eπor are equal. Since only eight bits of output are required, the approximation works just fine. In binary, the correction multiplier in this case is 1.00000101 101. Since only an eight bit output is required, this multiplication is accomplished with only a one shift and addition of the raw output according to the present invention since only one of the first seven fraction bits is non-zero. In contrast, prior art radix < 2 systems purposefully design an α on the order of 7% (as in Karaniclas et al.) into the converter. If α is set to 7%, the approximations show a correction of 38.5% where the true correction should be 47.97881772%. Here the approximation and the true correction value agree to within only four bits. Since an eight bit result is desired, the approximations can not be used. Alternatively, a very complicated radix conversion circuit equivalent to a series of nested multiplications must be used to convert the raw output using the actual unapproximated conversion factor. The above discussion illustrates the great advantage to maintaining a radix 2 structure. The present invention allows for the maintenance of a radix 2 structure while eliminating the chance of "range overflow error." This type of error, discussed above, occurs when the input to a stage is above +V re f or below -V re f so that the output of that stage is twice as far out of range, resulting in that stage and all the remaining stages latching to the same meaningless output value. Figure 10 shows a residue transfer function for a novel 1.5 bit "overflow reduction" stage according to the present invention. In the present invention, the redundancies are removed by redesigning the residue. Figure 11 shows an 11-bit pipelined converter constructed using the present invention. Nine of the stages 10 are of the standard 1 bit per stage variety well known in the art. However, overflow reduction stages 20 are placed at the fourth and eighth stages. The exact pipelined sequence of overflow stages with 1-bit stages is not critical. There should be enough overflow reduction stages to alleviate overflow errors occurring in the manufacturing process used for producing the convener. The overflow reduction stage has two very desirable qualities. First, the peaks of this residue occur when the input residue is at + V re f and -'/-V re f. This means that the gain peaks do not coincide with d e other 1 bit stages, so that an A/D convener built with a combination of both designs will be as insensitive to charge injection and amplifier offsets as the prior an design constructed solely of cascaded 1.5 bit stages. Assume that the previous stage suffered from one or more of the many causes of error, and that its residue input was unlucky enough to be at a level which produced an output that was above + V- e f or below -V re f Since the residue transfer function for the overflow reduction stage for inputs near +V re f and -V re f has no discontinuities and output a residue near zero, the overflow reduction stage has the extremely important characteristic that it reduces the out-of-range residue input into an in-range residue output. Catastrophic geometric overflow growth is eliminated. It is desirable to place the overflow reduction stages strategically in the convener, so that there is never a chance that any out of range input can multiply enough to reach a power supply voltage before that residue is brought back into appropriate input range by an overflow reduction stage. Thus, to insure correct conversion, the designer will determine what the worst case overflow for a stage will be and how much far out of range any stage can operate before the output becomes non-linear (or flat in the worst case when the power supply is reached). A cany overflow stage will be inserted into the converter chain so that overflow will be reduced before any non-linearities could occur. It is worth noting that just because the output of a 1 -bit stage is out of range, the subsequent outputs which all have the same value prior to overflow reduction are not necessarily meaningless, so long as the supply voltage has not been reached to destroy the gain of the residue transfer characteristic. This is because the situation which leads to an out of range output occurs when the voltage is very near the discontinuity boundary of the residue transfer characteristic. Consider the case where in a radix 10 convener, for instance, the analog input corresponds to a digital value of 9995412 and the first stage detects the first 9. It is perfectly natural for two other 9's to follow, depending upon how close the input voltage was to the boundary. However, if one of the converters sends a residue that is out of range that is multiplied by 10 each stage, the system will run up against the supply voltage limit. In that case, if the supply voltage is reached before the fourth stage, where a 5 is supposed to be output, the overall convener output will be 9999999, and the accuracy will be lost at that point. The correct overall output could have been salvaged if an overflow reduction stage had been used. Any error due to imperfect gain or mismatch can be calibrated and corrected so long as the convener stages remain in their linear ranges and do not slam up against the power supply. Figure 1 1A depicts another possible use of the overflow reduction stage. This is a recirculating algorithmic implementation. In this design, there is a mini-pipeline of some number of 1-bit per stage sections 10 followed by one overflow reduction stage 20. The residue of the overflow correction stage is fedback to the first stage through the analog multiplexor 25. In this manner, a small converter chain can be used to generate a high resolution output. Each stage produces output bits through digital output lines 15. Most pipeline schemes can also be used as algorithmic converters in this manner. A second very important characteristic of the overflow reduction stage is diat it introduces a gap into the output codes so that multiple representations of the same code are not possible. Although the overflow reduction stage has three possible digital output states D j , those output states are D j = -2, Dj = 0, and D j = +2. This introduces number gap into the raw code when this stage is reached because the differences between -2 and 0, and between 0 and 2 is greater than one code. Most of the stages are standard I bit stages, and although this overflow reduction stage has three possible output values, the fact that there is a number gap in its output reduces the possibility of multiple representations of the same code. There are no multiple representations possible in part because each Equation 9A and 9B have only 1 possible solution. To illustrate this, assume that output D ; comes from an overflow reduction stage, thus D j has possible values of 2, 0, and -2. D j+j necessarily has a 1 bit representation of 1 or -1, since overflow reduction stages should not be directly cascaded with each other since there is no advantage to doing so. In this case, the only solution to Equation 6A (2D j + D j+j = -1) is D j = 0 and D= +| = -1. The only solution to Equation 6B (2D j + D j+1 = 1) is D j = 0 and D j+1 = 1. Since neither Equation has multiple solutions, the multiple representations inherent in a the prior art 1.5 bit per stage architecture are eliminated. Furthermore, the possible values taken on by the D j D j+J viewed as a binary number are as follows. 2D j + D i+1 = 5, 3, 1, -1, -3, or -5 (20) if D j = 2, 0, or -2, and D j+1 = 1 or -1 Now assume that input D j is a 1 bit stage, and D j+1 is a overflow reduction stage. Thus, D j has possible values of 1 or -1, and D j+j has possible values of +2, 0, and -2. In this case, D j+j is viewed as representing two binary orders of magnitude. Thus, the possible values taken on by D j D j+ j viewed as a binary number are as follows. 4D j + D i+1 = 6, 4, 2, -2, -4, or -6 (21) if D j = 1 or -1, and D j +1 = 2, 0, or -2 Note that neither of the above representations contains a code for zero. Note also that there are no multiple representations for any of the possible output codes. Each output code has only one combination of D j and D j+ , which represents that code. Because the minimum difference between any number having D j = 2 and any number having D j = -2 is greater than 1 least significant bit, there is a number gap in the output code when the carry occurs and the transition is made from D j = 2 to D j = -2. Figure 12 shows an overflow reduction stage according to the present invention. During the first phase of the non-overlapping clock, Switches ip 31 and Si ^ 32 are closed, and Switch i^^ 33 is open. Capacitor Cap2 34 has a capacitance which is twice as high as the sum of Capacitor Capl 35 and some mismatch error α j . Capacitor Capl 35 is held to zero volts during this phase, while capacitor Cap2 34 samples VreS j j . During phase 2 of the nonoverlapping clock, Switches S^Q 31 and S j ^ 32 are open, while Switch 33 is closed. During phase 2, D j * rej 2 is connected to Cap2 34. The residue transfer function for this circuit is below. Vres, = (0.*a)Vr s i _ (\ *-^)D,Vref (\ -^γ β l (22) During phase 2, the output Vres j is generated according to the above transfer function. Fully differential configurations of the converter are also possible. In a fully differential converter, each op amp has a positive and a negative output as well as a positive and negative input. In practice, most pipelined converter implementations are fully differential because the output swing of the amplifier is almost twice the single-ended configuration. This maximizes the signal to noise ratio on the chip. In addition, by using a diffential implementation, certain charge injection errors are substantially matched from positive to negative signal paths, then when they are subtracted (Vout+ - Vout-), the charge injection is essentially cancelled. Differential implementation is a standard technique, although most descriptions in the journals are described with single-ended amplifiers to make the drawings less confusing. Digital self-calibration accomplishes the purpose of eliminating the missing codes and preventing non-monotonicities by insuring that the overall converter gain is linear. Figure 13A shows an overall convener gain which has missing codes and non-monotonicities. Figure I3B shows an overall convener output where there are no non-monotonicities or missing codes. On both Figures, the analog input voltage V jπ is plotted along the X-axis V jn , while the digital output is plotted along the Y-axis. Figure 14 shows the self-calibration structure of a five-bit pipelined converter having an overflow reduction stage 80 at stage 3. The digital self-calibration occurs beginning with the last stage 50 which produces the least significant results, which in this case is a 1-bit stage. During the calibration of the 1 bit stage 50, the input is forced to the discontinuity point which is at or near zero on Figure 6A which shows the transfer characteristic for a 1-bit stage 50. The difference in voltage from the highest point on the left of die function (where D j = -1) to the lowest point on the right of the function (where D j = 1) is determined. SI and S2 correspond to the quantized representation of V oul , when V jn = 0 with D = -1 and D = 1, respectively. The digital self-calibration algorithm can be represented as follows: Y j = X j , if D j = -l (23) Y j = X j + S j , if D j = 1 where D j is the bit decision, X j is die raw code, S j is Sl j - S2 j , and Y j is the transformed code. This transform ensures that the output code Y j widi V jn = 0 is the same for D = -1 and D = 1, eliminating missing codes that might otherwise occur if the gain of the stage were less than two, and eliminating d e non-monotonicity and duplicate codes that might otherwise occur if the gain of the stage were greater than two. This logic and arithmetic are performed by a calibration logic module 70 associated with each stage. With the digital calibration of one stage 50 accomplished, the digital calibration of higher level stages 60 can proceed. Figure 14 demonstrates a structure for this procedure. The calibrated least significant stage is now used as an A D converter to measure the second to the last stage. Digital self-calibration of an overflow reduction stage 80 is similar to self-calibration of a 1-bit stage and is performed by a corresponding module 90 using the following steps. V jn is forced to - V j /2, which is at or near the first discontinuity 100 in the transfer characteristic shown in Figure 10. Similar to a 1-bit stage, a digitized difference, S* ow , is computed for this first discontinuity using the subsequent calibrated stages as an A D converter. V jπ is then forced to +V rej /2, which is at or near the second discontinuity 1 10. The digitized difference, S gj ., is similarly computed. The calibrated output Y for an overflow reduction stage is calculated as follows. Y - X, if D = -2 (24) Y = X + S, ow if D = 0 Y = X + S low + S high if = 2 To avoid having to perform two additions if D = 2, the stage 80 can store the sum of S- ow and S high as S total' m ^ tnat 1 uant - t y can be used t0 replace the last situation where D = 2 with the following. Y = X + S total if D = 2 < 25) Here, as well as in the other calibrated stages; at most one addition needs to be performed. Once the self-calibration has been completed, the calibrated correction quantities may be added and used to correct the raw output in a pipelined fashion as shown in Figure 15. Figure 15 shows a 5-bit pipelined analog to digital converter which utilizes the quantities determined by self-calibration to produce a digital output C5. It is not necessary to wait until all the Di outputs are produced before adding in the correction quantities Si. Instead, each single bit stage 120 needs only a register to hold the corrected output code and an adder to selectively add in that stages' corrected code. The overflow correction stage 130 needs those elements as well as an additional multiplexor to select which correction quantity will be added if addition is required. In Figure 15, Ci represents the corrected output code as it exists after stage i. C5 is the final corrected and calibrated output; no further processing is necessary. While the present invention has been disclosed above with particular reference to the preferred embodiment shown, this has been presented by way of example, not by way of limitation. Those of ordinary skill in the art would be enabled by t is disclosure to add to or modify this embodiment of the invention in various ways as needed and still be within the scope and spirit of the present invention as recited in the appended claims.

Claims: WHAT IS CLAIMED IS: 1. A method for producing a digital output and an analog residue from an analog input in an analog to digital convener, the method comprising the steps of: outputting the digital output as a first logic value and an analog residue which is substantially twice the sum of the analog input plus a predetermined reference level when the analog input is less than negative one half times the predetermined reference level; outputting the digital output as a second logic value and the analog residue which is substantially twice the analog input when the analog input is between negative one half times the predetermined reference level and positive one half times the predetermined reference level; and outputting the digital output as a third logic value and the analog residue which is substantially twice the sum of the analog input minus the predetermined reference voltage when the analog input is greater than positive one half times the predetermined reference level. 2. A method for producing a digital output and an analog residue from an analog input as in claim 1 , wherein the second logic value differs from the first logic value by an amount which corresponds to greater than one least significant bit increment of raw output of the analog to digital converter. 3. A method for producing a digital output and an analog residue from an analog input as in claim 1 , wherein the third logic value differs from the second logic value by an amount which corresponds to greater than one least significant bit increment of raw output of the analog to digital convener. 4. An apparatus for producing a digital output and an analog residue from an analog input in an analog to digital convener, die apparatus comprising: means for outputting the digital output as a first logic value and an analog residue which is substantially twice the sum of the analog input plus a predetermined reference level when the analog input is less than negative one half times the predetermined reference level; means for outputting the digital output as a second logic value and the analog residue which is substantially twice the analog input when the analog input is between negative one half times the predetermined reference level and positive one half times die predetermined reference level; and means for outputting the digital output as a third logic value and the analog residue which is substantially twice the sum of the analog input minus the predetermined reference voltage when the analog input is greater than positive one half times the predetermined reference level. 5. A apparatus for producing a digital output and an analog residue from an analog input as in claim 4, wherein die second logic value differs from die first logic value by an amount which corresponds to greater than one least significant bit increment of raw output of the analog to digital converter. 6. A apparatus for producing a digital output and an analog residue from an analog input as in claim 4, wherein the third logic value differs from die second logic value by an amount which corresponds to greater than one least significant bit increment of raw output of the analog to digital converter. 7. In an analog to digital converter, an apparatus for producing an analog residue output from an analog input and a reference input having two distinct levels, die apparatus comprising: amplification means having a positive input, a negative input, and an output terminal, for producing die analog residue output, wherein die positive input is connected to a predetermined voltage; a first capacitance having a first positive terminal and a first negative terminal, wherein the first negative terminal is connected to the negative input, and the first positive input is connected to the output terminal; a second capacitance having a second positive terminal and a second negative terminal, wherein the second capacitance is substantially two times the first capacitance, and wherein the second positive terminal is connected to the negative input; a first switch having an open connecting state and a closed disconnecting state which selectively connects the analog input to the second negative terminal; a second switch having an open connecting state and a closed disconnecting state which selectively connects the reference input to the second negative terminal; and a third switch having an open connecting state and a closed disconnecting state which selectively connects the output terminal to the negative input. 8. An apparatus as in claim 7 wherein the amplification means is an operational amplifier. 9. An apparatus as in claim 7 wherein the predetermined voltage is ground. 10. An apparatus as in claim 7, wherein both the first switch and the third switch are always either both open or both closed, and wherein the second switch is always open when the first switch and third switch are closed. 11. A method for correcting raw digital output of an analog to digital converter having a plurality of single bit stages with two digital output states and at least one overflow reduction stage having three digital output states to produce a corrected output, the method comprising the steps of: for each single bit stage, selectively either adding or not adding to die raw digital output one digital correction quantity which corresponds to that stage from a set of predetermined digital correction quantities, wherein the selective adding or not adding depends upon the digital output state of that stage; and for each overflow reduction stage, selectively adding or not adding to die raw digital output one of two digital correction quantit i es which correspond to two of the output states of that stage from a set of predetermined digital correction quantities, wherein the selective adding or not adding depends upon the digital output state of that overflow reduction stage. 12. A method for correcting raw digital output of an analog to digital converter as in claim 11, wherein the selected adding or not adding step corresponding to each stage is performed prior to the production of the digital output state for the subsequent stage. 13. An apparatus for performing a multi-stage pipelined analog to digital conversion comprising: at least one overflow reduction stage, each stage having a first digital output, a first analog input, and a first analog residue output, and each stage including, means for outputting the first digital output as a first logic value and a first analog residue which is substantially twice the sum of the first analog input plus a first predetermined reference level when the analog input is less than negative one half times the first predetermined reference level, means for outputting the first digital output as a second logic value and die first analog residue which is substantially twice the first analog input when the first analog input is between negative one half times the first predetermined reference level and positive one half times the first predetermined reference level, and means for outputting the first digital output as a third logic value and the first analog residue which is substantially twice the sum of the first analog input minus the first predetermined reference voltage when the first analog input is greater than positive one half times the first predetermined reference level; and at least one single-bit stage, each stage having a second digital output, a second analog input, and a second analog residue output, and each stage including, means for outputting the second digital output as a first logic value and a second analog residue which is substantially the first predetermined reference voltage plus twice the second analog input when the analog input is less than a second predetermined reference level, and means for outputting the second digital output as a second logic value and the second analog residue which is substantially sum of the negative of the first predetermined reference voltage plus twice the analog input when the analog input is greater than the second predetermined reference level. 14. An apparatus as in claim 13, wherein the apparatus is 1 1-bit, 1 1-stage, and the fourth and the eighth stages are overflow reduction stages, and all other stages are single-bit stages. 15. An apparatus as in claim 13, wherein a plurality of overflow reduction stages and a plurality of single bit stages are connected in a pipeline such that no two overflow reduction stages are directly cascaded. 16. An apparatus as in claim 13, wherein the apparatus is configured in an recirculating algorithmic implementation, such that one or more single bit stages are followed by one overflow reduction stage, and the first analog output is fedback to the second analog input.

Inventors: LEWICKI LAURENCE D, OPRIS ION E, LEWICKI, LAURENCE, D., OPRIS, ION, E.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1995
Main classification: H03M1
IPC codes: H03M1