Voltage-level shifter

Abstract: In a voltage-level shifter, a P-channel MOS transistor (early cut-off circuit) (Qp2403) is interposed between a voltage source (Vpp) of the voltage-level shifter and a source of a P-channel MOS transistor (Qp2402) which tends to be turned on when a voltage of a voltage source (Vcc) of an input signal supplies a low voltage or a large potential difference exists between the voltage source of the input signal and the voltage source of the voltage-level shifter, and is supplied on its gate with the input signal of the voltage-level shifter. Accordingly, the interposed P-channel MOS transistor (Qp2403) is turned off prior to the P-channel MOS transistor (Qp2402) having a tendency of being turned on, so that the voltage level of the output signal of the voltage-level shifter can be rapidly fixed at the "L" level.

Description: The invention refers to a voltage-level shifter according to the preamble of claim 1 as known from US-A-5,266,848. From US-A-5,266,848, a CMOS circuit is known having a signal receiving unit, a signal processing unit and a driving circuit. The signal receiving unit converts a small amplitude signal form a bus into a large amplitude signal. The signal processing unit processes the large amplitude signal. The driving circuit converts the large amplitude signal processed into a small amplitude signal processed to output on the bus. The aim of the decrease of the voltage amplitude of the signal on the bus is to reduce the power consumption of the whole arrangement while maintaining a high operation speed by making the voltage amplitude of the signal within the circuit blocks larger than the signal swing of the signal on the bus. US-A-4,490,633 shows a TTL to CMOS input buffer buffering a TTL signal to a CMOS signal without static current flow when the TTL is a logic "1". A first transistor which is of a first conductivity type has a control gate for receiving the input signal, a first current electrode coupled to a first power supply terminal, and a second current electrode for providing a first output. A second transistor which is of a second conductivity type has a control gate for receiving the input signal, a first current signal coupled to a second power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor. A third transistor is interposed between the input signal and the control electrode of the first transistor, and couples the input signal to the control electrode of the first transistor when the input signal is in the first logic state, but decouples the input signal from the control electrode of the first transistor when the input signal is in the second logic state. A force transistor is coupled to the control gate of the first transistor and the first output to prevent the first transistor from turning on when the input signal is in the second logic state. A semiconductor device using a plurality of voltage sources requires a voltage-level shifter for shifting potentials of signals to potential levels of the respective voltage sources. A voltage-level shifter in the prior art will be described below. Fig. 3 shows a circuit structure of a conventional voltage-level shifter in the prior art, and Fig. 5 shows an operation timing of the conventional voltage-level shifter. In these figures, I30 indicates an input signal, O30 indicates an output signal, VCC indicates a first voltage source, VPP indicates a second voltage source, VSS indicates a ground voltage source, 3001 indicates a voltage-level shifter, Qn3001 and Qn3002 indicate N-channel MOS transistors, Qp3001 and Qp3002 indicate P-channel MOS transistors, and N3001 indicates a node name. A circuit structure in Fig. 3 will be described below. The input signal I30 is connected to a source of the N-channel MOS transistor Qn3001 and a gate of the N-channel MOS transistor Qn3002. A gate of the N-channel MOS transistor Qn3001 is connected to the first voltage source VCC, and a source of the N-channel MOS transistor Qn3002 is connected to the ground voltage source VSS. A source of the P-channel MOS transistor Qp3001 and a source of the P-channel MOS transistor Qp3002 are connected to the second voltage source VPP. A drain of the N-channel MOS transistor Qn3001, a drain of the P-channel MOS transistor Qp3001 and a gate of the P-channel MOS transistor Qp3002 are connected together. The output signal O30 is connected to a drain of the N-channel MOS transistor Qn3002, a gate of the P-channel MOS transistor Qp3001 and a drain of the P-channel MOS transistor Qp3002. Fig. 4 shows a basic structure of the voltage-level shifter in Fig. 6. The structure in Fig.4 differs from that in Fig.3 in that an N-channel MOS transistor Qn3001' is supplied on its gate with a signal formed by inverting the input signal by an inverter INV32, has a source connected to the voltage source VSS of the input signal, and has a drain connected to the P-channel MOS transistor Qp3202. In other words, the structure in Fig. 3 eliminates the inverter circuit INV32 by employing the appropriate connection structure of the N-channel MOS element Qn3001, but performs the same operation as the basic structure in Fig. 32. Accordingly, the operation will be described below only in connection with the structure in Fig. 3. Referring to an operation timing diagram of Fig. 5, the operation will be described below. When the input signal I30 is at the "L" (Low) level, the node N3001 is at the "L" level, the N-channel MOS transistor Qn3002 is off, P-channel MOS transistor Qp3002 is on, output signal O30 is at the "H" level set by the second voltage source VPP, and the P-channel MOS transistor Qp3001 is completely off. When the input signal I30 transits from the "L" level to the "H" level, the N-channel MOS transistor Qn3002 is completely turned off, the node N3001 attains a potential (VCC-Vtn) which is lower than the potential of the first voltage source VCC by a threshold voltage (Vtn) of the N-channel MOS transistor Qn3001, and the P-channel MOS transistor Qp3002 is substantially turned off. Then, the output signal O30 attains the "L" level, the P-channel MOS transistor Qp3001 is completely turned off, the node N3001 attains the potential of the second voltage source VPP, and the p-channel MOS transistor Qp3002 is, completely turned off. Fig. 6 shows another voltage-level shifter. This voltage-level shifter amplifies both the maximum and minimum values of an amplitude of an input signal to produce a signal having a large amplitude. The voltage-level shifter includes a signal inverter circuit 50 inverting the input signal, a positive level shifter 51 which receives the input signal and an output signal of the signal inverter circuit 50 to amplify the maximum value of the amplitude of the input signal, a negative level shifter 52 which receives the input signal and the output signal of the signal inverter circuit 50 to amplify the minimum value of the amplitude of the input signal, and a positive/negative level shifter 53 which receives output of the positive and negative level shifters 51 and 52 to compose them. However, in the voltage-level shifters of the conventional structures shown in Figs. 3 and 5, when the input signal I30 transits from the "L" level to the "H" level, the N-channel MOS transistor Qn3002 is completely off, and the P-channel MOS transistor Qp3002 is substantially off as already described. In particular, if the first voltage source VCC supplies a low voltage, and/or a large potential difference exists between the first and second voltage sources VCC and VPP, the P-channel MOS transistor Qp3002 is on. Therefore, a through current flows from the second voltage source VPP to the ground voltage source VSS via the N-channel MOS transistor Qn3002 and the P-channel MOS transistor Qp3002, which causes a disadvantage that the voltage level of the output signal O30 cannot fixed at the "L" level. The conventional voltage-level shifter shown in Fig. 6 requires three level shifters and hence many transistors forming them, and is constructed to compose the shifted outputs of the positive and negative level shifters, resulting in reduction of the operation speed. SUMMARY OF THE INVENTION It is the object of the invention to provide a voltage-level shifter, in which both maximum and minimum values of an input signal are amplified by level shift at one stage, so that a speed for the level shift can be improved, and component transistors are not substantially increased in number to simplify a structure. This object is achieved by a voltage-level shifter according to claim 1. Preferred embodiments of the invention are subject matter of the dependent claims. According to the voltage-level shifter of the invention, a level shifter for amplifying the maximum amplitude value of the input signal and a level shifter for amplifying the minimum amplitude value of the same are appropriately combined together to perform amplification with level shift at a single stage. According to the invention an early cut-off circuit is disposed at one of positions between the voltage source and the source of the second MOS transistor, between the drain of the second MOS transistor and the gate of the first MOS transistor, between the voltage source and the source of the first MOS transistor, and between the drain of the first MOS transistor and the gate of the second MOS transistor. In the voltage-level shifter of the invention, when the input signal transits from the "L" level to the "H" level, the electric charge supply circuit supplies electric charges to the gate of the second MOS transistor, so that the off state of the second MOS transistor changes toward the complete off state. Therefore, even when the voltage source VCC of the input signal supplies a low voltage, and/or a large potential difference exists between the voltage source VCC of the input signal and the voltage source VPP of the level shifter, the output signal is surely fixed at the "L" level. It is possible to restrict effectively a through current flowing from the voltage source VPP of the level shifter to the ground VSS. In the voltage-level shifter of the invention having an early cut-off circuit, when the input signal transits from the "L" level to the "H" level, the early cut-off circuit is turned off at a timing earlier than the off timing of the second MOS transistor. Therefore, even if the second MOS transistor is not surely turned off when the voltage source VCC of the input signal supplies a low voltage, and/or a large potential difference exists between the voltage source VCC of the input signal and the voltage source VPP of the level shifter, the output signal is surely fixed at the "L" level. Also, it is possible to restrict effectively a through current flowing from the voltage source VPP of the level shifter to the ground VSS. Other objects, features and advantages of the invention will appear more fully from the following detailed description thereof taken in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings showing preferred embodiments of the invention: Fig. 1 shows a structure of a first embodiment of a voltage-level shifter of the invention; Fig. 2 shows a structure of a second embodiment of the voltage-level shifter of the invention; Fig. 3 shows a structure of a voltage-level shifter in the prior art; Fig. 4 shows a basic structure of the voltage-level shifter in the prior art; Fig. 5 shows an operation timing of the voltage-level shifter in the prior art; and Fig. 6 shows a structure of another conventional voltage-level shifter. DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the invention will be described below with reference to the drawings. [First and second Embodiments] A voltage-level shifter of a first embodiment of the invention, will now be described below. Fig. 1 shows a circuit structure. 2401 indicates a voltage-level shifter, I24 indicates an input signal of the voltage-level shifter 2401, O24 indicates, an output signal, VSS indicates the ground voltage source (first voltage source), VCC indicates the second voltage source, VPP indicates the third voltage source, and VBB indicates the fourth voltage source. Qn2400-Qn2402 indicate N-channel MOS transistors, Qn2403 indicates an N-channel MOS transistor (third N-channel MOS transistor), Qp2400-Qp2402 indicate P-channel MOS transistors, Qp2403 indicates a P-channel MOS transistor (third P-channel MOS transistor), and N2401 and N2402 indicate node names. The circuit structure in Fig. 1 will be described below. In the voltage-level shifter 2401, the input signal I24 is connected to the source of the N-channel MOS transistor Qn2400, the source of the P-channel MOS transistor Qp2400, the source of the P-channel MOS transistor Qp2400, the gate of the P-channel MOS transistor Qp2403 and the gate of the N-channel MOS transistor Qn2403. The node N2401 is connected to the drain of the N-channel MOS transistor Qn2400, the drain of the P-channel MOS transistor Qp2401 and the gate of the P-channel MOS transistor Qp2402, and the node N2402 is connected to the drain of the P-channel MOS transistor Qp2400, the drain of the N-channel MOS transistor Qn2401 and the gate of the N-channel MOS transistor Qn2402. The output signal O24 is connected to the gate of the P-channel MOS transistor Qp2401, the drain of the P-channel MOS transistor Qp2402, the gate of the N-channel MOS transistor Qn2401 and the drain of the N-channel MOS transistor Qn2402. The sources of the P-channel MOS transistors Qp2401 and Qp2402 are connected to the third voltage source VPP. The sources of the N-channel MOS transistors Qn2401 and Qm2403 are connected to the fourth voltage source VBB. The source of the P-channel MOS transistor Qp2402 and the drain of the P-channel MOS transistor Qp2403 are connected together, and the source of the N-channel MOS transistor Qn2402 and the drain of the N-channel MOS transistor Qn2403 are connected together. The third P-channel MOS transistor Qp2403 forms a first early cut-off circuit 251, and the third N-channel MOS transistor Qn2403 forms a second early cut-off circuit 252. The voltage level converter circuit 2401 functions to shift the input signal of the amplitudes of the ground voltage source (first voltage source) VSS and the second voltage source VCC to the amplitudes of the third voltage source VPP and the fourth voltage source VBB. Owing to provision of the P-channel MOS transistor Qp2403 and the N-channel MOS transistor Qn2403, the output signal O24 can be set rapidly to the potential of the voltage source VPP or VBB. [Fourth Embodiment] A second embodiment of a voltage-level shifter of the invention will be described below. Fig. 2 shows a circuit structure. In the figure, 2501 indicates a voltage-level shifter, I25 indicates an input signal of the voltage-level shifter 2501, O25 indicates an output signal, VCC indicates the first voltage source, VPP indicates the second voltage source, VSS indicates the ground voltage source, and VBB indicates the third voltage source. Qn2500-Qn2502 indicate N-channel MOS transistors, Qn2503 indicates an N-channel MOS transistor (third N-channel MOS transistor), Qp2500-Qp2502 indicate P-channel MOS transistors, Qp2503 indicates a P-channel MOS transistor (third P-channel MOS transistor), and N2501 and N2502 indicate node names. The circuit structure in Fig. 2 is similar to that of the first embodiment except for that the P-channel MOS transistors Qp2402 and Qp2403 are connected in series in the opposite order, and the N-channel MOS transistors Qn2402 and Qn2403 are connected in series in the opposite order. The third P-channel MOS transistor Qp2503 forms a first early cut-off circuit 261, and the third N-channel MOS transistor Qn2503 forms a second early cut-off circuit 262. The voltage level converter circuit 2501 functions similarly to the first embodiment, and specifically operates to shift the input signal of amplitudes of the ground voltage source VSS and the second voltage source VCC to the amplitude of the third voltage source VPP and the fourth voltage source VBB. Owing to provision of the P-channel MOS transistor Qp2503 and the N-channel MOS transistor Qn2503, the output signal O25 can be set rapidly to the potential of the voltage source VPP or VBB.

Claims: A voltage-level shifter for receiving an input signal (I24; I25) of a predetermined amplitude and outputting an output signal (O24; O25) of an amplitude larger than that of said input signal (I24; I25), comprising: a first N-channel MOS switch element (Qn2400; Qn2500) and a first P-channel MOS switch element (Qp2400; Qp2500); first and second N-channel MOS transistors (Qn2401; Qn2402; Qn2501; Qn2502), and first and second P-channel MOS transistors (Qp2041, Qp2402; Qp2501, Qp2502); first and second voltage sources (VSS, VCC) forming voltage sources of said input signal (I24; I25), and third and fourth voltage sources (VPP, VBB) forming voltage sources of said output signal (O24; O25), said fourth voltage source (VBB) being lower in potential than said first voltage source (VSS), and said third voltage source (VPP) being higher in potential than said second source (VCC); said first N-channel MOS switch element being connected to the gate of said second P-channel MOS transistor (Qp2402; Qp2502), and the potential of said first voltage source (VSS) being interruptibly supplied to the gate of said second P-channel MOS transistor (Qp2402; Qp2502) in accordance with the potential of said input signal (I24; I25); said first P-channel MOS switch element (Qp2400; Qp2500) being connected to the gate of said second N-channel MOS transistor (Qn2402; Qn2502), the potential of said second voltage source (VCC) being interruptibly supplied to the gate of said second N-channel MOS transistor (Qn2402; Qn2502) in accordance with the potential of said input signal (I24; I25); the gate of said first N-channel MOS switch element (Qn2400; Qn2500) being connected to said first voltage source (VSS) and the gate or said first P-channel MOS switch element (Qp2400; Qp2500) being connected to said second voltage source (VCC); the drain of said first P-channel MOS transistor (Qp2401, Qp2501) being connected to the gate of said second P-channel MOS transistor (Qp2402; Qp2502); the drain of said first N-channel MOS transistor (Qn2401, Qn2501) being connected to the gate of said second N-channel MOS transistor (Qn2402; Qn2502); the sources of said first and second P-channel MOS transistors (Qp2401, Qp2402; Qp2501, Qp2502) being connected to said third voltage source (VPP); the sources of said first and second N-channel MOS transistors (Qn2401; Qn2402; Qn2501; Qn2502) being connected to said fourth voltage source (VBB); the gate of said first P-channel MOS transistor (Qp2401, Qp2501), the drain of said second P-channel MOS transistor (Qp2402; Qp2502), the gate of said first N-channel MOS transistor (Qn2401, Qn2501) and the drain of second N-channel MOS transistor (Qn2402; Qn2502) being connected together to form a common connection; and the potential of said common connection being used as said output signal (O24; O25), characterized in that said voltage-level shifter further comprises first and second early cut-off circuits (251,252; 261,262); said first early cut-off circuit (251, 261) is disposed at one of positions between said third voltage source (VPP) of the output signal and the source of said second P-channel MOS transistor (Qp2402), between the drain of said second P-channel MOS transistor (Qp2502) and the gate of said first P-channel MOS transistor(Qp2501), between said third voltage source of said output signal and the source of said first P-channel MOS transistor, and between the drain of said first P-channel MOS transistor and the gate of said second P-channel MOS transistor, and is turned off at a timing earlier than an off timing of said second P-channel MOS transistor (Qp2402; Qp2502) when said input signal transits from the "L" level to the "H" level; and said second early cut-off circuit (252, 262) is disposed at one of positions between said fourth voltage source (VBB) of the output signal and the source of said second N-channel MOS transistor (Qn2402), between the drain of said second N-channel MOS transistor (Qn2502) and the gate of said first N-channel MOS transistor (Qn2501), between said fourth voltage source of said output signal and the source of said first N-channel MOS transistor, and between the drain of said first N-channel MOS transistor and the gate of said second N-channel MOS transistor, and is turned off at a timing earlier that an off timing of said second N-channel MOS transistor (Qn2402; Qn2502) when said input signal transits from the "L" level to the "H" level. The voltage-level shifter according to claim 1, wherein said first early cut-off circuit (251; 261) is formed of the third P-channel MOS transistor (Qp2403; Qp2503), which receives on its gate the input signal (I24, I25) of said first voltage-level shifter. The voltage-level shifter according to claim 1, wherein said second early cut-off circuit (252; 262) is formed of the third N-channel MOS transistor (Qn2403; Qn2503), which receives on its gate the input signal (I24,I25) of said voltage-level shifter.

Inventors: HIRANO HIROSHIGE, HIRANO, HIROSHIGE
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1995
Main classification: H03K19
IPC codes: H03K19