Video signal processor

Abstract: The processor is capable of executing on/off control of a copy inhibiting process and rendering extremely difficult any illegal cancellation of the copy inhibiting process by a third person. This processor comprises an obstructor (4,9,26) for obstructing proper recording of a video signal; a memory (7) for storing a specific code inputted when enabling the obstructor, and also storing a disable request code inputted in response to a request for disabling the obstructor; a judge means (16) for judging the relationship of correspondence between the value of the specific code and the value of the disable request code outputted from the memory; and a decider (17) for deciding an operation to disable the obstructor in accordance with the output of the judge means. The memory has a plurality of registers (11,14), and the bit components of at least one of the specific code and the disable request code are stored dispersedly in the plural registers of the memory.

Description: The present invention relates to a video signal processor equipped with a copy preventive function and capable of executing on/off control of such a copy preventive function. In the conventional video apparatus such as analog VTRs known heretofore, it has been customary that, in manufacture of any tape software, a disturbance signal adapted to disturb the operation of an AGC circuit in a recording section of the VTR is inserted, for the purpose of protecting the copyright, in a predetermined line during a vertical blanking interval of a video signal. Due to the existence of such a disturbance signal, if the soft tape is illegally dubbed by any third person, the dubbed tape is recorded in a non-reproducible state to consequently achieve desired protection of the copyright. U.S. Patent 4,631,603 relates to this type of copyright protection. Meanwhile, wide progress is observed of late in digitizing video apparatus with resultant remarkable improvements in the picture quality. Since video signals in such digitized video apparatus are essentially superior in quality, there is a more acute demand than in the analog video apparatus that an adequate circuit be incorporated to inhibit both digital-to-digital dubbing and digital-to-analog dubbing. Video compression technology for curtailing the quantity of data is adopted in the known digitized video apparatus currently available, particularly in digital VTRs and some apparatus designed to deal with digital television broadcasting, video-CD, CDI, video karaoke and so forth which have a signal format conforming with the MPEG (Motion Picture Experts Group) standard. Generally the digital video signal processed in such apparatus is composed merely of the data representing the actual picture alone, and there are eliminated any other signal components relative to vertical blanking, horizontal blanking and so forth not concerned directly with the picture. Normally, each such digital video apparatus incorporates a video signal processor therein to convert a digital video signal into an ordinary analog television signal having data of blanking interval. Under such circumstances, there is recently contrived an idea to execute, in the video signal processor, insertion of the aforementioned disturbance signal into a vertical blanking interval to thereby substantially inhibit the operation of recording, on any tape, the analog television signal outputted from the video apparatus. In European patent application number EP-A-0580367 which was published January 26, 1994, is disclosed a copy protection system. In EP-A-0 648 050, published on 12/4/95, or EP-A-0 667 720, published on 16/8/95 is disclosed a similar copy protection video system. Each of the above applications are owned by the assignee of the present invention and corresponding US applications are still pending and hereby incorporated by reference. Although the above-described inhibition of any illegal video recording on tape is an important social demand, it is also desired on the other hand that the video-recording inhibited state be cancelled to permit a condition where the television signal from the video apparatus is recordable on tape properly in compliance with the requirements inclusive of application and services of the video apparatus. In other words, it is also desired that on/off control of the copy inhibiting process be executable freely. As one specific method for realizing such on/off control of the copy inhibiting process in the aforementioned video signal processor, it may be considered that on/off control data of 1 bit is allocated to each register. However, in the case of employing this method, it is possible for a third person to easily find which bit in a bit stream is used for on/off control of the copy inhibiting process by monitoring and comparing the bit stream at the on-time and the one at the off-time of the copy inhibiting process by means of a logic analyzer or the like. Accordingly, there arises a problem that the copy inhibiting process is illegally cancelled by a third person. And even if a command for on/off control of the copy inhibiting process is composed of a plurality of bits, it is still possible to cancel the copy inhibiting process with facility in the same manner as the above (see e.g. EP-A-0 580 367 published on 26/04/94). It is an object of the present invention to provide a video signal processor which is capable of executing on/off control of a copy inhibiting process and rendering extremely difficult any illegal cancellation of the copy inhibiting process by a third person. According to the present invention, there is provided a video signal processor comprising: an obstructor for selectively obstructing proper recording of a video signal; a memory for storing a specific code inputted when enabling said obstructor, and also storing a disable request code inputted in response to a request for disabling said obstructor; a judging means for judging the relationship of correspondence between the value of said specific code and the value of said disable request code outputted from said memory; and a decider for deciding whether to permit an operation to disable said obstructor in accordance with the output of said judging means. In the above constitution, it is preferred that the memory has a plurality of registers, and the bit components of at least one of the specific code and the disable request code are stored dispersedly in the plural registers in the memory. It is also preferred that the obstructor has a copy inhibit signal generator means and an adder means for adding a video signal and a copy inhibit signal to each other; and the decider has first and second registers for respectively storing the specific code and the disable request code outputted from the memory and supplying such two codes to the judge means. It is further preferred that all of the adder means, the copy inhibit signal generator means, the first register, the second register and the judge means are incorporated in a unified integrated circuit. The code for disabling the copy inhibit operation is formed to be different from the code inputted when the copy inhibit operation is enabled, and the relationship of correspondence between the values of the two codes is judged to decide whether the copy inhibit operation is to be disabled or not. In the present invention, a copying operation can be inhibited immediately by turning a process on-signal to "high". And for allowing the once-inhibited copying operation to be executable, it is necessary to input a copy inhibiting process off-key code having a certain value in a predetermined relationship of correspondence to the value of a copy inhibiting process on-key code inputted at the copy inhibit time, whereby it is rendered extremely difficult for any third person to cancel the copy inhibited state. The invention will be further described by way of non-limitative example with reference to the accompanying drawings, in which:- Fig. 1 shows a configuration of a copy inhibit controller circuit employed in a preferred embodiment of the present invention; Figs. 2A and 2B are a waveform chart and a timing chart, respectively, of signals in the embodiment of Fig. 1; Fig. 3 illustrates an operation mode of a modulator circuit; Fig. 4 shows a circuit configuration of an embodiment representing the video signal processor of the present invention; and Fig. 5 shows a memory map of a register group used in the embodiment of Fig. 4. First, with reference to a circuit configuration shown in Fig. 4, a description will be given on an embodiment of the present invention which represents a video signal processor contrived for use in a video apparatus based on the MPEG standard. The video signal processor shown in this diagram is formed into a semiconductor integrated circuit of a single chip, wherein input video signals include a digital Y signal (DY) composed merely of data of an effective picture area and having a sample frequency of 13.5 MHz, and digital R-Y signal (CR) and B-Y signal (CB) composed merely of data of an effective picture area and having a sample frequency of 6.75 MHz; and output signals produced from such input video signals include analog Y signal, chroma signal (C signal) and composite colour video signal (Y+C) with blanking interval data. In this video signal processor, the following operation is performed. The input signals CR and CB are first fed to interpolators 10 and 21 respectively to be thereby converted into digital colour difference signals having a sample frequency of 13.5 MHz, and then are fed to modulators 22 and 23 respectively to be modulated by digital signals of 13.5 MHz which are supplied from a sync signal generator 8 and correspond to a subcarrier of R-Y phase and B-Y phase. The signals thus modulated are added to each other by an adder 24, which then produces a digital chroma signal of 13.5 MHz as an output. Thereafter the digital chroma signal is fed to a burst inserter 25, where a signal of 13.5 MHz corresponding to the burst signal from the sync signal generator 8 is inserted, and the output signal of the burst inserter 25 is fed to a D-A converter 28, from which an analog chroma signal is delivered. Meanwhile the input signal DY is fed first to a closed-caption signal inserter 1 where a closed caption signal is inserted in a predetermined line during a vertical blanking interval, and then a digital sync signal is further inserted by a sync signal inserter 3. Further in a copy inhibit signal adder 4, a digital copy inhibit signal corresponding to the aforementioned disturbance signal is added in accordance with requirement so as to disturb the operation of a recording section in a VTR. Thereafter the digital Y signal outputted from the adder 4 is supplied to a D-A converter 27, from which an analog Y signal is delivered. Meanwhile the digital Y signal and the chroma signal are added to each other by an adder 5, whose output is then supplied to a D-A converter 6 which delivers an analog composite colour video signal Y+C therefrom. In this circuit configuration, a register group 7 is supplied with input data from outside, inclusive of closed caption data, data 50/60 relative to television system (identification data relative to NTSC system, PAL system, etc.), parameter data relative to the format of a copy inhibit signal, and control data for switching on or off the copy inhibit operation. A closed caption signal generator 2 produces a digital closed caption signal of 13.5 MHz on the basis of the closed caption data and inserts this signal into the signal DY on a predetermined line during a vertical blanking interval in synchronism with a timing signal obtained from a sync signal generator 8. The sync signal generator 8 generates a synchronizing signal and a colour subcarrier, which are prescribed by the system based on the aforementioned data relative to the television system, in the form of digital signals of 13.5 MHz, and also produces timing signals indicative of required various time points and supplies such timing signals to both the closed caption signal generator 2 and a copy inhibit signal generator 9. The sync signal generator 8 further has an input circuit for external synchronization so that, when the video signal processor of the invention is incorporated and used in a specific video apparatus, an internal sync signal synchronized with a sync signal in such video apparatus can be obtained. The control data concerned with the copy inhibit operation and inputted to the register group 7 is supplied therethrough as a process on-signal or a key code to a copy inhibit controller 26, and when the control data is the one to turn on the copy inhibit operation, a copy inhibit signal on a predetermined line during a vertical blanking interval is outputted from the copy inhibit signal generator 9 to the adder 4 in response to the control signal outputted from the copy inhibit controller 26, whereby the copy inhibit operation is executed. Meanwhile, when the control data is the one to turn off the copy inhibit operation, the supply of the copy inhibit signal from the copy inhibit signal generator 9 to the adder 4 is interrupted to thereby cancel the copy inhibit operation. Although unshown in Fig. 4, a parameter relative to a copy inhibit signal is obtained from the register group 7 and is inputted to the copy inhibit signal generator 9, so that a copy inhibit signal of the prescribed format based on such parameter is produced in the signal generator 9. For further ensuring the copy inhibit operation with enhanced certainty, it is desired to adopt an additional circuit configuration for disturbing the burst signal inserted in the chroma signal. An arrowed dotted line shown in this diagram denotes an exemplary configuration to meet such requirement, wherein the signal generator 9 generates, in addition to the aforementioned disturbance signal, a polarity inversion signal for inverting the polarity of the burst signal every other line, so that the value of the burst signal in a burst inserter 25 is inverted every other line by this polarity inversion signal. Referring next to Fig. 5 and Figs. 1 to 3, a description will be given on the copy inhibit control data stored in the register group 7, and also on the circuit configuration and the operation of the copy inhibit controller 26. Fig. 5 shows an exemplary arrangement of the register group 7 and a composition of the copy inhibit control data stored therein. In the example of Fig. 5, the register group 7 consists of a total of seventeen 8-bit registers (i.e., register 0 to register 16). The control data is composed of a 1-bit process on-signal stored as data D0 in the register 0, an 8-bit copy inhibiting process on-key code stored as data D0 to D7 in the register 1, and an 8-bit copy inhibiting process off-key code stored as data D6 in the registers 8 to 11 and as data D5 in the registers 12 to 15. In addition to the above, the aforementioned closed caption data, system data 50/60 and parameter data relative to the copy inhibit signal are further stored in the register group 7. However, since these data are not concerned directly with the on/off control of the copy inhibit operation which is the subject of the present invention, an explanation thereof is omitted here. Now the copy inhibit on/off control action performed by the copy inhibit controller 26 will be described below with reference to the internal circuit configuration of the copy inhibit controller 26 shown in Fig. 1 and also to the timing charts of Figs. 2A and 2B. In Fig. 5, when the copy inhibit operation is to be switched on, the process on-signal inputted to the register group 7 is turned to "high", and simultaneously a predetermined 8-bit code, e.g., "AAh" (hexadecimal notation), is inputted as a process on-key code to the register group 7. Input of the data to the register group is expressed as an SI input of a copy inhibiting process on-sequence shown in Fig. 2A. Although it is expressed as serial input data in this diagram, it may be of parallel input type as well. As the above input operations are performed, the copy inhibiting process on-key code stored in the register 1 is then stored in the register 11 which is included in an on-key code processing circuit 33 incorporated in the copy inhibit controller of Fig. 1, and the process on-signal is supplied from the register group 7 to a flip-flop 17 shown in Fig. 1. Subsequently the flip-flop 17 is set by the "high" process on-signal, so that a "high" internal process on-signal is outputted from the flip-flop 17, and a copy inhibit signal is generated from the copy inhibit signal generator 9 in Fig. 5 on the basis of such output signal to thereby execute the copy inhibit operation. The copy inhibiting process on-key code stored in the register 11 is supplied via a modulator 12 to a latch circuit 13. Meanwhile, an AND output obtained from the process on-signal and a write signal is supplied to a clock input terminal of the latch circuit 13. More specifically, when both of the process on-signal and the write signal are "high", the operation of the latch circuit 13 is executed. As shown in the copy inhibiting process on-sequence of Fig. 2A, the write signal is produced on the basis of a chip select signal CS in synchronism with the input end time of the copy inhibiting process on-key code to the register group 7. The signal latched by the latch circuit 13 is used as a hidden key code when switching off the copy inhibit operation. Fig. 3 illustrates an exemplary mode of conversion performed by the modulator 12. This diagram represents an example of converting the copy inhibit on-key code "AAh" into 55h by replacing odd and even bits. However, the operation is not limited to this example alone and may be performed in any other adequate mode of conversion. Essentially, the requisite is to scramble the input signal by some means. When the copy inhibit operation is to be switched off, the process on-signal inputted to the register group 7 is turned to "low", and simultaneously the hidden key code is inputted as a copy inhibiting process off-key code (see the SI input in the copy inhibiting process off-sequence shown in Fig. 2B). As a result, the copy inhibiting process off-key code inputted to the register group 7 is written in the register 14 included in an off-key code processing circuit 34 shown in Fig. 1. Meanwhile, the AND circuit 19 is supplied with an inverted signal ("high") of the process on-signal and a write signal (see the copy inhibiting process off-sequence shown in Fig. 2B) generated in synchronism with the end time of the data input to the register 15 in the register group 7, and then the copy inhibiting process off-key code is latched by the latch circuit 15 at the time when the write signal is turned to "high". A comparator 16 shown in Fig. 1 compares the outputs of the latch circuits 13 and 15 with each other and produces a coincidence signal when a coincidence is attained between the two latch outputs. A flip-flop 17 is reset by this coincidence signal, and the internal process on-signal is turned to "low", so that generation of the copy inhibit signal in the copy inhibit signal generator 9 is brought to a halt to thereby cancel the copy inhibit operation. As obvious from the description given hereinabove, the copy inhibit operation can be immediately executed only by turning the process on-signal to "high" and inputting the same to the register group. However, when cancelling the copy inhibited state, it is necessary to input to the register group the copy inhibiting process off-key code which is obtained by modulating (scrambling) the process on-key code inputted previously for switching on the copy inhibit operation. Thus, due to the necessity of using two kinds of different codes to cancel the copy inhibit operation, it is extremely difficult for any third person to illegally cancel the copy inhibited state. The copy inhibiting process off-key code for such cancellation needs to be inputted dispersedly in the input bit stream to the register group 7, so that illegal cancellation by any third person is difficult from this point of view as well. Although in the above embodiment the copy inhibiting process off-key code is dispersed in the bit stream, it may be modified in such a manner that the copy inhibiting process on-key code is existent dispersedly, or both the on-key code and the off-key code are existent dispersedly. In the configuration of Fig. 1, the modulator circuit is incorporated in the copy inhibiting process on-key code processing circuit. However, it may be so modified that the modulator circuit is incorporated in the off-key code processing circuit. In another modification, the modulator circuit may be incorporated in each of the on-key and off-key code processing circuits. In this case, the modulation modes of the two modulator circuits need to be mutually different. Since the whole circuit configuration of the embodiment shown in Fig. 4 is formed into an integrated circuit of a single chip, it is impossible for any third person to find out the hidden key code latched internally, or to interrupt the feed path of the copy inhibit signal to the adder 4, hence realizing exact copy inhibition with certainty. And when any third person is permitted to copy by the copyright holder, desired copying is rendered immediately possible by inputting the copy inhibiting process off-key code informed by the copyright holder. Although the video signal processing circuit described above consists of a digital one, an analog processing circuit may be employed as well. In this case, the input video signal in Fig. 4 is composed of analog Y and colour difference signals of merely effective scanning period, and the circuits 1 to 5, 8 and 9, and 22 to 25 consist of analog ones. The D-A converters 6, 27, 28 and the interpolators 10 and 21 are not required. As for the register group 7 and the copy inhibit controller 26, those shown in Figs. 5 and 1 may be used respectively. The video signals (Y+C, Y, C) outputted from the video signal processor 29 are supplied to a VTR block 50. As described already, the video signal thus supplied contains a copy inhibit signal added thereto in accordance with the circumstance of the video signal, and is so controlled in the VTR block that no recording is performed if the copy inhibit signal is detected. In Fig. 6 is disclosed the video signal (Y+C) supplied to the VTR block 50. As shown, dummy sync pulses a, b, c, d and e are inserted in portions where the essential H (horizontal) sync signal is not to be existent, so as to disturb a servo circuit in the recording section of the VTR. And simultaneously, AGC (automatic gain control) pulses f, g, h, i and j are also inserted to change the level analogously. There are various modes including a pulsing mode where the pulse signal level is varied between certain levels (the signal level is changed approximately between 40% and 70% at a rate of once or twice per second), and a still mode where the level is kept still at the maximum of 129 IRE or the pedestal level of 12 IRE (the signal level is lower approximately by 33% than the normal level). In Fig. 6, k denotes a white reference fixed normally at 119 IRE. However, this reference is also changeable from 119 IRE to the pedestal level of 12 IRE by manipulation. Consequently, the recording signal level in the VTR is swung approximately in a range of 30% to 70% of a normal signal level, and even if a recording operation may be performed, the resultant pictures are disordered and therefore proper recording can be substantially prevented. Finally, regarding a concrete example of application, a brief description will be given on an exemplary case of employing the video signal processor of the present invention as a copy inhibit means in a digital television broadcast receiver. In this case, when a copyrighted program is broadcast from a broadcasting station, a process on-signal of a "high" level and a copy inhibiting process on-key code are also transmitted as incidental data in addition to digital video data. And in a receiver, the process on-signal and the copy inhibiting process on-key code included in the transmitted incidental data are inputted to the register group 7 of the video signal processor incorporated in the receiver, whereby the copy inhibit signal is inserted into the television signal. Meanwhile, when a copy free program without any copyright is broadcast, a process on-signal of a "low" level and a copy inhibiting process off-key code are transmitted to thereby halt generation of a copy inhibit signal in the video signal processor. A data input unit is so constituted previously that, if the channel being received is changed by a user during the operation of the receiver, such channel change is detected, then the copy inhibiting process off-key code is obtained automatically through computation from the copy inhibiting process on-key code and is inputted to the register group 7. In this manner, whenever any channel is changed in the receiver, the receiver is selectively switched over to a copy allowed state. And when the program being broadcast in the changed channel is a copyrighted one, the receiver is switched again to the copy inhibited state since the process on-signal is being transmitted.

Claims: A video signal processor comprising: an obstructor for selectively obstructing proper recording of a video signal; a memory (7) for storing a specific code inputted when enabling said obstructor, and also storing a disable request code inputted in response to a request for disabling said obstructor; a judging means (16) for judging the relationship of correspondence between the value of said specific code (11) and the value of said disable request code (14) outputted from said memory; and a decider for deciding whether to permit an operation to disable said obstructor in accordance with the output of said judging means. The video signal processor according to claim 1, wherein said memory has a plurality of registers (7), and the bit components of at least one of said specific code and said disable request code are stored dispersedly in said plurality of registers in said memory. The video signal processor according to claim 2, wherein said obstructor has a copy inhibit signal generator means (9) and an adder means (4) for adding the video signal and the copy inhibit signal to each other; and said decider has first and second registers (11,14) for respectively storing said specific code and said disable request code outputted from said memory; and all of said adder means, copy inhibit signal generator means, first register, second register and judge means are unified to form an integrated circuit (29). The video signal processor according to claim 3, wherein said integrated circuit includes a digital-to-analog converter circuit (27) for converting an input digital video signal into an analog video signal in such a manner that the analog video signal outputted from said converter circuit contains the copy inhibit signal combined therewith. The video signal processor according to claim 4, wherein said copy inhibit signal combined with said analog video signal has a period where the signal level thereof is approximately equal to a sync tip level in the video signal period. The video signal processor according to claim 3, wherein said analog video signal is varied to a predetermined signal level. The video signal processor according to claim 6, wherein said analog video signal is varied to a predetermined signal level cyclically at every elapsing of a predetermined time interval.

Inventors: YAMAUCHI ETSURO, YAMAUCHI, ETSURO, YAMAUCHI, ETSURO, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1995
Main classification: H04N5
IPC codes: H04N5, G11B20