Method for producing a top gate thin-film transistor

Abstract: A transparent insulation film is formed on a glass substrate. Source and drain electrodes are formed on the transparent insulation film with their ends in spaced and opposing relation. The entire face of the substrate is treated with PH 3 plasma to diffuse P atoms to form a doped surface layer. An a-Si semiconductor layer is formed on the doped surface layer so as to span a space between the source and drain electrodes with the opposite end portions of the semiconductor layer overlying those electrodes. A gate insulation film is formed on the semiconductor layer to extend all over the substrate. A gate electrode is formed of metal on the top of the gate insulation film 6 such that the opposite side edges of the gate electrode are recessed inwardly of the edges of the source and drain electrodes. An excimer laser beam is radiated against the face of the substrate with the gate electrode acting as a mask so that the laser-irradiated regions of the semiconductor layer comprise source and drain regions of n + poly-Si.

Description: FIELD OF THE INVENTION This invention relates to a method for producing a top gate a-Si thin film transistor and, more particularly, to such method involving the self alignment performed by excimer laser-annealing and thin-film transistors produced by the method. BACKGROUND OF THE INVENTION Taking a liquid crystal display panel by way of example, it has pixel electrodes arrayed in the form of a matrix formed over the entire display surface area, the pixel electrodes being connected with the drain electrodes of the respective thin-film transistors (as will be referred to as "TFT" hereinafter) formed adjacent to the pixel electrodes. The gate electrodes of the TFTs in each row are connected to a corresponding gate bus while the source electrodes of the TFTs in each column are connected to a corresponding source bus. Upon a driving voltage being applied to a selected gate bus, the TFTs connected with the gate bus are turned on, so that the turned-on TFTs are supplied with respective image signals through the source buses whereby the corresponding pixel electrodes are loaded with electric charges according to the image signals. Fig. 1 shows one example of the structure of each TFT such as a top gate TFT in such matrix. As illustrated in Fig. 1, an insulation film 2 is formed on and all over one side surface of a glass substrate 1. Formed on the insulation film 2 are a source lead 3 and a drain lead 4 having at ends source electrode 3a and drain electrode 4a in opposed parallel relation. A semiconductor layer 5 of amorphous silicon (a-Si) overlies the insulation film 2 so as to extend between and overlap with the opposed marginal edges of the source electrode 3a and the drain electrode 4a. The semiconductor layer 5 is covered by a gate insulation film 6 on which a gate electrode 7 is formed in confronting relation with the semiconductor layer 5. With the TFT as shown in Fig. 1 it is preferred that the gate electrode 7 be formed such that the opposed side edges of the gate electrode 7 and the end edges of the source and drain electrodes 3a and 4a are in registration with each other because the ON-resistance of the TFT is increased if there is any portion of the semiconductor layer 5 in the channel region 5c between the source and drain electrodes 3a and 4a to which no gate voltage is applied. It is seen in the example of Fig. 1 that the formation is such that the opposed side edges of the gate electrode 7 will overlap the marginal edges of the source and drain electrodes 3a and 4a over the distance d. While this reduces the ON-resistance of the TFT, the response characteristics of the TFT are deteriorated due to parasitic capacitances produced between the gate electrode 7 and the source electrode 3a and between the gate electrode 7 and the drain electrode 4a. One approach to overcoming these problems has been proposed by Sakoda, Matsumura et al as disclosed in the "IN-SITU CRYSTALLIZATION AND DOPING OF a-Si FILM BY MEANS OF SPIN-ON-GLASS" Mat. Res. Soc. Symp. Proc. Vol. 345, pages 59-64. 1994. This approach will be described with reference to Fig. 2. A SOG (spin-on-glass) coating 9 doped with P atoms is applied as an insulation film onto a glass substrate and baked at 450°C, followed by forming on the coating 9 an a-Si semiconductor layer 5 which is in turn covered with a gate insulation film 6. Then, a gate electrode 7 is formed on the gate insulation film 6 prior to forming source and drain leads 3 and 4, respectively. An excimer laser beam 8 is radiated as indicated by arrows 8 with the gate electrode 7 as a mask to melt those hatched portions of the semiconductor layer 5 which are not shaded by the gate electrode 7 to thereby cause P atoms to diffuse from the SOG into the melted portions of the semiconductor layer 5. Upon termination of the laser radiation, the melted portions of the semiconductor layer is allowed to cool down to form an n - poly-Si having a high electrical conductivity. Next, contact holes 6H are formed through the gate insulation film 6 on the opposite sides of the gate electrode 7 to reach the opposite marginal sides of the semiconductor layer 5, and then source and drain leads 3 and 4 are formed on the gate insulation film 6 such that one end of each of the source and drain leads 3 and 4 fills the corresponding contact hole 6H so as to contact the semiconductor layer 5. It is thus possible to reduce the parasitic capacitances and ON-resistances since the hatched n + poly-Si portions of the semiconductor layer serve as source and drain regions although the channel portion 5c of the layer remains to be a-Si. However, there are difficulties in forming the SOG film uniformly and defectlessly over the entire large display surface area, because the SOG film 9 is inferior in film thickness distribution due to its being applied to the glass substrate by spin-coating and because the film is susceptible to cracks as it is subjected to baking especially when it is relatively thick. Such cracks can lead to pixel defects, breakage of source and gate buses, TFT defects, etc. Moreover, the baking of SOG at an elevated temperature of 400°C or higher is likely to cause distortion and/or shrinkage of the glass substrate. The document K. Sera et al.: IEEE Transactions in Electron Devices 36 (1989), No. 12, pages 2868-2872, discloses an integrated active-matrix liquid-crystal display using top gate thin film transistors, namely a-Si:H thin film transistors for active elements and poly-Si thin film transistors for peripheral circuits. Both kinds of transistors are fabricated with the same process except for a laser annealing step used for the poly-Si thin film transistors only. In the known process a Cr layer and a n + doped a-Si:H layer are deposited on a glass substrate and then etched to define source/drain electrodes. An undoped a-Si:H film is then deposited and locally crystallized by excimer laser annealing for the poly-Si thin film transistors. After annealing, both the crystallized and non-crystallized a-Si:H films are plasma etched at the same time to define island patterns. Subsequently, an Sin x film is deposited as a gate insulator followed by contact etching. A Cr layer is then sputtered and used for metallization. It is an object of the invention to provide a method of manufacturing a TFT having reduced parasitic capacitance and ON-resistance without employing SOG thereby to avoid the problems described above. This object is achieved with a method as claimed in claims 1, 3, 6 and 8, respectively. The invention, its objects and advantages will be more fully explained below with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing the structure of one example of the conventional top gate TFT; Fig. 2 is a cross-sectional view showing the structure of another example of the conventional top gate TFT; Fig. 3A is a diagramatical, cross-sectional representation of the first step of the first method of this invention; Fig. 3B is a diagramatical, cross-sectional representation of the second step of the first method of this invention; Fig. 3C is a diagramatical, cross-sectional representation of the third step of the first method of this invention; Fig. 3D is a diagramatical, cross-sectional representation of the fourth step of the first method of this invention; Fig. 3E is a diagramatical, cross-sectional representation of the fifth step of the first method of this invention; Fig. 3F is a diagramatical, cross-sectional representation of the sixth step of the first method of this invention; Fig. 3G is a plan view of the TFT produced by the first method of this invention; Fig. 4A is a diagramatical, cross-sectional representation of the first step of the second method of this invention; Fig. 4B is a diagramatical, cross-sectional representation of the second step of the second method of this invention; Fig. 4C is a diagramatical, cross-sectional representation of the third step of the second method of this invention; Fig. 4D is a diagramatical, cross-sectional representation of the fourth step of the second method of this invention; Fig. 4E is a diagramatical, cross-sectional representation of the fifth step of the second method of this invention; Fig. 4F is a diagramatical, cross-sectional representation of the sixth step of the second method of this invention; Fig. 4G is a plan view of the TFT produced by the second method of this invention; Fig. 5A is a diagramatical, cross-sectional representation of the first step of the third method of this invention; Fig. 5B is a diagramatical, cross-sectional representation of the second step of the third method of this invention; Fig. 5C is a diagramatical, cross-sectional representation of the third step of the third method of this invention; Fig. 5D is a diagramatical, cross-sectional representation of the fourth step of the third method of this invention; Fig. 5E is a diagramatical, cross-sectional representation of the fifth step of the third method of this invention; Fig. 5F is a diagramatical, cross-sectional representation of the sixth step of the third method of this invention; Fig. 5G is a bottom plan view of the TFT produced by the third method of this invention; Fig. 6A is a diagramatical, cross-sectional representation of the first step of the fourth method of this invention; Fig. 6B is a diagramatical, cross-sectional representation of the second step of the fourth method of this invention; Fig. 6C is a diagramatical, cross-sectional representation of the third step of the fourth method of this invention; Fig. 6D is a diagramatical, cross-sectional representation of the fourth step of the fourth method of this invention; Fig. 6E is a diagramatical, cross-sectional representation of the fifth step of the fourth method of this invention; Fig. 6F is a diagramatical, cross-sectional representation of the sixth step of the fourth method of this invention; Fig. 6G is a bottom plan view of the TFT produced by the fourth method of this invention; Fig. 7 is a graph showing the measured results of the resistivity versus irradiation energy of XeF excimer laser annealing for the samples # 1 and #2 in which SiO 2 film was P-treated for the former and not P-treated for the latter prior to forming an a-Si layer thereon ; Fig. 8A is a plan view showing the pattern of the a-Si layer of the samples # 1 and 2; and Fig. 8B is a plan view showing the electrodes 26A and 26B formed on the terminals of the pattern shown in Fig. 8A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First embodiment: The first embodiment of this invention will now be described in the sequence of the process steps with reference to Figs. 3A-3F. The TFT produced thereby is shown in a plan view in Fig. 3G illustrating one of the TFTs of a liquid crystal display panel, which is connected to a source bus 3b, a pixel electrode 4p and a gate bus 7b. This is also the case with Figs. 4G, 5G and 6G showing the other embodiments which will be described hereinbelow. (a) First, a transparent insulation film 2 such as SiO 2 or SiN x is formed on and all over one side surface of a glass substrate 1 as illustrated in Fig. 3A. (b) Source and drain leads 3 and 4, respectively are formed of ITO (indium·tin oxide), Mo or Mo alloy on the transparent insulation film 2 (see Figs. 3B and 3G). The ends of the source and drain leads 3 and 4 comprise source and drain electrodes 3a and 4a, respectively the edges 3e and 4e of which are spaced apart from and parallel to each other. (c) The entire face of the substrate is treated with PH 3 plasma to diffuse P atoms into the surface to form a doped surface layer 12 (see Fig. 3C). (d) A generally rectangular a-Si semiconductor layer 5 is formed on the doped surface layer 12 so as to cover that portion of the transparent insulation film 2 lying between the source and drain electrodes 3a and 4a with the opposite end portions of the semiconductor layer 5 straddling on those electrodes, followed by forming a gate insulation film 6 such as SiN x or SiO 2 all over the face of the substrate (see Fig. 3D). The n + a-Si semiconductor layer 5 may be produced in an atmosphere of silane gas (SiH 4 ) having phosphine gas (PH 3 ) incorporated therein by plasma CVD process whereby highly conductive amorphous silicon which is doped with impurity atoms P and excessively enriched in electrons may be obtained. (e) A gate electrode 7 is then formed of Al or Al alloy on the top of the gate insulation film 6 (see Fig. 3E). The gate electrode 7 is formed such that it opposes the portion of the a-Si semiconductor layer 5 between the electrodes 3a and 4a with the gate insulation film 6 interposed therebetween and that the opposite side edges of the gate electrode are recessed by a distance L inwardly of the edges 3e and 4e of the electrodes 3a and 4a. The distance L is determined taking into account possible pattern alignment errors of the gate electrode 7 so that the gate electrode would not overlap with either of the source and drain electrodes 3a and 4a. (f) An excimer laser beam 8 is radiated normally against the face of the substrate with the gate electrode 7 acting as a mask for a short period of time. The a-Si semiconductor layer 5 is melted in the regions irradiated with the laser beam to take in P atoms as impurities from underlying boundary with electrodes 3a, 4a and the transparent insulation film 2. Upon termination of the laser radiation, the Si is allowed to cool down to be polycrystalized to thereby form source and drain regions 5b and 5c, respectively of n + poly-Si having a high conductivity. The portion of the semiconductor layer within the region shaded by the gate electrode 7 remains to be a-Si and serves as a channel region 5a (see Fig. 3F). It is to be noted that the reason for choosing excimer laser beam among various types of laser beams is that the excimer laser will not provide such deleterious effects as reducing the electric conductivity of the ITO of which is formed a pixel electrode, not shown, to which the drain lead 4 of the TFT is connected as well as the conductivity of the source and drain leads 3, 4 when they are made of ITO. As indicated above, in this embodiment where an excimer laser beam is radiated with the gate electrode 7 acting as a mask to form the channel region 5a, source region 5b, and drain region 5c, there is no area where the gate electrode 7 and the source and drain regions 5b, 5c overlap with each other as is the case with Fig. 2, so that the parasitic capacitances are significantly reduced. In addition, the ON-resistance between the source electrode 3a and the drain electrode 4a is also reduced since the portion of the semiconductor layer not opposing the gate electrode 7 is converted to n + poly-Si having a high conductivity. Moreover, it is possible to form a TFT without the need for heating the glass substrate 1 to such an elevated temperature as required in the SOG process; for in this embodiment P atoms are caused by the use of plasma treatment rather than SOG to diffuse into and across the exposed surfaces of the electrodes 3a, 4a and of the portion of the insulation film 2 between the electrodes so that P atoms may be caused to diffuse into and across the a-Si semiconductor layer 5 subsequently formed on those exposed surfaces by laser irradiation of the layer 5 with the gate electrode 7 as a mask. Further, the cracking problem incidental to the use of SOG may be eliminated. Second embodiment: The second embodiment of this invention will be described with reference to Figs. 4A-4F. The TFT produced thereby is shown in Fig. 4G. This embodiment is different from that of Figs. 3A-3G in that the source and drain leads 3 and 4 are formed on the same gate insulation film 6 as that on which the gate electrode 7 is formed as in Fig. 2 and are connected with the source 5b and drain 5c through contact holes 6H. (a) A transparent insulation film 2 such as SiO 2 or SiN x is formed on and all over one side surface of a glass substrate (see Fig. 4A). (b) The surface of the transparent insulation film 2 is treated with PH 3 plasma to form a doped surface layer 12 having P atoms diffused therein (see Fig. 4B). (c) A generally rectangular a-Si semiconductor layer 5 is formed on the doped surface layer 12, and on the top of which a gate insulation film 6 such as SiN x or SiO 2 is formed to extend all over the face of the substrate (see Fig. 4C). (d) A gate electrode 7 is formed of Al, Al alloy or the like on the top of the gate insulation film 6 (see Fig. 4d and 4G). The opposite side edges of the gate electrode 7 are recessed by substantially equal distances inwardly of the corresponding opposite edges of the semiconductor layer 5. (e) An excimer laser beam 8 is briefly radiated normally against the face of the substrate with the gate electrode 7 acting as a mask to thereby convert the laser irradiated portions of the semiconductor layer 5 into source and drain regions 5b and 5c, respectively composed of n + poly-Si (see Fig. 4E). The portion of the semiconductor layer shaded by the gate electrode 7 remains to be a-Si and serves as a channel region 5a. (f) Contact holes 6H, 6H are formed through the gate insulation film 6 adjacent the gate electrode 7 to reach the source region 5b and drain region 5c, respectively. Then, source and drain leads 3 and 4 are formed on the gate insulation film 6 as by sputtering of metal such that one ends of the source and drain leads fill the corresponding contact holes 6H so as to contact the source region 5b and drain region 5c, respectively (see Fig. 4F). Third embodiment: In the embodiment of Figs. 3A-3G as described above, when the gate electrode 7 is made of transparent conductive film such as ITO, such gate electrode cannot be used as a mask during the laser annealing for partial polycrystalization of the a-Si semiconductor layer 5. In that case, the present invention may be practiced by utilizing for the self-alignment process a light shield used to reduce the influences exerted by the photoconductive effects on the Si semiconductor layer 5. Such embodiment of the invention is illustrated in Figs. 5A-5F, and the TFT produced thereby is shown in a bottom plan view in Fig. 5G. As illustrated in Fig. 5A, a rectangular light shield 21 is formed of a metal layer on a glass substrate 1 before a transparent insulation film 2 is formed on and all over one side surface of the glass substrate 1 so as to cover the light shield. In the subsequent steps illustrated in Figs. 5B-5D, as in the steps of Figs. 3B-3D, source and drain leads 3 and 4, respectively are formed with one ends of the leads comprising source and drain electrodes 3a and 4a which are spaced apart from each other. The distances L between the opposite side edges of the light shield 21 and the corresponding edges of the electrodes 3a and 4a may be equal to the distances L between the opposite side edges of the gate electrode 7 and the corresponding edges of the electrodes 3a and 4a in Fig. 3E. The assembly is treated with PH 3 plasma all over the surface thereof to diffuse P atoms into the surface layer to form a doped surface layer 12 (Fig. 5C), and a-Si semiconductor layer 5 is formed on the doped surface layer 12 so as to span between the source and drain electrodes 3a and 4a, followed by forming a gate insulation film 6 (Fig. 5D). Then, as shown in Fig. 5E, a gate electrode 7 composed of transparent conductive film such as ITO is then formed on that portion of the gate insulation film 6 which is shaded by the light shield 21 by photolithography using exposure to back light 22 with the light shield 21 acting as a mask. In this way, the gate electrode 7 may be accurately patterned on the location overlying the light shield 21. Further, as shown in Fig. 5F, the annealing of the a-Si semiconductor layer 5 (diffusion of impurities P atoms into the Si layer and the subsequent polycrystalization thereof) may be carried out by radiation of laser beam from the back surface of the substrate with the light shield 21 acting as a mask. The self-alignment may thus be effected with about the same precision as in the case of Fig. 3A-3F utilizing the gate electrode as a mask. Fourth embodiment: In the embodiment of Figs. 4A-4G as described above, when the gate electrode 7 is made of ITO, it is possible, as in the case of Figs. 5A-5F, to form a light shield 21 which may be used as a mask to define the gate electrode 7 by patterning and which may also be used as a mask to effect of laser-annealing of the a-Si semiconductor layer 5. The steps of the TFT manufacturing process according to such alternative embodiment are illustrated in Figs. 6A-6F, and the TFT produced thereby is shown in a bottom plan view in Fig. 6G. These steps will be apparent from the foregoing descriptions of the embodiments of Figs. 4A-4G and of Figs. 5A-5F. Accordingly, further description is omitted for purposes of convenience. The present invention as described above with respect to the various illustrated embodiments is based on the fact that the n + poly-Si which may be produced by causing P atoms to diffuse from the plasma-treated underlying surface layer 12 into the a-Si layer through laser-annealing and cooling the a-Si layer will provide a higher electric conductivity than the a-Si. This has been confirmed by experiments to be described below. Fig. 7 shows the measured results of the resistivity versus the input energy of laser radiated for XeF excimer laser-annealing for two samples # 1 and # 2 of TFT. The sample # 1 was prepared by forming a transparent insulation film (SiO 2 ) on a glass substrate 1 and subjecting the surface layer of the insulation film to P-treatment (PH 3 plasma treatment to diffuse P atoms into the exposed surface) prior to forming an a-Si layer on the insulation film. The sample # 2 of TFT was similarly prepared, but not subjected to P-treatment prior to forming an a-Si layer. The surface of the a-Si layer of each of the samples # 1 and # 2 was subjected to XeF excimer laser-annealing, followed by forming thereon a pattern having a rectangular section 25A with a length D and a width W and two square terminal sections 25B and 25C adjoining the opposite ends of the rectangular section 25A, each of the square sections having a side longer than the width W of the rectangular section 25A, as shown in Fig. 8A. Then, Al electrodes 26A and 26B were formed on the terminal sections 25B and 25C, as shown in Fig. 8B. The current/voltage characteristics between the electrodes were measured to determine the resistance R. The resistivity ρ was calculated by the following equation: ρ = R · d · W/D where d is the film thickness of the Si layer which is 60nm and W/D = 100 µm /200 µm. It is seen in Fig. 7 that the sample # 1 exhibits a sharp decrease in resistivity whereas the sample # 2 exhibits only a gentle decrease in resistivity. It is believed that the reason is that in the sample # 1 P atoms are taken as impurities from the doped surface layer of SiO 2 into the Si layer melted by laser energy, which is then transformed to n + poly-Si upon cooling down, whereas in the sample # 2 the a-Si is melted by laser energy and gets only polycrystalized when it cools down. In Figs. 3A-3F and Figs. 4A-4F, while the transparent insulation film 2 formed on the glass substrate 1 serves to reduce unevenness in the electrical characteristics of the TFT by smoothing out any flaws and/or irregularities that may be present on the surface of the substrate, it may be omitted for reduction in the cost of production. While the self-alignment is described as being effected by the use of laser beam in the foregoing description of the invention, infrared radiation as from an infrared lamp may be used in lieu of laser beam. While it is stated in the foregoing description that PH 3 plasma treatment is used to diffuse P atoms to produce an n type TFT, B 2 H 6 plasma treatment may be equally used to diffuse B (boron) atoms to produce a p type TFT. In the latter case, the source and drain regions 5b and 5c will be p + poly-Si. As discussed hereinabove, according to this invention, P or B atoms are diffused into the surface layer by plasma treatment, and the a-Si layer formed on top of the doped layer is irradiated with a laser beam with the gate electrode 7 acting as a mask, whereby source and drain regions 5b and 5c of either n + type or p + type poly-Si may be formed adjacent to and on the opposite sides of the channel region 5c of a-Si having a width equal to that of the gate electrode. Consequently, since there are no portions of the gate electrode which overlap with the source and drain regions 5b and 5c, the parasitic capacitances between the electrodes may be greatly reduced, and so may the ON-resistance between the source and drain be reduced, as is the case with the conventional TFT as shown in Fig. 2. In addition, as no SOG is used, it is possible to produce TFTs without heating the glass substrate to an elevated temperature of 400°C or higher. Consequently, when this invention is applied to production of TFTs for large surface area LCDs, it is only required to employ substantially the same level of process temperature as in the prior art, so that the distortion and/or shrinkage of the glass substrate may be mitigated to a negligible level. Further, there is no crack problem which would occur when the SOG technique is used. When TFTS produced by the method of this invention are employed as switching elements for TFTLCD, the image-holding phenomenon is reduced owning to reduced parasitic capacitances. Moreover, the precision limits on the registration between the source or drain lead and the gate electrode may be moderated because of the self-alignment realized by this invention.

Claims: A method for producing a top gate thin-film transistor, comprising the steps of: (a) forming source and drain electrodes (3a, 4a) on one side of a glass substrate (1) with end edges (3e, 4e) of said electrodes facing each other with a space in between; (b) subjecting the entire one side of said glass substrate on which said source and drain electrodes (3a, 4a) are formed to plasma treatment to form a doped surface layer (12) having impurity atoms diffused therein; (c) forming an a-Si semiconductor layer (5) on said doped surface layer so as to span said space between said source and drain electrodes (3a, 4a) with the opposite end portions of said semiconductor layer extending onto said electrodes; (d) forming a gate insulation film (6) on said semiconductor layer to extend all over said one side of said substrate; (e) forming a gate electrode (7) of metal on top of said gate insulation film (6), said gate electrode having a length smaller than that of said space between the end edges (3e, 4e) of said source and drain electrodes (3a, 4a) and being positioned such that, in plan view, it is within said space with each of its opposite side edges displaced by a predetermined distance relative to the respective one of said end edges (3e, 4e); and (f) radiating a laser beam (8) perpendicularly against said one side of said substrate with said gate electrode (7) acting as a mask so as to diffuse said impurity atoms from said doped surface layer (12) into the portions of said semiconductor layer (5) irradiated with said laser beam and to convert these portions to poly-Si layer portions defining source and drain regions (5b, 5c), while allowing the portion of said semiconductor layer masked by said gate electrode to remain as a channel region (5a) of a-Si. The method of claim 1 wherein, step (a) includes the step of forming a transparent insulation film (2) on and all over said one side of the glass substrate (1) prior to forming said source and drain electrodes (3a, 4a). A method for producing a top gate thin-film transistor, comprising the steps of: (a) forming a light shield (21) having a predetermined width on a front side of a glass substrate (1); (b) forming a transparent insulation film (2) on said light shield to extend all over said front side of said glass substrate; (c) forming a source electrode (3a) and a drain electrode (4a) on the transparent insulation film (2) such that end edges of said electrodes face each other with a space in between that is larger than said predetermined width such that, in plan view, said light shield (21) is positioned within said space with each of its opposite side edges displaced by a predetermined distance relative to the respective one of said end edges; (d) subjecting the entire front side of said substrate to plasma treatment from the top of said source and drain electrodes (3a, 4a) to form a doped surface layer (12) having impurity atoms diffused therein; (e) forming an a-Si semiconductor layer (5) on said doped surface layer so as to span said space between said source and drain electrodes (3a, 4a) with the opposite end portions of said semiconductor layer extending onto said electrodes (3a, 4a); (f) forming a gate insulation film (6) on said semiconductor layer to extend all over said front side of said substrate; (g) exposing said substrate to light from the back side thereof with said light shield (21) acting as a mask to form a gate electrode (7) composed of transparent conductive film by photolithography on that portion of said gate insulation film (6) which is shaded by said light shield; and (h) radiating a laser beam (8) perpendicularly against the back side of said substrate with said light shield (21) acting as a mask so as to diffuse said impurity atoms from said doped surface layer (12) into the portions of said semi-conductor layer (5) irradiated with said laser beam and to transform these portions to poly-Si layer portions defining source and drain regions (5b, 5c), while allowing the portion of said semiconductor layer masked by said gate electrode to remain as a channel region (5a) of a-Si. The method of claim 1 or 3 wherein, said source and drain electrodes (3a, 4a) are formed of ITO. The method of claim 1 or 3 wherein, said source and drain electrodes (3a, 4a) are formed of metal composed of at least Mo. A method for producing a top gate thin-film transistor, comprising the steps of: (a) subjecting the entire one side of a glass substrate (1) to plasma treatment to form a doped surface layer (12) having impurity atoms diffused therein; (b) forming a generally rectangular semiconductor layer (5) of a-Si on said doped surface layer (12); (c) forming a gate insulation film (6) on said semiconductor layer (5) to extend all over said one side of said substrate; (d) forming a gate electrode (7) of metal on top of said gate insulation film (6), said gate electrode having a length smaller than that of said semiconductor layer (5) and being positioned such that, in plan view, it is within the area of said semiconductor layer with each of its opposite side edges displaced by a predetermined distance relative to the respective one of opposite end edges of said semiconductor layer; (e) radiating a laser beam (8) perpendicularly against said one side of said substrate with said gate electrode (7) acting as a mask so as to diffuse said impurity atoms from said doped surface layer (12) into the portions of said semiconductor layer irradiated with said laser beam and to transform these portions to poly-Si layer portions defining source and drain regions (5b, 5c) while allowing the portion of said semiconductor layer masked by said gate electrode to remain as a channel region (5a) of a-Si; (f) forming contact holes (6H) through said gate insulation film (6) adjacent to said opposite side edges of said gate electrode (7) to extend to said source region and drain region, respectively; and (g) forming a source electrode (3a) and a drain electrode (4a) to extend over said gate insulation film (6) such that a respective end of said source and drain electrodes fills the corresponding contact hole (6H) so as to contact said source region and drain region, respectively. The method of claim 6 wherein, step (a) includes the step of forming a transparent insulation film (2) on and all over said one side of said glass substrate (1) prior to said plasma treatment. A method for producing a top gate thin-film transistor, comprising the steps of: (a) forming a light shield (21) having a predetermined width on a front side of a glass substrate (1); (b) forming a transparent insulation film (2) on said light shield to extend all over said front side of said glass substrate; (c) subjecting the entire front side of said substrate to plasma treatment from the top of said transparent insulation film (2) to form a doped surface layer (12) having impurity atoms diffused therein; (d) forming a generally rectangular semiconductor layer (5) of a-Si on said doped surface layer, said semiconductor layer having a width larger than said predetermined width and being positioned such that, in plan view, said light shield (21) is within an intermediate portion of the width of said semiconductor layer; (e) forming a gate insulation film (6) on the said semiconductor layer (5) to extend all over said front side of said substrate; (f) exposing said substrate to light from the back side thereof with said light shield (21) acting as a mask to form a gate electrode (7) composed of a transparent conductive film by photolithography on that portion of said gate insulation film (6) which is shaded by said light shield; and (g) radiating a laser beam (8) perpendicularly against the back side of said substrate with said light shield (21) acting as a mask so as to diffuse said impurity atoms from said doped surface layer (12) into the portions of said semiconductor layer (5) irradiated with said laser beam and to transform these portions to poly-Si layer portions defining source and drain regions (5b, 5c), while allowing the portion of said semiconductor layer masked by said gate electrode to remain as a channel region (5a) of a-Si; (h) forming contact holes (6H) through said gate insulation film (6) adjacent to the opposite side edges of said gate electrode (7) to extend to said source region and drain region, respectively; and (i) forming a source electrode (3a) and a drain electrode (4a) to extend over said gate insulation film (6) such that a respective end of said source and drain electrodes fills the corresponding contact hole (6H) so as to contact said source region and drain region, respectively. The method of claim 1, 3, 8 or 10 wherein, said plasma treatment is a plasma treatment with PH 3 , said impurity atoms comprise P atoms, and said source and drain regions (5b, 5c) comprise n + type poly-Si layers. The method of claim 1, 3, 8 or 10 wherein, said plasma treatment is a plasma treatment with B 2 H 6 , said impurity atoms comprise B atoms, and said source and drain regions (5b, 5c) comprise p + type poly-Si layers. The method of claim 1, 3, 8 or 10 wherein, said laser beam comprises an excimer laser beam. The method of claim 1, 3, 8 or 10 wherein, an infrared radiation from an infrared lamp is used in lieu of said laser beam.

Inventors: NAKAGAWA TAKANOBU, SUNATA TOMIHISA, TAKEUCHI SHU, UKAI YASUHIRO, NAKAGAWA, TAKANOBU, SUNATA, TOMIHISA, TAKEUCHI, SHU, UKAI, YASUHIRO
Applicants: HOSIDEN AND PHILIPS DISPLAY CO, HOSIDEN AND PHILIPS DISPLAY CORPORATION
Application year: 1995
Main classification: H01L29
IPC codes: H01L29, H01L21