Integrated processor providing indications of internal activity to an external power management bus

Abstract: An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor depending upon the system requirements. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an outside power management unit. The power management message bus is channeled from the integrated processor at a set of package pins that are isolated from the standard external peripheral bus of the integrated processor. By providing encoded information regarding the internal events of the integrated processor, monitoring of such events by an external power management unit is possible while the number of external pins on the integrated processor are minimized.

Description: This invention relates to integrated processors and more particularly to the power management of computer systems that employ integrated processors. An ongoing developmental goal of manufacturers has been to reduce the power consumption of computer systems. Reducing power consumption typically reduces heat generation of the system, thereby increasing reliability and decreasing cost. In addition, power reduction has been particularly important in maximizing the operating life of battery-powered portable computer systems. Various techniques have been devised for reducing the power consumption of computer systems. These techniques include increasing the integration of circuitry and incorporation of improved circuitry and power management units (PMUs). One specific power reduction technique involves the capability of stopping clock signals that drive inactive circuit portions. A system employing such a technique typically includes a power management unit that detects or predicts inactive circuit portions and accordingly stops the clock signals associated with the inactive circuit portions. By turning off "unused" clock signals that drive inactive circuit portions, overall power consumption of the system is decreased. A similar technique involves the capability of reducing the frequency of clock signals that drive circuit portions during operating modes which are not time critical, and another technique involves the capability of removing power from inactive circuit portions. Power managed computer systems that employ the above-described power reduction techniques typically monitor various activities at the point of use or by snooping centralized buses. For example, an activity monitor of a power management unit may be connected directly to various control lines associated with the microprocessor and peripheral devices to determine whether certain activities are occurring. Depending upon the detected activities, the power management unit may responsively power down selected circuit portions, reduce the frequencies of selected clock signals, and/or completely stop selected clock signals. In recent years, integrated processors have been developed to replace previously discrete microprocessors and associated peripheral devices within computer systems. An integrated processor is an integrated circuit that performs the functions of both a microprocessor and various peripheral devices such as, for example, a memory controller, a DMA controller, a timer, and a bus interface unit, among other things. The introduction of integrated processors has allowed for decreases in the overall cost, size, and weight of computer systems, and has in many cases accommodated improved performance characteristics of the computer systems. A problem encountered in the design of computer systems that incorporate integrated processors is that many points of monitoring are no longer available to an external power management unit. That is, since the CPU core and various peripheral devices are contained on a common integrated circuit chip, internal connections between the CPU core and the peripheral devices may not be accessible externally. Thus, certain system activities may be undetectable in real-time. Although external package pins could be provided on the integrated processor to provide external access directly to the selected internal points of monitoring, such dedicated pins would result in a significant increase in the overall pin count of the integrated processor and would further require that the die size of the integrated processor be increased to accommodate the additional bond wire pads. As a result, a significant cost would be added to the cost of the integrated processor. The problems outlined above are in large part solved by an integrated processor including a power management message bus in accordance with the present invention. In WO-A-93 01542 there is disclosed a microprocessor with a special OEM mode of operation transparent to system programmers that can be used by an OEM system integrator to implement power management tasks, the OEM mode being accessed by a signal on a special I-O pin. The signals on the I-O pin may be provided periodically by an external timer, the signals interrupting the microprocessor and placing it in the OEM mode. In OEM mode power management code stored in an external ROM can be executed, after which the microprocessor is restored to the state where the OEM mode of operation began. In Digest of Papers, Compcon Spring '93,22 February 1993, San Francisco, CA, USA, pages 96-102, XP379034, S.C.Ellis: 'The low power Intel 486 SL microprocessor', the Intel 486 SL Microprocessor is described, including how features of this microprocessor are used to create robust, power managed portable computers which achieve a significant power reduction and performance increase. The present invention provides, according to a first aspect, an integrated processor comprising a CPU core, and internal bus coupled to the CPU core and a power management message unit coupled to the CPU core for detecting the occurrence of internal activity of the integrated processor and for providing an encoded value indicative of the internal activity to a set of external package pins for connection to an external power management message bus. In a second aspect, the present invention further provides a computer system which includes the integrated processor of the first aspect, wherein the power management message bus is coupled to the integrated processor, and a power management unit coupled to the power management message bus for managing power within the computer system at least partly according to said encoded value on said power management message bus (210). In a third aspect, the present invention provides a method for managing power within a computer system of the second aspect. The method comprises the steps of detecting an internal activity of the integrated processor, generating an encoded value indicative of the activity, providing the encoded value on the external power management message bus and receiving the encoded value at the power management unit. In one embodiment, an integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor depending upon the system power management requirements. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an external power management unit. The power management message bus is channelled from the integrated processor at a set of package pins that are isolated from the standard external peripheral bus of the integrated processor. By providing encoded information regarding the internal events of the integrated processor, monitoring of such events by an external power management unit is possible while the number of external pins on the integrated processor are minimized. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon reading the following detailed description of preferred embodiments of the invention with reference to the accompanying drawings in which: Figure 1 is a block diagram of an integrated processor including a power management message bus in accordance with the present invention. Figure 2 is a block diagram of a power management message unit incorporated within the integrated processor of Figure 1. Figure 3 is a timing diagram that illustrates a message transmit cycle executed by the power management message unit of Figure 1. Figure 4 is a diagram of an algorithmic state machine embodied within the power management message unit of Figure 1. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the present invention as defined by the appended claims. DETAILED DESCRIPTION OF THE INVENTION Referring now to Figure 1, a block diagram is shown of a computer system 200 including an integrated processor 202 coupled to a peripheral device 204 via an external bus 206. Integrated processor 202 is further coupled to a power management unit 208 via a power management message bus 210. Integrated processor 202 includes a CPU core 220 coupled to a variety of on-chip peripheral devices such as a DMA (direct memory access) controller 222, an interrupt controller 224, and a timer 226. CPU core 220 is coupled to external bus 206 via an on-chip bus interface unit 228. A clock generator 230 and a power management (PM) message unit 232 are further incorporated within integrated processor 202. The operation of clock generator 230 and power management message unit 232 will be described in further detail below. External bus 206 is illustrative of, for example, a PCI local bus. It is noted that other bus standards such as the ISA or EISA bus standards could be alternatively employed. Peripheral device 204 is illustrative of any externally connectable peripheral device such as a video controller, a disk drive, or a printer. Power management unit 208 is provided for managing and minimizing the power consumed by computer system 200. The power management unit 208 receives an encoded signal PMCODE [2:0] on power management message bus 210. The encoded signal PMCODE[2:0] is indicative of certain activities that occur within integrated processor 202, as will be described below. Power management unit 208 generates a set of clock control signals at lines 250 and a set of power control signals at lines 252. The clock control signals and the power control signals are used, respectively, to control the frequencies of selected clock signals and to control the application of power to selected circuit portions. Specifically, the clock control signals are received by clock generator 230 which generates a CPU clock signal and a system clock signal. The frequencies of the CPU clock signal and the system clock signal are dependent upon the clock control signals generated by power management unit 208. The power control signals on lines 252 are provided to control the application of power to selected circuit portions that comprise computer system 200 such as peripheral device 204. It is understood that certain power control signals may be provided to integrated processor 202 to control the application of power to various internal circuit portions of integrated processor 202. CPU core 220 is a data processing unit that implements a predetermined instruction set, such as the model 80486 microprocessor instruction set. CPU core 220 further includes a floating-point coprocessing subunit. DMA controller 222 is provided for controlling data transfers between a system memory (not shown) and various I/O peripheral devices (also not shown). Interrupt controller 224 is provided for interfacing, priortizing, and masking various interrupt signals associated with computer system 200. Timer 226 is provided for general purpose timing functions, including the generation of a timer tick interrupt signal. Finally, bus interface unit 228 is provided for orchestrating and controlling the transfer of data, address, and control signals between external bus 206 and an internal bus 260. It is noted that DMA controller 222, interrupt controller 224, timer 226, and bus interface unit 228 may be fabricated in accordance with a variety of known circuit implementations. Referring next to Figure 2, a block diagram is shown of ' the power management message unit 232. As illustrated in the figure, the power management message unit 232 includes a bus request detector 302, an NPU monitor 304, and an interrupt detector 306 coupled to a message transmit logic unit 308. The bus request detector 302 is capable of detecting a bus request signal associated with bus 260, and is capable of detecting the subsequent release of the bus 260. It is noted that the bus request signal may be generated by DMA controller 222 or by bus interface unit 228 (which asserts the bus request signal in response to an external bus master). NPU monitor 304 is coupled to CPU core 220 and is capable of detecting when the coprocessing subunit of CPU core 220 is active. Interrupt detector 306 is coupled to interrupt controller 224 and CPU core 220 and is capable of detecting the assertions of an interrupt signal INT, a non-maskable interrupt signal NMI, a system management interrupt signal SMI, and a timer tick interrupt signal. Interrupt detector 306 is further capable of detecting when a corresponding interrupt service and a corresponding timer tick service have cleared. Depending upon the system activity as detected by bus request detector 302, NPU monitor 304, and interrupt detector 306, message transmit logic unit 308 issues an encoded signal on the power management message bus 210. The encoding of the power management message bus 210 is indicated below in Table I. Internal Event Bit Definition PMCODE[2:0] Description PM Bus NOP 000 May be used as a no-operation command. NPU Active 001 The start of an NPU instruction has been detected. Bus request 010 Either an external bus master or the internal DMA controller is active. NMI occurred 011 A non-maskable interrupt was generated to the CPU. SMI Active 100 A system management mode interrupt was generated to the CPU. Interrupt Active 101 At least one interrupt service routine is in progress, excluding timer interrupts. Timer Active 110 A timer interrupt is pending or in service. All Clear 111 Indicates that any bus request or interrupt service has completed. As indicated in Table I, the power management message bus 210 is driven with a PMCODE [2:0] value of 001 when the start of a co-processor instruction has been detected by NPU monitor 304. The power management message bus 210 is driven with a PMCODE [2:0] value of 010 if either an external bus master or the internal DMA controller 222 is active, as detected by bus request detector 302. A PMCODE [2:0] value of 011 is driven on the power management message bus 210 if a non-maskable interrupt is received by CPU core 220, and a PMCODE [2:0] value of 100 is driven on power management message bus 210 if a system management mode interrupt is received by CPU core 220. A PMCODE [2:0] value of 101 is driven on the power management message bus 210 if at least one interrupt service routine is in progress, excluding timing interrupts, and a PMCODE [2:0] value of 110 is driven on the power management message bus 210 if a timer interrupt is pending or is in service. Finally, a PMCODE [2:0] value of 111 is driven on the power management message bus 210 if any bus request or interrupt service previously indicated has completed. Figure 3 is a timing diagram that illustrates a message transmit cycle executed by message transmit logic unit 308. As illustrated, when the occurrence of a monitored activity has been detected, or when the completion of a monitored activity has been detected, the PMCODE [2:0] lines of power message bus 210 are driven with a valid encoded message in accordance with values defined in Table I. A validation strobe signal labeled PMVALID# is simultaneously asserted on power management message bus 210 to indicate that a valid message is being driven on lines PMCODE [2:0]. Figure 4 is a diagram of an algorithmic state machine 500 embodied within message transmit logic unit 308. State machine 500 enters a idle state 502 upon system reset, and transitions to state 504 when a monitored activity is detected by either bus request detector 302, NPU monitor 304, or interrupt detector 306. The type of detected activity is determined during state 504. State machine 500 next transitions to state 506 during which a valid message in accordance with the encoded values of Table I is driven on lines PMCODE [2:0] of the power management message bus 210. The validation strobe PMVALID# is further asserted during state 506. If additional activity is detected during state 506, state machine 500 transitions back to state 504, determines the type of activity detected, and reverts back to state 506 and drives the power management message bus 210 accordingly. When all interrupts have been cleared and all bus requests have been deasserted, the state machine 500 enters state 508 during which an encoded "All Clear" message is broadcast on the power management message bus 210. The validation strobe PMVALID# is again asserted during state 508 when the all clear message is asserted on lines PMCODE [2:0]. Following the all clear message, state machine 500 reverts back to idle state 502. Referring back to Figure 1, power management unit 208 latches each message transmitted by power management message unit 232 upon the assertion of the validation strobe PMIVALID#. When power management unit 208 receives a new message, it controls the clock control signals at lines 250 and the power control signals 252 in accordance with a predetermined power management algorithm. For example, when the all clear message is received by power management unit 208 from power management message unit 232, the power management unit 208 may drive the clock control signals at lines 250 such that the frequencies of the CPU clock signal and the system clock signal are reduced or such that the CPU clock signal and/or the system clock signal is stopped.Power management unit 208 may similarly drive the power control signals at lines 252 to remove, power from selected peripheral devices and/or subunits of computer system 200. Depending upon subsequent system activity that may be reported on power management message bus 210, the power management unit 208 controls the clock control signals such that the frequencies of the CPU clock signal and the system clock signal are raised, and such that the power control signals are driven to reapply power to selected peripheral devices and subunits of computer system 200. It is further noted that while the power management message unit 232 of Figure 1 detects the specific activities as indicated within Table I, other internal system activities may be alternatively or additionally detected and indicated via power management message bus 210. For example, the power management message unit may be configured with a decoder to snoop the internal bus 260 to detect the execution of selected bus cycles. In addition, while the power management unit 208 of Figure 1 controls the generation of various clock signals within computer system 200 as well as the application of power to various peripheral devices and subunits of computer system 200, the power management unit 208 may be configured to control only selected clock signals of computer system 200 or to control only the application of power to various peripheral devices. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims: An integrated processor (202) comprising: a CPU core (220); an internal bus (260) coupled to said CPU core; and a power management message unit (232) coupled to said CPU core for detecting the occurrence of internal activity of the integrated processor and for providing an encoded value indicative of said internal activity to a set of external package pins for connection to an external power management message bus (210). An integrated processor as claimed in claim 1 further comprising an on-chip peripheral device (222, 224, 226, 228, 230) coupled to the said internal bus. An integrated processor as claimed in Claim 1 wherein said power management message unit (232) includes an interrupt detector (306) for detecting the assertion of an interrupt signal. An integrated processor as claimed in Claim 1 wherein said power management message unit includes a bus request detector (302) for detecting the assertion of a bus request signal. An integrated processor as claimed in Claim 1 further comprising a DMA controller (222) coupled to said CPU core. An integrated processor as claimed in Claim 4 further comprising a DMA controller (222) coupled to said CPU core, wherein said DMA controller is capable of generating said bus request signal. An integrated processor as claimed in Claim 1 wherein said power management message unit is further capable of detecting co-processor activity within said CPU core. An integrated processor as claimed in Claim 1 further comprising a bus interface unit (228) for interfacing said internal bus to an external peripheral bus (206). An integrated processor as claimed in Claim 8 wherein said external peripheral bus is isolated from said power management message bus. An integrated processor as claimed in Claim 1 wherein said power management message unit asserts a validation strobe when said encoded value is provided on said power management message bus. An integrated processor as claimed in Claim 8 wherein said power management message bus is asynchronous with respect to said external peripheral bus. An integrated processor as claimed in Claim 3 wherein said power management message unit includes a bus request detector for detecting the assertion of a bus request signal, wherein said power management message unit provides a first encoded value on said power management message bus in response to the assertion of said interrupt signal, and wherein said power management message unit provides a second encoded value on said power management message bus in response to the assertion of said bus request signal. An integrated processor as claimed in Claim 12 wherein said power management message unit is further capable of detecting when an interrupt service has completed, and wherein said power management message unit provides a third encoded value on said power management message bus in response to the completion of said interrupt service. A computer system (200) comprising: the integrated processor of claim 1; said power management message bus (210) coupled to the integrated processor; a power management unit (208) coupled to the said power management message bus (210) for managing power within the said computer system (200) at least partly according to said encoded value on said power management message bus (210). A computer system as claimed in claim 14 wherein said power management message unit includes an interrupt detector for detecting the assertion of an interrupt signal. A computer system as claimed in Claim 15 wherein said power management message unit further includes a bus request detector for detecting the assertion of a bus request signal. A computer system as claimed in Claim 16 wherein said integrated processor further includes a DMA controller coupled to said CPU core, wherein said DMA controller is capable of generating said bus request signal. A computer system as claimed in Claim 17 wherein said power management message unit is further capable of detecting co-processor activity within said CPU core. A method of managing power within the computer system of claim 14, the method comprising the steps of: detecting an internal activity of the said integrated processor (202); generating an encoded value indicative of the said activity; providing the said encoded value on the external power management message bus (210); and receiving the said encoded value at the said power management unit (208). A method as claimed in claim 19, wherein the integrated processor includes at least one on-chip peripheral device. A method as claimed in claims 19 and 20 comprising the further step of generating a validation strobe simultaneously with said step of providing said encoded value on said external power management bus. A method as claimed in claims 19 and 20 wherein said step of detecting an internal activity of said integrated processor includes the step of detecting an assertion of an interrupt signal.

Inventors: GEPHARDT DOUGLAS D, MACDONALD JAMES R, GEPHARDT, DOUGLAS D., MACDONALD, JAMES R.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES INC.
Application year: 1995
Main classification: G06F1
IPC codes: G06F1