Output control circuit for a voltage regulator

Abstract: A depletion mode pass transistor is used as the output transistor. A PMOS transistor on/off switch is connected between the source of the pass transistor and the output terminal of the regulator to effectively turn the regulator on or off without shutting down the depletion mode pass transistor. This avoids the need to form a negative supply voltage generator.

Description: This invention relates to a output control circuit for a voltage regulator. Fig. 1 is a block diagram illustrating the general configuration of a linear-type voltage regulator of the prior art whose output voltage V out is regulated using a feedback loop. A battery or other unregulated power supply voltage V+ is applied to an input terminal of an output amplifier 10. Output amplifier 10 includes a pass transistor connected between V+ and V out . A resistor-divided output voltage V out is fed back into an error amplifier 2, and this feedback voltage is compared to a reference voltage generated by a reference voltage generator 14. The error amplifier 2 generates an error signal which controls the pass transistor in output amplifier 10 to have a conductivity such that the divided V out voltage matches the reference voltage despite changes in load current.. Output capacitor C is used for both filtering V out and for frequency compensation to improve the stability of the circuit when transients are created at the V out terminal. Such transients may be created by varying load conditions. As would be understood by those skilled in the art, the proper selection of the output capacitor C value is dependent upon the impedance of the pass transistor in output amplifier 10. The impedance of the pass transistor (and thus the output impedance of the regulator) changes as the load current varies. This impedance change can occur even before the feedback circuit reacts to the changed load condition. For example, if the pass transistor were an MOS device having its source coupled to V out or if the pass transistor were a bipolar transistor having its emitter coupled to V out , a sudden drop in load resistance would reduce the source or emitter voltage and instantaneously increase the V GS or V BE of the pass transistor. This, in turn, decreases the output impedance of the regulator. In the shown type of low dropout voltage regulators, a high voltage depletion mode NMOS device is used as the pass element in output amplifier 10. If it were desired to turn the voltage regulator off, the gate of the depletion mode NMOS device must then be driven to a voltage below its source, which usually means that a negative voltage supply is required to pull the gate below ground. Creating a negative voltage source requires additional complexity and silicon real estate. What is needed is a circuit and method to turn off a voltage regulator having a depletion mode pass transistor without requiring the creation of a negative voltage supply. In the preferred embodiment of the invention, a depletion mode pass transistor is used as the output transistor. In prior circuits, a negative voltage supply was required to pull the gate of the depletion mode device below the source voltage in order to completely turn off the pass transistor. In the preferred circuit, a PMOS transistor on/off switch is connected between the source of the pass transistor and the output terminal of the regulator to effectively turn the regulator on or off without shutting down the depletion mode pass transistor. This avoids the need to form a negative supply voltage generator. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a prior art voltage generator. Fig. 2 illustrates one embodiment of the voltage generator in accordance with the present invention. Fig. 3 is a schematic diagram of the error amplifier, output amplifier circuitry, current detection circuitry, and current feedback circuitry shown in Fig. 2 Fig. 4 is a simplified schematic diagram of the feedback portions of Fig. 3. Fig. 5 is a Bode plot of the output amplifier stage illustrating its improved performance. Fig. 6 illustrates the voltage regulator's response to output current steps. Fig. 2 illustrates a schematic block diagram of a voltage regulator 16 incorporating the inventive circuits. Some portions of the voltage regulator will not be described herein in detail. In Fig. 2, reference voltage generator 20 provides a stable reference voltage despite changes in temperature. This reference voltage, which is about 1.25 volts in one embodiment, is compared by an error amplifier 22 to a voltage, taken at the junction of resistors R1 and R2, related to the output voltage V out . The resistor divider is not needed if a gain stage is used at the output of the reference voltage generator to output the desired V out voltage. The error signal is applied to an output amplifier 24 for controlling a pass transistor to supply more or less current to a load (R L ) to keep V out constant despite changes in R L . Output control circuit 30 controls the output amplifier 24 to be on or off and provides a current limiting function. A current detector 32 detects an output current of the pass transistor and applies a feedback signal, related to the current, to the elements controlling the pass transistor. The current detector 32 and feedback circuitry operate rapidly to cause the impedance of the pass transistor to not substantially change with rapid fluctuations of the load R L . A bias circuit 28 provides various bias voltages to the circuitry in blocks 20, 22, 24, and 32. Capacitor C provides filtering and frequency compensation to improve the stability of the regulator in response to transient conditions at V out . The feedback provided by the current detector 32 to stabilize the output impedance of the regulator enables the designer to select the value of capacitor C based primarily upon the filtering requirements rather than on frequency compensation requirements. Fig. 3 is a schematic diagram of error amplifier 22, output amplifier 24, and current detector 32, along with some biasing and output control circuitry, in accordance with the preferred embodiment voltage regulator. NMOS transistor MD2 is a high voltage/high current depletion mode transistor, acting as a pass transistor, having a drain connected to a positive power supply terminal VPLUS. VPLUS may be an automobile battery or another voltage source generating up to 60 volts. The gate of transistor MD2 is controlled to supply a current through PMOS transistor MP9 such that the output voltage at the output VREG of the voltage regulator remains at 5 volts despite the changing current needs of a load (not shown) connected between VREG and ground. Transistor MP9 acts as an on/off switch and receives either a high signal or a low signal at its gate, via terminal PG, for connecting the source of transistor MD2 to the VREG terminal. By controlling the on/off state of PMOS transistor MP9, the output voltage at VREG is turned on or off without having to turn off depletion mode transistor MD2. This avoids the need for a negative voltage supply to apply a negative voltage to the gate of transistor MD2 to turn off transistor MD2. This results in a considerable savings of silicon area and complexity. PMOS transistor MP9 may be a 5 volt device. Other types of suitable switches may be substituted for transistor MP9. A 5 volt reference voltage, generated by an amplified output of a band gap reference generator (to be described later), is applied to input terminal V5 and applied to the input of bipolar transistor QN1. The voltage drops across bipolar transistors QN1, QP1, QP2, and QN2 are maintained such that the output voltage at VREG is the same voltage as applied to pin V5. The V GS of pass transistor MD2 is automatically adjusted up or down to cause the voltage drops across QN1 and QP1 to equal the voltage drops across QN2 and QP2. This then balances the transistor bridge and causes the voltage at VREG to be at 5 volts. Depending on the matching of voltage drops across the transistor bridge, the gate voltage of transistor MD2 is either pulled down by transistor QN5 or pulled up by transistor QN4 controlling MOS transistors MP4, MP5, and MP8 to pull up the gate of transistor MD2 to the source voltage of NMOS transistor MD1. Other types of push/pull stages may also be used. Using transistor MD1 to power the gate drive circuitry for transistor MD2 allows the gate of transistor MD2 to be raised nearly 1 volt above the source of transistor MD2 at high currents, providing an increased maximum output current for the regulator. A fixed bias current is applied to input terminals C, D, and D2. The VN terminal is connected to ground. The PB terminal is connected to a bias voltage to cause transistors MN1, MP3, and MP7 to properly bias transistor MN2 and the transistor bridge. Current flowing into terminal ZOUT can be used for adjusting the gain of the error amplifier. Compensating the output stage is accomplished with two capacitors, C1 and C2. The main gain roll-off capacitor is C2. The dominant parasitic pole in the circuit is generated by the gate of the pass transistor MD2 and the output impedance of the push-pull amplifier. If the pole due to a load capacitor connected to VREG occurs while the gain of the circuit is greater than one, oscillations will occur. Capacitor C1 is introduced as a zero in the circuit to cancel out the dominant parasitic pole. The effect of C1 is to lower the output impedance of the regulator. Capacitor C1 is a pole cancellation capacitor to extend the operating range to lower values of output capacitance. Typically, the poles of the load capacitance will be on the order of hundreds of kilohertz. The compensation capacitance C2 is placed in the current loop of the amplifier. Changes in output current are slowed by the operation of this capacitor C2. Further, a zero is introduced into this circuit by the operation of resistors R1 and R2. A portion of the circuit of Fig. 3 which is used to improve the stability of the regulator by offsetting changes in output impedance due to transients at the VREG terminal will now be described. The feedback loop which compares the reference voltage at terminal V5 to the voltage at VREG and adjusts the gate voltage of transistor MD2 is relatively slow and does not react to high frequency transients at the VREG terminal. These transients change the conductivity of transistor MD2, making compensation difficult. Without proper compensation, the regulator may be unstable in response to these transients. In order to maintain the output impedance of the voltage regulator relatively constant despite transients on VREG, a fast feedback loop is provided primarily consisting of depletion mode transistor MD1, PMOS transistors MP6 and MP2, resistors R1 and R2, capacitor C2, and bipolar transistor QN5. This feedback loop reacts to the current through transistor MD2 rather than voltage fluctuations at the VREG terminal. Since MOS devices are square law devices, if the threshold voltage of pass transistor MD2 is subtracted from its V GS voltage, this resulting voltage is proportional to the square root of the current through transistor MD2. The difference between nodes VP and P in Fig. 3 represents this voltage. A PMOS threshold is added by the operation of transistor MP6. The V GS of PMOS transistor MP2 generates a current proportional to the current through pass transistor MD2, and a voltage proportional to this current is generated across R1. This voltage at resistor R1 is then used to generate the compensation gate voltage for pass transistor MD2. This scheme allows the amplifier to anticipate overshoot in the load by slowing changes in current under conditions which generate high rates of change of current such as step loads and startups. A simplified version of this fast feedback loop portion of Fig. 3 is shown in Fig. 4. The current source I1 connected to the source of transistor MD1 is formed in part by PMOS transistors MP3 and MP7 in conjunction with NMOS transistor MN1 in Fig. 3. A second current source I2 shown in Fig. 4 is provided by a bias circuit (not shown) connected to terminal PB in Fig. 3. Transistors MD1 and MD2 are similar depletion mode NMOS transistors except that MD1 is much smaller than MD2 and hence carries a low current and provides a low voltage drop. Transistors MD1 and MD2 have their gates connected together so that the current through transistor MD1 somewhat tracks the current through MD2. The voltage at the source of transistor MD1 reflects the gate voltage of transistor MD2 minus the threshold voltage of transistor MD2 (the V TH of MD1 and MD2 are equal) at a given instant. This V G -V TH voltage is applied at the source of transistor MP2. The source of transistor MD2 is connected to the source of transistor MP6. The gate and drain of MP6 are connected together so that the voltage drop (i.e., a threshold voltage) across transistor MP6 is constant. The voltage at the drain of transistor MP6 is coupled to the gate of transistor MP2 so that the V GS of transistor MP2 is related to the V GS -V TH of transistor MD2. Thus, the current through transistor MP2 will track the current through transistor MD2. The current through transistor MP2 is reflected as a voltage drop across resistor R1, where an increased current through MP2 (or MD2) raises the voltage at resistor R1. This voltage is coupled to the base of NPN bipolar transistor QN5, via resistor R2 and capacitor C2. Transistor QN5 is coupled between the common gate of MD1 and MD2 and ground such that an increased voltage at resistor R1 lowers the gate voltage of transistor MD2. This, in turn, quickly lowers the current through transistor MD2 in response to an increase in load current. Conversely, a drop in load current causes the gate voltage of transistor MD2 to be raised accordingly. As an example, if the load connected to the VREG terminal attempts to draw more current, the source of transistor MD2 will be pulled down. This would normally raise the V GS of MD2 and thus rapidly decrease the output impedance of the voltage regulator. In response, transistor MP2, in conjunction with resistor R1 and transistor QN5, pulls down the gate of transistor MD2 so that the resulting V GS of MD2 will remain relatively constant even in light of this fast transient on the VREG terminal. The voltage at resistor R1 is also coupled to the emitter of transistor QN4, comprising part of the gate pull-up circuitry. If the voltage at resistor R1 were to decrease, then the gate of transistor MD2 would be pulled up to achieve a constant V GS . Transistor MP1 in Fig. 3 provides a capacitance across transistor MP2 to improve stability. Diode D1 conducts when the voltage at terminal VP exceeds a certain level in order to limit voltage excursions on VREG. This conduction of diode D1 turns on transistor QN5 to pull the gate of transistor MD2 low. As seen, this fast feedback circuit provides current feedback compensation rather than output voltage compensation in response to a transient on the VREG terminal. This unique compensation scheme incorporating the fast feedback loop makes the output stage stable into almost any capacitive or resistive load by design from 0.1 microfarads to 100 microfarads and nearly independent of ESR (Equivalent Series Resistance of the capacitor). With a 10 microfarad output capacitance, there is an 89° phase margin and nearly two decades of gain margin. This makes the circuit useful over almost any reasonable capacitive load. In addition, the push-pull amplifier design makes the circuit very responsive to steps in the load current. It can be seen from the Bode plot of Fig. 5 for the amplifier that the output has three decades of gain margin and 90 degrees of phase margin. This allows the regulator to be stable into a wide variation of capacitive loads. The low output impedance insures that step changes will not perturb the output voltage severely and the current compensation acts to limit overshoot. The output stage was designed to be stable into capacitive loads from 0.1 µf to 100 µf and to be very inventive to capacitor ESR. To be stable, the amplifier requires a few tens of milliohms of ESR. The zero in the output impedance makes the circuit very responsive to current steps. Fig. 6 is a plot of the output voltage as current is ramped exponentially from near zero to 500 ma with positive going 100 ma current steps. The load is a "worst case" type load with low capacitance and high ESR. The output capacitor is 2 µF and the ESR is 10 ohms. The ESR resistor should produce 1 volt steps. It is apparent that the excursions are small and fast due to the low output impedance and high frequency response of the output stage. The nominal output voltage steps is only 50 mV positive and -250 mV negative on the short spikes due to the ESR of the capacitor. A small parallel capacitor with low ESR should remove the fast spikes. It is important here to note the stability and lack of oscillation.

Claims: An output control circuit for a linear voltage regulator comprising: a depletion mode MOS transistor (MD2) having a drain, a source, and a gate, said drain being electrically coupled to a first supply voltage (Vplus), said gate being coupled to a signal for controlling the current flow between said source and drain, so said depletion mode MOS transistor being controlled by said signal to supply a current to a load at a regulated voltage; characterized by : a transistor switch (MP9) having a first current handling terminal connected to said source of said first transistor (MD2) and a second current handling terminal connected to an output terminal (VREG) of said voltage regulator, said transistor switch having a control terminal coupled to receive a control signal (PG); and a controller (30) connected to said control terminal of said transistor switch (MP9) for turning said switch on and off so that said regulated voltage may be selectively applied to said output terminal (VREG) of said voltage regulator without turning off said depletion mode transistor (MD2). The circuit of Claim 1, wherein said transistor switch (MP9) is a PMOS transistor. The circuit of any of the Claims 1 or 2, further comprising a feedback circuit (22) for receiving a voltage proportional to said regulated voltage and providing an error signal for controlling the conductivity of said depletion mode transistor (MD2) to adjust said regulated voltage. The circuit of any of the Claims 1-3, wherein said depletion mode MOS transistor (MD2) is a pass transistor. The circuit of any of the Claims 1-4, wherein said depletion mode MOS transistor (MD2) is an NMOS transistor. A method for selectively applying an output voltage to an output terminal (VREG) of a voltage regulator having a depletion mode pass transistor (MD2) connected between said output terminal and a voltage source, said pass transistor for conducting current to a load connected to said output terminal, said method comprising the steps of: controlling a transistor switch (MP9) connected between a current output terminal of said pass transistor (MD2) and said output terminal (VREG) of said voltage regulator to selectively apply said current output of said pass transistor (MD2) to said output terminal (VREG) of said voltage regulator as said switch (MP9) is turned on and off, such that said output current is decoupled from said output terminal (VREG) without turning off said depletion mode pass transistor (MD2). The method of Claim 6, wherein said switch(MP9) is a PMOS transistor and said pass transistor (MD2) is an NMOS transistor.

Inventors: FRANCK STEVEN J, WRATHALL ROBERT S, FRANCK, STEVEN J., WRATHALL, ROBERT S.
Applicants: SILICONIX INC, SILICONIX INCORPORATED
Application year: 1995
Main classification: G05F3
IPC codes: G05F3