Semiconductor memory device incorporating redundancy memory cells

Abstract: In a semiconductor memory device including a plurality of memory cell clocks (1-1∼1-4) each having a mormal memory cell array and first and second redundancy memory cell rows (or columns) (1-1a, 1-1b, ···), one first redundancy row (or column) selecting circuit (5-1a, 5-2a, ···) is provided for each of the memory cell blocks to access the first redundancy memory cell row (or column) upon receipt of a respective memory cell block selection signal, and one second redundancy row (or column) selecting circuit (5-1b', 5-1b', ···) is provided for at least two of the memory cell blocks to access the second redundancy memory cell row (or column) upon receipt of a respective memory cell block selection signal.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device and, more particularly, to an improve ment of a redundancy decoder portion thereof. Description of the Related Art In a prior art semiconductor memory device including a plurality of memory cell blocks, two redundancy memory cell rows (or columns) are incorporated into each of the memory cell blocks. In this case, two redundancy decoders are provided for each of the memory cell blocks. In other words, the number of redundancy decoders is twice that of memory cell blocks. Therefore, when two defectice memory cells are found in one of the memory cell blocks, addresses (hereinafter, referred to as defective addresses) of the cells are written into the redundancy decoders of the same memory cell block by laser trimming or the like. As a result, when one of the defective addresses is received by its corresponding redundancy decoder, the redundancy decoder deactivates the normal memory cells of the same memory cell block and in its place, selects the corresponding redundancy memory cell row (or column). Thus, the defective memory cell is replaced by a redundancy memory cell, and alleviated. This will be explained later in detail. In the above-described prior art semiconductor memory device, however, since the number of redundancy decoders is too large, the integration of the device is low. Document US-A- 5 265 055 provides a semiconductor memo having redundancy technique which can improve the manufacturing yields of the memory without requiring a large chip area. This document does not disclose nor does it suggest an arrangement composed of a first and second redundancy selecting means as proposed in the present application. SUMMARY OF THE INVENTION It is an object of the present invention to improve the integration of a semiconductor memory device including memory cell blocks each having a normal memory cell array and two redundancy cell rows (or columns), without reducing the manufacturing yield. According to the present invention, in a semiconductor memory device including a plurality of memory cell blocks each having a normal memory cell array and first and second redundancy memory cell rows (or columns), one first redundancy row (or column) selecting circuit is provided for each of the memory cell blocks to access the first redundancy memory cell row (or column) upon receipt of a respective memory cell block selection signal, and one second redundancy row (or column) selecting circuit is provided for at least two of the memory cell blocks to access the second redundancy memory cell row (or column) upon receipt of a respective memory cell block selection signal. Thus, the mumber of redundancy row (or column) selecting circuits is reduced, to thereby raise the integration of the device. This is solved in advantageous manner basically by applying the features laid down in the independent claims. Further enhancements are provided by the subclaims. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: Fig. 1 is a block circuit diagram illustrating a prior art semiconductor memory device incorporating redundancy memory cells; Fig. 2 is a circuit diagram of the redundancy column decoders of Fig. 1; Fig. 3 is a block circuit diagram illustrating another prior art semiconductor memory device incorporating redundancy memory cells; Fig. 4 is a circuit diagram of the redundancy row decoders of Fig. 3; Fig. 5 is a diagram explaining the area of the redundancy decoder of Figs. 1 and 3; Fig. 6 is a block circuit diagram illustrating a first embodiment of the semiconductor memory device incorporating redundancy memory cells according to the present invention; Fig. 7 is a circuit diagram of the redundancy column decoders of Fig. 6; Fig. 8 is a circuit diagram illustrating a modification of Fig. 7; Fig. 9 is a block circuit diagram illustrating a second embodiment of the semiconductor memory device incorporating redundancy memory cells according to the present invention; Fig. 10 is a circuit diagram of the redundancy column decoders of Fig. 9; Fig. 11 is a circuit diagram illustrating a modification of the circuit of Fig. 10; Fig. 12 is a block circuit diagram illustrating a third embodiment of the semiconductor memory device incorporating redundancy memory cells according to the present invention; Fig. 13 is a block circuit diagram illustrating a fourth embodiment of the semiconductor memory device incorporating redundancy memory cells according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before the description of the preferred embodiments, prior art semiconductor memory devices incorporating redundancy memory cells will be explained with reference to Figs. 1 through 4. In Fig. 1, which illustrates a prior art semiconductor memory device, reference numerals 1-1, 1-2, 1-3 and 1-4 designate memory cell blocks each including a normal memory cell array as well as two redundancy memory cell columns such as 1-1a 1-1b. X decoders (row decoders) 2-1, 2-2, 2-3 and 2-4 are provided for the memory cell blocks 1-1, 1-2 1-3 and 1-4, respectively. Also, Y decoders (column decoders) 3-1, 3-2, 3-3 and 3-4 including Y switch circuits and sense amplifiers 4-1, 4-2, 4-3 and 4-4 are provided for the memory cell blocks 1-1, 1-2, 1-3 and 1-4, respectively. The X decoders 2-1, 2-2, 2-3 and 2-4 receive an m-bit X address signal AD X , and the Y decoders 3-1, 3-2, 3-3 and 3-4 recieve an n-bit Y address signal AD Y . The redundancy memory cell columns 1-1a, 1-1b, 1-2a, 1-2b, 1-3a, 1-3b, 1-4a and 1-4b are selected by redundancy Y decoders (redundancy column decoders) 5-1a, 5-1b, 5-2a, 5-2b, 5-3a, 5-3b, 5-4a and 5-4b, respectively, not by the Y decoders 3-1, 3-2, 3-3 and 3-4. The X decoder 2-1, the Y decoder 3-1, and the redundancy Y decoders 5-1a and 5-1b are activated by a memory cell block selection signal BK1. The X decoder 2-2, the Y decoder 3-2, and the redundancy Y decoders 5-2a and 5-2b are activated by a memory cell block selection signal BK2. The X decoder 2-3, the Y decoder 3-3, and the redundancy Y decoders 5-3a and 5-3b are activated by a memory cell block selection signal BK3. The X decoder 2-4, the Y decoder 3-4, anti the redundancy Y decoders 5-4a and 5-4b are activated by a memory cell block selection signal BK4. Also, the redundancy Y decoders 5-1a, 5-1b, 5-2a, 5-2b, 5-3a, 5-3b, 5-4a and 5-4b are precharged by a clock signal  R . Further, when the redundancy Y decoder such as 5-1a selects the redundancy memory cell column 1-1a, the Y decoder 3-1 is disabled by a normal memory cell array disabling signal  d which is shown not in Fig. 1 but is shown in Fig. 2. In Fig. 2, which is a detailed circuit diagram of the redundancy Y decoders 5-1a and 5-1b of Fig. 1, each of the redundancy Y decoders 5-1a and 5-1b is comprised of a fuse-type NOR-type read-only memory (PROM). For example, the redundancy Y decoder 5-1a includes a precharging P-channel MOS transistor Q 10 , fuses F 11 , F 11 ', F 12 , F 12 ',···, F 1 n , F 1 n ', and N-channel MOS transistors Q 11 , Q 11 ', Q 12 , Q 12 ',···, Q 1 n , Q 1 n ', and a NAND circuit G 11 . In this case, the transistors Q 11 , Q 11 ', Q 12 , Q 12 ',···, Q 1 n , Q 1 n ' are controlled by Y address signals Y 1 , Y 1 , Y 2 , Y 2 ,···, Y n , Y n , respectively. Similarly, the redundancy Y decoder 5-1b includes a precharging P-channel MOS transistor Q 20 , fuses F 21 , F 21 ', F 22 , F 22 ', ···, F 1 n , F 1 n ', and N-channel MOS transistors Q 21 , Q 21 ', Q 22 , Q 22 ',···, Q 2 n , Q 2 n ', and a NAND circuit G 12 . In this case, the transistors Q 21 , Q 21 ', Q 22 , Q 22 ',···, Q 2 n , Q 2 n ' are controlled by the Y address signals Y 1 , Y 1 , Y 2 , Y 2 ,···, Y n , Y n , respectively. Also, a NOR circuit 6-1 is connected to the redundancy Y decoders 5-1a and 5-1b. As a result, when the redundancy Y decoder 5-1a or 5-1b generates a redundancy memory cell column selection signal RCS 11 or RCS 12 to select the redundancy memory cell column 1-1a or 1-1b, the NOR circuit 6-1 disables the Y decoder 3-1. First, when a defective memory cell is found in the memory cell block 1-1, the fuses F 11 , F 11 ', F 12 , F 12 ', ···, F 1 n , F 1 n ' are trimmed by a laser, so that a defective column address indicating this defective memory cell is written into the redundancy Y decoder 5-1a. Further, when another defective memory cell is found in the memory cell block 1-1, the fuses F 21 , F 21 ', F 22 , F 22 ', ···, F 2 n , F 2 n ' are trimmed by a laser, so that another defective column address indicating this second defective memory cell is written into the redundancy Y decoder 5-1b. When the Y address signal AD Y defined by bits Y 1 , Y 1 , Y 2 , Y 2 , ···, Y n , Y n does not coincide with any of the defective column addresses written into the redundancy Y decoders 5-1a and 5-1b, at least one of the transistors Q 11 , Q 11 ', Q 12 , Q 12 ',···, Q 1 n , Q 1 n ' connected to the non-melted fuses and at least one of the transistor Q 21 , Q 21 ', Q 22 , Q 22 ',···, Q 2 n , Q 2 n ' connected to the non-melted fuses are turned ON, so that the voltages at nodes N 1 and N 2 become low (= GND). As a result, the redundancy column selection signals RCS 11 and RCS 12 are both high, and the output of the NOR circuit 6-1 is high. Thus, one column of the normal cell array of the memory cell block 1-1 is selected. On the other hand, when the Y address signal AD Y defined by the bits Y 1 , Y 1 , Y 2 , Y 2 ,···, Y n , Y n coincides with the defective column address written into the redundancy Y decoder such as 5-1a, all the turned ON ones of the transistors Q 11 , Q 11 ', Q 12 , Q 12 ',···, Q 1 n , Q 1 n ' are connected to melted fuses, so that the voltage at the node N 1 remains high the same as when precharged with the transistor Q 10 . Therefore, when the voltage of the block selection signal BK1 becomes high, the redundancy column selection signal RCS 11 is low and the output of the NOR circuit 6-1 is low. Thus, the normal cell array of the memory cell block 1-1 is disabled, and instead of this, the redundancy memory cell column 1-1a is selected. In other words, a defective memory cell column of the normal cell array of the memory cell block 1-1 is replaced with the redundancy memory cell column 1-1a. Note that the memory cell block 1-2 (1-3, 1-4) the X decoder 2-2 (2-3, 2-4), the Y decoder 3-2 (3-3, 3-4), the sense amplifier 4-2 (4-3, 4-4), and the redundancy Y decoders 5-2a, 5-2b (5-3a, 5-3b, 5-4a, 5-4b) have the same configuration as the memory cell block 1-1, the X decoder 2-1, the Y decoder 3-1, the sense amplifier 4-1, and the redundancy Y decoders 5-1a, 5-1b, respectively. Here, in a 4 Mbit dynamic random access memory (DRAM) formed by four memory cell blocks, if the probability of relieving each memory cell block by its first column is 90% and the probability of relieving each memory cell block by its second redundancy memory cell column is 10%, the probability of relieving each memory cell block by its two redundancy memory cell columns is 100%, and accordingly, this DRAM can be completely relieved. In this example, if the second redundancy memory cell column is absent in each memory cell block, the probability of each memory cell block being relieved by its redundancy memory cell is 90%, and accordingly, the probability of relieving the DRAM is only 65% (= 0.9 4 ). Thus, the second redundancy memory cell column is indispensable for each memory cell block. In Fig. 3, which illustrates another prior art semiconductor memory device, two redundancy memory cell rows such as 1-1c and 1-1d are incorporated into each of the memory cell blocks 1-1, 1-2, 1-3 and 1-4, instead of the two redundancy memory cell columns such as 1-1a and 1-1b. The redundancy memory cell rows 1-1c and 1-1d are selected by redundancy memory cell selection signals RRS 11 and RRS 12 , respectively. The redundancy memory cell rows 1-1c, 1-1d, 1-2c, 1-2d, 1-3c, 1-3d, 1-4c and 1-4d are selected by redundancy X decoders (redundancy row decoders) 5-1c, 5-1d, 5-2c, 5-2d, 5-3c, 5-3d, 5-4c and 5-4d, respectively, not by the X decoders 2-1, 2-2, 2-3 and 2-4. In Fig. 4, which is a detailed circuit diagram of the redundancy X decoders 5-1c and 5-1d of Fig. 3, the redundancy X decoders 5-1c and 5-1d have the same configuration as the redundancy Y decoders 5-1a and 5-1b of FIg. 2. However, the redundancy X decoders 5-1c and 5-1d receive X address signals X 1 , X 1 , X 2 , X 2 ,···, X m , X m , not the Y address signal Y 1 , Y 1 , Y 2 , Y 2 , ···, Y n , Y n . The operation of the circuit of Fig. 4 is the same as that of the circuit of Fig. 2. That is, when the X address signal AD x defined by bits X 1 , X 1 , X 2 , X 2 ,···, X n , X n does not coincide with any of the defecitve row addresses written into the redundancy X decoders 5-1c and 5-1d, at least one of the transistors Q 11 , Q 11 ', Q 12 , Q 12 ', ···, Q 1 m , Q 1 m ' connected to the non-melted fuses and at least one of the transistor Q 21 , Q 21 ', Q 22 , Q 22 ',···, Q 2 m , Q 2 m ' connected to the non-melted fuses are turned ON, so that the voltages at nodes N 1 and N 2 become low (= GND). As a result, the redundancy row selection signals RRS 11 and RRS 12 are both high, and the output of the NOR circuit 6-1 is high. Thus, one row of the normal cell array of the memory cell block 1-1 is selected. On the other hand, when the X address signal AD x defined by the bits X 1 , X 1 , X 2 , X 2 ,···, X m , X m coincides with the defecitve row address written into the redundancy X decoder such as 5-1c, all the turned ON ones of the transistors Q 11 , Q 11 ', Q 12 , Q 12 ',···, Q 1 m , Q 1 m ' are connected to melted fuses, so that the voltage at the node N 1 remains high the same as when precharged with the transistor Q 10 . Therefore, when the voltage of the block selection signal BK1 becomes high, the redundancy row selection signal RRS 11 is low and the output of the NOR circuit 6-1 is low. Thus, the normal cell array of the memory cell block 1-1 is disabled, and instead of this, the redundancy memory cell row 1-1c is selected. In other words, a defective memory cell row of the normal cell array of the memory cell block 1-1 is replaced with the redundancy memory cell row 1-1c. In the case of a 4 Mbit DRAM, each of the redundancy Y decoder such as 5-1a of Fig. 2 and the redundancy X decoder such as 5-1c has the following area. That is, in the abscissa direction, the width of a fuse and the interval of fuses is 3 µ m to thereby surely carry our a laser trimming. Also, a protection area having a width of 6 µ m is provided on both sides. Thus, if the number of bits of the Y address signal AD Y or the X address signal DA X is 7, the width in the abscissa direction as shown in Fig. 5 is (1 + 3) · 14 + 6 · 2 = 68 µm Also, in the ordinate direction, the length of each fuse including its protection area is 12 µm and a length of each transistor is 28 µ m. Therefore, the length in the ordinate direction as shown in Fig. 5 is 12 + 28 = 40 µm Thus, an area of each redundancy decoder is 68 · 40 ≒ 2800 µm 2 Also, in Figs. 1 and 3, a total area of the redundancy decoders is 2800 · 8 = 22400 µm 2 Thus, in Figs. 1 and 3, the total area of the redundancy decoders is so large that a chip area of the device is increased, and accordingly, the integration of the device is reduced. In Fig. 6, which illustrates a first embodiment of the present invention, a redundancy Y decoder 5-1b' is provided instead of the redundancy Y decoders 5-1b and 5-2b of Fig. 1. That is, the redundancy Y decoder 5-1b' is provided commonly for the redundancy memory cell column 1-1b of the memory cell block 1-1 and the redundancy memory cell column 1-2b of the memory cell block 1-2. In this case, the redundancy Y decoder 5-1b' receives both the memory cell block selection signals BK1 and BK2. Assume that the Y address signal AD Y defined by Y 1 , Y 1 , Y 2 , Y 2 , ···, Y n , Y n coincides with the defective column address written into the redundancy Y decoder 5-1b'. In this case, when the memory cell block selection signal BK1 is high, the redundancy column Y decoder 5-1b' makes the redundancy column selection signal RCS 12 low, thus selecting the redundancy memory cell column 1-1b. On the other hand, when the memory cell block selection signal BK2 is high, the redundancy column Y decoder 5-1b' makes the redundancy column selection signal RCS 22 low, thus selecting the redundancy memory cell column 1-2b. Similarly, a redundancy Y decoder 5-4b' is provided instead of the redundancy Y decoders 5-3b and 5-4b of Fig. 1. That is, the redundancy Y decoder 5-4b' is provided commonly for the redundancy memory cell column 1-3b of the memory cell block 1-3 and the redundancy memory cell column 1-4b of the memory cell block 1-4. In this case, the redundancy Y decoder 5-4b' receives both the memory cell block selection signals BK3 and BK4. Assume that the Y address signal AD Y defined by Y 1 , Y 1 , Y 2 , Y 2 , ···, Y n , Y n coincides with the defective column address written into the redundancy Y decoder 5-4b'. In this case, when the memory cell block selection signal BK3 is high, the redundancy Y decoder 5-4b' makes the redundancy column selection signal RCS 32 low, thus selecting the redundancy memory cell column 1-3b. On the other hand, when the memory cell block selection signal BK4 is high, the redundancy Y decoder 5-4b' makes the redundancy column selection signal RCS 42 low, thus selecting the redundancy memory cell column 1-4b. In Fig. 7, which is a detailed circuit diagram of the redundancy Y decoders 5-1a, 5-2a and 5-1b' of Fig. 6, the redundancy Y decoder 5-1b' has the same configuration as the redundancy Y decoder 5-1a and 5-2a, except that two NAND circuits G 12 and G 22 are provided. That is, when the memory cell block selection signal BK1 is high and the Y address signal defined by Y 1 , Y 1 , Y 2 , Y 2 , ···, Y n , Y n coincides with the defective column address defined by the fuses F 21 , F 21 ', F 22 , F 22 ',···, F 2 n , F 2 n ', the output of the NAND circuit G 12 , i.e., the redundancy column selection signal RCS 12 becomes high to select the redundancy memory cell column 1-1b. On the other hand, when the memory cell block selection signal BK2 is high and the Y address signal defined by Y1, Y 1 , Y 2 , Y 2 , ···, Y n , Y n coincides with the defective column address defined by the fuses F 21 , F 21 ', F 22 , F 22 ',···, F 2 n , F 2 n ', the output of the NAND circuit G 22 , i.e., the redundancy column selection signal RCS 22 becomes high to select the redundancy memory cell column 1-2b. Also, in Fig. 7, the NOR circuit 6-1 receives the precharged voltage of the redundancy Y decoder 5-1a and the precharged voltage of the redundancy Y decoder 5-1b' via an AND circuit 7-1, to thereby disable the Y decoder 3-1 when one of the redundancy memory cell columns 1-1a and 1-1b is selected. Note that the AND circuit 7-1 is activated by the memory cell block signal BK1. Similarly, the NOR circuit 6-2 receives the precharged voltage of the redundancy Y decoder 5-2a and the precharged voltage of the redundancy Y decoder 5-1b' via an AND circuit 7-2, to thereby disable the Y decoder 3-2 when one of the redundancy memory cell columns 1-2a and 1-2b is selected. Note that the AND circuit 7-2 is activated by the memory cell block signal BK2. In Fig. 8, which is a modification of the circuit of Fig. 7, the redundancy Y decoder 5-1b' of Fig. 7 is modified into a redundancy Y decoder 5-1b". That is, the NAND circuits G 12 and G 22 are apart from the redundancy Y decoder 5-1b", and, in order to compensate for a long distance therebetween, inverters I 1 and I 2 are added. Since the NAND circuits G 12 and G 22 receive the memory cell block selection signals BK1 and BK2, respectively, the NAND circuits G 12 and G 22 are located in accordance with the location of signal lines of the memory cell block selection signals BK1 and BK2. As a result, the NAND circuits G 12 and/or G 22 are distant from the redundancy Y decoder 5-1b". This can be compensated for by the inverters I 1 and I 2 . In Fig. 6, the total area of the redundancy decoders is 2800.6 = 16800 µm 2 Therefore, the total area of the redundancy decoders can be reduced by about 25 percent as compared with the prior art (see formula (1)), so that the integration of the device can be enhanced. Here, in Fig. 6, if the probability of relieving each of the memory cell blocks 1-1 and 1-2 by its first redundancy memory cell column such as 1-1a is 90% and the probability of relieving each of the memory cell blocks 1-1 and 1-2 by its second redundancy memory cell column such as 1-1b is 10%, since it is impossible to simultaneously relieve two defective memory cells for each of the memory cell blocks 1-1 and 1-2, the probability of relieving each of the memory cell blocks 1-1 and 1-2 by its two redundancy memory cell columns is (1 - 0.1 2 ) = 99% Similarly, the probabity of relieving each of the memory cell blocks 1-3 and 1-4 by its two redundancy memory cell columns is (1 - 0.1 2 ) = 99% Therefore, the probability of relieving the device is (1 - 0.1 2 ) · (1 - 0.1 2 ) = 98% Particularly, if a column address of a defective memory cell found in the memory cell block 1-1 is the same as a column address of a defective memory cell found in the memory cell block 1-2, this column address is written into the redundancy Y decoder 5-1b', thus slightly raising the probalility of relieving the device. Thus, in the first embodiment, the probability of relieving the device is not so reduced. In Fig. 9, which illustrates a second embodiment of the present invention, a redundancy Y decoder 5-b is provided instead of the redundancy Y decoders 5-1b, 5-2b, 5-3b and 5-4b of Fig. 1. That is, the redundancy Y decoder 5-b is provided commonly for the redundancy memory cell column 1-1b of the memory cell block 1-1, the redundancy memory cell column 1-2b of the memory cell block 1-2, the redundancy memory cell column 1-3b of the memory cell block 1-3 and the redundancy memory cell column 1-4b of the memory cell block 1-4. In this case, the redundancy Y decoder 5-b receives all the memory cell block selection signals BK1, BK2, BK3 and BK4. Assume that the Y address signal AD Y defined by Y 1 , Y 1 , Y 2 , Y 2 , ···, Y n , Y n coincides with the defective column address written into the redundancy Y decoder 5-b. In this case, when the memory cell block selection signal BK1 is high, the redundancy column Y decoder 5-b makes the redundancy column selection signal RCS 12 low, thus selecting the redundancy memory cell column 1-1b. Also, when the memory cell block selection signal BK2 is high, the redundancy column Y decoder 5-1b' makes the redundancy column selection signal RCS 22 low, thus selecting the redundancy memory cell column 1-2b. Further, when the memory cell block selection signal BK3 is high, the redundancy column Y decoder 5-b makes the redundancy column selection signal RCS 32 low, thus selecting the redundancy memory cell column 1-3b. Further, when the memory cell block selection signal BK4 is high, the redundancy column Y decoder 5-b makes the redundancy column selection signal RCS 42 low, thus selecting the redundancy memory cell column 1-4b. In Fig. 10, which is a detailed circuit diagram of the redundancy Y decoder 5-b, of Fig. 9, the redundancy Y decoder 5-b has the same configuration as the redundancy Y decoder 5-1b' except that two additional NAND circuits G 32 and G 42 are provided. That is, when the memory cell block selection signal BK1 is high and the Y address signal defined by Y 1 , Y 1 , Y 2 , Y 2 , ···, Y n , Y n coincides with the defective column address defined by the fuses F 21 , F 21 ', F 22 , F 22 ',···, F 2 n , F 2 n ', the output of the NAND circuit G 12 , i.e., the redundancy column selection signal RCS 12 becomes high to select the redundancy memory cell column 1-1b. Also, when the memory cell block selection signal BK2 is high and the Y address signal defined by Y 1 , Y 1 , Y 2 , Y 2 , ···, Y n , Y n coincides with the defective column address defined by the fuses F 21 , F 21 ', F 22 , F 22 ', ···, F 2 n , F 2 n ', the output of the NAND circuit G 22 , i.e., the redundancy column selection signal RCS 22 becomes high to select the redundancy memory cell column 1-2b. Further, when the memory cell block selection signal BK3 is high and the Y address signal defined by Y 1 , Y 1 , Y 2 , Y 2 ,···, Y n , Y n coincides with the defective column address defined by the fuses F 21 , F 21 ', F 22 , F 22 ', ···, F 2 n , F 2 n ', the output of the NAND circuit G 32 , i.e., the redundancy column selection signal RCS 42 becomes high to select the redundancy memory cell column 1-3b. Further, when the memory cell block selection signal BK4 is high and the Y address signal defined by Y 1 , Y 1 , Y 2 , Y 2 ,···, Y n , Y n coincides with the defective column address defined by the fuses F 21 , F 21 ', F 22 , F 22 ',···, F 2 n , F 2 n ', the output of the NAND circuit G 42 , i.e., the redundancy column selection signal RCS 42 becomes high to select the redundancy memory cell column 1-4b. In Fig. 11, which is a modification of the circuit of Fig. 10, the redundancy Y decoder 5-b of Fig. 10 is modified into a redundancy Y decoder 5-b'. That is, the NAND circuits G 12 , G 22 , G 32 and G 42 are apart from the redundancy Y decoder 5-b', and, in order to compensate for a long distance therebetween, inverters I 1 and I 2 are added. Since the NAND circuits G 12 , G 22 , G 32 and G 42 receive the memory cell block selection signals BK1, BK2, BK3 and BK4, respectively, the NAND circuits G 12 , G 22 , G 32 and G 42 are preferably located in accordance with the location of signal lines of the memory cell block selection signals BK1, BK2, BK3 and BK4. As a result, some of the NAND circuits G 12 , G 22 , G 32 and G 42 are distant from the redundancy Y decoder 5-b'. This can be compensated for by the inverters I 1 and I 2 . Note that the NOR circuits such as 6-1 and 6-2 of Fig. 7 for disabling the Y decoders such as 3-1 and 3-2 are provided in the device of Fig. 9; however, these circuits are omitted therefrom to simplify the description. In Fig. 9, the total area of the redundancy decoders is 2800 · 5 = 14000 µm 2 Therefore, the total area of the redundancy decoders can be reduced by about 38 percent as compared with the prior art (see formula (1)), so that the integration of the device can be further enhanced. Again, in Fig. 9, if the probability of relieving each of the memory cell blocks 1-1, 1-2, 1-3 and 1-4 by its first redundancy memory cell column such as 1-1a is 90% and the probability of relieving each of the memory cell blocks 1-1 and 1-2 by its second redundancy memory cell column such as 1-1b is 10%, it is impossible for two of the memory cell blocks 1-1, 1-2, 1-3 and 1-4 to use the redundancy Y decoder 5-b simultaneously. This probability is 0.1 2 · 4 C 2 = 0.01 · 6 = 0.06. Also, it is impossible for three of the memory cell blocks 1-1, 1-2, 1-3 and 1-4 to use the redundancy Y decoder 5-b simultaneously. This probability is 0.1 3 · 4 C 3 = 0.001 · 4 = 0.004. Further, it is impossible for all the memory cell blocks 1-1, 1-2, 1-3 and 1-4 to use the redundancy Y decoder 5-b simultaneously. This probability is 0.1 4 · 4 C 4 = 0.0001 · 1 = 0.00001 Therefore, the probability of relieving the device is 1 - (0.06 + 0.004 + 0.0001) = 93.59% Thus, in the second embodiment, the probability of relieving the device is not so reduced. In Fig. 12, which illustrates a third embodiment of the present invention, the first embodiment is applied to the device of Fig. 3. That is, a redundancy X decoder 5-1d' is provided commonly for the redundancy memory cell column 1-1b of the memory cell block 1-1 and the redundancy memory cell column 1-2b of the memory cell block 1-2. Also, a redundancy X decoder 5-4d' is provided commonly for the redundancy memory cell column 1-3b of the memory cell block 1-3 and the redundancy memory cell column 1-4b of the memory cell block 1-4. The operation and effect of the third embodiment are basically the same as those of the first embodiment. In Fig. 13, which illustrates a fourth embodiment of the present invention, the second embodiment is applied to the device of Fig. 3. That is, a redundancy X decoder 5-d is provided commonly for the redundancy memory cell column 1-1b of the memory cell block 1-1, the redundancy memory cell column 1-2b of the memory cell block 1-2, the redundancy memory cell column 1-3b of the memory cell block 1-3 and the redundancy memory cell column 1-4b of the memory cell block 1-4. The operation and effect of the third embodiment are basically the same as those of the first embodiment. Although the above-described embodiments relate to a semiconductor memory device having four memory cell blocks, the present invention can be applied to a semiconductor memory device having any number of memory cell blocks such as 32 memory cell blocks and 64 memory cell blocks. As explained hereinbefore, according to the present invention, since the total area of redundancy decoders can be reduced, the integration of the device can be enhanced without substantially reducing the probability of relieving the device.

Claims: A semiconductor memory device comprising: a plurality of memory cell blocks (1-1~1-4) each having a normal memory cell array and first and second redundancy memory cell columns (1-1a, 1-2a, ···, 1-1b, 1-2b, ···); a plurality of first redundancy column selecting means (5-1a, 5-2a, ···), each provided for one of said memory cell blocks and storing a first redundancy column address, each of said first redundancy column selecting means accessing said first redundancy memory cell column of a respective memory cell block in response to receiving a respective memory cell block selection signal (BK1, ···) and said first redundancy column address; and a plurality of second redundancy column selecting means (5-1b', 5-4b', ···), each provided for at least two of said memory cell blocks and storing a second redundancy column address, each of said second redundancy column selecting means accessing said second redundancy memory cell column of a respective memory cell block in response to receiving a respective memory cell block selection signal and said second redundancy column address. A device as set forth in claim 1, wherein each of said first redundancy column selecting means comprises: a first precharging transistor (Q 10 , ···) connected to a first power supply terminal (V DD ); a plurality of first fuses (F 11 , F 11 ', ··· ) connected to said first precharging transistor; a plurality of first switching transistors (Q 11 , Q 11 ', ···) each connected between one of said first fuses and a second power supply terminal (GND), each of said first switching transistors being controlled by one of column address signals (Y 1 , Y 2 , ···) and their inverted signals ( Y 1 , Y 2 ,···); and a first gate circuit (G 11 ,···) having a first input connected to a first node between said first precharging transistor and said first fuses, a second input for receiving a respective memory cell block selection signal (BK1) and an output for generating a selection signal (RCS 11 ,···) for said first redundancy memory cell column of a respective memory cell block. A device as set forth in claim 1, wherein each of said second redundancy column selecting means comprises: a second precharging transistor (Q 20 , ···) connected to a first power supply terminal (V DD ); a plurality of second fuses (F 21 , F 21 ', ···) connected to said second precharging transistor; a plurality of second switching transistors (Q 21 , Q 21 ', ···), each connected between one of said second fuses and a second power supply terminal (GND), each of said second switching transistors being controlled by one of column address signals (Y 1 , Y 2 , ···) and their inverted signals ( Y 1 , Y 2 , ···); and a plurality of second gate circuits (G 21 , G 22 , ···), each having a first input connected to a second node between said second precharging transistor and said second fuses, a second input for receiving a respective memory cell block selection signal and an output for generating a selection signal (RCS 12 , ···) of said second redundancy memory cell column of a respective memory cell block. A semiconductor memory device comprising: a plurality of memory cell blocks (1-1~1-4) each having a normal memory cell array and first and second redundancy memory cell columns (1-1a, 1-2a,···, 1-1b, 1-2b,···); a plurality of first redundancy column selecting means (5-1a, 5-2a,···), each provided for one of said memory cell blocks and storing a first redundancy column address, each of said first redundancy column selecting means accessing said first redundancy memory cell column of a respective memory cell block in response to receiving a respective memory cell block selection signal (BK1,···) and said first redundancy column address; and a single second redundancy column selecting means (5-b), provided for said memory cell blocks and storing a second redundancy column address, said second redundancy column selecting means accessing said second redundancy memory cell column of a respective memory cell block in response to receiving a respective memory cell block selection signal and said second redundancy column address. A device as set forth in claim 4, wherein each of said first redundancy column selecting means comprises: a first precharging transistor (Q 10 ,···) connected to a first power supply terminal (V DD ); a plurality of first fuses (F 11 , F 11 ',···) connected to said first precharging transistor; a plurality of first switching transistors (Q 11 , Q 11 ',···) each connected between one of said first fuses and a second power supply terminal (GND), each of said first switching transistors being controlled by one of column address signals (Y 1 , Y 2 ,···) and their inverted signals ( Y 1 , Y 2 ,···); and a first gate circuit (G 11 ,···) having a first input connected to a first node between said first precharging transistor and said first fuses, a second input for receiving a respective memory cell block selection signal and an output for generating a selection signal (RCS 11 ,···) for said first redundancy memory cell column of a respective memory cell block. A device as set forth in claim 4, wherein said second redundancy column selecting means comprises: a second precharging transistor (Q 20 ,···) connected to a first power supply terminal (V DD ); a plurality of second fuses (F 21 , F 21 ', ···) connected to said second precharging transistor; a plurality of second switching transistors (Q 21 , Q 21 ',···), each connected between one of said second fuses and a second power supply terminal (GND), each of said second switching transistors being controlled by one of column address signals (Y 1 , Y 2 ,···) and their inverted signals ( Y 1 , Y 2 ,···); and a plurality of second gate circuits (G 21 , G 22 , ···), each of said second gate circuits being provided for one of said memory cell blocks, each of said second gate circuits having a first input connected to a second node between said second precharging transistor and said second fuses, a second input for receiving a respective memory cell block selection signal and an output for generating a selection signal (RCS 12 ,···) of said second redundancy memory cell column of a respective memory cell. block. A semiconductor memory device comprising: a plurality of memory cell blocks (1-1~1-4) each having a normal memory cell array and first and second redundancy memory cell rows (1-1c, 1-2c,···, 1-1d, 1-2d,···); a plurality of first redundancy row selecting means (5-1c, 5-2c,···), each provided for one of said memory cell blocks and storing a first redundancy row address, each of said first redundancy row selecting means accessing said first redundancy memory cell row of a respective memory cell block in response to receiving a respective memory cell block selection signal (BK1,···) and said first redundancy row address; and a plurality of second redundancy row selecting means (5-1d', 5-4d',···), each provided for at least two of said memory cell blocks and storing a second redundancy row address, each of said second redundancy row selecting means accessing said second redundancy memory cell column of a respective memory cell block in response to receiving a respective memory cell block selection signal and said second redundancy row address. A device as set forth in claim 7, wherein each of said first redundancy row selecting means comprises: a first precharging transistor (Q 10 ) connected to a first power supply terminal (V DD ); a plurality of first fuses (F 11 , F 11' ,....) connected to said first precharging transistor; a plurality of first switching transistors (Q 11 ,Q 11 ',...) each connected between one of said first fuses and a second power supply terminal (GND), each of said first switching transistors being controlled by one of row address signals (X 1 , X 2 , ···) and their inverted signals ( X 1 , X 2 ,···); a first gate circuit having a first input connected to a first node between said first precharging transistor and said first fuses, a second input for receiving a respective memory cell block selection signal and an output for generating a selection signal (RRS 11 ,···) for said first redundancy memory cell row of a respective memory cell block. A device as set forth in claim 7, wherein each of said second redundancy row selecting means comprises: a second precharging transistor (Q 20 ,···) connected to a first power supply terminal (V DD ); a plurality of second fuses (F 21 , F 21 ', ···) connected to said second precharging transistor; a plurality of second switching transistors (Q 21 , Q 21 ',···) each connected between one of said second fuses and a second power supply terminal (GND) each of said second switching transistors being controlled by one of row address signals (X 1 , X 2 ,··· ) and their inverted signals ( X 1 , X 2 , ··· ); and a plurality of second gate circuits, each having a first input connected to a second node between said second precharging transistor and said second fuses, a second input for receiving a respective memory cell block selection signal and an output for generating a selection signal (RRS 12 ,···) of said second redundancy memory cell row of a respective memory cell block. A semiconductor memory device comprising: a plurality of memory cell blocks (1-1~1-4) each having a normal memory cell array and first and second redundancy memory cell rows (1-1c, 1-2c,···, 1-1d, 1-2d,···); a plurality of first redundancy row selecting means (5-1c, 5-2c,···), each provided for one of said memory cell blocks and storing a first redundancy row address, each of said first redundancy row selecting means accessing said first redundancy memory cell row of a respective memory cell block in response to receiving a respective memory cell block selection signal (BK1,···) and said first redundancy row address; and a single second redundancy row selecting means (5-d), provided for said memory cell blocks and storing a second redundancy row address, said second redundancy row selecting means accessing said second redundancy memory cell row of a respective memory cell block in response to receiving a respective memory cell block selection signal and said second redundancy row address. A device as set forth in claim 10, wherein each of said first redundancy row selecting means comprises: a first precharging transistor (Q 10 ,···) connected to a first power supply terminal (V DD ); a plurality of first fuses (F 11 , F 11 ',···) connected to said first precharging transistor; a plurality of first switching transistors (Q 11 , Q 11 ',···) each connected between one of said first fuses and a second power supply terminal (GND), each of said first switching transistors being controlled by one of row address signals (X 1 , X 2 , ···) and their inverted signals ( X 1 , X 2 ,···); and a first gate circuit (G 11 ,···) having a first input connected to a first node between said first precharging transistor and said first fuses, a second input for receiving a respective memory cell block selection signal and an output for generating a selection signal (RRS 11 ,···) for said first redundancy memory cell row of a respective memory cell block. A device as set forth in claim 10, wherein said second redundancy row selecting means comprises: a second precharging transistor (Q 20 ,···) connected to a first power supply terminal (V DD ); a plurality of second fuses (F 21 , F 21 ', ···) connected to said second precharging transistor; a plurality of second switching transistors (Q 21 , Q 21 ',···), each connected between one of said second fuses and a second power supply terminal (GND), each of said second switching transistors being controlled by one of row address signals (X 1 , X 2 ,···) and their inverted signals ( X 1 , X 2 ,···); and a plurality of second gate circuits, each of said second gate circuits being provided for one of said memory cell blocks, each of said second gate circuits having a first input connected to a second node between said second precharging transistor and said second fuses, a second input for receiving a respective memory cell block selection signal and an output for generating a selection signal (RRS 12 ,···) of said second redundancy memory cell row of a respective memory cell block.

Inventors: OGAWA SUMIO, OGAWA, SUMIO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1995
Main classification: G06F11
IPC codes: G11C29, G11C11, H04Q3