Method for fabricating oxide layer in semiconductor technology

Abstract: In one embodiment a high-quality tunnel oxide suitable for programmable devices, such as EEPAL devices, is formed upon a surface region of a semiconductor body over a heavily-doped N+ layer, and a gate oxide is formed over a gate region, by first oxidizing the semiconductor body to form an initial oxide layer upon the surface region of the semiconductor body over the heavily-doped N+ layer and upon the surface of the gate region. Next, at least a portion of the initial oxide layer overlying the heavily-doped N+ layer is removed. The semiconductor body is then exposed to an environment suitable for oxidation, to thicken the remaining portions of the initial oxide, thereby forming the gate oxide, and to form the tunnel oxide over the heavily doped N+ layer. A concentration of nitrogen is introduced into both gate and tunnel oxides by introducing the semiconductor body to a source of nitrogen.

Description: This invention relates to the fabrication of semiconductor devices, and more specifically, to methods for achieving high quality oxides on the surface of a semiconductor substrate. The importance of high quality oxides in the fabrication of semiconductor devices cannot be over-emphasized. Many broad categories of commercial devices, such as Electrically Erasable Programmable Array Logic (EEPAL) devices, Electrically Erasable Programmable Read-Only Memories (EEPROMS), Dynamic Random Access Memories (DRAMs), and more recently, even high-speed basic logic functions, owe their commercialization to the reproducibility of high quality, very thin oxide layers. Major improvements in gate oxide quality have been achieved by improved cleaning techniques, the addition of HCL/TCA to the gate oxidation process, and higher purity gasses and chemicals. RCA cleaning techniques are described in "Dependence of Thin Oxide Quality on Surface Micro-Roughness" by T. Ohmi, et. al., IEEE Transactions on Electron Devices, Vol. 39, Number 3, March 1992. Other techniques have incorporated different gas (NH 3 , ONO, WET O 2 ) schemes in the gate oxidation cycle other than the conventional O 2 with HCL or TCA. Also considerable progress has been made with single wafer RTA (RTP) gate processing, as is described in "Effect of Rapid Thermal Reoxidation on the Electrical Properties of Rapid Thermally Nitrided Thin-Gate Oxides", by A. Joshi, et. al., IEEE Transactions on Electron Devices, Vol. 39, Number 4, April 1992. These techniques refer to "gate oxides" as in the gate of an MOS transistor, but are usually applicable to any thin (usually less than 300Å) oxide. The "tunnel" oxide of an EEPAL process technology is a very thin gate oxide (usually less than 100Å), with the somewhat unusual requirement that it be grown above a very heavily doped N+ layer. Oxides grown from heavily doped substrate surfaces are generally considered to be lower in quality than those grown from more lightly doped surfaces, as would be the case for the transistor channel region of most MOS transistor processes. Despite the care taken in forming thin oxides, further quality improvement is desirable. Moreover, even thinner oxides are desirable for new devices, and must have similarly high quality oxide characteristics. It would be desirable to improve the quality of a very thin oxide layer. It would also be desirable to improve the quality of a tunnel oxide for a programmable technology, such as an EEPAL. Furthermore, it would be desirable to improve the quality of a gate oxide for an MOS transistor. It would be desirable to provide an environment for forming a thin oxide using a relatively low oxidation temperature. Moreover, it would be desirable to produce high quality, highly manufacturable and reproducible thin oxides, especially those having thicknesses in the range from 25-75Å. US 5 296 411, by the same applicants, discloses a method as defined in the preamble of Claim 1. However, the method is not suitable for producing oxide layers of less than 60Å thickness. In one embodiment of the present invention for an integrated circuit fabrication process, a method for forming a first oxide layer having a thickness of 6nm or less upon a first surface region of a semiconductor body, and further for forming a second oxide layer, of greater thickness than the first oxide layer, upon a second surface region of the semiconductor body. includes the step of forming an initial oxide layer upon the first and second surface regions. The method then includes the step of removing at least a portion of the initial oxide layer in a region disposed above the first surface region of the semiconductor body, followed by the step of exposing the semiconductor body to an environment suitable for oxide formation, at a temperature of 800°C or less and in the absence of low O 2 , to form a first oxide layer disposed above the first surface region of the semiconductor body and to thicken the initial oxide layer disposed above the second surface region, thus forming the second oxide layer. The method includes the step of introducing, subsequent to the commencement of the exposing step, the semiconductor body to a source of nitrogen, to form a concentration of nitrogen in both the first and second oxide layers. In another embodiment of the current invention, the introducing step is performed simultaneously with the exposing step, whereby the environment suitable for oxide formation includes a source of nitrogen during at least a portion of the exposing step, to form a concentration of nitrogen in at least a portion of both the first and second oxides. In yet another embodiment of the current invention, the method further includes the additional step, subsequent to the exposing and introducing steps, of annealing the semiconductor body. Alternatively, in still yet another embodiment of the current invention, the introducing step comprises the step of annealing the semiconductor body, subsequent to the exposing step, under an ambient containing nitrogen, to form a surface layer in both the first and second oxides containing a concentration of nitrogen BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1-6 are cross-sectional views illustrating a sequence of process steps for forming gate and tunnel oxides in a P-well active area of a CMOS EEPAL process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figs. 1-6 are cross-sectional views illustrating a sequence of process steps for forming gate and tunnel oxides in a P-well active area of a CMOS EEPAL process. Such views are also applicable to other similar processes, such as those for certain CMOS EEPROMs. The gate oxide is used to fabricate N-channel MOS transistors, and the tunnel oxide is used to fabricate a structure useful to an EEPAL cell element. Referring to Fig. 1, P-well field oxides 102 are formed using a LOCOS process upon substrate 100. P-well field oxides 102 define a P-well active area 110 between the field oxides 102. KOOI oxide 104 then is grown in a steam oxidation environment to a thickness of approximately 225Å. The growing and subsequent removing of KOOI oxide is a well known procedure for eliminating the remnant KOOI ribbon of nitride which forms around the active area at the LOCOS edge during the previous field oxidation. (Silicon nitride in a steam oxidation environment decomposes into ammonia and silicon dioxide. The ammonia diffuses down through the field oxide until reaching the silicon surface, where it reacts to form a silicon nitride, and leaving a ribbon of nitride at the silicon/silicon dioxide interface around the edge of the active area.) V TI Implant 162 is then implanted over the whole wafer to set the nominal threshold of MOS transistors to be fabricated later in the P-wells. This is preferably a light boron implant which is applied without any masking photoresist (i.e. a "blanket implant") to both P-well regions and N-well regions (not shown). A preferable implant dose is 0.4-2.0 x 10 12 ions/cm 2 at an implant energy of 25 keV. A separate V TP implant (not shown) is then implanted into the N-well regions (not shown) to adjust the threshold of P-channel MOS transistors to be fabricated later in the N-wells. To accomplish this, a photoresist layer is applied and defined to cover the P-wells while exposing the N-wells, the implant into the N-wells is performed (typically with an implant dose of 4 x 10 11 ions/cm 2 at an implant energy of 25 keV), and the photoresist overlying the P-wells then removed. Continuing with the process sequence as affects the P-well shown, a photoresist layer is applied and defined to form photoresist layer 106 which exposes a portion of the KOOI oxide 104 over the P-well active area 110. The resulting structure is shown in Fig. 2. The as-yet unactivated V TI implant layer 180 is shown under the KOOI oxide 104. Next, a phosphorus implant 108 is implanted through the exposed KOOI oxide and into the substrate 100 in the P-well active area 110 for the EEPAL process of this embodiment. A preferable implant dose is 1.0 x 10 15 ions/cm 2 at an implant energy of 60 keV. Other regions of the substrate are masked by the photoresist layer 106. Photoresist layer 106 is then removed and the surface is prepared for annealing by an RCA clean operation, resulting in the structure shown in Fig. 3. Phosphorus implant layer 120 has been created by the heavy dose of the phosphorus implant 108. Due to the implant damage to the KOOI oxide which was exposed to the phosphorus implant 108, the RCA clean operation etches some of the implant-damaged KOOI oxide, resulting in etched KOOI oxide 122 approximately 100Å thick in the region above phosphorus implant layer 120. The portion of the KOOI oxide 104 which was formerly protected by photoresist layer 106 and consequently not damaged by phosphorus implant 108 remains substantially unetched at 225Å thick. V TI implant layer 180 is not shown extending into phosphorus implant layer 120 because the doping density of phosphorus implant layer 120 is far greater than that of V TI implant layer 180. An anneal operation follows which drives the phosphorus implant layer 120 into the substrate 100, thereby lowering the surface concentration of phosphorus. Moreover, the anneal operation activates the phosphorus implant, thereby forming an N+ layer in the P-well, and activates the V TI implant layer 180, thereby forming a V TI layer. Next, a short oxide etch (e.g., 1.7 minutes in 10:1 HF) removes the remaining KOOI oxide 104 and etched KOOI oxide 122 from the surface of the P-well in preparation for gate oxidation. Preferable etch conditions for such a pre-gate oxidation etch step are discussed in commonly-assigned European Patent Application EP-A-0 595 464, filed on October 29, 1992, which names Mark I. Gardner, Henry Jim Fulford, Jr., and Jay J. Seaton as inventors and is entitled "Method for growing oxide layers in an integrated circuit fabrication process. The resulting structure is shown in Fig. 4, and shows P-well active area surface 142 free of overlying oxide, and further shows the formation of N+ layer 140, being deeper and broader than the previous unactivated phosphorus implant layer 120, due to the drive in accomplished during the previous anneal step. Moreover, the unactivated V TI implant layer 180 has been activated by the anneal step, resulting in V TI layer 224. Next, a gate oxide is formed over the P-well active area 110. This is preferably grown in a dry oxidation environment to a 140Å thickness, but alternatively may be deposited by a CVD process (discussed below). An in-situ anneal is preferably performed at the conclusion of the gate oxidation cycle by changing the ambient gases in the oxidation furnace to an inert annealing ambient, while continuing to apply a high temperature (e.g., 1000°C for 30 minutes in Argon). Several advantageous gate oxidation conditions are discussed in commonly-assigned United States Patent No. 5,316,981, issued on May 31, 1994, which names Mark I. Gardner and Henry Jim Fulford, Jr. as inventors and is entitled "Method for Achieving a High Quality Thin Oxide Using a Sacrificial Oxide Anneal" which patent corresponds to the European application No. EP-4-0 592 124. Continuing with the process sequence as affects the P-well shown, a photoresist layer is applied and defined to expose the gate oxide over the N+ layer 140, followed by an etch step to remove the exposed gate oxide. This Tunnel Opening etch may be a 0.2 minute etch in a 6:1 buffered oxide etchant, and removes the 140Å of gate oxide to expose the surface of the substrate over the N+ layer 140. Preferable conditions for this etch are discussed in the above-referenced patent application EP-A-0 595 464. The resulting structure is shown in Fig. 5 and shows the N+ surface 184 exposed by the tunnel opening etch. Photoresist layer 182 defines the tunnel opening and protects the remainder of gate o-xide 160 not overlying N+ layer 140. The V TI layer 224 is shown disposed under the gate oxide 160. Lastly, the photoresist layer 182 is removed and an oxidation sequence as described hereinafter both grows a tunnel oxide upon N+ surface 184 overlying N+ layer 140, and increases the thickness of the existing gate oxide 160. Referring to Fig. 6, tunnel oxide 220 may be nominally 85Å thick, while re-oxidized gate oxide 222 may be nominally 180Å thick. Tunnel oxides from 60-90Å and gate oxides from 100-180Å may be easily achieved using similar sequences to those described below. In an alternate embodiment, the tunnel opening etch may only partially remove (not shown) the gate oxide 160 overlying N+ layer 140, which is then subsequently thickened by the tunnel oxidation sequence to form the tunnel oxide. Subsequent to this step a polysilicon layer is deposited, doped, and defined to form, in accordance with any of a variety of well-known processes, transistors, interconnect, and other features. In particular, the polysilicon is deposited above tunnel oxide 220 to form a structure useful to an EEPAL cell which conducts current through tunnel oxide 220 if the electric field across the tunnel oxide 220 is high enough. Measurements of oxide quality can be made immediately after the polysilicon layer is patterned into useful structures. The reference oxidation sequence shown in Table 1 may be used to both grow a tunnel oxide from N+ surface 184 overlying N+ layer 140, and to increase the thickness of the existing gate oxide 160. As is shown, the tunnel oxidation proceeds as an oxidation stage, followed by a ramp-down in temperature, and then by an RTP anneal (a "rapid thermal process" anneal, which is also known as an "RTA anneal", and as a "rapid thermal anneal") in a nitrogen ambient. This sequence typically produces a tunnel oxide 220 having a nominal thicknes of 85Å. Tunnel Oxidation Sequence STEP GASSES TEMP TIME I. Push/Stabilize Ar Ramp to 800° C Final Temp t=28 min. II. Ramp to 850 Low O 2 /Ar 850° C Final Temp t=10 min. III. Oxidation O 2 850° C t=5 min. IV. Ramp to 800 N 2 or Ar 800° C Final Temp t=16 min. V. Pull/Stabilize N 2 or Ar less than 500° C t=31 min. VI. RTP anneal N 2 O 1050° C t=10 sec. Alternately, a reference oxidation sequence as described in Table 2 may be used to both grow a tunnel oxide from N+ surface 184 overlying N+ layer 140, and to increase the thickness of the existing gate oxide 160. As is shown, the tunnel oxidation proceeds as a three-stage oxidation cycle, with HCl gettering performed between the first and second stages, and again between the second and third stages. This procedure keeps the HCl away from both the silicon and the polysilicon interfaces, while still providing a high enough HCl concentration within the body of the gate oxide to getter any mobile ionic charge or heavy metals that may be present. HCl coming into contact with either a silicon or polysilicon interface will degrade that interface surface, and likewise degrade any oxide contiguous to that surface. Additionally, the gettering steps provide an annealing environment for the partially-grown oxide which serves to reduce roughness at the Si/SiO 2 interface and to densify the oxide, both of which are useful in promoting a high quality oxide. After the third stage of oxidation and a ramp-down in temperature, a rapid thermal anneal (RTP anneal, and also known as an "RTA anneal", even though technically redundant terminology) may be optionally performed in an N 2 O ambient environment. The N 2 O anneal step may form approximately another 15Å of oxide, resulting in a final thickness of approximately 75Å. Steps I-IX of Table 2, which include the oxidation and 75Å Tunnel Oxidation Sequence STEP GASSES TEMP TIME I. Push/ramp to 800°C Ar Ramp to 800°C Final Temp t=28 min. II. Ramp to 850 Low O 2 /Ar 850° C Final Temp t=10 min. III. Oxidation O 2 850° C t=12 min. IV. HCL Getter HCl/Ar 850° C t=5 min. V. Oxidation O 2 850° C t=2.0 min. VI. HCL Getter HCl/Ar 850° C t=5 min. VII. Oxidation O 2 850° C t=2.0 min. VIII. Ramp to 800 N 2 or Ar 800° C Final Temp t=16 min. IX. Pull/Stabilize N 2 or Ar less than 650° C t=31 min. X. RTP anneal N 2 O 1050°C t=10 sec. gettering steps, are preferably performed in a diffusion tube, while step X is, of course, preferably performed in an RTP system. Nonetheless, the final anneal (step X) can also be performed in a diffusion tube, if desired. Earlier doping profiles may need to be adjusted due to the high thermal mass of the tube and the resultant additional time at high temperature a wafer would experience compared to an RTP anneal. Many of the specific steps described above may be performed using a variety of different process steps. For example, the gate oxide may be advantageously formed by either a low-pressure chemical vapor deposition (LPCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a rapid thermal process (RTP), or a furnace process as described above. Similarly, the tunnel oxide may be advantageously formed by either a LPCVD, PECVD, RTP, or furnace process. Both oxide formations may be performed in either a N 2 O or O 2 ambient, and may or may not include the introduction of Cl into the oxide. Moreover, the nitrogen anneal may be advantageously performed in either a PECVD process, an RTP process, or in a conventional furnace process. Other oxidation sequences involving nitrogen are discussed in commonly-assigned United States Patent No. 5,296,411, issued on March 22, 1994, which names Mark I. Gardner and Henry Jim Fulford, Jr. as inventors and is entitled "Method for Achieving an Ultra-Reliable Thin Oxide Using a Nitrogen Anneal". The basic process sequence as described in Table 2 may be utilized to produce oxides down to approximately 60Å thick. To obtain thickness in the 30-40Å range, the temperature of the sequence must be lowered to 800°C. Table 3 discloses a tunnel oxidation sequence useful for producing a 40Å tunnel oxide, and is preferably performed in a furnace tube and followed by an RTP anneal (not shown in the table). Such an RTP anneal, which can range from a temperature of 900-1050°C, ensures a high quality oxide even though grown at a low furnace temperature. In contrast with the process shown in Table 2, no low O 2 is used in the tunnel oxidation cycle shown in Table 3. 40Å Tunnel Oxidation Sequence STEP GASSES TEMP TIME I. Push/ramp Ar Ramp to 800° C Final Temp t=28 min. II. Stabilize to 800 Ar 800° C Final Temp t=5 min. III. Oxidation O 2 800° C t=8 min. IV. HCL Getter HCl/Ar 800° C t=1.0 min. V. Oxidation O 2 800° C t=2.5 min. VI. HCL Getter HCl/Ar 800° C t=1.0 min. VII. Oxidation O 2 800° C t=2.5 min. VIII. Ramp to 800 Ar 800° C t=16 min. IX. Pull/Stabilize Ar less than 650°C t=31 min. The tunnel oxidation sequence disclosed in Table 4 may be used to produce a 30Å oxide. Similarly to the process of Table 3, and in contrast with the process shown in Table 2, no low O 2 is used in the tunnel oxidation cycle shown in Table 4. Even lower furnace temperatures of 700-750°C, followed by an RTP anneal, should allow 20-25Å tunnel oxides to be produced. Rather than an RTP anneal, the tunnel oxide may be produced by following a furnace growth with an LPCVD anneal under a low pressure ambient of N 2 O. Typical pressures range from 5-30 torr, while typical temperatures range from 900 to 1050°C. 30Å Tunnel Oxidation Sequence STEP GASSES TEMP TIME I. Push/ramp Ar Ramp to 800° C Final Temp t=28 min. II. Stabilize to 800 Ar 800° C Final Temp t=5 min. III. Oxidation O 2 800° C t=5 min. IV. HCL Getter HCl/Ar 800° C t=1.0 min. V. Oxidation O 2 800° C t=1.0 min. VI. HCL Getter HCl/Ar 800° C t=1.0 min. VII. Oxidation O 2 800° C t=1.0 min. VIII. Ramp to 800 Ar 800° C t=16 min. IX. Pull/stabilize Ar less than 650°C t=31 min. The tunnel oxidation may also be accomplished by utilizing an LPCVD process rather than by a furnace oxidation process. Such a process may be performed at a temperature in the range of 700 to 800°C, and may use a mixture of N 2 O and SiH 4 having a ratio in the range from 2:1 to 10:1, and may be performed at a pressure in the range from 100mTorr to 500mTorr. One notable advantage of this process is the ability to be performed in a conventional polysilicon deposition system. Further, the LPCVD oxidation may optionally be followed by either an RTP or furnace anneal. The tunnel oxidation may also be accomplished by utilizing an PECVD process rather than by a furnace oxidation process or by an LPCVD process. Such a process may also use a mixture of N 2 O and SiH 4 having a ratio in the range from 2:1 to 10:1, may be performed at a pressure in the range from 2 Torr to 30Torr, and may be performed at a power level in the range from 50-500 Watts. Since the energy required for dissociation of the N 2 O SiH 4 molecule is contained in the plasma, the process may be performed at a temperature in the range from room temperature (25°C) to 400°C. Further, the LPCVD oxidation may optionally be followed by either an RTP or furnace anneal. If the gate oxide is deposited, rather than grown, a much thinner oxide is achievable. For example, a 10-20Å gate oxide may be deposited, followed by a tunnel oxidation. This results in a gate oxide very similar in thickness to the tunnel oxide. Such a gate oxidation may be accomplished by either an LPCVD or PECVD process. The techniques thus described have far reaching implications for any oxidation cycle prior to polysilicon deposition for producing high quality, very thin oxides, and have tremendous potential application to most all MOS process technologies. It is believed that the techniques are particularly suited to improving the quality of deposited oxides and, as illustrated in the sequence of Fig. 1-6 in forming the gate oxide, for re-grown oxides. A deposited oxide is potentially useful for forming a tunnel oxide less than 50Å thick, rather than growing the oxide as discussed above. It is also believed that a concentration of nitrogen in the oxide provides a diffusion barrier to reduce the migration of dopant atoms, particularly boron, from an overlying polysilicon layer down through the oxide to the channel or substrate region below the oxide, which could degrade the performance of a device using the oxide (by significantly altering the doping profile of the substrate region). This diffusion barrier is particularly attractive when boron is present, because boron diffuses through oxide faster than either phosphorus or arsenic. A source of nitrogen in the oxide layer can be provided by the N 2 O anneal as described above, or alternatively by other gases, such as NO, NH 3 , NH 4 , or NF 3 , typically in combination with a source of oxygen, such as O 2 . Furthermore, the nitrogen can be introduced earlier in the oxidation process than during a final anneal. For example, it is believed that nitrogen may be introduced during the gettering operations, and yield an oxide having similar quality improvements as the oxides discussed above, even if the final anneal is only under an inert ambient, such as Argon. The nitrogen may also be introduced during some or all of the growth steps themselves, albeit requiring re-calibration of the optimal growth conditions necessary to yield an oxide of the desired thickness. While the above descriptions reference an EEPAL technology fabricated in a CMOS technology, the teachings of this disclosure can be advantageously applied to other semiconductor process technologies incorporating thin oxides. For example, a DRAM process requiring capacitors fabricated with very thin oxide dielectrics could benefit greatly from these teachings. Certainly other programmable technologies utilizing tunnel oxides are beneficiaries as well. While the invention has been described with respect to the embodiments set forth above, the invention is not necessarily limited to these embodiments. For example, the invention is not necessarily limited to any particular transistor process technology. Moreover, variations in certain of the process steps can be practiced. For example, a wide variety of gate oxide and tunnel oxide thickness may be produced, and whether to anneal and/or how to anneal the two oxides may be decided in a number of different ways. Accordingly, other embodiments, variations, and improvements not described herein are not necessarily excluded from the scope of the invention, which is defined by the appended claims. Throughout this application, the units of Torr may be converted to the SI unit (Pascal) by multiplying by 133.322. 1 Å is 1x10 -10 m.

Claims: A method of forming, in integrated circuit fabrication processes, a first oxide layer (220) upon a first surface region of a semiconductor body (100), and further for forming a second oxide layer (222), of greater thickness than the first oxide layer (220), upon a second surface region of the semiconductor body (100), comprising the steps of: i) forming an initial oxide layer (160) upon the first and second surface regions of the semiconductor body (100); ii) removing at least a portion of the initial oxide layer in a region disposed above the first surface region of the semiconductor body; iii) exposing, subsequent to the removing step, the semiconductor body to an environment suitable for oxide formation, to form a first oxide layer (220) disposed above the first surface region of the semiconductor body and to thicken the initial oxide layer disposed above the second surface region, thus forming the second oxide layer (222); and iv) introducing, subsequent to the commencement of the exposing step, the semiconductor body to a source of nitrogen, to form a concentration of nitrogen in both the first and second oxide layers; characterised in that said first oxide layer (220) has a thickness of less than 6nm (60Å) and in that the oxide formation step iii) is conducted at a temperature of 800°C or less and O 2 is applied at this temperature. A method as claimed in Claim 1 wherein the removing step comprises the complete removal of the initial oxide within the region disposed above the first surface region, thus exposing the first surface region of the semiconductor body. A method as claimed in Claim 1 wherein the removing step comprises the partial removal of the initial oxide within the region disposed above the first surface region, thus leaving a remaining portion of the initial oxide, of lesser thickness than its thickness at the completion of the forming step, disposed above the first surface region of the semiconductor body. A method as claimed in Claim 1 further comprising, subsequent to the removing step and prior to the exposing step, the additional step of thinning the initial oxide layer disposed above the second surface region of the semiconductor body. A method as claimed in Claim 1 wherein the initial oxide layer disposed above the second surface region of the semiconductor body is of a thickness, just prior to the exposing step, substantially unchanged as compared to its thickness at the completion of the forming step. A method as claimed in Claim 1 wherein the first surface region of the semiconductor body is disposed overlying a heavily-doped layer of the semiconductor body. A method as claimed in any one of Claims 1 to 6 wherein the forming step comprises an LPCVD, PECVD, RTP, or furnace oxidation process. A method as claimed in any one of Claims 1 to 7 wherein the exposing step comprises an LPCVD, PECVD, RTP or furnace oxidation process. A method as claimed in any one of Claims 1 to 8 wherein the introducing step comprises a PECVD, RTP or furnace process. A method as claimed in any one of Claims 1 to 9 wherein the introducing step comprises the step of annealing the semiconductor body, subsequent to the exposing step, under an ambient containing nitrogen, to form a surface layer in both the first and second oxides containing a concentration of nitrogen. A method as claimed in any one of Claims 1 to 9 further comprising, subsequent to the exposing and introducing steps, the step of annealing the semiconductor body. A method as claimed in any one of Claims 1 to 9 wherein the introducing step is performed simultaneously with the exposing step. wherein the environment suitable for oxide formation includes a source of nitrogen during at least a portion of the exposing step. to form a concentration of nitrogen in at least a portion of both the first and second oxides. A method as claimed in any one of Claims 10, 11 or 12 wherein the annealing step comprises an RTP or LPCVD annealing step and wherein the exposing step comprises a furnace growth step. A method as claimed in Claim 13 wherein the RTP or LPCVD annealing step is performed at a temperature in the range from 900°C to 1050°C. A method as claimed in Claim 12 or 13 wherein the exposing step is performed at a temperature in the range from 700°C to 800°C. A method as claimed in any one of Claims 13 to 15 wherein the annealing step is an LPCVD annealing step and is performed at a pressure in the range from 666-4000 Pa (5 torr to 30 torr). A method as in any one of Claims 1 to 16 wherein the exposing step is an LPCVD or PECVD exposing step and the environment suitable for oxidation comprises a mixture of N 2 O and SiH 4 having a ratio in the range from 2:1 to 10:1. A method as in Claim 17 wherein the exposing step is an LPCVD exposing step performed at a pressure of 13·3-66·6 Pa (100 mTorr to 500 mTorr); or a PECVD exposing step performed at a pressure of 266-4000 Pa (2 Torr to 30 Torr). A method as in Claim 17 or 18 wherein the exposing step is a PECVD exposing step and is performed at a temperature in the range from approximately 25°C to 400°C. A method as in Claim 17, 18 or 19 wherein the exposing step is a PECVD exposing step and is performed at a power level in the range from 50 W to 500 W. A method as in any one of Claims 1 to 16 wherein the environment suitable for oxide formation includes a source of HCI during at least a portion of the exposing step, to form a concentration of chlorine in at least a portion of both the first and second oxides. A method as in any one of Claims 1 to 16 wherein the environment suitable for oxide formation comprises an HCl-free environment during the exposing step, to form both the first and second oxides free from chlorine.

Inventors: FULFORD H JIM JR, GARDNER MARK I, FULFORD, H. JIM, JR., GARDNER, MARK, I.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES INC.
Application year: 1995
Main classification: H01L21
IPC codes: H01L29, H01L21