Pseudo-random number generator, and communication method and apparatus using encrypted text based upon pseudo-random numbers generated by said generator

Abstract: A communication apparatus through which encryption/decryption processing can be executed at high speed includes a CPU for performing overall control of the apparatus, an encryption unit for encrypting communication data that has been stored in a RAM and outputting encrypted data, and a decryption unit for decrypting encrypted data transmitted from an external communication apparatus and storing the decrypted data in the RAM. The decryption unit issues a request to generate a series of random numbers serving as an encryption key necessary in decryption processing of the encrypted data applied thereto. A pseudo-random number generating circuit generates random numbers and delivers them to the decryption unit. The encryption unit issues a request to generate a series of random numbers serving as an encryption key necessary in encryption. The pseudo-random number generating circuit generates random numbers and delivers them to the encryption unit. The latter generates a cryptogram sentence based upon these random numbers.

Description: This invention relates to a pseudo-random number generating method and apparatus using a method and apparatus for generating random numbers in communication, especially encrypted communication. More particularly, the invention relates to a pseudo-random number generating method and apparatus employed in information processing such as a Monte Carlo simulation. [Description of the Related Art] The rapid progress that has recently been made in information communication systems using computer networks has led to greater importance being attached to encryption techniques for the purpose of protecting the content of data. As for the random numbers used in encrypted communication, it is required that a series of random numbers to be generated from a certain point in time onward should not be readily understandable from a series of random numbers generated up to this point in time. JP-A-61-239328 refers to Advances in Cryptology, Proceedings of CRYPTO '82, p.61-78 published by the Plenum Press in 1983 as a reference describing a series of random numbers satisfying this condition as follows: Specifically, letting a series of random numbers be represented by {b 1 , b 2 , ···}, a bit b i is given by the following: b i = [least significant bit of x i ] (i = 1, 2, ···) where x i = x i-1 2 mod n (i = 1, 2, ···) x 0 : initial integer given arbitrarily by the user n = p·q, (p, q are prime numbers) In the above-cited reference, it is disclosed that b i+1 can be determined solely from b 1 , b 2 , ···, b i if one takes an amount of time equivalent to that which would needed to factorize n. Accordingly, in order to make factorization difficult, it is required that n = p·q be given a length of several hundred bits. A problem which arises in such case is that computing x 2 (mod n) takes too much time. The following technique utilizing the fact that n = p·q holds and employing the Chinese remainder theorem is known: x i = a·p·z i + b·q·y i (mod n) where y i = y i-1 2 mod p z i = z i-1 2 mod q y 0 , z 0 : initial integers given arbitrarily by the user a·p + b·q = 1 The Chinese remainder theorem is described, by way of example, in "Fugou Riron (Coding Theory)" (by Miyakawa, Iwatare, Imai), published by Shokodo . By using the Chinese remainder theorem, Equations 3 and 4 can be implemented by the four-rule operations of a number less than max(p,q), which is half the number of bits of n. This method is advantageous in that it is faster than the arithmetic operation of Equation 1 implemented by four-rule operations with the numbers less than n. Further, the specification of Japanese Patent Application Laid-Open (KOKAI) No. 61-239328 illustrates the following technique, in which the operation of Equation 2 is modified: x i = [a·(z i -y i ) (mod q)] · p + y i Equation 6 is established by substituting b·q of Equation 5 for that of Equation 2. Further, x i obtained from Equation 6 is smaller than n = p·q, as indicated by the following equation: 0 ≤ [a·(z i -y i ) (mod q)] · p + yi ≤ (q-1)·p + p - 1 = n - 1 Though Japanese Patent Application Laid-Open (KOKAI) No. 61-239328 illustrates that Equation 6 also is advantageous in that it can be implemented by four-rule operations with input of a number of less than max(p,q), n is an integer on the order of several hundred bits. Accordingly, even if the number is less than max(p,q), computation of a large integer is necessary, computation time is prolonged and the scale of processing circuitry is increased. According to the present invention there is disclosed a pseudo-random number generator for generating a random number X i , i = 0, 1, 2, ..., n, comprising: y i operating means operable to output y i , i = 0, 1, 2, ..., n, upon performing an operation of a recurrence formula "y i = f(y i-1 ) mod p; i = 1, 2, ..., n-1", based upon a prescribed initial value y 0 , a prescribed prime number p and a function f(y i-1 ) of y i-1 ; z i operating means operable to output z i , i = 0, 1, 2, ..., n upon performing an operation of a recurrence formula "z i = g(z i-1 ) mod q; i = 1, 2, ..., n-1", based upon a prescribed initial value z o , a prescribed prime number q and a function g(z i-1 ) of z i-1 ; and calculating means operable to calculate the lowest order bit of X i in accordance with a remainder formula "X i = [a. (z i - y i ) mod q].p + y i " based upon a prescribed coefficient "a" and the prescribed prime number q; characterised in that the calculating means comprises: m i operating means operable to extract prescribed lower order bits out of m i i = 0, 1, 2, ..., n, upon performing an operation of a remainder formula "m i = a.(z i - y i ) mod q"; and prescribed bit operating means operable to multiply said prescribed lower order bits extracted from m i and prescribed lower order bits extracted from the prescribed prime number p, to add prescribed lower order bits of y i to prescribed lower order bits of a result of multiplication and to adopt prescribed lower order bits of a result of addition as an i-th pseudo-random number X i , i = 0, 1, 2, ..., n, wherein the number of prescribed lower order bits is smaller than the full bit length. An advantage of the present invention is to provide a method and apparatus through which pseudo-random numbers can be generated at high speed. A further advantage of the present invention is to provide a communication method and apparatus through which encryption/decryption processing can be executed at high speed. Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Fig. 1 is a diagram for describing the construction of a pseudo-random number generating circuit according to a first embodiment of the present invention; Fig. 2 is a diagram for describing the construction of a pseudo-random number generating circuit according to a second embodiment of the present invention; Fig. 3 is a diagram for describing the construction of a pseudo-random number generating circuit according to a third embodiment of the present invention; Fig. 4 is a diagram for describing the construction of a pseudo-random number generating circuit according to a fourth embodiment of the present invention; Fig. 5 is a diagram for describing the construction of a communication apparatus according to a sixth embodiment of the invention; and Fig. 6 is a diagram for describing the network connection of the communication apparatus according to the sixth embodiment. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. [Overview of the Invention] The embodiments of the invention provide a high-speed arithmetic method and apparatus for obtaining a random-number series b i (i = 1, 2, ···) through an operation with the numbers sufficiently smaller than max(p,q) in order to solve the aforementioned problems, as well as a communication method and apparatus for performing encrypted communication processing at high speed using the high-speed arithmetic method and apparatus. Each of the random-number series b i (i = 1, 2, ···) obtained is the least significant bit of x i , respectively, as mentioned above. When xi is computed by Equation 1, all bits of x i are necessary to compute the next x i+1 . When x i is computed by Equation 2 or 6, however, x i is unrelated to computation of x i+1 . However, all bits of y i , z i are required to compute y i+1 , z i+1 for generation of x i+1 . Accordingly, it is not required that the operation of Equation 2 or 6 be carried out with respect to all bits of x i , and it will suffice to perform the computation of the least significant bit in the following manner: b i = c·d + e where c: least significant bit of m = [a·(z i -y i )(mod q)] d: least significant bit of p e: least significant bit of y i + exclusive-OR operator It is known that the random-number series b i need not consist of just the least significant bit of x i , and that if the series b i consist of lower order bits of x i where the number of lower order bits is on the order of log 2 n, the stability of the random-number series b i will not change. In this case, c, d and e can each be a plurality of bits and not the least significant bit, but it is clear that the operation involved will be sufficiently small in comparison with max(p,q). [First Embodiment] Fig. 1 illustrates the construction of a pseudo-random number generator 10 according to a first embodiment of the invention. The generator 10 basically performs the operation of Equation 8 above. As shown in Fig. 1, the generator 10 includes selectors S1, S2 and registers R1, R2. The selectors S1, S2 select y 0 , z 0 , respectively, which are applied in the initial state, and store y 0 , z 0 in the registers R1, R2, respectively. Following the initial state, the outputs of remainder squaring circuits Q1, Q2, described below, are selected and stored in the registers R1, R2, respectively. Using the above-mentioned prime numbers p, q, the remainder squaring circuits Q1, Q2 perform the following operations with respect to integers y i-1 , z i-1 being stored in the registers R1, R2, respectively: y i = y i-1 2 (mod p) z i = y i-1 2 (mod q) The generator 10 further includes a subtracting circuit Subl and a remainder multiplying circuit M1. The subtracting circuit Sub1 computes z i -y i from its inputs y i , z i , and the remainder multiplying circuit M1 performs the operation m = a·(z i -y i ) (mod q) The output from the remainder multiplying circuit M1 need be only the least significant bit c of m and not all bits. AND1 represents a one-bit AND gate, and EXOR1 denotes a one-bit ex-OR gate. The AND gate AND1 takes the logical product of the least significant bit c of m and the least significant bit d of p, and the ex-OR gate EXOR1 takes the exclusive-OR of this output of the gate AND1 and the least significant bit e of y i , with the result of this operation being outputted as the random number b i . [Second Embodiment] Fig. 2 illustrates the construction of a pseudo-random number generator 20 according to a second embodiment of the invention. The generator 20 basically performs the operation of Equation 8 above. In Fig. 2, selectors S3, S4 select y 0 , z 0 , respectively, which are applied in the initial state. Following the initial state, the selectors S3, S4 select the outputs of register R4 and remainder squaring circuit Q3, respectively. The selected outputs are stored in registers R3, R4, respectively. The remainder squaring circuit Q3 squares its input value, divides the resulting value by p or q and then outputs the remainder. Here p and q are alternated, starting with p. In other words, p and q are entered into the remainder squaring circuit Q3 in alternating fashion. Processing from a subtracting circuit Sub2 onward is executed only at the moment the remainder squaring circuit Q3 uses p. The reason for this is that y i , z i are stored in the registers R3, R4 immediately before this point in time. The processing from a subtracting circuit Sub2 onward is similar to that of the first embodiment. That is, the subtracting circuit Sub2 computes z i -y i from its inputs y i , z i , and a remainder multiplying circuit M2 performs the operation m = a·(z i -y i ) (mod q) The output from the remainder multiplying circuit M2 need be only the least significant bit c of m and not all bits. AND2 represents a one-bit AND gate, and EXOR2 denotes a one-bit ex-OR gate. The AND gate AND2 takes the logical product of the least significant bit c of m and the least significant bit d of p, and the ex-OR gate EXOR2 takes the exclusive-OR of this output and the least significant bit e of y i , with the result of this operation being outputted as the random number b i . [Third Embodiment] It is known that b i need not be just the least significant bit; if the number of bits is on the order of log 2 n, the stability of the random number b i will not decline even when a plurality of lower bits of x i are used as b i . Accordingly, if we take u bits from the least significant place of x i , Equation 8 becomes as follows: b i = c·d + e where c: value of u bits from least significant place of m = [a·(z i -y i ) (mod q)] d: value of u bits from least significant place of p e: value of u bits from least significant place of y i +: logical addition operator Accordingly, Equation 8" is an operation involving a plurality of bits, but it is clear that the operation is sufficiently small in comparison with max(p,q). The pseudo-random number generator of the third embodiment basically can be implemented by performing a simple extension of the operational bits in the first embodiment described in connection with Fig. 1. Fig. 3 illustrates the construction of a pseudo-random number generator 30 according to the third embodiment of the invention. A comparison with Fig. 1 shows that the construction of the generator is identical up to the subtracting circuit Sub1 and has different components following the subtracting circuit Subl. Only the different components will be described. The output of the computation "z i -y i " from the subtracting circuit Sub1 in Fig. 3 enters a remainder multiplying circuit M3, and so do q and a. After the remainder multiplying circuit M3 performs the operation m = a·(z i -y i ) (mod q) u bits are extracted from the least significant bit of m, which is the result of the operation, and this is entered into a multiplying circuit MUL1. Further, "d", which is u bits from the least significant bit of p, is entered into the multiplying circuit MUL1 simultaneously. The multiplying circuit MUL1 performs the multiplication (u bits) x (u bits) and enters the lower order u bits of the product into an adder ADD1. The latter, to which e is simultaneously applied as an input, adds e to the value of the lower order u bits of the result of multiplication. The lower order u bits of the resulting sum is outputted as the random number b i . [Fourth Embodiment] The pseudo-random number generator of the fourth embodiment basically can be implemented by performing a simple extension of the operational bits in the second embodiment described in connection with Fig. 2. Fig. 4 illustrates the construction of a pseudo-random number generator 40 according to the fourth embodiment of the invention. A comparison with Fig. 2 shows that the construction of the generator is identical up to the subtracting circuit Sub2 and has different components following the subtracting circuit Sub2. Only the different components will be described. The result of the computation "z i -y i " output from the subtracting circuit Sub2 in Fig. 4 enters a remainder multiplying circuit M3, and so do q and a. After the remainder multiplying circuit M3 performs the operation m = a·(z i -y i ) (mod q) u bits are extracted from the least significant bit of m, which is the result of the operation, and this is entered into a multiplying circuit MUL1. Further, "d", which is u bits from the least significant bit of p, is entered into the multiplying circuit MUL1 simultaneously. The multiplying circuit MUL1 performs the multiplication (u bits) x (u bits) and enters the lower order u bits of the product into an adder ADD1. The latter, to which e is simultaneously applied as an input, adds e to the value of the lower order u bits of the result of multiplication. The lower order u bits of the resulting sum is outputted as the random number b i . [Fifth Embodiment] In the foregoing embodiments, the output is identical even if p and q are interchanged. Further, in the foregoing embodiments, an example is described in which random numbers are generated using the polynomial y i = y i-1 2 . However, it goes without saying that the invention is not limited solely to y i = y i-1 2 because the other polynomials more than quadratic which has the form y i = f(y i-1 ) can also be used. Further, in the foregoing embodiments, circuit arrangements are described in which a series of pseudo-random numbers is generated at high speed based upon Equation 8 and Equation 8''. However, in accordance with the embodiments of the invention, as opposed to the prior art, Equations 8 and 8'' can be implemented by an integral operation which is sufficiently small in comparison with max(p,q). It goes without saying that these operations can be readily implemented even by executing software using a CPU or the like. For example, in a case where n is an integer of 512 bits, u may be on the order of "log 2 n", i.e., nine bits. Further, in a case where encrypted communication is performed wherein a part of information is concealed as by using the Chinese remainder theorem in RSA encryption processing of the kind illustrated in "Gendai Angou Riron (Modern Encryption Theory)" (by Nobuichi Ikeno and Kenji Koyama), published by Denshinjoho Tsushin Gakkai , it is obvious that this embodiment of the invention can be applied to greatly reduce the amount of computation by calculation solely of the necessary portions. [Sixth Embodiment] The focus of the invention has been on a method and apparatus for generating pseudo-random numbers in which the processing for generating pseudo-random numbers is executed at high speed. In the sixth embodiment, reference is had to Fig. 5 to describe an example of a communication apparatus (1120) for encrypting and decrypting communication data, which uses this method and apparatus for generating pseudo-random numbers. Fig. 6 illustrates the construction of an n to n communication system 302 based upon the communication apparatus 1120 of the sixth embodiment. A connection 301 in Fig. 6 represents a local communication network such as a local area network (LAN) or wide area communication network such as a telephone line. Further, A ∼ Z represent users of the respective communication apparatus 1120. Users employing these items of communication equipment or terminals are capable of communicating with other users by performing various operations including the above-described pseudo-random number generation processing using the method and apparatus for generating pseudo-random numbers of the embodiments of this invention. The construction of the communication apparatus 1120 of the sixth embodiment will be described with reference to Fig. 5. A CPU 1121 performs overall control of the communication apparatus 1120. The control program is stored in a ROM 1124 in advance and is executed by the CPU 1121. A keyboard 1122 serves as an input terminal for entering command and data into the communication apparatus 1120. A RAM 1123 stores communication data as well as working data which the CPU 1121 uses to execute various types of processing. A monitor 1125 displays the results of various processing in the communication apparatus 1120, communication data and input commands from the keyboard 1122. An encryption unit 1127 executes encryption processing of communication data stored in the RAM 1123 and outputs encrypted data on a communication line 1129. A decryption unit 1126 decrypts encrypted data, which is transmitted from an external communication apparatus via a communication line 1128, and stores the decrypted data in the RAM 1123. Numeral 200 denotes any one of the circuits for generating pseudo-random numbers described in Figs. 1 ∼ 4. The circuit 200 generates a series of random numbers as an encryption key on the basis of a request from the encryption unit 1127 or decryption unit 1126. The decryption unit 1126 requests that the circuit 200 generate a series of random numbers as an decryption key necessary for decryption processing of entered encrypted data. The generated series of random numbers enters the decryption unit 1126, which subjects the entered encrypted data to decryption processing using the series of random numbers as a decryption key, thereby producing a plain text. Further, when the encryption unit 1127 performs encryption processing of communication data, it requests the circuit 200 to execute processing for generating a series of random numbers as an encryption key and receives the generated series of random numbers as an input. The encryption unit 1127 then proceeds to use this series of random numbers as an encryption key to subject communication data, which is a plain text, to encryption processing, thereby generating a cryptogram. It will suffice to adapt the encryption processing performed by the encryption unit 1127 so as to obtain encrypted data {c i } by performing a bit-by-bit exclusive-OR operation c i = m i + b i between communication data {m i } and a random-number series {b i } from the pseudo-random number generating circuit 200, in which the communication data {m i } is the result of separating communication data bit by bit. In this case, in the decryption processing performed by the decryption unit 1126, a random-number series {b i } identical with the random-number series used in the encryption processing is generated by the pseudo-random number generating circuit 200 based on the same initial value, and the communication data {m i } is obtained by a bit-by-bit exclusive-OR operation m i = c i + b i between the received communication data {c i } and a random-number series {b i }. No stability-related problem arises in the foregoing even if the items of communication data {m i } and random-number series {b i } are made a plurality of bits on the order of log 2 n rather than one bit. As a consequence of the above encryption/decryption processing, the encryption unit 1127 and decryption unit 1126 can each be implemented by an exclusive-OR circuit. Further, the encryption unit 1127 and decryption unit 1126 can share the same exclusive-OR circuit, in which case the input/output of the circuit would be changed over depending upon whether the operation is encryption or decryption. Thus, as described above, the method and apparatus for generating pseudo-random numbers of the embodiments are used when encryption/decryption processing is executed, thereby making it possible to execute encryption/decryption processing at high speed. This in turn makes it possible to raise the overall processing performance of communication processing. Encryption/decryption processing between communication apparatus is described in the sixth embodiment. However, encryption/decryption processing between an information processing apparatus and a recording medium can be executed in a similar manner. An example of the recording medium is a magnetic recording medium such as a hard disk or floppy disk. In such case the apparatus for accessing the recording medium would correspond to the communication apparatus. The present invention can be applied to a system constituted by a plurality of devices or to an apparatus comprising a single device. Furthermore, it goes without saying that the invention is applicable also to a case where the object of the invention is attained by supplying a program to a system or apparatus. Though the invention has been described above in relation to a communication method and apparatus, it goes without saying that the method and apparatus for generating pseudo-random numbers according to the embodiments can be used also in processing performed by an image processing apparatus and especially in information processing such as a Monte Carlo simulation. In accordance with the present invention, as described above, encryption/decryption processing of data can be executed at high speed. In addition, pseudo-random numbers can he qenerated at high speed. It is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims. Of course it will be understood that the phrase "plain text" employed in the above description and the claims to define the data for encryption and decryption is in no way limited as to the type of information that can be encrypted. Thus, for example, the phrase "plain text" should be read as encompassing encoded images, sound, computer language and any other type of data, in addition to written natural language.

Claims: A pseudo-random number generator (10, 20, 30, 40) for generating a random number X i , i = 0, 1, 2, ..., n, comprising: y i operating means (S1, R1, Q1; S3, R3, Q3; S4, R4) operable to output y i , i = 0, 1, 2, ..., n, upon performing an operation of a recurrence formula y i = f(y i-1 ) mod p; i = 1, 2, ..., n-1 based upon a prescribed initial value y 0 , a prescribed prime number p and a function f(y i-1 ) of y i-1 ; z i operating means (S2, R2, Q2; S3, R3, Q3; S4, R4) operable to output z i , i = 0, 1, 2, ..., n upon performing an operation of a recurrence formula z i = g(z i-1 ) mod q; i = 1, 2, ..., n-1, based upon a prescribed initial value z o , a prescribed prime number q and a function g(z i-1 ) of z i-1 ; and calculating means (Sub1, M1 AND1, EXOR1; Sub2, M2, AND2, EXOR2, M3, MUL1, ADD1) operable to calculate the lowest order bit of X i in accordance with a remainder formula X i = [a. (z i - y i ) mod q].p + y i based upon a prescribed coefficient a and the prescribed prime number q; characterised in that the calculating means comprises: m i operating means (Sub1, M1; Sub2, M2; M3) operable to extract prescribed lower order bits out of m i , i = 0, 1, 2, ..., n upon performing an operation of a remainder formula m i = a.(z i - y i ) mod q; and prescribed bit operating means (AND1, EXOR1; AND2, EXOR2; MUL1, ADD1) operable to multiply said prescribed lower order bits extracted from m i and prescribed lower order bits extracted from the prescribed prime number p, to add prescribed lower order bits of y i to prescribed lower order bits of a result of multiplication and to adopt prescribed lower order bits of a result of addition as an i-th pseudo-random number X i , i = 0, 1, 2, ..., n, wherein the number of prescribed lower order bits is smaller than the full bit length. The pseudo-random number generator according to claim 1, wherein said function f(y i-1 ) is a polynomial related to y i-1 , and said function g(z i-1 ) is a polynomial related to z i-1 . The pseudo-random number generator according to claim 1, wherein said function f(y i-1 ) is a polynomial which is the square of y i-1 , and said function g(z i-1 ) is a polynomial which is the square of z i-1 . A pseudo-random number generator as claimed in any of claims i to 3, wherein the number of prescribed lower order bits is less than a number of bits in the vicinity of log 2 p.q bits. A pseudo-random number generator as claimed in claim 4, wherein the number of prescribed lower order bits is one. A communication apparatus (1120) including a generator (200) according to any preceding claim comprising: encryption means (1127) operable to generate a cryptogram from a plain text on the basis of the pseudo-random number X i , i = 0, 1, 2, ..., n, generated by said generator; and output means (301) for outputting the cryptogram. A communication apparatus (1120) including a generator (200) according to any one of claims 1 to 5, comprising: decryption means (1126) operable to generate a plain text from a received cryptogram on the basis of the pseudo-random number X i , i = 0, 1, 2, ..., n generated by the generator. A pseudo-random number generating method for generating a random number X i , i = 0, 1, 2, ..., n, comprising the steps of: outputting y i , i = 0, 1, 2, ..., n, upon performing an operation of a recurrence formula y i = f(y i-1 ) mod p; i = 1, 2, ..., n-1, based upon a prescribed initial value y 0 , a prescribed prime number p and a function f(y i-1 ) of y i-1 ; outputting z i i = 0, 1, 2, ..., n, upon performing an operation of a recurrence formula z i = g(z i-1 ) mod q; i = 1, 2, ..., n-1, based upon a prescribed initial value z 0 , a prescribed prime number q and a function g(z i-1 ) of z i-1 ; and calculating the lowest order bit of X i in accordance with a remainder formula X i = [a.(z i - y i ) mod q].p + y i based upon a prescribed coefficient a and the prescribed prime number q; characterised by the calculating step further comprising the steps of: extracting prescribed lower order bits out of m i , i = 0, 1, 2, ..., n, upon performing an operation of a remainder formula m i = a.(z i - y i ) mod q; and multiplying said prescribed lower order bits extracted from m i and prescribed lower order bits extracted from the prescribed prime number p, adding prescribed lower order bits of y i to prescribed lower order bits of a result of said multiplying step and adopting prescribed lower order bits of a result of addition as an i-th pseudo-random number X i , i = 0, 1, 2, n, wherein the number of prescribed lower order bits is smaller than the full bit length. The method according to claim 8, wherein said function f(y i-1 ) is a polynomial related to y i-1 , and said function g(z i-1 ) is a polynomial related to z i-1 . The method according to claim 8, wherein said function f(y i-1 ) is a polynomial which is the square of y i-1 , and said function g(z i-1 ) is a polynomial which is the square of z i-1 . The method according to claim 8, wherein the number of prescribed lower order bits is less than a number of bits in the vicinity of log 2 p.q bits. The method according to claim 11, wherein the number of prescribed lower order bits is one. A communication method including said generating method according to any one of claims 8 to 12, comprising the steps of: generating a cryptogram from a plain text on the basis of the pseudo-random number X i , i = 0, 1, 2, ..., n, generated in said generating method; and outputting the cryptogram. A communication method including said generating method according to any one of claims 8 to 12, comprising the steps of: generating a plain text from a received cryptogram on the basis of the pseudo-random number X i , i = 0, 1, 2, ..., n, generated in said generating method.

Inventors: IWAMURA KEIICHI, YAMAMOTO TAKAHISA, IWAMURA, KEIICHI, YAMAMOTO, TAKAHISA, IWAMURA, KEIICHI, C/O CANON KABUSHIKI KAISHA, YAMAMOTO, TAKAHISA, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1995
Main classification: H04L9
IPC codes: G09C1, H04L9