Trenched DMOS transistor fabrication using seven masks

Abstract: A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

Description: This application is related to commonly owned U.S. Patent No. 5,316,959, entitled "Trenched DMOS Transistor Fabrication Using Six Masks", issued May 31, 1994. This invention relates to a method for fabricating a trenched DMOS transistor using e.g. seven masking steps, resulting in a transistor having narrow trenches, shallow diffusions, and formed using relatively few process steps, and having a thick dielectric layer in the termination region. DMOS transistors are well known as a type of MOSFET (metal on semiconductor field effect transistor) using diffusions to form the transistor regions, with a typical application being as a power transistor. Such devices enjoy widespread use in such applications as automobile electrical systems, power supplies, and power management applications. Many different processes have been used for the fabrication of power MOSFET devices over the years; these are generally deep diffusion processes. It is also well known to form such transistors having a trench in the substrate, the trench being lined with a thin oxide layer and filled with a conductive polysilicon to form the transistor gate structure. Prior art trenched DMOS transistors have the shortcoming that typically it takes a fairly large number (such as eight or nine) fabrication masking steps to define the various transistor regions, including the tubs in which the active transistor regions are formed, the body region of the transistor, the source region of the transistor, the body contact regions, each of which are separate diffusions, and the termination structures, i.e. field plates and field rings. Additional masking steps define the oxide layers and polysilicon portions of the transistor. Each additional masking step requires a mask alignment and thus results in the possibility of alignment error, undesirably reducing yield. Additionally, the many process steps which include temperature cycles tend to result in unwanted diffusion of certain of the implanted ions, thus undesirably altering the lateral extent and/or depth of various of the diffused regions. Thus there is a need for transistor fabrication processes using relatively few masks. The process and resulting transistor structure of the above-referenced patent provide the same oxide (dielectric) layer thickness in the active (gate) region of the transistor as in the termination (edge) portion of the transistor. This has been found to be somewhat disadvantageous because breakdown instability is observed probably due to the charging effect from the passivation layer and floating gate. In accordance with the invention there is provided a method for forming a field effect transistor as defined in claim 1. In accordance with one embodiment, a trenched DMOS transistor has relatively narrow and shallow trenches with relatively shallow associated transistor active regions. By using an additional masking step to expose the principle surface of the substrate in the termination region of the transistor prior to growing the thick field oxide, a field oxide dielectric layer is provided in the termination region which is relatively thicker than the gate oxide in the active portions of the transistor. Advantageously the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable. Furthermore, process control is improved due to this thicker oxide. Additionally, thicker oxide in the termination region prevents dopant or ionic contamination of the underlying substrate from the overlying layers, thereby reducing leakage current problems in the termination region. In one embodiment, in addition to the thick field oxide in the termination region, also present in the termination region is a field plate which is electrically connected to a guard ring by a metallized contact and shorted to the source region in the transistor active region. Figures 1a through 1k show in cross section a sequence of steps to form a transistor in accordance with the present invention. The present invention is to be understood in the context of two commonly owned other disclosures, both incorporated herein by reference. The first of these is U.S. Patent No. 5,304,831, entitled "Low On-Resistance Power MOS Technology", inventors Hamza Yilmaz et al., which discloses a method for fabricating a DMOS transistor using five masking steps. The second is U.S. Patent Application Serial No. 07/918,996, filed July 23, 1993 entitled "Field Effect Transistor Having Edge Termination Utilizing Trench Technology", inventor Izak Bencuya, attorney docket number M-2140. A process in accordance with the invention and using seven masking steps is described hereinafter. It is to be understood that the reference herein to "seven masking masking steps" is illustrative and not limiting; other processes with other numbers of masking steps are also in accordance with the present invention. In Figure 1a an N-channel process in accordance with the invention uses an N- doped epitaxial layer 100 having a resistivity of for example 0.20 to 2.0 ohm-cm formed on a conventional N+ doped silicon substrate (not shown), the layer 100 having a resistivity of for example 0.001 to 0.010 ohm-cm and being 5 to 15 microns (micrometers) thick. The substrate is about 500 µm thick. A thin layer of silicon dioxide 102 is thermally grown 300Å to 500Å thick on the principal surface of the epitaxial layer 100, and a mask layer of silicon nitride 104 having a thickness of from 100Å to 2000Å is deposited thereon. Mask layer 104 is conventionally patterned and etched. Then boron is predeposited by using the boron nitride process or by implanting boron at an energy of 30 to 60 KeV and a dose of 2 x 10 13 to 1 x 10 16 /cm 2 through the mask layer 104 and driven in to form P+ deep body regions 106, 108 which are about 2 to 3 microns deep and having a final concentration at the principal surface of 1 x 10 16 to 2 x 10 19 /cm 3 , and similar P+ field rings (termination structures) 110, 112, 114. Then in Figure 1b, an additional mask is used to pattern mask layer 104 in the termination region 116, exposing the relatively thin gate oxide layer 102. This additional masking step is an improvement herein over the method disclosed in the above referenced Patent No. 5,316,959. Then local oxidation (LOCOS) 118 of silicon to a thickness of 5,000 to 8,000Å in Figure 1c to grow the thicker field oxide layer is followed by stripping of the nitride mask layer 104 to define both the active transistor cells and the device termination portion. (It is to be understood that in Figures 1a to 1k, the device termination region is located at the right hand side of the figures and the central active cell portion of the transistor is at the left hand portion of the figures. Also, the process steps are shown schematically and not to scale.) As shown in Figure 1c, thick field oxide layer 118 extends over termination region 116. Then in Figure 1d an LTO (low temperature oxide) second mask layer (not shown) is conventionally deposited and patterned, and trenches 120, 122, 124, 126 are each formed by anisotropic reactive ion dry etching to a depth of 1.5 to 3 microns and a width of 1 to 2 microns. Trenches 120, 122, 124 serve as the gate electrode trenches and trenches 124, 126 separate the field rings from adjacent structures. After the trench walls and corners are smoothed by an isotropic plasma "round hole" etch and a sacrificial oxide growth and subsequent stripping of the sacrificial oxide, the gate oxide layer 130 is conventionally grown on the sidewalls of the trenches 120, 122, ..., 126 to a thickness of 100 to 1000Å. Then in Figure 1e the trenches are planarized by the deposition of a layer of polycrystalline silicon 132 which is at least as thick as the width of each trench. This relatively thick polysilicon layer 132 is partially dry etched away (without a mask) leaving a thickness of 0.5 microns. By protecting the principal surface with photo resist (not shown), the substrate back side polysilicon and oxide layers are removed by wet chemical etch. The remaining polysilicon 132 is then doped to a conductivity less than 2 ohm/square. Then masking of polysilicon 132 and a second polysilicon "defreckable" etching is performed, resulting in the structure of Figure 1e defining windows for subsequent processing. The use of the LOCOS oxide process eliminates the prior art "poly stringer" problem by reducing the oxide step height. This is followed in Figure 1f by a blanket boron P- body implant and diffusion at an energy of about 60 KeV and dose of 2 x 10 13 to 5 x 10 13 /cm 2 , providing a final surface concentration of about 2 x 10 17 /cm 3 forming body regions 134, 136, 138. Then a blanket N+ arsenic source implant and diffusion are performed at an energy of 60 to 120 KeV at a dosage of 1 x 10 15 to 1 x 10 16 /cm 2 to achieve a final surface concentration of 5 x 10 19 /cm 3 in Figure 1g forming N+ source regions 140, 142. The N+ source regions 140, 142 depth is about 0.5 microns. Then in Figure 1h a layer of boro-phosphorsilicate glass (BPSG) 146 is conventionally deposited to a thickness of about 1.35 microns over the entire structure. Then in Figure 1i BPSG layer 146 is masked and patterned to define the electrical contact openings 150, 152, 154, 156 to the transistor structure. Also, opening 158 in the termination region BPSG layer 146 is formed in this step. The BPSG layer 140 is then conventionally reflowed to smooth its corners. Then in Figure 1j a layer of metal 160 (e.g. aluminum or aluminum plus 1% silicon) is deposited over the entire structure, such as by sputtering and then etched using a conventional patterned mask layer. Then in Figure 1k a passivation layer 162 such as PSG or plasma nitride is conventionally deposited and by a mask step, bonding pad openings (not shown) to contact the gate and source area are opened therethrough. In contrast to the final structure disclosed in the above-referenced U.S. Patent No. 5,316,959, here the thick field oxide layer 118 extends to the edge of the termination region at the right side of Figure 1k, providing the above-described benefits. Also, here the P+ doped region 114 is contacted by overlying metal contact 160c. The resulting termination structure is a P+ guard ring 114 electrically connected to polysilicon plate 132b via contact 160c and to the transistor source regions. The polysilicon field plate 132b improves breakdown voltage in the termination region by smoothing the electric field distribution near the P+/N junction in the termination region. As will be recognized, seven masking steps are thereby utilized in one embodiment of the fabrication process described in Figures 1a to 1j of the present invention. These seven masking steps are as follows: 1) a deep body P+ masking step in which openings are formed in layer 102 as shown in Figure 1a through which P+ regions are doped; 2) a termination region mask patterning step in which an additional opening is formed in mask layer 104 for growing LOCOS oxide layer 118 over the termination region 116 shown in Figure 1b; 3) a trench masking step in which a layer of photoresist is patterned to define the trenches 120, ..., 126 shown in Figure 1d; 4) a polysilicon masking step in which a layer of photoresist is used to protect and thereby to define the portions of polysilicon layer 132 shown in Figure 1e; 5) a contact opening masking step in which portions of a BPSG layer 146 are removed to define a contact to the P+ regions and to define a contact to the doped polysilicon in trench 124 of Figure 1i. 6) a metal masking step in which portions of a metal layer 160 are removed to define the metal source electrode 160(a), the metal gate finger 160(b), and the guard ring contact 160c of Figure 1j; and 7) a conventional pad masking step in which portions of passivation layer 162 are removed to expose a gate bonding pad and source bonding pad. It is to be understood that the above-described process is for fabricating an N-channel vertical DMOS transistor device as shown. By reversal of the various semiconductor region doping types the opposite type, a P-channel vertical DMOS transistor structure may also be formed. With reference to the structure of Figure 1k, the field rings 112, 114 are separated by insulated trench 126, thus allowing the field rings to be closely spaced together and hence conserving chip surface area. Trench 126 is filled with doped polysilicon. Trench 124 is also filled with polysilicon and is electrically connected to the gate finger electrode connected in turn (outside the plane of Fig. 1j) to the doped polysilicon which fills trenches 120, 122. The drain electrode is conventionally formed on the back side (not shown) of the substrate. The area immediately to the right of trench 122 has no active (source or body) regions and hence serves as a dummy cell adjacent to the termination structures; this dummy cell can be dispensed with in one embodiment. Also, the above described process can be implemented in a transistor having a termination other than that described herein. The above description is illustrative and not limiting; further modifications will be apparent to one skilled in the art in light of this specification.

Claims: A method for forming a field effect transistor comprising: a) providing a semiconductor substrate (100) having a principal surface and being of a first conductivity type; b) forming a patterned mask layer (104) on the principal surface; c) doping semiconductor regions of a second conductivity type, opposite to the first conductivity type, in portions of the substrate (100) exposed by the patterned mask layer (104), thereby forming regions of a second conductivity type including deep body regions (106, 108) in an active portion of the field effect transistor, and a termination structure (114); d) forming an additional opening in the patterned mask layer (104) in a termination region (116), the termination region being located at the principal surface adjacent and in direct contact with the termination structure (114); e) locally oxidising portions of the principal surface exposed by the patterned mask layer (104) to form an oxide layer (118) after step d; f) forming a plurality of trenches (120, 122, 124, 126) in the substrate (100) between the semiconductor regions (106,108) of the second conductivity type; g) removing the patterned mask layer (104); h) forming a conductive polysilicon layer (132) over the structure obtained in the removing step g) and in the trenches (120, 122, 124, 126); i) patterning the conductive polysilicon layer (132) to form a gate of the field effect transistor in at least one of the trenches and a field plate (132b) on a section of the oxide layer (118) which extends over the termination structure (114) and the termination region (116); j) forming first and second doped regions of the second and first conductivity type respectively, the first and second doped regions extending from the exposed portions of the principal surface, the first and second doped regions respectively being body and source regions in the active portion of the field effect transistor; k) forming a patterned insulating layer (146) on the structure obtained in step j); l) forming a patterned interconnect layer (160a, 160b, 160c) on the structure obtained in step k); the patterned interconnect layer contacting the deep body, the body, and the source regions, the gate electrode, and electrically interconnecting the field plate (132b) and the termination structure (114). A field effect transistor comprising: a) a semiconductor substrate (100) having a principal surface and being of a first conductivity type; b) a plurality of semiconductor regions (106,108,110,112,114) being of a second conductivity type opposite to said first conductivity type, the plurality of semiconductor regions being spaced apart and extending from the principal surface into the semiconductor substrate, the plurality of semiconductor regions being deep body regions (106, 108) of the field effect transistor in an active portion of the field effect transistor and a termination structure (114); c) a patterned oxide layer (118) comprised of a plurality of oxide sections positioned on the plurality of semiconduction regions while the oxide section on the termination structure extends over a termination region which termination region is located at the principal surface adjacent and In direct contact with the termination structure; d) a plurality of trenches (120, 122, 124, 126) extending into the semiconductor substrate from the principal surface while being positioned between the plurality of semiconductor regions; e) a patterned conductive polysilicon layer (132) comprising first polysilicon sections within the plurality of trenches and a second polysilicon section which extends over the termination structure and the termination region, one of the polysilicon sections being a gate of the field effect transistor, the second polysilicon section being a field plate (132b); f) first and second doped regions (136, 134) of the second and first conductivity type respectively extending into the substrate from the principal surface adjacent to at least some of the trenches, the first and second doped regions respectively being body and source regions in the active portion of the field effect transistor; f) a patterned insulating layer (146) over the patterned polysilicon layer; and g) a patterned interconnect layer (160a, 160b, 160c) over the patterned insulating layer, the patterned interconnect layer contacting the deep body, source regions, the gate electrode, and electrically interconnecting the field plate and the termination structure. The transistor of claim 2, wherein the patterned oxide layer (118) has a thickness of between 5000 and 8000 Å.

Inventors: CHANG MIKE F, HO YUEH-SE, HSHIEH FWU-IUAN, OWYANG KING, CHANG, MIKE F., HO, YUEH-SE, HSHIEH, FWU-IUAN, OWYANG, KING
Applicants: SILICONIX INC, SILICONIX INCORPORATED
Application year: 1995
Main classification: H01L21
IPC codes: H01L21, H01L29