Decoding of Huffman Codes with MSB and LSB look-up tables

Abstract: A variable length decoder for decoding a variable length code. The variable length decoder includes a shifter for receiving a q-bit data input word and for extracting an m-bit fixed-length word. The m-bit fixed-length word contains the variable length code value and a code length code value where m and q are integers and m is less than or equal to q. A code length conversion table is also provided for receiving p bits of the m-bit fixed-length word. The code length code value is held in the p bits where p is an integer and less than m. The code length conversion table produces a decoded code length value. The shifter also produces a next m-bit fixed-length word from the q-bit input word in response to the decoded code length value. The next m-bit fixed-length word has a next variable code value and a next code length value.

Description: The present invention relates to a variable length decoder and, in particular, to a decoder for a variable length code which is suited for decoding compressed image data. BACKGROUND OF THE INVENTION Recently, some remarkable progress has been made in image data compression techniques. The goal of these techniques is to raise the efficiency of, for example, digital transmission and recording by encoding the image data at a lower bit rate than would be required for unencoded image data. Exemplary techniques which have been used to obtain these coding efficiencies are predictive coding and transform coding. In addition, further image data compression can be achieved by performing variable length encoding on the compressed code. The variable length encoding consists of varying the encoded bit width in accordance with the frequency of occurrence of the value to be encoded. Thus, a smaller bit rate can be obtained as compared to fixed length coding. One example of a variable length code is a Huffman code. Next, as an example of variable length coding, a description is given with reference to FIGS. 9a and 9b of a method for generating Huffman codes. Assume that t fixed length data values S 1 S 1 ,...S t are to be converted into Huffman codes. FIGS. 9a and 9b show an example for the case where t=6. First of all, codes S 1 to S 6 are arranged in order of the magnitude of the frequency of their occurrence (these magnitudes can be normalized to obtain the probabilities of occurrence). The probabilities of occurrence of codes S 1 to S 6 are respectively 0.35, 0.20, 0.15, 0.15, 0.10 and 0.05 as shown in FIG. 9a. They are therefore arranged in order of codes S 1 to S 6 . Next, taking the two codes which have the smallest probability of occurrence as one group, their composite probability (the sum of the two probabilities of occurrence) is found. In FIG. 9a, codes S 6 and S 5 have the smallest probability of occurrence, and their composite probability is 0.15. Next, this group and the other codes are arranged in order of magnitude of their probabilities of occurrence for composite probability. The two codes (or groups) having the smallest probability of occurrence (or composite probability) are taken as a new group, and the composite probability of this group is found. Subsequently, this process is repeated until a listing with the composite probability of one has been effected as shown in FIG. 9a. Finally, using FIG. 9a, a code tree as shown in Fig. 9b is compiled. "0" and "1" are then allocated in accordance with the branching of this code tree. In FIG. 9b, the upper branches are allocated "0", while the lower branches are allocated "1". The Huffman codes are obtained by following this branching. For example, as shown by the thick line in FIG. 9b, the fixed length code S 4 passes along a branch "0", along a branch "I", and finally along a branch "0", so it is converted to the Huffman code "010". The Huffman codes of the codes S 1 to S 6 found in this way are shown in Table one below. CODE Huffman Code Code Huffman Code S 1 00 S 4 010 S 2 10 S 5 0110 S 3 11 S 6 0111 As shown in Table one, codes which have higher probability of occurrence are converted into Huffman codes of short bit length, while codes which have a lower probability of occurrence are converted into Huffman codes of longer bit length. In this way, the overall bit rate for transmitting a given number of data values can be reduced. In general, to decode such variable length code into fixed length code, a conversion table, embedded in a solid state memory such as a ROM, is used. In FIG. 9a, for convenience in explanation, the maximum bit number of the variable length code (Huffman code) was taken as being four bits, in an actual image data signal, the maximum bit number may be larger, for example, 17 bits. The Huffman coding for the m most significant bits of an n-bit variable length code are necessarily different from the k least significant bits (where n, m and k are natural numbers and m, k < n) are necessarily different from the patterns of variable length code of n bits or less. For example, in the Huffman code of Table one above, the patterns "00", "10" of the Huffman code of S 1 and S 2 are not present in the most significant two bits of the Huffman code of S 3 , S 4 , S 5 and S 6 . Consequently, by examining the most significant bits or the least significant bits of the variable length code, it is possible to decode the variable length code. One exemplary prior art method for decoding the variable length is shown in Fig. 11. A n-bit parallel data signal is coupled to a look-up table (LUT) 111. The n-bit signal contains a variable length code word which is used as an address for data stored in LUT 111. The variable length code may be n bits in length. The data stored in LUT 111 corresponds to the code length and the code value. The code length data specifies the length of the variable length code word that has been identified in the n-bit signal. The code value is the decoded (i.e. fixed length) value of the variable length code. The output of LUT 111 is code length and code value which are z-bit and v-bit parallel data streams respectively. In operation, the variable length code received in the n-bit signal is used as an address to a memory location in LUT 111. After the memory location has been identified, the LUT outputs code length and code value which are stored at the memory location. However, the prior art device of Fig. 11 requires a large memory because an n-bit address must be provided as an input to LUT 111. In addition, each memory location in LUT 111 stores an z-bit code length and a v bit code value. As a result, a total of z + v bits are needed to store code length and the code value. The total number of bits required for LUT one is 2 n * (z + v). Accordingly, proposals have been made to limit the size of the conversion tables to reduce the required memory size for the conversion table. However, these techniques have resulted in a slower decoding process. For example, one such apparatus was proposed in U.S. Patent No. 5,138,316, entitled VARIABLE LENGTH CODE DEMODULATING APPARATUS AND ADDRESS CONTROL METHOD THEREOF, issued to Konishi (hereinafter '316 patent), shown in FIG. 10 and incorporated herein by reference for its teachings on decoders for variable length codes. The '316 patent describes a variable length code in which the most significant bits (MSBs) are provided to conversion table 822 and where the least significant bits (LSBs) are provided to conversion table 823. Respective 9 bit output values of each conversion table 822, 823 are coupled to a selector 830. In addition, a five bit output value of conversion table 822 is coupled to the LSB input of conversion table 823. Also a one bit output signal is provided by conversion table 822 to selector 824. In operation, 15 parallel bits of a variable length encoded bit stream are applied through the input terminal 821. The most significant eight bits of a segment of the bit stream are applied to conversion table 822. The seven least significant bits are provided at the address input terminal of conversion table 823 as the LSBs of a 12 bit address value which also include the 5-bit conversion code from conversion table 822. If a Variable length Code (VLC) value consists of 8 bits or less, then a length code "1" is produced by conversion table 822 to the control terminal 826 of selector 824. Further, the 9-bit fixed length value stored at the address indicated by this variable length code value is provided by conversion table 822 to the first input terminal 828 of the selector 824. Since the selector receives a "1" at its control input terminal 826, it passes the fixed length code applied to the first input terminal 828. In contrast, if the variable length code value is 9 bits or more, a length code "0" is generated by the conversion table 822. The conversion table 822 also generates the 5-bit conversion code stored at the address corresponding to the most significant 8 bits. Thus, a 12-bit code word is supplied to the address input port of conversion table 823. The address conversion table 823 is thus designated and the 9-bit fixed length code corresponding to the VLC of 9-bits or more is applied to the second input terminal 830 of selector 824. Although this arrangement reduces the table size, it also reduces the rate at which the VLC can be decoded. This occurs because conversion table 822 first attempts to decode the VLC. However, if conversion table 822 fails to decode the VLC, conversion table 822 must first provide additional bits to conversion table 823 prior to decoding by conversion table 823. The paper by J.W. Peake entitled "Decompaction" describes a variable-length decoding system which employs a first programmable logic array (PLA) as a length decoding circuit and a second PLA as a code-value decoding circuit. These circuits operate in parallel such that the length of the variable length code word is determined at substantially the same time as the code value represented by the variable length code word. U.S. patent No. 5,173,695 describes a variable length decoding system which was also described in the "Decompaction" article. This system uses a programmable logic array having AND terms and OR terms. The AND terms are used as a content-addressable memory to recognize the code words in the bit stream. The OR terms are used to provide both the decoded value and the length of the variable length value. U.S. patent No. 4,276,544 discloses a variable-length decoder (see Fig. 14) that employs two parallel look-up tables, one table decodes the 4-bit fixed-length input value to determine a code-length value. The other table decodes the same 4-bit fixed-length input value to determine the decoded data value. SUMMARY OF THE INVENTION The present invention relates to an apparatus that reduces the memory size of the table used to decode the VLC without slowing the decoding process. The present invention further relates to reducing the memory size by reducing the number of bits stored at an address in the LUT. The present invention is embodied in a variable length decoder for decoding a variable length code value. The variable length decoder includes a code length look-up table which receives n-j bits of an n-bit fixed-length word. A segment of the variable length code value is held in the n-j bits where n and j are integers and j is less than or equal to n. The code length look-up table also produces a decoded code length value. The variable length decoder also includes a code value look-up table which receives the n-bit fixed-length word and produces a decoded code value of the variable length code. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a variable length decoder. FIG. 2 is a block diagram of a variable length decoder according to the first exemplary embodiment of the present invention. FIGs. 3a-3c are tree diagrams showing a example of how code trees are combined. FIGs. 4a-4c are tree diagrams showing another example of how code trees are combined. FIGs. 5a-5c are tree diagrams showing another example of how code trees are combined. FIG. 6 is a tree diagram showing a partial code tree suitable for use in the coding standard defined by the Moving Picture Expert's Group (MPEG) of the International Standards Organization (ISO) . FIGs. 7a-7g are tree diagrams showing the code tree of FIG. 6 divided into lower level code trees to produce smaller conversion tables. FIG. 8 is a block diagram of a variable length decoder for decoding MPEG variable length codes according to the third exemplary embodiment of the present invention. FIGs. 9a and 9b (prior art) are tree diagrams explaining huffman codes, where FIG. 9a shows the process of generating Huffman codes, and FIG. 9b, shows a Huffman code tree. FIG. 10 (prior art) is a block diagram of a conventional variable length code demodulating apparatus. FIG. 11 is a block diagram of a prior art variable length decoder for decoding variable length codes. A variable length decoder is described with reference to Fig. 1. A separate code length table is used to determine the code length of the variable length code. As shown in Fig. 1, an n-bit input stream is provided to code value LUT 3. Code value LUT provides a decoded value of the variable length code contained in the n-bit input stream. In addition, n minus j (n - j) bits of the n-bit input stream are provided to code length LUT 2. The separate code length LUT is used to determine the code length of a variable length code contained in the n-bit input stream. In operation, a segment, the (n-j) most significant bits, of the n-bit input stream is provided to code length LUT 2. The entire n-bit input stream is provided to code value LUT 3 to recover the data values of the variable length code from the bit stream. The code value LUT 3 does not store the code length of the variable length code. As described below, by using a separate code length table, it is possible to reduce the overall size of the memory required for decoding the variable length code. This results because the code value LUT does not have to include both the code value and its corresponding code length. Thus, the number of bits stored in the code value LUT at an address may be reduced. The code length LUT 2 uses the n-j most significant bits of the n-bit stream as an address in memory. The bits located at that address specify the length of the code. A corresponding address for each variable length code does not have to be provided because some of the variable length codes have the same length. For example, of the codes shown in Table one, the code length can be uniquely determined from the first three bits of the variable length codes even though the longest code word is four bits. Accordingly, j would be one. In operation, after receiving the n-j bits, the code length LUT provides the code length specifying the length of the variable length code. For example, of the codes shown in Table one, the code length value stored in the memory of the code length LUT would be two for S1 to S3, three for S4 and four for S5 to S6. If j is set equal to one, then the lengths of the variable length codes in Table One may be determined using the three most significant bits of the variable length code. Accordingly, if the three most significant bits of the variable length code is 010, the code length LUT would provide a length value of three. If the three most significant bits of the variable length code is 011, the code length LUT would provide a code length value of four. Code value LUT 3 uses the n-bit stream as an address in memory. Stored at the address in memory is a code value for the variable length code. However, the length of the variable length code may not be stored in the memory of code value LUT 3 because it is stored in the memory of code length LUT 2. As a result of using both code length LUT 2 and code value LUT 3 to decode code length and the code value respectively, it is possible to reduce the required memory used for look up tables. To illustrate the reduction in memory, consider the prior art shown in Fig. 11 where a separate code length table is not used. The memory size for the prior art device is 2n * (z + v). The memory size for the exemplary embodiment shown in Fig. 1 is the memory size, 2 (n-j) * z, of the code length LUT + the memory size, 2 n * v, of the code value LUT or (2 (n-j) * z) + (2 n * v). The reduction in memory size is calculated as (2 n * (z + v)) - ((2 (n-j) * z) + (2n * v)) which is equal to (2n - 2 (n-j) ) * z. Thus, the size of the memory needed to hold the code length values is reduced by a factor of 2 j . First Exemplary Embodiment FIG. 2 shows a variable length decoder according to a first exemplary embodiment of the invention. At input terminal 5, the decoder receives a segment of a variable length encoded data stream of, for example, n bits. The variable length encoded data is split so that the m MSBs, where m is a natural number and 0 < m <= n, of the variable length code are applied to LUT zero 20. The k LSBs, where k is a natural number and 0 <= k <= n, of the variable length code are applied to LUT one 30. The addresses in LUT zero 20 and LUT one 30 are specified by the bits that are applied at the address input terminal, and the data output values of LUT zero 20 and LUT one 30 are specified by the data stored at the designated address. The output signal of LUT zero 20 is applied to a first data input port of both multiplexer 40 and multiplexer 41. In addition, a decode signal is also provided by LUT zero 20 to a control input terminal of multiplexer 40 and 41. The output signal of LUT one 30 is applied to a second data input port of multiplexer 40 and multiplexer 41. In operation, the m MSBs and k LSBs are provided to LUT zero 20 and LUT one 30 respectively. Each table decodes the bits provided using the bits as an address within the table and by providing, as its output value, the data stored at that addressed location within the table. In the exemplary embodiment LUT zero 20 and LUT one 30 decode the m MSBs and the k LSBs respectively of the n-bit fixed length segment, at substantially the same time, thus, performing a parallel decoding operation. The data stored at the address location includes a code length indicating the length of the variable length code and a code value which is the decoded value of the variable length code. The code length and the code value are z and v bit parallel streams. In addition to providing the data value at the address indicated by the m MSBs, LUT zero 20 also provides a decode signal, DS, to multiplexers 40 and 41 indicating whether table zero 20 has correctly decoded the variable length code word. If the decode signal is "0", then multiplexers 40 and 41 passes the data provided by LUT zero 20. This is done because LUT zero 20 has successfully decoded the variable length code word and thus, it is unnecessary to consider the output of LUT one 30. If, however, the decode signal is "1", then LUT zero 20 has not successfully decoded the variable length code word. As indicated above, in this instance, LUT one 30 has necessarily decoded the variable length code word because LUT zero 20 has not. Accordingly, multiplexers 40 and 41 pass the data value provided to it by LUT one 30. Thus, according to the second exemplary embodiment, the variable length decoder is able to reduce the size of the tables needed for conversion while also maintaining decoding speed by using the LUTs in parallel to decode the MSBs and LSBs of the variable length code. LUT zero 20 and LUT one 30 have m and k corresponding addresses for the m MSBs and k LSBs of the variable length code respectively. The partitioning of the code tables and the number of most significant bits and least significant bits, m and k, are determined in accordance with a method described below. What is desired is to produce a combination of addresses for LUT zero 20 and LUT one 30 such that the combined table is reduced in size in order to minimize the amount of memory required for the tables. The method for determining the size of the tables 20 and 30 shown in Fig. 2 is described below with reference to FIGs. 3a-3c, 4a-4c, and 5a-5c. The method uses code trees which correspond to the variable length codes. The correlation between the variable length codes and code trees is illustrated by Table One and Fig. 9b. Table One has variable length codes which may be generated by tracing the branches of the tree shown in Fig. 9b. For example, the variable length code for S5 is generated by tracing the branches from A to S5. The variable length code produced is 0110. For example, assume that an n-bit code tree is given where n is also the maximum length of the variable length code. If it is assumed that LUT zero 20 has m bits, as noted above, the minimum size k of table one 30 can be determined as follows. First, k is set equal to n minus m (k = n - m). Then a level for the main tree is calculated as n minus k (n - k). For example, consider FIG. 3a, level two is the tree level corresponding to leaf nodes 00 and 10. A higher level, for example level one, is the tree level corresponding to branch nodes zero and one. A tree level may have subtrees below the level. For example, level two of FIG. 5a has one subtree. The subtree is below branch node 00 with two branches having two leaf nodes 000 and 001. For each tree and subtree a corresponding LUT may be generated. The LUT for a respective tree or subtree uses the variable length codes at the leaf nodes of the respective tree or subtree as addresses in memory. The inventor has determined that lowest possible value of k for LUT one which will both (1) decode the variable length code in combination with LUT zero and (2) produce the minimum combined table size, is k = n - m. It can be determined if a variable length code can be decoded by LUT one having k LSBs and LUT zero having m MSBs by combining subtrees of the main tree which correspond to the tables respectively. If the subtrees can be combined without overlap, then LUT one having k LSBs and LUT zero having m MSBs will decode the variable length code. For example, if the subtrees shown in FIG. 3a and 3b are combined, then the tree in FIG. 3c is produced. This is accomplished by combining the different subtrees and the subtrees' corresponding leaf nodes of the main tree shown in FIGs. 3a and 3b. Alternatively, the combination of the two subtrees may be performed by laying one tree on top of the other tree. If the leaf nodes of FIG. 3a at level two do not overlap with the leaf nodes of FIG. 3b, then the combination of the subtrees is valid. As a result, k, where k has been set equal to n-m, would be minimized. If, however, as shown in Figs. 4a, 4b, and 4c, subtrees are combined, and an overlap at leaf node 00 occurs, then leaf node 00 is not unique to either of the subtrees shown in FIG. 4a and 4b, and the split shown in FIGS 4a and 4b may not be used. Another improper combination is illustrated in FIGs. 5a-5c. Here, FIG. 5a contains an additional leaves at level three. When the subtrees of FIGs. 5a and 5b are combined, it is not possible to distinguish the leaf nodes at level three because the leaf nodes at level two of the subtree shown in FIG. 5b includes a leaf node which makes the level three leaf nodes shown in FIG. 5a not unique. Multiple trees may be combined by first combining two subtrees to produce a new tree and then by combining the next subtree with the new tree. This, process may be repeated if additional trees are provided. If the branches at level n minus k (n - k) can not be combined, then the next level, (n - k) + 1 or n - k' where k' = k - 1, is tested. Prior to combining at the n - k' level, all of the leaves at the n - k level are pruned (removed). Then, the main tree is divided into subtrees at the n - k' level. For example, if a level two split does not work, the leaf nodes at level two are pruned and then the main tree is split at level one. Then, the subtrees at level one are combined. The method for combining subtrees at the next level, n - k', is same as the method used to combine the subtrees at the n-k level. This process is repeated until the main tree is split into subtrees which may be combined. The first value of k which produces a valid split is the lowest value of k which will produce a combined table which uses a smaller amount of memory than a single table that processes n bits in parallel. Using this method, a LUT may be split into a smaller primary and secondary LUTs where each of the smaller tables corresponds to a subtree which may be combined with the other subtrees to produce a tree that corresponds to the original LUT. In addition, the minimum table size for the secondary tables may be determined. Further, to maximize the overall size of the primary table and the secondary table, the minimum of 2m +2 k , where m is the bit length for the primary table and k is the bit length for the secondary table, is calculated. The minimum value may be determined by calculating different values of k for different values of m. For example, consider the partial MPEG tree shown in FIG. 6. FIGs 7a-7g show examples of different combinations of m and k for LUT zero 20 and LUT one 30 assuming that the maximum length of the variable length code is only 10 bits. FIG. 7a shows the case where m for LUT 20 is one bit and k for LUT one 30 is 9 bits. When the two subtrees corresponding to the two tables are combined the tree in FIG. 7a is produced. However, leaves 10 and 11 overlap when the trees are combined. Thus the subtrees can not be combined. FIG. 7b shows the case where m is two bits and k is 8 bits. This combination is also improper because leaves 01 and 00 conflict. FIG. 7c shows the case where m is two bits and k is 9 bits. As shown, a conflict does not exist when the trees corresponding to the tables are combined. Therefore, a valid split of the table has been performed. This process is repeated in FIGs. 7d-7g for different combinations of m and k bits. The splits shown in Fig. 7d, 7e, and 7f can not be combined. However, the split shown in FIG. 7g may be successively combined. By iteratively performing the above method of combining subtrees for different values of m and k it is possible to arrive at Table two below which lists combinations of m and k bits for tables that produce valid combinations. In Table two, the first column. represents the number of m bits for LUT zero 20 and the second column shows a corresponding number of k bits for LUT one 30. The third column shows the combined table size using different combinations of m and k in column one and two of table two. TABLE ZERO (Bits) TABLE ONE (Bits) MEMORY SIZE (in words) 1 10 1026 2 9 516 3 9 520 4 8 272 5 8 288 6 8 320 7 8 384 8 3 264 9 3 520 10 0 1024 The table size is determined using the formula 2 m + 2 k . For example, where m = 3 and k = 9, the memory size is 2 3 + 2 9 = 520. The combination of m and k which produces the minimum table size is m = 8 and k = 3. For this implementation the codes defined in the tree for level three and below are in one table, the secondary table, and the codes for the first eight levels of the trees are in another table, the primary table. Next, for example, consider the code tables B-14 and B-15 defined in the MPEG-2 standard, proposed by the Moving Picture Experts Group (MPEG) of the International Standards Organization (ISO). This standard is described in a draft internal standard (DIS) publication entitled "Information Technology - Generic Coding of Moving Pictures and Associated Audio, Recommendation H.626" ISO/IEC 13818-2 DIS, 3/94 which is available from the ISO and which is hereby incorporated by reference for its teaching on the MPEG-2 digital video encoding standard. In this code table, variable length code words having a maximum size of 17 bits are to be decoded. Tables three and four below show the split of a 17 bit segment of the bit stream of LUT zero 20 and LUT one 30 for providing the most significant bits and the least significant bits to the respective tables for decoding the variable length code word. The proposed MPEG standard has two tables, "DCT Coefficient Table Zero" and "DCT Coefficient Table One", corresponding to two sets of discrete cosine transform DCT coefficients. Table three shows the split for "DCT Coefficient Table Zero" and Table four shows the split for "DCT Coefficient Table One". (Combinations for DCT Coefficient Table Zero for MPEG-2) MSB's bit width LSB's bit width Redundant bit width Total table size 6 15 4 32832 7 15 5 32896 8 15 6 33024 9 11 3 2560 * 11 10 4 3072 13 9 5 8704 (Combinations for DCT Coefficient Table One for MPEG-2) MSB's bit width LSB's bit width Redundant bit width Total table size 8 15 6 33024 9 11 3 2560 * 10 11 4 3072 11 10 4 3072 13 9 5 8704 As can be seen from Tables three and 4, an optimum table size of 2560 can be obtained for "DCT Coefficient Table Zero" and for "DCT Coefficient Table One". Optimization limits the amount of memory required to implement the tables while ensuring that the variable length code is accurately and rapidly decoded. Thus, a variable length code may be decoded using parallel LUTs which results in reduced memory usage and high speed decoding. Second Exemplary Embodiment The second exemplary embodiment is an MPEG decoder which is described with reference to FIG. 8. According to the third exemplary embodiment, a separate code length table is used to determine the code length of the variable length code and to decode the variable length code. As shown in FIG. 8, shifter 610 is connected to a 32 bit input stream. The output of shifter 610 is coupled to code length table 620 through a n-j parallel bit stream and to variable length code word table 630 through an n parallel bit stream. Shifter 610 is also coupled to control circuitry 660 which is in turn coupled to code length table 620. Code length table may also be divided into two tables as indicated by the dashed lines for CDL 621 and multiplexer 622. The code length table may be divided into two tables using the LUT dividing method described in the second exemplary embodiment. Variable length table 230 includes two LUTs 635, 636 coupled to multiplexer 640. LUTs 635, 636 receive m and k parallel bit streams from shifter 610 respectively. The values n, n-j, m and k may be set equal to 17, 11, 9 and 11 respectively. In operation, shifter 610 receives a 64-bit parallel segment of the bit stream. The 64 bit segment received by shifter 610 includes several variable length code values. A programmable segment of the bit stream is provided by the shifter 610 to variable length code word table 630 and to code length (CDL) table 620. An n-bit parallel segment of the bit stream is provided to variable length code word table 630 to recover the code values from the variable length code from the bit stream. An (n-j)-bit wide parallel bit stream is applied to code length table 620 to acquire the code length. As described below, the code length is used to separate the variable length encoded value from the subsequent variable length encoded values in the continuous bit stream. Accordingly, the variable length encoded value does not need to be immediately decoded because the subsequent variable encoded value may be identified in the bit stream using the acquired code length. Further, as described in the first exemplary embodiment, by using a separate code length table, it is possible to reduce the overall size of the memory required for decoding the variable length code. This results because the table does not have to include both the decoded variable length code value and its corresponding length value. Thus, the number of bits stored in the table at an address may be reduced. Once code length table 620 has decoded the code length, the decoded code length is provided to control circuitry 660. The code length table uses the (n-j) bits as an address in memory. The data contained at the address in memory is supplied by the code length table 620 to control circuitry 660. Control circuitry 660 uses the code length value to determine the number of bits in the variable length code value at the start of the segment of the data stream being provided by shifter 610. Accordingly, control circuitry 660 controls shifter 610 in response to the code length to provide a subsequent segment of the bit stream immediately after the variable length code value that has been provided. For example, if the variable length code is two bits in length, the code control circuitry 660 causes shifter 610 to provide a subsequent segment which starts immediately after the two-bit variable length code as the next output value of shifter 610. As a consequence, control circuitry 660 can identify the start of the next series of bits regardless of whether the variable length table 630 has decoded the code value. In addition, CDL 620 may be divided into two CDLs 620, 621 which provide output code lengths to multiplexer 625 for a corresponding LUT 636 and 635. First, variable length table 630 is divided into LUTs 635, 636. Then a separate CDL 621, 620 is created for each of the LUTs 636, 635. In operation, each CDL 620 and 621 receives a parallel bit segment of the n-bit data stream corresponding to the m and k parallel bit streams received by LUTs 636 and 635 respectively. Then each CDL 621, 620 decodes its respective segment. CDL 621 provides a detected code length signal, DCL, of "1" to multiplexer 625 if CDL 621 has obtained a valid code length. CDL 621 provides a DCL of "0" to multiplexer 625 if CDL 621 has not obtained a valid code length. If multiplexer 625 receives a DCL "1", multiplexer 625 provides the code length provided by CDL 621 to control circuitry 660. However, if multiplexer 625 receives a DCL "0", multiplexer 625 provides the code length provided by CDL 620 to control circuitry 660. Variable length table 630 uses the method described in the first exemplary embodiment to decode the variable length code. As a result of using both code length table 620 and variable length table 630 to decode code length and the variable length code word respectively, it is possible to operate the decoding system at a high rate of speed while also reducing the required memory used for look up tables to decode encoded values. Further, the decoding apparatus may be prepared to receive the next segment of bits and process those bits without waiting for all of the previous data in the previous segment of bits to be decoded. To illustrate the reduction in memory, consider the case where separate code length tables and parallel LUTs are not used as shown in Fig 11. The table memory size would be 2 n * (z+v). In contrast, for the third exemplary embodiment employing a separate code length table and separate LUTs for obtaining the code value, the total size of the tables would be (2m + 2 k ) * v + 2 (n-j) * z. Thus, a reduction in the size of the tables can be realized. The reduction is calculated as (2 n * (z+v)) - ((2 m + 2 k ) * v + 2 (n-j) * z) which is equal to (2 n - 2 (n-j) ) * z + (2 n - 2 m - 2 k ) * v. Since m and k are less than n, then 2 n >= 2 m + 2 k . Accordingly, as m and/or k are decreased in value, the reduction in memory size increases. For example, if the minimum table size from Table 3 is used, 9 and 11 for table zero 636 and table one 635 where n is 17 bits, and assuming (n-j) is equal 11, the total reduction in memory realized is (2 17 - 2 11 ) * z + ((2 17 - 2 9 - 2 11 ) * v) or (128512 * v + 129024 * z). The described variable length decoder may be modified so that LUT zero 20 supplies the code length value of the variable length code to shifter 10 through parallel bit line 21. LUT zero 20 would also store the code length value in addition to the decoded variable length code value at an address corresponding to the m MSBs. Accordingly, LUT zero 20 supplies both the code length value to shifter 10 and a decoded variable length code value to multiplexer 40. In addition, it is possible to divide a primary LUT into more than two LUTs to minimize the required size for the LUTs. This process is accomplished by first dividing a primary LUT into two LUTs having m-bit and k-bit input data streams using the method described in the second exemplary embodiment. Then the LUT having the k-bit input data stream is divided as if it is a primary LUT using the method described in the second exemplary embodiment.

Claims: A variable length decoder for decoding a variable length code value, the decoder comprising: code length look-up table means (620, 621) for receiving n-j bits of an n-bit fixed-length word, a segment of the variable length code value being held in the n-j bits, n and j being integers and j is less than n, and for producing a decoded code length value; and a code value look-up table (630) for receiving the n-bit fixed-length word and for producing a decoded code value, CHARACTERIZED IN THAT : the code value look-up table (630) includes: first code value look-up table means (636) for receiving the m most significant bits of the n-bit fixed-length word holding the variable length code and for producing a first decoded code value of the variable length code; second code value look-up table means (635) for receiving the k least significant bits of the n-bit fixed-length word holding the variable length code for producing a second decoded code value of the variable length code and a selection signal indicating if the second decoded code value is valid; and multiplexing means (640), coupled to receive the first and second decoded code values and responsive to the selection signal to pass the second decoded code value if the selection signal indicates that the second decoded code value is valid and to pass the first decoded code value otherwise. A variable length decoder as recited in claim 1 further comprising: shifter means (610) for receiving an q-bit data input word and for extracting an n-bit fixed-length word holding the variable length code value, the variable length code value having a maximum bit length of r which is less than n; n, r, and q being integers, n being less than or equal to q and m and k being less than r; and control means (660) for causing the shifter means (610) to extract a next n-bit fixed-length word from the q-bit input word in response to the decoded code length value, the next n-bit fixed-length word holding a next variable length code value The variable length decoder as recited in claim 1 or 2, wherein: the code length look-up table means (620) includes a first memory (620) and the n-j bits of the n-bit fixed-length word are used as an address for the first memory; the first code value look-up table means (636) includes a second memory (636) and the m most significant bits of the n-bit fixed-length word are used as an address for the second memory; and the second code value look-up table means (635) includes a third memory (635) and the k least significant bits of the n-bit fixed-length word are used as an address for the third memory. The variable length decoder as recited in claim 3, wherein the decoded code length values are stored at the addresses in the first memory (620), a first subset of the decoded code values are stored at the addresses in the second memory (636) and a second subset of the decoded code values are stored at the addresses in the third memory (635), wherein the second subset of decoded code values represents a sub-tree of the code set. The variable length decoder as recited in claim 3 or 4, wherein the first, second and third memories (620, 636, 635) are read only memories. A method for decoding a variable length code value comprising the steps of: receiving an q-bit data input word and extracting an n-bit fixed-length word holding the variable length code value, n and q being integers and n being less than or equal to q; extracting n-j bits of the n-bit fixed-length word, a segment of the variable length code value being held in the n-j bits, j being an integer and less than n, decoding the code length code value using a look-up table and the n-j bits of the n-bit fixed-length word to produce a decoded code length value; decoding the m most significant bits of the n-bit fixed-length word, m being less than n, to produce a first decoded code value of the variable length code; decoding the k least significant bits of the n-bit fixed-length word, k being less than n, for producing a second decoded code value of the variable length code and a selection signal indicating if the second decoded code value is valid; selecting one of the first decoded code value and the second decoded code value responsive to the selection signal; and extracting bits from the q-bit data input word using the decoded code length value to produce a next n-bit fixed-length word having a next variable length code value.

Inventors: INOUE SHUJI, INOUE, SHUJI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1995
Main classification: H03M7
IPC codes: H04N7, H04N1, H03M7