INTEGRATED CIRCUIT TEMPERATURE SENSOR WITH A PROGRAMMABLE OFFSET

Abstract: Temperature sensor (10), with programmable offset, generates an output voltage (Vo) that is a PTAT voltage VPTAT shifted by offset voltage Voff. Band gap cell (12) generates a basic voltage across first resistor (RPTAT) to produce current (IPTAT). Second resistor (Rgain), connected between first resistor (RPTAT) and reference voltage terminal (Vee), provides voltage gain. Third resistor (Roff) is connected across the base-emitter junction of transistor (Q1) and between second resistor (Rgain) and output terminal (20) where voltage (Vo) is provided. The transistor's base-emitter voltage provides a portion of Voff. Third resistor (Roff) reduces the portion of current (IPTAT) flowing through second resistor (Rgain) to provide the remaining portion of Voff. Current source (IS1) supplies an emitter current and a current for third resistor (Roff). Offset voltage Voff is set by trimming third resistor (Roff) until voltage (Vo) equals a voltage applied to reference voltage terminal (Vee) at a lower end of a desired temperature range. The gain of VPTAT is then set by trimming first resistor (RPTAT).

Description: INTEGRATED CIRCUIT TEMPERATURE SENSOR WITH A PROGRAMMABLE OFFSET BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to integrated circuit (IC) proportional to absolute temperature (PTAT) temperature sensors, and more specifically to an IC temper¬ ature sensor with a programmable offset. Description of the Related Art The base-emitter voltage V be of a forward biased tran- sistor is a linear function of absolute temperature T in degrees Kelvin (°K), and is known to provide a stable and relatively linear temperature sensor. where k is Boltzmann's constant, T k is the absolute tempera- ture (°K) , q is the electron charge (k/q=86.17μV/°K) , I c is the collector current, A e is the emitter area, and J s is the saturation-current density. PTAT sensors eliminate the dependence on collector current by using the difference ΔV be between the base-emitter voltages V bel and V be2 of two tran- sistors that are operated at a constant ratio between their emitter-current densities to form the PTAT voltage. The emitter-current density is conventionally defined as the ratio of the collector current to the emitter size (this ignores the second order base current) . The basic PTAT voltage ΔV be is given by: Δ be = V bel -V be2 ( 2 ) ΔV b, e ( H£ ) in (lΞi * (3 ) <2 I c 2 A el The basic PTAT voltage is amplified so that its gain, i.e. its sensitivity to changes in absolute temperature, can be calibrated to a desired value, suitably lOmV/°K, and buf¬ fered so that a PTAT voltage can be read out without cor¬ rupting the basic PTAT voltage. A drawback of standard PTAT sensors is that at ordi¬ nary operating temperatures for most ICs there is a large offset voltage signal. For example, if the desired operat¬ ing range for an IC is 0 to 125°C (273 to 398°K) and the sensor has a gain of 10mV/°K, the PTAT sensor will have an offset voltage of 2.73V at 0°C. If the gain of the PTAT sensor is not perfectly stable, a relatively small change in the offset voltage may shift the output temperature by several degrees. To read out a temperature from 0 to 125° C, a reference voltage of precisely 2.73V must be sub- tracted from the output of the PTAT sensor. Providing a reference voltage with adequate precision and stability is difficult and costly. Furthermore, PTAT sensors require relatively large supply voltages to supply the offset volt¬ age in addition to the voltage needed to respond over the desired operating range and any head voltage needed to op¬ erate the sensor. Thus, products such as lap top computers which run off approximately 3V supplies cannot use PTAT sensors. Pease, "A New Fahrenheit Temperature Sensor, " IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 6, Dec. 1984, pages 971-977, discloses a temperature sensor that provides an output voltage scaled proportional to the Fahr¬ enheit temperature without subtracting a large constant offset voltage at the output. Pease generates a PTAT volt- age using a conventional transistor pair and internally subtracts two base-emitter voltages to shift the PTAT volt¬ age by a constant offset voltage. A non-inverting amplifi¬ er is used to multiply the shifted PTAT voltage by a fixed gain, e.g. 1.86, to simultaneously set the sensor's desired offset voltage, e.g. 770mV at 77°F, and gain, e.g. 10mV/°F. The gain is inherently calibrated by simply trimming the offset error at room temperature. In this manner, Pease effectively subtracts the offset voltage so that the sen¬ sor's output voltage is zero at 0°F. Pease's circuit topology has several drawbacks. The shifted output voltage is produced in two separate stages: a constant offset is first subtracted from the basic PTAT voltage and then the result is multiplied by the amplifier to achieve the desired output. This increases the sensor's complexity. Because the amplifier is used to buffer the output voltage in addition to providing gain, any errors in the amplifier such as offset voltage or offset voltage drift are reflected into the output voltage signal and may cause a temperature shift. For the Fahrenheit sensor to measure 0°F, the inverting input of the amplifier must be able to go to ground potential. This type of amplifier is complex and difficult to design. National Semiconductor Corporation produces an LM35 series of Precision Centigrade Temperature Sensors which are disclosed in their Data Acquisition Data Book, 1993, pages 5-12 to 5-15 and are the centigrade equivalent of Pease's Fahrenheit sensor. The centigrade sensors exhibit the same problems and require a minimum 4V supply voltage. SUMMARY OF THE INVENTION The present invention provides a temperature sensor with a an accurate programmable offset that generates an output voltage V 0 over a desired temperature range that is a PTAT voltage V PTAT shifted by an offset voltage V of£ , but with a simpler design than prior temperature sensors. This is accomplished with a band gap cell that gener¬ ates a basic PTAT voltage across a first resistor to pro¬ duce a PTAT current Ipτ AT . A second resistor is connected from the first resistor to a reference voltage terminal to provide voltage gain. A transistor has a base that is con¬ nected between the first and second resistors, a collector that is tied to a supply voltage, and an emitter that is connected to an output terminal at which V 0 is generated. The transistor's base-emitter voltage provides a portion of offset voltage V off . A third resistor is connected across the transistor's base-emitter junction, which reduces the portion of Ipχ AT that flows through the second resistor and provides the remaining portion of V off . A current source is positioned between the transistor's emitter and the refer¬ ence voltage terminal to supply its emitter current and the current for the third resistor. The offset voltage V off is set by trimming the third resistor until V 0 equals a voltage applied to the reference voltage terminal at a lower end of the desired temperature range. The desired gain of V PTAT is then set by trimming the first resistor. For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plot of the output voltage for the sensor of the present invention versus absolute temperature; FIG. 2 is a simplified schematic diagram of a band gap temperature sensor with a programmable offset voltage in accordance with the present invention; FIG. 3 is a more detailed schematic diagram of a pre¬ ferred embodiment of the band gap temperature sensor shown in FIG. 2; and FIG. 4 is a simplified schematic diagram that illus¬ trates the programmable offset capability of the present invention for a general PTAT voltage source. DETAILED DESCRIPTION OF THE INVENTION As shown in FIG. 1, the present invention provides a temperature sensor that generates an output voltage V 0 that is a PTAT voltage shifted by a desired offset voltage V of£ so that V 0 goes to the sensor's low supply, typically ground, when the temperature is at the lower end of a de¬ sired temperature range. The 0V temperature intercept is set by programming the sensor's offset voltage and gain. This increases the sensor's accuracy, removes the need to generate and subtract a reference voltage from the output voltage, and allows the temperature sensor to operate from 0 to 125°C with a gain of 10mV/°C off a single-sided supply voltage of approximately 2.7V. This approach allows the sensor's offset voltage and gain to be adjusted to accomrno- date both Centigrade and Fahrenheit sensors with a wide range of operating temperatures and gains. Pease's sensor is capable of generating the same graph, but requires more complicated circuitry and at least a 4V supply. A programmable offset is provided by adding a single offset resistor to a conventional band gap temperature cell and by generating V 0 at a different point in the cell. The desired offset is programmed by trimming the offset resis¬ tor until V 0 equals 0V at the desired offset temperature. The sensor's gain is programmed independently by trimming another resistor in the band gap cell. An output amplifier is preferably connected to the cell to buffer V 0 so that it is not effected by external loading. This approach is simple and accurate. The offset voltage is programmed in a single stage by trimming a sin- gle resistor while the gain is controlled independently by trimming a second resistor. The output amplifier is used only to buffer V 0 , and hence errors in the amplifier are not reflected into the output voltage. Furthermore, the ampli¬ fier is a simple one whose input does not have to be capa- ble of going to ground potential. As shown in FIG. 2, a temperature sensor 10 that has a programmable offset in accordance with the invention in¬ cludes a band gap cell 12 that provides a basic PTAT volt¬ age ΔV be , and an offset resistor R off that selects an offset voltage so that sensor 10 produces output voltage Vo, where V 0 substantially equals the voltage at the low supply V ee , preferably ground potential, at a lower end of a desired temperature range. Band gap cell 12 includes a pair of npn transistors QI and Q2 that conduct different current densi- ties to establish the basic PTAT voltage. The ratio of their current densities is preferably set by substantially equating their collector currents I Q1 and I Q2 , suitably 3μA, and providing transistor QI with an emitter area A el that is A, suitably 10, times larger than the emitter area A e2 of transistor Q2. The emitters 16 and 18 of transistors QI and Q2, re¬ spectively, are tied together at an output terminal 20. A current source IS1 is connected between output terminal 20 and ground, and supplies tail current for both transistors. Their bases 22 and 24 are connected across a resistor and establish the basic PTAT voltage ΔV be , as described in equations 2 and 3, across a resistor R PTAT . The PTAT voltage causes a PTAT current to flow through resistor R PTAT . A resistor R gaιn is connected from the base 22 of transistor QI to ground to provide gain for the basic PTAT voltage. Without the invention and ignoring the base currents of transistors QI and Q2, I PTAT would flow through resistor R gain . The collector currents I Q1 and I Q2 that flow through the collectors 26 and 28 of transistors QI and Q2, respective- ly, are input to a differential current amplifier Al which has a current gain of suitably one hundred. ' The ampli¬ fier's output 32 is connected between a high voltage supply V cc and the base 24 of transistor Q2, and supplies I PTAT (ig¬ noring the second order effects of Q2's base current) to maintain the basic PTAT voltage across resistor R PTAT . The purpose of amplifier Al is to make the band gap cell insen¬ sitive to changes in supply voltage V cc . Alternately, a differential voltage amplifier could be used with pull re¬ sistors connecting its differential input and output 32 to the high supply. In the absence of R off , the output voltage would be taken from the top of resistor R PTAT and would be given by: R kT V 0 = (l+_2≥iS) ! j .l n (A) (4) R PTAT q The ratio of R gain to R PTAT would be set to select the desired gain for the temperature sensor, and the conventional out¬ put voltage V 0 would be PTAT, and thus would incorporate a large offset voltage. In accordance with the invention, resistor R off is con¬ nected across transistor Ql's base 22 and emitter 16, and output voltage Vo is read out at output terminal 20. The effect of taking the output voltage at output terminal 20 is twofold. First, the base-emitter voltage of transistor QI is subtracted from the PTAT voltage across resistor R gain and provides a portion of the desired offset V off . Second, the output voltage V 0 can be reduced to 0V at a desired temperature by collapsing the voltage across current source IS1. The effect of connecting resistor R off across transistor Ql's base-emitter junction is to provide a current source that sinks a portion of IPTAT from resistor R PTAT , thereby reducing the portion of I PTAT that flows through resistor R ga i n - This reduces the voltage across resistor R gain by the remaining portion of the desired offset V off , which reduces V 0 by the same amount. Because the base-emitter voltage of transistor QI is a function of temperature, connecting resistor R off across its base-emitter junction and moving the output has the additional effect of increasing the gain of output voltage Vo. This reduces the amount of gain that must be provided by the basic PTAT voltage and resistor R gain , which in turn reduces the supply voltage V cc required to drive the sensor. The characteristic equation for output voltage V 0 is given by the following derivation. First, the voltage across resistor R gain is described by: V R g ain = ^ I PTAT~ I Rof f ' R gain ( 5 ) Δ V h V h where I p τ AT = — and I off = — — . Substituting these rela- RpTAT "off tionships into equation 5 gives: Thus, the output voltage, which is V Rgain shifted down by a base-emitter voltage, is given by: V, / kT In(A) Vteiv p , r t- x ( XT ~ _ R R g in V bel \ ' > y, - J ^-pTAT Λ OFF The base-emitter voltage for a transistor is given by: V„ Ω = E -BT (8) where E g is the band gap voltage and B is a constant. E g is independent of processing parameters, bias-current levels, and transistor geometry, and thus provides a constant ref- erence value of approximately 1.17V for silicon. The con¬ stant B depends on bias current and processing, and has a typical value of 2mV/°K. Substituting the relation for V be from equation 8 into equation 7 and rearranging to separate the voltage compo- nent that is PTAT from the constant voltage offset gives: V Q = [ 2SiΞj^ln(A}+B(l + siΞ)]T k - ( 1 + ^≡ ) E g (9) RpTAT °- R-off off Therefore, the desired offset voltage V off is given by: V off = -(l+ )E g (10) and the PTAT voltage V PTAT generated at output terminal 20 is: V PTAT = [- ^-ln(A) + B(l + ^≥i 2 )]T k (11) RpTAT °J- R off Thus, offset voltage V off is set by selecting the ratio of R ga i n / off / and the gain of VPTAT is calibrated by select ¬ ing the resistance of R PTAT . In practice E g does not vary appreciably, and hence R ga i n off can t> e set without trimming. The slope of V be does vary so that R PTAT can be trimmed until V out equals a desired value, for example V ώut =0.25V at 25°C. This configuration has the additional benefit of re- ducing the amount of supply voltage V cc that is required to drive the temperature sensor. The supply voltage has to provide approximately the voltage at base 24 of transistor Q2 for the maximum desired temperature plus a V be for ampli- fier Al. Simply providing an offset voltage at the output would not reduce this amount. However, the invention re¬ duces the gain of the basic PTAT voltage and offsets the voltage across resistor R gain . This reduces the voltage at base 24, and thus reduces the required supply voltage. A good approximation is that the voltage at base 24 is a V be above the output voltage, and hence the supply voltage V cc must be at least two V be 's above the maximum output volt¬ age. For example, a temperature sensor with a temperature range of 0-125°C and a gain of 10mV/°K has a maximum V 0 of 1.25V. A V be is approximately 0.414V at 125°C. Thus, the minimum supply voltage V cc would be approximately 2.1V. Therefore, a centigrade temperature sensor with a 10mV/°C gain and a range of 0-125°C would run comfortably off a 2.7V supply. FIG. 3 shows a preferred temperature sensor that 10 includes the band gap cell 12 from FIG. 2 with preferred implementations of current source IS1 and differential am¬ plifier Al, and an output amplifier A2 for buffering V 0 . Current source IS1 is implemented with a current source IS2 that provides current I s2 , suitably 3μA, which flows from the positive supply V cc through a diode DI to ground. Diode DI is implemented as a diode-connected npn transistor hav¬ ing an emitter 34 that is connected to ground and a base- collector 36. Another npn transistor Q3 has an emitter 38 that is connected to ground, a base 40 that is connected to base-collector 36 of diode DI, and a collector 42 that mir¬ rors I s2 to output terminal 20 with a fixed amount of gain. This supplies the emitter currents of transistors QI and Q2 and the offset current I off flowing through resistor R off . Differential current amplifier Al includes a current mirror Ml that drives a difference current equal to IQ1-I Q2 into the base 44 of a pnp output stage transistor Q4 that amplifies the difference current to supply I PTAT . One side of current mirror Ml includes a diode D2 that is implement- ed as a diode connected pnp transistor having an emitter 46 that is connected to V cc and a base-collector 48 that is connected to transistor Ql's collector 26. The other side of mirror Ml includes a pnp transistor Q5 having a base 50 that is connected to base-collector 48 of diode D2, an emitter 52 that is tied to V cc , and a collector 54 that is connected to transistor Q2's collector 28 and base 44 of output stage transistor Q4. The emitter 56 of transistor Q4 is connected to V cc and its collector, which provides amplifier Al's output 32, is connected to the base 24 of transistor Q2. Current mirror Ml and output stage transistor Q4 to¬ gether provide a negative feedback path that stabilizes band gap cell 12 and makes it insensitive to fluctuations in the supply voltage V cc . For example, an increase in the difference current causes an increase in Ip-xv This in turn increases the voltage at the base 24 of transistor Q2, which increases its collector current I Q2 and consequently reduces the difference current. Output amplifier A2 is connected between band gap cell 12 and a load 57 such as a read out circuit, and supplies load current I L to drive load 57 in accordance with output voltage V 0 . Without amplifier A2, transistors QI and Q2 would have to drive the load. Although QI and Q2 are ca¬ pable of providing some current without affecting V 0 , it is preferable to use amplifier A2 to provide a buffer that maintains the integrity of V 0 over a wide range of load conditions. Amplifier A2 includes a current mirror M2 that mirrors collector current I Q1 to a current node 58. Current mirror M2 shares diode D2 with mirror Ml and includes a pnp tran- sistor Q6 having a base 60 that is connected to D2's base- collector 48, an emitter 62 that is tied to V cc , and a col¬ lector 64 that is connected to node 58. An npn transistor Q7 having a base 66 that is connected to the base-collector 36 of diode DI, an emitter 68 tied to ground, and a collec¬ tor 70, sinks a reference current I ref from current node 58 so that a difference current of I Qι -I ref is supplied from node 58 to the base 72 of an output transistor Q8. This transistor has a collector 74 that is tied to V cc , and an emitter 76 that is connected to output terminal 20. Output transistor Q8 amplifies the difference current I Q1 -I ref by its current gain β, suitably 100, to supply most of the load current I L at output terminal 20. Transistors QI and Q2 supply a small second order portion of the total load current I L , approximately I L /β, which is not appreciable and does not significantly effect V 0 . In the preferred embodiments of temperature sensor 10 shown in FIGs. 2 and 3, transistor QI served a dual pur¬ pose. First, it forms part of the transistor pair Q1/Q2 that sets the basic PTAT voltage. Second, transistor QI together with offset resistor R off provides the program¬ mable offset voltage. However, many different circuit to¬ pologies might be used to generate the basic PTAT voltage ΔV be . The generalized situation is shown in FIG. 4, in which a PTAT voltage source 80, such as band gap cell 12 in FIGs. 2 and 3, generates the basic PTAT voltage across re¬ sistor R FTM , which causes I PTAT to flow through resistor R gain . The combination of transistor QI and resistor R off reduces the portion of I PTAT that flows through resistor R gain so that the output voltage V D at output terminal 20 is shifted by the desired offset. While several illustrative embodiments of the inven¬ tion have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Such variations and alternate embodiments are contem- plated, and can be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims: AMENDED CLAIMS [received by the International Bureau on 29 November 1995 (29.11.95); original claims 3-6 amended; remaining claims unchanged ( 3 pages )]. 1. A band gap temperature sensor, comprising: a first resistor R PTA ; first and second transistors (Q1,Q2) having respective bases that are connected across said first resistor, collectors, and emitters that are connected together, said transistors conducting respective collector currents with different current densities which establishes a basic voltage proportional to absolute temperature (PTAT) across resistor R PTA τ causing a PTAT current I TA to flow through resistor R PTA ; a reference voltage terminal (V ee ) ; a second resistor R ga i n that is connected between the base of the first transistor and said reference voltage terminal and conducts a first portion of I P AT ; a biasing current source (IS1) that is connected from the emitters of said transistors to said reference vol¬ tage terminal and supplies emitter current for said transis¬ tors; and an offset current source (R 0ff ) that sinks a sec¬ ond portion of I PTAT to set the first portion of I PTA that flows through resistor Rg a i n - said temperature sensor responding to I PTAT by producing an output voltage V 0 at said emitters that is a PTAT voltage V PTAT shifted by an offset voltage V off , re¬ sistor R ga in being selected to set V off so that V 0 is substan¬ tially the same as a voltage applied to said reference voltage terminal at a desired temperature. 2. The temperature sensor of claim 1, wherein said offset current source comprises a third resistor R off that is connected across the first transistor's base and emitter and conducts said second portion of I PTAT ■ the ratio of R ga in to R off being selected to set V 0ff . 3. The temperature sensor of claim 1, further com¬ prising: a supply voltage terminal for receiving a supply voltage (V cc ) ; and a differential amplifier (Al) that is connected to the supply voltage terminal, and has a differential input that is connected to the transistors ' collectors and an output that is coupled to the base of the second tran¬ sistor, said differential amplifier stabilizing the temperature sensor so that the basic PTAT voltage is insensitive to changes in said supply voltage. 4. The temperature sensor of claim 1, wherein said output voltage V 0 responds to centigrade temperatures from approximately zero degrees centigrade to approximately 125 degrees centigrade with a sensitivity of approximately 10mV/°C, said reference and supply voltages differing by less than 3 volts. 5. The temperature sensor of claim 1, wherein said reference voltage is ground reference potential. 6. The temperature sensor of claim 3, wherein said differential amplifier comprises: a current mirror (Ml) having a current input that is connected to said supply voltage terminal, said differen- tial input, and a current output; an output stage transistor (Q4) having a base that is connected to said current output and a current circuit that supplies current to resistor R PTAT - 7. The temperature sensor of claims 3,4 or 5, further comprising: a reference current source (IS1) that generates a reference current; an output amplifier (A2) having a differential input that is connected to said reference current source and the collector of said first transistor, and having a current output that is connected to said first transistor's emitter, said output amplifier comparing said first transistor's collector current to said reference current to supply a drive current at said current output. 8. The temperature sensor of claim 7, wherein said first and second transistors' emitters are connected at an output node (20), said differential and output amplifiers comprising: a current mirror (M1,M2) having a reference input that is connected to said first transistor's collector and supplies its collector current, first and second inputs that are connected to said second transistor's collector and said reference current source, respectively, and which conduct said first transistor's collector current, and first and second current outputs that supply the difference between the first and second transistors ' collector currents and the difference between the first transistor's collector current and said reference current, respectively; an output stage transistor (Q4) having a base that is connected to said first current output and a current circuit that supplies current to resistor R AT ; and a drive transistor (Q8) having a base that is connected to said second current output and a current circuit that supplies current at said output node. 9. The temperature sensor of claim 8, wherein said output voltage V 0 responds to centigrade temperatures from approximate zero degrees centigrade to approximately 125 degrees centigrade with a sensitivity of approximately 10mV/°C, said reference voltage is ground potential and said supply voltage is less than 3 volts.

Inventors: AUDY JONATHAN M, AUDY, JONATHAN, M.
Applicants: ANALOG DEVICES INC, ANALOG DEVICES, INC. (ADI)
Application year: 1995
Main classification: G05F3
IPC codes: G01K7, G05F3