Digital signal reproducing apparatus

Abstract: In a digital signal reproducing apparatus, data can be reproduced even in a variable speed reproduction mode as easily as in a normal reproduction mode. In the apparatus, data read from a magnetic tape (1) is supplied to a reproduction equalizing portion (4) via a reproducing amplifier (3). The reproduction equalizing portion (4) trims the waveshape and supplies the resultant signal to a data determining comparator (5) which digitizes the input signal. The digitized data is supplied to a reproduction clock extracting portion (7) which extracts a reproduction clock signal. The extracted clock signal is supplied to a reproduction data strobe portion (6) which supplies the digitized data to an error correcting portion (8) in synchronization with the reproduction clock signal. The error correcting portion (8) generates an error correction flag, an interpolation flag, and so forth. A reproduction signal processing portion (10) and a memory (9) process signals and output a sound signal through a D/A converting portion (11).

Description: This invention relates to digital signal reproducing apparatus, for example apparatus for reproducing an audio PCM (Pulse Code Modulated) signal recorded on a recording medium via a rotating magnetic head. As an example of a digital signal reproducing apparatus, a DAT (Digital Audio Tape) apparatus may be considered. In the DAT apparatus, data is recorded on the recording medium in a two-track-paired interleaved format. Thus, when data is reproduced from the DAT at a double reproducing speed, data at the same interleave region is selected and deinterleaved. The present applicants have proposed a digital data recording apparatus that reproduces sound data that has been interleaved on more than two tracks: see Japanese Patent Application No. HEI 5-198782 (Publication No. HEI 7-37336). Figs. 1A and 1B are conceptual schematic diagrams showing an example of the structure of data for one frame. As shown in Fig. 1A, one frame is composed of ten tracks. Signals on L channel are recorded on tracks TR1 to 5. Signals on R channel are recorded on tracks TR6 to 10. These tracks are recorded on a magnetic tape as shown in Fig. 1B. Now, assume the case that data of frames that have been interleaved is reproduced at a variable speed. When data is reproduced at +2.0 times variable speed, the reproducing magnetic head passes through the same track number for each frame. When image signals are reproduced, the position of a noise bar is fixed. To prevent such a problem, data is reproduced at +2.1 times speed. Fig. 2 shows an example of a reproduction RF signal at +2.1 times speed in track pattern coordinate method. In Fig. 2, the horizontal axis represents time t and the vertical axis represents tape traveling amount s. The slope p = s / t in Fig. 2 represents reproducing speed. The dotted lines represent the +2.1 times reproducing speed. The solid lines represent standard reproducing speed. Numerals in Fig. 2 represent track numbers that identify tracks that have been interleaved. At this point, each of the widths of the recording head and the reproducing head is the same as the track pitch. When the azimuth of the reproducing head is considered, the reproduction RF signal is represented in a parallelogram shape as shown in Fig. 2. The length in the vertical direction is proportional to the level of the reproduction RF signal. In other words, the ratio of the length of each side in the vertical direction of the parallelogram in the normal reproduction mode and the length of each side in the vertical direction of the parallelogram in the variable speed reproduction mode is equal to the ratio of reproduction levels. Since sound data is recorded on the entering side of the magnetic tape, if the magnetic head travels from track TR1, as shown in Fig. 2, the signal levels of data on tracks TR1, TR5, TR8, and TR9 of the first reproduction frame and tracks TR2, TR3, TR6, TR7, and TR10 are 0 dB, -2.2 dB, -12 dB, -4.4 dB, -5.6 dB, -8.5 dB, -3.1 dB, -14 dB, and -1.4 dB, respectively. Likewise, the signal levels of data on tracks TR4 and TR8 of the third reproduction frame and tracks TR1, TR2, TR5, TR6, and TR9 of the fourth reproduction frame are -1.4 dB, -3.1 dB, -8 dB, -6 dB, -5.2 dB,-10.5 dB, and -2.5 dB, respectively. The data on these tracks are reproduced. Fig. 3 shows signal levels of reproduction RF signals for four frames including a reproduction frame at +2.1 times reproducing speed. In Fig. 3, the horizontal axis represents L/R channels and the vertical axis represents frame numbers of reproduction data. By considering error correction in the reproduction signal processing portion, it is assumed that signals with signal levels of up to -3.0 dB can be reproduced. Only signals of data in the same frame are processed. Signals reproduced in the first frame are processed. On L channel, one of data on track TR1 or TR5 is reproduced in frame number N. On R channel, since the signal level of data on track TR9 in frame number N exceeds -3.0 dB, it is not reproduced. At this point, on R channel, data on track TR10 in the next frame N + 1 is reproduced. Likewise, on L channel, data on track TR4 in frame number N + 2 is reproduced. On R channel, data on track TR9 in frame number N + 3 is reproduced. On the next L channel, one of data on track TR3 in frame number N + 4, data on track TR1 in frame number N + 5, and data on track TR2 in frame number N + 6 is reproduced. On R channel, one of data on track TR7 in frame number N + 4 and data on track TR8 in frame number N + 5 is reproduced. On the next L channel, data on track TR1 in frame number N + 9 is reproduced. On R channel, data on track TR6 in frame number N + 7 is reproduced. Thus, at +2.1 times speed, only data on one track or two tracks are reproduced. Thus, the data amount at +2.1 times speed is 1/5 to 2/5 as low as that at the normal speed. When deviation of tracking in variable speed reproduction mode and losses such as spacing loss in a tape/head portion are considered, reproduction data cannot be always reproduced with 100 % accuracy. Data with a large loss is interpolated with preceding and following data corresponding to an interpolation flag received from an error correcting portion of a reproduction signal processing portion. On track TR1 in frame number N and on track TR3 in frame number N + 4 that are represented by solid lines, sound data recorded at the beginning of the tape can be reproduced as with the case in the normal reproduction mode. In the previously proposed signal processing method for the variable speed reproduction mode, the amount of data reproduced in the same frame is small. In addition, data with interpolation flag should be interpolated with reproduced data with small amount. The resultant signals cannot be properly recognized. European Patent Application Publication No EP-A-0 155 101 and US Patent No US-A-4 943 872 disclose apparatus for reproducing data recorded in an interleaved manner on respective tracks on a recording medium. According to the present invention there is provided a digital signal reproducing apparatus having a non-integer relation between a sampling frequency of a digital information signal to be recorded and an inner interleave reference signal frequency and adapted for reproducing adjacent sample sequence data interleaved on non-adjacent tracks, comprising a signal process memory means for dividing a memory region into a plurality of regions and writing/reading data to/from the divided memory regions and a means for treating A/D converted data corresponding to an error flag other than the error flag after a data read region of the memory region as null data and rewriting the data to a flag representing that all data is null data. In a preferred embodiment of the invention described hereinbelow, a signal processing buffer memory of a reproduction signal processing portion is divided into a plurality of banks and data is read and written therefrom and thereto. At this point, after a data read region, all data (other than an error flag) that is supposed to be sent to an A/D converting portion is treated as null data. An error flag received from an error correcting portion of the reproduction signal processing portion is rewritten to a flag that represents that all data is error data. In a variable speed reproduction mode such as two times speed reproduction mode, regardless of whether or not data is in the same interleave region, data written in the memory is deinterleaved. When an error flag that represents that the data should be interpolated is received from the error correcting portion, a data read signal processing portion optimally interpolates data corresponding to the error flag. In the variable speed reproduction mode, the address generating rate of an address counter is varied so as to read data written in the memory corresponding to the variable speed. Thus, sound signals can be easily heard. According to the preferred embodiment of the invention, in the normal reproduction mode and, in particular, the variable speed reproduction mode, a sound signal can be recognized as clearly as possible without need to change the reproduction signal processing method. In addition to the case that the reliability of the interpolation flag received from the error correcting portion is low as in the variable speed reproduction mode, since all data in the memory banks are rewritten as null data after the data are read, noise due to error correction can be more properly prevented. Moreover, even if an E/D ID is erroneously detected, since data in other than valid data recording region of the memory is null data, occurrence of noise can be easily suppressed, thereby improving the reliability. The invention will now be further described, by way of illustrative and nonlimiting example, with reference to the accompanying drawings, in which: Figs. 1A and 1B are schematic diagrams showing an example of one frame of data; Fig. 2 is a schematic diagram showing an example of a reproduction RF signal in a variable speed reproduction mode corresponding to track pattern coordinate method; Fig. 3 is a schematic diagram showing an example of the level of a reproduction RF signal in the variable speed reproduction mode; Fig. 4 is a schematic diagram showing an example of one block of data; Fig. 5 is a schematic diagram showing an example of one track of data; Fig. 6 is a schematic diagram showing an example of interleaving on a track of data; Fig. 7 is a schematic diagram showing an example of interleaving among tracks of data; Figs. 8A and 8B are block diagrams showing a digital signal reproducing apparatus according to an embodiment of the present invention; Fig. 9 is a block diagram showing a reproduction signal processing portion according to an embodiment of the present invention; Fig. 10 is a schematic diagram showing signal wave of reproduced at +2.1 times speed for sine wave; Fig. 11 is a schematic diagram for explaining an example of the operation of a three-bank type memory for use in apparatus embodying the invention; and Fig. 12 is a schematic diagram for explaining an example of the operation of a two-bank type memory. Next, with reference to the accompanying drawings, an embodiment of the present invention will be described. The description will be made in the following order. (1) Example of structure of block (2) Example of structure of track (3) Example of interleaving on track (4) Example of interleave among tracks (5) Example of entire block construction of digital signal recording apparatus (6) Example of block construction of reproduction signal processing portion (7) Example of description of operation of memory banks (1) Example of structure of block Fig. 4 is a conceptual schematic diagram showing an example of the structure of one block of record data. One block is composed of a header portion, a main data portion, and a C1 parity portion. The header portion is positioned at the beginning of the block and composed of a block sync (Sync)(two bytes), header IDs (ID0 and ID2)(two bytes), and a header ID parity (one byte). Thus, the header portion is composed of a total of five bytes. A track ID number (1 to 10) is written to the low order four bits of the header ID0. A block ID number (1 to 14) is written to the low order four bits the header ID1. The main data portion (hereinafter referred to as data portion) is composed of 78 bytes. Data and C2 parity are written to the data portion. At the beginning of the data portion, there is a region in which an ID signal that identifies whether data recorded in a frame portion is E data frame (excess data frame) or D data frame (diminished data frame). The C1 parity portion is composed of eight bytes. Thus, one block is composed of 91 bytes. At the beginning of the data portion, an E/D ID that identifies whether the number of samples in the frame portion being recorded is E data or D data is written. (2) Example of structure of track Fig. 5 is a conceptual schematic diagram showing an example of the structure of data of one track. One track is composed of a first data portion (five blocks), a C2 parity portion (four blocks), and a second data portion (five blocks). Thus, one track is composed of a total of 14 blocks. Even number data on L and R channels are positioned in the data portion at addresses BA1 to 5 (hereinafter, these data are referred to as even number sequence). Odd number data on L and R channels are positioned in the data portion at addresses BA10 to 14 (hereinafter, there data are referred to as odd number sequence). A parity that is interleaved in the direction of block addresses BA is placed in position of the C2 parity portion at addresses BA6 to 9. One frame is composed of 10 tracks in the above-described structure. (3) Example of interleaving on track Fig. 6 is a conceptual schematic diagram showing an example of interleaving of data recorded on a track. For simplicity, only track TR1 will be described. In Fig. 6, five blocks of the first data portion and five blocks of the second data portion are shown. Four blocks of the C2 parity portion are omitted. As described above, data on L channel is written to track TR1. The regions surrounded by solid lines in Fig. 6 represent ID regions. In each of the ID regions, E/D ID, sampling frequency fs, number of quantizing bit Qu, and so forth are written. In Fig. 6, the vertical direction and the horizontal direction are defined as symbol address SA direction and block address BA direction, respectively. With respect to data L0, the data sequence in the symbol address SA direction is L0, L50, L100, L150, L200, ..., and so on. Thus, the interleave length in the symbol address SA direction is 50 samples. Likewise, with respect to data L0, the data sequence in the block address BA direction is L0, L10, L20, L30, L40, ..., and so on. Thus, the interleave length in the block address BA direction is 10 samples. The interleave lengths in the symbol address SA direction and in the block address BA direction are the same as those of data of even number sequence, odd number sequence, and other track TR data. Now, as described above, it is assumed that the standard number of samples is 1602 and that the numbers of samples of IDs (f1, f2) of two bits are represented as follows. (0, 0) : 1582 (number of D2 data) (0, 1) : 1592 (number of D1 data) (1, 0) : 1612 (number of E1 data) (1, 1) : 1622 (number of E2 data) When the frequency of the reference signal (inner interleave reference signal) that is recorded is the same as the frequency of the reference signal that is reproduced, it is not necessary to designate the number of samples other than the standard number of samples. However, when a digital interface input is considered, the sampling frequency may deviate for around ±1000 ppm. Thus, the number of samples should be designated so that it can absorb such deviation. When the sampling frequency fs is 48 kHz, the deviation of ±1000 ppm becomes 48.048 kHz (+1000 ppm) to 47.952 kHz (-1000 ppm). Thus, the number of samples should be designated with proper tolerance. Now, it is assumed that the standard number of samples is 1602, the number of E data is 1612, and the number of D data is 1592. In this case, when the frequency of the reference signal is 29.97 Hz, the sampling frequency fs of the number of E data is represented as follows. 29.97 (Hz) x 1612 = 48.31 (kHz) > 48.048 (kHz). The sampling frequency fs of the number of D data is represented as follows. 29.97 (Hz) x 1592 = 47.71 (kHz) < 47.952 (kHz). Thus, the deviation of ± 1000 ppm can be absorbed. Individual data are interleaved and written to corresponding tracks. At this point, in non-data regions,null data (00H) is written. Regions at BA5 and SA7 and at BA14 and SA7, an ID signal generated by an E/D ID generating circuit (that will be described later) is written. (4) Example of interleaving among tracks Fig. 7 is a conceptual view showing an example of interleaving of data recorded among tracks. With respect to data L0 of the even number sequence on track TR1, the data sequence on tracks is L0, L2, L4, L6, L8, ..., and so on. Thus, the interleave length between each track is two samples. With respect to data L5 of the odd number sequence on track TR1, the data sequence on tracks is L5, L7, L9, L1, L3, ..., and so on. Thus, the data L9 is followed by the data L1. However, when the conception of remainder is employed, the interleave length between each track is two samples. Thus, it is clear that data are regularly interleaved. (5) Example of entire block construction of digital signal recording apparatus Figs. 8A and 8B are block diagrams showing the construction of a digital signal reproducing apparatus embodying the present invention. Next, with reference to Figs. 8A and 8B, the operation of the digital signal reproducing apparatus will be described. On a magnetic tape 1, sound data that has the data structure described in (1) to (5) and that has been interleaved is recorded. The data recorded on the magnetic tape 1 is reproduced by a magnetic head 2 and amplified by a reproducing amplifier 3. The wave form of the data amplified by the reproducing amplifier 3 is equalized by a reproduction equalizing portion 4. Thereafter, the equalized data is digitized by a data determining comparator 5. The digitized data is supplied to a reproduction data strobe portion 6, a reproduction clock extracting portion 7, and an output terminal 13. The digitized data is supplied to a video signal processing portion (not shown) through an output terminal 13. The reproduction clock extracting portion 7 extracts a reproduction clock from the supplied data and supplies the reproduction clock to the reproduction data strobe portion 6 and an output terminal 14. The reproduction data strobe portion 6 outputs the data supplied from the data determining comparator 5 to an error correcting portion 8 in synchronization with the reproduction clock supplied from the reproduction clock extracting portion 7. The error correcting portion 8 generates an error correction flag, an interpolation flag, and so forth and supplies them to a reproduction signal processing portion 10. The reproduction signal processing portion 10 performs various data processes such as deinterleaving process, interpolating process, data time expanding process, E/D ID detecting process, and memory data clearing process trough a memory 9. The data processed by the reproduction signal processing portion 10 is supplied to a D/A converting portion 11. The converted data is output as a sound signal from an output terminal 12. (6) Example of block construction of reproduction signal processing portion Fig. 9 shows an example of the construction of the reproduction signal processing portion 10. Next, with reference to Fig. 9, the operation of the reproduction signal processing portion 10 will be described. Signals such as an error correction flag and an interpolation flag supplied from the error correcting portion 8 through an input terminal 21 are supplied to a track/block address detecting portion 22. The track/block address detecting portion 22 detects an address that identifies each data block, controls a data write address generating portion 23 corresponding to the detected signal, and generates an address in such a manner that data is written to a predetermined region of the memory 9. Data supplied from the input terminal 21 is sent to a data bus DB through a data write buffer 32 and then written to the memory 9. The data write address is sent to an address bus AB through a write address buffer 33. A data read address generating portion 26 generates a deinterleave address and outputs data that is supplied to the address bus AB through the read address buffer 38, expanded on time axis, and read through the data read buffer 39 to a D/A converting portion 11. The D/A converting portion 11 outputs the D/A converted sound signal through an output terminal 12. An E/D ID read address generating portion 25 generates an address so that an E/D ID is read in a data read region. The address is supplied to the address bus AB through an E/D ID read address buffer 36. The E/D ID identifies one of frames E1, E2, D1, and D2. The E/D ID is read through an E/D ID read buffer 37. A counter in the data read address generating portion 26 is controlled so that samples in the signal process frame region are read corresponding to the ID. After samples of data corresponding to the detected E/D ID are read, an error flag ON/00H data write address generating portion 27 operates. The operated error flag ON/00H data write address generating portion 27 is supplied to the address bus AB through the 00H data write address buffer 34. The error flag ON/00H data generating portion 28 writes <00H> data to the memory 9 through the 00H data write buffer 35 and the data bus DB so that data that sets the generated error flag and all reproduced data become null data. Thus, since <00H> data is written to the data portion of tracks that have not been reproduced by the magnetic head 2, ragged noise is not output. When there is a loss of the reproduction RF signal as in the variable reproduction mode and thereby the reliability of the interpolation flag supplied from the error correcting portion is low, even if the error flag has been set, since the <00H> data is written, the noise is suppressed and the reliability is improved. Even if data in different frames are reproduced in variable speed reproduction mode, the track/block address detecting portion 22 writes data to a predetermined data region corresponding to the detected address. Referring to illustrations representing reproduction signals corresponding to track pattern coordinate method shown in Figs. 2 and 3, it is clear that data of one or two frame ahead is reproduced in the +2.1 times speed reproduction mode. In this embodiment, as described above, the length of interleaving between each track is two samples. Reproduction data in different frames at the sample data interval are deinterleaved. When a sound with a delay and a sound without a delay are added, the resultant signal is heard as an echo sound. In the signal process of the embodiment of the invention, the same effect occurs. Even if an echo sound takes place in a signal, it is more easily recognized than the case of no data. Fig. 10 is a conceptual schematic diagram showing signal wave of reproduced at +2.1 times speed for sine wave. This diagram represents L channel. Reference numeral 1 to 5 represents track number respectively. Block dots represent sample data that will be reproduced. It will be understood that data similar to that of obtained in normal reproduction mode can be reproduced, although data of 3 frame regions are mixed in frame region of (N+4). If the reading rate of the memory is normal, the pitch of reproducing signal becomes high. Then the reading rate of the memory is reduced to make the pitch of the signal equal to that of normal reproducing mode as a simple manner. As described above, after data is expanded on time axis, data in the memory 9 is all <00H>. Data portion that is not reproduced becomes no-sound portion. In addition, data that is deinterleaved is always data of one or two frames ahead. Thus, as a sound signal, remarkably strange feeling does not take place. (7) Example of description of operation of memory bank Fig. 11 is a timing chart for explaining an example of the operation of banks of a memory in the reproduction signal processing portion embodying the present invention. In Fig. 11, for simplicity, the operation in the case of three banks will be described. Data is written at a frame region corresponding to FLID2 that synchronizes with frame reference signal FLID1. A read counter pulse P is generated after an address at which the last sample data is read in the frame is output. Thus, the position of the read counter pulse P varies depending on the E/D ID. However, the position of the read counter pulse P is present in the vicinity of the leading edge of the frame reference signal FLID1. The data at the frame region is extended on time axis in the period of the read counter pulse P. The resultant data is read from the memory and then A/D converted. Next, the operation of banks at several frame regions will be described. The memory has three banks 0 to 2. Each bank should have the storage capacity that can store at least the number of samples of E2 data, E/D ID, interpolation flag, and so forth. Now, it is assumed that the number of samples of the E2 data is 1622, the number of quantizing bits is 16, and the number of channels is two (L/R). In this case, the number of bits required for three banks of the memory can be represented as follows. 3 x 1622 x 2 x 16 = 155712 (bits) Thus, with only one 256 kbit memory, all required data including IDs can be stored. As the storage capacity of the memory increases, the number of banks increases. In addition, the lip sync delay amount between the sound signal and the image signal can be increased. Now, it is assumed that data of bank 0 is read and the data is D/A converted. This region is DA1. DA1 is D data. A read counter pulse P2 is positioned slightly on the left of the leading edge of the frame reference signal FLID1. The next reading region is DA2 of bank 1 of the memory. Data is read after the read counter pulse P2. The DA1 region of bank 0 is followed by an N1 region. At the N1 region, the error flag is set and sound data is rewritten as <00H>. The N1 region is followed by a W4 region. In the variable speed reproduction mode, only reproduced data is written. The length of data write region is the length of the region of the period of the frame reference signal. Such data read/write operations are repeated for banks 0 to 2. Fig. 12 is a conceptual schematic diagram showing the operation of a two-bank type memory. As shown in this diagram, in the two-bank type, since the data read region and the D/A converting region are not constant, the data read region may overlap with the write region. For example, while D data of DA3 of bank 0 is being read and D/A converted, data of bank 1 is written. Thus, the read region may overlap with the write region. In this embodiment, when the phase of the data write reference signal FLID2 is varied in such a manner that it does not overlap with the data read region, a lip synchronization between an image signal and a sound signal can be established. When the number of banks is increased, the variable range can be easily increased. Having described a specific preferred embodiment of the present invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to that precise embodiment, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims: A digital signal reproducing apparatus having a non-integer relation between a sampling frequency of a digital information signal to be recorded and an inner interleave reference signal frequency and adapted for reproducing adjacent sample sequence data interleaved on non-adjacent tracks, comprising: signal process memory means (24) for dividing a memory region into a plurality of regions and writing/reading data to/from the divided memory regions; and means for treating A/D converted data corresponding to an error flag other than the error flag after a data read region of the memory region as null data and rewriting the data to a flag representing that all data is null data. The digital signal reproducing apparatus as set forth in claim 1, further comprising: means (22, 23) for detecting an address that represents a data sequence of blocks or symbols and writing the data to the memory (9) according to the detected address when a variable speed reproduction is performed; means (26) for deinterleaving the data written in the memory regardless of whether or not the data is at the same interleave region; and means for interpolating the data read from the memory corresponding to the error flag when the data is read. The digital signal reproducing apparatus as set forth in claim 2, further comprising: means for varying an address generating rate of an address counter (26) for reading the data written in the memory (9) corresponding to a changed speed when a variable speed reproduction is performed. The digital signal reproducing apparatus as set forth in claim 3, wherein the data on the tracks is composed of a first data portion, a second data portion, a first parity (C2), and a second parity (C1). The digital signal reproducing apparatus as set forth in claim 4, wherein the first parity (C2) is placed between the first data portion and the second data portion and the second parity (C1) is placed after the first data portion, the first parity, and the second data portion. The digital signal reproducing apparatus as set forth in claim 5, wherein the memory (9) is composed of a plurality of data banks and a reproduced signal is recorded in the banks with reference to a first field and a second field. The digital signal reproducing apparatus as set forth in claim 6, wherein the data is recorded in the banks when the first field starts. The digital signal reproducing apparatus as set forth in claim 7, wherein there are at least three banks, data of the first field and the second field being successively recorded, the data being recorded in each of the banks whenever one field changes to another field.

Inventors: MURABAYASHI NOBORU, MURABAYASHI, NOBORU, MURABAYASHI, NOBORU, C/O INTELLECTUAL PROP. DIV.
Applicants: SONY CORP, SONY CORPORATION
Application year: 1995
Main classification: G11B20
IPC codes: G11B20, G11B27, G11B15