Method for manufacturing a bipolar transistor

Abstract: The invention described herein includes, in one of its forms, a method for fabricating a bipolar transistor having a reduced base-collector capacitance. A specific embodiment includes forming a selectively etchable material 44 over a highly doped subcollector layer 42, removing portions of the selectively etchable material 44 and then growing collector 46, base 48, and emitter 50 layers over the structure. The selectively etchable material 44 may then be removed to form an undercut region between the highly doped subcollector layer 42 and the highly doped base 48. The structure provides the advantage of improved high-frequency and high-power operation.

Description: FIELD OF THE INVENTION This invention generally relates to high performance bipolar transistors, and more specifically to transistors having reduced base-collector capacitance. BACKGROUND OF THE INVENTION Heterojunction bipolar transistors (HBTs) exhibit desirable features such as high power density and an extremely high cut-off frequency as compared to other devices like MESFETs. Even so, HBTs intended for microwave power applications require ever-increasing power gain and efficiency. It is well-known that power gain is inversely proportional to base-collector capacitance. Hence, a transistor that has its base-collector capacitance reduced by a factor of two can produce approximately 3 dB more in power gain. Previous partial solutions addressing this base-collector capacitance have tended to produce transistors with inferior performance because the process of reducing base-collector capacitance often results in an increase in other parasitic impedances. For example, one simple method of reducing base-collector capacitance is to minimize the base contact area. However, this involves a design tradeoff between base resistance, which improves with increasing contact area, and junction capacitance, which degrades with increasing contact area. Another past effort was the ion bombardment of the extrinsic base region (see Japanese Patent No. 2-235341). Ion bombardment reduces the effective doping density of the layer beneath the base in the extrinsic base region. At best, this approach ensures that the collector layer beneath the extrinsic base is depleted of free carriers. This increases the effective dielectric thickness between the base and the underlying subcollector, thereby reducing the capacitance between those layers. A disadvantage of the ion bombardment approach is that the bombardment of the base layer results in increased base resistance. In addition, this technique requires great sensitivity, as it may result in reduced device reliability and degraded device current gain. Another problem is that it only reduces zero-bias base-collector capacitance. Another approach taken in the prior art has been to include a layer in the material structure next to the collector layer. This layer is of a material that allows it to be easily removed without removing the surrounding material. In other words, the layer may be selectively etched. An example of this approach is shown in Figure 1, where the transistor is an emitter-up type that is fabricated on a monolithic semiconductor substrate 20. The transistor comprises an emitter mesa 30 and emitter contact 32 over base 28 and collector 26 layers. The transistor shown includes an etch layer 24 between the subcollector 22 and the collector 26 layers. The etch layer allows the area of the interface between the lightly doped collector layer 26 and the highly doped subcollector layer 22 to be decreased. This also has the effect of lowering the overall base-collector capacitance. The problem with this approach is that it is difficult to reproducibly perform the selective etch so that the degree of undercut is the same across a semiconductor wafer or from wafer to wafer. In addition, the ledge comprising the base layer 28 and base contact 34, and that overhangs the undercut region, is prone to breakage in subsequent processing steps. The present invention is intended to address these problems. SUMMARY OF THE INVENTION The invention described herein includes methods for fabricating a bipolar transistor having a reduced base-collector capacitance as defined in independent claims 1-3. BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be further described by way of example, with reference to the accompanying drawings in which: Figure 1 is a cross-sectional view of a prior art transistor; Figures 2-10 are cross-sectional views of a first preferred embodiment transistor at various stages of an embodiment process; Figure 11 is a second preferred embodiment transistor; Figures 12-14 are views of a second preferred embodiment transistor at various stages in an embodiment process; Figure 15 is a third preferred embodiment transistor; Figures 16-18 are views of a third preferred embodiment transistor at various stages in an embodiment process; DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS A first preferred embodiment of the invention is described with reference to Figures 2 to 7. Two material structures that may be used for this embodiment are described in Table Ia and Ib. Element Generic Name Preferred Material Examples of Alternate Materials Approximate Layer Thickness Approximate Doping (cm -3 ) 54 Emitter contact InGaAs 700 A 1x10 19 52 Buffer GaAs 1000 Å 5x10 18 50 Emitter AlGaAs GaInP 1000 Å 5x10 17 48 Base GaAs 800 A 2x10 19 46 Collector GaAs 1 mm 2x10 16 44 Etch layer AlGaAs AlAs,GaInP 3000 A undoped 42 Subcollector GaAs 1 mm 2x10 18 Element Generic Name Preferred Material Examples of Alternate Materials Approximate Layer Thickness Approximate Doping (cm -3 ) 54 Emitter contact InGaAs 700 A 5x10 17 52 Buffer GaAs 500 Å 3x10 19 50 Emitter AlGaAs GaInP 1500 Å 3x10 17 48 Base GaAs 800 A 4x10 19 46 Collector GaAs 1 mm 2x10 16 44 Etch layer AlGaAs AlAs,GaInP 500 A 2x10 16 42 Subcollector GaAs 1 mm 2x10 18 The first step in the process is to form a highly doped subcollector layer 42 over a semiconductor substrate 40. In the embodiments described herein the substrate is GaAs, but transistors fabricated on other materials such as silicon (Si), indium phosphide (InP), and so forth may also obtain benefit from the invention. The layers in the embodiments described herein are typically epitaxially formed with a common technique such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or metal-organic molecular beam epitaxy (MOMBE). Etch layer 44 is then formed over the subcollector layer 42 as shown in Figure 2. The substrate is then removed from the MBE, MOCVD, or MOMBE apparatus. Photoresist (not shown) is patterned over etch layer 44, and the uncovered portions are removed as shown in Figure 3. The width of the uncovered portion defines the extent of the collector undercut of the finished transistor. It is important that the undercut not extend into the high-current-carrying region of the transistor's collector that lies directly beneath the emitter. Therefore, the width of the uncovered portion is typically chosen to extend approximately 0.25 mm beyond the edges of the high-current region generally defined by the location and boundaries of the emitter (formed in later process steps). Referring now to Figure 4, the lightly doped collector layer 46 is then grown by MBE, MOCVD, or MOMBE to fill the space left by the removal of a portion of layer 44 and also to form the collector of the transistor. The space is filled by growth on layer 42 as well as on the vertical sidewalls of layer 44. Layer 46 is essentially planar after about 0.5 um of growth. The quality of the interface between the vertical sidewalls of layer 44 and layer 46 and between layer 42 and layer 46 is important to the performance of the transistor. As described in co-assigned European application EP-A-0 627 761 (TI-17815 EU),of the overgrowth interface has been shown to be dependent on the crystallographic orientation of the substrate 40. The use of a substrate with a precise orientation of (100) (within a tolerance of 0.5°) avoids ledges that can form during epitaxial overgrowth and that adversely impact the quality of the layers subsequently grown on the structure. After collector layer 46 is grown, base layer 48, emitter layer 50, buffer layer 52, and emitter contact layer 54 may be formed in a conventional manner. Referring now to Figure 5, an emitter mesa is formed by depositing emitter contact metallization 56 of an alloy such as TiPtAu, AuGeNi, and so forth, on emitter contact layer 54. The emitter contact metallization is typically approximately 2.5 mm in width. Portions of layers 54, 52, and 50 not covered by emitter metallization 56 are then removed. Base contact metallization 58, also of TiPtAu, AuGeNi, or similar such alloys, are then formed on base layer 48. Photoresist 60 is then patterned over the emitter mesa and the base contact metallization 58 as shown in Figure 6. The collector 46 and etch 44 layers are then removed from areas not covered by photoresist. This exposes the edges of etch layer 44. Referring now to Figure 7, the etch layer 44 is then removed. If the etch layer 44 is AlAs (or AlGaAs with an aluminum content of greater than approximately 40%), a chemical such as hydrofluoric acid (HF) can be used to remove the etch layer 44 without affecting layers 48, 46, or 42, which in this embodiment are made of GaAs. It should be noted that AlAs tends to oxidize readily when exposed to air. Therefore, a thin layer of another material, such as GaAs may be grown over layer 44 in Figure 2. This generally prevents the AlAs from oxidizing when the wafer is removed from the growth chamber for the etch step shown in Figure 3. As an alternative to AlAs, AlGaAs may be used as an etch layer. If the aluminum content is greater than approximately 40%, the selectivity in etchability between AlGaAs and GaAs is acceptable. AlGaAs possesses the benefit of not readily oxidizing when exposed to the atmosphere. If a material such as GaInP is used for the etch layer 44, a chemical such as hydrochloric acid (HCl) or a combination of hydrochloric and phosphoric acid (HCl+H 3 PO 4 ) in the ratio of three parts H 3 PO 4 to 1 part HCl by volume can be used to remove the etch layer without affecting the surrounding layers of GaAs. An advantage of this technique is that there is no need to strip photoresist 60 and reapply photoresist to cover the edges of the base mesa as in prior art techniques where the collector layer itself is removed, see Japanese Patent Number 3-108339. Additionally, the extent of the undercut is predetermined by the initial etch pattern of the etch layer 44 shown in Figure 3. This eliminates the process variability that has plagued the prior art approach shown in Figure 1, which relies on a timed etch to create the undercut of the collector layer. Referring to Figure 8, an additional processing step is the deposition of a layer of a passivating dielectric 60, the purpose of which is to prevent the collapse of the mesa ledge that overhangs the undercut region. In subsequent processing steps, like the collector metal liftoff shown in Figure 9, the ledge is subjected to forces that can cause it to break. The tensile stress of the thin layer 60 is sufficient to prevent the ledge from succumbing to the downward force encountered in the liftoff process. A wide variety of materials are suitable for this function, but ones that are usually readily available in semiconductor processing are dielectrics like silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ), polyimide, or oxynitride. Similarly, the thickness of the dielectric layer is not critical. The layer is preferably about 2000 Å or greater, but the minimum thickness actually only depends on the thickness of the ledge being protected and on the forces encountered in processing. A typical transistor will have an undercut on the order of 1 um with a 3000 Å ledge overhanging the undercut. A layer of nitride 2000 Å thick has been shown to be very effective in preventing breakage of the ledge. After the collector metal (Figure 9) is lifted off, a passivating layer of dielectric 68 can be applied to the entire structure. This passivating layer will preferably conformally coat the undercut region as shown in Figure 10. The layer of air left in the undercut region serves to decrease the capacitance between layers 48 and 42 more than if the undercut region is completely filled with dielectric. However, even a completely dielectric-filled undercut region provides an advantage in base-collector capacitance in comparison to a transistor lacking an undercut. In a second preferred embodiment, the etch layer is moved down into the highly doped subcollector layer. Two material structures that may be used for this embodiment are described in Table IIa and IIb. Element Generic Name Preferred Material Examples of Alternate Materials Approx. Layer Thickness Approx. Doping (cm -3 ) 94 Emitter contact InGaAs 700 A 1x10 19 92 Buffer GaAs 1000 A 5x10 18 90 Emitter AlGaAs GaInP 1000 A 5x10 17 88 Base GaAs 800 Å 2x10 19 86 Collector GaAs 1 mm 2x10 16 84 Filled subcollector GaAs 1 mm 2x10 18 83 Etch layer AlGaAs AlAs, GaInP 3000 A undoped 82 Subcollector GaAs 1 mm 2x10 18 Element Generic Name Preferred Material Examples of Alternate Materials Approx. Layer Thickness Approx. Doping (cm -3 ) 94 Emitter contact InGaAs 700 A 1x10 19 92 Buffer GaAs 2000 A 1x10 19 90 Emitter AlGaAs GaInP 700 A 5x10 17 88 Base GaAs 800 Å 4x10 19 86 Collector GaAs 1 mm 2x10 16 84 Filled subcollector GaAs 1 mm 2x10 18 83 Etch layer AlGaAs AlAs, GaInP 500 A 3x10 18 82 Subcollector GaAs 1 mm 2x10 18 A cross-sectional diagram of the transistor is shown in Figure 11. The structure is generally the same as that of the first preferred embodiment, except that the space left following the removal of a portion of etch layer 83 (Figure 12) is filled with semiconductor 84 having a doping concentration on the order of that used for subcollector layer 82, rather than the much lighter doped layer 46 used in the first preferred embodiment. Additionally, the highly doped layer 84 is grown only to the top of the depression in layer 83 as shown in Figure 13. As in the first preferred embodiment the collector layer 86, base layer 88, emitter layer 90, buffer layer 92 and contact layer 94 are grown in a conventional manner atop layers 83 and 84 as shown in Figure 14. Similarly, in a third preferred embodiment shown in Figure 15, the subcollector layer 112 is even with the top of the undercut region. In this embodiment, the subcollector layer 112 is initially etched to form a mesa as shown in Figure 16. The etch layer 113 is then formed with the overgrowth process described above for the first preferred embodiment. Subsequently, the collector 116, base 118, emitter 120, buffer 122, and emitter contact 124 layers may be formed in a conventional manner atop layers 112 and 113. Two material structures that may be used in this embodiment are described in Table IIIa and Table IIIb. Element Generic Name Preferred Material Examples of Alternate Materials Approx. Layer Thickness Approx. Doping (cm -3 ) 124 Emitter contact InGaAs 700 A 1x10 19 122 Buffer GaAs 1000 A 5x10 18 120 Emitter AlGaAs GaInP 1000 A 5x10 17 118 Base GaAs 800 Å 2x10 19 116 Collector GaAs 1 mm 2x10 16 113 Etch layer AlGaAs AlAs, GaInP 3000 A undoped 112 Subcollector GaAs 1 mm 2x10 18 Element Generic Name Preferred Material Examples of Alternate Materials Approx. Layer Thickness Approx. Doping (cm -3 ) 124 Emitter contact InGaAs 700 A 1x10 19 122 Buffer GaAs 2000 A 1x10 19 120 Emitter AlGaAs GaInP 700 A 5x10 17 118 Base GaAs 800 Å 4x10 19 116 Collector GaAs 1 mm 2x10 16 113 Etch layer AlGaAs AlAs, GaInP 500 A 2x10 16 112 Subcollector GaAs 1 mm 2x10 18 The advantage of the second and third embodiments is that the distance d between the base layer (118 in Figure 15) and the highly doped subcollector layer (112 in Figure 15) is equivalent to the distance d' between the base layer 118 and the top of the undercut region. This is in contrast to the structure of Figure 7 where the distance d between the base layer 48 and the highly doped subcollector layer 42 is greater than the distance d' between the base layer 48 and the top of the undercut region. The structure of the second and third embodiments can be expected to have a slight advantage in capacitance over that of the first preferred embodiment. For example, assuming that C 1 is the base-collector capacitance of a transistor lacking an undercut region and C 2 is the base-collector capacitance of the first embodiment transistor, the ratio of the two is given by the following relation: where w is the width of the base mesa, L is the extent of the undercut beneath the base mesa, t is the depth of the undercut, d is the distance between the base layer and the highly doped subcollector, d' is the distance between the base layer and the undercut (so d' = d - t), and e g is the dielectric constant. In the first preferred embodiment of the invention shown in Figure 7, the distance d and the distance d' differ by the depth of the undercut, t. If d is 1 um, w is 4 um, L is 1 um and t is 0.1 um, the ratio of C 2 to C 1 is 0.725. In other words the capacitance of the undercut structure is only 72.5% of the capacitance of the structure without the undercut. However, if d' is the same as d, as in the second and third embodiments of the invention, the ratio of C 2 to C 1 is only 71.6%. It should be noted that the base-collector capacitance is greatly influenced by the depth or height of the undercut region. A depth of less than about 1000 Å results in little improvement in capacitance over a structure lacking an undercut, while an undercut depth of greater than approximately 1.5 um can result in a structure having dimensions unsuited to high frequency operation. Whatever the depth of the undercut region, the benefit of decreased base-collector capacitance is also dependent upon the material that fills the undercut region. It is preferable that a material having a low dielectric constant, such as air, fill the undercut to provide the lowest capacitance possible. However, it is often desirable to passivate the semiconductor surfaces of the undercut region with a dielectric such as Si 3 N 4 or SiO 2 . Preferably, this dielectric coating will conform to the surfaces of the undercut region and is thin enough to prevent complete filling of the undercut. Even a thin layer of air in the undercut provides a significant advantage in the capacitance of the structure. This approach is shown by nitride layer 68 in Figure 10. A few preferred embodiments have been described in detail hereinabove. For example, in the embodiments described herein, an emitter-up configuration is described, though one may appreciate that a collector-up transistor may be similarly fabricated. Internal and external connections can be ohmic, capacitive, inductive, direct or indirect, via intervening circuits or otherwise. Implementation is contemplated in discrete components or fully integrated circuits in silicon, gallium arsenide, or other electronic materials families, as well as in optical-based or other technology-based forms and embodiments. While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. For example, though AlAs, AlGaAs, and GaInP were used as etch layer materials, it may be appreciated that any material that can be removed without affecting the layers adjacent to the etch layer is suitable.

Claims: A method of fabricating a bipolar transistor comprising the steps of: forming a sub-collector layer 42 on a substrate 40; forming an etch layer 44 over the sub-collector layer 42; removing portions of the etch layer 44 to form an opening exposing a region of said sub-collector layer 42; forming a collector layer 46 over at least said exposed region of said sub-collector layer 42 to at least fill said opening; forming a base layer 48 over said collector layer 46; removing portions of said etch layer 44, and of said collector layer 46, and said base layer 48 if necessary to expose an edge of said etch layer 44; removing remaining portions of said etch layer 44 to form an undercut region between said sub-collector layer 42 and said base layer 46, whereby a capacitance between said collector layer 46 and said sub-collector layer 42 is reduced by the removal of said etch layer 44. A method of fabricating a bipolar transistor comprising the steps of: forming a sub-collector layer 82 on a substrate 80; forming an etch layer 83 over the sub-collector layer 82; removing portions of the etch layer 83 to form an opening exposing a region of said sub-collector layer 82; depositing a fill layer 84 on at least said exposed region of said sub-collector layer 82 to fill said opening; forming a collector layer (86) over said fill layer (84) and said etch layer (83); forming a base layer 88 over said collector layer 86; removing portions of said etch layer 83, said collector layer 86, and said base layer 88 to expose an edge of said fill layer 84; removing remaining portions of said etch layer 83, whereby a capacitance between said collector layer 86 and said sub-collector layer 82 is reduced by the removal of said etch layer 83. A method of fabricating a bipolar transistor comprising the steps of: forming a sub-collector layer 112 on a substrate 110; removing portions of the sub-collector layer 112 to form a mesa; forming an etch layer 113 over the sub-collector layer 112 in those regions where portions have been removed, thus having an exposed region of said sub-collector layer (112) where removed did not take place; forming a collector layer (116) over said etch layer and exposed region of said sub-collector layer (112); forming a base layer (118) over said collector layer (116); removing portions of said etch layer 113, said collector layer 116, and said base layer 118 to expose an edge of said sub-collector mesa; removing remaining portions of said etch layer 113, whereby a capacitance between said collector layer 116 and said sub-collector layer 112 is reduced by the removal of said etch layer 113. The method of any preceding claim, wherein said etch layer is selected from a group of compound semiconductors consisting of: aluminium arsenide, aluminium gallium arsenide having an aluminium content greater than approximately 40%, and GaInP. The method of claim 1 and claim 4 when dependent on claim 1, wherein said step of forming said collector layer 46 comprises forming said collector layer 46 in said opening and over a surface of said etch layer 44. The method of any preceding claim further comprising the steps of: prior to the step of removing portions of said etch layer 44, said collector layer 46, and said base layer 48: forming an emitter layer 50 over said base layer 48; forming a buffer layer 52 over said emitter layer 50; forming an emitter contact layer 54 over said buffer layer 52; forming an emitter contact metallization 56 on a region of said emitter contact layer 54, said emitter contact metallization 56 being substantially formed over said opening; removing portions of said emitter contact layer 54, said buffer layer 52, and said emitter layer 50 to form an emitter mesa from regions of said emitter contact layer 54, said buffer layer 52, and said emitter layer 50 substantially underlying said emitter contact metallization 56. The method of Claim 6, wherein the step of forming said emitter contact metallization 56 comprises forming an emitter contact metallization from a material comprising TiPtAu or AuGeNi. The method of claim 6 or 7 further comprising the step of: forming at least one base contact metallization region on said base layer 48 and adjacent to said emitter mesa. The method as claimed in any preceding claim, wherein the width of said exposed region of said sub-collector layer 42, 82, 112 extends beyond an edge of a high currentcarrying region substantially underlying said emitter mesa. The method of claim 8 further comprising the step of: forming a tensile layer 60 over said base layer 48 said base contacts and said emitter mesa, said tensile layer 60 comprising a material being in tensile stress. The method of claim 10, wherein step of forming said tensile layer 60 comprises forming said tensile layer 60 from a dielectric material. The method of claim 11, wherein step of forming said tensile layer 60 comprises forming said tensile layer 60 from a dielectric material selected from a group of materials consisting of: silicon nitride, silicon dioxide, polyimide, oxynitride. The transistor of Claims 10-12, wherein said undercut region is generally rectangular in shape.

Inventors: HENDERSON TIMOTHY S, HILL DARRELL G, HENDERSON, TIMOTHY S., HILL, DARRELL G.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1995
Main classification: H01L21
IPC codes: H01L21, H01L29