Video signal processing apparatus and method

Abstract: A video signal processing apparatus and method for converting a frame-unit video signal into a field-unit video signal includes a memory (116) for storing the frame-unit video signal, a control circuit (31) for controlling reading of the stored frame-unit video data from the memory so as to obtain the field-unit video signal having fields which are arranged in a desired order and a vertical filter (32) which receives the field-unit video signal read from the memory. The vertical filter shifts a centroid of a picture represented by the received video signal in accordance with at least one coefficient which is selectively set based upon the field order. The reading of the video signal may be controlled so as to operate as a delay device thereby eliminating the need for such delay in the vertical filter. When applied to a digital VTR or the like, the present apparatus prevents line flicker and suppresses plane flicker.

Description: This invention relates to methods and apparatus for video signal processing. A digital video tape recorder (hereinafter, a digital VTR) has been proposed for recording and/or reproducing video signals which utilizes analog-to-digital conversion and subsequent data compression. Figure 22 illustrates an example of such a digital VTR. As shown in Figure 22, a digital VTR 99 generally includes analog-to-digital (A-D) converters 1-3, a blocking shuffling circuit 4, a picture compression encoder 5, an error correction code adder 6, a modulator 7, a demodulator 13, an error corrector 14, a picture compression decoder 15, a deblocking-deshuffling circuit 16, and digital-to-analog (D-A) converters 17-19. The recording mode of the digital VTR 99 will be initially described below, after which the reproducing mode of the digital VTR will be described. In the recording mode, analog component video signals composed of a luminance signal Y and color difference signals U (B-Y) and V (R-Y) are respectively supplied to the A-D converters 1-3 so as to be converted therein into digital signals which are supplied to the blocking-shuffling circuit 4. From such converted digital output signals, the blocking-shuffling circuit 4 receives picture data in an effective area. (For example, an effective area or effective scanning period in the NTSC or the 525/60 system is the 240 lines from lines 23H to 262H in a first field and the 240 lines from lines 285H to 524H in a second field. On the other hand, in the PAL or 626/50 system, the effective scanning period is the 288 lines from lines 23H to 310H in a first field and the 288 lines from lines 335H to 622H in a second field.) Figure 23 illustrates the relationship between scanning lines in an effective area and an image plane thereof for the 525/60 system. The blocking-shuffling circuit 4 converts the received field-unit (interlaced) component picture data into frame-unit (non-interlaced) time division picture data which may be shuffled to enhance the data compression efficiency. Thereafter, such picture data is supplied to the picture compression encoder 5. The picture data received from the blocking-shuffling circuit 4 is compressed by the picture compression encoder 5 by use of discrete cosine transform (DCT) and variable-length encoding. Such compressed data is supplied to the error correction code adder 6, whereupon an error correction code is added to the compressed data. Such error correction code may be utilized for correcting an error produced during reproduction. An output data signal from the error correction code adder 6 is supplied to the modulator 7 which processes the received data in accordance with a predetermined recording modulation. A modulated data signal from the modulator 7 is supplied through a recording amplifier 8 to a recording head 9 so as to be recorded on a video tape 10. In the reproduction mode, data is reproduced from the video tape 10 by a reproducing head 11 and amplified by a reproduction amplifier 12 and thereafter supplied to the demodulator 13. The demodulator 13 demodulates the received data in a manner substantially opposite to that performed by the modulator 7 and supplies the demodulated data to the error corrector 14, whereupon an error correction operation is performed by using the error correction code added in the recording mode. The corrected data is supplied to the picture compression decoder 15 which processes the received data by use of variable-length decoding and inverse discrete cosine transform (IDCT) techniques in a manner substantially opposite to that performed by the picture compression encoder 5. An output signal from the picture compression decoder 15 is supplied to the deblocking-deshuffling circuit 16. The deblocking-deshuffling circuit 16 deshuffles the received data so as to restore the original arrangement of the data (that is, the data arrangement prior to being shuffled in the recording section) and deblocks the frame-unit time division picture data so as to form the original field-unit component picture data (that is, the field-unit component picture data supplied to the blocking-shuffling circuit 4). Output signals from the deblocking-deshuffling circuit 16 are supplied to D-A converters 17-19. Figure 24 illustrates the timing relationship between the input and output signals of the deblocking-deshuffling circuit 16 for a normal reproduction mode. More specifically, the input data signal to the deblocking-deshuffling circuit 16 is illustrated in Figure 24a, and the data signal outputted therefrom is illustrated in Figure 24b. As shown therein, the input picture data of each frame is outputted as picture data of two fields with a delay of one frame. As is to be appreciated, although data corresponding to only one output picture data signal is shown, three sets of data corresponding to Y, U and V may be outputted in parallel. The D-A converters 17-19 convert the received data signals to digital form. Further, the converters 17-19 may add to such signals a synchronizing signal and other such signals which, for example, may be obtained from a reference signal generator (not shown). Analog component video signals Y, U and V are respectively supplied from the D-A converters 17-19. In the above-described digital VTR, variable-speed reproduction may be performed by successively outputting picture data of one field with the use of a memory which may be utilized to store the picture data in the deblocking-deshuffling circuit 16. As an example, in a still reproduction mode, picture data of either field within a frame may be outputted twice within one frame. However, as is apparent from Figure 23 which illustrates the relationship between an image plane and scanning lines, picture data of one field is offset from that of the other field within a frame by an amount corresponding to one-half of a line interval. As a result, in the above example, although the picture data of either field is outputted twice within one frame, such same picture data is outputted during one field period at a position different by one half of a line interval from that of the other field period. Such situation produces line flicker at the field frequency. As a result, the picture is vibrated vertically with an amplitude corresponding to one half of a line interval. Additionally, line flicker may occur in a picture formed by selectively switching between a picture produced by successively outputting the first fields and a picture produced by successively outputting the second fields. That is, in this situation, a vertical positional deviation exists between the two types of pictures which corresponds to one-half of a line interval. Further, so-called plane flicker may occur when a frame formed of first and second fields is inserted between frames formed of successive first or second fields. In other words, plane flicker may occur when a picture having a vertically high resolution is inserted between pictures having a vertically low resolution due to fluctuations of the vertical resolution. GB-A-2 269 718 discloses a filter for changing field polarity in a video signal, i.e. for converting the order in which even and odd fields of a frame are outputted, in which a field is vertically shiftable so that a vertical displacement between input and output fields is suppressed. EP-A-0 454 460 discloses a video signal recording/reproducing apparatus which controls the number of repetition of a field in a variable speed mode. US-A-4 258 384 discloses techniques for maintaining the PAL field sequence in variable speed reproduction. Various respective aspects of the invention are defined in the appended claims. The above-described flicker may be suppressed or eliminated by selectively adjusting the respective centroids of the pictures of two fields. Accordingly, it is desirable to have a video signal processing apparatus which is adapted to selectively adjust the respective field centroids so as to eliminate or minimize line flicker and eliminate or suppress plane flicker. This invention provides a video signal processing apparatus for converting a frame video signal representing a plurality of video frames into a field video signal representing a plurality of video fields, said apparatus comprising: memory means for storing the fields of a frame of said frame video signal and for reading out the stored video signal as said field video signal; control means for controlling the order in which the fields of a frame of said field video signal are read from said memory means so as to arrange the fields in a desired order wherein a portion of the first field is stored at a first time in a first memory area of said memory means, said first memory area having a data storage capacity smaller than an amount of data of one field, and another portion of the first field is stored at a different time in a second memory area of said memory means, and a portion of the second field is stored in the second memory area after the stored portion of the first field is read out therefrom; and vertical filter means for receiving said field video signal read out from said memory means and for vertically shifting a centroid of a picture represented by the received field video signal in accordance with a coefficient selectively set based upon the field order. This invention also provides a video signal processing method for converting a frame video signal representing a plurality of video frames into a field video signal representing a plurality of video fields, said method comprising the steps of: storing the fields of a frame of said frame video signal in memory means and reading out the stored video signal therefrom as the field video signal; controlling the order in which the fields of a frame of said field video signal are read from said memory means so as to arrange the fields in a desired order wherein a portion of the first field is stored at a first time in a first memory area of said memory means, said first memory area having a data storage capacity smaller than an amount of data of one field, and another portion of the first field is stored at a different time in a second memory area of said memory means, and a portion of the second field is stored in the second memory area after the stored portion of the first field is read out therefrom; and filtering the field video signal read from said memory means by vertical filter means for vertically shifting a centroid of a picture represented by the received field video signal in accordance with a coefficient selectively set in accordance with the field order. According to embodiments of the present video signal processing technique, the write/read of data into/from the storage device is controlled such that an input frame-unit video signal is converted into a field-unit video signal having a desired field order, and a coefficient or coefficients are selectively changed in the vertical filter in accordance with such field order to change the filtering characteristic so as to prevent line flicker and to suppress plane flicker during variable-speed reproduction. The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figure 1 is a block diagram of a video signal processing apparatus according to an embodiment of the present invention; Figure 2 is a table which illustrates the relationship between control signals VFF, VFS and output fields; Figure 3 is a block diagram of a deblocking-deshuffling circuit for controlling the order of fields outputted therefrom which may be utilized in the video signal processing apparatus of Figure 1; Figure 4 is a diagram to which reference will be made in explaining write/read timing for a normal reproduction mode; Figures 5A and 5B are diagrams illustrating write/read control signals which may be utilized in the normal reproduction mode; Figure 6 is a diagram to which reference will be made in explaining write/read timing when data of first fields are successively outputted; Figures 7A and 7B are diagrams illustrating write/read control signals which may be utilized when data of first fields are successively outputted; Figure 8 is a diagram to which reference will be made in explaining write/read timing when data of second fields are successively outputted; Figure 9 is a diagram to which reference will be made in explaining write/read timing when the field order is inverted and data are outputted; Figures 10A and 10B are diagrams illustrating write/read control signals which may be utilized when the field order is inverted and data are outputted; Figure 11 is a block diagram of a vertical filter which may be utilized in the video signal processing apparatus of Figure 1; Figure 12 is a truth table illustrating values of output signals as a function of input signals for a control logic circuit of the vertical filter of Figure 11; Figure 13 is a modification of the vertical filter of Figure 11 wherein a line delay circuit is omitted by controlling the read timing of a memory in the deblocking-deshuffling circuit of Figure 3; Figure 14 is a block diagram of a control logic circuit of the vertical filter of Figure 13; Figure 15 is a truth table illustrating values of output signals as a function of input signals for the control logic circuit of Figure 13; Figures 16a to 16f are diagrams illustrating timing of signals and the amount in which the centroids are shifted for a 1/3 slow reproduction mode; Figures 17a to 17f are diagrams illustrating timing of signals and the amount in which centroids are shifted for a -1 reverse reproduction mode; Figure 18 is a block diagram of another vertical filter which may be utilized in the video signal processing apparatus of Figure 1; Figure 19 is a truth table illustrating a first set of values of coefficient multipliers as a function of input signals to a control logic circuit of the vertical filter of Figure 18, the amount in which the centroids are shifted and other information pertaining thereto; Figure 20 is a truth table illustrating a second set of values of coefficient multipliers a function of input signals to the control logic circuit of the vertical filter of Figure 18, the amount in which the centroids are shifted and other information pertaining thereto; Figure 21 is a truth table illustrating a third set of values of coefficient multipliers as a function of input signals to the control logic circuit of the vertical filter of Figure 18, the amount in which the centroids are shifted and other information pertaining thereto; Figure 22 is a diagram of a digital VTR to which the present video signal processing apparatus of Figure 1 may be applied; Figure 23 is a diagram to which reference will be made in explaining the relationship between scanning lines in an effective area and an image plane for the NTSC 525/60 system; Figures 24a and 24b are diagrams illustrating the timing relationship between an input signal and an output signal of a deblocking-deshuffling circuit in a normal reproduction mode; and Figure 24c is a diagram of a field identification signal. A video signal processing apparatus according to the present invention will now be described with initial reference to Figure 1. As shown therein, such video signal processing apparatus 97 includes a deblocking-deshuffling circuit 116, a microcomputer 31 and a vertical filter 32. Such apparatus may be utilized in recording and/or reproducing devices or the like, such as the digital VTR 99 of Figure 22. In this latter situation, the deblocking-deshuffling circuit 16 of the digital VTR 99 is replaced with the video signal processing apparatus 97. As a result, the output signal from the picture compression decoder 15 is supplied to the deblocking-deshuffling circuit 116 and output Y, U and V signals from the vertical filter 32 are respectively supplied to the D-A converters 17-19. The remaining elements of the digital VTR 99 may operate in a manner substantially similar to that previously described and, in the interest of brevity, will not be repeated herein. The video signal processing apparatus 97 will now be further described hereinbelow. The microcomputer 31 is adapted to supply an instruction signal to a capstan motor (not shown) so as to drive the same at a predetermined speed. The microcomputer 31 is further adapted to simultaneously supply control signals or flags VFF (video frame/field flag) and VFS (video first/second flag) to the deblocking-deshuffling circuit 116. Such control signals VFF and VFS may have either a relatively high value (H) or a relatively low value (L) and are utilized for designating output fields. In response to such control signals, the deblocking-deshuffling circuit 16 controls the order of the output fields. The VFF control signal may provide an indication as to whether both fields of a frame are outputted or whether only one of such fields is outputted twice within the respective frame period. For example, a relatively low value of the VFF control signal may indicate that only one of the two fields of a frame is outputted twice within the respective frame, and a relatively high value thereof may indicate that both fields of a frame are outputted. On the other hand, the VFS control signal may provide an indication as to which of the fields is outputted twice during a frame period or the order in which two fields of a frame are outputted. Figure 2 illustrates a relationship between the output fields and combinations of the control signals VFF and VFS. For example, as shown in Figure 2, if the control signals VFF and VFS each have a relatively high value (H), then the deblocking-deshuffling circuit 116 causes the first field and the second field to be outputted in this order. As another example, if the control signal VFF has a relatively low value (L) and the control signal VFS has a relatively high value (H), then the deblocking-deshuffling circuit 116 causes the first field to be outputted twice. The deblocking-deshuffling circuit 116 may be configured as illustrated in Figure 3. As shown therein, the deblocking-deshuffling circuit 116 may include a 1-field video random access memory (VRAM) 33, a 1/3-field VRAM 34, a write control circuit 35 and a read control circuit 36. The write control circuit 35 receives the control signals VFF and VFS and generates write control and address signals which are supplied to the appropriate one or ones of the VRAMs 33 and 34. As a result, input frame-unit picture data may be written into the VRAMs 33 and 34. The read control circuit 36 receives the control signals VFF and VFS and generates read control and address signals which are supplied to the appropriate one or ones of the VRAMs 33 and 34. As a result, the previously stored or written picture data may be read from the VRAMs 33 and 34 in field units. Such reading and writing of picture data may be performed so as to arrange the output field data in a desired order. Thus, the deblocking-deshuffling circuit 116 receives frame-unit picture data from the picture compression decoder 15 (Figure 22) and, in accordance with control signals VFF and VFS received from the microcomputer 31 (Figure 1), executes write and read control signals for supply to the VRAMs 33 and 34 so as to produce field-unit picture data having a desired field order which is supplied therefrom. Writing and reading operations performed by the deblocking-deshuffling circuit 116 for several modes or situations will now be described hereinbelow. Figure 4 illustrates the write/read timing for the VRAMs 33 and 34 during a normal reproduce mode. (In this and other similar figures in this application, that is, Figures 6, 8 and 9, solid and broken lines respectively represent writing and reading operations.) For the arrangement of Figure 4, the control signal VFF has a high level (H) and the control signal VFS has a high level (H) as indicated in Figure 2. In such arrangement, as shown in Figure 4, a portion of data such as the first 1/3 of the first field of the input data of each frame is stored or written into the 1/3-field VRAM 34 during an interval a, a portion such as the second 1/3 of such first field is written into the 1-field VRAM 33 during an interval b, and a portion such as the last 1/3 of such first field is written into the 1/3-field VRAM 34 during the interval b. The data previously written into the 1/3-field VRAM 34 during the interval a is read during an interval d. Such reading of the data during interval d occurs prior to the writing of data into the 1/3-field VRAM 34 during interval b. Data corresponding to the second field of the input data of each frame is written into the 1-field VRAM 33 during an interval c. The data previously written into the 1-field VRAM 33 during the interval b is read during half (such as the first half) of an interval e, and the data previously written into the 1/3-field VRAM 34 during the interval b is read during the other half of the interval e. Further, the data previously written into the 1-field VRAM 33 during the interval c is read during an interval f. Figures 5A and 5B respectively illustrate write control signals generated by the write control circuit 35 and read control signals generated by the read control circuit 36 for the write/read timing arrangement of Figure 4. Accordingly, the intervals a-f of Figures 5A and 5B correspond to those of Figure 4. Further, in these figures, write 1 represents a write control signal for the 1-field VRAM 33, write 2 represents a write control signal for the 1/3-field VRAM 34, read 1 represents a read control signal for the 1-field VRAM 33, and read 2 represents a read control signal for the 1/3-field VRAM 34. In Figures 5A and 5B, writing into and reading from the VRAMs 33 and 34 is performed when the corresponding control signal is at a relatively low level. Furthermore, the write/read operations may be performed on the input time-division picture data directly or on each component thereof. Figure 6 illustrates the write/read timing for the VRAMs 33 and 34 when data of the first fields are outputted successively. For such situations, the control signal VFF has low level (L) and the control signal VFS has a high level (H) as indicated in Figure 2. In the arrangement of Figure 6, data corresponding to the first field of the input data is written into the 1-field VRAM 33 during an interval c. Further, in such arrangement, the data previously written into the 1-field VRAM 33 during the interval c is read during the intervals f ' and f. Figures 7A and 7B respectively illustrate write control signals generated by the write control circuit 35 and read control signals generated by the read control circuit 36 for the write/read timing arrangement of Figure 6. Accordingly, the intervals c, f ' and f of Figures 7A and 7B correspond to those of Figure 6. Further, in these figures, write 1 represents a write control signal for the 1-field VRAM 33 and read 1 represents a read control signal for the 1-field VRAM 33. As with the control signals of Figures 5A and 5B, writing into and reading from the VRAM 33 for the arrangement of Figure 6 is performed when the corresponding control signals of Figures 7A and 7B are at relatively low levels. Figure 8 illustrates the write/read timing for the VRAM 33 when data of the second fields are outputted respectively. For such situation, the control signal VFF has a low level (L) and the control signal VFS has a low level (L) as indicated in Figure 2. In the arrangement of Figure 8, data corresponding to the second field of the input data is written into the 1-field VRAM 33 during an interval c. Further, in such an arrangement, the data previously written into the 1-field VRAM 33 during the interval c is read during the intervals f' and f. The write and read control signals for this arrangement are similar to those shown in Figures 7A and 7B. Figure 9 illustrates the write/read timing for the VRAMs 33 and 34 when data are outputted in an inverted or reversed field order. For this arrangement, the control signal VFF has a high level (H) and the control signal VFS has a low level (L) as indicated in Figure 2. The timing arrangement of Figure 9 is similar to that of Figure 4 and, as such, a further description thereof is omitted. The write and read control signals for this arrangement are shown in Figures 10A and 10B. As is to be appreciated, such control signals are similar to those of Figures 5A and 5B and, as such, a further description thereof is omitted. Thus, by utilizing the above-described arrangements for reading and writing so as to convert frame-unit picture data into field-unit picture data, the present deblocking-deshuffling circuit 116 may utilize VRAMs having a relatively small storage capacity (such as that which is able to store one 1/3 fields of data) as compared to that normally required (which may store two or more fields of data). Further, such present writing and reading control enables the output field data to be arranged or set in a desired or arbitrary order. Although in the above descriptions the writing and reading operations were performed in response to write and read control signals having low values, the present technique is not so limited. As an alternative, the present technique may be arranged so that writing and reading operations are performed in response to relatively high level control signals. Referring back to Figure 1, the microcomputer 31 further supplies the VFF and VFS control signals and a SFON (still filter on) signal to the vertical filter 32. The vertical filter also receives signals Y, U and V and a field identification signal (FLID) from the deblocking-deshuffling circuit 116. An example of such FLID signal is illustrated in Figure 24c. The vertical filter 32 is adapted to shift the centroid of a picture in a predetermined direction, such as in a vertical direction, in accordance with the SFON, VFF, VFS and FLID signals. Such vertical filter 32 may include a plurality of vertical filters each adapted to process one of the Y, U and V output signals from the deblocking-deshuffling circuit 116. Different embodiments of the present vertical filter will now be described hereinbelow. Figure 11 illustrates a vertical filter 95 which may be utilized in the video signal processing apparatus 97 (Figure 1). As shown therein, such vertical filter 95 includes 1H delay circuits 21 and 41, a control logic circuit 44, coefficient multipliers 22-25, adders 26 and 27, and switches 28, 42 and 43. An input signal, such as a Y output signal from the deblocking-deshuffling circuit 116 is supplied through an input terminal to the 1H delay circuit 41 and a low terminal of the switch 42. The 1H delay circuit 41 is adapted to delay the received signal by a predetermined time amount, such as that corresponding to the time associated with one horizontal line. A delay signal from the 1H delay circuit 41 is supplied to a high terminal (H) of the switch 42 and a low terminal (L) of the switch 43. The switch 42 is operable in accordance with a control signal DLY from the control logic circuit 44 so as to select either the H or L terminal. An output signal from the switch 42 is supplied to the 1H delay circuit 21 and coefficient multipliers 24 and 25. The coefficient multipliers 24 and 25 are adapted to respectively multiply the received signal by predetermined coefficients c and d. The 1H delay circuit 21, like the 1H delay circuit 41, delays the received signal and supplies the same to the coefficient multipliers 22 and 23, whereupon such delayed signal is respectively multiplied by predetermined coefficients a and b. Multiplied output signals from the coefficient multipliers 22 and 24 are supplied to the adder 26, whereupon such signals are added so as to form a summed signal which is supplied to a high terminal (H) of the switch 28. In a similar manner, multiplied output signals from the coefficient multipliers 23 and 25 are added to a low terminal (L) of the switch 28. The switch 28 is controlled in accordance with a control signal CONT from the control logic circuit 44 so as to select either the H or L terminal. An output signal from the switch 28 is supplied to the high terminal (H) of the switch 43. The switch 43 is controlled in accordance with the signal SFON received from the microcomputer 31 (Figure 1) and supplies an output signal therefrom to an output terminal. The control logic circuit 44 is adapted to receive signals VFF, VFS and FLID from the microcomputer 31 (Figure 1) and form control signals DLY and CONT in accordance with such received signals. As previously described, the control logic circuit 44 supplies the DLY signal to the switch 42 and supplies the CONT signal to the switch 28. As a result, the switch 42 selects either a delayed output signal from the 1H delay line 41 or the input signal from the input terminal, and the switch 28 selects either the H or L terminal thereof so as to supply therefrom either the output of the adder 26 or 27. Values of the DLY and CONT signals formed by the logic control circuit 44 as a function of the input signals VFF, VFS and FLID are illustrated in Figure 12. Also illustrated in this truth table are the contents or results of the processing performed by the vertical filter 95 as a result of each combination of the input signals. More specifically, the truth table of Figure 12 provides the eight (1-8) combinations of output signals for a variable-speed reproduction mode wherein the SFON signal has a relatively high (H) level. As a result, signals from the switches 28 and 42 are selectively changed depending upon which of the first and second fields is to be outputted as a first field or a second field so as to shift the centroid of the respective picture in four ways as hereinafter more fully described. In a normal reproduction mode, the SFON signal has a relatively low (L) level and the delayed output signal of the 1H delay line 41 is selected and supplied by way of the low (L) terminal of the switch 43 to the output terminal. Such signal or data is passed through the 1H delay line 41 during the normal reproduction mode so as to minimize the vertical shift of the picture at the switchover between normal and variable-speed reproduction. In the variable-speed reproducing modes, on the other hand and as previously described, the SFON signal has a relatively high (H) level. As a result, in this situation, the signal supplied from the switch 43 is processed by the portion of the vertical filter 95 including the 1H delay circuit 21, coefficient multipliers 22-25, and adders 26 and 27. Accordingly, the SFON signal effectively controls whether or not the input signal is processed or filtered by such portion of the vertical filter. Thus, the SFON signal controls whether such filtering is on or off. The signal supplied from the output terminal of the vertical filter 95 corresponds to the signal received by such vertical filter wherein the centroid of a picture corresponding thereto may be shifted by an amount due to the processing performed therein. More specifically, the vertical filter 95 operates such that the centroid positions of the respective pictures are rendered effectively fixed when pictures of the same fields are successively outputted, and such that the centroid position is selectively shifted in other situations as hereinafter more fully described. As a result, the vertical filter 95 enables variable-speed reproduced video signals to be obtained without any, or with a minimal amount of line flicker during both still and slow reproduction modes. Further, the present vertical filter 95 enables changes in the resolution or frequency characteristics to be diminished so that plane flicker may be suppressed when a frame of first and second output fields is inserted between frames of either successive first or successive second output fields. Figure 13 illustrates a modification of the vertical filter 95. As shown therein, the 1H delay circuit 41 is replaced by the read control circuit 36 of the deblocking-deshuffling circuit 116 which is operated to control the timing for reading data from the VRAM so as to effectively obtain the delay caused by the 1H delay circuit 41. The remaining portion of the modified vertical filter 95' is substantially similar to the vertical filter 95 and, as such, will not be further described herein. As a result, the vertical filter 95' is configured without the 1H delay circuit 41, thereby reducing the number of components and cost of the vertical filter. Figure 14 illustrates the control logic circuit 44 in more detail. As shown, such control logic circuit 44 includes inverters 102 and 104, an AND gate 106, OR gates 110 and 112, and EXCLUSIVE-OR (XOR) gates 108 and 114 which are connected as shown in Figure 14. More specifically, the signal SFON from the microcomputer 31 (Figure 1) is supplied to the inverter 102, whereupon the signal is inverted and supplied to one input of the OR gate 110. The signal FLID from the deblocking-deshuffling circuit 116 (Figure 1) is supplied to one input of the OR gate 112 and to the inverter 104 so as to be inverted. The signal VFF from the microcomputer 31 is supplied to one input of the XOR gate 108 and to the other input of the OR gate 112. The signal VFS from the microcomputer 31 is supplied to the other input of the XOR gate 108 and one input of the XOR gate 114. The inverted signal from the inverter 104 and an output signal from the XOR gate 108 are supplied to the AND gate 106 which, in turn, supplies an output signal to the other input of the OR gate 110. The output signal of the OR gate 110 is the DLY signal. An output signal from the OR gate 112 is supplied to the other input of the XOR gate 114 which, in turn, produces the CONT signal for supply therefrom. Figure 15 illustrates a truth table for the control logic circuit 44 of Figure 13. The table of Figure 15 indicates values of the output signals CONT and DLY for different combinations of input signals SFON, VFF, VFS and FLID. As an example, if SFON has a high (H) value and each of the other input signals (that is, VFF, VFS and FLID) has a low (L) value, then the CONT and DLY signals produced by the control logic circuit 44 each have a low (L) value. Furthermore, in this arrangement, the read timing is controlled so as to be delayed by 1H when DLY has a relatively high (H) value, and not to be delayed when DLY has a relatively low (L) value. An example of variable-speed reproduction will now be described with reference to Figure 16. Such Figure 16 illustrates the timing for a 1/3 slow reproduction mode. As shown therein, Figures 16a and 16b respectively illustrate input and output signals of the deblocking-deshuffling circuit 116, Figures 16c-16e respectively illustrate the signals FLID, VFS and VFF, and Figure 16f illustrates the control logic and the amount in which the centroid is shifted. More specifically, in a frame having periods or fields T1 and T2, a first field of frame 0 is outputted twice as shown in Figure 16b. (In particular, reference is made to the two left-most blocks labelled"0-1" of Figure 16b. Such "0-1" refers to the 0th frame and the 1st field.) As shown in Figure 16f, during the period T1, the control logic is (4) and the centroid of the picture corresponding to the respective field is shifted downward by 5/8 line; and during the period T2, the control logic is (3) and the centroid of the picture corresponding to the respective field is shifted downward by 9/8 line. (The control logic referred to in Figure 16f is described in Figure 12.) As a result of such shifting, the picture outputted as the latter-half second field is positioned so as to be 1/2 line lower than the picture of the former-half first field. As a result, the respective centroids are coincident with each other and, as such, line flicker is eliminated or reduced. In periods T3 and T4, the centroids of the respective pictures are each shifted downward by 5/8 line and, as a result, the positional relationship between the first and second fields is maintained which enables a natural picture to be obtained. During such periods T3 and T4, the control logic is (8) and (7), respectively. The centroid of the picture corresponding to the field or period T5 is shifted downward by 1/8 line and the centroid of the picture corresponding to the field or period T6 is shifted downward by 5/8 line. As a result, the picture outputted as the latter-half second field is positioned so as to be 1.2 line lower than the picture of the former-half first field, in a manner similar to that performed during the periods T1 and T2. As such, line flicker is eliminated or reduced. During such periods T5 and T6, the control logic is (2) and (1), respectively. The above-described processing is repeated every three frames thereafter. Thus, the present technique enables smooth slow reproduction to be performed throughout the frames without any line flicker. Furthermore, although a frame having first and second fields is inserted in the periods T3 and T4 between frames formed of successive first fields (T1 and T2) and frames formed of successive second fields (T5 and T6), plane flicker may be suppressed by the present technique. Figure 17 illustrates the timing of signals for a -1 reverse reproduction mode. As shown therein, Figures 17a and 17b respectively illustrate input and output signals of the deblocking-deshuffling circuit 116, Figures 17c-17e respectively illustrate the signals FLID, VFS and VFF, and Figure 17f illustrates the control logic and the amount in which the centroid is shifted. Figures 17a-17f are similar or correspond to Figures 16a-16f and, as such, a further explanation of Figures 17a-17f is omitted herein. In any event, the present technique enables satisfactory reproduced pictures to be obtained without any line flicker for the reverse reproduction mode of Figure 17 as for the slow reproduction mode. As previously described, the centroids are shifted by predetermined amounts such as 1/8. 5/8 or 9/8 of a line interval. An explanation as to how such amounts are determined will now be provided. In still or slow reproduction modes or the like, first and second fields of outputted pictures are generated from an original field which is either an odd or even field. (The first and second fields respectively correspond to odd and even fields. Such first/second and odd/even is used to aid in distinguishing between the outputted pictures and the original pictures.) In this situation, four arrangements are possible: 1. an odd field of the original picture is outputted during first field periods of outputted pictures, 2. an odd field of the original picture is outputted during second field periods of outputted pictures, 3. an even field of the original picture is outputted during first field periods of outputted pictures, and 4. an even field of the original picture is outputted during second field periods of outputted pictures. In arrangements 1 and 4 above, the first and second fields of the outputted pictures respectively correspond to the odd and even fields of the original pictures. As a result, the centroids need not be shifted. In arrangement 2, there is an upward shift of 1/2 line interval. Accordingly, in this arrangement, the centroids should be shifted downward by 1/2 line interval. Similarly, in arrangement 3, the centroids should be shifted upward by 1/2 line interval. It is difficult to shift centroids upwards as for the above arrangement 3. Therefore, as an alternative to shifting centroids up and down as described above, the centroids for all of the above 1-4 arrangements are shifted downward by an offset amount. One preferred such offset amount is 5/8 line interval. utilizing such offset amount causes the centroids for arrangements 1 and 4 to be shifted downward by 5/8 line interval, the centroid for arrangement 2 to be shifted downward by 9/8 line interval, and the centroid for arrangement 3 to be shifted downward by 1/8 line interval. Other offset amounts, in addition to 5/8 line interval, may be utilized. For example, 2/4 line interval may be used. However, a 2/4 line interval offset would produce a net shift of zero for arrangement 3 above. As a result, the resolution for this arrangement is not decreased as compared to the other arrangements and, as such, plane flicker due to such difference in resolution may arise. Another embodiment of the present vertical filter is illustrated in Figure 18. As shown therein, such vertical filter 195 includes a control logic circuit 144, 1H delay circuits 150 and 152, coefficient multipliers 154, 156 and 158, and an adder 160. More specifically, an input signal from the deblocking-deshuffling circuit 116 (such as a Y signal) is supplied through an input terminal 148 to the coefficient multiplier 154 and the 1H delay circuit 150 which is adapted to delay the received signal by a predetermined time amount such as that corresponding to the processing time associated with 1 horizontal line. A delayed signal from the 1H delay circuit 150 is supplied to the coefficient multiplier 156 and the 1H delay circuit 152, whereupon such received signa lis delayed in a manner similar to that performed by the delay circuit 150. A delayed signal from the delay circuit 152 is supplied to the coefficient multiplier 158. The control logic circuit 144 is adapted to receive input signals FLID, VFF, VFS and SFON from the microcomputer 31 and the deblocking-deshuffling circuit 116 (Figure 1) and generate control signals in accordance with such input signals. The control logic circuit 144 is further adapted to supply such control signals to the coefficient multipliers 154, 156 and 158. Each of the coefficient multipliers 154, 156 and 158 has a variable coefficient (K1, K2 and K3) which is selected in accordance with the received control signals. The variable coefficient multipliers respectively multiply the received input or delayed signal by the selected coefficient. The multiplied signals from the coefficient multipliers 154, 156 and 158 are added by the adder 160, whereupon the obtained summed signal is supplied to an output terminal 162 for supply therefrom. Such summed signal corresponds to the input signal wherein the centroid of a picture corresponding thereto may be shifted by an amount corresponding to the processing performed therein. Thus, in the vertical filter 195, coefficients K1 to K3 of the coefficient multipliers 154, 156 and 158 are selected by the control logic circuit 144. Figures 19 to 21 illustrate values for the coefficients K1 to K3, output signals or characteristics, the amount in which the centroid is shifted, and the contents of the output data as a function of the input signals the control logic circuit 144 (that is, VFF, VFS, FLID and SFON). Also indicated on Figures 19-21 is the control logic 1-9. That is, control logic 1-8 refers to the aforementioned logic in Figure 12, and control logic 9 corresponds to a normal reproduction mode. Data is passed through the 1H delay circuit(s) even in the normal reproducing mode so as to minimize the vertical shift which may otherwise be caused at the switchover from a normal reproduction to variable-speed reproduction. In the above-described circuit, a minimum vertical shift of 1/8 is utilized. However, other minimum vertical shift amounts may be utilized. Although the present technique was described in conjunction with a digital VTR, the present technique is not so limited and may be applied to a number of other devices. For example, the present technique may be utilized with a digital video disk player and so forth. Further, although the vertical filter 32 may have a plurality of portions or filters each adaptable for separately processing one signal (such as either the Y, U or V signal), the present invention is not so limited. As an alternative, the vertical filter may be configured so as to process all of the desired signals within a single portion or filter. Moreover, although it is preferred to have vertical filters for the Y, U and V signals as described above, the present technique is not so limited. For example, the present technique may utilize only a vertical filter for the Y signal. Furthermore, the present technique is not limited to only one type of system (such as the 525/60 system), but may also be applied to other systems such as the 625/50 system or a high definition (HD) system and so forth. Therefore, the present technique selectively adjusts the centroids of pictures so as to enable smooth variable-speed reproduction to be performed while preventing line flicker and suppressing plane flicker. Further, the circuit complexity of the vertical filter can be reduced by controlling the read timing of the memory which converts a frame-unit video signal into a field-unit video signal. Furthermore, since the VRAMs utilized by the present apparatus have a relatively small storage capacity, the size and cost associated therewith are minimized. In summary, embodiments of the invention provide a video signal processing technique which selectively adjusts centroids of respective fields so as to prevent or minimize line flicker and suppress plane flicker during a variable-speed reproduction mode in a digital VTR or the like. Embodiments of the invention provide a video signal processing technique as aforesaid which utilizes a video signal converter for converting an input frame-unit video signal into a field-unit video signal and a vertical filter for filtering an output video signal of the video signal converter, wherein the video signal converter executes write/read control of a storage device so as to control the field order of the output video signal in accordance with a desired order and wherein a coefficient or coefficients of the vertical filter may be selectively changed in accordance with the field order of the output video signal of the video signal converter. Embodiments of the invention provide a video signal processing technique as aforesaid which enables the storage device to have a storage capacity which is less than that normally used. Embodiments of the invention provide a video signal processing technique as aforesaid in which the timing for the reading of the storage device is controlled in such a manner so as to eliminate a delay device which may otherwise be utilized in the vertical filter.

Claims: A video signal processing apparatus for converting a frame video signal representing a plurality of video frames into a field video signal representing a plurality of video fields, said apparatus comprising: memory means (33, 34) for storing data from the fields of a frame of said frame video signal and for reading out the stored video signal as said field video signal; control means (35, 36) for controlling the order in which the fields of a frame of said field video signal are read from said memory means so as to arrange the fields in a desired order wherein a portion of the first field is stored at a first time in a first memory area (34) of said memory means, said first memory area having a data storage capacity smaller than an amount of data of one field, and another portion of the first field is stored at a different time in a second memory area (33) of said memory means, and a portion of the second field is stored in the second memory area after the stored portion of the first field is read out therefrom; and vertical filter means (32; 95) for receiving said field video signal read out from said memory means and for vertically shifting a centroid of a picture represented by the received field video signal in accordance with a coefficient selectively set based upon the field order. The video signal processing apparatus according to claim 1, wherein said apparatus includes means (21, 41) operable as delay means for said vertical filter means for controlling the timing at which said field video signal is read out therefrom. The video signal processing apparatus according to claim 1, wherein the coefficient of said vertical filter means is set such that the centroid of the picture is shifted vertically by an amount corresponding to n/8 of the interval between adjacent horizontal lines where n is an integer. A video signal processing method for converting a frame video signal representing a plurality of video frames into a field video signal representing a plurality of video fields, said method comprising the steps of: storing data from the fields of a frame of said frame video signal in memory means (33, 34) and reading out the stored video signal therefrom as the field video signal; controlling the order in which the fields of a frame of said field video signal are read from said memory means so as to arrange the fields in a desired order wherein a portion of the first field is stored at a first time in a first memory area (34) of said memory means, said first memory area having a data storage capacity smaller than an amount of data of one field, and another portion of the first field is stored at a different time in a second memory area (33) of said memory means, and a portion of the second field is stored in the second memory area after the stored portion of the first field is read out therefrom; and filtering the field video signal read from said memory means by vertical filter means (32; 95) for vertically shifting a centroid of a picture represented by the received field video signal in accordance with a coefficient selectively set in accordance with the field order. The video signal processing method according to claim 4, wherein means operable as delay means for said vertical filter means are operated to delay the field video signal for controlling the timing at which the field video signal is read out therefrom. The video signal processing method according to claim 4, including a step of setting the coefficient of said vertical filter means such that said centroid of a picture corresponding to the field video signal is shifted vertically by an amount corresponding to n/8 of the interval between adjacent horizontal lines where n is an integer.

Inventors: TAUCHI YOICHIRO, TAUCHI, YOICHIRO
Applicants: SONY CORP, SONY CORPORATION
Application year: 1995
Main classification: H04N9
IPC codes: H04N5, H04N9, G11B20