PLL circuit having shortened locking time

Abstract: Disclosed herein is a PLL circuit including a VCO controlled in oscillation frequency by a control voltage, a divider dividing in frequency an oscillation signal of the VCO by a frequency division ratio to produce a frequency-divided signal, a phase comparstor producing a phase comparison signal indicative of a difference in phase between a reference signal and the frequency-divided signal, and a filter converting the phase comparison signal into the control voltage to be used for controlling the VCO. The oscillation frequency of the VCO is thereby changed from a current frequency by variation of the frequency-division ratio and locked to a new frequency after a locking period of time elapses. There is further provided a control circuit which changes a time constant of the filter circuit a plurality of time during the locking period of time, this control circuit operating in response to the output of the phase comparator.

Description: BACKGROUND OF THE INVENTION The present invention relates to a Phase Locked Loop (PLL) circuit and, more particularly, to a PLL circuit employed in a frequency synthesizer tuning system. For a purpose of the realization of the multichannel or the digital communication such as a cordless telephone and a portable communication equipment, a frequency synthesizer tuning system employing a PLL circuit is widely used. The PLL circuit operates to tune a system to a desired channel and hence is required to have a high response speed. The time needed to switch the current channel over to a new channel, i.e. frequency-locking time, is thereby shortened. The PLL circuit includes a phase comparator and a loop filter to control the oscillation frequency of a voltage controlled oscillator (VCO) by comparing in phase a reference signal with a signal from a counter for dividing the oscillation signal of the VDO. The frequency-locking time thereby depends on the response speed of the PLL circuit. The transient response speed is determined by a loop gain, a natural angular frequency and a damping factor of the PLL circuit. Among these factors, the loop gain has the dominant input/output characteristic of the VCO and the phase comparator, and the damping factor mainly depends on a time constant of the loop filter. When the loop filter is constituted by an active type filter having an operational amplitier, an input resistor and a feedback circuit, the natural angular frequency ωn and the damping factor ζ are represented as follows: ωn = {(K·Kv/C1·R1)}1/2 ζ = {(K·Kv/C1·R1)}1/2 x (C1·R2/2) = ωn x (C1·R2/2) where K and Kv denote the phase comparator gain and the VCO conversion gain, respectively, and R1, C1 and R2 represent an input impedance, a feedback capacity and a resistance of the active filter. The damping factor depends on two time constants C1·R1 and C1·R2. In general, to make the frequency-locking time small, the damping factor ζ is set to approximately 0.7. Referring to Fig. 7 showing an example of the transient response speed of a PLL circuit, when the damping factor ζ is set to be large, for example, 2.0, since the natural angular frequency ωn is also large, the first transition rapidly occurs. Although the time to shift from the initial frequency fol to the set frequency fo2 is short, the compensation sensitivity with respect to a minute frequency deviation is low and hence the convergence time to obtain the final stable state is long, thereby taking a long locking time TL. Further, since the equivalent noise bandwidth of the loop is large, the noise component in the high frequency of the VCO can not be sufficiently eliminated, the carrier/ noise ratio (C/N ratio) is thus deteriorated. When the damping factor ζ is small, for example, 0.3, the natural angular frequency ωn is also small, the first transition delays and hence the time to shift from the initial frequency fol to the set frequency fo2 is long, thereby resulting in the long locking time TL. When the damping factor ζ is in the vicinity of 0.7, the time to shift from the initial frequency fol to the set frequency fo2 is moderate. However, the compensation sensitivity with respect to the frequency deviation is high, the convergence time to obtain the final stable state is hence short, realizing the minimum locking time TL. Referring to Fig. 6, a conventional PLL circuit includes a synthesizer unit 1, an active type filter 2 as a loop filter which generates a voltage control signal VC in response to a control signal CP from the unit 1, and a VCO 3 for outputting an oscillation signal O in response to the voltage control .signal VC. This signal O is used for tuning. The unit 1 has a phase comparator 11 for carrying out the phase comparison between a reference signal R and a frequency division signal F to output a phase error signal D, a charge pump circuit 12 for converting the phase error signal D into the control signal CP, and a frequency-divider 13 which receives the oscillation signal O and divides it by a frequency division ratio set therein to produce the frequency division signal F. The filter 2 includes an inverting operational amplifier Al, an input resistor R1, and a feedback circuit composed of a resistor R2 and a capacitor C1 which are connected in series between the input and output of the inverting amplifier Al. The PLL circuit as shown in Fig. 6 operates to lock the frequency division signal F in phase with the reference signal R. Accordingly, the VCO 3 produces a signal O having a frequency fo which is equal to the frequency fr of the reference signal R multiplied by N, i.e., fo = N x fr, wherein N indicates the frequency-division ratio set into the divider 13. When the frequency division ratio N of the divider 13 is changed from the first frequency division ratio N1 to N2 in order to tune to another channel, the frequency of the frequency division signal F is varied accordingly. The phase comparator 11 thereby detects a difference in phase between the reference signal R and the varied frequency division signal F and produces the signal D indicative . of that difference. This signal D causes the VCO to change the frequency of the oscillation signal O through the charge pump circuit 12 and the filter 2. As a result, the VCO 3 oscillates and produces the signal O having a oscillation frequency fo2·that is equal to N2 x fr. The respective values of the capacitor C1 and resistors R1 and R2 correspond to C1, R1 and R2 of the equation (2), respectively, and are selected such that the damping factor ζ is in the vicinity of 0.7, as described above. The frequency-locking time of the PLL circuit is, however, constant. The frequency-locking time is required to be further shortened for the multichannelization of a tuner. To this end, a PLL circuit is disclosed in Japanese Patent Laid-open Publication No. Hei 2-94710 in which the reference signal frequency is raised only when the transient state (unlocked state) at the time of frequency switching is reached and is again lowered to the original frequency after the locking. Another PLL circuit is shown in Japanese Patent Laid-open Publication No. Sho 60-16731, Japanese Patent Laid-open Publication No. Sho 62-92521 and Japanese Patent Laid-open Publication No. Hei 3-191642, for the purpose of adopting the two-mode damping factor switching system in which the damping factor is switched by means of the charge pump circuit, the switches and others in accordance with the locked or unlocked state before and after the locking of the PLL in order to achieve the optimization of the locking time. From EP-A-0 458 269 a PLL circuit is known which has a lock-up time shortening circuit switching the lock-up time to a lower fixed level when the dividing ratio has changed as long as the control voltage does not change its direction. EP-A-0 444 237 shows another PLL circuit for radio devices intended for improving the response when significantly changing the radio frequency from one radio channel to another radio channel by using two or more smaller changes instead of one larger change in frequency. From EP-A-0 461 358 a further PLL circuit is known in which the output frequency of the VCO is changed incrementally by changing the value of a resistor in a loop filter step by step after a change of the dividing ratio. Thus, although various types of PLL circuits are proposed, there are many performance degradation factors such as the unstable locking during frequency switching or the malfunction due to the jittering and the difficult adjustment. Moreover, it is impossible to reduce the locking time determined by an optimum value of the loop constant more than ever. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an improved PLL circuit. It is another object of the present invention to provide a PLL circuit having a shortened frequency-locking time with a stabilized operation. A PLL circuit according to the present invention is characterized in that the control circuit detects an overshoot an undershoot, respectively, at the end of the first period of time and changes the time constant to a higher value during a second period of time, and thereafter gradually achieves corresponding changes for the further undershoots and overshoots, respectively, until the maximum time constant is reached. In more detail, the filter circuit has a variable resistance circuit whose resistance value determines the time constant thereof. When the frequency-division ratio of a divider is changed, the control circuit causes the variable resistance circuit to have a small resistance value. The time constant is thereby made small, so that the frequency of an oscillation signal from the VCO is changed quickly. When an overshoot or an undershoot occurs in frequency of the oscillation signal, the control circuit detects that by use of an output signal from a phase detector and then makes the resistance value of the variable resistance circuit large. Similar operations are performed each time the overshoot or undershoot occurs. As a result, the locking time is shortened. BRIEF DESCRIPTION OF THE DRAWINGS The above arid other objects, features and advantages of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram showing a PLL circuit according to a first embodiment of the present invention; Fig. 2 is a circuit diagram illustrative of a switch control circuit illustrated in Fig. 1; Fig. 3 is a time chart showing the operation of the switch control circuit illustrated in Fig. 2;. Fig. 4 is a graph illustrative of transient response characteristic of the PLL circuit shown in Fig. 1; Fig. 5 is a block diagram showing a PLL circuit according to a second embodiment of the present invention; Fig. 6 is a block diagram showing a prior art PLL circuit; and Fig. 7 is a characteristic representation showing an example of the transient response characteristic of the prior art PLL circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 1, there is shown a PLL circuit according to a first embodiment of the present invention, in which the same constituents as those shown in Fig. 6 are denoted by the same reference numerals to omit the further description thereof. In the present PLL circuit, a synthesizer unit 1 is fabricated as a monolithic semiconductor integrated circuit device and further includes, in addition to the phase comparator 11, the charge pump circuit 12 and the divider 13, a control unit 17, a switch control circuit 15, four switches S1 to S4, and five resistors R11 to R15. Since one or more resistors of the resistors R11 to R15 operate as an input resistor of the filter circuit 2A, this filter circuit 2A omits the input resistor. It is to be further noted that the phase comparator 11 produces two phase comparison signals U and D, as well known in the art. The signal U indicates an up-command and takes an active low level when the reference signal R advances in phase to the signal F. On the other hand, the signal D indicates a down-command and takes an active low level when the signal F advances in phase to the reference signal R. The switch control circuit 15 responds to the output signals U and D from the phase comparator 11 and a control signal PS from the controller 11 and produces switching control signals U1 to U4 for controlling the respective switches S1 to S4. Each of the switches S1 to S4 has one end connected to the output of the charge pump circuit 12 and the other end connected to an associated one of the resistors R11 to R14. The control circuit 17 produces a frequency-division ratio data to set the divider 13. It is to be noted that the control unit 17 sets the ratio data for the divider 13 via a bus 17-1 whiling producing the control signal PS of a one-shot pulse. Referring to Fig. 2, the switch control circuit 15 includes eight D-type flip-flops F1 to F8 each including a set terminal S and four OR gates G1 to G4 which are connected as shown. The respective outputs of the OR gates G1 to G4 are derived as the respective switching control signals U1 to U4. Each of the flip-flops F1 to F4 holds its output Q at the high level so long as its set terminal S receives the high level and fetches and outputs an input at its data terminal D in response to the falling edge of a clock signal applied to its clock terminal C while the set terminal S is being at the low level. In operation, assume that the present PLL circuit is in a phase-locked state in which the VCO is producing its output signal O having a frequency fo as shown in Fig. 4. Both of the phase comparison signals U and D from the phase comparator 11 are thereby at the high level. When the control unit 17 is commanded to tune to a new channel that requires the VCO 3 to produce the oscillation signal O of a frequency f1, the unit 17 produces and sets new frequency-division ratio data into the divider 13 while producing the control signal PS at a timing t0 as shown in Figs. 3 and 4. All the flip-flops F1 to F8 (Fig. 2) thus change the respective output Q to the high level as shown in Fig. 3. Accordingly, all the switching control signals U1 to U4 are changed to the high level, as shown in Fig. 3, to thereby turn all the switches S1 to S4 ON. All the resistors R11 to R15 are thus connected in parallel to one another, so that total resistance value thereof becomes a minimum value R1A. Since the new division ratio is smaller than the previous one, the phase comparator 11 produces the active low up-command signal U indicative of a difference. in phase between each clock of the reference signal R and the corresponding one of the output F of the divider 13, as shown in Fig. 3. At this time, although the flip-flop F1 produces the low level output Q, the flip-flop F5 maintains its output Q at the high level, so that the switching control signal U1 takes the high level. The remaining switching control signals U2 to U4 also keep the high level. Therefore, the charge pump circuit 12 charges the filter 2A through the combined resistors R1 to R5 taking the minimum resistance value R1A. As a result, the oscillation frequency of the VCO is changed toward the frequency f1 at a maximum speed, as shown in Fig. 4. When the oscillation frequency of the VCO exceeds : the frequency f1 at a time t1 as shown in Fig. 4, the phase comparator 11 then outputs the active low down-command signal D in place of the up-command signal U, as shown in Fig. 3. In response thereto, the flip-flop F5 produces the low level output Q. The switching control signal U1 is thereby changed to the low level to turn the switch OFF. The resistor R11 is thus disconnected from the charge pump circuit 12. Although the flip-flop F6 also produces the low level output Q, the flip-flop F2 had received the high level at its set terminal S when the first down-command signal D was produced, so that the output Q of the flip-flop F2 has been held at the high level. The remaining switching control signals U2 to U4 maintain the high level, accordingly. The total resistance value is thereby determined by the resistors R12 to R15 and thus becomes higher than the minimum resistance value RA1. The oscillation frequency of the VCO 3 is in turn decreased at speed that is slower than the maximum speed. Similarly, each time the phase comparator 11 changes its output from a down-command to an up-command and vice versa, the switching control signals S2 to S4 are changed in that order to the low level, as shown in Fig. 3. In other words, the resistance value determined by the resistors R11 to R15 is gradually increased from the minimum value R1A to the maximum value R1D at the respective timings t0 to t4 as shown in Fig. 4. As described above, the natural angular frequency ωn and the damping factor ζ which. determine the locking time of the PLL circuit are proportional to the time constant of the filter which is in turn proportional to the square root of the resistance value r1 determined by the resistors R11 to R15 group 17 according to this embodiment. In the present embodiment, therefore, the damping factor ζ is changed to 2.0, 1.5, 1.0 and 0.7 at the timings t0, t1, t2 and t3, respectively, as shown in Fig. 4. Accordingly, the locking time from the frequency fo to that f1 is shortened. For instance, the locking time according to the present embodiment is less than 5 mS, whereas the prior art circuit as shown in Fig. 6 requires a locking time of 40 ms. The present PLL circuit is thus greatly advantageous in being used in a cordless telephone system. Referring to Fig. 5, there is shown a PLL circuit according to a second embodiment of the present invention, in which the same constituents as those shown in Fig. 1 are denoted by the same reference numerals to omit the further description thereof. In this embodiment, the synthesizer IC 1 includes two charge-pump terminals CP1 and CP2 and four transfer gates X1 to X4. The terminal CP1 is directly connected to the output of the charge pump circuit 12, and the transfer gates X1 to X4 are connected in parallel between the output of the circuit 12 and the terminal CP2. Although the transfer gates X1 to X4 are controlled to be on or off by the respective control signals U1 to U4, the conductive resistances thereof are designed to be a certain value. In this embodiment, further, a filter circuit 2B includes two input resistors R15 and R16 connected respectively to the terminals CP1 and CP2. Accordingly, when a new frequency-division ratio data is set into the divider 13, all the transfer gates X1 to X4 are turned ON, so that the time constant of the filter becomes a minimum value. Thereafter, the time constant is changed step by step in a manner as described in the first embodiment. In the embodiment as shown in Fig. 5, since the synthesizer IC 1B requires no resistors, the chip area is made small as compared to that shown in Fig. 1. Moreover, by changing the resistance value of the resistor R15 or R16, a desired change in time constant is obtained suitable for a target system. For example, the combination of the switch S and the resistors R as shown in Fig. 1 may be replaced by a transfer gate transistor having a desired conductive resistance value. In this connection, the transfer gates X1 to X4 as shown in Fig. 5 may have different conductive resistance values from one another. The resistor R16 may be omitted.

Claims: A PLL circuit comprising: a phase comparator (11) producing an output signal indicative of a difference in phase between a first signal and a second signal; a circuit means having a time constant and converting said output signal into a control voltage; an oscillation circuit (3) producing an oscillation signal controllable by said control voltage; and a frequency-division circuit (13) dividing said oscillation signal by frequency-division ratio data set therein and producing said second signal; said circuit means including a switching circuit (15) for, during a first period of time, setting said time constant to a value corresponding to a maximum speed of oscillation frequency change, in response to a change in the frequency-division ratio data, characterized in that the control circuit detects an overshoot and undershoot, respectively, at the end of the first period of time and changes the time constant to a higher value during a second period of time, and thereafter gradually achieves corresponding changes for the further undershoots and overshoots, respectively, until the maximum time constant is reached. The circuit as claimed in claim 1, wherein said first change of said output signal represents that one of said first and second signals is in advance in phase of the other of said first and second signals by changing the frequency-division ratio data, and said second change of said output signal represents that said other of said first and second signals is in advance in phase of said one of said first and second signals. The circuit as claimed in claim 1, wherein said output signal of said phase comparator (11) includes a first command signal commanding said oscillation circuit (3) to increase a frequency of said oscillation signal and a second command signal commanding said oscillation circuit (3) to decrease the frequency of said oscillation signal, said first change of said output signal being indicated by generation of one of said first and second command signals, and said second change of said output signal being indicated by generation of the other of said first and second command signals.

Inventors: KONDOU TOYOO, KONDOU, TOYOO, KONDOU, TOYOO, C/O NEC YAMAGATA, LTD.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1995
Main classification: H03L7
IPC codes: H03L7