Sampling and holding circuit

Abstract: An analog input voltage is inputted to the first sampling and holding circuit and the second sampling and holding circuit is connected to an output of the first sampling and holding circuit. The output of the first and second sampling and holding circuits are inputted to a multiplexer which alternatively outputs the output of first sampling and holding circuit or the second sampling and holding circuit. When one of the first and second sampling and holding circuits is refreshed, the output of the other sampling holding circuit is selected to be outputted from the multiplexer.

Description: The present invention relates to a sampling and holding device for holding an analog or multi-valued voltage during a predetermined timing or for transferring the voltage up to a predetermined stage. Background of the Invention The inventors of the present invention have proposed a sampling and holding device for analog voltage Japanese Patent application Hei No. 05045900 (Figure 13). This device uses two sets of 3 stage serial inverters for holding data in good accuracy. This type of device has disadvantages of large circuit size due to many inverters for each sampling and holding circuit, particularly in the technical field if image processing or voice processing, a lot of data parallelly processed along time sequence or of two dimension. As shown in fig. 13, this sampling and holding device has a) a sampling circuit S1 with an odd number of serial MOS inverters input and output of which are connected through a feedback capacitance with each other, b) a switch SW1 for connecting an input voltage to the sampling circuit through a coupling capacitance CC2 and c) a switch for connecting the sampling circuit SI and the coupling capacitance CC2. The data is held by capacitances CF1, CF2, CC1 and CC2 as electrical charges. The electrical charge may remain in the MOS or in the capacitances so as to cause an offset voltage. It is necessary to make refreshment in order to delete the offset by short-circuiting input and output of the sampling and holding circuit S1 and H1. A refresh noise is occurred by the refreshment at the output of the sampling and holding circuit. A similar sampling and holding device comprising two series connected sampling and holding circuits is disclosed in EP-A-0 400 725. Summary of the Invention The present invention has an object to provide a sampling and holding device free from refresh noise. According to the present invention, there are provided a sampling and holding circuit as specified by claim 1. Brief Description of the Drawings Figure 1 is a block diagram showing the first embodiment of a sampling and holding device according to the present invention; Figure 2 is a circuit diagram of the first sampling and holding circuit of the first embodiment; Figure 3 is a circuit diagram showing the second sampling and holding circuit of the first embodiment; Figure 4 is a circuit diagram of a multiplexer in the first embodiment; Figure 5 is a circuit diagram of an inverter in the first embodiment; Figure 6 is a circuit diagram of the first switch in the first embodiment; Figure 7 is a circuit diagram of the second switch in the first embodiment; Figure 8 is a circuit diagram of a reference voltage generating circuit in the first embodiment; Figure 9 is a graph showing a characteristic of a reference voltage generating circuit. Figure 10 is a timing chart showing the performance of the second embodiment; Figure 11 is a circuit diagram showing the first sampling and holding circuit of the second embodiment; Figure 12 is a timing chart of the circuit in figure 11; and Figure 13 is a circuit diagram showing a conventional sampling and holding device. Preferred Embodiment of the Present Invention Hereinafter, an embodiment according to the present invention is described with referring to the attached drawings. In Figure 1, a sampling and holding circuit has the first sampling and holding circuit SH1, the second sampling and holding circuit SH2 and multiplexer MUX, and an input voltage Vin is inputted to the first sampling and holding circuit SH1. The second sampling and holding circuit SH2 receives an output of the first sampling and holding circuit. The multiplexer MUX receives outputs of the first and the second sampling and holding circuits and alternatively outputs one of the outputs. A sampling signal Ss, holding signal Sh, the first refreshing signal Rf1 and the second refreshing signal Rf2 are inputted to the first sampling and holding circuit SH1, and the sampling signal Ss and first refreshing signal Rf1 are inputted to the second sampling and holding circuit SH2. Sampling signal Ss executes sampling in sampling and holding circuits SH1 and SH2, and holding signal Sh executes holding in sampling and holding circuit SH1. This sampling corresponds to the data holding by S1 of the circuit in Figure 13, and the holding corresponds to the data holding by H1 in Figure 13. Sampling and holding circuit SH 2 receives the input from the sampling and holding circuit SH1, the input voltage Vin reaches SH2 with a delay time of one sampling and holding timing. During this delay time, the multiplexer MUX introduces the output of SH2 instead of SH1 to the output OUT of the multiplexer MUX, when SH1 is refreshed. There is no influence of the refresh noise in SH1. After the refreshment, MUX introduces the output from SH1 again. SH2 can be refreshed in any time when SH1 is used. Figure 2 is a circuit diagram showing the first sampling and holding circuit. Input voltage Vin is connected to a sampling circuit S11 through a switch SW11 and coupling capacitance CC11, and output of sampling circuit S11 is connected to a holding circuit H11 through switch SW12 and coupling capacitance CC12. The sampling circuit S11 is a serial circuit of three stages MOS inverters INV11 to INV13, as shown in Figure 5. The output of the final stage INV13 is fed through a feedback capacitance Cf11 back to the input of the first stage INV11. Since the inverters INV1 to INV2 have high gain of amplification, the output of S11 has good linearity and is an inverse of the input, that is, (Vdd - Vin). Vdd is the voltage of the electrical source for the inverters. The holding circuit H11 is a serial circuit of the stages MOS invereters INV11 to INV13, similar to S11, as shown in Figure 5. The output of the final stage INV13 is fed through a feedback capacitance Cf12 back to the input of INV11. When switch SW12 is closed, Vin as it is, that is, an inverted output of S11 is generated at the output of H11. The sampling and holding circuit SH1 has switches SW13 to SW16 for refreshment of capacitances CC11, CC12, Cf11 and Cf12. When switches SW15 and SW16 are closed, refreshment is performed by impressing equal voltages on opposite terminals of capacitances Cf11 and Cf12. Switches SW13 and SW14 impress the reference voltage Vstd generated by a circuit Gstd to CC11 and CC12 so as to reset the inputs of S11 and H11 to be the reference voltage. In Figure 8, the circuit Gstd consists of a circuit INV6 of a plurality of MOS inverters of even number of stages and a feedback capacitance CF3 shortcircuiting the input and output of the circuit. Figure 9 is a graph showing how the reference voltage Vstd is determined. Vstd is a crossing point of a input/output characteristics curve of 3 stages inverters and a straight line meaning that input and output voltages are equal. Usually, it is preferable to define a condition of Vstd = Vdd/2. Further, the circuit Gstd includes a refresh switch SW3 for connecting the opposite terminals of the capacitance CF3 and the circuit INV6. The accuracy of the reference voltage Vstd is compensated by the refreshment executed by the switch SW3. In order to improve the capacity of electrical charge of S11, an additional capacitance Cad 11 is connected between switch SW11 and capacitance C11, and the other terminal of Cad 11 is connected to the reference voltage Vstd. In order to improve the capacity of electrical charge of H11, an additional capacitance Cad 12 is connected between switch SW12 and capacitance CC12, and the other terminal of Cad12 is connected to the reference voltage from Gstd. When the switches SW13 and SW14 are closed, equal voltages are impressed on the opposite terminals of Cad 11 and Cadl2 so that the capacitances are refreshed. Sampling signal Ss and holding signal Sh are inputted to switches SW11 and SW12, respectively. When Ss becomes high level, SW11 is closed, when Sh becomes high level, SW12 is closed. Ss and Sh are inputted at a timing shown in a timing chart of Figure 10, and an output Ds1 of the sampling circuit S11 and output Dh1 of holding circuit H11 are generated. When a value of Vin is "a" at the timing that Ss is inputted, " a" is kept as Ds1. When Sh is input, "a" is transferred to a holding circuit and kept as Dh1. The first refresh signal Rfl consists of two signals Rf11 and Rf12. Signal Rf11 is inputted to switch SW15, and signal Rf12 is inputted to switch SW13. Rf1 refreshes S11 at an intermittent timing on every several times of sampling and holding. As soon as the refreshment is completed, Ss is inputted so that the sampling is started. Rf12 and Rf11 become high level simultaneously, and Rf12 becomes low level a little after that Rf11 becomes low level. In order to perform the refreshment of capacitance CC11, it is necessary to keep a voltage of opposite terminals in constant, but there is a possibility that charged voltage is impressed to CC11 in a transient period, when Rf11 and Rf12 are finished in the same time. This unexpected charging is prevented by the above duration of Rf12. The second refresh signal Rf2 consists of signals Rf21 and Rf22. Signal Rf21 is inputted to switch SW16, and signal Rf22 is inputted to switch SW14. Rf2 refreshes H11 at an intermittent timing on every several times of sampling and holding. As soon as the refreshment is completed, Sh is inputted so that the holding is started. Rf22 and Rf21 become high level simultaneously, and Rf22 becomes low level a little after that Rf21 becomes low level. In order to perform refreshment of capacitance CC12, it is necessary to keep a voltage of opposite terminals in constant, but there is a possibility that charged voltage is impressed to CC12 in a transient period, when Rf21 and Rf22 are finished in the same time. This unexpected charging is prevented by the above duration of Rf22. Figure 3 is a circuit diagram showing the second sampling and holding circuit SH2. The output of the sampling and holding circuit SH1 is connected to a sampling circuit S21 through an switch SW21 and coupling capacitance CC21. An output of sampling circuit S21 is connected to a holding circuit H21 through a switch SW22 and coupling capacitance CC22. The sampling circuit S21 is a serial circuit of three stages MOS inverters INV11 to INV13, as shown in Figure 5. The output of the final stage INV13 is fed through a feedback capacitance Cf21 back to the input of the first stage INV11. Since the inverters INV11 to INV13 have high gain of amplification, the output of S21 has good linearity and is an inverse of the input, that is, (Vdd-Vin). The holding circuit H21 is a serial circuit of three stages MOS inverters INV11 to INV13, similar to S21, as shown in Figure 7. The output of the final stage INV13 is fed through a feedback capacitance Cf22 back to the input of INV11. When switch SW22 is closed, Vin as it is, that is, an invereted output of S21 is generated at the output of H21. The sampling and holding circuit SH2 has switches SW23 to SW26 for refreshment of capacitances CC21, CC22, Cf21 and Cf22. When switches SW25 and SW26 are closed, refreshment is performed by impressing equal voltages on opposite terminals of capacitances Cf21 and Cf22. Switches SW23 and SW24 impress the reference voltage Vdd/2 (a half of source voltage Vdd) to CC21 and CC22 so as to reset the inputs of S21 and H21 to be the reference voltage. In order to improve the capacity of electrical charge of S11, an additional capacitance Cad 21 is connected between switch SW21 and capacitance CC21, and other terminal of Cad 21 is connected to the reference voltage Vstd generated by the circuit Gstd. In order to improve the capacity of electrical charge of H21, an additional capacitance Cad22 is connected between switch SW22 and capacitance CC22, and other terminal of Cad22 is connected to the reference voltage from the circuit Gstd. When the switches SW23 and SW24 are closed, equal voltages are impressed on the opposite terminals of Cad 21 and Cad22 so that the capacitances are refreshed. Sampling signal Ss is inputted to the switches SW21 and SW22 so that the switches are closed when Ss becomes high level. The sampling and holding circuit SH2 takes the output of SH1 as an output Ds2 synchronously to the sampling timing of SH1. The timing of the output Ds2 is delayed by one sampling timing, as shown in Figure 10. As shown in Figure 4, the outputs Dh1 and Ds2 and the signal Rf22 are inputted to the multiplexer MUX, and MUX alternatively passes Dh1 or Ds2 in response to the high and low level of Rf22. MUX has a pair of MOS switches MS1 and MS2 to which Dh1 and Ds2 are inputted, respectively. MS1 is closed when Rf22 is low level, and M22 is closed when Rf22 is high level. Each MOS switch is composed of nMOS and pMOS serially connected from Vdd to the ground and controlled by a pair of signals of inverse polarity to be inputted to gates of the nMOS and pMOS. An invereted signal is generated by inputting Rf22 to a MOS inverter INV3. When holding circuit H11 of SH1 is refreshed, Ds2 is outputted from MUX as the final output Dout. After the refreshment, MUX introduces the output from SH1 again. It is possible to continuously output Vin as the final output Dout, without any influence of the refresh noise in SH1. SH 2 can be refreshed in any time when SH1 is used. As shown in the circuit of inverters INV11 to INV13 in Figure 5, a capacitance CL is connected between the output of the final stage inverter INV13 and the ground. The inverters have a low pass characteristics by the capacitance CL. An equilibrium resistance Re1 and Re2 are connected to a juncture of INV 12 and INV13. Re1 is connected to the voltage source Vcc and Re2 is grounded. These resistances lower the gain of the circuit of three stages inverters. As the result, unstable oscillations of S11, S12, H11 and S21 are prevented. As shown in Figure 6, each of the switches SW11 to SW 14 and SW 21 to SW24 is a circuit of MOS switch MS3 and a dummy transistor DT1 connected serially after the MOS switch MS3. An inverter INV4 is provided for generating inverter signal for pMOS in the MOS switch and nMOS in the dummy transistor. As shown in Figure 7, each of the switches SW15, SW16 and SW25 to SW26 is a circuit of MOS switch SW4 and a dummy transistor DT2 connected serially before the MOS switch SW4. An inverter INV5 is provided for generating inverter signal for pMOS in the MOS switch and nMOS in the dummy transistor. Hereinafter, the second embodiment of a sampling and holding circuit according to the present invention is described with referring to the attached drawings. In this embodiment, a plurality of analog input voltages can be held in the first sampling and holding circuit. A sampling and holding circuit similar to the first embodiment has the first sampling and holding circuit as shown in Figure 11. The first sampling and holding circuit has a plurality of input switches SW11, SW12 to Swn1 parallelly connected to input voltage Vin, and each of these input switches is connected to one of a plurality of sampling and holding capacitances C1, C2 ... and Cn, respectively. The sampling and holding capacitances C1 to Cn are connected at the first terminal t11 to tn1 to a common reference voltage source VR, and the input switches SW11 to SWn1 are connected to the second terminals t12 to tn2 of capacitances C1 to Cn, respectively. The reference voltage Vstd is stably impressed on each capacitance C1 to Cn. The second terminal of capacitances C1 to Cn are connected to output switches SW12, SW22 ... and SWn2, respectively. These switches are parallel to the input switches SW11 to SWn1 and are connected to an output capacitance C0 corresponding to the capacitance C12 in Figure 2. After the capacitance C0, an inverter I2, feedback capacitance Cf and refresh switch are connected similar to the INV2, Cf12 and SW16 in Figure 2. Then, a voltage inputted to capacitance Co is outputted as a stable inverted output Vout. The above Vstd changes depending on the characteristics of the amplifier I1, mainly on an offset voltage of the amplifier. Both amplifiers I1 and I2 are positioned closely in a large scale integrated circuit (LSI) so as to be substantially equal to each other in the characteristics, and total accuracy becomes high because both offset voltages of I1 and I2 are canceled each other. If the electrical charges of capacitances C0 and Cf are completely discharged, the following formula (1) is valid under the condition that a potential difference at opposite terminals of capacitance Co is ΔV. Vout = Vstd - (Co/Cf)(ΔV) When, one of the output switch is selectively closed under the condition of the following formula (2), and it is defined that a voltage held by the capacitance Ci is Vi when the closed switch is SWi2, C0 = C1 = C2 = ... = Cn the following formula (3) is obtained. ΔV = Ci(Vi-Vstd) / (Co+Ci) = (Vi-Vstd) /2 Then formula (3) is substituted for ΔV in formula (1), and formula (4) is obtained. Vout = Vstd - (Co/Cf)(Vi-Vstd)/2 Furthermore, when Cf = Co/2 Formula (4) is changed by substitution of formula (5), to be formula (6). Vout = Vdd - Vi The formula (6) means that the held voltage is outputted as it is. On the other hand, when input switch is closed during the time the output switch SWi2 is opened, then input voltage Vin is impressed to capacitance Ci so that Ci is charged up to an electrical charge corresponding to a voltage difference between the reference voltage Vdd and the input voltage Vin. As a result, Ci is kept generating voltage Vin at the terminal connected to the input switch. As mentioned above, input voltage Vin is held in a capacitance and then outputted by controlling the input and output switch. One output portion is commonly used for a plurality of capacitances and switches, one inverted amplifier is enough for a plurality of input voltages to be held. The circuit size is not so large relative to the circuit in Figure 2, and much smaller than the sampling and holding circuit of Figure 13. Therefore, this embodiment is effective for holding a lot of data in a limited circuit area. One control signals Rf instead of two refresh signals and sampling and holding signals Ss and Sh are used for the circuit of the second embodiment. Figure 12 is a timing chart of the embodiment. First, a sampling is performed by closing and opening of switches Sw11 to SWn1 successively. For example, first, SW11 is closed and then opened. Next, SW21 is closed and then opened. SW31 to SWnl are similarly operated. So, successive analog input voltages are held in the capacitances C1 to Cn. This is the sampling of a plurality of data such as 256 successive data in time sequence. The sampling signal is given successively to the switches SW11 to SWn1. Figure 12 shows one long pulse as the total sampling time of the switches SW11 to SWn1. After the sampling, the refreshment and holding are alternatively performed. Data in the capacitances are successively outputted through the switches SW12 to SWn2 toward the capacitance C0. SW12 to SWn2 are successively operated so as to output the data, and one cycle of the refreshment is executed before each operation of switches from SW12 to SWn2. For example, first,the refresh signal Rf is given to the switches R1 and R2 for refreshing C0, Cf and I2. Next, SW12 is closed and then opened. The next refreshment is performed and SW22 is closed and then opened. SW32 to SWn2 are similarly operated. So, successive analog input voltages sampled are held in the following circuit as well as outputted to the second sampling and holding circuit. This is the holding of a plurality of data with refreshment. The refreshment for each holding compensate the accuracy of data to be outputted. The holding signal is given successively to the switches SW12 to SWn2. Input switches and output switches are controlled by a well known controlling circuit, for example, by a combination circuit of a counter and a decoder. The control of refresh switches R1 and R2 are performed by a circuit for opening and closing in response to the operation of input and output switches. The circuit may include a counter for counting a pulse with higher constant frequency than a clock pulse of the counter for the input and output switch, so that the refresh switches repeatedly open and close in a constant frequency. It is possible to omit C0 and R2 by adjusting the capacity of C1 to Cn. The circuit is simplified by this omission. Since C0 is effective in preventing influences of parasitic capacity of inverter I2, it is necessary to consider the parasitic capacity when C0 is omitted. The second sampling and holding circuit performs sampling and holding by stages of circuit including multi-stage inverters as mentioned above. The second circuit compensate the accuracy of the analog input voltage to be outputted. The circuit in Figure 11 is available for a circuit for sampling and holding of a plurality of analog input voltages independently from the second sampling and holding circuit SH2 and the multiplexer MUX. This independent circuit is advantageous that a lot of analog data can be sampled and held by a small circuit because the inverter is commonly used for a plurality of capacitances. As mentioned above, according to the present invention, the refresh noises are prevented by an auxiliary sampling and holding circuit which is used when the main sampling and holding circuit works.

Claims: A sampling and holding device comprising: a first sampling and holding circuit (SH1), having an output for outputting a first output voltage (Dh1), connected to an analog input voltage (Vin) and receiving a sampling signal (Ss), a holding signal (Sh) and second refresh signals (Rf1, Rf2), said input voltage (Vin) being sampled by said first sampling and holding circuit when said sampling signal is inputted, said analog input voltage being transferred to be held when said holding signal is inputted, said first sampling and holding circuit being refreshed for said sampling and holding when said first and second refresh signals are inputted; a second sampling and holding circuit (SH2), having an output for outputting a second output voltage (DS2), connected to said output of said first sampling and holding circuit (SH1) and receiving said sampling signal (Ss), said first refresh signal (Rf1), said first output voltage (Dh1) being sampled by said second sampling and holding circuit (SH2) when said sampling signal (Ss) is inputted, said first output voltage (Dh1) being transferred to be held when said holding signal (Sh) is inputted, said second sampling and holding circuit (SH2) being refreshed for said sampling and holding when said first refresh signal (Rf1) is inputted; and a multiplexer (MUX), having an output for outputting a third output voltage, (Dout), connected to said output of said first and second sampling and holding circuit for alternatively passing said first output voltage (Dh1) or said second output voltage (DS2) to said output as said third output voltage (Dout), said second output voltage (DS2) being selectively passed when said first sampling and holding circuit is refreshed, otherwise said first output voltage (Dh1) being selected to be passed. A sampling and holding device as claimed in claim 1, wherein; said first refresh signal (Rf1) is inputted to said first sampling and holding circuit for refreshing before said sampling signal (Ss) is inputted; and said second refresh signal (Rf2) is inputted to said second sampling and holding circuit for refreshing before said holding signal (Sh) is inputted. A sampling and holding device as claimed in claims 1 or 2, wherein said first sampling and holding circuit (SH1) comprises: a first sampling circuit (S11) which comprises an MOS inverter (INV1), said first sampling circuit (S11) being refreshed by discharging of electrical charges when said first refresh signal (Rf1) is inputted; a first switch (SW11) connecting said input voltage (Vin) to said first sampling circuit (S11) through a first coupling capacitance (CC11), said first switch being closed when said sampling signal (Ss) is inputted; a second switch (SW12), having an output, connected to said output of said first sampling circuit (S11), said second switch being closed when said holding signal (Sh) is inputted; and a first holding circuit (H11) which comprises an MOS inverter (INV2), said first holding circuit being refreshed by discharging electrical charges when said second refresh signal (Rf2) is inputted. A sampling and holding device as claimed in any one of claims 1 to 3, wherein said second sampling and holding circuit (SH2) comprises; a second sampling circuit (S21) comprises a MOS inverter (INV1) said second sampling circuit being refreshed when said first refresh signal (Rf1) is inputted; a third switch (Sw21) connecting said output of said first sampling and holding circuit (SH1) to said second sampling circuit (S21) through a third coupling capacitance (CC21), said third switch being closed when said sampling signal (Ss) is inputted; a second holding circuit (H21) which comprises an MOS inverter (INV2), said second holding circuit being refreshed when said first refresh signal (Rf1) is inputted; and a fourth coupling capacitance (CC22) connecting said output of said second sampling circuit (S21) to said input of said input of said second holding circuit (H21). A sampling and holding device as claimed in claim 2, wherein said first and second refresh signals comprise a first portion giving a term for discharging of electrical charge and a second portion giving a waiting time after said discharging. A sampling and holding device as claimed in claim 4, further comprising a fourth switch (Sw22) connected between said second sampling circuit (S21) and said fourth coupling capacitance (CC22), said fourth switch being closed when said holding signal (Sh) is inputted. A sampling and holding device as claimed in claim 1, wherein said first sampling and holding circuit (SH1) comprises: a plurality of capacitances (C1, C2 ....) having first and second terminals for sampling, a plurality of input switches (Swn1) commonly receiving said analog input voltage (Vin), each said input switches connected to said second terminal of one of said capacitances for sampling; a plurality of output switches (Swn2) each connected to said second terminal of one of said capacitances for sampling, an output capacitance (Co) for holding and commonly connected with one terminal of said output switches; an inverted amplifier (12) having an input and output, said inverted amplifier connected at said input to the other terminal of said output capacitance; and a feedback capacitance (Cf1) connecting said output of said inverted amplifier to said input of said inverted amplifier (fig. 11). A sampling and holding device as claimed in claim 7, wherein said first sampling and holding circuit further comprises a first refresh switch (R1) for short-circuiting said input and output of said inverted amplifier (I2). A sampling and holding device as claimed in claim 8, wherein said first sampling circuit further comprises a second refresh switch (R2) connected to said output capacitance parallelly to said output switches, said refresh switch connecting a reference voltage (Gstd) to said output switches. A sampling and holding device as claimed in claim 9, wherein said reference voltage (Gstd) is generated by a circuit of an inverted amplifier (INV6), an output and input of which are short-circuited with each other. A sampling and holding device as claimed in any one of claims 7 to 10, wherein said first sampling and holding circuit (SH1) is used independently from said second sampling and holding circuit (SH2) so that said first output from said first sampling and holding circuit is directly used.

Inventors: MOTOHASHI KAZUNORI, SHOU GUOLIANG, TAKATORI SUNAO, YAMAMOTO MAKOTO, MOTOHASHI, KAZUNORI, SHOU, GUOLIANG, TAKATORI, SUNAO, YAMAMOTO, MAKOTO
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1995
Main classification: G11C27
IPC codes: G11C27