Differential type capacitive sensor system

Abstract: In a capacitive sensor system, first and second driving signals (S2, S3) opposite in phase are applied to a sensor capacitor (3-1) and a reference capacitor (3-2), respectively, which are both connected to a switched capacitor circuit (4). An output signal of the switched capacitor is sampled by two sample-and-hold circuits (7-1, 7-2) which are operated in different phases of the driving signals. A differential amplifier (8) generates a sensor signal in response to the difference in potential between the outputs of the sample-and-hold circuits.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a capacitive sensor system for detecting a physical amount by a small change of capacitance. Description of the Related Art A capacitive sensor generates an electrical signal in proportion to capacitance change caused by pressure or acceleration. A prior art system for such a capacitive sensor includes a sensor capacitor, a reference capacitor, and a switched capacitor circuit connected to the sensor capacitor and the reference capacitor (see: Y. E. Park et al., "AN MOS SWITCHED-CAPACITOR READOUT AMPLIFIER FOR CAPACITIVE PRESSURE SENSORS", IEEE Custom Circuit Conf. pp. 380-384, 1983). In this prior art system, when a first driving voltage is applied to the sensor capacitor while applying ground voltage to the reference capacitor, the switched capacitor circuit is inactive. Then, when a second driving voltage is applied to the reference voltage while applying ground voltage to the sensor capacitor, the switched capacitor circuit is active to thereby generate a sensor voltage in response to pressure or acceleration applied to the sensor capacitor. This will be explained later in detail. In the above-described prior art system, however, when the switched capacitor circuit is transferred from an inactive state to an active state, a charge stored in a feedback control switch transistor of the switched capacitor circuit appears in the output thereof as an offset voltage. This offset voltage also depends upon ambient temperature, so that a temperature drift is also generated. DE-C-3,915,563 discloses a capacitive sensor having a sensor capacitor, a reference capacitor, and a switched capacitor circuit for generating a signal corresponding to a different incapacitance between the sensor capacitor and the reference capacitor. At the output of the switched capacitor circuit there is connected a sample-and-hold-circuit for sampling and holding an output of the switched capacitor circuit. US-A-4,814,714 discloses a method and apparatus for performing integration using a circuit capable of integrating an input signal over a wide linear dynamic range. The input signal is modulated with a biphase signal having positive and negative phases. Track-and-hold-circuits respectively track and hold each interval of the integrated signal responding to positive and negative phases of the biphase signal. The subtracted intervals are then added together by a sample-and-hold circuit joined with a summing circuit to produce the integrated signal corresponding to the linear integration of the input signal. SUMMARY OF THE INVENTION It is an object of the present invention to provide a capacitive sensor system excluding the affection of an offset voltage and a temperature drift. The invention is defined in claim 1. The dependent claims define particular embodiments thereof. In a capacitive sensor system, first and second driving signals opposite in phase are applied to a sensor capacitor and a reference capacitor, respectively, which are both connected to a switched capacitor circuit. An output signal of the switched capacitor is sampled and held by two sample-and-hold circuits which are operated in different phases of the driving signals. A differential amplifier generates a sensor signal in response to the difference in potential between the outputs of the sample-and-hold circuits. Thus, even when an offset voltage and a temperature drift are included in each of the outputs of the sample-and-hold circuits, such an offset voltage and such a temperatuere drift cancel each other in the output of the differential amplifier. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description as set forth below, in comparison with the prior art, with reference to the accompanying drawings, wherein: Fig. 1 is a circuit diagram illustrating a prior art capacitive sensor system; Figs. 2A, 2B 2C and 2D are timing diagrams showing the operation of the system of Fig. 1; Fig. 3 is a circuit diagram illustrating a first embodiment of the capacitive sensor system according to the prenset invention; Fig. 4 is a circuit diagram of the driving circuit of Fig. 3; Figs. 5A through 5N are timing diagrams showing the operation of the circuits of Figs. 3 and 4; and Figs. 6, 7 and 8 are circuit diagrams illustrating second, third and fourth embodiments, respectively, of the capacitive sensor system according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before the description of the preferred embodiments, a prior art capacitive sensor system will be explained with reference to Fig. 1, and 2A through 2D. In Fig. 1, reference numeral 1 designates a clock signal generating circuit whose output signal S1 is supplied via three inverters 2-1, 2-2 and 2-3 as a signal S2 to a sensor capacitor 3-1 and via the three inverters 2-1 to 2-3 and an inverter 2-4 as a signal S3 to a reference capacitor 3-2. A capacitance C S of the sensor capacitor 3-1 is changeable in response to pressure change or acceleration change, while a capacitance C R of the reference capacitor 3-2 is definite. The sensor capacitor 3-1 and the reference capacitor 3-2 are connected to a switched capacitor circuit 4 formed by an operational amplifier or a feedback amplifier 41, a feedback capacitor 42 whose capacitance is C F , and a feedback control switch (in this case, an N-channel MOS transistor) 43. In this case, an input terminal (-) of the feedback amplifier 41 has a parasitic capacitor 5 whose capacitance is C P . In the capacitive sensor system of Fig. 1, a sensor voltage V S is generated in response to a difference (C S -C R ) in capacitance. The operation of the system of Fig. 1 is explained next with reference to Figs. 2A through 2D. At time t 0 , as shown in Fig. 2A, the voltage of the signal S1 is high (=V P ), so that the feedback control switch 43 is turned ON. Therefore, the switched capacitor circuit 4 is inactive. Also, as shown in Fig. 2B, the voltage of the signal S2 is V P . Therefore, a charge Q S generated by the sensor capacitor 3-1 at a node N 1 is Q S = -C S · (V P - V R ) where V R is a reference voltage applied to an input terminal (+) of the feedback amplifier 41. Further, as shown in Fig. 2C, the voltage of the signal S3 is OV. Therefore, a charge Q R generated by the reference capacitor 3-2 at the node N 1 is Q R = C R · V R Thus, from the formulae (1) and (2), a total charge Q t at the node N 1 is Q t = C R · V R - C S · (V P - V R ) Further, since the feedback control switch 43 is turned ON, the sensor voltage V S remains at V R as shown in Fig. 2D. Next, at time t 1 , as shown in Fig. 2A, the voltage of the signal S1 is changed from V P to OV, so that the feedback control switch 43 is turned OFF. Therefore, the switched capacitor 4 is active. Next, at time t 2 , as shown in Fig. 2B and 2C, the voltages of the signals S2 and S3 become OV and V P , respectively. Therefore, a charge Q S ' generated by the sensor capacitor 3-1 at a node N 1 is Q S ' = C S · V R Further, a charge Q R ' generated by the reference capacitor 3-2 at the node N 1 is Q R ' = -C R · (V P - V R ) Thus, from the formulae (4) and (5), a total charge Q t ' at the node N 1 is Q t ' = = C S · V R - C R · (V P - V R ) As a result, from the formulae (3) and (6), since the feedback control switch 43 is turned OFF, the following charge Q0 is stored in the feedback capacitor 42: Q0 = Q t - Q t ' = - (C S - C R ) · V P Therefore, as shown in Fig. 2D, the sensor voltage V S is represented by V S = -Q0/C F = V P · (C S - C R )/C F Thereafter, the above-described operations at time t 0 , t 1 and t 2 are repeated at time t 4 , t 5 and t 6 . Thus, the sensor voltage V S of t;he capacitive sensor system of Fig. 1 is not affected by the parasitic capacitance C P which is dependent upon the ambient temperature, to thereby detect a small capacitance change. In the capacitive sensor system of Fig. 1, however, every time the voltage of the signal S1 is changed from high (=V P ) to low (0V) indicated by times t 1 and t 6 in Fig. 2A, a charge Q d stored in the gate electrode of the feedback control switch 43 is emitted therefrom. As a result, the sensor voltage V S is actually represented by V S = (V P · (C S - C R ) + Q d )/C F As is apparent from the formula (9), the charge Q d emitted from the gate electrode of the feedback control switch 43 appears in the sensor voltage V S as an offset voltage. This offset voltage is dependent upon the gate voltage V P and the soure-drain voltage. This offset voltage is particularly dependent upon the ambient temperature, and as a result, a temperature drift is generated in the sensor voltage V S . Further, an offset voltage and a temperature drift of the feedback amplifier 41 appears in the sensor voltage V S . Thus, it is difficult to completely remove the offset voltage and the temperature drift from the sensor voltage V S . In Fig. 3, which illustrates a first embodiment of the present invention, a driving circuit 6, two sample-and-hold circuits 7-1 and 7-2, and a differential amplifier 8 are added to the elements of Fig. 1. In this case, the driving circuit 6 serves as the clock signal generating circuit 1 and the inverters 2-1 through 2-4, and therefore, the driving circuit 6 generates the signals S1, S2 and S3. Also, the driving circuit 6 generates signals S4 and S5 to operate the sample-and-hold circuits 7-1 and 7-2 alternately. The driving circuit 6 is explained next in detail with reference to Fig. 4. In Fig. 4, reference numeral 61 designates a clock signal generating circuit for generating a clock signal whose time period is T, and 62 designates a frequency divider for dividing the clock signal of the clock signal generating circuit 61 to generate a divided signal whose time period is, for example, 16T. Also, reference numeral 63 designates a shift register for receiving the divided signal from the frequency divider 62 and generating shifted signals Q1, Q2, ···, Q8 as shown in Figs. 5A through 5H clocked by the clock signal of the clock signal generating circuit 61. The signal S3 is derived via inverters 64 and 65 from the signal Q8, and therefore, as shown in Fig. 5H, the signal S3 is approximately the same as the signal Q8. The signal S2 is derived via an inverter 66 from the signal Q8, and therefore, as shown in Fig. 5I, the signal S2 is opposite in phase to the signal S3. Also, an exclusive OR circuit 67 receives the signals Q4 and Q7, and as a result, the exclusive OR circuit 67 generates the signal S1 having a time period of 8T as shown in Fig. 5J. Further, an exclusive OR circuit 68 receives the signals Q1 and Q3, and as a result, the exclusive OR circuit 68 generates a signal S0 having a time period of 8T as shown in Fig. 5K. The signal S0 is masked at an AND circuit 69 by the signal Q8, so that the signal S4 having a time period of 16T as shown in Fig. 5L is generated. simultaneously, the signal S0 is masked at an AND circuit 70 by an inverted signal of the signal Q8, so that the signal S5 having a time period of 16T as shown in Fig. 5M is generated. That is, the signals S4 and S5 are opposite in phase to each other. As shown in Figs. 5H, 5I and 5J, the signal S1 is made high (=V P ) for a definite time period before the signal S3 (the signal S2) is changed from low (=0V) to high (=V P ) (from high to low), and as shown in Figs. 5H, 5I and 5L, the signal S4 is made high (=V P ) for a definite time period after the signal S3 (the signal S2) is changed from low (=0V) to high (=V P ) (from high to low). Similarly, as shown in Figs. 5H, 5I and 5J, the signal S1 is made high (=V P ) for a definite time period before the signal S3 (the signal S2) is changed from high (=V P ) to low (=0V) (from low to high), and as shown in Figs. 5H, 5I and 5M, the signal S5 is made high (=V P ) for a definite time period after the signal S3 (the signal S2) is changed from high (=V P ) to low (=0V) (from low to high). The operation of the system of Fig. 3 is explained next with reference to Figs. 5H through 5N. At time t 0 , as shown in Fig. 5J, the voltage of the signal S1 is high (=V P ), so that the feedback control switch 43 is turned ON. Therefore, the switched capacitor circuit 4 is inactive. In this case, the sensor voltage V S is represented by V S = V R + V offset where V offset is an offset voltage of the feedback amplifier 41. Next, at time t 1 , as shown in Fig. 5J, the voltage of the signal S1 is changed from high (=V P ) to low (=0V), the feedback control switch 43 is turned OFF. Therefore, the switched capacitor circuit 4 is active. At this time, the signals S2 and S3 are unchanged, and a charge Q d is emitted from the gate electrode of the feedback control switch 43. As a result, the sensor voltage V S is represented by V S = V R + V offset + V d where V d is Q d /C F . Next, at time t 2 , as shown in Figs. 5I and 5H, the voltages of the signals S2 and S3 become 0V and V P , respectively. Therefore, the charge Q0 represented by the formula (7) is stored in the feedback capacitor 42, and therefore, from the formulae (7) and (11), the sensor voltage V S is represented by V S = V P · (C S - C R )/C F + V R + V offset + V d = VSH1 Next, at time t 3 , as shown in Fig. 5L, the signal S4 is changed from low to high, and as a result, the sample-and-hold circuit 7-1 samples and holds the voltage V S represented by the formula (12). Then, at time t 4 , as shown in Fig. 5L, the signal S4 is changed from high to low, so that the operation of the sample-and-hold circuit 7-1 is stopped. At time t 5 , as shown in Fig. 5J, the voltage of the signal S1 is again high (=V P ), so that the feedback control switch 43 is turned ON. Therefore, the switched capacitor circuit 4 is inactive. In this case, the sensor voltage V S is represented by V S = V R + V offset Next, at time t 6 , as shown in Fig. 5J, the voltage of the signal S1 is changed from high (=V P ) to low (=0V), so that the feedback control switch 43 is turned OFF. Therefore, the switched capacitor circuit 4 is active. At this time, the signals S2 and S3 are unchanged, and a charge Q d is emitted from the gate electrode of the feedback control switch 43. As a result, the sensor voltage V S is represented by V S = V R + V offset + V d Next, at time t 7 , as shown in Figs. 5I and 5H, the voltages of the signals S2 and S3 become V P and 0V, respectively. Therefore, the following charge Q0' is stored in the feedback capacitor 42: Q0' = -Q0 = (C S - C R ) · V P Therefore, from the formulae (15) and (11), the sensor voltage V S is represented by V S = -V P · (C S - C R )/C F + V R + V offset + V d VSH2 Next, at time t 8 , as shown in Fig. 5M, the signal S5 is changed from low to high, and as a result, the sample-and-hold circuit 7-2 samples and holds the voltage V S represented by the formula (16). Then, at time t 4 , as shown in Fig. 5L is changed from high to low, so that the operation of the sample-and hold circuit 7-1 is stopped. On the other hand, in the differential amplifier 8, a difference between the sampled and hold voltages VSH1 and VSH2 of the sample-and-hold circuits 7-1 and 7-2 is calculated. That is, a sensor voltage V S ' of the differential amplifier 8 is represented by V S ' = VSH1 - VSH2 = 2V P · (C S - C R )/C F Thus, in the capacitive sensor system of Fig. 3, the sensor voltage Vs' is dependent upon only the voltage V P of the driving signals S1 and S2, the capacitance C S of the sensor capacitor 3-1, the capacitance C R of the reference capacitor 3-2 and the capacitance C F of the feedback capacitor 42, not upon the offset voltage V offset of the feedback amplifier 41 and the offset voltage V d of the charge of the feedback control switch 43. In Fig. 6, which illustrates a second embodiment of the present invention, a gain amplifier 9 is interposed between the switched capacitor circuit 4 and the sample-and-hold circuits 7-1, and 7-2. The gain amplifer 9 amplifies the output voltage V S of the switched capacitor circuit 4 with respect to the reference voltage V R . Even in the second embodiment, the offset voltage V offset of the feedback amplifier 41 and the offset voltage V d of the charge of the feedback control switch 43 can be removed. In Fig. 7, which illustrates a third embodiment of the present invention, a highpass circuit 10 is interposed between the switched capacitor circuit 4 and the sample-and-hold circuits 7-1, and 7-2. The highpass circuit 10 passes a high frequency component of the output voltage V S of the switched capacitor circuit 4 therethrough, to thereby remove a low frequency band noise therefrom. Even in the third embodiment, the offset voltage V offset of the feedback amplifier 41 and the offset voltage V d of the charge of the feedback control switch 43 can be removed. In Fig. 8, which illustrates a fourth embodiment, the second embodiment is combined with the third embodiment. Even in the fourth embodiment, the offset voltage V offset of the feedback amplifier 41 and the offset voltage V d of the charge of the feedback control switch 43 can be removed. In the third and fourth embodiments, a lowpass circuit or a bandpass circuit can be used instead of the highpass circuit 10. In this case, the lowpass circuit removes a high frequency band noise, and the bandpass circuit removes a high frequency band noise and a low frequency band noise. Also, in the above-described embodiments, both of the capacitances of the sensor capacitor and the reference capacitor can be changed in accordance with the change of pressure or acceleration. As explained hereinbefore, according to the present invention, the offset voltage of the feedback amplifier and the offset voltage of the charge of the feedback control switch can be removed, and thus, a reliable capacitive sensor system can be obtained.

Claims: A capacitive sensor system comprising: first means for generating a first driving signal (S2); second means for generating a second driving signal (S3) opposite in phase to said first driving signal; a sensor capacitor (3-1), connected to said first means, for receiving said first driving signal; a reference capacitor (3-2), connected to said second means, for receiving said second driving signal; a switched capacitor circuit (4), connected to said sensor capacitor and said reference capacitor, for generating a signal corresponding to a difference in capacitance between said sensor capacitor and said reference capacitor; a first sample-and-hold circuit (7-1), connected to said switched capacitor circuit, for sampling and holding an output of said switched capacitor circuit in response to a first signal (S4), said sensor system being characterized by : a second sample-and-hold circuit (7-2), connected to said switched capacitor circuit, for sampling and holding the output of said switched capacitor circuit in response to a second signal (S5); and a differential amplifier (8), connected to said first and second sample-and-hold circuits, for generating an output signal in response to a difference between outputs of said first and second sample-and-hold circuits; whereby said first and second signals (S4, S5) for sampling and holding the output of said switched capacitor circuit (4) are in different phases of said first and second driving signals (S2, S3). A system as set forth in claim 1, wherein switched capacitor circuit comprises: a feedback amplifier (41) having a first input connected to said sensor capacitor and said reference capacitor, a second input for receiving a reference voltage, and an output; a feedback capacitor (42) connected between the first input and the output of said feedback amplifier; and a feedback control switch (43) connected between the first input and the output of said feedback amplifier, said feedback control switch being turned ON for a certain time period after an operation of one of said first and second sample-and-hold circuits is completed before a transition of said first and second driving signals. A system as set forth in claim 1, further comprising a gain amplifier (9), connected between said switched capacitor circuit and said first and second sample-and-hold circuits, for amplifying an output of said switched capacitor circuit. A system as set forth in claim 3, further comprising a circuit (10) connected between said gain amplifier and said first second sample-and-hold circuits, for removing a frequency component of an output of said gain amplifier therefrom. A system as set forth in claim 4, wherein said circuit (10) comprises at least one of a highpass circuit, a lowpass circuit and a bandpass circuit. A system as set forth in claim 1, further comprising a circuit (10), connected between said switched capacitor circuit and said first and second sample-and-hold circuits, for removing a frequency component of an output of said switched capacitor circuit therefrom. A system as set forth in claim 6, wherein said circuit (10) comprises at least one of a highpass filter, a lowpass filter and a bandpass filter. A capacitive sensor system according to claim 1, further comprising: a driving circuit (6), connected to said sensor capacitor, said reference capacitor, said switched capacitor circuit and said first and second sample-and-hold circuits, for generating a first driving signal (S2) having a definite time period (16T) and applying said first driving signal to said sensor capacitor, generating a second driving signal (S3) opposite in phase to said first driving signal and applying said second driving signal to said reference capacitor, generating a reset signal for a definite time period (3T) in advance of a transition of said first and second driving signals and applying said reset signal to said switched capacitor circuit to thereby deactivate said switched capacitor circuit, generating a first sampling and holding signal for a definite time period (2T) after a rising transition of said first driving signal and before generation of said reset signal and applying said first sampling and holding signal to said first sample-and-hold circuit to thereby operate said first sample-and-hold circuit, and generating a second sampling and holding signal for a definite time period (2T) after a rising transition of said second driving signal and before generation of said reset signal and applying said second sampling and holding signal to said second sample-and-hold circuit to thereby operate said second sample-and-hold circuit. A system as set forth in claim 8, wherein said driving circuit comprises: a clock signal generator (61) for generating a clock signal having a definite time period (T); a frequency divider (62), connected to said clock signal generator, for generating a divided signal having a definite time period (16T); a shift register (63), connected to said clock signal generator and said frequency divider, for shifting said divided signal by said clock signal to generate a plurality of signals; and a logic circuit (64-70), connected to said shift register, for generating said first and second driving signals, said reset signal, and said first and second sampling and holding signals. A system as set forth in claim 8, wherein said switched capacitor circuit comprises: a feedback amplifier (41) having a first input connected to said sensor capacitor and said reference capacitor, a second input for receiving a reference voltage, and an output; a feedback capacitor (42) connected between the first input and the output of said feedback amplifier; and a feedback control switch (43) connected between the first input and the output of said feedback amplifier, said feedback control switch being turned ON by said reset signal. A system as set forth in claim 8, further comprising a gain amplifier (9), connected between said switched capacitor circuit and said first and second sample-and-hold circuits, for amplifying an output of said switched capacitor circuit. A system as set forth in claim 11, further camprising a circuit (10) connected between said gain amplifier and said first and second sample-and-hold circuits, for removing a frequency component of an output of said gain amplifier therefrom. A system as set forth in claim 12, wherein said circuit (10) comprises at least one of a highpass circuit, a lowpass circuit, and a bandpass circuit. A system as set forth in claim 8, further comprising a circuit (10), connected between said switched capacitor circuit and said first and second sample-and-hold circuits, for removing a frequency component of an output of said switched capacitor circuit therefrom. A system as set forth in claim 14, wherein said circuit (10) comprises at least one of highpass circuit a lowpass circuit and a bandpass circuit.

Inventors: OKADA HIROYUKI, OKADA, HIROYUKI, Okada, Hiroyuki, c/o NEC Corp
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1995
Main classification: G01D5
IPC codes: G01R27, G01D5, G01L9, G01P1, G01D3, H03F3