MOS integrated device comprising a gate protection diode

Abstract: The device (10) presents a polysilicon layer (36) extending over a wafer (20) of semiconductor material, along the edge of the active region (34) of the device, and partly over a thick field oxide layer (35) which externally delimits the active region. The polysilicon layer (36) forms both a field-plate region (37) at its inner edge, and a Zener protection diode (11) over the field oxide layer (35), outwards of and contiguous to the field-plate region (37). The terminals of the diode (11) are respectively connected to the source metal region (30) and the gate metal region (44); the diode (11) therefore extends along the whole of the perimeter of the device (10), and presents an extensive junction area without greatly reducing the active area of the device.

Description: The present invention relates to a MOS integrated device comprising a gate protection diode, according to the preamble of claim 1. As is known, power MOS technology is aimed at forming power components interfaceable directly with control logic circuits. As this implies a 3-5 V control voltage of the gate region of MOS devices, power MOS technology has tended to produce devices with a low threshold and, hence, thin gate oxide. Moreover, in low-voltage (30-60 V) applications, a reduction in output resistance obviously now requires the use of scaled processes with ever-smaller channel lengths and gate oxide thicknesses. As a result, currently used low-voltage power MOS transistors feature gate oxide thicknesses ranging from 20 to 50 nm (200 to 500 Å). On the one hand, therefore, technological and application requirements demand thin gate oxides, whereas, on the other, application and quality standard requirements demand gate oxides capable of withstanding electrostatic charges. Therefore tests, now become standard, have been devised using test circuits, the most commonly used of which is shown in Figure 1. The test circuit 1 in Figure 1 substantially comprises a capacitor 2, which is precharged to a test voltage (e.g. 20 V for transistors with a breakdown voltage of 50 V) and then discharged via a resistor 3 into the test transistor 4; the current through transistor 4 is measured by an ammeter 6; and any defective gate oxide is determined according to the current reading. To protect the gate oxide of power MOS transistors of the above type, it has been proposed to integrate Zener diodes with a lower breakdown voltage than the gate oxide in any operating condition, as shown schematically in Figure 2, in which 10 indicates the power MOS transistor, and 11 indicates the Zener diode, which in this case is formed by a pair of back-to-back diodes 12, 13, and is located between the gate terminal G and source terminal S of transistor 10. There are various ways of integrating a diode between the gate and source terminals of a MOS transistor, the simplest being to exploit the source-body junction with an inverse bias. According to this solution, a region similar to the source regions of the MOS transistor is formed in a special body well; the well is connected to the gate metal region; and the source-similar region formed in the well is connected to the source metal region of the transistor. The above solution, however, presents the disadvantage of inevitably involving a parasitic NPN transistor, which impairs the dynamic strength of the structure. According to another known solution, protection diodes are integrated over the wafer of semiconductor material using the polysilicon layer used for the gate regions; such solution presents the advantage of eliminating any parasitic elements, by virtue of the diodes being located outside the wafer and separated electrically from it by a thick oxide layer. The disadvantage of the above solution, however, lies in the need to minimize the area occupied by the protection diodes, to avoid an excessive reduction in the area available for the active device components, or an undesired increase in the overall size of the device. Generally speaking, it is desirable that protection diodes should occupy no more than 3-5% of the total area of the device, which limitation, however, seriously impairs their effectiveness. In fact, the characteristic of a polysilicon diode presents, after the breakdown voltage, a far from negligible resistance (a few tens of ohms) which depends partly on the aluminium-polysilicon contact and partly on the area of the PN junction. In practice, diode characteristic V D is of the type: V D = V Z + R Z I where V Z is the breakdown voltage (start of inverse conduction of the diode), R Z is the equivalent resistance of the inversely conducting diode, and I is the current through the diode. In other words, the Zener diode is no longer capable of maintaining the breakdown voltage independently of the current flow, and, following breakdown, presents a voltage drop increasing with the current. Consequently, in the event, for example, of R Z = 30 Ω , V Z = 15 V, and an oxide breakdown voltage of 25 V, a current I ≥ 350 mA is enough to make the protection diode ineffective, by virtue of the voltage guaranteed by it being greater than the oxide breakdown voltage. This is particularly undesirable in view of the fact that, when ESD testing using the Figure 1 circuit, the current through the diode may be as high as a few Amps, so that breakdown resistance R Z should be at most a few ohms (R Z < 5 Ω). In view of the very small voltage margin (defined as V OX - V Z , where V OX is the oxide breakdown voltage) of particularly thin oxides, the solution whereby the diodes are formed in the polysilicon requires very large junction and contact areas for the protection diode to function properly, which, as stated, is in direct conflict with the need to reduce the area occupied by the diodes. EP-A-0 600 229 discloses in figure 15, as prior art, a MOS device having the features indicated in the preamble of claim 1, wherein the diode is arranged between the drain and the gate for turning on the MOS device in case of high flyback voltage. US-A-4 688 323 discloses a MOSFET having a protective element comprising back-to-back connected diodes (D1, D2), connected between the gate electrode and the source electrode of the MOS device. The protective element is formed around the MOS device. It is an object of the present invention to provide an integrated device of the aforementioned type featuring gate protection diodes, designed to overcome the drawbacks typically associated with known techniques. In particular, the integrated device should comprise protection diodes that are effective even in the case of very thin gate oxides, without involving an excessive increase in the overall area of the device. According to the present invention, there is provided an integrated device as claimed in Claim 1. A number of preferred, non-limiting embodiments of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a known test circuit; Figure 2 shows the electric diagram of a known integrated transistor to which the present invention is applied; Figure 3 shows a top plan view of one embodiment of the device according to the present invention; Figure 4 shows a cross section along line IV-IV of a portion of the Figure 3 device; Figure 5 shows a top plan view of an enlarged detail of the Figure 3 device; Figure 6 shows a top plan view of an enlarged detail of a further embodiment of the Figure 3 device; Figure 7 shows a cross section of a further embodiment of the device according to the present invention. Figures 3-5 show a power MOS transistor 10 integrated in a wafer 20 of semiconductor material comprising a first N + type region 21 connected to a drain terminal D, and a second N type region 22 over region 21 and presenting a surface 23. P + type body regions 24 are housed, facing surface 23, inside second region 22, and in turn house N + type source regions 25 separated by respective portions 24a of body regions 24. Polysilicon gate regions 27 are located on surface 23, between pairs of body regions 24, and are insulated electrically from surface 23 by a gate oxide layer 28. A thick oxide layer 29 surrounds the gate regions and separates them electrically from a source metal region 30 extending over wafer 20 and electrically contacting source regions 25 and portions 24a of body region 24 by means of contact regions 30a. A P - -type edge ring 33 formed in second region 22 fully surrounds the portion in which body regions 24 are formed (active area 34), and is located beneath a thick field oxide layer 35. A polysilicon layer 36 extends partly over field oxide layer 35 and partly over active area 34, and is separated electrically from surface 23 by gate oxide layer 28. As shown in Figure 4, polysilicon layer 36 forms both a field-plate region 37 at its inner edge, and a Zener diode 11 over field oxide layer 35 and adjacent to field-plate region 37. More specifically, diode 11 comprises portions 40, 41, 42, which are so doped as to present respective conductivity types N + , P and N + . Portions 40-42 have a concentric annular shape with portion 40 adjacent to field-plate region 37, portion 41 adjacent to but outwards of portion 40, and portion 42 adjacent to but outwards of portion 41. Portion 40 is located beneath and close to the outer edge of source metal region 30, and is connected to it by a contact portion 30b extending through thick oxide layer 29; and portion 42 is located beneath and connected to a gate metal region 44 (fully surrounding the transistor, outside active area 34, as shown in Figure 3) by a contact portion 44a also extending through thick oxide layer 29. As such, diode 11 extends about the whole perimeter of transistor 10, and is formed in the polysilicon layer 36 already provided for forming field-plate region 37 for increasing the voltage-strength of the structure, and for forming annular gate metal region 44 for reducing the gate resistance. The peripheral arrangement of diode 11 is shown clearly in Figure 3, in which the portion of polysilicon layer 36 in which diode 11 is formed (not directly visible) is shown hatched. The above structure therefore provides for inserting an extremely large-area Zener diode 11 with no loss in the active area of the device; and the fact that Zener diode 11 is located over field oxide layer 35, and is separated by the thickness of it (roughly 1 µm). from wafer 20, makes a special polysilicon island superfluous. As shown in Figure 4, the area of Zener diode 11 therefore equals the perimeter of the transistor times the thickness of polysilicon layer 36, and the contact area of contact portions 30b, 44a of metal regions 30, 44 extends along the whole of the junction on the perimeter, and equals: A C,S = P S x L S ; A C,G = P G x L G where A C,S and A C,G are respectively the contact area of the source and gate metal regions; P S and P G are respectively the length of the perimeter of source and gate contact portions 30b, 44a (approximately corresponding to the inside and outside perimeters of diode 11); and L S and L G are respectively the width of the same contact portions (Figure 5). For a 10 mm 2 (roughly 3 mm square) transistor 10 with a 0.5 µm thick polysilicon layer 36 and L S = L G = 4µm, it is therefore possible to form a diode with an area A of 6000 µm 2 and a contact area of 48000 µm 2 . By way of comparison, to form a diode of the same size using the known solution described previously, a polysilicon island of roughly 0.5-1 mm 2 , equal to 5-10% of the transistor area, would be required, at the expense of the active cells of the transistor. Forming the diode in the polysilicon layer, adjacent to field-plate region 37, also enables the formation, if necessary, of gate fingers extending from any point of metal region 44, as shown by way of example in Figure 6 illustrating an enlarged detail of transistor 10, and in which, from peripheral gate metal region 44, there extends a metal "finger" 44b with a contact portion 44c for contacting the polysilicon gate strips (not shown). If the voltage guaranteed by the Zener diode is greater than the breakdown voltage of one diode, a number of pairs of diodes in series may be provided between the source and drain contact portions. Figure 7, for example, shows two pairs of diodes 12a, 12b, 13a, 13b. More specifically, starting from the outer edge of field-plate region 37 in Figure 7, polysilicon layer 36 houses an N + type region 50 contacting source contact portion 30b; a P type region 51 adjacent to region 50; an N + type region 52 adjacent to region 51; a P type region 53 adjacent to region 52; and an N + type region 54 adjacent to region 53 and contacting gate contact portion 44a. Regions 50, 51 form diode 12a; regions 51, 52 diode 13a; regions 52, 53 diode 12b; and regions 53, 54 diode 13b. Clearly, changes may be made to the device as described and illustrated herein without, however, departing from the scope of the present invention.

Claims: A MOS device (10) including a body (20) of semiconductor material having a surface (23) and defining an active region (34) having a perimeter; the MOS device comprising at least one source region (25) formed in said active region; at least one gate region (27) formed over and electrically insulated from said source region; a layer (36) of semiconductor material extending over said surface (23) and along said perimeter and electrically insulated from said body (20) of semiconductor material; and a gate protection diode (11) formed in said layer (36) of semiconductor material, outside said perimeter; said gate protection diode (11) comprising a plurality of contiguous annular portions (40-42; 50-54) of opposite conductivity extending each along substantially the whole perimeter of said active region (34), and including a first contact region (40) electrically contacting said source region (25), and a second contact region (42) electrically contacting said gate region (27); wherein said layer (36) of semiconductor material forms a field-plate protection region (37) adjacent and inwardly contiguous to said gate protection diode (11); characterized in that said first contact region (40) is an inner contact region and said second contact region (42) is an outer contact region. A device as claimed in Claim 1, characterized in that said layer (36) of semiconductor material is made of polycrystalline silicon. A device as claimed in any one of the foregoing Claims, characterized in that it comprises a source metal region (30) extending over said active region (34) and said gate region (27); and a gate metal region (44) extending outside said source metal region (30) and said active region (34), and electrically insulated from said source metal region; said source metal region (30) presenting a contact portion (30b) contacting said first contact region (40) of said protection diode (11); and said gate metal region (44) presenting a contact portion (44a) contacting said second contact region (42) of said protection diode. A device as claimed in any one of the foregoing Claims, characterized in that it comprises a field oxide layer (35) externally defining said active region (34); and in that said protection diode (11) is formed over said field oxide layer. A device as claimed in any one of the foregoing Claims, characterized in that said protection diode (11) comprises a pair of back-to-back diodes (12, 13). A device as claimed in any one of the foregoing Claims from 1 to 4, characterized in that said protection diode (11) comprises at least two pairs of back-to-back diodes (12a, 13a, 12b, 13b). A device as claimed in any one of the foregoing Claims, characterized in that said contiguous portions (40-42; 50-54) are concentric.

Inventors: FRISINA FERRUCCIO, FRISINA, FERRUCCIO
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO - CORIMME
Application year: 1995
Main classification: H01L27
IPC codes: H01L27, H01L29