SIGNAL CONDITIONING CIRCUIT FOR COMPRESSING AUDIO SIGNALS

Abstract: A signal conditioning circuit (10) compresses an audio signal by producing a gain signal (Vc) that is a function of the time-averaged audio signal and a compression ratio, and amplifying the audio signal by an exponential function of the gain signal. The conditioning circuit merges the functions of buffering the audio signal and producing a full-wave rectified version of the audio signal into a single buffer circuit (12). An averaging circuit (14) generates a time-averaged signal in response to the full-wave rectified signal. An interface circuit (16) includes downward expansion (60), compression (58) and limiting (59) circuits for scaling the time-averaged signal with a low compression ratio when it is less than a break point, with a selected compression ratio when it is between the break point and a rotation point, and with a high compression ratio when it exceeds the rotation point.

Description: SIGNAL CONDITIONING CIRCUIT FOR COMPRESSING AUDIO SIGNALS BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to signal con¬ ditioning circuits, and more specifically to a signal con- ditioning circuit that merges buffering and rectification functions and provides downward expansion, variable com¬ pression and limiting capabilities. Description of the Related Art Audio systems such as public address (PA) and digital computer multi-media systems receive audio signals through microphone inputs. PA systems use power amplifiers to am¬ plify the signals through a speaker system while multi-me¬ dia computers digitize the inputs for storage, processing or playback. The audio signals are typically provided by a person speaking into the microphone. Often the speaker is not experienced or comfortable with using a microphone, and may hold the microphone too close or too far away or may move the microphone around as he speaks. Furthermore, a person giving a presentation may be moving back-and-forth with respect to the microphone. In a PA system, this will cause the amplified signal to become very loud, and possibly distort, or fade in and out. Similarly, the computer will record a signal whose dynamic range varies due to the fluctuations in the detected audio signal. To reduce the unnatural and annoying variances in the amplified or recorded audio signal, these systems use con¬ ditioning circuits to compress the dynamic range of the output audio signal such that faint signals are boosted and loud signals are attenuated. This improves the perceptual quality or vocal clarity of the signal. The amount of com¬ pression in the conditioning circuit is given by a compres¬ sion ratio r, which is the ratio of the amplitude change of the RMS input audio signal compared to the amplitude change of the RMS output audio signal in decibels (dB) . At one extreme a compression ratio of 1:1 produces no compression, while at the other extreme the RMS value of the output is held constant regardless of the input level (this is com¬ monly referred to as an infinite ratio) . When plotted in dB, a given circuit's compression curve is generally a straight line whose slope is the compression ratio. If the compression ratio can be varied, the lines for different ratios will generally intersect at a fixed reference point called the rotation point. At the rotation point, the cir¬ cuit's gain is the same for all of its available compres- sion ratios. At an infinite compression ratio, variances in the output audio signal that would otherwise result from an improper use of a microphone are eliminated. However, the natural dynamic range of speech (the input audio signal) is also lost. In general, if the compression ratio is too large, the output signal amplitude will flatten out and very low noise signals will be amplified. If the compres¬ sion ratio is too small, the microphone input problems will remain and the output may saturate or clip for large sig- nals. The best perceptual audio quality is usually achieved between compression ratios of 2:1 and 10:1. Conditioning circuits such as those described in pro¬ duct data sheets for an "AGC Microphone and Power Amplifi¬ er, " model CS4611 produced by Crystal Semiconductor of Aus- tin, Texas, December, 1992, and an "AGC Microphone and Pow- er AMP," model MVA611 produced by Media Vision, Inc. of Fremont, California, September, 1992, include separate in¬ put buffer and level detection circuits, and are packaged in 24 and 28 pin packages, respectively. The input buffer presents a high impedance to the microphone and outputs a buffer signal. The level detection circuit includes both a full-wave rectifier and a root-mean-square (RMS) circuit for computing the RMS value of the input signal. Blocking capacitors are connected at the input to the level detec- tion circuit, and between the input buffer and a voltage controlled amplifier (VCA) to prevent small DC currents in the conditioning circuitry from adversely affecting accura¬ cy of the VCA and the level detection circuit. An interface circuit produces a gain signal in re- sponse to the RMS input signal and a preset compression ratio. The VCA amplifies the buffer signal by an exponen¬ tial function of the gain signal to produce a compressed output signal. The compression ratio can be adjusted ex¬ ternally to balance the competing interests of good signal quality in the desired audio range, reduced clipping and saturation for excessively large signals, and minimal am¬ plification of noise signals. However, when the compres¬ sion ratio provides enough compression to reduce the fluc¬ tuations in the audio signal without completely flattening the speaker's dynamic range, there is insufficient ampli¬ tude limiting of large signals, resulting in clipping and distortion. Furthermore, when the person is not speaking the noise level is amplified considerably. Another type of conditioning circuit, such as de- scribed in the product data sheet for a "Record/Playback Circuit with ALC, " model TDA7284 produced by SGS-Thomson Microelectronics of St. Genif Pouilly, France, May, 1991, and a "Bipolar Linear Integrated Circuit Silicon Monolith¬ ic, " model TA2011S produced by Toshiba Corporation of Tokyo, Japan, September, 1991, uses feedback to control the signal compression. The conditioning circuit's compressed output signal is fed back to scale the input signal, so that an approximately constant signal value is input to the fixed gain amplifier that produces the compressed output signal. These circuits are Full Automatic Gain Control (AGO circuits with an infinite compression ratio, and suf¬ fer from the problems mentioned above that are associated with infinite compression ratios. Analog Devices, Inc., the assignee of the present in- vention, produces audio circuits AN-133, AN-116 and AN-134 that incorporate signal conditioning. The conditioning circuitry uses a buffer to communicate the input signal to a VCA and a level detection/RMS circuit, each requiring its own blocking capacitor. The RMS signal is compared to a rotation point using conventional comparator circuits. In the AN-116, the compression ratio can be externally pro¬ grammed to one of six preset values. Conventional RMS circuits, such as those disclosed by D. Sheingold "Nonlinear Circuits Handbook," Analog Devices, Inc ., pp. 398-403, 1976, fall into one of two categories: explicit or implicit. Explicit detectors square the input signal, compute its mean, and then calculate the square root. Squaring the input signal reduces the dynamic range of the detector, and the large number of components needed to implement the explicit detector reduces its accuracy. Implicit detectors use negative feedback in the log domain to produce the RMS signal. By processing the signal in the log domain, the implicit detector has an improved dynamic range. However, the feedback topology limits the practical bandwidth of the detector. VCAs that are presently available for compression cir¬ cuits, such as the that described in a product data sheet for a "Voltage-Controlled Amplifier/OVCE, " model SSM-2018 produced by Analog Devices, Inc., 1981, use a negative feedback architecture around a gain core stage to produce a differential output current and a differential feedback current. A transresistance stage comprising a pair of re¬ sistors responds to a differential input voltage and the differential feedback current to produce a differential voltage. A one pole transconductance stage uses a capaci¬ tor to limit the VCA's high frequency gain to stabilize the feedback loop and supply a differential drive current to the gain core stage. The VCA also includes a second gain core stage and a differential pair of transistors for ad- justing the effective capacitance of the transconductance stage to maintain a constant loop gain. The second gain core stage and its control circuitry use a large number of components to maintain the loop gain, which increases cost and reduces accuracy. SUMMARY OF THE INVENTION The present invention provides a signal conditioning circuit that has a programmable compression ratio in a de¬ sired audio range and amplitude limiting and expansion ca- pabilities outside that range. The present circuit re¬ quires fewer components and pins on an IC package, uses less capacitance and exhibits better accuracy than prior conditioning circuits. This is accomplished by merging the buffering and lev- el detection functions into a single input buffer, which produces a rectified version of the input signal and also produces a buffered input that substantially follows the input signal. The rectified signal is applied to an aver¬ aging circuit which produces an averaged input. An inter- face circuit establishes three different compression regions. For normal input signals that are above the noise level and below the level at which signal clipping can oc¬ cur, the user can select a desired compression ratio. When the input signal becomes large and approaches a level at which clipping can occur, the interface circuit automati- cally increases the compression ratio to limit the output level; the circuit is preferably designed so that the change in compression ratio occurs at the rotation point. If, on the other hand, the input signal falls so low that it becomes too noisy, the interface circuit reduces the compression ratio to downwardly expand the output level; the circuit is preferably designed so that the change in compression ratio occurs at a break point. In response to the averaged input and its corresponding compression ratio, the interface circuit produces a gain signal. A VCA ampli¬ fies the buffered input by an exponential function of the gain signal to produce a compressed output signal. A sin¬ gle capacitor is connected between the VCA and the input buffer to isolate the VCA and rectification circuitry in the buffer from DC variations in the conditioning circuit. For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a signal conditioning circuit in accordance with the present invention; FIG. 2 is a plot of characteristic compression curves for the signal conditioning circuit shown in FIG. 1; FIG. 3 is a schematic diagram illustrating a preferred implementation of an input buffer and an averaging circuit used in the signal conditioning circuit of FIG. 1; FIGs. 4a, 4b, 4c, 4d and 4e are plots of the input voltage signal, a pair of class AB output stage currents in the input buffer, the buffered voltage signal, and the rec¬ tified current, respectively, in the circuit of FIG. 3; FIG. 5 is a schematic diagram illustrating a preferred implementation of the interface circuit used in the signal conditioning circuit of FIG. 1; and FIG. 6 is a schematic diagram illustrating a preferred implementation of the voltage controlled amplifier used in the signal condition circuit of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION The present invention provides a signal conditioning circuit possessing a variable compression capability for audio signals in a desired audio range, a limiting function for preventing distortion of large input signals, and a downward expansion capability for suppressing noise sig¬ nals. The circuit topology merges the buffering and recti¬ fication functions into a single input buffer. The topol¬ ogy reduces the total number of components, which increases the circuit's accuracy and reduces the number of pins on an IC package. The preferred embodiment uses primarily NPN transistors, which are typically faster than PNP transis¬ tors, to improve the circuit's speed and reduce signal dis¬ tortion. Furthermore, the VCA and rectifier can be isolat¬ ed from DC variations in the conditioning circuit by a sin- gle blocking capacitor. FIG. 1 is a block diagram of the present signal condi¬ tioning circuit 10. A signal source (not shown) , such as a microphone, generates an input signal V in that is applied to the conditioning circuit 10. In response to V in , the conditioning circuit 10 produces an averaged input V L and also produces a buffered input V buf that approximately fol¬ lows V in . In response to the averaged input V L , the conditioning circuit sets a compression ratio, generates an internal gain signal V c , and amplifies the buffered input V buf by an exponential function of the gain signal V c to pro¬ vide a compressed output signal V out . The conditioning cir¬ cuit 10 is preferably fabricated as an integrated circuit (IC) and may have as few as 8 pins. The high and low sup¬ ply voltage pins V dd and GND, respectively, are not shown. The RMS output signal V out is given by : ( v V v out ' rms = (V v ι-n ) / rms e° Vc/Vt (1- L ') which in dB is expressed as : where (V in ) dB =20log 10 ( (V in ) rms ) , (V out ) dB =20log 10 ( (V outa , and K 1 =20log 10 (e) , and e is the natural logarithm base. The change in output level as a function of the change in input level can be derived from equation 2, and is given as fol¬ lows: ΔV„ Δ<V OTt ) dB =K 1 -^-S+Δ(V in ) dB (3) 1 Using Δ (V 0Ut ) dB =—Δ (V in ) dB where r is the compression ratio, r and solving equation 3 gives: ΔV„=—^ -Δ(V 1n ) K,r in' B (4) In the conditioning circuit, a given value of V c is chosen to correspond to a reference input level for CVi n ) < ~ . Letting these values be V co and V^, ΔV C =V C -V C0 , and Δ (V in ) dB =(V in ) dB -(V rp ) . The reference input level ^ is commonly referred to as the rotation point. Solving equa¬ tion 4 provides the control equation for the gain signal V c that produces the desired compression ratio r: V t (r-1) r , , c -Vo o —H t(v in ) dB -v rp 3 (5) To implement the control equation, the input signal V in is applied through the IC's MICIN to an input buffer 12. The buffer merges the normal buffering and rectification functions into a single circuit that produces both the buf¬ fered input V buf at a BUFOUT pin and a full-wave rectified version I R of the input V in . The buffer 12 is preferably a voltage follower that presents a high impedance, suitably 100 KΩ, to the signal source to avoid loading the source, and uses negative feedback so that V buf follows V in . The buffer includes rectification circuitry that senses V buf to produce the rectification current I R . An averaging circuit 14 produces the time-averaged voltage V L in response to the rectified current I R , where V L is preferably proportional to the log mean-square of I R . The integration period of the averaging circuit is program¬ med through a pin CAVE with a capacitor C ave connected to CAVE. The sensitivity of V L to changes in the rectified current is reduced as the capacitance of capacitor C ave is increased. An interface circuit 16 establishes three different compression regions that define the conditioning circuit's characteristic curve, in which V ouC in dB is plotted against V in in dB. The slope of the curve in the respective regions is equal to the reciprocal of the compression ratio r asso¬ ciated with that region. For normal input signals that are above the noise level and below the level at which signal clipping can occur, the user can select a desired compres¬ sion ratio, suitably between 1:1 and 10:1. When the input signal becomes large and approaches a level at which clip¬ ping can occur, the interface circuit automatically in¬ creases the compression ratio, preferably to approximately infinite compression, to limit the output level; the cir- cuit is preferably designed so that the change in compres¬ sion ratio occurs at the rotation point. If, on the other hand, the input signal falls so low that it becomes too noisy, the interface circuit reduces the compression ratio, suitably less than 1:1, to downwardly expand the output level; the circuit is preferably designed so that the change in compression ratio occurs at a break point. The desired audio range is preferably 60 dB, which is satisfied by a circuit design in which the input signal at the rotation point is one thousand times its value at the break point, suitably 1 V ^ at the rotation point and 1 tnV, ^ at the break point. The rotation point is preferably slightly below the input level at which clipping or other distortion would occur and the break point is preferably just above the noise floor. This allows the normal com¬ pression curve to be used for most of the input range, with excessively large inputs limited and low inputs in the noise range suppressed. The interface circuit computes the square root of V L so that to a first order approximation V L represents (V^^. As described in equation 5, the interface circuit 16 shifts V L with respect to a rotation point reference voltage V^, scales it in accordance with the compression ratio for the particular region, and adds the reference gain signal V co . The square root operation can be carried out in the averag¬ ing circuit, but would require additional circuitry. The compression ratio for the normal region, typically between 1:1 and 10:1, is programmed through a COMPR pin by setting the value of an external resistor R comp . A VCA 18 has a current input 19 that is connected to a VCAIN pin. An external load 21, preferably a resistor R in series with a capacitor C, is connected between the buf¬ fer's BUFOUT pin and the VCAIN pin. The capacitor C blocks the DC component of the buffered voltage V buf at the BUFOUT pin such that a substantially AC current I buf is supplied to the current input 19 of the VCA. The capacitor also blocks small DC bias currents in the VCA from the buffer's full wave rectifier. The VCA converts the current signal I bu£ to a voltage signal that follows the input signal V in , and am- plifies that voltage signal by an exponential function of the gain signal V c as described above in equation 1. The amplified output of VCA 18 is applied to by a current-to- voltage converter 22 to provide the compressed audio signal V ou t • FIG. 2 is a plot of the conditioning circuit's charac¬ teristic compression curve 23 described in equation 2 above, illustrating the downward expansion of input signals below the break point BP, programmable compression ratios for input signals in the desired range, and limiting of input signals above the rotation point RP. As shown, the conditioning circuit has a gain of 10 dB at the rotation point RP. The gain signal at this point, and hence the output level, are constant for different compression ratios. Above the rotation point, the output is held sub- stantially constant to avoid distortion and clipping. In the desired input signal range between the rotation point and the breakpoint, the compression of the audio signal can be set between preferably 1:1 and 10:1. For audio signals below the breakpoint, e.g. when a person is not speaking, the compression ratio is reduced (downward expanded) below 1:1 to suppress background noise. These downward expan¬ sion, variable compression and limiting functions improve vocal clarity without introducing distortion or amplifying noise signals. As shown in FIG. 3, the input buffer 12 is a first stage voltage follower comprising a differential-to-single ended operational amplifier Al, a second stage transistor Ql and a class AB. output stage 24 that are connected in a negative feedback loop, and a summing current mirror 26 which provides the full wave rectified output. The dynam- ics of the differential amplifier Al force the voltage at its non-inverting terminal 28 to follow the voltage at its inverting terminal 30. V in is applied to the inverting ter¬ minal 30 and the output of the buffer at BUFOUT is fed back to the non-inverting terminal 28, causing the voltage V buf to follow the input signal V in and to be buffered from the signal source by the internal resistance of amplifier Al. In the preferred embodiment the low voltage supply is at ground reference potential. Thus, the AC input signal V in must be level shifted so that the AC output signal V buf can swing between the low and high voltage supplies without clipping. However, if the low supply is -5 V, level shift¬ ing is not be required. Level shifting is accomplished by providing an internal DC offset in amplifier Al so that the voltage at its non-inverting terminal 28 equals the input voltage V iπ plus the DC offset. The amplifier Al is designed with an internal gain so that a constant input generates a voltage V A1 at its output terminal 31 having a nominal value at a bipolar transistor base-emitter differential, approximately 0.7 V. The output voltage V A1 is applied to the base 32 of the second stage transistor Ql, turning it on. The emitter 34 of transistor Ql is connected to ground, and its collector 35 is coupled to the class AB output stage 24. The amplifier Al responds to an AC input signal V in , by perturbing the voltage V M at base 32, which changes the amount of base current driven into transistor Ql, which in turn changes the transistor's collector current, and as a consequence its collector volt¬ age. The second stage transistor Ql amplifies the pertur- bations in the amplifier's output voltage V A1 to control the class AB output stage 24. The class AB output stage 24 comprises an NPN transis¬ tor Q2 whose emitter 36 is connected to the base-collector junction 38 of a diode-connected NPN transistor Q3. Tran- sistor Q2's collector 39 is connected to a current mirror Ml which draws current from the high voltage supply V dd . The base-collector junction 38 of Q3 is also connected through the BUFOUT pin to the load 21 and is fed back to the non-inverting terminal 28 of amplifier Al. The AC in- put signal V in modulates the voltage at transistor Ql's col¬ lector 35, which is connected to the emitter 40 of transis¬ tor Q3, causing transistors Q2 and Q3 to conduct on alter¬ nating half cycles of V in . Q2 supplies a current I Q2 to load 21 while Q3 sinks a current I Q3 from the load so that volt- age V buf at the BUFOUT pin follows the input voltage V in plus the DC offset. Ideally, for best performance of the full wave recti¬ fier Q3 is fully off when Q2 is on, and vice versa. Howev¬ er, this causes distortion when the input voltage V in is crossing 0 V. A voltage multiplier 44 is connected in par¬ allel with transistors Q2 and Q3 to supply a bias voltage v b±as across the transistors to reduce this crossover distor¬ tion. The voltage multiplier 44 comprises a pair of resis- tors Rl and R2 that are connected across the base-collector and base-emitter junctions, respectively, of an NPN tran¬ sistor Q4. The emitter 46 of transistor Q4 is connected to the emitter 40 of transistor Q3, and the collector 48 of transistor Q4 is connected to the base 50 of transistor Q2. A current source I bias supplies current, suitably 50 μA, from the high supply V dd to the multiplier 44 such that V bias is approximately equal to (1+— Rl)V be , where V be is the base- R2 emitter voltage of transistor Q . The resistance of resis¬ tor Rl is less than that of resistor R2, suitably one quar- ter of R2, so that V bias is between one and two diode drops. Thus, when either transistor Q2 or Q3 is conducting the other transistor is turned off. The dynamics of the negative feedback around the buff¬ er circuitry force the voltage at the non-inverting termi- nal 28 of Al to follow the voltage at inverting terminal 30 plus the DC offset. Transistor Ql sinks approximately all of the current I bias flowing through voltage multiplier 44. Thus, transistors Q2 and Q3 idle at very small currents, preferably less than 30 nA. Because transistors Q2 and Q3 idle at very low currents, the class AB output stage is very efficient. When an AC input signal V in , as shown in FIG. 4a, is applied to the inverting terminal 30 of amplifier Al, transistors Q2 and Q3 deliver power to load 21 with each transistor conducting currents I Q2 and I Q3 , respectively, on alternate half cycles of the input signal, as shown in FIGs. 4b-4c. Specifically, when voltage V in at inverting terminal 30 is increasing, amplifier Al reduces the base current to transistor Ql, which increases the voltage at its collector 35 and pulls up the voltage at the base 50 of Q2. Transistor Q2 turns on and supplies current to load 21 so that V buf increases and follows the input voltage V in plus the DC offset, as shown in FIG. 4d. Conversely, when the voltage V in at inverting terminal 30 is reduced, amplifier Al drives transistor Ql harder, which reduces the voltage at its collector 35 and pulls the voltage at the emitter 40 of transistor Q3 down. Transistor Q3 turns on and draws current from load 21 so that V buf is reduced and follows the input voltage V in . The second function of the input buffer 12 is to pro¬ duce a full wave rectified version I R of the current I buf supplied to load 21. Full wave rectification is achieved using an NPN transistor Q5 and the current mirror Ml. The base-emitter junction of transistor Q5 is connected across the base-emitter junction of transistor Q3 such that the current I QS that flows through transistor Q5 replicates the current I Q3 flowing through transistor Q3 during the nega¬ tive half cycle of the input signal V in . One branch of cur- rent mirror Ml is connected to supply the collector cur- rents for both transistors Q2 and Q5 so that the current mirror Ml conducts during both the positive and negative half cycles of the input signal V in , thereby producing the full-wave rectified current I R (shown in FIG. 4e) through its other branch. The current mirror Ml supplies the cur¬ rent I R to the averaging circuit 14. By merging the full- wave rectifier with the buffer circuit, the rectifier can directly sense the current I buf supplied to the VCA, which improves the accuracy of the conditioning circuit. As shown in FIG. 3, the preferred averaging circuit 14 is an explicit log mean-square detector that produces the log mean-square voltage V L in response to the full-wave rectified input current I R . The rectified current I R is ap¬ plied to diodes Dl and D2, that are connected in series be- tween an input node 52 and ground, to produce a log square voltage signal V x at the input node 52. In general, n di¬ odes could be connected in series to effectively raise the input signal to the n th power. The logarithmic nature of the diodes' I-V (current v. voltage) curves produces the voltage signal V x that is equivalent to the voltage signal created by the square of the input current I R flowing through a single diode normalized by the reverse saturation current. The voltage signal V- L is given by: I i 2 V 1 =2V t ln [ -S ] =V t ln [ - ] (6 ) J s l where V t is the thermal voltage and I s is the diode reverse saturation current. The relation described in equation 6 is valid in forward bias for the base-emitter voltage in a transistor as well as diodes. The diodes in the condition¬ ing circuit are preferably diode connected NPN transistors. The log square voltage signal V 1 is applied to a low pass filter (lpf) 53, preferably a first order filter, which approximately performs the "mean" operation. The filter comprises an NPN transistor Q6, whose collector 54 is connected to the high voltage supply V dd , the external capacitor C ave connected between the emitter 55 of Q6 and ground, and a current source ISl which draws a bias current I b from the Q6/C ave junction to ground. The voltage signal V- L is applied to the base 56 of Q6 such that a portion of its exponential emitter current I e is supplied to the ca¬ pacitor C ave . The current source ISl draws the bias current I b , suitably 3μA, from I e , producing a net capacitor current I c that is equal to (I e - I b ) . When the emitter current exceeds the bias current, I c flows into the capacitor C ave and charges it to increase its voltage. Conversely, the capacitor C ave is discharged when the net current I c is nega¬ tive. The filter's cut-off frequency ω 0 is set by the capac¬ itance of capacitor C ave , which is nominally 10μF. Larger capacitances increase the integration time and reduce the cut-off frequency. Conversely, smaller capacitances reduce the integration time and increase the cut-off frequency. In general, the frequency response of a low pass filter is described by the differential equation: -g = -ω 0 X+ω 0 I(t) (7) where I(t) is the input to the filter and X is its time response. To a first order approximation, the time re- sponse X equals the mean of the input I(t) . The voltage V L across the capacitor C ave , ignoring the effects of base current, is given by the following equa¬ tions: τ -r dVL - T P ( V -- V L ) /V -- T ( R ) •J -C -L a e-^ - 1 S e 1 b ^ ti > Rearranging equation 8, v t dt c ave v t c ave v t Substituting X=e V ' in equation 9 and combining equa¬ tions 6 and 9 gives: where ω n = — . 0 Cave V v t Equation 11 is a ' differential equation that describes the lowpass filter 53, where X is the time response of the I 2 filter to an input . Therefore, to a first order ap- proximation, I 2 1 X =mean(—- -) = _±_mean(l R ) (12) • Vs I b I s Substituting equation 12 into X=e VL/Vt and solving for V L : V L = V t ln(-^-mean(l ) ) (13) I b I S The capacitor voltage V L , which is a logarithmic func¬ tion of the mean-square input current I R , is provided at an output 57 that is connected to the interface circuit. As shown in FIG. 5, the interface circuit 16 prefera¬ bly comprises a compression circuit 58, a limiting circuit 59 and a downward expansion circuit 60 for generating the gain signal V c in accordance with equation 5 to achieve the compression ratios for the three different compression re¬ gions shown in FIG. 2. The limiting circuit 59 controls V c for input signals above the rotation point while the com¬ pression and downward expansion circuits 58 and 60 are in- active. Similarly, the compression circuit 58 controls the gain signal for input signals between the rotation and break points and the limiting and downward expansion cir¬ cuits 59 and 60 are inactive. When the input falls below the break point, the compression and downward expansion circuits 58 and 60 control the gain signal. Voltage V L at the output 57 of the averaging circuit 14 (shown in FIG. 3) is level shifted up by diode D3. The diode D3 is biased at approximately the same quiescent cur¬ rent I b as transistor Q6 (shown in FIG. 3) by current sour- ces IS2 and IS3, which are connected in series with diode D3 between the high voltage supply V dd and ground. The lev¬ el shifted voltage V L is buffered by a voltage following operational amplifier A2 so that one side of a resistor R3, suitably 1.2 KΩ, which is connected to an output terminal 61 of A2, can be held at the shifted voltage level V M with¬ out loading diode D3 and the averaging circuit 14. The voltage V^ at input terminal 61 is given by: where A is the transistor junction area scale factor for diodes Dl and D2, and is suitably equal to 10. A DC reference voltage V^, which corresponds to the rotation point RP on the characteristic curve 23 shown in FIG. 2, is established at the base 62 of an NPN transistor Q7. A diode D4 is connected between the emitter 63 of transistor Q7 and ground. A current source IS4 supplies bias current I rot , suitably between 10μA and 100μA, to tran¬ sistor Q7 and diode D4 so that the reference voltage V^ is equal to V M when the RMS value of the input signal V in is at the rotation point. The reference voltage is given by: The other side of resistor R3 is connected to the base 62 of transistor Q7 so that the difference between V^ and Vj a causes a current I corap to flow through resistor R3. From equations 14 and 15 the current is: From equations 14 -16 , when the input signal is at the rotation point , V A2 =V rp , I R =I r 2 ot A 2 and I comp is zero . When V ω is less than V^, ^ (I R ) <I rot A and I comp is positive (designat¬ ed as I corop + in FIG. 5) . Conversely, when V M is greater than V rp , y' d ) >I rot A and I comp is negative (designated as I comp " in FIG . 5 ) . The interface circuit 16 supplies a portion of I comp + and substantially all of I comp " by drawing current through a pair of resistors R4 and R5, respectively, which are con¬ nected between a reference voltage V ref , suitably approxi¬ mately 2.5V, and negative and positive nodes 64 and 65, re- spectively. The differential gain signal V c is developed across nodes 64 and 65, and is controlled by the amount of current flowing through resistors R4 and R5. The compres¬ sion and downward expansion circuits 58 and 60 direct a portion of I oomp + through R4, which pulls the negative side of the differential gain signal V c down and increases V c . The limiting circuit 59 directs the current I comp " through R5, which pulls the positive voltage down and reduces the gain signal V c . A current source IS5 supplies current I att , suitably between 0 and 100μA, to R5 to establish the refer¬ ence gain signal V co . Equivalently, the current source IS5 could draw current from R4. Drawing the compression currents I comp + and I comp " through R4 and R5, respectively, in the manner described produces the differential gain signal V c , which in the compression region is given by: The square root of the mean square rectified current is computed by setting the resistance of resistors R4 and R5 to approximately half the resistance of R3, suitably 600Ω. The ratios of R4 to R3 and R5 to R3 results in the gain signal being effectively multiplied by 1/2, which is equiv¬ alent to taking the square root. Thus, the gain signal V c generated by the interface circuit 16 satisfies the control relation given in equation 5. The compression circuit 58 comprises a pair of tran- sistors Q8, Q9 whose emitters 66, 68 are connected to the base 62 of transistor Q7 to supply the positive current com "- Tne base 70 of transistor Q8 is connected to the collector 71 of transistor Q7 and its collector 72 is con¬ nected to the high voltage supply. The collector 73 of transistor Q9 is connected to the negative node 64, and its base 74 is connected to a voltage divider 76 that sets the compression ratio r, which controls the fraction ^ r 1 ^ of r the current I comp + supplied by transistor Q9. When the RMS value of V in is below the rotation point, voltage V^ at input terminal 61 is less than voltage V^ at the base 62 of transistor Q7, which turns transistors Q8 and Q9 on so that they conduct and together supply the cur¬ rent I comp + . The current drawn from the reference voltage through R4 lowers the voltage level at the negative node 64 causing the gain signal V c to increase. As V ω is further reduced, the gain signal V c is increased to maintain the nominal compression ratio. The voltage divider 76 comprises a DC voltage source 78, suitably 0.2 V, which holds the voltage at the output terminal 79 of a voltage follower A3 at approximately 0.2 V above the voltage at the base 70 of transistor Q8. A resistor R6, suitably 1 KΩ , is connected between output terminal 79 and the base 74 of transistor Q9, which is also connected through the COMPR pin to the external resistor R oomp . With proper selection of the resistance of R comp , the voltage at the base 74 of transistor Q9 can be raised above or lowered below the voltage at the base 70 of transistor Q8, so that the fraction — (r-1) of current I comp + that is supplied by transistor Q9 can be set between approximately 0 and 1. This is equivalent to setting the nominal com- pression ratio between 1:1 and approximately infinity-to- one. The limiting circuit 59 comprises a transistor Q10 that keeps transistor Q7 in its active region when I comp is negative and controls the application of I comp " to resistor R5. Transistor QlO's base 80, emitter 82 and collector 83 are connected to the collector 71 of transistor Q7, a cur¬ rent source IS6, and the high voltage supply, respectively. A diode D5 is connected between the base 62 of transistor Q7 and current source IS6 to supply the current I COmp ~ - The collector 88 of a transistor Qll is connected to positive node 65, and its base-emitter junction 90 is connected across diode D5 so that transistor Qll mirrors the current I comp " flowing through diode D5 to positive node 65. When V M is less than V^, transistor Q8 conducts, which holds the voltage at the base 80 of transistor Q10 at ap¬ proximately a base-emitter voltage above V^ . Consequently, diode D5 does not conduct and all of the current from cur- rent source IS6 flows through transistor Q10. Conversely, when V M exceeds V^, transistors Q8 and Q9 turn off. This reduces the voltage at the bases of Q8 and Q10 and conse¬ quently at the cathode 86 of diode D5 so that diode D5 con¬ ducts and supplies I comp ". Transistor Qll mirrors I comp " to node 65 to reduce the gain signal V c . As V M is increased further, diode D5 conducts more current to supply I comp " , which further reduces the gain signal V c and maintains the desired compression ratio. In the preferred embodiment, the limiting circuit in- creases the compression ratio from the nominal value to infinity by directing all of I comp " to the positive side of the differential gain signal. Alternatively, a differen¬ tial pair of transistors and a voltage divider circuit sim¬ ilar to those used in the compression circuit 58 could be used to provide a variable compression ratio for the limit¬ ing circuit 59. The downward expansion circuit 60 sets a DC reference voltage V bp that corresponds to the lower break point BP in the characteristic curve 23 shown in FIG. 2. When V M falls below V bp , the downward expansion circuit 60 supplies a por¬ tion of the current I comp + that flows through R3. This re¬ duces the amount of current supplied by transistors Q8 and Q9. Thus, instead of allowing the compression circuit 58 to increase the gain signal V c to maintain the nominal com- pression ratio, the downward expansion circuit 60 reduces V c so that the compression ratio is less than 1:1. The downward expansion circuit 60 comprises a resis¬ tor R7 that is connected between terminal 61 and the base 92 of an NPN transistor Q12. A diode D6 is connected be- tween the emitter 94 of transistor Q12 and ground. A cur¬ rent source IS7 supplies current I de , suitably lμA, to tran¬ sistor Q12's collector 96. The device area scale factor of Q12 and D6 is suitably chosen to be greater than 1, typi¬ cally 10. Current I de flows through transistor Q12 and di- ode D6, and establishes the reference voltage V bp at the base 92 of transistor Q12. Transistor Q12 and diode D6 are biased so that the DC reference voltage V bp corresponds to an input signal that is 60 dB less than that corresponding to the DC reference voltage V-^. The base-emitter junction of a transistor Q13 is con¬ nected across the collector-base junction of transistor Q12. When V^ is less than V bp , transistor Q13 turns on so that it can supply the current I e flowing through resistor R7. The collector 98 of transistor Q13 is connected to a current mirror M2, which mirrors I e to the base 62 of Q7, thereby supplying a portion of I comp + . Conversely, when V^ exceeds V bp , transistor Q12 saturates and the voltage across the base-emitter junction of Q13 is insufficient to turn it on. As Vj a is reduced, I comp + and I e increase. The addition of I e fights the increase in I comp + so that the portion of the current supplied by transistors Q8 and Q9 does not increase as rapidly as I comp + - Furthermore, by choosing resistor R7 to have less resistance than resistor R3, I e increases more rapidly than I comp + . This causes the current in transistor Q9 to actually decrease as V M falls. The same result can be achieved by setting the resistances of R7 and R3 to be the same and by making mirror M2 have a fixed gain greater than 1. By reducing the portion of I comp * that is supplied by transistors Q8 and Q9, the downward expansion circuit 60 effectively reduces the compression ratio r, as described in equation 16, from its nominal value to a value less than 1:1. If V^ falls far enough below V bp , I e will actually ex- ceed I comp + . In this case, the extra current will flow through the limiting circuit 59, resulting in a further reduction of the gain signal V c . As shown in FIG. 6, the preferred current mode VCA 18 uses a negative feedback architecture around a differential gain core stage 100. For clarity, bias currents are desig¬ nated with a capital I and AC signal currents are designat¬ ed with a lower case i. In describing the VCA, the buffer current I buf is given as i buf . The buffer current i bu£ is injected into the signal path through the VCAIN pin at current input 19 and is converted to a differential voltage V D by a transresistance stage 102. The voltage V D is applied to a transconductance stage 104 which limits the VCA's high frequency gain with a capacitor and stabilizes the feedback loop. The transconductance stage supplies a differential drive current (I DC -i g ,I DC +i g ) , where I DC is the gain core's bias current, that drives the gain core stage 100. The gain core stage 100 produces two differential out¬ put currents that sum to the differential drive current supplied to the gain core by the transconductance stage. The fraction of the drive current provided to each output current is controlled by the application of gain signal V e¬ to the gain core stage 100. A differential feedback cur¬ rent (I- L -ii,Ix+ix) is returned to the transresistance stage 102 to complete the negative feedback loop. A differential output current (I 0 -i 0 ,1 0 +i 0 ) is applied to the differential current-to-voltage converter 22 to produce output voltage V out =2Ri 0 at pin VOUT where R is the resistance of converter 22. The gain core stage 100 comprises two pair of differ- entially connected NPN transistors Q14, Q15 and Q16, Q17. The emitters 106 and 108 of transistors Q14 and Q15, re¬ spectively, are connected and together supply the tail cur¬ rent I DC -i g , and the emitters 110 and 112 of transistors Q16 and Q17, respectively, are connected and together supply the tail current I DC +i g . The collectors 114 and 116 of tran¬ sistors Q15 and Q16, respectively, are connected to the current-to-voltage converter 22 to supply the differential output current, and the collectors 118 and 120 of Q14 and Q17, respectively, are connected to the transresistance stage 102 to supply the differential feedback current. The bases 122 and 124 of Q15 and Q16, respectively, are con¬ nected at a positive node 126, and the bases 128 and 130 of Q14 and Q17 are connected at a negative node 132. The gain signal V c generated by the interface circuit 16 (shown in FIG. 5) is applied across the positive and negative nodes 126, 132 causing the tail currents I DC -i g and I DC +i g to be split into the differential feedback and output currents, I_ . ±i ι and I 0 ±i 0 / respectively, where I 0 =GI DC , i 0 =Gi g , I 1 =(1-G)I DC and i 1 =(l-G)i g . The splitting fraction G varies between 0 and 1 in response to the gain signal V c according to the following relation: ~ v c /v t G - iv ( 18 ) 1 +e c ' The transresistance stage 102 comprises a pair of di- odes D7, D8 that are connected between a reference voltage V refl , approximately 1 V lower than the high voltage supply V dd , and the collectors 118 and 120 of transistors Q14 and Q17, respectively. Alternately, the diodes D7 and D8 can be implemented as the emitter-base junctions of a pair of NPN transistors having a common base connection to V refl . The input current i buf is injected into the signal path at VCAIN between diode D8 and transistor Q17 such that di- odes D7 and D8 conduct currents I 2 +i 2 and I 2 -i 2 / respec¬ tively, to produce differential voltage V D . Ignoring base currents, the current flowing from diode D7 is equal to the current supplied to transistor Q14's collector 118, and diode D8's current equals transistor Q17's collector cur¬ rent minus the input current i buf . Thus, and I 2 -i 2 =I 1 +i 1 -i buf (20) Solving equations 19 and 20, and Equation 22 shows that although the input current i buf is injected into one side of the signal path it is effec¬ tively injected differentially. However, as described in equation 21, the bias current I 2 has a common mode component of -i buf /2. This common mode component is applied to both sides of the signal path and is canceled out by the trans- resistance stage 102. The resistance of the transresistance stage is 2r, where r is the dynamic impedance of diodes D7 and D8. The dynamic impedance r is inversely proportional to the bias currents flowing through diodes D7 and D8. Since the bias current flowing through the diodes is provided exclusively from gain core stage 100, the bias current I 2 = (l-G)I DC and r = V t /(1-G)I DC . Thus, the differential voltage V D measured across the diodes is: 2V i V D =r [(I 2+ i a ) -(I 2 -i 2 )] = (1 ^ 3 t )j (23) The transconductance stage 104 is a low pass filter, preferably a first order filter, that converts the differ- ential voltage V D to the differential drive current I DC -i g and I DC +i g , where i g =gm(f)V D . The effective transconductance function for a first order low pass filter is: where f is frequency, f 0 is the cutoff frequency and gm 0 is the low frequency gain. By rolling off the gain at high frequencies, the second order transistor effects that would otherwise become significant at higher frequencies are re¬ duced to ensure stability. The transconductance stage 104 comprises a current source IS8, suitably 10μA, which supplies current to an emitter-coupled pair of PNP transistors Q18 and Q19. This causes bias currents I 3 , approximately 5μA, to flow through the collectors 136 and 138 of transistors Q18 and Q19, re¬ spectively. The bases 140 and 142 of transistors Q18 and Q19, respectively, are connected to cathodes 144 and 146 of diodes D7 and D8, respectively. Thus, the differential voltage V D shifts the relative base voltages of transistors Q18 and Q19, causing their collector currents I 3 to be perturbed by +i 3 and -i 3 , respectively. A current mirror M3 is connected to collectors 136 and 138 so that the mirror sinks a current I 3 +i 3 at a node 148, which is connected to transistor Q19's collector 138. As a result, a current 2i 3 alternately charges and discharges a capacitor C v , suitably 5 pf, that is connected between node 148 and ground. Because the impedance of the capaci¬ tor C v is reduced at higher frequencies, the gain of the transconductance stage falls off as the frequency is in- creased. A current source IS9 supplies tail current, suitably 2 ma, to an emitter-coupled pair of NPN transistors Q20 and Q21, whose collectors 150 and 152 are connected to emitters 106 and 108 of transistors Q14 and Q15, and to emitters 110 and 112 of transistors Q16 and Q17, respectively: this sup¬ plies the differential drive current I DC -i g and I DC +i g , where I DC is nominally 1 ma. A reference voltage V re£2 , suitably 1 V plus a diode voltage above ground, is connected to base 154 of transistor Q21. Base 156 of transistor Q20 is con- nected to node 148 at the top of capacitor C v . The base currents of transistors Q20 and Q21 are assumed zero; how¬ ever, in practice this can be ensured by using Darlington pairs in place of Q20 and Q21. At DC (i buf =0) , the capacitor voltage V c is substan- tially equal to V re£2 , so that the tail current 2I DC is split evenly between transistors Q20 and Q21 and i g =0. When the input current i bu£ is positive, V D is positive, and 2i 3 dis¬ charges capacitor C v . This lowers the voltage at transistor Q20's base relative to the voltage at transistor Q21's base and reduces the current flowing through Q20 by i g . This in turn reduces the differential feedback current by i 1# which fights the positive input current i bu£ . Conversely, when i bu£ is negative the capacitor C v is charged and a larger portion of the current flows through transistor Q20 providing the negative feedback that fights the negative input current. The output voltage V out produced by the current-to-volt¬ age converter 22 in response to the differential drive cur¬ rent is described by: V out =2GRi g (25) The drive current i g produced by the transconductance stage 104 is given by: i =gm(f)V D (26) Substituting equations 23 and 22, i x = (1-G)i g , and solving for i g produces: ι„ = (1-G) L buf (27) 1 + - DC 2V t gm(f) Substituting i g into equation 25, using _ = e Vc Vt and rearranging gives: V out = H(f)e Vc Vt Ri buf (28) where and V in « Ri buf (30) When the loop gain 2gm 0 V t /I DC is much greater than 1, H(f) is approximately 1 and the input/output gain function described in equation 28 is the desired exponential func¬ tion of V c given originally in equation 1. Furthermore, the loop gain is held constant regardless of the amount of gain extracted from the VCA. Thus, the VCA can provide the de- sired 60 dB of gain up to approximately 100 Khz for a typi¬ cal IC process. Additionally the signal distortion shown by transistors, specifically the PNP emitter-coupled pair (Q18, Q19) in the transconductance stage 104, in response to large input signals is substantially canceled by the opposing distortion in the transresistance stage diodes (D7, D8) . Control feedthrough is introduced by the fact that input node 19 moves in response to gain changes. The addi- tion of op amp A4 holds node 19 constant with gain changes. Its non-inverting 160 input is connected to a reference V re£3 , which is suitably equal to or more positive than V re£ in FIG. 5. The inverting input 162 is connected to node 19. The output 164 of op amp A4 is connected to the anode of diodes D7 and D8 or preferably the bases of npn tran¬ sistors used in place D7 and D8 as mentioned earlier. This establishes a negative feedback loop around op amp A4 that causes node 19 to be held at the same potential as V re£3 . Not only is control feedthrough minimized in this way, but the input impedance of the VCA is greatly reduced which improves the accuracy of the voltage-to-current conversion via the resistor/capacitor combination 21 shown in FIG. 1. While several illustrative embodiments of the inven¬ tion have been shown and described, numerous variations and alternate embodiment will occur to those skilled in the art. Such variations and alternate embodiments are contem¬ plated, and can be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims: WE CLAIM : 1. A circuit for conditioning an input signal in accordance with a compression ratio, comprising: an input buffer (12) having an output terminal (BUFOUT) , said input buffer responding to an input signal (V in ) by producing a buffer signal (V buf ) at said output ter¬ minal that follows said input signal and also producing a rectified input signal (I R ) ; an averaging circuit (14) that produces an aver¬ aged signal (V L ) from said rectified input signal; an interface circuit (16) that produces a gain signal (V c ) that is a function of said averaged signal and said compression ratio; and an amplifier (18) connected to amplify the buffer signal by an exponential function of said gain signal to produce a compressed output signal (V 0ϋT ) . 2. A circuit in accordance with claim 1, wherein said input buffer comprises a full-wave rectifier (24,26) that produces said rectified input signal, said input buff¬ er being connected through a capacitor (21) to said ampli- fier to isolate the amplifier and the full-wave rectifier from DC variations in the signal conditioning circuit. 3. A circuit in accordance with claims 1 or 2, wherein said circuit has a characteristic compression curve (23) that relates its compressed output signal to said in¬ put signal, said interface circuit comprising: a biasing circuit (D4,Q7,IS4) that establishes a rotation point on said characteristic compression curve; a comparator (R3) that compares said averaged signal to said rotation point; a compression circuit (58) that establishes a nominal value for said compression ratio, and scales said averaged signal in accordance with said nominal value to produce said gain signal when said avergaed signal is less than said rotation point; and a limiting circuit (59) that increases said com- pression ratio to a limiting value and scales said averaged signal in accordance with said limiting value to reduce said gain signal when the averaged signal exceeds said ro¬ tation point. 4. A circuit in accordance with claim 3, wherein said compression circuit has a programmable input (RCOMP) for selecting said nominal value, said interface circuit further comprising: a downward expansion circuit (60) that establish¬ es a breakpoint that lies below said rotation point on said characteristic compression curve, and reduces the value of said compression ratio when the averaged signal is less than said breakpoint. 5. A circuit in accordance with claims 3 or 4, wherein said rotation point corresponds to a high reference voltage, said interface circuit including an input terminal (57) for receiving said averaged signal, said biasing cir- cuit including a biasing transistor (Q7) having a base and establishing said high reference voltage at the biasing transistor's base, said comparator including a first input resistor that is connected between the biasing transistor's base and said input terminal such that a positive current flows through said first input resistor when said averaged signal is less than said high reference voltage, and said compression circuit comprising first and second compression transistors (Q8,Q9) that together supply said positive cur¬ rent, with a known fraction of said positive current flow- ing through said second compression transistor in accor¬ dance with said nominal compression ratio to provide said gain signal. 6. A circuit in accordance with claim 5, wherein said gain signal is a gain voltage and said averaged signal is proportional to the log mean square of the rectified input signal, said compression circuit further comprising: a reference voltage node; and a first output resistor connected between said reference voltage node and said second compression transis¬ tor such that said known fraction of said positive current flows through said first output resistor providing said gain voltage, said first output resistor having substan¬ tially one-half the resistance of said first input resistor such that the gain voltage is proportional to the log root- mean-square of said input signal. 7. A circuit in accordance with claim 5, wherein said gain signal is a differential gain signal that is formed as the difference between the known fraction of the positive current flowing through said second compression transistor and a limiting current, said limiting circuit comprising: a sensing circuit (Q10) that senses when said averaged signal exceeds said high reference voltage and causes a negative current to flow through said first input resistor, and that produces a control signal; a limiting circuit (D5) that supplies said nega¬ tive current in response to said control signal; and a mirror circuit (Qll) that mirrors a portion of said negative current to produce said limiting current at a level that increases said compression ratio to said lim¬ iting value. 8. A circuit in accordance with claim 4, wherein said breakpoint corresponds to a low reference voltage, said downward expansion circuit comprising: a second biasing circuit (Q12,D6) comprising a second bias transistor having a base, said second biasing circuit establishing said low reference voltage at the base of said second bias transistor; a second input resistor (R7) that is connected between said second bias transistor's base and the inter- face circuit's input terminal such that an expansion cur¬ rent (I e ) flows through said second input resistor when said averaged signal is less than said low reference voltage; and a current mirror (M2) that mirrors said expansion current to the base of said first biasing transistor to supply a portion of the positive current, thereby reducing the current flowing through said second compression tran¬ sistor, which in turn reduces the gain signal and said com¬ pression ratio, the resistance of said second input resis- tor being less than the resistance of said first input re¬ sistor such that said expansion current increases faster than said positive current as the averaged signal is re¬ duced. 9. A circuit in accordance with claim 1, wherein said averaging circuit comprises: a log converter (D1,D2) for producing a log sig¬ nal in response to said rectified input signal; a first multiplier (53) for producing a log power signal as the log of the input signal raised to a known power factor by scaling said log signal by said known power factor; and a log filter (53) for producing a log mean-power signal by averaging said log power signal. 10. A circuit in accordance with claim 1, wherein said compressed output signal is a differential output cur- rent, and said controllable amplifier is a voltage con¬ trolled amplifier (VCA) (18) that comprises: a gain core stage (100) that produces a differen¬ tial feedback current and said differential output current in response to a differential drive current and said gain signal; a transresistance stage (102) having a dynamic impedance that varies in accordance with said gain signal such that the loop gain of said VCA is approximately con¬ stant, said buffered input signal being injected with said differential feedback current to produce a differential voltage across said dynamic impedance; and a transconductance stage (104) that low pass fil¬ ters the differential voltage and supplies said differen¬ tial drive current.

Inventors: COPLEY PATRICK, FREY DOUGLAS R, COPLEY, PATRICK, FREY, DOUGLAS, R.
Applicants: ANALOG DEVICES INC, ANALOG DEVICES, INC. (ADI)
Application year: 1995
Main classification: H03G7
IPC codes: H03G7