Negative word line voltage regulation circuit for electrically erasable semiconductor memory devices

Abstract: A negative word line voltage regulation circuit, integratable in an electrically erasable semiconductor memory device for regulating a negative word line voltage (01-08) to be supplied to word lines (WL) of the memory device during an electrical erasure of the memory device, comprises an operational amplifier (2) with a first input (3) coupled to a reference voltage (GND), a second input (4) coupled to the negative word line voltage (01-08) and an output (6) controlling a voltage regulation branch (8,13,14,151-158), connected between an external power supply (VCC) and the negative word line voltage (01-08), to provide a regulation current (IR) for regulating the negative word line voltage (01-08). The output (6) of the operational amplifier (2) also controls a voltage sensing branch (7,9,10,121-128), connected between the external power supply (VCC) and the negative word line voltage (01-08), to provide a sensing signal (11) coupled to the second input (4) of the operational amplifier (2).

Description: The present invention relates to a negative word line voltage regulation circuit for electrically erasable semiconductor memory devices, particularly for Flash EEPROMs. Flash Electrically Erasable and Programmable ROMs (shortly, Flash EEPROMs) have memory cells which are formed by floating-gate MOSFETs. A Flash EEPROM memory cell is written by means of hot-electron injection into the floating gate, and is erased by means of Fowler-Nordheim tunneling of electrons through the oxide layer interposed between the floating gate and the semiconductor substrate. To activate the tunnel effect, a suffiently high electric field must be present in the oxide layer. This is normally achieved by applying a suitable electric potential difference between the source electrode and the control gate electrode of the memory cell, while the drain electrode is normally left floating. According to a known technique, such a potential difference is developed by biasing the source electrode of the floating-gate MOSFET with a high positive voltage of the order of 12 V, and keeping the control gate electrode grounded. In Dual Power Supply (DPS) memories the 12 V voltage is supplied by an external power supply, provided in addition to the 5 V (or 3 V) power supply. As an alternative, the 12 V voltage could be generated directly on-chip by suitable charge pumps which, starting from the available 5 V voltage, boost it to the required high voltage; memory devices of this kind are called Single Power Supply (SPS), since they only require one external power supply (namely, the 5 V one). The above-mentioned technique for erasing memory cells has however a number of drawbacks, mainly related to the high reverse bias condition of the PN junction formed by the source electrode and the substrate (normally at the ground potential). One of the most important drawbacks is that when a memory cell is biased to be erased, a current of the order of 10 nA starts flowing due to band-to-band tunneling. Since in Flash EEPROMs several memory cells (sometimes all of them) can be erased simultaneously, the individual currents sum up to values of some tens of milliamperes in memories with size of the order of some megabits. If on the one hand this is not a major problem in DPS memories, wherein the 12 V external power supply is able to provide the required current, on the other hand the high current consumption during erasure makes it impossible to use on-chip charge pumps to generate the 12 V voltage. In the United States Patent No. 5,077,691 a Flash EEPROM array with negative gate voltage erase operation is proposed which provides for erasing a Flash EEPROM memory cell by applying a relatively high negative voltage (-12 V to -17 V) to the control gate electrode of the cell, and a low positive voltage (+0.5 V to +5 V) to the source electrode. In this way, the source electrode bias voltage can be derived from the 5 V external supply, and the negative voltage for the control gate can be generated directly on-chip by means of charge pumps. When such a solution is adopted, it is however necessary to provide a suitable regulation for the on-chip generated negative voltage. The United States Patent No. 5,282,170 describes a negative power supply circuit for a SPS Flash EEPROM implementing said negative gate voltage erase operation. The negative power supply circuit comprises charge pumps for generating a high negative voltage to be supplied to word lines of the memory array during flash erasure of the memory cells, and a regulation circuit for regulating the negative voltage generated by the charge pumps, so that it is independent of the external 5 V supply. The regulation circuit comprises a comparator with the inverting input supplied with a reference voltage derived by resistive partition from the external supply; the non-inverting input is connected to the central node of a capacitive divider connected between ground and a sensing node in turn coupled to the negative voltage to be regulated (i.e. to the outputs of the charge pumps) via a pair of diode-connected P-channel MOSFETs; the output of the comparator controls the gate electrode of a pull-up P-channel MOSFET connected to the external supply and coupled to the sensing node via a further diode-connected P-channel MOSFET. During an initialization phase, the two capacitors of the capacitive divider are charged up to a voltage of about 2 V, and the sensing node is grounded. After the initialization phase, the comparator compares the voltage at the central point of the capacitive divider with said reference voltage and, if the former is lower than the latter, turns the pull-up MOSFET on: in this way, the load current of the charge pumps is increased, and the voltage on the word lines decreases in absolute value. A problem of the regulation circuit described above resides in that the potential on the sensing node is affected by the voltage drop across said pair of diode-connected P-channel MOSFETs, due to the current flowing through them during the regulation of the negative voltage. This means that the voltage compared by the comparator with the reference voltage does not exactly correspond to the voltage to be regulated. In view of the state of the art described, it is a first object of the present invention to provide a circuit for regulating the negative voltage supplied to the word lines of a Flash EEPROM during erasure, which overcomes the first above-mentioned problem of the known regulation circuit. According to the present invention, said object is attained by means of a negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device for regulating a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the memory device, comprising an operational amplifier with a first input coupled to a reference voltage, a second input coupled to said negative word line voltage and an output controlling a voltage regulation branch, connected between an external power supply and said negative word line voltage, to provide a regulation current for regulating said negative word line voltage, characterized in that said output of the operational amplifier also controls a voltage sensing branch, connected between said external power supply and said negative word line voltage, to provide a sensing signal coupled to said second input of the operational amplifier. Thanks to the fact that in the regulation circuit of the present invention the operational amplifier controls two distinct branches, the first one providing the regulation current necessary for regulating the word line negative voltage, the second one providing a sensing signal which is fed back to the input of the operational amplifier, the sensing signal provided by the second branch and fed back to the input of the operational amplifier is not affected by voltage drops due to the regulation current flowing in the first branch. These and other features and advantages of the present invention will be made more evident by the following detailed description of a particular embodiment, described as a non-limiting example in the annexed drawings, wherein: Figure 1 is a schematic circuit diagram of a negative word line voltage regulation circuit according to the present invention; Figure 2 is a detailed circuit diagram of a first circuit block of the circuit of Figure 1; Figure 3 is a detailed circuit diagram of a second circuit block of the circuit of Figure 1; Figure 4 is a detailed circuit diagram of a third circuit block of the circuit of Figure 1; Figures 5A to 5C are electrical equivalent circuit diagrams of the first circuit block, in three different operating conditions. In Figure 1 the reference numeral 1 is used to indicate a matrix 1 of memory cells of an electrically erasable semiconductor memory device, for example a Flash EEPROM. As known, the memory cells in the matrix 1 are arranged in rows (word lines) and columns (bit lines); each memory cell, represented by a floating-gate MOS transistor, has a control gate electrode connected to one respective word line. In Figure 1, the word lines are indicated with the reference numeral WL. The word lines WL are grouped together to form sectors S1-S8 of the memory matrix 1. All the word lines WL of a given sector S1-S8 are commonly coupled, via respective diode-connected P-channel MOSFETs 1, to a negative voltage output 01-08 of a negative charge pump NP1-NP8 associated to said sector S1-S8. A negative word line voltage regulation circuit according to the present invention comprises an operational amplifier 2 having a non-inverting input 3 connected to ground (GND) and an inverting input 4 connected to a central node 5 of a capacitive divider comprising a first capacitor C0 and a second capacitor C1. Preferably, capacitors C0 and C1 have plates respectively formed by the two polysilicon layers which also form the floating gates and the control gates of the memory cells, the dielectric of the capacitors being formed by the oxide layer which isolates the control gates from the floating gates. In this way, the capacitive values of capacitors C0, C1 do not depend on the voltage applied across them. An output 6 of the operational amplifier 2 drives a gate electrode of two N-channel MOSFETs 7 and 8 with drains connected to an external voltage supply VCC (typically the 5 V supply). The N-channel MOSFET 8 has a source electrode connected to a P-channel MOSFET 13 with gate tied to ground and drain connected to a diode-connected P-channel MOSFET 14. The drain electrode of MOSFET 14 is coupled to each one of the negative voltage outputs 01-08 through respective diode-connected P-channel MOSFETs 151-158. The N-channel MOSFET 7 has a source electrode connected to a P-channel MOSFET 9 with gate tied to ground and drain connected to a diode-connected P-channel MOSFET 10. The drain electrode of MOSFET 10 is coupled to each one of the negative voltage outputs 01-08 through respective diode-connected P-channel MOSFETs 121-128. The drain electrode of MOSFET 10, being further connected to a a node 11 to which a second plate of capacitor C1 is also connected, is coupled to the inverting input 5 of the operational amplifier 2. The MOSFETs 8, 13 and 14, together with the MOSFETs 151-158, form a plurality of voltage regulation branches, one for each of the negative voltage outputs 01-08 of the negative charge pumps NP1-NP8. The MOSFETs 7, 9 and 10, together with the MOSFETs 121-128, form a plurality of voltage sensing branches, one for each of the negative voltage outputs 01-08 of the pumps NP1-NP8. The MOSFETs 8, 13 and 14 have bigger dimensions than the MOSFETs 7, 9 and 10, so that the current IS flowing through the voltage sensing branches is always negligible with respect to the regulation current IR flowing through the voltage regulation branches. The regulation circuit also comprises a circuit 16 for biasing the capacitors C0, C1 of the capacitive divider, shown in detail in Figure 2. This circuit comprises a chain of four inverters IN1-IN4; the first three inverters IN1-IN3 are supplied with the external voltage supply VCC, while the fourth inverter IN4 is supplied with a fixed voltage V1, which is for example generated by a band-gap reference voltage generator schematically indicated with 17 in Figure 1. The first inverter IN1 receives a signal HVN which is activated by an internal control circuit 18 of the memory device when an electrical erasure must be performed; the output of the first inverter IN1, in addition of supplying the input of the second inverter IN2, controls a gate electrode of an N-channel MOSFET 19 connected between the central node 5 of the capacitive divider and ground. A capacitor C3 is connected between the output of the second inverter IN2 and ground to provide a delay between the transition of the output of IN1 and the transition of the input of IN4. An output of the fourth inverter IN4 is connected to a node 21 to which a second plate of capacitor C0 is also connected. The node 11 of capacitor C1 is connected to ground through a P-channel depletion MOSFET 20, whose gate electrode is controlled by a signal VDEP generated by the internal control circuit 18. A damping capacitor C4 is connected between the second plate 11 of capacitor C1 and ground, to prevent the voltage on the second plate 11 of C1 from oscillating. Figure 3 is a detailed circuit diagram of one of the negative charge pump blocks of Figure 1, for example NP1. The circuit comprises, in a per-se known way, a chain of diode-connected P-channel MOSFETs 22, 23 and 24. The first P-channel MOSFET of the chain, 22, has a drain electrode connected to ground through an N-channel MOSFET 25 whose gate electrode is controlled by an output of an AND gate 26 with a first input supplied with the signal HVN, and a second input supplied with a signal P10N. The signal HVN commonly supplies all the negative charge pumps NP1-NP8. The signal P10N is generated by the internal control circuit 18 and is one of a plurality (eight in this example) of signals P10N-P80N, each supplying a respective one of the negative charge pumps NP1-NP8 to selectively activate the respective negative charge pump NP1-NP8 when the respective sector S1-S8 must be erased. To turn a given negative charge pump on, both HVN and the respective selection signal P10N-P80N must be logic "1". A first capacitor C5 has one plate connected to the common node 27 of MOSFETs 22 and 23, and the other plate supplied with a first clock signal PHI1. A second capacitor C6 has one plate connected to the common node 28 between MOSFETs 23 and 24, and the other plate supplied with a second clock signal PHI2. The two clock signals PHI1 and PHI2 are generated by a clock generator 29. The source electrode of MOSFET 24 forms the output O1 of the negative charge pump NP1. The detailed circuit structure of the operational amplifier 2 is shown in Figure 4. As visible, the operational amplifier 2 substantially comprises in a per-se known way two stages, a first stage composed by two branches 30, 31 connected in a current mirror configuration and a second stage inverting the output of the first stage. The inputs of the operational amplifier 2 are P-channel MOSFETs, due to the choiche of using ground as the reference voltage for the amplifier. The working of the negative word line voltage regulation circuit described above works will be described hereinafter. When the memory device is not in the electrical erase mode, the signal HVN is a logic "0". In this condition, all the negative charge pumps NP1-NP8 are off, the output of the first inverter IN1 is a logic "1" and MOSFET 19 is on, so that the central node 5 of the capacitive divider is tied to ground. Also, the input of the fourth inverter IN4 is a logic "1", so that the second plate 21 of capacitor C0 is tied to ground. Furthermore, as long as HVN is a logic "0", the signal VDEP is approximately equal to -4 V, and the depletion MOSFET 20 is on, so that the second plate 11 of capacitor C1 is also tied to ground. This means that before an electrical erasure starts, the capacitors C0 and C1 of the capacitive divider are not charged. This situation is depicted in Figure 5A. When the memory cells of one or more of the sectors S0-S8 must be erased, the control circuit activates the signal HVN, as well as one or more of the signals P10N-P80N; the negative charge pumps associated to the sectors to be erased are thus turned on, and the voltage on their respective output nodes becomes progressively more negative. However, due to the rather high capacitive load seen by the negative charge pumps, the voltage on their output nodes changes rather slowly. In Figure 5B the situation at the beginning of the erase operation is depicted. Simultaneaously with the activation of HVN, VDEP takes an approximate value of 4 V, so that the depletion MOSFET 20 turns off. Also, the output of the first inverter IN1 goes to a logic "0", and MOSFET 19 turns off, thus leaving the node 5 floating; after a predetermined delay, fixed by capacitor C3, the input of inverter IN4 also goes to a logic "0", so that the second plate 21 of capacitor C0 is tied to the fixed reference voltage V1. The initial voltage V(5) on node 5 is given by: V(5) 0 =V1*C0/(C0+C') where C'=(C1+C4)/(C1*C4) , and the initial voltage on the second plate 11 of C1 is given by: V(11) 0 =V1*C''/(C4+C'') where C''=(C0+C1)/(C0*C1) . These are the voltage values on nodes 5 and 11 before the regulation circuit has stabilized. The value of the regulated negative voltage outputs after the regulation circuit has stabilized can be found noting that the voltage V(5) on node 5 is kept to ground (node 5 is a virtual ground); the voltage variation on node 11 necessary to bring V(5) to ground is: ΔV(11)=-V(5) 0 *(C0+C1)/C1 so that during regulation the voltage on node 11 is: V(11)=V(11) 0 +ΔV(11). It is to be noted that the value of the voltage on node 11 during regulation is a function of V1, C0, C1 and C4, but not of the external power supply VCC. If V1 is chosen to be 2 V, C0 2 pF, C1 0.5 pF and C4 4 pF, the following voltage values are obtained: V(5) 0 =1.63 V V(11) 0 =0.18 V ΔV(11)=-8.15 V V(11)=-7.97 V The regulation circuit keeps the negative voltage outputs of the negative charge pumps at a voltage value equal to V(11)+VTH, where VTH is the (negative) threshold voltage of the diode-connected P-channel MOSFETs 121-128. The regulated negative voltage V(WL) on the word lines WL is equal to: V(WL)=V(11)+VTH-VTH=V(11)=-7.97 V which is a suitable value to perform the electrical erasure of the memory cells. The regulation circuit of the present invention is designed to work in a linear way, differently from the regulation circuit according to the prior art which works in an "on-off" way. If the negative voltage outputs of the negative charge pumps become too negative, a regulation current IR flows through the voltage regulation branch to increase the load current of the negative charge pumps, so that the negative voltage outputs become less negative. The sensing current IS flowing in the voltage sensing branch is always negligible with respect to the regulation current IR: IS must only keep the diode-connected MOSFETs 10 and 121-128 biased. It is important to note that a significant problem of the regulation circuit according to the prior art is the progressive loss of charge of the capacitors of the capacitive divider due to leakage currents; this effect, related to the fact that the voltage on the central node of the capacitive divider is 2 V, introduces drifts in the voltage compared by the comparator with the reference voltage, and as a consequence also the regulated voltage drifts. In the regulation circuit of the present invention, thanks to the fact that the reference voltage for the operational amplifier is chosen to be the ground voltage, during regulation the central node 5 of the capacitive divider is kept to ground, and the effect of leakage currents on the charge of capacitors C0 and C1 is minimized.

Claims: Negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device for regulating a negative word line voltage (01-08) to be supplied to word lines (WL) of the memory device during an electrical erasure of the memory device, comprising an operational amplifier (2) with a first input (3) coupled to a reference voltage (GND), a second input (4) coupled to said negative word line voltage (01-08) and an output (6) controlling a voltage regulation branch (8,13,14,151-152), connected between an external power supply (VCC) and said negative word line voltage (01-08), to provide a regulation current (IR) for regulating said negative word line voltage (01-08), characterized in that said output (6) of the operational amplifier (2) also controls a voltage sensing branch (7,9,10,121-128), connected between said external power supply (VCC) and said negative word line voltage (01-08), to provide a sensing signal (11) coupled to said second input (4) of the operational amplifier (2). Negative word line voltage regulation circuit according to claim 1, characterized in that said regulation current (IR) flowing in the voltage regulation branch (8,13,14,151-152) is substantially higher than a sensing current (IS) flowing through the voltage sensing branch (7,9,10,121-128). Negative word line voltage regulation circuit according to claim 2, caracterized in that said first input (3) of the operational amplifier (2) is a non-inverting input, and in that said reference voltage is a ground voltage (GND). Negative word line voltage regulation circuit according to claim 3, characterized in that said first and second inputs (3,4) of the operational amplifier (2) are two gate electrodes of two respective P-channel MOSFETs. Negative word line voltage regulation circuit according to claim 4, characterized in that said sensing signal (11) is coupled to said second input (4) of the operational amplifier (2) through a capacitive divider (C0,C1) comprising a first capacitor (C0) and a second capacitor (C1) having respective first plates connected to a common node (5) which is connected to said second input (4) of the operational amplifier (2). Negative word line voltage regulation circuit according to claim 5, characterized in that said sensing signal (11) is connected to a second plate (11) of said second capacitor (C1) of the capacitive divider (C0,C1). Negative word line voltage regulation circuit according to claim 6, characterized in that it comprises a circuit (16) for biasing said capacitive divider (C0,C1), said biasing circuit (16) comprising first means (IN4), responsive to an enable signal (HVN) activated when an electrical erasure must be performed, to selectively connect a second plate (21) of the first capacitor (C0) to the ground or to a fixed voltage (V1) respectively when said enable signal (HVN) is activated or de-activated, second means (19), also responsive to said enable signal (HVN), for selectively connecting the common plate (5) of the first and second capacitors (C0,C1) to the ground (GND) or leaving said common plate (5) floating respectively when said enable signal (HVN) is de-activated or activated, and third means (20) for connecting the second plate (11) of the second capacitor (C1) to the ground when the enable signal (HVN) is de-activated. Negative word line voltage regulation circuit according to claim 7, characterized in that said first means (IN4) comprise an inverter (IN4) supplied with said fixed voltage (V1), said second means (19) comprise an N-channel MOSFET (19), and said third means (20) comprise a P-channel MOSFET (20) of the depletion type. Negative word line voltage regulation circuit according to claim 7, characterized in that said fixed voltage (V1) and said first and second capacitors (C0,C1) have respective values suitable to provide a negative word line voltage of approximately -8 V. Negative word line voltage regulation circuit according to anyone of the preceding claims, characterized in that said negative word line voltage (01-08) is generated by at least one negative charge pump (NP1-NP8) integrated in the memory device. Negative word line voltage regulation circuit according to anyone of the preceding claims, characterized in that said first and second capacitors (C0,C1) have plates respectively formed by a first and a second polysilicon layers also forming floating gates and control gates of the memory cells, respectively, and a dielectric formed by an oxide layer also insulating the control gates of the memory cells from the floating gates.

Inventors: CARRERA MARCELLO, SALI MAURO, VILLA CORRADO, CARRERA, MARCELLO, SALI, MAURO, VILLA, CORRADO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: G11C16
IPC codes: G11C17, G11C16