System and method for processing commands without polling of the hardware by the software

Abstract: A CPU introduces software commands to a first limited capacity memory (e.g. FIFO), on an integrated circuit chip. Data (e.g. graphics) from a first portion of a second memory (off chip) is processed in accordance with such commands. A second portion (e.g. FIFO) of the second memory may also store commands normally passing from the CPU through the first memory. When the first memory becomes full, the commands may pass from the CPU through the second portion of the second memory (which may have a storage capacity considerably greater than that of the first memory) and then through the first memory. The commands may continue to flow in this auxiliary path until the second portion of the second memory becomes empty. A third memory of a limited capacity on the chip may pass the commands from the CPU to the first memory in the normal operation or to the second portion of the second memory when the first memory becomes full. The CPU may also pass commands to other peripheral equipment while a ready line is high. When low, the ready line prevents commands from passing to the peripheral equipment while the third memory is full. However, a command may pass from the third memory to the first or second memory to make the ready line high. A counter indicates the number of commands in the first and third memories and the second portion of the second memory. Software occasionally interrogates the counter to update in the software the number of commands in the counter.

Description: This invention relates to systems for, and methods of processing data in accordance with commands from a central processing unit. More particularly, the invention relates to systems for, and methods of, minimizing the delays provided by software in processing commands, thereby increasing the rate at which data is processed in accordance with such commands. Architectures presently used for processing graphics information in environments incorporating personal computers typically consist of three (3) layers of software, the last of which communicates with the image rasterization hardware. The three (3) layers of software may be respectively designated as (1) application software, (2) graphics device interface (GDI) software and (3) device driver (DD) software. These three (3) layers of software are schematically illustrated in Figure 1 of the drawings. The application software is written to accomplish a specific task. An output of the application software may be an image. For example, the application software may provide three (3) vertices to define a triangle. The CPU may process several different applications at the same time. For example, one application may output the vertices of a triangle while another outputs the vertices of a rectangle, both of which are to be displayed simultaneously in different display "windows" of a video monitor. These different display windows may be separated or overlapping on the screen. The applications software is written to provide the standard inputs to the graphics device interface software for such operations as the drawing and color filling of polygons. This is designated as "polygon fill". The graphics device interface (GDI) software illustratively manages any overlap between the images simultaneously developed in different windows by different software applications such as the triangle and rectangle specified above. For example, the graphics device interface software may clip a part of the triangle or the rectangle when such portions are overlapped by another window. The GDI software passes the clipped polygons to the next level of software, the device driver. The device driver software (the third software layer) performs several operations on the clipped polygons. For example, in the example in the previous paragraph, the device driver software performs operations on the clipped portions of the triangle and the rectangle. These operations include the steps of breaking each clipped polygon into separate simplified blocks or image lines. These blocks or image lines are to be written into a random access memory (RAM) which stores the image for display on the video monitor. For example, the device driver software indicates the beginning and end of each horizontal line in each polygon and also indicates the color of the line. The device driver software accordingly provides three (3) words (the beginning position of the line, the end position of the line and the individual color between such beginning and end) to define such line. It may be that the polygon to be rasterized is a vertical line with a width of a few pixels. The device driver software takes account of this by drawing several horizontal lines, each a few pixels long. In another example, a line of an individual color may be slanted at an angle, not 90°, relative to the horizontal lines in the raster scan. This may require each horizontal line drawn to be more than a few pixels, the specific number of pixels depending upon the angle relative to the horizontal. As will be seen from the discussion above, the device driver software may be relatively complicated. Furthermore, the three (3) layers of software are closely linked in the passage of commands from each layer to the next. For example, the application software has to wait for the graphics user interface to complete the execution of its clipped polygon commands; and the graphics user interface software has to wait for the device driver software to complete the execution of its line fill commands. When the device driver software has completed its commands, it returns control to the applications software for the applications software to provide the commands for the next polygon. Unfortunately, the communication between the device driver software and the image rasterization hardware is not as efficient as the communication between the three (3) layers of software. The inefficiency results in part because of the way in which the device driver software communicates with the hardware to determine if the hardware has completed the execution of the last command specified by the device driver software. This communication process is designated as "polling". An average of ten (10) to fifteen CPU clock cycles is required after the completion of the execution of the last command from the device driver software for the CPU to recognize that the operation is complete. If the CPU has a clock frequency of thirty three megahertz (33 Mhz), this time may constitute approximately four hundred and fifty nanoseconds (450 ns). During this time, no other graphics software commands may be executed. Another problem exists between the software and the hardware in the systems now in use. A line exists between the CPU memory and the hardware on the local bus to discontinue the transfer of data from the CPU to the bus. This line is designated as the "CPU ready line". When the voltage on the CPU ready line is forced low, the CPU is not able to transfer commands to any devices on the bus. It is not permissible in the systems now in use for any device on the bus to lower the voltage on the CPU ready line for more than a specified period of time such as a few microseconds. One reason is that the CPU would be unable to properly service hard disk data transfer requests if the CPU ready line is low for more than this period of time. Since the execution of a single device driver graphics command by the hardware may require a time period greater than a few microseconds, the CPU ready line is not suitable for providing a fast arbitration of the flow of graphics commands between the CPU memory and the hardware. Although the communication time between the software and the hardware is relatively slow, the command execution within the image rasterization hardware is relatively fast. For example, when the hardware communicates with the random access display memory, the recording of a line of ten (10) pixels in the random access memory requires one (1) random DRAM cycle to set the address for the first pixel and then a single additional page mode cycle to record each additional pixel. The random clock cycle may require two clock cycles for address initialization and one clock cycle for pixel data write. If the clock in the hardware has a frequency of twenty five megahertz (25 Mhz), each clock cycle may require forty (40) nanoseconds (40ns.). Thus, the total transfer time for recording ten (10) pixels in a horizontal line into a random access memory is approximately 80+10(40) = 480 nanoseconds. Line fill for a vertical line requires considerably more time than that specified in the previous paragraph. In such a case, a random cycle write time of one hundred and twenty nanoseconds (120 ns.) is required for each pixel. Thus the total time for recording the ten (10) pixels in the vertical line would be approximately twelve hundred nanoseconds (80+40)(10) = (1200 ns.). Thus, the average time for recording the ten (10) pixels, whether horizontal or vertical, is approximately slightly more than eight hundred nanoseconds. By comparing the average time of approximately eight hundred nanoseconds (800 ns.) in the hardware for recording a horizontal or vertical line of ten (10) pixels and a polling time of approximately four hundred and fifty nanoseconds (450 ns.), it will be seen that the polling time represents significantly more than half of the total time required to record the ten (10) pixels in the average line. This further slows the operation of the system. The computer graphics industry spends millions of dollars annually in improving the speed at which graphics information is processed in hardware. The speed of processing the graphics information in hardware has accordingly been accelerated considerably. The computer industry would also like to shorten the time for processing the graphics information in software. This may be seen from the discussion above. The computer industry would particularly like to shorte, if not completely eliminate, the time for the poliing of the hardware by the software. This problem has been known to exist for a considerable number of years but no one has to be able to provide a satisfactory resolution of the problem. A prior art (WO 93/04462) computer graphics system dealing with the above-mentioned problems comprising a system bus, a FIFO command buffer in main memory for temporary storage of graphics commands, a residue buffer for the temporary storage of memory transmissions not immediately usable by the graphics processor and a "short circuit" feature for routing graphics commands to the command processor in a minimum number of steps. In this prior art the FIFO command buffer is not allowed to get full since an "almost full" function causes a FIFO control unit controller to inhibit further transmissions to the command buffer. The control unit controller then issues an interrupt to a CPU to suspend the transmitting of graphics commands. When the length of the FIFO command buffer has reached a programmable "almost empty" value, a FIFO command full/empty comparator signals the FIFO control unit controller to resume the transmission of graphics commands. This allows the prior art system to be programmed with an "almost full" and "almost empty" value, that will then issue interrupts to hold or to restore the full transmission of graphics commands via the system bus. It is the object of the invention to provide a system and a method for the transfer of commands from software to hardware and the processing of such commands in the hardware with infrequent polling of the hardware by the software to determine if the hardware has processed such commands. This object is solved by the features as claimed in claims 1 and 10. In compliance with the invention the first determining means determines the number of commands in the second FIFO shift register and the second determining means determines the number of commands in the third FIFO shift register. The first and second determining means provide feedback for the command providing means to control the rate at which data is provided. While the prior art implements an on/off mechanism for graphics commands, the present invention provides a set of numbers which may be read by the command providing means in order to modulate the flow of graphics data into the first FIFO shift register. By providing the command providing means with numbers representing the loading state of the second FIFO shift register and the third FIFO shift register, the system of the invention provides for means of controlling the flow of graphics commands into the first FIFO shift register in other ways besides the strictly digital means of a "turn on" command when the second FIFO shift register is almost full and a "turn off' command when the second FIFO shift register is almost empty as provided by the prior art. This allows the processor to control the flow of commands under program control, and thereby adjust the rate of providing commands, not merely turn the flow of commands on and off. Further developments of the invention are claimed in the sub-claims. This invention provides a system for satisfactorily eliminating the requirement for the polling of the hardware by the software after each command to determine if the hardware has completed that command. The invention provides an integrated circuit chip system which enables a large number of commands to be transmitted in succession (a packet of commands) before any polling of the hardware my be required. The system includes memories on the chip of a limited capacity for processing the commands and for providing for the processing of data (e.g. graphics) for output to a display memory in accordance with such commands. An auxiliary memory portion is provided in the display memory in the system of this invention for receiving overflows of commands not capable of being stored in the memory on the chip. By providing this arrangement, the commands continue to pass in a steady stream, preferably in packet form, from the device driver software to the hardware without polling from the software after each such command. In one embodiment of the invention, a central processing unit (CPU) introduces software commands to a first memory (e.g. FIFO), of a limited capacity, on an integrated circuit chip. Data (e.g. graphics) from a first portion of a second memory (off chip) is processed in accordance with such commands. A second portion (e.g. FIFO) of the second memory may also store commands normally passing from the CPU through the first memory. When the first memory becomes full, the commands may pass from the CPU through the second portion of the second memory (which may have a storage capacity considerably greater than that of the first memory) and then through the first memory. The commands may continue to flow in this auxiliary path until the second portion of the second memory becomes empty. A third memory of a limited capacity on the chip may pass the commands from the CPU to the first memory in a normal operation or to the second portion of the second memory when the first memory becomes full. The CPU may also pass commands to other peripheral equipment while a ready line is high. When low, the ready line prevents commands from passing to the peripheral equipment while the third memory is full. However, a command may pass from the third memory to the first or second memory to make the ready line high. A counter indicates the number of commands in the first and third memories and the second portion of the second memory. Software occasionally interrogates the counter to update in the software the number of commands in the counter. In the drawings: Figure 1 illustrates a general arrangement of software and hardware in a system of this invention; Figure 2a is a simplified block diagram of a system constituting one embodiment of the invention and employing a local bus for providing commands from a central processing unit (CPU) to hardware including a graphics user interface and a display memory and for processing data (e.g. graphics) in the display memory in accordance with such commands; Figure 2b is a simplified block diagram of a system constituting another embodiment of the invention and employing a peripheral bus for providing commands from a central processing unit (CPU) to hardware including a graphics user interface and a display memory and for processing data (e.g. graphics) in the display memory in accordance with such commands; Figure 2c is a simplified block diagram of a system constituting a third embodiment of the invention and employing a high speed bus common to all of the hardware for providing commands from a central processing unit (CPU) to hardware, including a graphics user interface and a high speed random access shared main memory, for processing data (e.g. graphics) in the main memory in accordance with such commands; Figures 3a(1) and 3a(2) are somewhat detailed schematic system diagrams, partially in block form, of a portion, including the graphics user interface and the display memory, of the system shown in Figure 2a when the display memory is a video random access memory (VRAM); Figures 3b(1) and 3b(2) are somewhat detailed schematic system diagrams, partially in block form, of a portion, including the graphics user interface and the display memory, of the system shown in Figure 2a when the display memory is a synchronous dynamic random access memory (dRAM); Figures 3c(1) and 3c(2) are somewhat detailed schematic system diagrams, partially in block form, of a portion, including the graphics user interface and the display memory, of the system shown in Figure 2c when the display memory is a high speed random shared main memory; Figures 4a(1) and 4a(2) are somewhat detailed system diagrams similar to that shown in Figure 3a(1) and 3a(2) but show, on more of an actual basis than that shown in Figures 3a(1) and 3a(2), the passage of commands, addresses and data between the graphics user interface and the display memory; and Figures 4b(1) and 4b(2) are somewhat detailed system diagrams similar to that shown in Figures 3b(1) and 3b(2) but show, on more of an actual basis than that shown in Figure 3b(1) and 3b(2), the passage of commands, addresses and data between the graphics user interface and the display memory. Figure 1 is a simplified block diagram of three (3) layers of application software and the graphics hardware associated with the software. The three (3) layers of software are designated in individual blocks as (1) application ("Appl") software, (2) graphics device interface ("GDI") software and (3) device driver ("DD") software. The graphics hardware is respectively designated in individual blocks as (1) graphics user interface ("GUI") or graphics accelerator and (2) random access memory (RAM) or display memory. The distinction between the software and the hardware is designated in Figure 1 by a horizontal line and by the word "SOFTWARE" and a line with an upwardly pointing arrow above the horizontal line and by the word "HARDWARE" and a line in the downwardly pointing arrow below the horizontal line. When the images are to be displayed on a video monitor, the application software provides vertices defining the outlines of images. For example, when a triangle is to be displayed on the video monitor, the application software provides the three (3) vertices defining the boundaries of the triangle. Similarly, the application software defines a parallelogram by four (4) vertices. Sometimes, more than one (1) image window can be provided simultaneously by a single software application. In other cases, more than one software application may be provided in the CPU on a time-shared basis. Each application may be outputting graphics data in a separate "window" on the video display. For example, each of the triangle and the parallelogram may be provided in a separate window by the application software. Application software such as described above is well known in the art. The graphics device interface in Figure 1 acts upon the polygon vertices provided by the application software. The graphics device interface clips the polygons in accordance with the window superposition to be provided for the images. If the polygon is clipped by a superimposed window, the graphics device interface cuts off the portion of the polygon overlapped by that window. Graphics device interface software such as described above is well known in the prior art. The device driver software in Figure 1 acts upon the clipped polygons provided by the graphics device interface software. The device driver software breaks the clipped polygons into lines or rectangles and then transmits the resulting line fill commands or rectangle fill commands to the graphics user interface (GUI) hardware. Device driver software such as described in this paragraph are well known in the prior art. Figure 1 also shows hardware identified in block form as a graphics user interface (GUI) and also identified as a graphics accelerator. GUI hardware is generally known in the prior art but the GUI hardware individual to the system of this invention is not known in the prior art. The GUI hardware shown in Figure 1 processes the commands from the device driver software in a manner unique to the system of this invention. The hardware shown in Figure 1 also includes a random access memory (RAM) or display memory. Random access memories or display memories are well known in the art. The random access memory or display memory in the system of this invention may be considered to be constructed in a manner similar to the random access memory or display memory of the prior art but the use provided by a portion of this memory is unique to the system of this invention. In that sense, the random access memory or display memory of this invention is different from the random access memories or display memories of the prior art. The system of this invention is advantageous in that the device driver software provides commands to the GUI hardware and does not have to poll the GUI hardware after each command to determine whether or when the GUI hardware has completed the processing of such command. This is indicated by a line between the device driver software and the GUI hardware with an arrow pointing toward the GUI hardware. However, after the transmission of a packet of commands, the device driver software may poll the GUI hardware to determine the space available in the graphics command storage portion of the display memory. Since this polling is infrequent, this is indicated by a broken line between the device driver software and the GUI hardware with an arrow pointing toward the device driver software. A line with arrows extending in opposite directions is disposed between the GUI hardware and the display memory to indicate that the GUI hardware and the display memory communicate with each other. Figure 2a is a simplified block diagram of one embodiment, generally indicated at 10, of a system constituting this invention for providing for an operation of hardware on the commands from the software without any polling by the software after the performance of each and every command. The system 10 includes a central processing unit (CPU) 12 which communicates over a host bus 14. The data portion of the host bus 14 is preferably thirty two (32) bits wide to accommodate the graphics command words, but it may provide any other number of bits, more or less than thirty two (32). The host bus 14 may also be considered as a local bus in its connection to the CPU 12 and to a graphics user interface generally indicated at 18. A CPU main memory 16 is also connected to the host bus 14. The CPU main memory 16 may constitute a dynamic random access memory (dRAM) for storing the software commands. A peripheral bus control 20 may also be coupled to the host bus 14. The peripheral bus control 20 may in turn be connected to a peripheral interface indicated at 22. The peripheral interface 22 is in turn coupled to peripheral equipment 23. An example of such peripheral equipment is a printer. The peripheral bus control 20, the peripheral interface 22 and the peripheral equipment 23 are well known in the prior art. A video random access memory (VRAM) generally indicated at 24 is connected to the graphics user interface 18. The memory 24 may include at least three (3) different portions. One portion may constitute a frame buffer memory 26 for storing graphics information in digital form. Another portion may constitute a video input memory 28 for storing video information in digital form. A third portion may constitute a GUI FIFO memory 30 for storing graphics commands. The GUI FIFO memory 30 receives the commands from the GUI interface 18 and passes the commands, after a delay, from the memory 30 in the same order as received. The provision of the GUI FIFO memory 30 in the display memory 24 with digital data such as graphics and video is considered to be unique to this invention. A system for, and a method of, processing graphics and video information recorded in a common memory such as the memory 24 is disclosed and claimed in application No. US-A-5 406 306 filed on February 5, 1993, in the names of Jonathan I. Siann, Conrad M. Coffey and Jeffrey L. Easley for a "System For, and Method of, Displaying Information from a Graphics Memory and a Video Memory on a Display Monitor", this application being assigned of record to the assignee of record of this application. A system for, and a method of, processing graphics and video information recorded in a common memory such as the memory 24 is also disclosed and claimed in application No. US-A-5 640 332 filed on March 16, 1994, by David C. Baker and Jonathan I. Siann for a "Multimedia Graphics System", this application also being assigned of record to the assignee of record of this application. The CPU 12 stores the data and program software for operating the system 10. The resultant graphics commands from the CPU 12 are introduced to the host bus 14. Other commands in the CPU 12 are introduced through the peripheral bus control 20 to the peripheral interface 22. The peripheral interface 22 operates upon such data in accordance with the commands from the CPU main memory 16. For example, the interface may include input-output (I/O) buffers for communicating with the peripheral equipment 23 such as a line printer. Such a printer may print a page outputting the rasterization of the graphics data in the frame buffer memory 26 in accordance with the commands from the CPU 12. The commands and the data from the CPU 12 are introduced to the graphics user interface (GUI) 18 which is considered to be unique to this invention. The graphics user interface 18 includes a GUI command input memory 32 and a GUI command output memory 33 which normally receive the commands from the CPU 12 and which process the digital data from the frame buffer memory 26 (representing graphics) in accordance with such commands. The memories 32 and 33 may constitute shift registers which receive the commands at one end and pass the commands from the other end, after a delay, in the same order as when received. Thus, the memories 32 and 33 may constitute FIFO's. Each of the memories 32 and 33 in the graphics user interface 18 has a limited capacity. In the normal operation, the input memory 32 receives the commands from the CPU 12 through the host bus 14 and passes the commands to the memory 32. The output memory 33 then passes the commands to image rasterization circuitry in the graphics user interface (GUI) 16. This circuitry processes the graphics commands from the CPU 12 and outputs pixel data as a result of such processing. Such pixel data may digitally represent an image. This digital data may be converted to analog data which may then be converted to pixel intensities of the resultant image for display on a video monitor. Since the output memory 33 in the graphics user interface 18 has a limited capacity, it may occasionally become full. When the memory 33 becomes full, the graphics user interface 18 operates to provide for the passage of the commands from the input memory 32 through the GUI FIFO memory 30 in the video random access memory (VRAM) 24 and then through the output memory 33. The GUI FIFO memory 30 accordingly functions as an auxiliary memory for receiving the commands which would otherwise overflow the memory 33. When the GUI FIFO memory 30 receives the commands which would otherwise overflow the memory 33, it continues to operate in this capacity until there are no commands in the GUI FIFO memory 30. Upon such an occurrence, the commands pass again from the input memory 32 directly to the output memory 33 and then outwardly from the memory 33 to the image rasterization circuitry in the graphics user interface 18. By providing the interrelationship between the memories 32 and 33 in the graphics user interface 18 and the GUI FIFO memory 30 in the display memory 24 as discussed above, the system shown in Figure 2a eliminates any polling of the graphics user interface after each command except under isolated circumstances which will be described in detail subsequently. This polling is provided in the prior art to determine if the graphics user interface of the prior art has completed the processing of data at each vertex in accordance with each command. By eliminating such polling, the system of this invention provides a considerable enhancement in the rate at which data may be processed. Since the polling of each vertex requires approximately four hundred and eighty nanoseconds (480 ns) and since there are a plurality of vertices in the performance of commands, the virtual elimination of polling as in this invention represents a considerable savings in time. The graphics image data stored in the frame buffer memory 26 passes in one embodiment from the frame buffer memory through a bus 36 to stages including a random access memory and a digital-to-analog converter for a conversion from digital values to corresponding analog values. These stages are often designated as "RAMDAC" stages (constituting the first initials of "random access memory" and "digital analog converter"). The "RAMDAC" stages are well known in the art. In such an embodiment, the data usually is passed in packets through the bus 36 in synchronism with the pixel clock of the video display. Figure 2b shows the same blocks as shown in Figure 2a but in a different interrelationship than that shown in Figure 2a. The arrangement of the blocks shown in Figure 2b is generally indicated at 40 and is provided for use with a bus designated in the trade as the "PCI" bus and indicated at 42 in Figure 2b. Figure 2b may be considered to be a preferred embodiment since it incorporates the "PCI" bus 42 which is considered to be the host bus of the future. One reason for this architecture is that it may be desirable in future applications to operate the local bus 44 with words in excess of thirty two (32) bits. For example, the local bus 44 may be operated with words of one hundred and twenty eight (128) bits to attain higher main-memory bandwidths. In the embodiment shown in Figure 2b, the stages are identified by the same numerals as the stages shown in Figure 2a except that the stages are further designated by the suffix "b". For example, the central processing unit (CPU) is designated as 12b. The CPU 12b, the CPU main memory 16b and the input of the peripheral bus control 20b are connected to a CPU local bus 44. Connections are made to the peripheral bus 42 from the output of the peripheral bus control 20b, the peripheral I/O interface 22b and the input to the graphics user interface 18. The output of the graphics user interface 18b and the input to the video random access memory (VRAM) 24b share a common bus 46. The graphics data from the video random access memory 24b passes through the line 36b to the equipment designated as "RAMDAC" in a manner similar to that provided for the graphics data in the embodiment shown in Figure 2a. The system shown in Figure 2b operates essentially the same as the system shown in Figure 2a except that the peripheral bus control 20b is disposed between the local bus 44 and the graphics user interface 18b. Because of this substantially common functionality, the system shown in Figure 2b operates in a manner similar to that of Figure 2a to preclude polling (except under rare circumstances) of the graphics user interface 18b by the device driver software in Figure 1 after each graphics command. Figure 2c is intended to operate in a system with a high-speed random-access-memory bus designated as "Rambus". The "Rambus" system is well known in the art. For example, International application PCT/US 91/02590 published on October 31, 1991, discloses such a system. The system shown in Figure 2c has the same blocks as the systems shown in Figures 2a and 2b but has a different arrangement of such blocks than the arrangements shown in Figures 2a and 2b. These blocks are identified in Figure 2c with the same numerals as the blocks in Figures 2a and 2b but with the suffix "c". The system shown in Figure 2c is generally indicated at 50. In the embodiment shown in Figure 2c, a local bus 52 is connected between the CPU 12c and the high speed peripheral bus control 20c. All of the other stages in the system 50 and the high speed peripheral bus control 20c are connected to a high speed bus 54 (designated as "RAMBUS"). Thus, all of the communication between the different stages (other than the CPU 12c) occurs through the high speed bus 54. Since essentially all of the communications occur through the high speed bus 54, the communications can occur at a faster rate than in the systems shown in Figures 2a and 2b. Furthermore, in Figure 2c, the RACDAC is shown as a single block 56 and the output (constituting analog pixel data) is shown as passing on a line 36c to a video monitor. As will be appreciated, however, the embodiment shown in Figure 2c has substantially the same advantages as the embodiments shown in Figure 2a and 2b. For example, the embodiment shown in Figure 2c processes graphics data in accordance with successive commands without requiring the device driver software (except under rare exceptions) to poll the hardware as to whether the hardware has completed the processing of data in accordance with each command before processing data in accordance with the next command. The embodiments shown in Figures 2a and 2b include a video random access memory (VRAM) 24. A video random access memory 24 has certain advantages because it operates at a relatively high serial output clock speed and because it includes a serial output register for shifting out digital data taken from different positions in the frame buffer memory. However, other types of memories can be used without departing from the scope of the invention. These include a high speed dynamic random access memory (dRAM) such as illustrated in Figure 2c and a synchronous dynamic random access memory. Actually, the embodiment shown in Figure 3b and discussed in some detail subsequently incorporates a synchronous dRAM. Figure 3a (broken into two (2) parts as Figure 3a(1) and 3a(2)) shows schematically in additional detail, but still in block form, the graphics user interface 18 and the video random access memory or display memory 24 also shown in Figure 2a. The graphics user interface (GUI) 18 is preferably disposed on an integrated circuit chip which is shown in Figure 3a in broken lines as a rectangle 60. The video random access memory 24 is shown in broken lines as a separate rectangle and is separate from the chip 60. The interrelationship between the graphics user interface 18 and the video random access memory 24 is indicated schematically at the left end of Figure 3a by a horizontal line 62. This interrelationship is further indicated by a designation above the line 62 of "on chip" adjacent a vertical line with an upwardly pointing arrow. It is also indicated by a designation below the line 62 of "off chip" adjacent a vertical line with a downwardly pointing arrow. The host bus is the local bus 14 (also shown in Figure 2a) which is connected to a host bus interface and FIFO 62 on the chip 60. The FIFO 62 may have a limited capacity such as four (4) words. This FIFO corresponds to a GUI command input memory 32 in Figure 2a. The number of bits in each word in the FIFO 62 may correspond to the data width (32) of the bus 14. The input data from the host bus to the FIFO 62 may be loaded by a clock signal on a line 64 extending from a host bus interface FIFO controller 66 which is disposed on the chip 60. This input clock may have a frequency such as twenty five megahertz (25 Mhz) corresponding to the frequency in the CPU 12 in Figure 2a. Addresses controlling the operation of the chip 60 may be provided on the address portion 63 of the host bus from the CPU 12 to the host bus interface FIFO controller 66. These addresses may constitute twenty four (24) bits, this being the number of bits provided in each address by the CPU. A CPU ready line 65 is connected (the connection not being shown in Figure 3a) from the controller 66 to the CPU 12 to halt the transmission of commands by the CPU over the host bus when the host bus FIFO 62 is full. A clock signal on a line 68 from the controller 66 causes the host bus FIFO 62 to shift out new data. This clock signal may have a suitable frequency such as approximately fifty megahertz (50 Mhz). The host bus interface and FIFO 62 may also receive data through a bus 69 from an up/down counter 70 disposed on the chip 60. The data on the bus 69 provides an indication of the total storage depth available in the off chip GUI FIFO memory 30, the host bus and interface FIFO 62 and an on chip GUI hardware FIFO 98. This data may be used by the device driver software to determine when graphics command transmission should be halted. The output of the host bus interface and FIFO 62 is introduced to a movable arm in a switch 72 which is shown schematically as having a single-pole double-throw construction. Actually, the number of poles corresponds to the width of the bus (32-wide). The switch 72 is shown as being included in a stage 74 disposed on the chip 60 and designated as a "bus switch bypass path". A single-pole double-throw switch 76 corresponding to the switch 72 is also included in the bus switch bypass path 74. Although the switches 72 and 76 are shown as mechanical switches for purposes of illustration, it will be appreciated that the switches will preferably constitute multi-pole electronic switches such as formed from transistors disposed on the integrated circuit chip 60. The upper stationary contacts (the upper contacts) of the switches 72 and 76 are common as by a connecting line 78. The other stationary contacts (the lower contacts) of the switches 72 and 76 are respectively connected through lines 73 and 75 to the input and output ends of the off chip GUI FIFO memory 30 (also shown in Figure 2a) in the display memory 24. Commands are written through the bus 73 into the input of the GUI FIFO memory 30 and are read through the bus 75 from the output of the GUI FIFO memory. The commands may pass to and from the off chip GUI FIFO 30 (also shown in Figure 2a) at a suitable frequency such as approximately twenty five megahertz (25 Mhz). This is less than the frequency at which the commands may be clocked out of the FIFO 62. However, the commands can pass through the FIFO 30 at a frequency up to or equal to the output frequency of the FIFO 62 without departing from the scope of the invention. The operation of the switches 72 and 76 is shown in Figure 3a(1) as being controlled by inputs through a line 81 (designated as "bus switch control") to the movable arms of the switches from a GUI FIFO controller 82 (Figure 3a(2)) which is disposed on the chip 60. The controller 82 receives inputs designated as "new output" on a line 84 from the host bus interface FIFO controller 66 and requests new data outputs from the FIFO on the "new data request" line 86 to the controller 66. The up/down counter 70 in Figure 3a(1) has several connections to the GUI FIFO controller 82 in Figure 3a(2). For example, clock signals at a suitable frequency such as approximately fifty megahertz (50 Mhz) pass on a line 88 from the controller 82 to the counter 70. The clock signals cause the up/down counter 70 to count up or down by one count in accordance with the logic level of a "U/D" or up/down control line 90. The actual count in the counter 70 is monitored through a bus 92 to the controller 82. The counter 70 indicates the number of the commands in the off chip GUI FIFO 30. The same count may also be used to determine the available storage space remaining in the off chip FIFO 30. This information is provided to the host bus interface 62 over the line 69 in Figure 3a(1). Similar connections are made between the GUI FIFO controller 82 (Figure 3a(2)) and an up/down counter 96. The up/down counter 96 indicates the number of commands in the GUI hardware FIFO 98 which is disposed on the chip 60. One of the connections between the GUI FIFO controller 82 and the up/down counter 96 is through a line 100 which introduces clock signals at a suitable frequency such as fifty megahertz (50 Mhz) from the controller 82 to the counter 96. The clock signals cause the up/down counter to count up or down one by count in accordance with the logic level of the "U/D" or up/down control line 102. A third one of these connections is through a bus 104 to provide an indication to the controller 82 of the number of commands stored in the on chip GUI hardware FIFO 98. The on chip GUI hardware FIFO 98 stores a limited number of commands. For example, the FIFO 98 may have a capacity of eight (8) commands. Eight (8) is a desirable number because it constitutes the number of words in a BLIT command. A BLIT generally defines the corners of two superimposed rectangles as produced by the graphics device interface software in Figure 1. The FIFO 98 receives the commands on the movable arm of the switch 76 (Figure 3a(1)) through a bus 106. The FIFO 98 passes the commands through a bus 108 to an on chip graphics engine 110 (Figure 3a(2)) on the chip 60. These commands may pass through the bus 108 at a suitable frequency such as approximately fifty megahertz (50 Mhz). The on chip graphics engine 110 shown in Figure 3a(2) rasterizes the graphics commands and provides pixel data through a bus 112 to the frame buffer memory 26 also shown in Figure 2a. This pixel data is written into the frame buffer memory 26. The video output data from the frame buffer memory 26 is introduced to the bus 36 also shown in Figure 2a. This output may be provided on a serial basis at a suitable frequency such as approximately sixty six megahertz (66 Mhz). Multiple VRAM chips can be used to provide the wide-bus serial output at a frequency as high as sixty six megahertz (66 Mhz). The on chip graphics engine 110 also provides addresses through a line 118 to a RAM controller 114 disposed on the chip 60. The RAM controller 114 provides on a bus 116 signals controlling the addresses for the read and write operations in the frame buffer 26. The RAM controller 114 also provides arbitration for similar address control signals passing through a bus 119 from the GUI FIFO controller 82. The commands from the CPU 12 in Figure 2a pass through the host bus 14 to the host-bus interface and FIFO 62. In the normal operation of the system shown in Figures 3a(1) and 3a(2), the commands then pass through the command input FIFO 62 and through the switches 72 and 76 (in the upper positions of the movable arms of the switches) and through the bus 106 to the command output FIFO 98 (Figure 3a(2). After a delay for the passage of the commands through it, the output FIFO 98 then passes the commands through the bus 108 to the on-chip graphics engine 110. These commands control the operation of the graphics engine 110 in rasterizing the graphics data for output to the frame buffer 26. The resultant pixel data is introduced to the frame buffer 26 for recording the video image in the frame buffer. The writing of the pixel data into the frame buffer 26 is controlled by addresses introduced from the graphics engine 110 through the memory address bus 118 to the RAM controller 114. The RAM controller 114 arbitrates the writing of the pixel data from the graphics engine 110 at image positions in the frame buffer 26 and writes the command FIFO information in the off chip GUI FIFO memory 30 in accordance with addresses provided by the GUI FIFO controller 82. The counter 96 indicates at each instant the number of commands in the FIFO 98 and provides this indication on the bus 92. It may sometimes happen that the GUI hardware FIFO 98 may become full. Under such circumstances, the next command from the input FIFO 62 (Figure 3a(1)) cannot pass into the output FIFO 98. When this occurs, the GUI FIFO controller 82 (Figure 3a(2)) introduces a signal through the line 81 to the switches 72 and 76 (Figure 3a(1)) to trigger the movable arms of the switches from engagement with the upper stationary contacts into engagement with the lower stationary contacts. This causes the commands to pass from the input FIFO 62 through the switch 72 into the off chip GUI FIFO memory 30 in the display memory 24. These commands control the processing of data in the graphics data as described above. The off chip GUI FIFO memory 30 may have a storage capacity which is adjustable in accordance with the desires or needs of the user. For example, the memory 30 may store a number of words through an adjustable range between approximately five hundred and twelve (512) words and approximately sixty four thousand (64,000) words. In selecting the number of words for the FIFO 30, the user has to balance equities. If the user provides a relatively small storage capacity for the FIFO 30, he maximizes the storage capacity of the graphics frame buffer memory 26 and the video input memory 28 both of which share the total VRAM storage capacity as shown in Figure 2(a). However, the user increases the possibility that the FIFO 30 will quickly become full. This is undesirable because there will be no place for additional commands from the FIFO 62 to be stored. On the other hand, if the user increases the storage capacity of the FIFO 30, the FIFO will not become full easily but the space available for the buffer memory 26 and the video input memory 28 will be reduced. The provision of the FIFO's 62 and 98 on the chip 18 offers certain advantages. This results from the fact that the FIFO's 62 and 98 operate at a faster rate, because they are on the chip 18, than the off chip GUI FIFO memory 30. Because of this, the hardware and software in this invention operate to provide the commands in the FIFO's 62 and 98 on the chip 18 as much as possible. When the FIFO 30 is inserted into the command loop between the input FIFO 62 and the output FIFO 98, it serves as an auxiliary memory to store commands. The FIFO 30 continues to operate as an auxiliary storage until there are no commands remaining in the FIFO. At such a time, the count in the counter 70 (which indicates the number of commands in the FIFO 30 at each instant) indicates a count of zero. This causes the GUI FIFO controller 82 (which receives the count indication from the counter 70) to actuate the movable arms of the switches 72 and 76 into engagement with the upper stationary contacts of the switch. The FIFO 62 and the FIFO 98 then operate again to pass the commands from the CPU host bus 14 directly (without passing through the memory 30) to the graphics engine 110 for processing. The software maintains a running estimate of the total number of commands at any instant in the off chip GUI FIFO 30 and in the on chip FIFO's 62 and 98. When the estimate in the software is that the off chip GUI FIFO 30 and the on chip GUI FIFO's 62 and 98 are substantially full, the software polls the counter 130 (Figure 3a(1)) to determine the remaining storage depth available in the FIFO's 62 and 98 and the memory 130. The counter 130 indicates at each instant the total number of commands in the on-chip FIFO's 62 and 98 and the off-chip GUI FIFO memory 30. This polling is provided because the software knows only of the commands being transferred to the on chip FIFO 62 and does not know of the commands being transferred from the FIFO 98. When queried in this manner (Figure 3a(1)), the counter 130 transmits, through the FIFO depth bus 69 to the host bus interface 62, the total number of commands in the on-chip FIFO's 62 and 98 and in the off-chip GUI FIFO memory 30. The host bus interface 62 then transmits this information through the bus 14 to have the depth count in the software updated to the actual count provided by the counter 130. The counter 130 is designated in Figure 3a as "UP/DOWN COUNTER FOR ON-CHIP and OFF-CHIP FIFO's." An up-down line 131 is provided to indicate the commands passing to the FIFO 62 and passing from the FIFO 98. This causes the bus 69 to indicate at each instant the total number of commands in the FIFO's 62 and 98 and in the GUI FIFO memory 30. Clock signals are provided on a line 132 connected to the counter 130. It will be appreciated that this type of query from the software to the counter 130 will be relatively infrequent. One reason is that the capacity of the off chip GUI FIFO 30 will be chosen to be large, typically approximately 1K words. It will also be appreciated that the frequency of such near-full occurrences will be progressively decreased even further as the capacity of the off chip GUI FIFO 30 is progressively increased from 512 commands to 64,000 commands. It may frequently happen that the host bus interface FIFO 62 becomes full. When this occurs, the host bus interface FIFO controller 66 makes the voltage on the CPU ready line 65 low. When the voltage on the CPU ready line 65 becomes low, the CPU is prevented from transmitting any additional commands over the local bus 14 in Figure 2a to the memory or to the peripheral equipment 23 in Figure 2a to operate the peripheral equipment such as servicing disk drive data transmission. If the CPU ready line 65 remains low continuously for an extended period of time such as several microseconds, disk drive data may be lost. To prevent this from happening, a command passes from the CPU 12 to the host bus interface and FIFO 62 (Figure 3a(1)). This occurs only when the off chip GUI FIFO 30 is one (1) or more words short of being full. When the off chip GUI FIFO 30 accepts this word from the input FIFO 62, it communicates a command through a bus 122 to the GUI FIFO controller 82. This causes the GUI FIFO controller 82 to shift the commands in the input FIFO 62 one position to the right in the input FIFO, making the input FIFO available to store a new command word. The interface FIFO controller 66 then causes the voltage on the ready line 65 to become high. The CPU 12 is now able to pass commands through the peripheral interface in Figure 2a to operate the memory or the peripheral equipment 23. When the device driver software predicts that the off chip GUI FIFO 30 is one (1) word short of being full, the flow of graphics commands from the CPU is halted. The depth available in the FIFO 30 is then polled by the device driver software through the line 69 from the up/down counter 70. The available count remaining in the off chip GUI FIFO 30 is updated in the software and no graphics commands are transmitted by the CPU 12 until the predicted depth available in the GUI FIFO 30 is greater than 1. While graphics commands are halted, other commands may be transmitted over the local and peripheral buses because the voltage on the CPU ready line 65 is high. Figures 3b(1) and 3b(2) show an embodiment similar to that shown in Figure 3a and described above. However, the embodiment shown in Figure 3b uses a synchronous dynamic random access memory (dRAM) as the display memory 24b. Although the memory has a single synchronous parallel port, signal flow in and out of the GUI FIFO 30 and the frame buffer memory 26 is schematically shown on four (4) separate lines for purposes of explanation. Because of this, the pixels read from the frame buffer 26 in the display memory 24 are introduced through a bus 130 to the integrated circuit chip 60. The integrated circuit chip 60 then passes the pixel data through a bus 132 to the RAMDAC stages or the PACDAC stages. The pixel data may pass through the buses 130 and 132 at a suitable frequency such as fifty megahertz (50 Mhz). Figures 3c(1) and 3c(2) show the graphic user interface (GUI) 18c of Figure 2c in additional detail but does not show the interrelationship of the graphics user interface 18 and the display memory 24c in additional detail. The reason is that both the graphic user interface 18c and the display memory 24c communicate with the high speed peripheral bus 54 in Figure 2c. The high speed peripheral bus 54 is also shown in Figure 3c. As in the previous embodiments, the graphics user interface 18c is disposed on an integrated circuit chip, this chip being indicated at 60c in Figure 3c. Furthermore, the chip includes all of the stages shown in Figures 3a and 3b, these stages having the same numerical designations as the corresponding stages shown in Figure 3a but with the suffix "c" following these numerical designations. A high speed combined memory bus auxiliary control and interface 140 is also disposed on the chip. The auxiliary control and interface 140 writes graphics commands onto the high speed bus 54 from the input switch 72 and reads graphics commands from the bus 54 into the output switch 76 from the bus 54. The graphics engine 110c writes pixel data through the line 112c into the auxiliary control and interface 140 which then passes the pixel data to the bus 54. The pixel address from the graphics engine 110c is written through the line 118c into the auxiliary control and interface 140 which then passes the pixel address into the bus 54. The GUI FIFO controller 82c provides the write/read address of the graphics command on a line 116c to the auxiliary control and interface 140 and provides the command word on the bus 54. Commands are transferred through a bus 142 from the auxiliary control and interface 140 to the host bus interface and FIFO 62c. Status and control information passes between the auxiliary control and interface 140 and the host bus interface FIFO controller through a bus 144. As previously described, Figures 3a(1) and 3a(2) show the connections to the display memory 24 on a schematic basis to enhance an understanding of the operating of such system. Figure 4a(1) and 4a(2) are substantially the same as Figures 3a(1) and 3a(2) except that the buses 112 and 116 and the buses 73 and 75 respectively extending between the switches 72 and 76 and the off chip GUI FIFO 30 are replaced by a bus 150 providing thirty two (32) bit data words, a control bus 152 and a ten (10) bit address bus 154. The buses 150, 152 and 154 provide communication between a display memory bus interface 156 and the display memory 24. The bus interface 156 receives command write information through a bus 158 from the switch 72 and write/read address control information from the off chip RAM controller 114 through a bus 160 and provides command read information through a bus 161 to the switch 76. The pixel write data is supplied through a bus 162 from the on chip graphics engine 110. Figures 4b(1) and 4b(2) are substantially the same as Figures 3b(1) and 3b(2) except that they incorporate the changes discussed above for Figures 4a(1) and 4a(2). However, the numerical designations individual to the embodiment shown in Figures 4a(1) and 4a(2) are the same in Figures 4b(1) and 4b(2) except that they are followed by the suffix (b). For example, the designation 150b in Figure 4b(2) corresponds to the designation 150 in Figure 4a(2). The system and method described above have certain important advantages. They provide for the transfer of commands from software to hardware and the processing of such commands in the hardware with infrequent polling of the hardware by the software to determine if the hardware has processed such commands. As will be appreciated, this significantly enhances the rate at which the system and method of this invention are able to process the commands from the CPU. The system and method of this invention are also advantageous in providing the FIFO's 62 and 98 of limited capacity in an integrated circuit chip and in providing the memory reservoir 30 in the display memory off the chip. By providing such an arrangement, commands are normally able to pass at high rates from a CPU to the FIFO's 62 and 98 of the limited capacity on the chip for processing. When the FIFO's 62 and 98 of the limited capacity become full, the commands pass to the FIFO memory 130 through the FIFO 62 and from the memory 130 to the other FIFO 98 for processing. The system and method of this invention are further advantageous in that they operate to insure that a ready line will provide a voltage which will allow the CPU to communicate with other equipment such as peripheral equipment when the FIFO's and the memory reservoir become substantially full.

Claims: System for use with means (66) for providing commands, comprising: a first FIFO shift register (62) for receiving and passing said commands; a second FIFO shift register (98) for receiving the commands from the first shift register (62) and passing same; a third FIFO shift register (30, 30b) for receiving the commands from the first shift register (62) and passing same; a switching means (74, 74b) having a first switch position to pass the commands from the first shift register (62) to the second shift register (98) and a second switch position to pass the commands from the first shift register (62) to the third shift register (30, 30b) and then from the third shift register (30, 30b) to the second shift register (98); a controller means (82) for providing switch-over in the switching means (74, 74b) from the first switch position to the second switch position upon the occurrence of a first particular state of operation in the second shift register (98); means (110) for processing the data from the command providing means (66) in accordance with the commands passing from the second shift register (98); and a first means (96) for determining the number of commands within the second shift register (98) and for ascertaining the occurrence of the first particular state of operation in the second shift register (98) thereby causing the routing of commands from the switching means (74, 74b) into the third shift register (30, 30b), wherein: the first determining means (96) ascertains the occurrence of a second particular state of operation in the second shift register (98) thereby causing the routing of commands from the switching means (74,74b) into the second shift register (98), and a second determining means (70) determines the number of commands within the third shift register (30, 30b) in order to provide the command providing means (66) with a measure by which the command providing means (66) can control the acceptance of commands by the command providing means (66). A system as set forth in claim 1 wherein the third shift register (30, 30b) and the command providing means (66) are provided on different portions of a display memory (24, 24b). A system as set forth in claim 2, wherein an integrated circuit chip (60) is provided and wherein the first and second shift registers (62, 98) are provided on the integrated circuit chip (60) and the display memory (24, 24b) is disposed off the integrated circuit chip (60). System as set forth in any one of claims 1 to 3wherein the switching means (74, 74b) continues in the second switch position, after being changed from the first switch position to the second switch position, until the occurrence of a particular operative relationship in the third shift register (30, 30b) and wherein the switching means (74, 74b) is changed to the first switch position upon the occurrence of the particular operative relationship in the third shift register (30, 30b). System as set forth in any one of claims 1 to 4, wherein the third shift register (30, 30b) being operative to delay the commands passing from the first shift register (62) to and through the third shift register before introducing the commands to the second shift register (98). System as set forth in claim 5, wherein the switching means (74, 74b) being operative in the second switch position during the time that the commands are passing from the first shift register (62) through the third register (30, 30b) to the second shift register (98). System as set forth in any one of claims 1 to 6, said first determining means (96) indicates at each instant the number of commands in the second shift register (98), and comprises means responsive to a particular count of the commands in the second shift register (98) for converting the switching means (74, 74b) from the first switch position to the second switch position. System as set forth in claim 7 wherein the particular count in the second shift register (98) indicates that the second shift register is filled to a particular level with commands and wherein the third shift register (30, 30b) thereafter receives the commands passing through the first shift register (62) until there are no commands in the third shift register. System as set forth in claim 7 wherein the particular count in the second shift register (98) indicates that same is full with commands. A method of processing information including the following steps: providing a plurality of commands for controlling the processing of the information, introducing the commands to a first FIFO shift register (62) which pass the commands from its output, after a first particular delay; introducing the commands from the first FIFO shift register to a second FIFO shift register (98) which pass the commands from its output, after a second particular delay; introducing the commands from the output of the first FIFO shift register (62) to a third FIFO shift register (30,30b) which pass the commands from its output, after a third particular delay to the input of the second FIFO shift register (98); normally providing for the introduction of the commands from the output of the first FIFO shift register (62) to the second FIFO shift register (98); providing for the introduction of the commands from the output of the first FIFO shift register (62) to the third FIFO shift register (30, 30b) when the second FIFO shift register (98) becomes overloaded; thereafter continuing the introduction of the commands from the output of the first FIFO shift register (62) to the third FIFO shift register (30, 30b) until there are no commands in the third shift register; providing for an estimate at each instant of the extent to which the first, second and third FIFO shift registers (62, 98, 30, 30b) are becoming overloaded on an aggregate basis; providing for an updating of the actual extent that the first, second and third FIFO shift registers have become overloaded on an aggregate basis when the estimate is that the overloading has occurred, and interrupting the transfer of commands to the first FIFO shift register (62) when the overloading of the commands in the first, second and third FIFO shift registers have actually occurred on an aggregate basis. Method as set forth in claim 10 wherein the step is in software of providing for an estimate at each instant of the extent to which the third FIFO shift register (30, 30b) is becoming overloaded and wherein the updating is in software of the actual extent that the first, second and third FIFO shift registers (62, 98, 30, 30b) have become overloaded on an aggregate basis when the estimate in software is that the overloading has occurred. Method as set forth in claim 10 or 11, the steps of: providing graphics data in a display memory (110), and processing the graphics data in accordance with the command from the output of the second shift FIFO register (98). Method as set forth in any one of claims 10 to 12 wherein the first FIFO shift register (62) passes the commands through same at a first particular rate, and the second FIFO shift register (98) passes the commands through same at the first particular rate, and the third FIFO shift register (30, 30b) passes the commands through same at a second particular rate different from the first particular rate. Method as set forth in any one of claims 10 to 13 wherein: the commands entering and leaving the second FIFO shift register (98) are counted to indicate the number of commands in same at each instant; the commands entering and leaving the third FIFO shift register (30, 30b) are counted to indicate the number of commands in same at each instant and the counts of the commands in the second and third FIFO shift registers (98, 30, 30b) are used to control the passage of the commands directly from the first FIFO shift register (62) to the second FIFO shift register (98) or the passage of the commands from the first FIFO shift register (62) through the third FIFO shift register (30, 30b) to the second FIFO shift register (98).

Inventors: ASAL MICHALE D, BAKER DAVID C, ASAL, MICHALE D., BAKER, DAVID C.
Applicants: BROOKTREE CORP, BROOKTREE CORPORATION
Application year: 1995
Main classification: G06F9
IPC codes: G06F9, G06T11, G06F3, G09G5