COMBINED PROGRAMMABLE LOGIC ARRAY AND ARRAY LOGIC

Abstract: A PLD comprises a programmable first AND array whose inputs are selectively connectable to input lines and whose outputs are selectively connectable to a programmable second OR array. The PLD further comprises a programmable third AND array whose inputs are selectively connectable to the input lines, and whose outputs are fixedly connected to inputs of a fixed fourth OR array. The outputs from the second OR array are also connected in a fixed manner to the fourth OR array. This arrangement overcomes some of the weaknesses in both the conventional PAL and PLA architectures while retaining most of their strengths.

Description: Combined programmable logic array and array logic HELD OF THE INVENTION The invention relates to an electronic circuit comprising a programmable logic device (PLD). The PLD has input lines, a first programmable AND array with first inputs, that are selectively connectable to the input lines, and with first outputs, and a second programmable OR array with second inputs, that are selectively connectable to the first outputs, and with second outputs. BACKGROUND ART Programable logic devices (PLD) are well known and widely used in the field of semiconductor digital integrated circuits. A reason for this is that PLD's allow flexibility in tailoring a general integrated circuit to meet specific applications at low cost. PLD's are generally classified as field-programmable (user-programmable) and mask programmable (programmable by the manufacturer in the fabrication process. Logical operations in PLD's are performed with arrays of basic logic gates having programmable elements at selected points. A PLD generally comprises a programmable matrix or array, functionally made up of a first array of AND gates whose outputs are connected to a second array of OR gates. A plurality of input lines provide input signals to the AND array, and a plurality of output lines carry the output signals of the OR array. Two popular commercial embodiments are known as Programmable Array Logic (PAL) and Programmable Logic Array (PLA). See the detailed description of such kinds of devices in USP 4, 124,899 which describes the PAL type of PLDs, and USPs 4,422,072 and 4,703,206 which describe in detail the PLA type of PLDs. Since the description in these patents are so detailed and complete, it is unnecessary to repeat those details here, and the full contents of those three patents are herewith incorporated by reference. For purposes of the present invention, it is only necessary to briefly point out that the PLA type of PLD is characterized by a programmable AND array and a programmable OR array and the PAL type is characterized by a programmable AND array and a fixed or non¬ programmable OR array. That is, in a PLA type, the input lines are selectively connectable to the gates of the AND array and the outputs of the AND array are selectively connectable to the inputs of the gates of the OR array. In a PAL type, on the other hand, the input lines are selectively connectable to the gates of the AND array but the outputs of the AND array are fixedly connected to the gates of the OR array. OBJECT OF THE INVENTION It turns out that the PLA architecture has certain advantages and disadvantages when used to implement certain kinds of logic circuits, and the PAL architecture has certain advantages and disadvantages when used to implement other kinds of logic circuits. Reference is made to the description of the drawings below and also to the aforementioned patents for a further description of problems and solutions of their respective architectures. It is an object of the invention to provide a PLD whose configuration renders the PLD more generally applicable than a sole PAL device or a sole PLA device. SUMMARY OF THE INVENTION Accordingly the invention provides a circuit as specified in the preamble, and characterized in that the PLD further comprises a third programmable AND array having third inputs selectively connectable to the input lines, and having third outputs, and a fourth fixed OR array having fourth inputs fixedly connected to both the second outputs of the second OR array and the third outputs of the third AND array, and having fourth outputs. The PLD architecture of the invention combines the best features of the PLA and PAL types of architectures in a single device. This arrangement overcomes some of the weaknesses in both the conventional PAL and PLA architectures while retaining most of their strengths. In a further embodiment, the third programmable AND array has a number of P sets each with a number of Q logic gates, wherein each of the Q logic gates of a respective one of the P sets has an output connected to a respective OR gate of the fourth array. BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the invention, its operating advantages and specific objects attained by its use, reference should be had to the accompanying drawings and descriptive matter in which there are illustrated and described the preferred embodiments of the invention. Like reference numerals or letters in the various figures designate the same or similar components. In the drawings: Fig. 1 is a schematic diagram of one form of PLD circuit in accordance with the invention; Fig. 2 is a schematic diagram of another form of PLD circuit in accordance with the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As is well known, a PLD comprises an array of logical AND and OR gates that can be programmed for a specific function. Each output function is the sum (logical OR) of selected products (logical ANDs), where each product is the product of selected polarities of selected inputs. The PLD can be programmed so that any input line can be connected to any AND input gate and any of the products (ANDs) can be summed by any of the OR gates. Programming is typically accomplished by blowing or not blowing fusible links connecting the conductors of the two arrays. Given enough products, often referred to for convenience as p-terms, the sum of the products can express all Boolean transfer functions. While these known principles have been explained in terms of AND and OR gate arrays, as is well known in the art, logical NAND and NOR gates may be utilized in conjunction with or as substitutes for the AND and OR gates, respectively. The main problems with the prior art PLDs are as follows. With an architecture made up of the PLA type only, when dealing with p-terms that are unique to one output, the PLA-only architectures are slow and array-inefficient, in that too many gates are needed to implement the desired logic circuit. On the other hand, when there exist common p-terms between outputs, the PAL-only architectures are array inefficient, and when more p-terms than are available are required for a particular output, then the PAL-only architectures are slow in performance. The PLD of the invention exhibits the best features of each of these previously-known types of architectures while optimizing array utilization and performance. Fig. 1 shows a circuit diagram of one form of PLD architecture of the invention. It comprises a programmable first AND array 10 comprised of a plurality (M) of AND gates 11 , each of which has a plurality of inputs represented by the single line input 12. A plurality (N) of PLD inputs 20 are provided connected to two inverters 21, 22 whose respective outputs 23, 24 provide opposite polarity (high or low; " l " or "0") signals of the signal at inputs 20. As will be observed, each dual input line 23, 24 is connectable to an input 12 of each gate 11. This connectability is represented by the circle at each intersection of the lines. Thus, if, say, four of the input lines had high or low polarity outputs connected to the single input line 12 of a gate 11, in reality it means that four separate inputs exist to that one gate, and in accordance with the usual truth tables, the gate output depends on the respective low and high inputs to that gate. This same symbology is used for the inputs to the other AND and OR gates shown. The gates 11 provide a first set of outputs 14 which are selectively connectable to a second set of inputs 32 to a programmable second OR array 30 comprising (O) OR gates 31 which drive a second set of output lines 34. The circuit further comprises a programmable third AND array 50 comprising a plurality (P) of sets of (Q) AND gates 51, 52 having a third set of respective inputs 53, 54 that are selectively connectable to the first set of input lines 20 and having a third set of respective outputs 56, 57 that are fixedly connected (non¬ programmable) as a fourth set of respective inputs 72, 73 to a fixed fourth OR array 70 comprising a plurality (R) of OR gates 71 providing a fourth set of outputs 74. Connected to each of the outputs 74 is a controllable buffer 80, e.g., a three-state buffer, whose control inputs are accessible via a further PLD input 81. Thus the outputs of the PLD at terminals 90 can be selectively controlled via the input 81. The second set of outputs 34 from the second OR array 30 is also connected in a fixed (non-programmable) manner as inputs to the fourth OR array 70. Also, each AND gate of a set 51, 52 has a respective output 72, 73 connectable to the same gate 71 of the fourth OR array 70. For simplicity, the additional inputs are indicated by the curved extension at the front of the OR gate symbol. As is common in this art as explained above, the small circles at the intersections represent fusible links that can be blown or left alone to provide the desired set of connections to implement a particular logic circuit. It will thus be clear that the first 10 and third 50 arrays made up of AND gates are programmable, and that the third 30 array made up of OR gates is also programmable, but that the fourth 70 array of OR gates is fixed or non-programmable. Typically, as examples for the PLD illustrated in Fig. 1, there can be provided N inputs = 8-48 for a first array 10 comprising M = 8-64 AND gates 11 , a second array 30 comprising O = 8-32 OR gates 31, a third array 50 comprising P = 8-32 sets of Q = 4-16 AND gates 51, 52 each, and a fourth array 70 of R = 8-32 OR gates 71 feeding R outputs 90. The invention is not limited to these typical numbers of components and other numbers of components are considered within the scope of the invention. The process or technology by which the PLD of the invention is made is not important and any of the standard bipolar, NMOS or CMOS processes can be used. Also, it will be clear from the foregoing that the number of array elements, i.e., the array size, in any of the four arrays can be varied without departing from the principles described herein. It will also be clear that the heretofore described "fuse-link" system may be implemented in any of the other well known technologies, including electrically-erasable floating gate memory elements. It will also be clear that macro cells, such as are described in the referenced patents, including EX-ORs and other well known macro cell parts such as flip-flops, can also be added without departing from the scope of the invention. Fig. 2 shows a circuit similar to that of Fig. 1 in which flip-flops 95, as macro cells, are added to the PLD of the invention, with an additional control line 96 provided to drive the flip-flops, as is described in the referenced patents. The main advantages of the invention are that it can handle faster and more array-efficiently logic functions using p-terms which are unique to one output, compared to PLA-only implementations, since the second array can effectively be bypassed in the signal path. Also, when common p-terms between outputs exist, again they are handled in a more array-efficient manner because only one p-term is needed, which can be shared among all relevant outputs. Performance is improved because the power dissipation required for the previous (PAL-only) multiple p-term implementation can be reallocated among the remaining, reduced number of, p-terms. And, when more p-terms than are available are required for a particular output, performance will be faster because additional outputs are not necessary to help form the required partial products, as would be required in a PAL-only implementation. While the invention has been described in connection with preferred embodiments, it will be understood that modifications thereof within the principles outlined above will be evident to those skilled in the art and thus the invention is not limited to the preferred embodiments but is intended to encompass such modifications.

Claims: CLAIMS: 1. An electronic circuit comprising a programmable logic device (PLD) having: - input lines (23, 24); - a first programmable AND array (10) having first inputs (12) selectively connectable to the input lines, and having first outputs (14); - a second programmable OR array (30) having second inputs (32) selectively connectable to the first outputs, and having second outputs (34); characterized in that the PLD further comprises: - a third programmable AND array (50) having third inputs (53, 54) selectively connectable to the input lines, and having third outputs (56, 57); - a fourth fixed OR array (70) having fourth inputs (72, 73) fixedly connected to both the second and third outputs, and having fourth outputs (74). 2. The circuit of claim 1, further comprising controllable buffers connected to the fourth outputs. 3. The circuit of claim 1, further comprising macro cells connected to the fourth outputs. 4. The circuit of claim 1, wherein: - the third programmable AND array has a number of P sets of a number of Q logic gates (51 , 52); - each of the Q logic gates of a respective one of the P sets has an output connected to a respective OR gate of the fourth array.

Inventors: CLINE RONALD LEE, CLINE, RONALD, LEE
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1995
Main classification: H03K19
IPC codes: H03K19