Flash EEPROM with integrated device for limiting the erase source voltage

Abstract: A Flash EEPROM comprises an array (1) of memory cells (MC) having a common source line (SL) connecting together source electrodes (S) of the memory cells (MC), said common source line (SL) being coupled to a positive potential (VPP) when the memory cells (MC) must be electrically erased, and resistive feedback means (R) coupled in series between said positive potential (VPP) and said common source line (SL). The Flash EEPROM comprises voltage limiting means (CL) coupled to said common source line (SL) for limiting the potential of the common source line (SL) to a prescribed maximum value (VCL) lower than said positive potential (VPP).

Description: The present invention relates to a Flash EEPROM with an integrated device for limiting the erase source voltage. It is known that the distinctive feature of Flash EEPROMs over other non-volatile semiconductor memories is the possibility to electrically erase large groups of memory cells simultaneously. A Flash EEPROM memory cell is a floating-gate MOSFET comprising an N type source region (source electrode) and an N type drain region (drain electrode) formed in a spaced-apart condition in a P type semiconductor layer. The portion of the P type layer comprised between the source and drain regions forms a channel region, and a polysilicon floating gate is placed above the channel region with the interposition of a gate oxide layer. A polysilicon control gate is insulatively disposed over the floating gate. The groups of memory cells which are to be simultaneously erased have the source electrodes commonly connected to a common source line. In dual power supply Flash EEPROMs, requiring a first external power supply typically of 5 V (5 V +/- 10%) and a second external power supply of approximately 12 V (12 V +/-10%) erasure of the memory cells is carried out by applying a high positive voltage to the common source line of the group of memory cells that must be erased, while keeping the control gate electrodes grounded and the drain electrodes floating. In this way, a strong electric field develops in the gate oxide layer causing electrons trapped in the floating gate to tunnel into the source region through the gate oxide layer (Fowler-Nordheim tunneling). The high electric fields at the surface of the source regions and at the junction between the source regions and the P type layer give rise to hot carrier generation and to large source-to-substrate currents (leakage currents), which are several order of magnitude higher than the Fowler-Nordheim tunneling current. To control the source-to-substrate currents and the generation of hot carriers, a resistive feedback is normally provided between the 12 V external power supply and the common source line of the group of memory cells that must be erased. Such a resistive feedback is for example the resistivity of a switching transistor provided in series to the common source line to allow switching of the common source line potential between ground (in READ and PROGRAM mode) and the 12 V power supply (in ERASE mode). The actual voltage of the common source line thus depends on the voltage drop across the resistive feedback, the latter depending in turn on the source-to-substrate current (the Fowler-Nordheim current is negligible). The source-to-substrate current is maximum at the beginning of erasing, when the potential of the floating gate is more negative due to the electrons trapped therein. As erasing proceeds, electrons are extracted from the floating gate and the potential of the latter becomes less negative. The electric fields at the surface of the source regions and at the junction between the source regions and the P type layer decreases, and so does the source-to-substrate current. The voltage drop across the resistive feedback decreases, and the potential of the common source line increases towards 12 V. In the final phases of erasing, the potential of the common source line (i.e. of the source regions of the memory cells) becomes unnecessarily high, and this causes the memory cells (expecially those that have a low erasing time) to be submitted to electric stresses that reduce the memory cell reliability. The article of Atsumi et al., "A16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation", IEICE Transactions on Electronics, vol. e77-c, no. 5, May 1994 Tokyo JP, pages 791-798, discloses that in the negative gate biased erase scheme, the gate and source voltages are internally controlled during the erase operation. Internal voltage generators which control the internal voltage independent of the external voltage supply and temperature has been disclosed. The circuit utilize forward and reverse biased diodes connected in series. In view of the state of the art described, it is an object of the present invention to provide a Flash EEPROM comprising a device suitable to limit the potential of the source regions of the memory cells during erase, without negatively affecting the reliability of the memory cells. According to the present invention, such object is achieved by means of a Flash EEPROM comprising an array of memory cells having a common source line connecting together source electrodes of the memory cells, said common source line being coupled to a positive potential when the memory cells must be electrically erased, resistive feedback means coupled in series between said positive potential and said common source line, characterized by comprising voltage limiting means coupled to said common source line for limiting the potential of the common source line to a prescribed maximum value lower than said positive potential. Thanks to the present invention, it is possible to limit the source potential of the memory cells in the final phases of erasing, to reduce the electric stresses to which the memory cells are submitted. This increases the memory cells' reliability. The voltage limiting means can be embodied by a simple junction diode with cathode coupled to the common source line and anode coupled to a ground potential: in this way, when the potential of the common source line reaches the breakdown voltage of the diode, the latter clamps the potential of the common source line preventing any further increase. If the breakdown voltage of the junction diode is too low, a plurality of serially connected diodes can be provided: in this way, the potential of the common source line is clamped to a voltage equal to the sum of the breakdown voltages of the diodes of the plurality. In an alternative embodiment, the voltage limiting means can be a bipolar junction transistor, with the emitter coupled to the common source line, collector coupled to ground and base floating. The potential of the common source line is clamped to a voltage equal to the turn-on voltage of the bipolar junction transistor. The features of the present invention will be made more evident by the following detailed description of two particular embodiments, described as non limiting examples in the annexed drawings, wherein: Figure 1 schematically shows a Flash EEPROM provided with a voltage limiting device according to the present invention; Figure 2 is a comparative diagram showing the variation of the erase source voltage of the memory cells in the prior art case and in the case of the present invention; Figure 3 is a cross-sectional view of a voltage limiting device according to a first embodiment of the invention; Figure 4 is a cross-sectional views of a voltage limiting device according to a second embodiment of the invention; Figs. 5 to 8 are cross-sectional view taken at intermediate steps of a manufacturing process of the voltage limiting device of Fig. 3; Figs. 9 and 10 are cross-sectional views taken at intermediate steps of a manufacturing process of the voltage limiting device of Fig. 4. With reference to Fig. 1, a Flash EEPROM is schematically shown. The Flash EEPROM comprises an array 1 of memory cells MC; each memory cell MC has a drain electrode D connected to a respective bit line BL, a control gate electrode CG connected to a respective word line WL and a source electrode S connected to a common source line SL to which the source electrodes S of all the memory cells MC of the array 1 are also connected. In ERASE mode, the bit lines BL are left floating, the word lines WL are tied to a ground potential GND and the common source line SL is coupled to a high positive external power supply VPP (12 V +/- 10%) by means of a resistive feedback (indicated in Fig. 1 by a resistor R). In practical implementations, the resistive feedback can effectively be an integrated resistor, or it can be represented by the internal resistance of a switching transistor (not shown) that allows to switch the potential of the common source line SL from ground (when the Flash EEPROM is operated in READ or PROGRAM modes) to the high positive external power supply VPP. According to the present invention, a voltage limiting device (clamping device) CL is also connected between the common source line SL and ground. The clamping device CL is normally off, and activates when the voltage of the common source line SL reaches a clamping voltage VCL lower than VPP. In Fig. 2, t represents the erasing time and VS the potential of the common source line SL. Curve A shows the variation of the voltage VS in the case of the prior art: at the beginning of erasing the voltage VS has a value VS0 that depends on the value of the sum IS of the source-to-substrate currents of the memory cells (as previously mentioned, the Fowler-Nordheim current is negligible). As erasing proceeds, the source-to-substrate current decreases, the voltage drop across the feedback resistor R decreases, and the voltage VS asymptotically approaches VPP. Curve B in Fig. 2 showsthe case of the present invention: starting from the value VS0, the voltage VS increases in the same way as in the prior art case, but when VS reaches the voltage VCL, the clamping device CL activates and any further increase of the voltage VS is prevented. In this way, the electric stress on the memory cells is reduced and the memory cell reliability increases. Fig. 3 is a cross-sectional view of a clamping device according to a first embodiment of the present invention. In this embodiment the clamping device CL is comprised of two diodes D1, D2 connected in series. The diodes D1, D2 are formed in respective N type wells 2 formed in a semiconductor substrate 3. Each diode D1, D2 has an N type cathode region 41, 42 formed by diffusion in the N type well 2. An N+ contact region 51, 52 (for example annular in shape) is formed inside the cathode region 41, 42 of each diode D1, D2. A P+ anode region 61, 62 is formed in the cathode region 41, 42, inside the annular contact region 51, 52. The anode region 61 of D1 is connected to ground; the contact region 51 of D1 is connected to the anode region 62 of D2; the contact region 52 of D2 is connected to the common source line SL. With this arrangement, when the voltage VS reaches a value equal to the sum of the breakdown voltages of D1 and D2, the diodes break down, thus limiting the voltage VS. The doping profile of the cathode regions 41, 42 is important since it determines the breakdown voltage of the diodes. In the shown example, it is supposed that each diode has a breakdown voltage of ranging from 5 V to 5.75 V; therefore, two serially connected diodes have been used to provide a clamping voltage VCL ranging from 10 V to 11.5 V. However, it should be understood that a different number of serially connected diodes could be used, depending on the particular breakdown voltage of the diodes obtainable in the available manufacturing process. Fig. 4 is a cross-sectional view of a clamping device according to a second embodiment of the invention. In this embodiment, the clamping device CL is comprised of a floating-base lateral NPN bipolar junction transistor (BJT). The transistor is formed in a P type well region 7 formed in a semiconductor substrate 8. Inside the P type well 7, an N+ emitter region 9 and an N+ collector region 10 are formed. Between the emitter and collector regions 9, 10, a P- base region 11 is formed. The emitter region 9 is coupled to the common source line SL, the collector region 10 is coupled to ground and the base region 11 is left floating. In this embodiment, the clamping voltage VCL is given by the turn-on voltage of the BJT which determines the onset of the emitter/collector conduction. The turn-on voltage of the BJT can be adjusted to the desired value by a proper dimensioning of the area of the BJT base region 11. Also in this case, it is thus possible to obtain a clamping voltage VCL ranging from 10 V to 11.5 V. Figs. 5 to 8 are cross-sectional views showing some intermediate steps of a manufacturing process of the clamping device according to the first embodiment of the invention. Starting from a silicon substrate 3, for example of the P type, a thick field oxide layer 12 is formed over the whole surface of the substrate 3. The field oxide layer 12 is then selectively removed (by means of a photolitographic process involving a first photolitographic mask) to define active areas of suitable dimensions. In this same step, the field oxide layer 12 is selectively removed to form active areas for both the array 1 of memory cells MC and N-channel and P-channel MOSFETs of the logic circuits of the Flash EEPROM. A layer of photoresist 13 is then deposited and selectively removed (by means of a photolitographic process involving a second photolithographic mask) over the active areas, and an N type dopant is implanted in a dose of the order of 10 13 atoms/cm 2 and with an energy of the order of 1 MeV to form the N type wells 2 (Fig. 5). In this same step, N type wells are formed in the areas where P-channel MOSFETs are to be formed. An N type dopant, for example arsenic in a dose of approximately 10 15 atoms/cm 2 , is selectively implanted into the N type wells 2 to form the annular contact regions 51, 52 of the diodes D1, D2 (Fig. 6). In this same step, source regions and drain regions of the N-channel MOSFETs are also formed. An N type dopant, for example phosporus in a dose ranging from 1-5*1015 atoms/cm 2 and with an energy of 50-100 keV, is then implanted into the whole active area of the diodes D1 and D2 with an implantation angle of approximately 45°, to form the cathode regions 41 and 42 of the diodes D1 and D2 (Fig. 6). This same implant is used to form graded source and drain regions of the N-channel MOSFETs. A P type dopant, for example BF 2 in a dose in the range 1-5*10 15 atoms/cm 2 and with an energy of 20-50 keV, is then selectively implanted into the cathode regions 41, 42 to form the anode regions 61 and 62 of the diodes D1 and D2. In this same step, source regions and drain regions of the P-channel MOSFETs are formed. The subsequent process steps provide, in a totally conventional way, for forming contacts to the anode regions 61, 62 and to the contact regions 51, 52 of the diodes D1, D2, and for forming metal interconnection lines. It is worth noting that the diodes D1 and D2 forming the clamping device can be fabricated in a typical N-well or twin-well CMOS Flash EEPROM manufacturing process making use of process steps already available; in other words, they don't require additional process steps. Figs. 9 and 10 are two cross-sectional views taken at intermediate steps of the manufacturing process of the clamping device according to the second embodiment of the present invention. As in the previous case, starting from a silicon substrate 3, for example of the P type, a thick field oxide layer 12 is formed over the whole surface of the substrate 3. The field oxide layer 12 is then selectively removed (by means of a photolitographic process involving a first photolitographic mask) to define active areas of suitable dimensions. In this same step, the field oxide layer 12 is selectively removed to form active areas for both the array 1 of memory cells MC and N-channel and P-channel MOSFETs of the logic circuits of the Flash EEPROM. A layer of photoresist 13 is then deposited and selectively removed (by means of a photolitographic process involving a second photolithographic mask) over the active areas, and a P type dopant is implanted into the substrate 3 in a dose of the order of 10 13 atoms/cm 2 and with an energy of the order of 1 MeV, to form the P type well 7. In this same step, P type wells are formed in the memory array area (wherein the memory cellsare to be formed) and in the areas wherein N-channel MOSFETs are to be formed. A P type dopant, for example BF 2 in a dose in the range 1-5*10 13 atoms/cm 2 , is then selectively implanted into the P type well 7 to form the base region 11 of the bipolar junction transistor forming the clamping device (Fig. 9); the extension of the base region 11 determines the clamping voltage VCL. This same implant is used to form graded source and drain regions of the P-channel MOSFETs. An N type dopant, for example arsenic in a dose in the range 1-5*10 15 atoms/cm 2 , is then selectively implanted into the P type well 7, outside the P type base region 11, to form the emitter region 9 and the collector region 10 of the bipolar junction transistor (Fig. 10). This same implant is used to form source regions and drain regions of the N-channel MOSFETs. The subsequent process steps provide, in a totally conventional way, for forming contacts to the emitter region 9 and to the cathode region 10, and for forming metal interconnection lines. As in the previous case, the bipolar junction transistor forming the clamping device can be fabricated in a typical N-well or twin-well CMOS Flash EEPROM manufacturing process making use of process steps already available, without any additional process step.

Claims: Flash EEPROM comprising an array (1) of memory cells (MC) having a common source line (SL) connecting together source electrodes (S) of the memory cells (MC), said common source line (SL) being coupled to a positive potential (VPP) when the memory cells (MC) must be electrically erased, resistive feedback means (R) coupled in series between said positive potential (VPP) and said common source line (SL), characterized by comprising voltage limiting means (CL) coupled between said common source line (SL) and ground for limiting the potential of the common source line (SL) to a prescribed maximum value (VCL) lower than said positive potential (VPP). Flash EEPROM according to claim 1, characterized in that said positive potential (VPP) is an external power supply voltage of the Flash EEPROM. Flash EEPROM according to claim 2, characterized in that said voltage limiting means (CL) comprise at least one junction diode (D1,D2) having a cathode electrode coupled to the common source line (SL) and an anode electrode coupled to a ground potential (GND), said prescribed maximum value (VCL) being the breakdown voltage of said diode (D1,D2). Flash EEPROM according to claim 3, characterized in that said at least one diode (D1,D2) comprises a plurality of serially connected diodes (D1,D2), said prescribed maximum value (VCL) being equal to the sum of the breakdown voltages of each diode (D1,D2) of said plurality of serially connected diodes (D1,D2). Flash EEPROM according to claim 3, characterized in that said junction diode (D1,D2) comprises a first semiconductor region (41,42) of a first conductivity type forming a cathode of the junction diode (D1,D2), a second semiconductor region (61,62) of a second conductivity type formed inside said cathode region and forming an anode region of the junction diode (D1,D2), an annular semiconductor region (51,52) of the first conductivity type formed inside said cathode region (41,42) and surrounding said anode region (61,62). Flash EEPROM according to claim 5, characterized in that said cathode region (41,42) is formed in a well region (2) of the first conductivity type formed in a semiconductor substrate (3). Flash EEPROM according to claim 6, characterized in that said first conductivity type is N type and said second conductivity type is P type. Flash EEPROM according to claim 2, characterized in that said voltage limiting means (CL) comprise a bipolar junction transistor having an emitter electrode coupled to said common source line (SL) and a collector electrode coupled to a ground potential (GND), said prescribed maximum value (VCL) being equal to a turn-on voltage of the bipolar junction transistor. Flash EEPROM according to claim 8, characterized in that said bipolar junction transistor comprises a first semiconductor region (9) of a first conductivity type forming an emitter region, a second semiconductor region (10) of the first conductivity type forming a collector region, and a third semiconductor region (11) of a second conductivity type extending between said emitter and collector regions and forming a base region. Flash EEPROM according to claim 9, characterized in that said emitter region (9), said collector region (10) and said base region (11) are formed in a well region (7) of the second conductivity type. Flash EEPROM according to claim 10, characterized in that said first conductivity type is N type, and said second conductivity type is P type.

Inventors: FRATIN LORENZO, RAVAZZI LEONARDO, RIVA CARLO, FRATIN, LORENZO, RAVAZZI, LEONARDO, RIVA, CARLO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: G11C16
IPC codes: G11C5, G11C16