Jitter reduction system in digital demultiplexers

Abstract: Comprising an elastic read-write memory subassembly (EM,WP,WA,RP,RA), whose read clock (RCK) varies its frequency with the signal obtained by a phase detector (PHC) as a function of the difference in time at which two pointers, for read (RP) and write (WP), take respective reference values. When the instant at which the write pointer (WP) takes the write reference value leads or lags by one write clock cycle (WCK) with respect to previous periods, this reference is increased or decreased in the same number of units, so that there is no abrupt change in the direct current component of the output signal of the phase detector (PHC); instead gradually and in fractions of the read reference, it is incremented or reduced in order to produce a smooth variation in the frequency of the read clock (RCK) that compensates the differences in net data output and input streams of the elastic memory (EM).

Description: OBJECT OF THE INVENTION This invention concerns a system for reducing phase fluctuations or jitter in synchronous digital transmission systems in which demultiplexing is done of a group of binary channels with a determined transmission rate, also termed tributaries, starting from a single binary channel of higher order in the digital hierarchy. The tolerances in the clock frequencies that determine the transmission rates of each of the tributary channels as well as the one of the channel of higher hierarchy require the use of certain justification mechanisms during the process of tributary multiplexing, and of frequency adjustment in some of the clocks of these tributaries when they are being demultiplexed. It is of special application in the demultiplexing of tributary channels in the Synchronous Digital Hierarchy when extracting the tributary channels from the corresponding channel of higher order in the digital hierarchy when there are strict limitations in the value of jitter in any of the tributary channels in question. BACKGROUND TO THE INVENTION In synchronous digital transmission systems, channels at a determined data rate are combined or multiplexed to form a channel of higher order in the digital hierarchy. This channel of higher hierarchical order is formed, for each frame, by a frame of each tributary plus additional information termed the path overhead in which are included justification bits that permit the absorption of excessive or insufficient net information streams in the incoming frames of each tributary, produced as a result of the dock tolerances of each channel. These bits are obtained by justification mechanisms, normally of bits or bytes, that compensate for the excess of input information of the corresponding tributary channel by means of negative justification, consisting of transmitting the excess information bits of the tributary in what are termed justification bits and indicating this situation with other justification control bits. In a similar manner, when there is insufficient input information in a tributary channel, positive justification is done, which basically consists of marking certain bits, which normally carry information, as vacant. These techniques are used, as has already been indicated, in a path in which lower order plesiochronous tributaries are combined to form a higher order channel. This higher order channel has its own fixed frequency dock, for which reason the differences with the corresponding tributary clocks are taken up by means of the justification mechanisms mentioned. In the inverse process, in which there is a higher order channel from which several tributaries have to be obtained, there are other mechanisms that permit the net data streams to be maintained, at both the input and the output, for the correct operation of the digital transmission system. These mechanisms are constituted by the use of "elastic memories" as explained in the book "Jitter in Digital Transmission Systems" by Patrick R. Trischitta and Eve L. Varma, published by Artech House with ISBN 0-89006-248-X, chapter 5, pages 103-139. This document discloses a jitter reduction system according to the preamble of independent claims 1 and 2. In this publication, figure 5.10 shows in graphical form how a tributary is obtained from a channel of higher hierarchical order in which there are two pointers, one for writing and one for reading, that operate cyclically on the same memory, in which the write pointer has control of the storage addresses of the input data entering this memory, and the read one has control of the read addresses for obtaining the output data. The write pointer is formed by a cyclic counter that is incremented according to a write clock signal, which is blocked when bits are detected that do not belong to the tributary in question; that is, it detects path overhead,' information from other tributaries, or else empty justification bytes or groups of eight justification bits, also empty. In this way, though not with a steady flow, the memory holds, in a sequential and cyclic form, only the information bits of the corresponding tributary. Simultaneously, the read pointer, which is another cyclic counter, is incremented in accordance with a read dock signal in order to proceed with the extraction of the information data of the corresponding tributary. When, as a consequence of the tolerances in the read and write dock frequencies, small differences arise in these, then one of the two pointers would catch up with the other so that all the information entering the memory could not be read and there would be a loss, or else the amount of information read would be greater than that entering and there would be a case. This comparison signal is filtered and applied to a voltage controlled oscillator which serves to generate the clock signal with which the read pointer works. In this manner, if the read pointer, or data output, is delayed with respect to the write pointer, the read clock frequency is increased in order to compensate the delay. Similarly, if the read pointer is fast, the read clock frequency is reduced to compensate the advance. Nevertheless, despite the assurance that the net amount of information that leaves the memory is the same as that which enters, the relative leads and lags in the phase comparison signals mentioned, mainly due to the justification mechanisms, produce a phase noise or jitter which can surpass the permissible values according to the standards set for the Synchronous Digital Hierarchy. Although at first sight it could be imagined that this can be achieved by narrowing the passband of the lowpass filter at the input to the voltage controlled oscillator, this would produce locking-on problems in the phase-locked loop circuit, and consequently this solution does not appear acceptable for this system. Document EP-A-0 500 243 (NEC CORPORATION) teaches a byte destuffing circuit which received data signal in a byte interleaved multiple frame structure is stored into a buffer memory, and a clock sequence is recovered. The recovered line clock is applied to a write address generator for storing the data on a per byte basis into a buffer memory. In response to a destuffing control signal, the write address generator suspends the generation of a write address if positive byte stuffing is effected at the transmit end, and destuffing is effected on the recovered clock sequence on a bit-by-bit basis during successive eight frames. The destuffed clock sequence is applied to a phase comparator for comparison with a local clock sequence generated by a VCO which is controlled by the phase comparator in a phase-locked loop. The local clock sequence is used to drive a read address generator for reading data from the buffer memory on a per byte basis. TECHNICAL PROBLEM TO BE RESOLVED The technical problem therefore lies in achieving a reduction in the phase noise or jitter in the Synchronous Digital Hierarchy output tributary data stream such that the strict limitations are satisfied with respect to the jitter permitted by the various standards. CHARACTERISATION OF THE INVENTION The system according to the invention comprises an elastic read-write memory subassembly for obtaining tributary channels in digital demultiplexers that reduces the jitter in the data recovered from a channel of higher hierarchical order. This assembly is based on the use of a read clock for the memory that varies its frequency in accordance with the control signal produced by a phase detector as a function of the difference in the times when two pointers, one for writing and the other for reading, respectively reach determined reference values, Rref, Wref.The basic characteristic of this system is that when, in an elastic memory fill cycle, the instant at which the write pointer reaches the write reference value Wref is ahead or is behind by at least one write clock cycle with respect to preceding periods, said reference is increased or decreased by this same number of units, so that there is no abrupt change in the direct current component of the output signal from the phase detector, but, by means of fractions of the read reference Rref, the latter is increased or decreased gradually, accordingly, in order to produce a smooth change in read clock frequency that compensates for the changes in the amount of information for the memory that varies its frequency in accordance with the control signal produced by a phase detector as a function of the difference in the times when two pointers, one for writing and the other for reading, respectively reach determined reference values, Rref, Wref. The basic characteristic of this system is that when, in an elastic memory fill cycle, the instant at which the write pointer reaches the write reference value Wref is ahead or is behind by at least one write dock cycle with respect to preceding periods, said reference is increased or decreased by this same number of units, so that there is no abrupt change in the direct current component of the output signal from the phase detector, but, by means of fractions of the read reference Rref, the latter is increased or decreased gradually, accordingly, in order to produce a smooth change in read dock frequency that compensates for the changes in the amount of information contained in the elastic memory. In a similar fashion, and based on the same generic concept, it is possible to keep the read reference constant, and make it the write reference Wref that is increased or decreased in a gradual manner in order to produce the smooth changes in the read dock frequency and compensate the same effect as before. BRIEF FOOTNOTES TO THE FIGURES A fuller and more detailed explanation of the invention can be found in the description of a preferred implementation based on the figures below in which: figure 1 is a block diagram of a demultiplexing system for a tributary of the Synchronous Digital Hierarchy that makes use of an elastic memory in accordance with the state of the art, figure 2 shows a block diagram of a demultiplexing system according to a preferred implementation of the invention, and figure 3 shows the timing charts of the input and output signals of the phase comparator of the block diagrams of figures 1 and 2. DESCRIPTION OF AN IMPLEMENTATION OF THE INVENTION A preferred implementation, according to the invention, is based on the recognised block diagram of the state of the art shown in figure 1. In this figure, an elastic memory EM is shown with a size 64x8, that is, 64 words with 1 byte each. Into this memory words appearing on a write data bus WDB can be written into write addresses WA indicated by a write pointer WP. This write pointer is formed by a module-64 cyclic counter. To increase the value of this write pointer, the latter receives a dock signal at a frequency one eighth of that of the digital hierarchy bit rate being received, so that all the bits transmitted are stored in the elastic memory EM grouped in eight-bit words. Simultaneously, in other different modules (not shown), frame detection, tributary selection, etc. take place, so that a write dock disable control signal DWCK is generated which blocks the write clock signal WCK at an inhibit gate of clock WCKI when the eight bits present on the write data bus WDB do not belong to the tributary to be recovered. In addition, the justification indicator bits at byte level are examined in a byte justification detector 8JD so that the write dock WCK is also blocked when there is a positive justification byte. At bit level, there is also a bit justification detector 1JD that progressively stores on a temporary basis the parallel input data and presents at its output the eight-bit words grouped consecutively by means of the necessary displacement that depends on the justified bits. In this way, when an extra bit appears at a given moment in a complete frame (due to the bit justification mechanism), the latter is temporarily stored so that, along with the first seven bits of the following byte corresponding to the same tributary, an eight-bit word can be completed which will be stored in the elastic memory EM. The bit justification detector 1JD also blocks the write clock WCK so that a new word is not written into memory until it is complete. On the read side, in like manner, there is a read pointer RP similar to the write one, for reading the words stored on a read address RA of the elastic memory EM. These words are present on the read data bus RDB. The read pointer RP is also formed by a cyclic counter of the same module as the memory size; it is increased in accordance with a read clock RCK at a rate that is one eighth that of the serial output data. This clock is obtained from a serial read dock SRCK by dividing the frequency by eight in a divider DIV, which is formed by a module-8 digital counter. The serial read clock SRCK is obtained from a voltage controlled crystal oscillator VCXO to which is applied a frequency control signal FC to increase or decrease its frequency of oscillation slightly with the object of keeping the frame mean data flow of input bit to the elastic memory EM equal to their output flow from it. To achieve this, there is also a phase comparator PHC that generates a digital signal the direct current component of which, obtained through a lowpass filter F, is the actual frequency control signal FC. The phase comparator PHC performs the following functions: generates a first internal signal that adopts a high level when the write address reaches a determined reference value Wref, as is indicated in figure 3, signal a), generates a second internal signal that adopts a high level when the read address reaches another determined reference level Rref, as is shown in figure 3, signal b), from the two signals mentioned, a third signal is obtained that is high when the rising edge of the first of these arrives and low when the rising edge of the second arrives. In this way, the direct current component of this signal depends on the duration ratio between the high and low periods of the signal so obtained as is indicated by signal waveform c) of the same figure. When an extra byte appears in a frame as a consequence of negative justification, the position of the high level pulse of the first internal signal of the phase comparator PHC is advanced by one write clock period WCK because the write reference value Wref is reached one clock cycle before it was expected, as can be seen from signal waveform d) of figure 3, while in the second internal signal there is still no change, as can be seen from signal waveform e) of the same figure. As a consequence of this, the duration of the low level of the output signal from the phase comparator has been shortened a little in the next period; this, even after the filter F, appears as a rounding of the frequency control signal FC that is applied to the input of the VCXO producing a variation in its frequency of oscillation that finally results in phase fluctuations or jitter. This is made worse by the fact that compensation is being done simultaneously in shifts equivalent to 8 bits, which are those that hold each word in the elastic memory EM. In figure 2 it is shown the block diagram which, according to the invention, achieves a reduction in the jitter in the recovered tributary. For this, the output signal from the VCXO that generates the serial reading clock SRCK is passed through a frequency divider DIV, which divides it by eight. This divider is formed by a 3-bit counter so that the three outputs from it are also sent to the phase comparator PHC (this differs from the previous case in that the read reference word Rref has three bits more) in order to identify the eight fractions of the read dock period RCK. For this reason the phase comparator PHC can have control not only of when the read pointer RP reaches the read reference value Rref, but also of the fractions of the read dock cycle RCK, among the eight possible, through which the second internal signal of the phase detector progresses. This is shown in figure 3, in which the waveform g) indicates the value of the three bits of the 8-bit counter that constitutes the frequency divider DIV. The waveform h) indicates the write address WA that is being taken by the read pointer RP; i) shows the waveform and position of the pulse of the second internal signal obtained by the phase comparator PHC in accordance with the state of the art (wide pulse) when the read reference is 26 and according to the invention (narrow pulse); finally, j) illustrates the gradual progression (1/8 of the read dock period) of the second internal signal of the phase comparator PHC that the latter uses to obtain the frequency control signal FC prior to passing through the lowpass filter F. With these changes, the phase comparator PHC works in principle in a similar manner but with the following differences: when the byte justification detector 8JD detects an extra byte or when the bit justification detector 1JD detects eight bits, occurring as a result of negative justifications, it increases the write reference value Wref by one unit; in this way the position of the high level pulse of the first internal signal of the phase comparator PHC is not altered; the value of the read reference Rref is increased by a fraction of a unit so that the position of the high level pulse of the second internal signal of the phase comparator is advanced by a fraction of a cycle of the read dock RCK; this is repeated on eight occasions in different cycles of the read dock RCK distributed over a relatively long period of time, on the eighth time that this process is carried out, the read reference Rref is increased by one unit, so that, once this situation has been reached, both the write reference Wref and the read reference Rref are restored to a state of equilibrium. In this way, instead of making a major variation in the frequency of the read dock RCK via the phase detector PHC, filter F and oscillator VCXO that compensates for an 8-bit excess in information in a single step, what is done is to provoke small variations that result in much smaller fluctuations in phase. To optimise the reduction in jitter even more, the system has been designed so that the moments when increments in the read reference Rref take place, are uniformly distributed between the occurrence of two byte justification detections (or of 8 detections of bit justifications). For this, the phase detector PHC has another counter that counts the time elapsed between each of the two consecutive detections of those indicated above and carries out the corresponding variations of the read reference Rref each eighth part of this time starting from the moment when the second of these two detections was received.

Claims: Jitter reduction system in a digital demultiplexer, comprising an elastic read-write memory (EM) whose read clock (RCK) varies in frequency in accordance with a control signal (FC) that is obtained from a phase detector (PHC) as a function of a difference between respective times at which a read pointer (RP) and a write pointer (WP) each take, respectively, determined read and write reference values (Rref,Wref) and characterised in that when in a cycle of the elastic read-write memory (EM), the instant when the write pointer (WP) takes the write reference value (Wref) leads or lags, with respect to the previous periods, by at least one write clock (WCK) cycle, this write reference (Wref) is increased or decreased by this same number of write clock (WCK) cycles, so that the direct current component of the output signal of the phase detector (PHC) is not altered abruptly, and the read reference (Rref) is accordingly increased or decreased gradually in fractions of the read clock (RCK) period, in order to produce a smooth increment or decrement in the frequency of the read clock (RCK) that compensates the differences in filling and emptying rates of the elastic memory (EM). Jitter reduction system in a digital demultiplexer comprising an elastic read-write memory (EM) whose read clock (RCK) varies in frequency in accordance with a control signal (FC) that is obtained from a phase detector (PHC) as a function of a difference between respective times at which a read pointer (RP) and a write pointer (WP) each take, respectively, determined read and write reference values (Rref,Wref) and characterised in that when in a cycle of the elastic memory (EM), the instant when the write pointer (WP) takes the write reference value (Wref) leads or lags, with respect to the previous periods, by at least one write clock (WCK) cycle, this write reference (Wref) is increased or decreased by this same number of wirte clock (WCK) cycles, so that the direct current component of the output signal of the phase detector (PHC) is not altered abruptly, and the read reference (Rref) is kept constant and the write reference (Wref) is put forward or back gradually in order to produce a smooth increase or decrease of the frequency of the read clock (RCK). System according to claim 1 characterised in that the instants when the read reference is increased or decreased in a fraction of a period of the read clock (RCK) have been uniformly distributed in the interval of time between the moments of detection of two consecutive justifications. System, according to claim 2 characterised in that the instants when the write reference is increased or decreased in a fraction of a period of the write clock (WCK) have been uniformly distributed in the interval of time between the moments of detection of two consecutive justifications.

Inventors: CASTANO PINTO FRANCISCO JOSE, RODRIGUEZ BEATO JOSE VICENTE, CASTANO PINTO, FRANCISCO JOSE, RODRIGUEZ BEATO, JOSE VICENTE, Castano Pinto, Francisco José, Rodriguez Beato, José Vicente
Applicants: CIT ALCATEL, ALCATEL
Application year: 1995
Main classification: H04J3
IPC codes: H04J3