METHOD AND APPARATUS IN A SEMICONDUCTOR CIRCUIT

Abstract: The present invention relates to the activation and deactivation of a transistor (Q1) in a final stage (10), for instance a push-pull final stage. The final stage is included in a voltage alternating drive system connected to a load. A current driving buffer circuit (24) in the drive system is connected to the transistor (Q1) and functions to activate and deactivate the transistor, i.e. to switch the transistor on and off, in a manner such as to generate only a low power loss in the transistor, even when the load is inductive. The current driving buffer circuit (24) includes a first inverting circuit (Q3, Q4), a second inverting circuit (Q5, Q6), a current generating circuit (Q7, Q8), and a semiconductor element (Q9). The inverting circuits coact with the current generating circuit (Q7, Q8) to switch off the transistor (Q1), wherein the current generating circuit generates a deactivation current (IDIS) which charges capacitances (CGSQ1, CGDQ1) in the transistor (Q1) very rapidly, so that the voltage (OUTLSB) on an input of the transistor (Q1) will increase to a deactivation level (VCCH). The inverting circuits coact with the semiconductor element (Q9) to activate or switch on the transistor (Q1), wherewith the semiconductor element generates an activation current (ICON) which charges the capacitances (CGSQ1, CGDQ1) in the transistor (Q1), so that the voltage (OUTLSB) on an input of the transistor (Q1) falls to an activation level (VREG).

Description: METHOD AMD APPARATUS IN A SEMICONDUCTOR CIRCUIT TECHNICAL FIELD The present invention belongs to the field of semiconductor circuits and relates to a voltage alternating power system which includes a final stage connected to a load, which may be inductive, for instance. More particularly, the invention relates to the switching of a transistor in the final stage. BACKGROUND ART There are known to the art many different types of voltage alternating power systems which have a load of an inductive character. One example is a power system having an output transistor of the kind N-channel FET-transistor. The output transistor is switched on and off alternately through the medium of a control system, wherein a voltage is applied to the inductive load when the output transistor is switched on. The control system includes one ormore components which, when the output transistor is switched off, function to discharge the gate-source capacitance in the output transistor, so that the transistor will be switched off quickly and without large power losses. Patent Specification No. EP 0 352 828 A2 describes, for instance, a bipolar transistor which is used to discharge the gate-source capacitance in the output transis¬ tor. According to U.S. Patent Specification No. 4,728,826, there is used a FET-transistor in series with a zener diode to discharge the gate-source capacitance in the output transis¬ tor, in conjunction with switching-off the transistor. U.S. Patent Specification No.4,928,053 shows how two FET-transis- tors are connected to an input on the output transistor for discharging capacitances in said transistor in conjunction with switching off the the transistor. It is also known to utilize a bipolar transistor for extract¬ ing charges from a Darlington final stage when switching off said stage in voltage-alternating power systems in which a Darlington final stage is coupled to an inductive load. An example of such a final stage is shown in Swedish Published Specification No. SE 454637. It is also known to use in a voltage alternating power system a push-pull final stage for supplying voltage to an inductive load. The push-pull final stage includes a driving or power transistor and a voltage reduction transistor which are switched on alternately, wherein when switched on the power transistor connects the load to a high voltage, whereas the voltage reduction transistor connects the load to a low voltage when switched on. Swedish Patent Specification No. SE 464 002 teaches a method of using a so-called bi-stable circuit for rapidly charging and discharging the capacitances of the power transistor when activating and switching-off the transistor respectively. The bi-stable circuit includes a number of field effect transistors and two two-pole control voltage circuits which are intended to rapidly charge the capacitances in the power transistor in conjunction with switching said transistor on and off, with the intention of reducing power losses in the power or driving transistor. The drawback with the last-mentioned voltage alternating drive system which includes a push-pull final stage is that said capacitances are not charged quickly enough, resulting in excessively high loss effects. SUMMARY OF THE INVENTION An object of the present invention is to enable the switch to be made quickly when switching off a power transistor in a final stage having an inductive load and therewith minimize power losses. This problem is associated with the fact that a voltage alternating drive system which includes a final stage having a transistor of the type PMOS power transistor, supplies voltage to a load of an inductive character. The power transistor is switched on and off in response to a control signal, the power transistor supplying voltage to the induc¬ tive load when the transistor is switched on. When the power transistor is switched off, the inductance behaves as a constant current generator resulting in a charge re- distribu- tion in the power transistor, this charge redistribution causing unintentionally the non-conducting transistor to become conductive again. The current that is conducted through the transistor unintentionally as a result of the inductive load is harmful, since it generates power losses which are particularly noticeable in high voltage circuits. It is therefore an object of the present invention to provide a method and an arrangement for switching on and off a power transistor in a final stage without generating power losses that cannot be handled. Another object is to provide a method and an arrangement which will ensure that a power transistor in a final stage will be switched of quickly and safely without risk of the power transistor being unintentionally fired or switched on and becoming current conductive. Still another object of the invention is to ensure that when a power transistor in a final stage is switched off, the inactive power transistor will receive a sufficiently large current to enable its gate-source capacitance to be quickly discharged, therewith resulting in rapid and safe deactiva- tion of the transistor. The present invention thus relates to an electric voltage alternating drive arrangement which is connected to a load, such as an inductive load, for instance. The drive arrangement may be constructed in several different ways. However, all embodiments include a final stage having a power transistor connected to the load, and an electric control circuit which is connected to the final stage and which functions to switch the power transistor on and off so that the final stage will supply the load with a high voltage when the power transistor is switched on. Activation and deactivation of the transistor, switching of the transistor from a conductive to a non- conductive state, is controlled by a control signal. An essential part of the invention resides in a current driving buffer circuit which is included in the control circuit and which is connected to the power transistor and functions to switch the power transistor on and off in response to the control signal, in a manner such that only a low power loss will be developed in the transistor, even when the load is inductive. The final stage may also include bipolar transis¬ tors, but the current driving buffer circuit is optimized for field-effect transistors. The current driving buffer circuit includes a first inverting circuit, a second inverting circuit and a Darlington circuit. When switching off the transistor, the inverting circuits coact in a manner such that the Darlington circuit will generate a switching off or deactivating current which passes to the power transistor, this transistor deactivating current causing the gate-source capacitance in the power transistor to drain rapidly so as to ensure that the transistor is switched off, therewith preventing the power transistor from unintentionally conducting current when switched off. The current driving buffer circuit also includes a semi¬ conductor element which activates the power transistor in response to the control signal, by generating an activating current which loads capacitances in the power transistor, thereby activating the same. The invention also relates to a method for switching on and off the power transistor of a voltage alternating drive arrangement of the aforedescribed kind. The method includes a first and a second inversion of a control signal, applying the inverted signals to a current generating circuit, genera¬ ting a switch off current and delivering said current to the input of the power transistor and therewith charge capacitan¬ ces in the power transistor so that the voltage level on the input of the power transistor is switched to an inactive level. This results in rapid and safe deactivation of the transistor. The method also includes activating the power transistor by generating a switch on current and charging capacitances in the power transistor, so as to switch the voltage on the input of the power transistor and therewith activate or fire said transistor. The invention thus solves the aforedescribed problem that is likely to occur when switching off a power transistor. The advantage afforded by this solution is that the power transis- tor is switched off so quickly and so positively that the drive arrangement is able to operate at high switching frequencies while still keeping power losses at a low level. Another advantage afforded by the low power losses in the final stage is that the capsule that is to enclose the final stage can be of a simple and inexpensive kind, since it need not be constructed to lead away large quantities of heat. The invention will now be described in more detail with reference to a preferred exemplifying embodiment thereof and also with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block schematic illustrating a voltage alter¬ nating drive arrangement according to the invention, includ¬ ing a push-pull final stage connected to an inductive load. Figure 2a is a detailed circuit diagram of a current driving buffer circuit in the drive arrangement, this buffer circuit being connected to a power transistor in the push-pull final stage and also to the inductive load. The Figure also shows those currents which are conducted in the circuit when switching off or deactivating the power transistor. Figure 2b illustrates the same circuit as Figure 2a, and shows those currents conducted by the circuit when activating the power transistor. Figure 3 is a flow schematic which illustrates an inventive method. Figure 4 is a diagrammatic illustration of signals which are generated in the inventive arrangement. Figure 5 is a block schematic which illustrates a further embodiment of a voltage alternating drive arrangement according to the invention, and shows a simple final stage connected to an inductive load. Figure 6 is a block schematic illustrating a third embodiment of a voltage alternating drive arrangement according to the invention, and shows a push-pull final stage connected to an inductive load. Figure 7 is a diagrammatic illustration of signals that occur in the voltage alternating drive arrangement according to Figure 6. BEST MODE OF CARRYING OUT THE INVENTION Figure 1 is a block schematic illustrating an electric voltage alternating drive arrangement connected to a load of inductive character. The drive arrangement includes a highvoltage push- pull final stage 10 connected to the inductive load 12, and an electric control circuit 14 which is connected to the push- pull final stage 10 connected to the inductive load 12, and an electric control circuit 14 which is connected to the stage 10. The final stage 10 includes a power transistor Ql which is connected to a voltage reduction transistor Q2, these transis¬ tors being connected between a positive terminal and a negative terminal of a first voltage generator VI. The positive terminal has a high supply voltage VCCH while the negative terminal has earthpotential. The high supplyvoltage may be 300 V, for instance. The connection between the transistors forms an output 16 on the final stage. The load 12 is connected to the output 16 of the final stage and also to a connection 18 between two equally as large capacitors C,. The capacitors C 1 are connected between the positive terminal and the negative terminal of the first voltage generator VI. Between the connection 18 and earth, the capacitor C 1 can be considered as a first voltage source which delivers half the high supply voltage VCCH. The inductive load 12 may be used, for instance, together with an electronically powered fluorescent tube and connected in series therewith. The control circuit 14 is constructed to alternately switch the power transistor and the voltage reduction transistor on and off, so that the load 12 on the output 16 of the final stage will be supplied alternately with the voltage VCCH on the positive terminal of the first voltage generator and alter¬ nately with a voltage of 0 V on the negative terminal of the voltage generator. The voltage on the output 16, i.e. the output voltage OUT, thus alternates between a high level, which is equal to the voltage on the positive terminal when the power transistor Ql is switched on and conducts current, and a low value which is equal to the voltage on the negative terminal when the voltage reduction transistor Q2 is switched on and conducts current. The transistors conduct current in opposite directions through the inductive load L. The push- pull final stage 10 has a first input Gl, corresponding to a control input on the power transistor, on which a buffer output signal OUTLSB is received ford switching the power transistor Ql on and off. The final stage 10 may also have a second input G2 corresponding to a control input on the voltage reduction transistor Q2 for receiving a switching signal OUTBUFF for switching the voltage reduction transistor Q2 on and off. The control circuit 14 includes a clock circuit 20, a level shifting circuit 22, an inventive current driving buffer circuit 24 connected to the power transistor Ql, and a simpler buffer circuit 26 connected to the voltage reduction transis¬ tor Q2. The clock circuit 20 (CL) is intended to generate a control signal INI, which is utilized to control activation and deactivation of the transistors in the push-pull final stage. In the illustrated case, the control signal INI is a clock signal having periodically repetitive clock pulses of equal lengths. The edge of one clock pulse is used to control deactivation of the power transistor and the activation of the voltage reduction transistor, whereas the other pulse edge is used to control deactivation of thevoltage reduction transis¬ tor and the activation of the power transistor. The control signal INI may also have shorter or longer pulses. Voltage is supplied to the clock circuit 20 from a second voltage generator V2 which delivers a logic voltage VLS of 9 V, for instance. The control signal INI, which alternates between the logic voltage VLS and 0 V is delivered from an output 28 on the clock circuit 20. The level-shifting circuit 22 (LS) has an input 30 connected to the clock circuit output 28 for receiving the control signal INI. Voltage is supplied to the level-shifting circuit 22 by the first voltage generator VI, by a second voltage generator V2 and by a third voltage generator V3 which delivers a third supply voltage VREG which is slightly lower than the high supply voltage VCCH, for instance 288 V. The level-shifting circuit 22 delivers on an output 32 a level- shifted control signal OUTLS which is synchronous with the control signal INI but the pulses shift between the high supply voltage VCCH and the slightly lower supply voltage VREG. The level-shifted control signal OUTLS has obtained in the level-shifting circuit 22 voltage levelswhich are adapted to the voltage levels in the current driving buffer circuit 24. The current driving buffer circuit 24 has an input 34 con¬ nected to the output 32 of the level-shifting circuit 22, for receiving the level-shifted control signal OUTLS. Because the level-shifted control signal OUTLS constitutes an input signal to the current driving buffer circuit 24, the signal is also referred in the description as a buffer input signal INLSB. The current driving buffer circuit 24 is connected to the positive terminals of the first voltage generator VI and to the positive terminals of the third voltage generator V3. The circuit 24 delivers on an output 36 a buffer output signal OUTLSB which is applied to the input Gl of the power transis¬ tor Ql. The buffer output signal OUTLSB alternates between a high level corresponding to the high supply voltage, and a low level corresponding tothe third supplyvoltage for activating and deactivating the power transistor Ql, ie switching the transistor on and off, in response to the control signal INI in accordance with the present invention. The simpler buffer circuit 26 has an input 38 connected to the clock circuit 20 for receiving the control signal INI. The simpler buffer circuit delivers the aforesaid switching signal OUTBUFF on an output 40, this signal being applied to the input G2 of the voltage reduction transistor Q2 for controlling activation and deactivation of the transistor. As before mentioned, the push-pull final stage 10 includes a power transistor Ql and a voltage reduction transistor Q2. The powertransistormayhave the form of a p-channel FET-transis¬ tor for instance and the voltage reduction transistormay have the form of an N-channel FET-transistor, for instance. Although bipolar transistors may also be used, the construc¬ tion is optimized for power transistors. The S-connection SI (SOURCE) of the power transistor Ql is connected to the positive terminal of the first voltage generator VI having the supply voltage VCCH, according to the present example 300 V (high voltage) , while the D-connection (DRAIN) of the transistor is connected to the output 16 of the push-pull final stage, and the G-connection Gl (GATE) is connected to the output 36 of the current driving buffer circuit 24 for receiving the buffer output signal OUTLSB. The power transistor Ql is either choked or conductive, depending on the voltage level of the buffer output signal. When the voltage of the buffer output signal is equal to the high supply voltage VCCH, the drive transistor is choked, but when the voltage is lowered to the slightly lower supply voltage VREG, the drive transistor is switched on and supplies the load with the high supply voltage. When the drive transistor is switched on, the transistor will conduct the inductive current I L from the transistor to the inductive load 12. A first so-called freewheel diode Dl is connected in parallel with the power transistor Ql, the diode Dl normally being incorporated in the drive transistor Ql. The S-connection S2 (SOURCE) of thevoltage reduction transis¬ tor Q2 is connected to the 0 V (earth) , and the D-connection (DRAIN) is connected to the output 16 of the final stage, while the G-connection G2 (GATE) is connected to the simpler buffer stage 26 for receiving the switching signal OUTBUFF. The switching signal OUTBUFF alternates between a high and a low level, wherein the high level is corresponded by the logic voltage VLS and the low level corresponds to the O voltage. The voltage reduction transistor is either choked or conduc¬ tive, depending on the voltage of the switching signal OUTBUFF. When the voltage OUTBUFF is 0 V, the voltage reduc- tion transistor is choked, whereas when the voltage OUTBUFF increases to 9 V (VLS) , the voltage reduction transistor is switched on and delivers the low voltage 0 V to the load 12. When switched on, the voltage reduction transistor Q2 leads an inductive current I L in a direction away from the load 12 to the transistor. A second so-called freewheel diode D2 is connected in parallel with the voltage reduction transistor Q2, this diode normally being incorporated in the voltage reduction transistor Q2. The two transistors Ql and Q2 are complementary to one another and together form an inverting push-pull final stage, which operates in the following, simplified, manner. When the input signals OUTLSB, OUTBUFF to the push-pull final stage have a high level, only the voltage reduction transistor Q2 is conductive or active, wherein the final stage output voltage OUT obtains a low level (0 V). This simplified description ignores thevoltage drop across thevoltage reduction transis¬ tor that occurs when the transistor is conductive, this drop in voltage being about 1 V. On the other hand, when the input signals OUTLSB, OUTBUFF have a low level, the power transistor is conductive and the final stage output voltage OUT obtains a high level (VCCH) . The voltage drop of about 1 V across the conducting drive transistorhas been ignored. The two transis¬ tors alternately conduct current in mutually opposite directions through the inductive load 12. Because the final stage output 16 is connected to an inductive load 12 and because the current through the load changes direction when the transistors Ql and Q2 are switched, the inductive load causes the output voltage level OUT to switch from a high level to a low level when the power transistor Ql is switched off. Correspondingly, the outputvoltage level OUT is switched from a low to a high level when the voltage reduction transistor Q2 is switched off. Figures 2a and 2b show a detailed circuit diagram of the current driving buffer circuit 24 in Figure 1. The Figures also show how the current driving buffer circuit is connected to the power transistor, represented by two capacitances, and to the inductive load 12. The power transistor Ql has been illustrated with two capacitances in order to enable the invention to be more easily understood. The only difference between the two Figures is that Figure 2a shows those currents that occur when the power transistor is switched off, while Figure 2b shows those currents that occur when the power transistor is switched on. A more detailed account of the problem which the invention is intended to solve is given with reference to Figures 1, 2a and 2b. In order to describe the problem, it is convenient to view the power transistor as two capacitances in accordance with Figures 2a and 2b. The first capacitance is comprised of a gate-source capacitance C GSQ1 between the input Gl of the drive transistor and the high supply voltage VCCH. The second capacitance is comprised of a gate-drain capacitance C G0Q1 between the input Gl of the drive transistor and the output 16. When the buffer output signal OUTLSB is low, i.e. at the voltage level VREG, the power transistor Ql is switched on and delivers the high supply voltage VCCH to the output 16. The voltage drop across the power transistor when said transistor is conductive has been ignored, this voltage drop being only one volt. At the same time, the transistor Ql drives an inductive current I L through the inductive load 12. Theoreti¬ cally, the power transistor is switched off as a result of the voltage on the input Gl of the drive transistor increasing to the supply voltage VCCH. This theoretical deactivation procedure, solely by increasing the voltage on the input of the drive transistor, is insufficient, however, since the power transistor can be considered as two capacitances in accordance with Figures 2a, 2b. The inductive load will behave as a current generator at the moment of cut-off and continues to conduct the inductive load current in spite of the deac¬ tivation procedure. Because the inductive load current continues to be passed through the load 12, the voltage OUT on the output 16 will fall very rapidly, so that the inductive load current I L can be passed through the freewheel diode D2 in the voltage reduction transistor Q2 until the energy in the inductive load has been discharged. The voltage OUT on the output falls to about minus 1 volt, so that the second diode D2 is able to conduct the discharge current. This rapid voltage drop on the output 16 is also assisted by the gate- drain capacitance C^, to the input Gl of the power transistor Ql, wherein the voltage on the input Gl will also fall, with the subsequent danger that the power transistor will again become conductive despite having been "switched off". The amount of current that is unintentionally passed through the power transistor in this way after having switched off the transistor will depend on the amplitude of the inductive loading current and on the driving efficiency of the transis¬ tor. This unintentional current results in power losses which are particularly notable in high voltage circuits. In brief, the problem is that when switching-off the power transistor, the voltage on its input may fall unintentionally, causing the switched off transistor to conduct current. The current driving buffer circuit 24 is constructed to solve the aforedescribed problem, and to this end includes a first inverting circuit Q3, Q4, a second inverting circuit Q5, Q6 and a current generating circuit which, in the illustrated case, is comprised of a Darlington circuit Q7, Q8. The current driving buffer circuit 24 also includes a semiconductor element Q9 for activating the power transistor Ql. The current driving buffer circuit 24 is constructed to deactivate, or switch-off, the power transistor Ql without the aforedescri¬ bed problem occurring. The circuit is also constructed to activate the power transistor. The first inverting circuit Q3, Q4 has an input 42 connected to the input 34 of the buffer circuit for receiving the buffer input signal INLSB, and an output 44 on which a first inverted signal Nl, corresponding to the buffer output signal OUTLSB, is delivered. The output 44 of the first inverting circuit Q3, Q4 is thus connected to the output 36 of the current driving buffer circuit. The second inverting circuit Q5, Q6 has an input 46 connected to the input 34 of the buffer circuit for receiving the buffer input signal INLSB, and an output 48 on which a second inverted signal N2 is delivered. The output 48 of the second inverting circuit Q5, Q6 is connected to an input 50 of the Darlington circuit Q7, Q8 and also to an input 52 on the semiconductor element Q9. The Darlington circuit Q7, Q8 has an output 54 connected to the output 36 of the current driving buffer circuit. The semiconductor element Q9 also has an output 56 connected to the buffer circuit output 36. As earlier mentioned, the output 36 of the current driving buffer circuit is connected to the control input Gl (G-connection) on the power transistor, represented in the Figure by the two capacitances C GSQ1 , C^ g .,. The inductive load 12 is also shown in the Figure. The first inverting circuit Q3, Q4 includes a third FET- transistor Q3 and a fourth FET-transistor Q4. The third FET- transistor Q3 is an n-channel type transistor and the G- connection G3 is connected to the input 42 of the first inverter. The D-connection D3 is connected to the output 44 of the first inverter and the S-connection S3 is connected to the positive terminal on the third voltage generator V3 for receiving the potential VREG. The fourth FET-transistor Q4 is a p-channel type transistor and the G-connection G4 is connected to the input 42 of the first inverter. The D- connection D4 is connected to the output 44 of the first inverter and the S-connection S4 is connected to the positive terminal on the voltage generator VI for receiving the potential VCCH. The voltage Nl on the output 44 of the first inverting circuit Q3, Q4 thus alternates between the high level VCCH and the low level VREG. The second inverting circuit Q5, Q6 includes a fifth FET- transistor Q5 and a sixth FET-transistor Q6. The fifth FET- transistor Q5 is an n-channel type and the G-connection G5 is connected to the input *46 of the second inverter. The D- connection D5 is connected to the output 48 of the second inverter, and the S-connection S5 is connected to the positive terminal on the third voltage generator V3 for receiving the potential VREG. The sixth FET-transistor Q6 is a p-channel type transistor with the G-connection G6 connected to the input 46 of the second inverter. The D-connection D6 is connected to the output 48 of the second inverter, and the S- connection S6 is connected to the positive terminal on the first voltage generator VI for receiving the potential VCCH. The voltage N2 on the output 48 of the second inverting circuit Q5, Q6 thus alternates between the high level VCCH and the low level VREG. The Darlington circuit Q7, Q8 includes a seventh transistor Q7 which is connected to an eighth transistor Q8. The seventh transistor Q7 is an NBPN bipolar transistor. The base connec¬ tion 50 on the NPN-transistor Q7 forms the input of the Darlington circuit and is connected to the output 48 on the second inverting circuit Q5, Q6. The collector connection C7 on the NPN-transistor Q7 is connected to the positive terminal on the first voltage generator VI for receiving the potential VCCH. The emitter connection E7 on the NPN-transistor is connected to the output 54 of the Darlington circuit via a first resistor RI. The eighth transistor Q8 is also an NPN bipolar transistor. Its base connection B8 is connected to the emitter connection E7 on the seventh transistor Q7. The collector connection C8 is connected to the plus terminal on the first voltage generator VI, whereas the emitter is connected to the output 54 of the Darlington stage. The semiconductor element Q9 is a ninth transistor and is of the P-channel FET type. The G-connection G9 of the ninth transistor forms its input 52, while the S-connection S9 forms its output 56. The D-connection D9 is connected to the positive terminal on the third voltage generator V3 for receiving the potential VREG. A zener diode Z is connected between the output 36 on the current driving buffer circuit 24 and the positive terminal on the first voltage generator VI. The function of the zener diode is to protect the transistors in the Darlington stage and the fourth FET-transistor from destruction when the voltage reduction transistor Q2 is switched off. Any current that may occur is led through the zener diode instead. The zener diode blocks the voltage OUTLSB on the input Gl and prevents the voltage from becoming too highwhen switching off the power transistor Ql. If no zener diode was provided, the voltage on the input of the power transistor Ql could rise to twice the supply voltage VCCH, possibly resulting in current being conducted in the wrong direction through the Darlington transistors. Figure 3 is a flow schematic which illustrates a method according to the invention, while Figure 4 shows signals that occur in the inventive arrangement. The manner in which the arrangement operates will now be described with reference to Figures 3 and 4. The manner in which the current driving buffer circuit operates when switching off the power transis¬ tor will be described with reference to Figure 2a, while the manner in which the buffer circuit operates when activating the transistor is described with reference to Figure 2b. Shown uppermost in the signal diagram in Figure 4 is the control signal INI and its repetitive pulses. The time point t, in the signal diagram can be considered as a starting point from which the inventive method can be described. In the starting position 58 in Figure 3, the power transistor Ql is switched on, which is illustrated in the signal diagram by the buffer input signal INLSB having the high level VCCH and the buffer output signal OUTLSB having the low level VREG, wherein the power transistor Ql supplies the output 16 with the high voltage level VCCH. The output voltage OUT thus has the high voltage level VCCH. The power transistor Ql leads a loading current I L through the inductive load 12. A first switching A of the control signal INI takes place at time point t 2 , whereupon the voltage level of the control signal is changed from the high voltage level VLS to the low level 0 V. This event is represented by a block 60 in the flow sheet of Figure 3. Corresponding switching E takes place in the level shifting circuit LS, so as to switch the buffer input signal INLSB from the high voltage level VCCH to the low voltage level VREG, therewith causing the current driving buffer circuit 24 to switch the buffer output signal OUTLSB to an inactivating level VCCH. The buffer input signal INLSB is inverted in the first inverting circuit Q3, Q4 and in the second inverting circuit Q5, Q6, wherein the first inverting signal Nl and the second inverting signal N2 are switched to the high level VCCH (not shown in Figure 4) . Switching of the inverted signals Nl, N2, however, does not take place instan¬ taneously and neither simultaneously. The second inverting signal is switched more quickly to the high level VCCH, meaning that the Darlington stage will obtain sufficient base voltage to generate a main deactivation current I 07 Q8 which charges the capacitances C GSQ1 , C^ g , in the power transistor Ql so that the buffer output signal OUTLSB rises to a deac¬ tivation limit level DIS liπ) , wherein the power transistor Ql is switched off. As a result of this first switching A of the control signal INI at time point t 2 , there is generated in the current driving buffer circuit a deactivation current I 0IS which is comprised of said main deactivation current I Q708 and an additional deactivation current I Q4 , in accordance with block 64 in the flow sheet. The main deactivation current I Q7 ^ is generated in the Darlington circuit Q7, Q8 when the second inverting circuit Q5, Q6 delivers a base current I B7 to the input 50 of the Darlington circuit, this base current I B7 being generated in the sixth transistor Q6 when the second inverting signal N2 on the Darlington circuit input 50 is switched to the high voltage level VCCH. The main deactivation current I Q708 , which is roughly equally as large as the inductive loading current I L at the moment of deactivation, is comprised of the total current generated in the Darlington circuit transistors Q7, Q8. The main deactivation current I Q7 M is delivered to the input Gl on the power transistor Ql so as to rapidly discharge the first capacitance C GSQ1 so that the voltage OUTLSB on the input Gl will rise to a sufficiently high level to deactivate the transistor Ql, as shown in block 66 of the flow sheet. The main deactivation current is so large that the voltage OUTLSB on the input Gl will rise above a limit level DIS UlI| . The power transistor Ql is definitely switched off above the limit level DIS lim . As a result of the charge supplied to the first capacitance C GSQ1 by the main deactivation current I Q7Q8 , the voltage on the input Gl increases to a deactivation range DIS liπι <θUTLSB<VCCH in which the power transistor Ql is defini¬ tely switched off. The main deactivation current I Q7 Q8 con¬ tinues to supply charge to the input Gl until the output voltage OUT has fallen to 0 V. The main deactivation current also charges up the second capacitance C^ g , to the voltage VCCH. In order for the Darlington circuit Q7, Q8 to be able to conduct the main deactivation current, it is necessary for the circuit to have a sufficient base voltage U B7 + U^ « 1.6 V. When the voltage OUTLSB has risen above the high supply voltage minus the base voltage for conducting so that the base voltage U B7 + U^ is lower than 1.6 V, the Darlington circuit Q7, Q8 ceases to conduct current. Further discharge of the first capacitance C GSQ1 , such that the voltage OUTLSB on the input Gl increases right up to the deactivation level VCCH, is effected with the additional deactivation current I w that is generated in the fourth transistor Q4 in the first inverting circuit when the buffer input signal INLSB has the low value VREG. In summary, the Darlington circuit Q7, Q8 requires both the aforesaid base current I B7 and the aforesaid base voltage U B7 + U B8 in order to generate the main deactivation current. In accordance with the earlier description, it is the coaction between the two inverting circuits that creates the base voltage required by the Darlington circuit to generate current. This coaction is achieved, by switching the inverting circuits with a given time shift. The total deactivation current I DIS is illustrated in the signal diagram with a current peak at time point t 2 . The procedure involving the discharge of the first capacitance C Gsa1 and the charging of the second capacitance C GDQ1 thus takes place very rapidly so that the voltage OUTLSB deactivates the power transistor Ql in a stable manner. The described proce¬ dure of charging the capacitances in the power transistor Ql with deactivation current I D1S is included in block 66 in the flow sheet. Upon completion of the deactivation procedure and the power transistor Ql, which is the power transistor in the push-pull final stage, is therewith switched off, the voltage reduction transistor Q2 is switched on by switching the switching signal OUTBUFF to the logic voltage level VLS. The switching signal OUTBUFF is generated in the simpler buffer circuit BUFF. Switching to the logic voltage VLS at time point t 2+ , im¬ mediately after switching-off the drive transistor Ql, is generated by delaying the switching signal OUTBUFF. When the voltage reduction transistor Q2 is switched on, the load 12 is supplied with the low supply voltage 0 V, so that the output voltage OUT has a low level, 0 V. The inductive loading current I L is led through the voltage reduction transistor Q2 in a direction away from the load 12 of the transistor Q2. The current driving buffer circuit 24 is also constructed to activate the power transistor Ql. However, the voltage redu¬ ction transistor Q2 is switched off immediately prior to activating the power transistor Ql, by switching the buffer output signal OUTBUFF to the low voltage value 0 V at time point t 3 _. When the voltage reduction transistor Q2 is switched off, the inductive load 12 causes the output voltage OUT to change its level to the high supply voltage VCCH very quickly, so that the energy in the load L can be discharged via the first diode Dl in the power transistor Ql. During this discharge procedure, the voltage OUT on the output rises up to one volt above the high level VCCH, so that the first diode is able to conduct current. According to the earlier description, thebuffer output signal OUTBUFF is switched at the time points t 2+ and t 3 _ so that deactivation of the voltage reduction transistor Q2 takes place after the power transistor Ql has been switched off, and so that the power transistor Ql is switched on after having switched off the voltage reduction transistor. The manner in which this activation delay is achieved in practice will be described in detail with reference to Figures 6 and 7. When deactivation of the voltage reduction transistor Q2 is terminated and the output voltage OUT has the high level VCCH, there is commenced a procedure for activating the power transistor Ql. This activation procedure is initiated by a second switching B, at time point t 3 , of the control signal INI, as shown in block 68 in the flow sheet. In this way, there is generated in the level-shifting circuit 22 a corresponding first switching F of the buffer input signal INLSB to the high level VCCH, wherein the first inverted signal Nl and the second inverted signal N2 are switched to the low level VREG. The inverted signals Nl, N2, however, are not switched instantaneously and neither simultaneously, since the input capacitance on the ninth transistor Q9 is charged-up more rapidly than the input capacitance of the first transistor Ql. The first transistor Ql has a much larger input capacitance than the ninth transistor Q9. By the input capacitance is meant both the capacitance between the G-connection and the D- connection and between the G-connection and the S-connection on respective transistors. This more rapid charging of the capacitance in the ninth transistor Q9 results in a voltage difference between the G-connection G9 and the S-connection S9 of the ninth transistor. This voltage difference is sufficiently large for the ninth transistor Q9 to generate and conduct a main activation current I Q9 , which charges-up the first capacitance C GS01 and the second capacitance C GDQ1 in the power transistor Ql, until the voltage OUTLSB on its input Gl has fallen to beneath a limit level CON in at which the power transistor Ql is switched on. The main activation current I Q9 ceases when the voltage OUTLSB on the output 56 of the ninth transistor has fallen to such a low level as to lie within an activation range VREG<OUTLSB<CON Uli for the power transistor Ql. In this state, the power transistor Ql is switched on and leads the inductive loading current I L through the load 12. The buffer input signal INLSB has the high voltage level VCCH during this activation procedure, wherein the third transis¬ tor Q3 in the first inverting circuit generates and conducts an additional activation current I Q3 . This additional ac¬ tivation current 1^ is utilized to further charge the capaci- tances in the power transistor Ql, so that the voltage level OUTLSB on the input Gl will fall right down to a power transistor activating level VREG. The voltage level OUTLSB is stabilized on the activation level VREG until the next time that the power transistor Ql is switched off. Thus, there is generated in total an activation current I C0N which is comprised of the main activation current I Q9 and the additional activation current I Q3 in accordance with block 70 of the flow sheet. As before mentioned, the activation current 1^ charges the capacitances in the power transistor Ql, so that the voltage on its input Gl will fall to the activation, level VREG, whereby the transistor is switched on in accordance with block 72 of the flow sheet shown in Figure 3. The activation current I cai which charges the capacitances in the power transistor Ql is illustrated in the signal diagram in Figure 4. The aforedescribed procedure illustrates how the current driving buffer circuit 24 deactivates and activates the power transistor Ql in response to the control signal INI. Figure 5 is a block schematic which illustrates a second embodiment of a voltage alternating drive arrangement according to the invention. The drive arrangement includes a simple final stage 74 connected to the inductive load 12 and a second control circuit 76 connected to the final stage. The simple final stage 74 includes only one transistor, the power transistor Ql. Instead of thevoltage reduction transis- tor in the push-pull final stage of the Figure 1 embodiment, a third diode D3 is connected in the simple final stage. The power transistorCΛ is connected in the simple final stage in the same manner as in the push-pull final stage. The third diode D3 is connected between the earth connection and the D- connection on the power transistor Ql. The output 16 of the simple final stage is connected to the D-connection on the power transistor Ql. The third diode D3 is connected so as to conduct current in a direction away from earth to the final stage output 16. The control circuit 76 of the Figure 5 embodiment corresponds to the control circuit of the Figure 1 embodiment, with the exception that it includes only those circuits CL, LS, LSB that are connected to the power transistor Ql. The clock circuit CL, the level-shifting circuit LS and the current driving buffer circuit LSB function in the same manner as that earlier described. Deactivation of the power transistor Ql in the simple final stage takes place in the same way as the deactivation of the power transistor in the push-pull final stage. The current driving buffer circuit operates in precisely the same manner, wherewith the deactivation procedure described earlier with reference to the signal diagram of Figure 4 also applies to this simple final stage. When switching off the power transistor Ql, the output voltage OUT falls very rapidly beneath 0 V, so that the third diode D3 is able to conduct the inductive current I L for draining the energy stored in the inductive load 12. When the energy is drained, the third diode D3 will cease to conduct current and the output voltage OUT will be 0 V. When it is again time to activate the power transistor, at time point t 3 in the signal diagram of Figure 4, it is necessary for the power transistor Ql to "pull" the output 16 high. Thus, in the case of the simple final stage 24, switching of the voltage OUT on the output 16 to the high level VCCH is effected by activation of the power transistor Ql. (In the case of the push-pull final stage, the voltage OUT was already switched when switching off the voltage reduction transistor Q2.) Upon activation of the power transistor Ql in the simple push-pull final stage 24, the current driving buffer circuit 24 operates in almost exactly the same manner as that earlier described. However, the activating current I cat results in a high discharge of the second capacitance C^ g ,, since the potential of the output 16 must be changed from 0 V to VCCH when the power transistor Ql is switched on. The loading current through the power transis¬ tor Ql also assists in changing the voltage on the output. There now follows a short summary of the method according to the flow sheet in Figure 3. According to block 58, the starting point taken is when the control signal INI has the high voltage level VLS and the buffer output signal OUTLSB has the low voltage level VREG, wherein the power transistor Ql is switched on. A first method step, described in block 60, involves first switching A of the control signal INI to the low voltage level 0 V. This first switching A of the control signal initiates deactivation of the power transistor Ql. A second method step, described in block 64, involves genera- ting a deactivation current I DIS for switching off the power transistor Ql. The deactivation current I DIS is comprised of said main deactivation current I Q7 ∞ and of the additional deactivation current I w . A third method step in accordance with block 66, involves delivering the deactivation current I DIS to the power transis¬ tor Ql and charging capacitances in said transistor, wherewith the voltage OUTLSB on the input Gl of the power transistor rises to the high level VCCH, therewith switching off the power transistor Ql. Block 68 describes a fourth method step, which involves a second switching B of the control signal INI, so that its voltage level switches to the higher level VLS and therewith initiates activation of the power transistor Ql. A fifth method step is described in block 70. This fifth method step involves generating an activation current I cai which is comprised of a main activation current I g , and an additional activation current I→^. The last method step according to the flow sheet is described in block 72. This last method step is comprised of charging the capacitances in the power transistor Ql with the addi¬ tional current J- ∞)t . so that the voltage OUTLSB on the input of the transistor falls to the low level VREG, thereby activating the power transistor Ql. Upon completion of the last method step, the procedure is repeated from the first method step in which the control signal is switched to the low level 0 V. Figure 6 illustrates a third embodiment and illustrates how thee inventive current driving buffer circuit can be used in an electric voltage alternating drive arrangement having an inductive load. The arrangement in Figure 6 includes the same push-pull final stage 10 as that in Figure 1. The inductive load 12 and the capacitors C. are the same as those in Figure 1 and are similarly connected to the high supply voltage VCCH. Although the control circuit 78 of the Figure 6 embodiment appears to be different, it has the same superordinate function of alternating activation and deactivation of the driving and the voltage reduction transistor, so that the load 12 will be supplied alternately with the voltage VCCH and the voltage 0 V. In addition to the current driving buffer circuit 24, the control circuit 78 also includes a number of circuits which function to achieve activation of the power transistor Ql immediately after the voltage reduction transistor Q2 has been switched off, whereas activation ofthevoltage reduction transistor Q2 is effected immediately after having switched off the drive transistor Ql. The arrangement illustrated in Figure 6 is described below. This arrangement is also descri¬ bed in Swedish Patent Application No. SE 9301974-3 with the exception of the current driving buffer circuit. The control circuit 78 includes a clock circuit 20 (CLOCK) for generating a control signal CL which is used to control deactivation of the transistors. The control signal CL in the present embodiment is a clock signal containing periodically repetitive clock pulses of equal length. The edge of one clock pulse is used to control deactivation of the power transistor and the edge of the other clock pulse is used to control deactivation of the voltage reduction transistor. Deac¬ tivation of respective transistors causes the inductive load to change the level of the output voltage OUT, which is utilized in the control circuit. The control signal CL may also include pulses of shorter or longer lengths. The control signal CL is delivered to a first input 80 on a non-overlapping circuit 82, which is constructed to generate a first clock signal CLD and a second clock signal CLU, these clock signals, however, being equal to the control signal CL when the arrangement is operated continuously. The first clock signal CLD is delivered from a first output 84, whereas the second clock signal CLU is delivered from a second output 86. The non-overlapping circuit 82 is utilized to generate the first clock signal CLD during a starting sequence, and the second clock signal CLU is displaced in relation to the control signal CL. The clock circuit 20 in the control equipment 78 thus controls deactivation of the transistors Ql, Q2 in the push-pull final stage 10. The control circuit includes a level sensing circuit 88 which functions to control the activation of the transis¬ tors. The function of the level sensing circuit 88 is to delay activation of the transistors Ql, Q2 such that the power transistor Ql is switched on first when the level of the output voltage has been changed to a high level after having switched off the voltage reduction transistor Q2, and, correspondingly, the voltage reduction transistor Q2 is not switched on until the level of the output voltage has been changed to a low level after having switched off the power transistor Ql. Activation of the transistors is controlled by feeding back the output voltage OUT to the level sensing circuit 88 in the control equipment 78. The level sensing circuit 88 (SENSE) has an input 90 connected to the output 16 of the final stage for sensing the output voltage OUT. The sensing circuit 88 has a first output 92 on which there is delivered a low limit signal OUTL for control¬ ling firing or activation of the voltage reduction transistor Q2. The sensing circuit 88 has a second output 94 on which there is delivered a high limit signal OUTH for controlling firing of the power transistor Ql. The limit signals OUTL, OUTH denote when the output voltage OUT has reached a limit value at which the output voltage OUT is defined as a high voltage or has fallen to a level at which the output voltage is defined as low. A more detailed description of the level sensing circuit 88 is given in Swedish Patent Application No. SE 9301975-0. The control circuit 78 also includes a first switching circuit 96 (PULL DOWN) for switching the voltage reduction transistor Q2 on and off. The first switching circuit 96 receives the low limit signal OUTL from the sensing circuit 88 on a first input 98. The voltage levels of the low limit signal OUTL are adapted to the voltage levels in the first switching circuit 96. The first switching circuit 96 receives said first clock signals CLD on a clock pulse input 100. The first control circuit 96 receives a disabling signal TD so as to temporarily disconnect the influence of the low limit signal OUTL on the first control circuit 96 when starting the control circuit 78. When the control circuit is started, the first clock signal CLD controls both activation and deactivation of the voltage reduction transistor Ql. On an output 104 on the first switching circuit 96, there is delivered a first switching signal DOWNOUT to the input G2 on the voltage reduction transistor in the push-pull final stage 10, for the purpose of switching the voltage reduction transistor Q2 on and off. The control circuit 78 includes a second switching circuit 106 (PULL UP) which controls activation and deactivation of the power transistor Ql. The second switching circuit 106 receives on a first input 108 the high limit signal OUTH from the sensing circuit 88. The voltage levels of the high limit signal OUTH are adapted to the voltage levels in the second switching circuit 106. The second control circuit 106 receives a level adapted second signal CLU LS on a clock pulse input 110. The second control circuit 106 receives a level adapted disabling signal TD LS on a second input 112, so that when starting the control equipment 78 the effect of the high limit signal OUTH on the first switching circuit 30 will be tem¬ porarily taken out. The level adapted signals are adapted to those voltages with which the second switching circuit 106 operates. When starting-up, the level adapted second clock signal CLU LS will thereby control both activation and deac- tivation of the power transistor Ql. A second switching signal UPOUT is delivered on an output 114 on the second switching circuit 106, this signal being used to control the activation and deactivation of the power transistor Ql. For purpose of switching the power transistor Ql on and off, the control circuit 78 also includes the aforesaid current driving buffer circuit 24 and an inverting circuit 116. The inverting circuit 116 is connected between the output 114 on the second switching circuit 104 and the input 34 on the current driving buffer circuit 24. The buffer circuit output 36 is connected to the input Gl on the power transistor Ql in the aforedescribed manner. A first level changing circuit 118 (LS) converts the voltage levels on the second clock signal CLU so that these levels are adapted to those voltage levels with which the second swit- ching circuit 106 operates. The first level changing circuit 118 delivers the level adapted second clock signal CLU LS to the clock pulse input 110 on the second switching circuit 106. The control equipment 78 also includes a disabling circuit 120 (TIMER DISABLE) , which is used to disable the influence of thee sensing circuit 88 on the switching circuits 96, 106 during said starting-up procedure, and also to cause said non- overlapping circuit 82 to generate the first and the second clock signals CLD, CLU displaced in relation to the control signal CL. The disabling circuit 120 delivers the aforesaid disabling signal TD to the second input 102 on the first switching circuit 96. The disabling signal TD is also delive¬ red to a second level changing circuit 122 (LS) which converts the voltage levels of the disabling signal so as to adapt these levels to those levels with which the second switching circuit 106 operates. The level adapted disabling signal TD LS is delivered to the second input 112 on the second switching circuit 106. The disabling signal TD is also delivered finally to a second input 124 on the non-overlapping circuit 82 so as to activate said circuit during the starting-up process. Functioning of a continuously operating drive arrangement according to Figure 6 with the inventive current driving buffer circuit 24 will be described in more detail below with reference to the signal diagram shown in Figure 7. The current driving buffer circuit 24 operates in precisely the same manner as that described with reference to Figures 2, 3 and 4 and will not therefore be repeated in this detailed descrip- tion. The functional description given with reference to Figure 7, however, does include the superordinate function of the buffer circuit 24 in the drive arrangement shown in Figure 6. Uppermost in the signal diagram of Figure 7 is the disabling signal TD. The arrangement operates continuously, KONT, from the time point t 0 . The disabling signal TD will then have a low level and the arrangement operates with feedback of the output voltage OUT to the control equipment 78, which activates the transistors in accordance with the level of the output voltage OUT. When the arrangement operates continuously, the first clock signal CLD and the second clock signal CLU are identical with the control signal CL, as shown in the signal diagram of Figure 7. The control signal CL includes continuously repeti- tive pulses of high level corresponded by the logic voltage VLS. The control signal has a low level corresponding to 0 V between pulses. At time point t→→→→ , the clock signal switches from a low to a high level, which is shown in the Figure by a first pulse edge M. At time point t 13 , the clock signal passes from a high to a low level, which is shown in the Figure by a second pulse edge N. The time duration between two mutually sequential first edges M corresponds to the period T (20 μs) of the control signal CL and the pulses continue during the half period time. The signal diagram of Figure 4 also shows the output voltage OUT. The voltage reduction transistor Q2 is switched on and conducts current between the time points t 0 and t→→→→ , the output voltage being low. The voltage reduction transistor Q2 is switched off at time point t 11# wherewith the current conduc¬ tive load 12 causes the output voltage OUT to be changed from a low to a high level. Deactivation of the voltage reduction transistor is controlled by the first edge M of the clock pulse. The power transistor Ql is switched on at time point t 12 , this activation being controlled by the high limit signal OUTH from the sensing circuit 88. The power transistor Ql is switched off at time point t 13 , wherewith the current conduc- ting load 12 causes the output voltage OUT to be changed from a high to a low level. Deactivation of the power transistor is controlled by the other edge N of the clock pulse. Finally, the voltage reduction transistor Q2 is switched on at time point t 14 , this activation being controlled by the low limit signal OUTL from the sensing circuit 88. The drive arrangement is constructed so that only one of the transistors in the push-pull final stage will be conductive at any one time. This is achieved by causing the inductive load to change the level of the output voltage OUT when switching off respective transistors. The control equipment 78 controls firing of the transistors, such that the power transistor Ql will be switched on after the sink Q2 has been switched off, wherewith the output voltage has been changed from a low to a high level. Correspondingly, thevoltage reduction transistor Q2 is switched on after the power transistor Ql has been switched off, wherewith the output voltage OUT has been changed from a high to a low level. Activation of the power transistor Ql may not take place until the output voltage OUT has increased to a high limit value H, the time point t 12 in the signal diagram for the output voltage OUT, after having switched off the voltage reduction transistor Q2. Activation of the voltage reduction transistor Q2 may not take place until the output voltage OUT has fallen to a low limit value L, the time point t u in the signal diagram for the output voltage OUT, after having switched off the power transistor Ql. Activation of both transistors is controlled by feeding the output voltage OUT back to the sensing circuit 88. The sensing circuit is constructed to control activation of respective transistors such that activation occurs when the output voltage OUT has fallen to beneath the lower limit value L or when the output voltage has risen above the high limit value H, in the aforedescribed manner. The activation and deactivation of the power transistor Ql is effected under the influence of the current driving buffer circuit 24 in the control circuit 78. Shown in the signal diagram of Figure 7 are the low limit signal OUTL and the high limit signal OUTH from the sensing circuit 88, the signals being used to control activation of the two transistors. The limit signals OUTL, OUTH shift from high to low levels at the time point t 12 , when the output voltage OUT reaches the high limit level H after the voltage reduction transistor Q2 has been switched off. The limit signals OUTL, OUTH return to a high level at time point t u , when the output voltage OUT has fallen to the low limit value L after having switched off the power transistor Ql. Also shown in the signal diagram of Figure 7 is the first switching signal DOWNOUT which is delivered from the first switching circuit 96 for switching the voltage reduction transistor Q2 on and off. At time point t 1l# the first edge M of the clock signal CLwill cause the switching signal DOWNOUT to switch to a low level, marked J in the Figure, therewith switching off the voltage reduction transistor. The fact that the low limit signal OUTL shifts to a low level at time point t 12 does not influence the first switching signal DOWNOUT. At time point t 14 , when the output signal OUT has fallen to a low level, there is generated a second level shift F in the low limit signal OUTL which causes the first switching signal DOWNOUT to activate the voltage reduction transistor Q2. The first switching signal DOWNOUT is caused by the low limit signal OUTL to switch from low to high level, marked I in the Figure, therewith activating thevoltage reduction transistor Q2. Activation of the voltage reduction transistor Q2 has thereby been delayed until the output level OUT has fallen to the lower limit value L, after the power transistor Ql has been switched off at time point t 13 . The signal diagram in Figure 7 also shows the buffer input signal INLSB which arrives from the second switching circuit 106 and which is inverted in the inverter 116. In the same manner as that earlier described, the buffer input signal INLSB causes the current driving buffer circuit 24 to activate and deactivate the power transistor Ql. The second flank N of the clock signal CL causes the buffer input signal INLSB to switch to a low level at time point t 13 , this low level being marked P in the Figure. The buffer input signal INLSB from the inverting circuit 116 then switches to the low level VREG, whereupon the current driving buffer circuit deactivates the power transistor Ql in the aforedescribed manner. The fact that the high limit signal OUTH switches to a high level at time point tl4 does not influence the buffer input signal INLSB. At time point t 12 , when the output voltage OUT has increased to a high level, there is generated a first level shift E in the high limit signal OUTH which causes the buffer input signal INLSB to switch to the high level VCCH, marked with K in the Figure, so as to control activation of the power transistor. According to the invention, the buffer input signal INLSB is inverted in the current driving buffer circuit 24, wherewith the falling output signal OUTLSB from the current drivingbuffer circuit 24 activates the powertransis- tor in the aforedescribed manner. Activation of the power transistor is thus delayed, with the control device 78, until the output voltage level OUT has reached the high limit value H, after having switched off the voltage reduction transistor Q2 at the time point t n . In the case of the first embodiment illustrated in Figure 1, the control circuit 14 has been simplified in order to give a clearer description of the current driving buffer circuit 24. The control circuit 78 of the Figure 6 embodiment is more complicated and can be realized in practice. The time referen¬ ces that have been used in Figure 7 for the control circuit 78 in Figure 6 do not fully coincide with the references used in Figure 4 with regard to the control circuit 14 of Figure 1. In Figure 4, the time point at which the power transistor Ql is switched off has been referenced t 2 , whereas the corresponding time point in Figure 7 is referenced t 13 . In Figure 4, the time point at which the power transistor Ql is switched on is referenced t 3 , whereas the corresponding time point in Figure 7 is referenced t 12 . Thus, in the signal diagram of Figure 7 for the continuous operation KONT, it is shown that deactivation of the transis¬ tors is controlled by changes in level of the control signal CL. Activation of the transistors is not controlled by the control signal, but instead by the limit signals OUTL, OUTH in order to delay activation of one transistor, so that this activation will not take place simultaneously with the deactivation of the second transistor in the final stage. This avoids the risk of currentpassing simultaneouslythroughboth transistors. It will be understood that the invention is not limited to the aforedescribed and illustrated exemplifying embodiments thereof, and that modifications can be made within the scope of the following Claims.

Claims: CLAIMS 1. A method relating to a voltage alternating drive arran¬ gement comprising a control circuit and a final stage having at least one transistor (Ql) , for switching on and off the transistor (Ql) alternately with the aid of the control circuit, wherein the final stage has an output (16) which is connected to an inductive load (12) , wherein the method comprises the steps of - switching on the transistor (Ql) , wherein the output (16) of the final stage is connected to a high supply voltage (VCCH) and the transistor (Ql) conducts a loading current (I L ) through the inductive load (12) ; - switching off the transistor (Ql) , wherein the output (16) of the final stage is connected to a low supply voltage (earth) , characterized in that the method comprises the further steps of - initiating deactivation of the transistor (Ql) by a first switching (A) of a control signal in the control circuit; - generating a main deactivation current (I 07 Q8 ) in a current generating circuit (Q 7 , Q 8 ) in the control circuit, said main deactivation current corresponding to the loading current (I L ) through the inductive load (12) ; and - delivering the main deactivation current (I Q708 ) to a control input (Gl) on the transistor (Ql) so as to discharge very rapidly a first capacitance (C GS01 ) in the transistor (Ql) , whereby the voltage level (OUTLSB) on the input (Gl) of the transistor is switched to a deactivation interval (DI- S liιn <OUTLSB<VCCH) , therewith switching off the transistor (Ql). 2. A method according to Claim l, characterized in that generation of themain deactivation current (I Q7 Q8 ) is achieved by the steps of - generating a base voltage (U^+U gg ) by the coaction between a first and a second inverting circuit (Q3, Q4, Q5, Q6) at a first switching (A) of a control signal in the control circuit; - generating a base current (I B7 ) in the second inverting circuit (Q5, Q6) at said first switching (A) of the control signal; and - delivering said base voltage (U^+U gg ) and said base current (I B7 ) to the current generating circuit (Q7, Q8) , wherewith said circuit generates the main deactivation current (I Q7 Q8 ) . 3. Amethod according to Claim 1, characterized by the steps of - generating a main activation current (I Q9 ) in the control circuit, generation of said current being initiated by a second switching (B) of the control signal; and charging the first capacitance (C GS01 ) with the main ac¬ tivation current (I Q ,) SO that the voltage level (OUTLSB) on the control input (Gl) of the transistor (Ql) is switched to an activation interval (VREG<OUTLSB<CON lim ) , wherewith the transistor (Ql) is switched on. 4. A method according to Claim 3, characterized by - generating an additional deactivation current (I w ) in order to further drain the first capacitance (C GSQ1 ) in the transis¬ tor (Ql) so that the voltage level (OUTLSB) on the control input (Gl) is stabilized at a deactivation level (VCCH) ; and - generating an additional activation current (I Q3 ) so as to further drain the first capacitance (C GSQ1 ) in the transistor (Ql) so as to stabilize the voltage level (OUTLSB) on the control input (Gl) at an activation level (VREG) . 5. A method relating to a voltage alternating drive arran¬ gement which includes a control circuit and a push-pull final stage having an output (16) connected to a current conducting inductive load (12) , for alternatingly switching on and off a power transistor (Ql) and a voltage reduction transistor (Q2) in the push-pull final stage in response to a control signal delivered via the control circuit, such that the transistors (Ql, Q2) are alternately switched on, said method comprising the steps of - connecting the output (16) of the push-pull final stage to a high supply voltage (VCCH) by activating the power transis¬ tor which when switched on conducts a load current (I L ) through the inductive load (12) ; - connecting the output (16) of the push-pull final stage to a low supply voltage (earth) , by activation of the voltage reduction transistor (Q2) ; - switching the voltage level (OUTLSB) on an input (Gl) of the power transistor (Ql) for switching the transistor on and off, characterized by the further steps of - initiating deactivation of the power transistor (Ql) by a first switching (A) of the control signal; - generating a main deactivation current (I Q7 Q8 ) in the control circuit, this main deactivation current corresponding to the load current (I L ) through the inductive load (12) ; - delivering the main deactivation current (I Q7 Q8 ) to the control input (Gl) of the power transistor (Ql) so that a first capacitance (C GSQ1 ) in the power transistor (Ql) is discharged very rapidly at the same time as a second capaci¬ tance (C gpg ,) in the power transistor (Ql) is charged very rapidly, whereby the voltage level (OUTLSB) on the input (Gl) of the power transistor is switched to a deactivation interval (DIS Um <OUTLSB<VCCH) , thereby activating the power transistor (Ql) ; - generating an activation current (I C0H ) . in the control circuit (LS, LSB) by a second switching (B) of the control signal (INI) ; and - charging the first capacitance (C^,) with the activation current (I C0H ) so that the voltage level (OUTLSB) on the control input (Gl) of the power transistor is switched to an activation interval (VREG<OUTI-SB<CON lJq) ) , thereby activating the power transistor (Ql) . 6. A method according to Claim 5, characterized by generating an additional deactivation current (I w ) for further draining the first capacitance (C GS01 ) in the power transistor, so as to stabilize the voltage level (OUTLSB) on the control input (Gl) at a deactivation level (VCCH) . 7. A method according to Claim 5, characterized by generat¬ ing an additional activation current (1^) for further charging the first capacitance (C GSQ1 ) in the power transistor, so as to stabilize the voltage level (OUTLSB) on the control input (Gl) at an activation level (VREG) . 8. An electric voltage alternating drive arrangement comprising a final stage and an electric control circuit, said final stage including a transistor (Ql) which is connected to an inductive load (12) and to the control circuit, wherein the control circuit includes a current driving buffer circuit (LSB) which is constructed to alternately activate and deactivate the transistor (Ql) in response to a control signal (INLSB) , wherein when in its switched on state the transistor (Ql) connects the output (16) of the final stage to a high supplyvoltage (VCCH) , whereas the output (16) is connected to a low supply voltage (earth) when the transistor (Ql) is switched off, and wherein the control signal (INLSB) when switched to a first position (E) controls deactivation of the transistor (Ql) , and when switched to a second position (F) controls activation of the transistor (Ql) , characterized in that the current drivingbuffer circuit (LSB) includes - an input (34) which receives the control signal (INLSB) ; an output (36) which delivers a buffer output signal (OUTLSB) to a control input (Gl) of the transistor (Ql) ; - a first inverting circuit (Q3, Q4) which is connected to the input (34) and constructed to deliver a first inverted signal (Nl) on an output (44) ; - a second inverting circuit (Q5, Q6) which is connected to the input (34) and constructed to deliver a second inverted signal (N2) on an output (48) ; and - a current generating circuit (Q7, Q8) which is connected to the output (36) on the current driving buffer circuit (LSB) and is also connected to the output (44) on the first inver- ting circuit and to the output (48) on the second inverting circuit, wherein the current generating circuit is construc¬ ted to receive said inverted signals (Nl, N2) upon the first switching (E) of the control signal (INLSB) and therewith generate amain deactivation current (I Q7 M ) which is delivered to the output (36) ; and wherein capacitances (C GSQ1 , C,^) in the power transistor (Ql) are charged so that the buffer output signal (OUTLSB) will increase to a deactivation interval (DIS ljπι <OUTLSB<VCCH) , thereby switching off the power transistor (Ql) . 9. An arrangement according to Claim 8, characterized in that the second inverting circuit (Q5, Q6) connected to the current generating circuit (Q7, Q8) is constructed to deliver a base current (I b7 ) to the current generating circuit on the occurrence of said first switching (E) of the control signal (INLSB) , for initiating generation of said main deactivation current (I 07|Q8 ) . 10. An arrangement according to Claim 9, characterized in that the current driving buffer circuit (LSB) also includes - a semiconductor element (Q9) which is connected to the two outputs (44, 48) on the inverting circuits and is constructed to receive the inverted buffer input signals (Nl, N2) upon the occurrence of said second switching (F) of the control signal (INLSB) and therewith generate a main activation current (I Q9 ) which charges said capacitances (C GSQ1 , C^^) in the transistor (Ql) so that the buffer output signal (OUTLSB) is switched to an activation interval (CON lJrn >OUTLSB>VREG) for activating the transistor (Ql) . 11. An arrangement according to Claim 10, characterized in that the first inverting circuit (Q3, Q4) is also constructed to generate an additional deactivation current (I w ) upon deactivation of the transistor (Ql) , so as to further charge the capacitances (C GS01 , C^ g ,) in the transistor and therewith stabilize the buffer output signal (OUTLSB) at a deactivation level (VCCH) . 12. An arrangement according to Claim 10, characterized in that the first inverting circuit (Q3, Q4) is also constructed to generate an additional activation current (I Q3 ) upon activation of the transistor (Ql) so as to further charge the capacitances (C GSQ1 , C^ g ,) in the transistor and therewith stabilize the buffer output signal (OUTLSB) at an activation level (VREG) . 13. An arrangement according to Claim 10, characterized in that the first inverting circuit (A3, A4) is a C-MOS inverter. 14. An arrangement according to Claim 10, characterized in that the second inverting circuit (Q3, Q4) is a C-MOS in¬ verter. 15. An arrangement according to Claim 10, characterized in that the current generating circuit (Q7, Q8) includes a first bipolar transistor (Q7) of the NPN type connected to a second NPN type bipolar transistor (Q8) . 16. An arrangement according to Claim 10, characterized in that the semiconductor element (Q9) is a p-channel MOS- transistor. 17. An electric current buffer circuit (LSB) for switching on and off a power transistor in response to a buffer input signal (INLSB) a power transistor (Ql) in a push-pull final stage (10) having an output (16) connected to a current conducting inductive load, wherein the power transistor (Ql) in the push-pull final stage is connected to a voltage reduction transistor (Q2) , wherein the connection between the two transistors is comprised of said output (16) , and wherein the transistors are switched on and off alternately, and wherein when switching off the power transistor (Ql) an output voltage (OUT) on the output (2) of the push-pull final stage falls, and wherein the voltage reduction transistor is switched on and connects the output of the push-pull final stage to a low supply voltage (earth) , and wherein when the voltage reduction transistor (Q2) is switched off, thevoltage on the output of the push-pull final stage increases, there¬ with activating the powertransistor and connecting the output of the push-pull final stage to a high supply voltage (VCCH) , characterized in that the current drivingbuffer circuit (LSB) includes - an input (34) for receiving the buffer input signal (INLSB) , which controls the deactivation of the powertransis¬ tor (Ql) through a first switching (E) and controls the activation of said power transistor (Ql) with a second switching (F) ; - an output (36) from which a buffer output signal (OUTLSB) is delivered to an input (Gl) on the power transistor (Ql) ; - a first inverting circuit (Q3, Q4) which inverts the received buffer input signal (OUTLSB) and delivers a first inverted signal (Nl) ; - a second inverting circuit (Q5, Q6) which receives the buffer input signal (INLSB) and delivers a second inverted signal (N2) ; - a current generating circuit (Q7, Q8) which is connected to the output (36) on the buffer circuit and is also connected to said inverting circuits for receiving the first and the second inverted signal (Nl, N2) , said current generating circuit upon said first switching (E) of the buffer input signal (INLSB) is constructed to deliver a main deactivation current (I Q7Q8 ) to the output (36) for charging capacitances (C CSQ1 , C^ g ,) in the power transistor (Ql) so that the buffer output signal (OUTLSB) will increase to a deactivation interval (DIS liπ) >OUTLSB<VCCH) , thereby switching off the power transis¬ tor; and a semiconductor element (Q9) which is connected to the first and the second inverting circuits and which is con¬ structed to deliver a main activation current (I Q9 ) to the output (36) on the occurrence of the second switching (F) of the buffer input signal (INLSB) , so as to charge said capaci¬ tances (C GSQ1 , C gj ,) in the power transistor (Ql) and therewith switch the buffer output signal (OUTLSB) at least to one limit level (CON lirn ) for activation of the power transistor (Ql) , therewith activating said power transistor. 18. An arrangement according to Claim 17, characterized in that the first inverting circuit (Q3, Q4) is also constructed to generate an additional deactivation current (I 04 ) upon deactivation of the power transistor (Ql) , so as to further charge the capacitances (C GSQ1 , C gpg .,) in the power transistor and therewith stabilize the buffer output signal (OUTLSB) at a deactivation level (VCCH) . 19. An arrangement according to Claim 17, characterized in that the first inverting circuit (Q3, Q4) is also constructed to generate an additional activation current (I^) upon activation of the power transistor (Ql) so as to further charge the capacitances (C GSQ1 , C^ Q →→ ) in the driving transistor and therewith stabilize the buffer output signal (OUTLSB) at an activation level (VREG) . 20. An arrangement according to Claim 17, characterized in that the second inverting circuit (Q5, Q6) , which is connected to the current generating circuit (Q7, Q8) , is constructed to deliver a base current (I b7 ) to the current generating circuit upon said first switching (E) of the control signal (INLSB) , so as to initiate the generation of said main deactivation current (I Q7#08 ) . 21. An arrangement according to Claim 17, characterized in that the current generating circuit (Q7, Q8) is a Darlington circuit. 22. An arrangement according to Claim 17, characterized in that the current generating circuit (Q7, Q8) includes a first NPN-type bipolar transistor (Q7) which is connected to a second NPN-type bipolar transistor (Q8) . 23. An arrangement according to Claim 17, characterized in that the semiconductor element (Q9) is a p-channel MOS- transistor. 24. An electric voltage alternating drive arrangement which includes a current conducting inductive load andwhich further includes a push-pull final stage (Ql, Q2) connected to the inductive load (12) and an electric control circuit which is connected to the final stage and which is switched on by a control signal (INI) , said push-pull final stage being characterized in that it includes a power transistor (Ql) connected to a voltage reduction transistor (Q2) , said transistors being connected between a positive terminal and a negative terminal on a first voltage generator (VI) , wherein the connection between the transistors is comprised of a final stage output (16) , wherein the inductive load (12) is con¬ nected between the final stage output (16) and a connection (18) on a voltage source (Cl, VI) , wherein the control circuit is connected to a first input (Gl) on the final stage and to a second input (G2) on said final stage for alternately switching the transistors (Ql, Q2) on and off so that the output voltage (OUT) on the final stage output will alternate between the high voltage (VCCH) on the positive terminal of the voltage generator (VI) and the low voltage (earth) on the negative terminal of the voltage generator, wherein the level of the output voltage is high (VCCH) when the power transistor (Ql) is switched on, and is low (earth) when the voltage reduction transistor (Q2) is switched on, wherein the control circuit includes a current driving buffer circuit (LSB) for switching the power transistor (Ql) on and off, and wherein the control circuit is constructed to generate a buffer input signal (INLSB) and deliver said signal to the current driving buffer circuit (LSB) , characterized in that said current driving buffer circuit (LSB) includes - an input (34) on which the buffer input signal (INLSB) is received, wherein a first switching (E) of the input signal controls deactivation of the power transistor (Ql) , and wherein a second switching (F) of said input signal controls the activation of the power transistor; an output (36) which delivers a buffer output signal (OUTLSB) to an input (Gl) on the power transistor (Ql) ; a first inverting circuit (Q3, Q4) which inverts the received buffer input signal (INLSB) and delivers a first inverted signal (Nl) ; - a second inverting circuit (Q5, Q6) which receives the buffer input signal (INLSB) and delivers a second inverted signal (N2) ; a current generating circuit (Q7, Q8) connected to said inverting circuits and receiving the first and the second inverted signal (Nl, N2) , wherein the current generating circuit is constructed to generate a main deactivation current (I Q7Q8 ) in response to the first switching (E) of the buffer input signal (INLSB) , said deactivation current charging capacitances (C GSQ1 , C^ g ,) in the power transistor (Ql) so that the buffer output signal (OUTLSB) will increase to a deac- tivation interval (DIS liπ >OUTLSB<VCCH) , thereby switching off the power transistor; and - a semiconductor element (Q9) which is connected to the first and the second inverting circuit and which is con¬ structed to generate a main activation current (I Q ) in response to the second switching (F) of the buffer input signal (INLSB) so as to charge said capacitances (C GSQ1 , C GDQ1 ) in the power transistor (Ql) and therewith switch the buffer output signal (OUTLSB) at least to a limit level (CON l |n ) for activation of the power transistor (Ql) , therewith activating said power transistor. 25. An arrangement according to Claim 24, characterized in that the first inverting circuit (Q3, Q4) is also constructed to generate an additional deactivation current (I Q4 ) upon deactivation of the power transistor (Ql) , so as to further charge the capacitances (C GSQ1 , C→^^→- ) in the power transistor and therewith stabilize the buffer output signal (OUTLSB) at a deactivation level (VCCH) . 26. An arrangement according to Claim 24, characterized in that the first inverting circuit (Q3, Q4) is also constructed to generate an additional activation current (I Q3 ) upon activation of the power transistor (Ql) , so as to further charge the capacitances (C GSQ1 , C^.,) in the power transistor and therewith stabilize the buffer output signal (OUTLSB) at an activation level (VREG) . 27. An arrangement according to Claim 24, characterized in that the first inverting circuit (Q3, Q4) is a C-MOS inverter. 28. An arrangement according to Claim 24, characterized in that the second inverting circuit (Q5, Q6) is a C-MOS in¬ verter. 29. An arrangement according to Claim 24, characterized in that the current generating circuit (Q7, Q8) includes a first NPN-type bipolar transistor (Q7) which is connected to a second NPN-type bipolar transistor (Q8) . 30. An arrangement according to Claim 24, characterized in that the semiconductor element (Q9) is a p-channel MOS- transistor. 31. An electric current driving buffer circuit (24) for switching on and off a power transistor (Ql) in a push-pull final stage (10) connected to an inductive load (12) in response to a buffer input signal (INLSB) , characterized by an input (34) which receives the buffer input signal (INLSB) , wherein a first switching (E) of the buffer input signal controls the deactivation of the powertransistor (Ql) , and a second switching (F) of said input signal controls activation of the power transistor (Ql) ; - an output (36) which delivers a buffer output signal (OUTLSB) to a control input (Gl) on the power transistor (Ql) ; - a first inverting circuit (Q3, Q4) which inverts the received buffer input signal (OUTLSB) and delivers a first inverted buffer input signal (Nl) on an output (44) ; - a second inverting circuit (Q5, Q6) which receives the buffer input signal (INLSB) and delivers a second inverted buffer input signal (N2) on an output (48) ; A current generating circuit (Q7, Q8) connected to the output (36) on the buffer circuit and also connected to the outputs (44, 48) on said inverting circuits for receiving the first and the second inverted signal (Nl, N2), wherein the current generating circuit is constructed to generate a main deactivation current (I Q7 Q8 ) on the occurrence of said first switching (E) of the buffer input signal (INLSB) and to deliver said main deactivation current to the output (36) , wherein the main deactivation current charges capacitances (C GSQ1 , C GDQ1 ) in the power transistor (Ql) so that the buffer output signal (OUTLSB) increases to a deactivation interval (DIS liπ >OUTLSB<VCCH) , therewith switching off the power transistor; - a semiconductor element (Q9) connected to the first and the second inverting circuits, said semiconductor element being constructed to generate a main activation current (I Q9 ) on the occurrence of the second switching (F) of the buffer input signal (INLSB) so as to charge said capacitances (C GSQ1 , C^ g .,) in the power transistor (Ql) so that the buffer output signal (OUTLSB) is switched at least to a limit level (CON ll|n ) for activation of the power transistor (Ql) , therewith activating the power transistor. 32. An electric voltage alternating drive arrangement, characterized by - a final stage which includes a transistor (Ql) and which has an output (16) connected to an inductive load (12) , wherein the transistor is intended to be alternated between a conductive and a non-conductive state; - a current driving buffer circuit (LSB) which is connected to said final stage and which is constructed to alternately activate and deactivate the transistor (Ql) , wherein when switched on the transistor (Ql) connects the final stage output (16) to a high supply voltage (VCCH) , while when the transistor (Ql) is switched off, the output (16) is connected to a low supply voltage (earth) , wherein the current driving buffer circuit includes - an input (34) which receives a buffer input signal (INLSB) , wherein a first switching (E) of the input signal controls the activation of the power transistor (Ql) and a second switching (F) of said input signal controls the activation of the power transistor (Ql) ; an output (36) for delivering a buffer output signal (OUTLSB) to a control input (Gl) on the power transistor (Ql) ; a first inverting circuit (Q3, Q4) which inverts the received buffer input signal (OUTLSB) and delivers a first inverted buffer input signal (Nl) on an output (44) ; a second inverting circuit (Q5, Q6) which receives the buffer input signal (INLSB) and delivers a second inverted buffer input signal (N2) on an output (48) ; - a current generating circuit (Q7, Q8) which is connected to the output (36) of the buffer circuit and also connected to the outputs (44, 48) of said inverting circuits, for receiving the first and the second inverted signal (Nl, N2) , wherein the current generating circuit is constructed to generate a main deactivation current (I 0708 ) on the occurrence of said first switching (E) of the buffer input signal (INLSB) , and to deliver said main deactivation current to the output (36) of the buffer circuit, said main deactivation current charging capacitances (C GSQ1 , C^ g ,) in the power transistor (Ql) so that the buffer output signal (OUTLSB) increases to a deactivation interval (DIS liπι >OUTLSB≤VCCH) , thereby switching off the power transistor; - a semiconductor element (Q9) connected to the first and the second inverting circuit, said semiconductor element being constructed to generate a main activating current (I Q ) upon the occurrence of the second switching (F) of the buffer input signal (INLSB) , so as to charge said capacitances (C GSQ1 , C,^) in the power transistor (Ql) and therewith switch the buffer output signal (OUTLSB) at least to a limit level (C0N Um ) for activation of the power transistor (Ql) , thereby activating the power transistor. 33. A method relating to a voltage alternating drive arran¬ gement for alternately switching on and off a transistor (Ql) in a final stage with the aid of a control circuit, said final stage having an output (16) connected to an inductive load (12), characterized by the steps of - activating the transistor (Ql) , wherein the output (16) of the final stage is connected to a high supply voltage (VCCH) and the transistor (Ql) conducts a load current (I L ) through the inductive load (12) ; - switching off the transistor (Ql) , wherein the output (16) of the final stage is connected to a low supply voltage (earth) ; - effecting a first switching (A) of a control signal (INI) in the control circuit so as to initiate deactivation of the transistor (Ql) ; - generating a main deactivation current (I Q7Q8 ) in a current generating circuit (Q7, Q8) in the control circuit, said main deactivation current corresponding to the load current (I L ) through the inductive load (12) ; and - delivering the main deactivation current (I 07 Q8 ) to a control input (Gl) on the transistor (Ql) so as to discharge very rapidly a first capacitance (C GSQ1 ) in the transistor (Ql) , thereby switching the voltage level (OUTLSB) on the input (Gl) of the transistor to a deactivation interval (DIS l1m <OUTLSB<VCCH) , thereby switching off the transistor (Ql) • 34. A method according to Claim 33, characterized by the steps of - generating a main activation current (I Q9 ) in the control circuit, by effecting a second switching (B) of the control signal (INI) ; and - charging the first capacitance (C GS01 ) with the main ac¬ tivation current (I Q9 ) such as to switch the voltage level (OUTLSB) on the control input of the transistor to an ac¬ tivation interval (VREG<OUTLSB<CON Um ) , therebyactivatingthe transistor (Ql) .

Inventors: CARLSSON MATS LENNART, JANSSON LARS, SVENSSON MATS OLOF, CARLSSON, MATS, LENNART, JANSSON, LARS, SVENSSON, MATS, OLOF
Applicants: CARLSSON MATS LENNART, ERICSSON TELEFON AB L M, JANSSON LARS, SVENSSON MATS OLOF, CARLSSON, MATS, LENNART, JANSSON, LARS, SVENSSON, MATS, OLOF, TELEFONAKTIEBOLAGET LM ERICSSON
Application year: 1995
Main classification: H03K17
IPC codes: H03K17