Limiting and selfuniforming cathode currents through the microtips of a field emission flat panel display

Abstract: A pixel emission current limiting resistance is realized by forming a stack of alternately doped amorphous or polycrystalline silicon layers over the cathodic conductors of a FED driving matrix. The stack of amorphous or polycrystalline silicon layers doped alternately n and p provides at least a reversely biased n/p junction having a leakage current that matches the required level of pixel emission current. The reversely biased junction constitutes a nonlinear series resistance that is quite effective in limiting the emission current through anyone of the microtips that form an individually excitable pixel and which are formed on the uppermost layer of the stack.

Description: This invention relates to a device for limiting and making uniform the current through microtips of a cathodic structure for flat panel displays (FPD) of the field emission type (FED). The continuous evolution towards portable electronic products such as laptop computers, personal organizers, pocket TVs and electronics games, has created an enormous market for monochromatic or color display screens of small dimensions and reduced thickness, having a light-weight and a low dissipation. Especially the first two requirements cannot be met by conventional cathode ray tubes (CRTs). For this reason, among the emerging technologies, let alone those related to liquid-crystal-displays (LCD), flat panel field emission display technology has been receiving increasing attention by the industry. A remarkable research and development work has been carried out in the past few decades on field emission displays (FED) employing a cathode in the form of a flat panel provided with a dense population of emitting microtips co-operating with a grid-like extractor essentially coplanar to the apexes of the microtips. The cathode-grid extractor structure is a source of electrons that are accelerable in a space, evacuated for ensuring an adequate mean free-path, towards a collector (anode) constituted by a thin and transparent conductor film upon which are placed luminescent phosphors excited by the impinging electrons. Emission of electrons is modulately excitable pixel by pixel through a matrix of columns and rows, constituted by parallel strips of said population of microtips and parallel strips of said grid-like extractor, respectively. The fundamental structure of these display systems and the main problems related to the fabrication technology, reliability and durability, as well as those concerning the peculiar way of exciting individual pixels of the display system and various proposed solutions to these problems, are discussed and described in a wealth of publications on these topics. Among the pertinent literature the following publications may be cited: US 5,391,259; Cathey, et al. US 5,387,844; Browning US 5,357,172; Lee, et al. US 5,210,472; Casper, et al. US 5,194,780; Meyer US 5,064,396; Spindt US 4,940,916; Borel, et al. US 4,857,161; Borel, et al. US 3,875,442; Wasa, et al. US 3,812,559; Spindt, et al. US 3,755,704; Spindt, et al. US 3,655,241; Spindt, et al. "Beyond AMLCDs: Field emission displays?", K. Derbyshire, Solid State Technology, Nov. 94; "The state of the Display", F. Dawson, Digital Media, Feb.-Mar. 94; "Competitive Display Technologies", 1993, Stanford Resources, Inc.; "Field-Emission Display Resolution", W. D. Kesling, et al., University of California, SID 93 DIGEST 599-602; "Phosphors For Full-Color Microtips Fluorescent Displays", F. Lévy, R. Meyer, LETI - DOFT - SCMM, IEEE 1991, pages 20-23; "Diamond-based field emission flat panel displays", N. Kumar, H. Schmidt, Solid State Technology , May 1995, pages 71-74; "Electron Field Emission from Amorphic Diamond Thin Films", Chenggang Xle, et al., Microelectronics and Computer Technology Corporation, Austin, TX; University of Texas and Dallas, Richardson, TX; SI Diamond Technology, Inc., Houston, TX; "Field Emission Displays Based on Diamond Thin Films", Natin Kumar, et al:, Microelectronics and Computer Technology Corporation, Austin, TX; Elliot Schlam Associates, Wayside, NJ; SI Diamond Technology, Inc., Houston, TX; "U.S. Display Industry on the Edge", Ken Werner, Contributing Editor, IEEE Spectrum, May 1995; "FEDs: The sound of silence in Japan", OEM Magazine, Apr. 1995, pages 49, 51; "New Structure Si Field Emitter Arrays with low Operation Voltage", K. Koga, et al., 2.1.1, IEDM 94-23. The major advantages of FEDs compared to modern LCDs are: low dissipation; same color quality of traditional CRTs; visibility from any viewing angle. FED technology has developed itself on the basic teachings contained in US Patent No. 3,665,241; 3,755,704 and 3,812,559 of CA. Spindt and in US Patent No. 3,875,442 of K. Wasa, et al.. FED technology connects back to conventional CRT technology, in the sense that light emission occurs in consequence of the excitation of the phosphors deposited on a metallized glass screen bombarded by electrons accelerated in an evacuated space. The main difference consists in the manner in which electrons are emitted and the image is scanned. A concise but thorough account of the state of modern FED technology is included in a publication entitled "Competitive Display Technologies - Flat Information Displays" by Stanford Resources. Inc., Chapter B "Cold Cathode Field Emission Displays". A schematic illustration contained in said publication and giving a comparison between a conventional CRT display and a FED (or FED array) is herein reproduced in Fig. 1. In a traditional CRT there is a single cathode in the form of an electron gun (or a single cathode for each color) and magnetic or electrostatic yokes deflect the electron beam for repeatedly scanning the screen, whereas in a FED the emitting cathode is constituted by a dense population of emission sites distributed more or less uniformly over the display area. Each site is constituted by a microtip electrically excitable by means of a grid-like extractor. This flat cathode-grid assembly is set parallel to the screen, at a relatively short distance from it. The scanning by pixel of the display is performed by sequentially exciting individually addressable groups of microtips by biasing them with an adequate combination of grids and cathode voltages. As shown in Fig. 2, a certain area of the cathode-grid structure containing a plurality of microtips and corresponding to a pixel of the display is sequentially addressed through a driving matrix organized in rows and columns (in the form of sequentially biasable strips, into which the cathode is electrically divided and of sequentially biasable strips into which the grid extractor is electrically divided, respectively). A typical scheme of the driving by pixel of the cathodic structure of a FED is shown in Fig. 3. This figure illustrates the driving scheme of a fragment of nine adjacent pixels through a combination of the sequential row biasing pulses for the three rows R1, R2, R3, relative to a certain bias configuration of the three columns C1, C2 and C3. A typical cross-sectional view of a FED structure is shown in Fig. 4. The microtip cathode plate generally comprises a substrate of an isolating material such as glass, ceramic, silicon (GLASS BACKPLATE), onto which is deposited a low resistivity conductor layer as for example a film of aluminum, niobium, nickel or of a metal alloy (NICKEL ELECTRODE), eventually interposing an adhesion layer for example of silicon (SILICON FILM) between the substrate and the conductor layer. The conductor layer (NICKEL ELECTRODE) is photolithographically patterned into an array of parallel strips each constituting a column of a driving matrix of the display. A dielectric layer, for example of an oxide (SILICON DIOXIDE), is deposited over the patterned conductor layer. A conductor layer (NIOBIUM GATE METAL), from which the grid extractor will be patterned, is deposited over the dielectric layer. The grid structure is eventually defined in parallel strips, normal to the cathode parallel strips (NICKEL ELECTRODE). According to a known technique, microapertures or wells that reach down to the surface of the underlying patterned conductor layer (NICKEL ELECTRODE) are defined and cut through the grid conductor layer (NIOBIUM GATE METAL) and through the underlying dielectric layer (SILICON DIOXIDE). Onto the surface of the conductor layer exposed at the bottom of the "wells", are fabricated microtips (MOLIBDENUM MICROTIPS) that will constitute as many sites of emission of electrons. On the inner face of a glass faceplate of the display is deposited a transparent thin conducting film, for example of a mixed oxide of indium and tin (ITO CONDUCTOR) upon which is deposited a layer of phosphors (monochromatic phosphor or color phosphors) excitable by the electrons accelerated toward the conducting layer (ITO CONDUCTOR) acting as a collector of the electrons emitted by the microtips. Emission that is stimulated by the electric field produced by suitably biasing the grid conductor and the cathode tips. In order to improve color resolution, the realization of a "switched" anodic (collector) structure for separately biasing adjacent strips, each covered with a phosphor of a different basic color, has been suggested in a publication entitled: "Phosphors For Full-Color Microtips Fluorescent Displays" by F. Lévy and R. Mayer, LETI - DOFT - SCMM, Grenoble - Cedex - France. Fabricating processes of microtips cathode plates are described in US Patents No. 4,857,161; 4,940,916; 5,194,780 and 5,391,259. In general there exist a well recognized problem of ensuring an uniform luminance (brightness) of the display that involves a control of the emission current of each single microtip (commonly in the order of several hundreds) that belong to a singularly addressable pixel (area) of the display. While on one hand an intervened reduction of the emission efficiency of single tips is not in itself a cause of failure in view of the fact that each pixel is constituted by a multiplicity of microtips working in parallel, on the other hand, the presence of microtips having an emission efficiency much higher than average is particularly detrimental, because of the following effects: a) screen faults in the form of intensely bright spots; b) (in extreme cases) severe damage to the panel by evaporation of the tip and of the adjoining grid. Essentially the current emitted by each single tip depends on two factors: i) the radius of curvature of the microtip which depends on the fabrication technique; ii) the electric field at the vertex of the microtip that depends on the distance between the tip and the adjoining grid. Both these geometric parameters depend on the process of fabrication and therefore present a certain statistic dispersion (spread). Another problem is tied to the ageing of the display, that is, the reduction of the luminance resulting from a progressive reduction of the phosphors' efficiency. This ageing process is closely connected to the electronic bombardment and therefore tends to become faster in correspondence of bright spots and is generally faster the higher is the initial pixel current. The problem of nonuniformity is well recognized in the literature on the subject and various solutions have so far been put forward. A) External resistors can be connected in series with each column of the display for limiting the maximum current by causing a certain voltage drop. In view of the fact that the microtip current is a rapidly increasing function of the electric field, the effect of this resistance is that of limiting the current swing. However, this solution can only be applied to displays of a limited size because of the delays that are inevitably induced by the combination of the increased series resistance and the column's capacitance. B) The microtips can be fabricated in the form of pillars having a first base layer (plinth) made of a relatively high resistivity material. This solution which is described in the US patent No. 3,789,471, is theoretically very efficient though high currents may cause the explosion of the tip because of a reduced ability to dissipate heat. C) An active element, for example a diode connected JFET or MOSFET can be realized in the substrate, in series with each tip or plurality of tips corresponding to a pixel of the display, as described in the US Patents Nos. 5,210,472; 5,357,172; 5,387,844 and in the patent application No. 08/077,181 (WO 94/14182). However, this approach requires the realization of active elements in the substrate leading to remarkable technological problems and tends to increase markedly the fabrication costs. The document US-A-5162704 describes the exploitation of the reverse biasing of a diode for limiting the current that is extracted from each cathodic micro tip. Diodes or diode-connected JFET are fabricated under the base layer of each micro tip by anisotropic etching of a monocrystalline silicon substrate. D) A resistive layer, usually constituted by a suitably doped amorphous or partially polycrystalline silicon, can be interposed between an underlying conductive layer that defines the columns and the microtips as described in the US Patent No. 4,940,916 and in the publication: "Current limiting of field emitter array cathodes" by K.J. Lee, Un. of Georgia. In this case, the resistance is in series with each group of microtips that form a pixel (thus reducing delay problems) and is constituted by a continuous layer (thus reducing the problems connected to heat dissipation). Even the above mentioned approach is nowadays regarded as the most promising, reserves some drawbacks: i) it is extremely difficult to control the resistivity of amorphous and/or polycrystalline silicon layers because resistivity critically depends on the grain boundary structure and/or on the superficial states of the structure; ii) the electrical resistance of the current path perpendicular to the layer can be insufficient unless the thickness of the resistive layer is markedly increased; iii) in the specific case of microtips obtained by etching a matrix layer of doped amorphous or polycrystalline silicon, as described in the US Patent No. 5,391,259, the resistance will depend critically on the residual thickness of the silicon layer which might present large variations across the surface of the panel. Item ii) has been partially overcome by realizing the cathode in a grating-like form as described in the US Patent No. 5,194,780. This solution however, brings about further complexities to the fabrication process and does not overcome the problems mentioned in i) and iii) above. According to the present invention, it is made possible to realize a current limiting structure that consists essentially of a reversely biased diode junction, having a relatively high intrinsic leakage current, the value of which may be easily controlled during the process of fabrication, in the form of a multilayer or stack that may be eventually patterned in an array of parallel strips defining the columns of the driving matrix of the cathodic structure. Essentially, the invention is based on a controlled deposition of a stack of amorphous and/or polycrystalline silicon layers, preferably by CVD (Chemical Vapor Deposition) and more preferably by PECVD (Plasma Enhanced CVD). The stacked silicon films can be doped directly during their deposition, for instance, by adding to a flow of silane small amounts of arsine or phosphine for obtaining an n-doped polycrystalline or amorphous silicon layer, or small amounts of diborane for obtaining a p-doped amorphous and/or polycrystalline silicon layer. Although other deposition methods may be followed, the PECVD technique offers the advantage of an acceptable deposition speed through keeping relatively low the deposition temperature. Of course, remaining in the realm of the known low temperature doping techniques of amorphous and/or polycrystalline silicon, compatible with the fabrication of a cathode structure on a glass substrate, it is possible to dope a deposited silicon film by ionic implantation according to common techniques. According to a preferred embodiment of this invention, it is possible to alternate the dopant species during the process of deposition by controlling the flow of gases through the reactor by electrovalves so as to realize three alternately p, n, p or n, p, n doped silicon layers. Fundamentally, the scope of the invention is to realize two counteropposed (back to back) junctions in order to have, under any bias condition, always an inversely biased junction that opposes the passage of current through the multilayer (or stack). While such an electric structure, if realized in a monocrystalline silicon would present an extremely high resistance in either bias conditions, in the case of stacked layers of polycrystalline and/or amorphous alternately doped silicon, the presence of grain boundaries and the relatively large coupling area of the superimposed layers, which practically coincides with a pixel's area of the display, determines an intrinsic leakage current having a relatively large value (in the order of hundreds of nA), which is compatible with the emission current requirements of a cathodic structure of a FED. In the context of the present invention, the double junction cannot be realized by a three-layer stack of monocrystalline silicon, but rather with a stack of amorphous silicon layers or in the alternative with partially or even wholly polycrystalline silicon layers. For the object of the invention it is essential that each pin junction have a level of current leakage (under reverse bias conditions) relatively high and compatible with emission current requirements through excitable sites of the cathodic structure as represented by the vertexes of the microtips. The use of substantially amorphous silicon layers is mostly preferred due to the simplicity and cost efficiency of the process for forming such layers. Naturally, the amorphous structure of the silicon layer or, better said, of the stacked silicon layers may also contain granules or regions within which may be present a recognizable crystallographic order of the silicon atoms. Normally, these zones or granules of appreciable crystallinity have dimensions in the order of ten nanometers and the whole structure can be considered substantially amorphous. Alternatively, leakage current of adequate level may be obtained across junctions realized with alternately doped silicon layers, the structure of which may be qualified as partially or completely polycrystalline. In practice, there is no clear distinction between the amorphous and polycrystalline phases, because this distinction will depend on the applicable structural parameter limits according to certain classification criteria. However, both the amorphous and polycrystalline phases clearly differ from a monocrystalline phase being the latter substantially free of a recognizable granular structure, that is presenting boundary zones between adjacent grains characterized by a strongly distorted lattice. It is the presence of either a total lattice misarrangement typical of an amorphous structure or a substantial lattice disarrangement, typical of a polycrystalline structure, that determines relatively high leakage currents and therefore compatible with the requirements of a cathodic emission current through excited pixels of the display. For these reasons, when referring to a polycrystalline (or microcrystalline) and/or amorphous structure of the silicon layers, it is intended to highlight these essential characteristics of silicon layers with which the two back-to-back p/n junctions are realized. Together, the two back-to-back junctions realized by the stack of alternately doped layer, have an electric behavior that may be regarded as equivalent to that of a nonlinear resistance of a relatively high value. An advantageous aspect of the structure is that the resistance does not depend on the thickness of the stacked layers, and, at least in first approximation, neither on the doping level of the layers. These peculiarities are of fundamental importance as they permit a great freedom in modulating the lateral resistance of the upper layer of the stack onto which the microtips are eventually fabricated, in function of the nonlinear resistance across the stack that is determined by the "double junction". Moreover, the microcrystalline and/or amorphous structure of the doped silicon layers that are alternately doped overlaid and that produce the "double" or back-to-back junction can be easily controlled by suitably adjusting the conditions of the deposition process. This permits to attain the desired levels of leakage current, to meet the requirements and conditions of pixel's emission. In practice, the cathode structure of the present invention realizes a distinct resistance in series to the groups or array of microtips belonging to each pixel of the display. The value of this series resistance is easily controllable in the fabrication process without the need to use a more complex and costly grating-like architecture as the one described in the US Patent No. 5,194,780 which implies an additional step of photolithography. Figure 1 is a general comparative scheme between a conventional CRT display device and a field emission flat array display device (FED); Figure 2 shows the general architecture of a FED device and of the relative driving circuitry; Figure 3 is an illustration of how every single pixel of a FED device is driven; Figure 4 is a schematic cross sectional illustration of the structure of a FED device: Figure 5 shows the microsection of a cathodic structure made according to this invention; Figures 6a and 6b compare the electric supply scheme, referred to a single pixel, of a microtip cathodic structure made according to the prior art and to the present invention, respectively. With reference to Fig. 5, a microtip cathodic structure is realized on a substrate 1 of a suitable insulating material, such as glass, ceramics, silicon and the like (GLASS SUBSTRATE). With or without the interposition of an adhesion layer, for example of silicon, over one (inner side) face of the substrate a conductor layer 2 of low resistivity, for example a layer of aluminum, niobium, nickel or a metal alloy (METALLIC CATHODE) is eventually deposited. The conductor layer may have a thickness comprised within 0.3 and 0.8 µm. The metallic layer 2 can be deposited by sputtering or by any other suitable technique. According to this invention the polycrystalline and/or amorphous silicon stack is preferably deposited by plasma-enhanced channel vapor phase deposition (PECVD) or at least the first two layers 2 and 4 of the stack are preferably deposited using this technique that ensures a good control of the deposition even at a relatively high rate of deposition and under conditions of relatively low temperature. The third or topmost layer 5 may be deposited by PECVD or, in the case the microtips are obtained from such a polycrystalline and/or amorphous silicon upper layer 5, said layer that must be deposited with an adequately large thickness, may be formed by other deposition techniques even though the PECVD process is regarded as preferable. The triple layer or stack (3, 4 and 5) of amorphous, partially polycrystalline or eventually polycrystalline silicon can be alternately doped to realize an n-p-n stack, as in the example illustrated in Fig. 5, or a p-n-p stack. Of paramount importance is the alternance of the type of conductivity of the three superimposed layers so as to realize a double (back-to-back) junction, one junction of which is always inversely biased, regardless of the polarity of the voltage applied to the cathodic structure through the control matrix, which matrix consists of rows (strips) of grid electrode and of columns (strips) in which is electrically subdivided the cathodic structure. With reference to the example of Fig. 5, the first layer 3 of n-doped polycrystalline and/or amorphous silicon, may have the following characteristics: thickness: from 0.3 to 0.1 µm; concentration of dopant: from 10 19 to 5 • 10 20 ; the intermediate p-doped layer 4 should guarantee that the electric structure constituted by the double junction p-n-p (or n-p-n) has a breakdown voltage higher than the grid voltage and for this reason it should have a lower doping level lower than both the bottom and top layer, in practice it may have the following characteristics: thickness from 0.5 to 1.0 µm; concentration of dopant: from 10 15 to 5 • 10 16 ; the third or upper n-doped layer 5, may have the following characteristics: thickness: from 0.5 to 1.0 µm; concentration of dopant: from 10 19 to 5 • 10 20 . The above mentioned ranges of variation of the characteristics of the amorphous and/or polycrystalline superimposed layers of alternately doped silicon are purely an indication of conditions that are considered suitable for obtaining an enhanced limiting and uniforming of the emission current through the microtips of an addressable pixel of the display. Of course, the most adequate thickness and the most adequate level of doping may be determined by a "trial and error" procedure for optimizing the performance of the cathodic depending on other parameters of the panel architecture on the process of fabrication used and on the dimensions and characteristics of the display. Of course, when the microtips 6 are formed by etching an upper layer of silicon that may be the top layer 5 of the stack, the thickness of the latter will have to be adequately increased by an amount equal to or modulately larger than the height of the microtips to be formed. According to the example illustrated in Fig. 5, the microtips are obtained by vertical sputtering a refractory metal, for example molibdenum, inside performed wells 9 created by a dedicated photolithographic step for patterning the stack that includes a dielectric isolation layer of adequate thickness 7, typically of silicon dioxide, and a conductive layer 8, typically of niobium or of a metal alloy of nickel and niobium from which the extractor grid of the cathode structure is defined. According to the architecture illustrated in the example of Fig. 5, the thickness of the upper layer 5 of the stack may be designed in function of the actual "resistivity" of the inversely biased junction of the triple layer of the alternately doped amorphous and/or polycrystalline silicon (3, 4 and 5) (n-p-n, as in the example shown, or p-n-p) in order to foster an enhanced uniformity of the emission currents through all the tips of a selected pixel. In practice, the lateral resistance through the upper layer 5, onto which the microtips are formed, as referred to the pixel dimensions, should be preferably lower than the series resistance along the path of the emission current that is provided by the inversely biased junction extending throughout the area of the selected pixel. The possibility of freely increasing the conductivity of the upper layer 5 over which or from the face of which the microtips 6 extend, either by adjusting the doping level or increasing the thickness of the upper layer 5, permits to ensure a high degree of bias uniformity over the whole pixel area and a good heat dissipation, whereas an effective limitation of the pixel current is ensured by the series resistance provided by the inversely biased junction, having a sufficiently high leakage current, constituted by the superimposition of alternately doped n and p layers of polycrystalline and/or amorphous silicon. This results in an outstanding controllability of the characteristics and performances of the fabricated panel.

Claims: A polycrystalline and/or amorphous silicon field emission display comprising pluralities of cathodic microtips extending from conductive strips defined on the surface of a dielectric substrate and constituting as many columns individually biasable by a column scanning drive circuitry of a pixel addressing matrix further comprising parallel conductive grid strips, orthogonal to and electrically insulated from said parallel conductive strips constituting said addressable columns, having pluralities of holes, each hole defining a circular edge of the conductive grid strip surrounding the vertex of a microtip and being individually biasable by a row scanning circuitry of said pixel addressing matrix, characterized in that each of said conductive strips defined on the surface of the dielectric substrate comprises a strip of a multilayer or stack composed of at least three superimposed layers of amorphous and/or polycrystalline silicon, each layer being doped to have type of conductivity opposite to the type of conductivity of a layer of doped amorphous and/or polycrystalline silicon adjacent thereto. the multilayer of a biased conductive strip allowing the passage of a current therethrough from said biasing circuitry to the microtip extending from the biased column of said pixel addressing matrix in the form of a leakage current of an inversely biased n-p junction estabilished between two of said alternately n and p doped layers. The field emission display as defined in claim 1, characterized in that said inversely biased n-p junction realizes an emission current path normal to said layers more resistive than any lateral path through the thickness of the uppermost one of said layers from which said microtips extend relative to the dimensions of the area of any single addressable pixel of the display containing a plurality of said microtips extending from the uppermost one of said layers within said pixel area.. The field emission display as defined in claim 1, wherein said three superimposed layers have respectively an n, p and n type of conductivity. The field emission display as defined in claim 1, wherein said three superimposed layers have respectively a p, n and p type of conductivity. The field emission display as defined in claim 1, characterized in that the intermediate layer of said stack of three superimposed layers has a concentration of dopant lower than the concentration of dopant of the other two layers. The field emission display as defined in claim 1, wherein said three superimposed layers are of at least partly amorphous silicon. The field emission display as defined in claim 1, wherein said three superimposed layers are ofpolycrystalline silicon. The field emission display as defined in claim 7, wherein said three superimposed layers of doped polycrystalline silicon have a grain size suitable for determining a relatively high level of leakage current across said inversely biased junction meeting the requisites of emission current level through said microtips. A method of limiting the current emitted by microtips of a cathodic structure of a field emission display characterized by realizing between a conductive strip of a pixel driving matrix and over which a population of emitting microtips is formed, at least an inversely biased junction in the form of at least three superimposed layers of alternately doped amorphous and/or polycrystalline silicon.

Inventors: BALDI LIVIO, BALDI, LIVIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: G09G1
IPC codes: G09G3, H01J1, H01J31