DATA CACHE

Abstract: A Data Cache (22) for a stack based computer (10) comprises an address calculation stage (25), a cache maintenance stage (26) and an arithmetic logic unit stage (27). The computer (10) comprises external memory (21) and a pipelined processor (20). An instruction from an instruction fetch stage (24) is passed to the address calculation stage (25). The address calculation stage (25) translates addresses relative to the top of stack into an absolute address. The cache maintenance stage receives the absolute addresses and determines if data corresponding to the addresses is available in a temporary register in the ALU stage (25). If necessary, the cache maintenance stage (26) injects read from or write to memory instructions into the pipeline (28).

Description: DATA CACHE The present invention relates to a data cache for a computer. The majority of computers may either be classed as register based computers or stack based computers. Register based computers comprise a processor, a register file, and a main memory. The register file is a small, fast memory whilst the main memory is much larger and relatively slow. Address fields in the processor's instructions refer to operands in the register file directly. Operands in the main memory are referenced indirectly, using the data contained in the register, specified by an address field, as an address. The performance of register based computers may be enhanced by the addition of a cache. A cache is a fast memory combined with ■ control logic which is used to store the contents of certain main memory locations. The control logic arranges that the cached locations are those most likely to be accessed in the near future. This is achieved by exploiting the phenomenon that recently accessed main memory locations are those which are most likely to be accessed again. Since the cache memory is faster than the main memory, the overall performance of the computer is improved by reducing the access time for data which is stored in the cache. Stack based computers comprise a processor and a main memory, part of which is organised as a stack. A register internal to the processor contains the address of the main memory location which is currently at the top of the stack. The instructions for a stack based computer processor contain no address fields, since operands are referenced implicitly relative to the current top of the stack. Generally, input operands are obtained by popping values from the stack, and output operands are stored by pushing data on to the stack. Compared with register based computers, stack based computers offer the potential of simpler compilers. Computers with stack based architectures are known, an example being the Burroughs B5500 computer as described by R.S.Barton in the Proceedings of the Western Joint Computing Conference (196l) pages 393"396. In this computer, high speed registers in a local store internal to the processor held the top two elements of the stack in memory. More recent processors incorporating stack based architectures include the AT&T CRISP system, described by D.R.Ditzel et al. in Proceedings, l^ th Annual International Symposium on Computer Architecture, IEEE Computer Press, Los Alamitos USA, June 1 87 pages 309-319ι and the Rockwell AAMP system described by D.W.Best et al. in IEEE Micro Volume 2, Number 3. August 1982 pages 10-26. Both of these systems have high speed register files internal to a processor chip which are maintained by a stack controller. The operation of the stack controller is transparent to the programmer, with the registers appearing to be a single linear stack. The AAMP system has four registers on the chip which contain four operands from the stack, whilst the CRISP system holds the top 3 words of the stack locally within the processor. The CRISP system registers are arranged as a circular buffer of registers, maintained by head and tail pointers. Each of the register files of these systems acts as a window to the stack providing sequential one-to-one mapping of the register file on to the memory stack. The sequential mapping arrangement is effective when the stack is accessed by push/pop operations but when access to locations at arbitrary offsets within the stack is required, performance is impaired. It is desirable to avoid regularly updating and flushing registers within a processor on an automatic basis as the stack front changes as this requires a great deal of redundant data to be exchanged. Maintenance of internal registers within a processor is simplified if the number of the internal registers is increased. However, the physical space available for high speed registers internal to a processor is generally limited. Although several early computer designs had a stack based organization, stack based computers have fallen out of favour. Register based processors now have a predominant position in modern processor design. Register based processors are commonly pipelined; that is to say, the processors contain a number of functional blocks, or stages, with information being passed from one stage to the next in response to a clock signal. Each stage carries out a simple function using specialised circuitry and ideally starts on the next instruction once it has completed an instruction. At any given time, there may be several instructions present in the pipeline, each of which is passed from one stage to the next in response to a clock signal. Pipelining is described by D.P.Siewiorek, C.G.Bell, and A.Newell in "Computer Structures: Principles and Examples", McGraw-Hill Book Company New York, 1982, Section 3, pages 260 to 264. It is an object of the invention to provide an alternative data cache. The present invention provides a data cache for a pipelined processor, the data cache being arranged to provide an arithmetic logic unit (ALU) with stored data, characterised in that the data cache is included within and extends over a plurality of stages within the pipeline. The invention provides the advantage that by having a data cache which extends over a plurality of pipeline stages, it is possible to determine whether an operand which is required for an operation is stored in the data cache prior to the instruction being passed to the ALU, and so decrease the access time for data stored in the cache. The data cache may comprise a cache controller and a data store. The cache controller and the data store may be contained within different stages of the pipeline and the data store may be within the same stage as the ALU. In a preferred embodiment, the pipelined processor is a stack based processor. The cache controller may comprise an address calculation stage and a cache maintenance stage. A stack based processor offers the potential advantage of a simpler compiler compared with the compiler required for register based processors. By separating the cache controller into two stages, the net processing time for instructions may be decreased. The data store of the data cache may be a register file. This provides the advantage that the benefits of having a stack based instruction set such as a simpler compiler may be combined with the benefits of registers such as high access speed. The cache maintenance stage may include random access memory (RAM) arranged to store information concerning the storage of data in the data store. The RAM may be three port, three access RAM. The present invention also provides a pipelined computer processor incorporating a data cache, the data cache being arranged to provide an arithmetic logic unit (ALU) with stored data, characterised in that the data cache is included within and extends over a plurality of stages within the pipeline. The invention further provides a data cache for a stack based processor, the data cache being arranged to provide an arithmetic logic unit (ALU) with stored data. A computer processor is that part of a computer that controls the operation of the computer system, executing arithmetical and logical functions contained in a particular program. It may be referred to as a central processing unit or a microprocessor. In order that the invention might be more fully understood, an example thereof will now be described, by way of example only, with reference to the accompanying drawings, in which:- Figure la is a schematic diagram of a computer incorporating the data cache of the invention; Figure lb is a schematic diagram of stages in the computer of Figure la together with control links between the stages; Figure 2a is a schematic diagram of an address calculation stage of the Figure la data cache; Figure 2b shows the address calculation stage in greater detail; Figure 2c is a diagram of a controller for the Figure 2a address calculation stage; Figure 3 is a schematic diagram of a cache maintenance stage of the Figure la data cache; Figure 4a is a diagram of a part of the Figure 3 cache maintenance stage; Figure 4b shows a diagram of a hit/miss logic unit of the Figure 4a part; Figure 4c is a diagram of a bank of tag cache memory of the Figure 4a part; Figure 5 is a diagram of a further part of the Figure 3 cache maintenance stage; Figure 6 is a schematic diagram of an arithmetic logic unit stage controller; Figure 7 is a schematic diagram of the arithmetic logic unit stage of the Figure la data cache; and Figure 8 is a state diagram of the Figure 6 controller. Referring to Figure la, there is shown a schematic block diagram of a stack based computer, indicated generally by 10. The computer 10 comprises a processor 20 and external memory 21. The processor 20 is comprised of a data cache 22 of the invention, a memory interface unit 23, and an instruction fetch stage 24. The processor 20 is a pipelined processor, in which several instructions are active throughout different stages of the processor. For the sake of ease of understanding of the current invention, stages occurring in the processor 20 prior to the data cache 22 are grouped together as the instruction fetch stage 24. Such stages are familiar to those familiar with computer architecture design. The computer 10 is an r-bit computer. In the present embodiment, r is 32 but other embodiments may have alternative values of r. The data cache 22 incorporates three sequential stages, these being an address calculation stage 25, a cache maintenance stage 26, and an arithmetic logic unit (ALU) stage 27- Information enters the data cache 22 and passes between its stages along a pipeline 28. Operation codes and operands are exchanged between the instruction fetch stage 24 and the memory interface unit 23 via a bus 29. Likewise, the ALU stage 27 exchanges data with the memory interface unit 23 via a bus 30. The memory interface unit 23 in turn exchanges data with the memory 21 via a bus 31- A typical instruction passed from the instruction fetch stage 24 to the data cache 22 is a three operand based instruction of the form "operator,c,b,a", corresponding to the equation "c = b operator a", where a, b, and c are operands and the operator defines the operation to be carried out, for example add. The address calculation stage 25 translates location references of operands from the instruction fetch stage 24 to absolute references in the external memory 21. The location references are in the form of offsets relative to the stack base of the current stack within the processor 20 or the top of the current stack. The cache maintenance stage 26 maintains the data in the ALU stage 27- The absolute address from the address calculation stage 25 is used to determine whether the data in the address referred to is cached in the ALU stage 27. If the data is not cached, it must be fetched from the external memory 21, and if this would cause existing cached data to be overwritten, the original data may need to be stored in memory first. Referring also to Figure lb, the four stages of the pipeline of Figure la are shown together with control links between the stages. Each stage sends a valid instruction signal to its succeeding stage, indicating that the contents of a pipeline register which supplies data to that succeeding stage contains valid data which can be acted upon. In addition, the ALU stage 27 and the cache maintenance stage 26 pass a stall signal to their respective preceding stage in order to inform the preceding stage that it has not finished processing the current instruction and that no more instructions should be passed down the pipeline 28. The instruction fetch stage 24 passes a valid instruction signal to the address calculation stage 25 along a control line 32. The address calculation stage 2 passes a valid instruction signal to the cache maintenance stage 26 along a control line 33 and the cache maintenance stage 26 passes a valid instruction signal to the ALU stage 27 along a control line 34. A clock signal is sent from a system clock (not shown) along a clock control line 35- The clock signal is passed directly to the ALU stage 27. The ALU stage 27 emits a stall signal which is passed along a control line 36 to an inverting input NAND gate 37- The gate 37 carries out a NAND operation on the inverted stall signal and an inverted clock signal from the clock control line 35- The result is passed to the cache maintenance stage 26 as a clock input on a clock control line 38. The cache maintenance stage 26 emits a stall signal which is passed along a control line 39 to an OR gate 40. The gate 40 carries out an OR operation on the stall signal on the control line 39 and the stall signal from the ALU stage 27 on the control line 36. The result is passed to two inverting input NAND gates 4l and 42 along a control line 3. The gate 4l carries out a NAND operation on an inverted clock signal from clock control line 35 and an inverted signal from control line 3 and passes the result to the address calculation stage 25 as a clock signal on a clock control line 44. The gate 42 carries out a NAND operation on an inverted clock signal from clock control line 35 and an inverted signal from control line 43 and passes the result to the instruction fetch stage 24 as a clock signal on a clock control line 45- The stall signals are used to inhibit the clock signals into preceding stages. Inverting inputs on the NAND gates 37. 4l, and 42 are required to ensure the correct polarity of the clock signal passed to each stage because the stall signal is an "inhibit- rue" signal. The stall signals are propagated throughout all previous stages since all stages have to be halted when either of the stall signals is true. Referring to Figure 2, there is shown the address calculation stage 25. Figure 2a shows the stage 25 in block form, Figure 2b shows the address calculation stage 2 in more detail and Figure 2c shows an address calculation stage controller. An instruction 50, indicated by a dashed box, is received from the previous stage in the pipeline (not shown) . The instruction 50 is comprised of three operands, operand A 5 , operand B , and operand C 56, and an operation code 58. The operation code 8 is not affected by the addresss calculation stage 25. The three operands 52, 5 , and 6 pass to a translation logic unit 60. The translation logic unit 60 translates a relative address for each operand into an absolute address of the operand in memory, depending on the type of the operand. To achieve this translation, the translation logic unit 60 is supplied with a stack base address from a stack base register unit 62 and a top of stack address from a top of stack register unit 64. The translation logic unit 60 passes translated operands A, B, and C, 66, 68, and 70 respectively, to a pipeline register 72. The unchanged operation code 58 is also passed to the register 72 as operation code 58 * . The stack base register unit 62 passes a stack base address 74 to the register 72, and the top of stack register unit 64 passes a top of stack address 76 to the register 72. Figure 2b is a more detailed diagram of the address calculation stage 25. The translation logic unit 60, the stack base register unit 62 and the top of stack register unit 64 are each indicated by dashed boxes in Figure 2b. Each of the operands 52, 54, and 56 is comprised of a type indicator and a data field indicated by the reference numeral of the operand together with the suffix "t" or "d" respectively. Each of the operands 52, 54, and 56 may be one of three types: "Constant", "Stack Offset" or "Top of Stack". If an operand has a Constant type, the operand data represents a constant which is used by the instruction as a numeric constant or as an address in memory, and so passes through the translation logic unit 60 unaltered; the constant may be signed or unsigned. If an operand has a Stack Offset type, the operand represents an offset into a current stack relative to a stack base, in which case, the translation logic unit 60 adds the contents of the data field to a stack base address received from the stack base register unit 62 to produce an absolute address of a memory location within the stack. If an operand has a Top of Stack type, the operand will be involved in a "pop" or "push" operation. A pop occurs when data is read from a stack and a push occurs when data is written to a stack. Both of these operations are carried out at the top of the stack and so when the operand has a Top of Stack type the top of stack register unit 64 provides the translation logic unit 60 with an absolute address of the location in the stack in memory where the push or pop operation will take place. The stack base register unit 62 comprises a two input multiplexer 100 and a register 102. The multiplexer 100 has a first input 104 and a second input 106. The multiplexer 100 switches one of the two inputs 104 and 106 to an output 108. A control signal is sent from the address calculation stage controller (not shown) along control line 110 to select which of the inputs 104 and 106 is switched to the multiplexer output 108. The output 108 supplies the register 102 with the address of the stack base. The contents of the register 102 are updated in response to a clock signal on a clock control line 44. The contents of the register 102 are supplied to the multiplexer 100 via the second input 106, to the pipeline register 72 via a data line 114, and to the translation logic unit 60 via a data line 116. The first input 104 is supplied with an address of the current stack base from an external source (not shown) . The second input 106 is switched to the output 108 except on computer start-up or when the current stack is changed, when the first input 104 is switched to the output 108. The top of stack register unit 64 comprises a four input multiplexer 120, a register 122, and two adders 124 and 126. The multiplexer 120 has four inputs 128, 130, 132, and 13 . The multiplexer switches one of the four inputs 128 to 13 to an output 136. A control signal is sent from the address calculation stage controller (not shown) along a control line l4θ to select which of the inputs 128 to 134 is switched to the multiplexer output 136. The output 136 supplies the register 122 with the top of stack address. The contents of the register 122 are updated in response to the clock signal on the clock control line 44. The contents of the register are supplied to the adders 124 and 126, to the input 128, to the pipeline register 7 via a data line 144, and to the translation logic unit 60 via a data line 146. The adder 124 adds either (+1) or (-1) to the contents of the register 122 and passes the result to the translation logic unit 60 along a data line 148 and to the multiplexer input 130. Adder 124 adds either (+1) or (-1) to the register contents under the control of a signal received from the address calculation stage controller (not shown) along a control line 150. Adder 126 adds (-2) to the contents of the register 122 and passes the result to the translation logic unit 60 along a data line 152 and to the multiplexer input 132. The type indicators 52t, 54t, and 56t are passed to the address calculation stage controller (not shown) along data lines 154, 156, and 158 respectively. The operation code 58 is passed to the address calculation stage controller along a data line l6θ. The address calculation stage controller determines the switching of the multiplexers 100 and 120 and the addition operation of the adder 124. The address calculation stage controller operates in accordance with the selector logic shown in either Table 1 or Table 2, depending on whether the operation code 58 corresponds to a three operand operation or a two operand operation respectively. Three operand instructions are typically arithmetic instructions which take two operands, perform a simple operation on them and return the value to the destination indicated by the third operand. Two operand instructions are simple monadic arithmetic instructions, such as negate instructions and move instructions where a first operand is operated on and returned to a destination indicated by the second operand. In Tables 1 and 2, the first columns ensure that when there are no incoming instructions to the address calculation stage, the internal register 122 is not updated. When instrValidln is false, indicated by a "0", the internal register 122 is not updated because the multiplexer 120 is switched to select input 128. A "-" in Tables 1 and 2 indicates that the entry is not relevant. The columns under the heading Operand Type show the possible combinations of operand types. Where an entry is given as "Constant", the operand type may either be Constant or Stack Offset, since this distinction is not relevant to the operation of the top of stack register unit. Where an entry is given as "ToS", the operand has a Top of Stack type. The penultimate column indicates whether the adder 124 is instructed to add (+1) or (-1), and the final column indicates which of the inputs to the multiplexer 120 is switched to the output 136. Multiplexer input 134 is selected if the contents of the register 122 are not the required top of stack address as may occur during computer start-up or when the current stack is changed. The translation logic unit 60 comprises three multiplexers 170, 172, and 174, which operate on operands A, B, and C, 52, 54, and 56, respectively. The multiplexer 170 is a three input multiplexer, with inputs l8θ, l82 and 184. Input lδO is a direct input of the data field 52d of operand A 52. Input 182 is the sum of the data field 52d and the stack base address from data line 116, summed by an adder 186. Input 184 is the output of the adder 124 on the data line 148. One of the inputs lδO, 182, and 184 is switched to an output 188 in response to a control signal from the address calculation stage controller (not shown) supplied on a control line 190. The output 188 passes a translated data field 66d of the operand A 66 to the pipeline register 72. The multiplexer 172 is a four input multiplexer, with inputs 200, 202, 204, and 206. Input 200 is a direct input of the data field 54d of operand B 5 . Input 202 is the sum of the data field 5 d and the stack base address from data line 116, summed by an adder 207- Input 204 is the output of the adder 124 on the data line 148, and input 206 is the output of the adder 126 on the data line 152. One of the inputs 200, 202, 204, and 206 is switched to an output 208 in response to a control signal from the address calculation stage controller (not shown) supplied on a control line 210. The output 208 passes a translated data field 68d of the operand B 68 to the pipeline register 72. The multiplexer 174 is a five input multiplexer, with inputs 220, 222 , 224, 226, and 228. Input 220 is a direct input of the data field d of operand C 56. Input 222 is the sum of the data field 56d and the stack base address from data line 116, summed by an adder 230. Input 224 is the output of the adder 124 on the data line 148, input 226 is the output of the adder 126 on the data line 152, and input 228 is the contents of the register 122 on the data line 146. One of the inputs 220, 222, 224, 226, and 228 is switched to an output 232 in response to a control signal from the address calculation stage controller (not shown) supplied on a control line 234. The output 232 passes a translated data field 70d of the operand C 70 to the pipeline register 72. The type indicators 52t, 541, and 56t are passed to the pipeline register 72 unchanged as type indicators 66t, 68t, and 70t of the operands A 66, B 68, and C 70 respectively. The pipeline register 72 is updated in response to the clock signal on the clock control line 44. The address calculation stage controller (not shown) determines the switching of the multiplexers 170, 172, and 174. The controller operates in accordance with the selector logic shown in either Table 3 or Table 4 depending on whether the operation code corresponds to a three operand instruction or a two operand instruction respectively. The columns under the heading Operand Type show the possible combinations of operand types. In Tables 3 and , where an operand type is shown as "Constant", this does not include a Stack Offset type. Stack Offset types are shown as "Offset", and Top of Stack types are shown as "ToS". The reference numbers in the columns under the Multiplexer Input selected heading indicate which inputs are switched to the respective outputs of the multiplexers 170, 172, and 174. The type indicators of operands A, B, and C, 52, 5 , and 56, are not altered in the address calculation stage but their meanings change slightly. A Constant operand type is unchanged; a Stack Offset type becomes a "Stack Address" type in which the data field corresponds to an absolute address of a memory location within the stack; and a Top of Stack type becomes a "Top of Stack Address" type in which the data field corresponds to an absolute address of the top of the stack, with implied push/pop operations. Figure 2c is a diagram of the address calculation stage controller indicated generally by 250. The controller 250 comprises a logic unit 2 2 which implements the logic of Tables 1, 2, 3. and 4, and a clocked D-type latch 254. The logic unit 252 receives the type indicators of the operands 52, 54, and 56 (not shown) on data lines 154, 156, and 158 respectively; the operation code 58 (not shown) on data line l6θ and the "instrValidln" signal from the instruction fetch stage 24 (not shown) on the control line 32. The logic unit 252 sends the control signals to the various components of the address calculation stage, as described previously, on control lines 110, l4θ, 234, 210, 190, and 150. The clocked D-type latch 254 receives the instrValidln signal on control line 32 and the clock signal on the clock control line 44 and sends out an instrValidOut signal on the control line 33 in response to a clock signal. The instrValidOut signal on the control line 33 is passed to the cache maintenance stage 26 (not shown) as an instrValidln signal. Referring now to Figure 3. there is shown a schematic diagram of the cache maintenance stage 26. The cache maintenance stage comprises an operand translation unit 300, a tag cache memory 302, a logic unit 304, and a multiplexer 306. The operand translation unit 300 extracts various fields from the operands in the pipeline register 72 and recombines them to form register addresses or absolute values for use by the ALU stage 27 (not shown) . The multiplexer 306 provides a means for overriding the current operation code 58 * to allow new data to be fetched from memory or updated data to be written to memory as necessary. The tag cache memory 302 stores information which is used to determine whether the data addressed by the operands is present in the ALU stage 27- The logic unit 30 provides the necessary signals for the cache maintenance stage to carry out its functions, selecting which data field to pass through to the ALU stage and injecting any instructions necessary to fetch new data or write back current data that may be overwritten. The three operands 66, 68, and 70 in the pipeline register 72 each have a type indicator and a data field as already described. The data fields of the operands comprise an offset field and a tag field. The offset field is formed from the lowest n bits of the data field where 2 n is the number of addressed locations within each of two banks of RAM of the tag cache memory 302. The tag field comprises the remaining bits of the data field. Operand A 66 comprises a type indicator 66t, a tag field 310, and an offset field 312. Operand B 68 comprises a type indicator 68t, a tag field 316, and an offset field 318. Operand C 70 comprises a type indicator 70t, a tag field 322, and an offset field 324. Type indicators 66t, 68t, and 70t are passed to the logic unit 304 along data lines 326, 328, and 330 respectively. The tag field 310 is passed to the operand translation unit 300 along a data line 332a, to the tag cache memory 302 along a data line 332b and to the logic unit 30 along a data line 332c. The offset field 312 is passed to the operand translation unit 300 along a data line 334a and to the tag cache memory 302 along a data line 334b. Similarly, the tag field 316 is passed to the operand translation unit 300 along a data line 336a, to the tag cache memory 302 along a data line 336b, and to the logic unit 30 along a data line 336c, and the offset field 318 is passed to the operand translation unit 300 along a data line 33δa and to the tag cache memory along a data line 338b. The tag field 322 is passed to the operand translation unit 300 along a data line 34θa, to the tag cache memory 302 along a data line 34θb,and to the logic unit 304 along a data line 34θc, and the offset field 324 is passed to the operand translation unit 300 along a data line 342a and to the tag cache memory 302 along a data line 342b. The logic unit 30 receives information from the tag cache memory 302 via a bus 344. The logic unit 304 sends control signals to the tag cache memory 302, the operand translation unit 300 and the multiplexer 3θ6 along control lines (not shown) . Revised operand type indicators are passed from the logic unit 304 to a pipeline register 36 along data lines 348a to 348c. The data lines 348a to 348c are referred to collectively as the data lines 348. The operation code 58 * passes via the multiplexer 306 to the pipeline register 346. The stack base address 7 and the top of stack address 76 pass to the pipeline register 346 unaltered. In order to simplify Figure 3, the stack base address 7 and the top of stack address 76 are represented by a single box 350. Referring now to Figure 4a there is shown a more detailed diagram of the tag cache memory 302 and the logic unit 304, which are indicated by dashed boxes. The tag cache memory comprises two banks of three port/three access RAM 400 and 402. Three port/three access RAM technology is described by M.L.Anindo et al . in "Proceedings of the 16th Annual Symposium on Computer Architecture" , IEEE Computer Society Press, 1989, pages 354-361, and by K.J.O'Connor in the IEEE Journal of Solid State Circuits, sc-22, 5, October 1987. pages 712-720. Each bank of RAM 400 and 402 is a contiguous set of memory which may be addressed from the three data lines 334b, 338b, and 342b, which carry the offset fields of the operands 66, 68, and 70 respectively. Since each offset field has n bits, there are 2 n locations for each of the banks 400 and 402. The logic unit 304, indicated by a dashed box, comprises a control logic unit 4θ4 and three hit/miss logic units 4θ6a, 4θ6b, and 4θ6c. The control logic unit 404 sends master write commands to the RAM bank 400 along a control line 4θ8 and to the RAM bank 402 along a control line 410. Provided the master write command is held false, when an address is placed on one of the data lines 334a, 338b, or 342b, data in the addressed location of the RAM bank for which the master write command is false is placed on either one of data lines 4l2a, 4l2b and 4l2c if the data is in RAM bank 402 or one of data lines 4l2d, 4l2e, and 4l2f if the data is in RAM bank 400. The data lines 4l2a to 4l2f are referred to collectively as data lines 412 and comprise the bus 344. The data which is placed on the data lines 412 comprises a tag field, which had been stored in the RAM bank previously, as well as a valid/invalid bit and a dirty/clean bit, as indicated by data entries 4l3a and 4l3b. The valid/invalid bit indicates whether data held in a register file in the ALU stage 27 (not shown) may be used (valid) or must be fetched from memory first (invalid) . The dirty/clean bit indicates whether the register file in the ALU stage 27 (not shown) is holding data which is the same as that in memory (clean) or that the contents are different because a local register write has occurred (dirty). The data on the data lines 412 is passed to one of three hit/miss logic units 4θ6a, 4θ6b, and 4θ6c. Hit/miss logic unit 4θ6a is concerned with operand A, hit/miss logic unit 4θ6b is concerned with operand B, and hit/miss logic unit 4θ6c is concerned with operand C. Referring also to Figure 4b, there is shown a schematic diagram of the hit/miss logic unit 4θ6a. The tag field 310 of operand A 66 is passed by the data line 332c to comparators 4l4 and 4l6. The comparators 4l4 and 4l6 compare the tag field 310 with either the tag field from RAM bank 402, received from data line 4l2a on a data line 4l2al or the tag field from RAM bank 400 received from data line 4l2d on a data line 4l2dl respectively. If the tag field 310 is equal to the tag field from the RAM bank, the comparator 4l4 or 4l6 outputs a true signal. The output signals from the comparators 4l4 and 4l6 are passed to a bank logic unit 4l8 along data lines 420 and 422 respectively. The output signals from the comparators 4l4 and 4l6 are also passed to four AND gates 424a to 424d. AND gate 424a carries out an AND operation on the output signal of comparator 4l4 and the valid/invalid bit received from data line 4l2a on a data line 4l2a2. The result is passed to an OR gate 426a. AND gate 424b carries out an AND operation on the output signal of comparator 4l4 and the dirty/clean bit received from data line 4l2a on a data line 4l2a3; the result is passed to an OR gate 426b. AND gate 424c carries out an AND operation on "the output signal of comparator 4l6 and the valid/invalid bit received from data line 4l2d on a data line 4l2d2 and passes the result to the OR gate 426a. AND gate 424c carries out an AND operation on the output signal of comparator 4l6 and the dirty/clean bit received from data line 4l2d on a data line 4l2d3 and passes the result to the OR gate 426b. The OR gate 426a carries out an OR operation on the outputs of the AND gates 424a and 424c and passes the result along a data line 428a to an action logic unit 430. OR gate 426b carries out an OR operation on the outputs of the AND gates 424b and 424d and passes the result along a data line 428b to the action logic unit 430. The output of the OR gate 426a indicates whether the data in the tag cache memory 302 is valid or invalid and the output of the OR gate 426b indicates whether the data in the tag cache memory is clean or dirty. The bank logic unit 4l8 is supplied with the type indicator 66t of the operand 66 on the data line 326. The bank logic unit 4l8 determines whether a tag has been found and in which bank it was found according to Table 5. A "0" in the Bank column of Table 5 indicates the tag is found in the RAM bank 400 and a "1" indicates that the tag is found in RAM bank 402. The condition where tag equality is found in both banks is illegal and would normally only be found on start up. Provided the bank logic unit includes a reset mechanism, this condition will not appear except under fault conditions. The bank logic unit 4l8 passes the contents of the Tag found column to the action logic unit 430 along a data line 43 . Hit/miss logic units 4θ6b and 4θ6c are similar to the hit/miss logic unit 4θ6a shown in Figure 4b, except logic unit 4θ6b receives information from operand 68 via the data lines 328 and 336b and from the cache tag memory banks 400 and 402 via data lines 4l2b and 4l2e, and logic unit 4θ6c receives information from operand 70 via data lines 330 and 34θb and from the cache tag memory banks via data lines 4l2c and 4l2f. The action logic unit, such as action logic unit 430, of each hit/miss logic unit 4θ6a to 4θ6c outputs a revised operand type and a required action according to logic tables Table 6 and Table 7 which are for write actions and for read actions respectively. Table 6 shows the logic for operand C and so is the required logic table for the action logic unit of hit/miss logic unit 4θ6c and Table 7 shows the logic for operands A and B and so is the required logic table for the action logic units of hit/miss logic units 4θ6a and 4θ6b. In both Tables 6 and 7, the entries in the column beneath the heading "Valid" indicate the output of the OR gate 426a, with a "1" indicating a valid entry in the tag cache memory and a "0" indicating invalid data. The entries in the column headed "Dirty" indicate the output of the OR gate 426b, with a "1" indicating that the data is dirty and a "0" indicating that the data is clean. The action logic unit of each hit/miss logic unit provides an action statement for each operand, indicating what the control logic unit 404 must do to pass the operands to the ALU stage correctly. There are three action statements associated with the C operand given in Table 6. These are Reg, WriteBack, and DirectCon, whose meaning is as follows:- i) Reg indicates that the operand contains a register address of the register in the ALU stage 27 which points to the value to be used by the instruction; ii) WriteBack indicates that the C operand contains a memory address which is used to write data from the register in the ALU stage 27 into the external memory 21; the B operand contains an address of the ALU stage register from where to get the data to be written and a write to memory instruction is inserted into the pipeline; the instruction which follows the write to memory instruction will be the original instruction that forced the write back of data; and iii) DirectCon indicates that the operand contains a constant to be used directly by the instruction. There are six action statements associated with the A and B operands given in Table 7 which are as follows:- i) DirectCon, which indicates that the operand contains a constant to be used directly by the instruction; ii) DirectRd, which indicates that the operand contains a memory address which is used to fetch data from the external memory 21 for use as the operand; it does not update the register file of the ALU stage 27; iii) Fetch, which indicates that the B operand contains a memory address which is used to fetch data from the external memory 21 for use as the operand, the C operand contains a register address and data is read from the memory address into the register file of the ALU stage 27 at the register address; the instruction is pre-set to be a "read memory" instruction and the instruction which follows the read memory instruction will be the instruction which forced the fetch; iv) Reg, which indicates that the operand contains a register address of the ALU stage register which points to the data to be used by the instruction; v) RegPop, which indicates that the operand contains a register address of the ALU stage register which points to the data to be used by the instruction; the tag cache memory 302 will be updated to reflect that the data has been disposed of; and vi) WriteBack, which indicates that the C operand contains a memory address which is used to write back data from the ALU stage register into the external memory 21 when the data in the register would otherwise be overwritten; the B operand contains a register address of the ALU stage register from where to get the data to be written; the instruction is set to be a write to memory instruction, the instruction following will be a read from memory instruction to get the data from the external memory 21 which would have overwritten the entry in the ALU stage register from where the write back is occurring, the following instruction is the instruction which forced the write back of data. The hit/miss logic units 4θ6a to 4θ6c pass the action statements according to Tables 6 and 7 to the control logic unit 4θ4 via data lines 434a to 3 c respectively. The logic units 4θ6a to 4θ6c also pass bank indicator bits to the control logic unit 4θ4 according to Table 5 along data lines 436a to 436c respectively. Tables 8a, 8b, and 8c are combinational logic tables for the control logic unit 404. The control logic unit 404 acts on the received action statements from the hit/miss logic units 4θ6a to 4θ6c and a instrValidln signal received from the address calculation stage 25 via the data line 258 according to control logic shown in Tables 8a, 8b, and 8c. Where an entry is given as "-", this indicates that the entry is not important. From the possible combinations of action statements, the control logic unit 4θ4 generates write enable bits, abbreviated to WrEn, as well as Valid bits and Dirty bits for each operand according to Table 8a. The write enable bits for operands A, B, and C are passed to the tag cache memory 302 via data lines 444a to 444c respectively; the Valid bits for operands A, B, and C are passed to the tag cache memory via data lines 446a to 446c respectively; and the Dirty bits for operands A, B, and C are passed to the tag cache memory via data lines 448a to 448c respectively. When the instrValidln signal is false, indicated by a 0, the write enable bits for the three operands A, B, and C are held false. WriteBack action statements are abbreviated to wrBack. Where a "Direct" action statement is shown in the columns relating to action statements received from the hit/miss logic units 4θ6a and 4θ6b the action statement may either be a DirectCon or a DirectRd action statement. Where an action statement column shows a "NOTwrBack" action statement, this indicates that any action statement which is not a WriteBack action statement; likewise, where a "NOT(wrBack/Fetch)" entry is shown, this indicates that the action statement is neither a WriteBack nor a Fetch action statement. A WriteBack action statement takes precedence over other action statements to ensure that data is not lost within the ALU stage 27- The Fetch and WriteBack action statements can only be performed one at a time, and a write back on operand C will take precedence over all other actions, and is followed in order of precedence by a write back on operand B, then a write back on operand A. A fetch on operand B will take precedence over any action on operand A. There is no fetch action on operand C. Table 8b is a further logic table for the logic unit 304. Table 8b indicates which inputs of multiplexers in the operand translation unit 300 are selected by the control logic unit 4θ4. The table also indicates revised operand data types which are passed to the pipeline register 346 along the data lines 348 by the hit/miss logic units 4θ6a to 4θ6c. The entries in the columns under the heading "opSel" are reference indicators for inputs of the translation unit multiplexers as will be described later. The opSel column headed A refers to a multiplexer associated with operand A, having two inputs; the opSel column headed B refers to a multiplexer associated with operand B, having five inputs; and the opSel column headed C refers to a multiplexer associated with operand C, having six inputs. The control logic unit 4θ4 controls the selection of the inputs to the multiplexers associated with operands A, B, and C via control lines 52a to 452c respectively. There are three revised data types which are passed to the pipeline register 346 via the data lines 348. These three data types are regAddr, memAddr, and constant. The meaning of these data types is as follows:- i) regAddr indicates that the data field is an address which refers to a location within a register file in the ALU stage 27 from where the operand value is to be stored or read from; ii) memAddr indicates that the data field is an address which refers to a location in the external memory 21 from where the operand must be fetched or to where it must be written, and is used directly by the ALU stage 27; and iii) constant indicates that the data field is a signed or unsigned constant which represents a numeric constant. The action statements of Table 8b have the same meanings as those of Table 8a except that DirectCon and DirectRd action statements are distinguished. Table 8c is a third logic table for the control logic unit 4θ4. According to Table 8c, the control logic unit 4θ4 determines whether the pipeline should be stalled, so as to allow read from memory or write to memory instructions to be inserted into the sequence of instructions. The meanings of the instrValidln column and the entries used in the Action statement columns are as for Tables 8a and 8b. If the pipeline is stalled, indicated by a 1 in the "Stall" column, the entries in the OpCode Sel column indicate which instructions are inserted. The stall bit is output on the control line 39 and an OpCode Sel is passes to the multiplexer 306 along a control line 460. Depending on the OpCode Sel signal, the multiplexer 306 is either instructed to pass the operation code 8 * to the pipeline register 346 when Table 8c shows an "instr" entry or to insert an instruction into the pipeline when Table 8c shows either a "readMem" entry, in which case a read fro memory instruction is inserted or a "writeMe " entry, in which case a write to memory instruction is inserted. The control logic unit 4θ4 controls the updating of entries in the tag cache memory 302 by controlling the master write commands on the write control lines 408 and 410. If the master write command on the write control line 408 is held true together with the corresponding write enable bit on data lines 444a to 444c for operands A to C, the data on the data lines 332b, 336b or 34θb respectively is placed into the memory location addressed by the offset fields on data lines 334b, 338b, or 3 2b respectively in memory bank 400. The Valid bit on data lines 446a to 446c and the Dirty bit on lines 448a to 448c according to Table 8a are also stored at the same offset within bank 400. If the master write command on the write control line 410 is held true, data is stored in memory bank 402 in a similar fashion. The control logic unit 4θ4 combines the received action statement for each of the operands A to C, the bank indicator bits for the operands A to C received from the hit/miss logic units 4θ6a to 4θ6c along data lines 436a to 436c respectively, and outputs signals on the write control lines 4θ8 and 410 according to Table 8d. For each operand A to C, a register bank indicator bit is output by the control logic unit 4θ4 to the operand translation unit 300 along data lines 48θa to 48θc respectively. The register bank indicator bits are used to determine which bank data is written to, or read from, in the register file of the ALU stage 27. In Table 8d, the instrValidln and the Action statements have the same meanings as the previous Tables 8a to 8c. The columns under the heading "Bank" contain the values of the bank indicator bits for operands A to C as determined by the hit/miss logic units 4θ6a to 4θ6c. The two columns for the master write commands underneath the heading "Wr" have a sub-heading Y or X. The column with the sub-heading Y indicates the status of the write control line 410 and the column with the sub-heading X indicates the status of the write control line 4θ8. Where the Wr columns show a "0", this indicates that the write control line associated with the relevant column is held false; where a "1" is shown, this indicates that the write control line is held true. The columns with the heading "RegBank" show the register bank indicator bits for operands A to C. A "b" in a RegBank column indicates that the entry takes the value of the corresponding bank indicator bit from the Bank columns. An entry with a superscript 1 beside it indicates that the entry is an arbitrary choice and a "-" entry indicates that the entry is not important. When the instrValidln signal on the control line 33 is false, the master write commands on the write control lines 408 and 410 are both held false. A clocked D-type latch 0 receives the instrValidln signal on the control line 33 and the clock signal on the clock control line 38 and sends out an instrValidOut signal on the control line 3 in response to the clock signal. The instrValidOut signal on the control line 34 is passed to the ALU stage 27 (not shown) as an instrValidln signal. Referring now to Figure 4c, there is shown a diagram of one bank of the tag cache memory 302 such as bank 400, indicated generally by 500. The bank of tag cache memory 500 comprises a multi-port memory unit 510 and an output data latch 512. The memory unit 510 has three data input ports 5l a to c and three address ports 5l6a to 5l6c. An inverted master write command is received on an input 518 and the clock signal on an input 520. An AND gate with inverting inputs 522 carries out an inverted input AND operation on the clock signal and the inverted master write command and feeds the result to the memory unit 510 via a command line 524. The memory unit 10 has three write enable inputs 526a to 526c. Providing the master write command is false, when an address is input to one of the address ports 5l6a to 5l6c, the data in the addressed location is placed on a respective data output 530a to 530c. If the addresses refer to the same memory location, the same data is placed on the respective data outputs. The data on the data outputs 530a to 530c passes to the output data latch 51 , which is controlled by a latch input 532 which is connected directly to the stage clock. The output data latch 512 has three output lines 534a to 534c corresponding to the three data outputs 530a to 530c of the memory unit 510. When the latch input 532 is held true, the output data latch 512 is "transparent" and the data on the outputs 530a to 530c and data on the output lines 534a to 534c are identical. When the latch input 532 is held false, the output data latch 12 is latched. For the bank of RAM 400, the data input port 5l4a receives data from the data lines 332b, 446a and 448a; the data input port 5l4b receives data from the data lines 336b, 446b, and 448b; and the data input port 5l4c receives data from the data lines 34θb, 446c, and 448c. The address ports 5l6a to 16c correspond to the data lines 334b, 338b, and 342b respectively; the write enable inputs 526a to 526c correspond to the data lines 444a to 444c respectively; the inverted master write command received at input 518 corresponds to an inverted signal on the control line 4θ8 and the clock signal on the input 520 is the clock signal on the clock control line 38. Referring now to Figure 5. there is shown a diagram of the operand translation unit 300, the translation unit 300 being indicated by a dashed box. The operand translation unit 300 comprises a first multiplexer 600, a second multiplexer 602, and a third multiplexer 604. The first multiplexer 600 has an output data line 606 which passes an address field 608 of operand C 610 to the pipeline register 346. The output on data line 606 is determined by an OpSel signal received on the data line 452c from the control logic unit 4θ4. The first multiplexer 600 has six inputs 6l4a to 6l4f. Input 6l4a is a full r-bit word comprising the tag field 322 and the offset field 324 of operand C 70 from data lines 34θa and 3 2a respectively. Input 6l4b comprises the offset field 324 of operand C 70 and the operand C RegBank bit according to Table 8d from control logic unit 4θ4 from data lines 342a and 480c respectively, with the offset field 324 forming the n least significant bits of the input. Input 6l4c comprises offset field 312 of the operand A 66 and the operand A RegBank bit according to Table 8d from the control logic unit 4θ4 from data lines 334a and 48θa respectively with the offset field 312 forming the n least significant bits of the input. Input 6l4d comprises the offset field 318 of operand B 68 and the operand B RegBank bit according to Table 8d from control logic unit 404 from data lines 338a and 48θb respectively with the offset field 318 forming the n least significant bits of the input. Input 6l4e is a full r-bit word comprised of the tag field 310 and the offset field 312 of operand A 66 from data lines 332a and 334a respectively; and input 6l4f is a full r-bit word comprised of the tag field 316 and the offset field 318 of operand B 68 from data lines 336a and 338a respectively. One of the inputs 6l4a to 6l4f is selected and connected to the output data line 606 in response to a signal received from the control logic unit 404 along data line 452c according to Table 8b. The reference letter of the selected input 6l4a to 6l4f is given in the column of table 8b headed opSel C. The second multiplexer 602 has five inputs 6l6a to 6l6e, one of which is selected in response to a control signal from the control logic unit 404 on data line 452b according to logic Table 8b and connected to an output data line 6l8. The output data line 6l8 passes data to the pipeline register 3 6 which forms an address field 620 of a revised operand B 622. Input 6l6a is like to input 6l4f; input 6l6b is like to input 6l4d; input 6l6c is like to input 6l4e; input 6l6d is like to input 6l4b; and input 6l6e is like to input 6l4c. One of the inputs 6l6a to 6l6e is selected and connected to the output data line 6l8 in response to a signal received from the control logic unit 4θ4 along data line 52b according to Table 8b. The reference letter of the selected input 6l6a to 6l6e is given in the column of Table 8b headed opSel B. The third multiplexer 604 has two inputs 624a and 624b. Input 624a is like to input 6l4e and input 624b is like to input 6l4c. The multiplexer 6θ4 has an output data line 626 passes data to the pipeline register 3 6 which forms an address field 628 of a revised operand A 630. One of the inputs 624a and 624b is selected and connected to the output data line 626 in response to a signal received from the control logic unit 404 along data line 452a according to Table 8b. The reference letter of the selected input 624a or 624b is given in the column of Table 8b headed opSel A. Also shown in Figure 5 is the multiplexer 306 which has three inputs 632a to 632c. The input 632a carries the operation code 58 * , the input 632b carries a read from memory operation code and the input 632c carries a write to memory code. The multiplexer 306 has an output data line 63 which passes a revised operation code 636 to the pipeline register 346. One of the inputs 632a to 632c is selected and connected to the output data line 634 in response to a signal received from the control logic unit 4θ4 along data line 460 according to Table 8c. The input selected by the control logic unit 4θ4 is given in Table 8c in the column under the heading Opcode Sel. Where an entry in the column is shown as "instr", input 632a is selected; where an entry is shown as "readMem", input 632b is selected; and where an entry is shown as "writeMem" , input 632c is selected. Operands A to C 630, 622 and 610 each have a respective operand type field 638, 640, and 642. The operand type fields 638, 640, and 642 are transmitted along data lines 348a to 348c respectively from respective hit/miss logic units 4θ6a to 4θ6c according to Tables 6 and 7- The pipeline register 3 6 is updated on the receipt of the clock signal on the clock control line 38. Referring now to Figure 6 and Figure 7 together there is shown the ALU stage 27. In Figure 6 there is shown a controller 700 for the ALU stage 27. The controller 700 receives the type fields 638, 640, and 642 of operands A 63O, B 622, and C 610 from the pipeline register 346 along a data bus 710 comprising data lines 710a to 710c (not shown) . The controller 700 also receives a "Done" signal from the memory interface unit 23 via a control line 712, indicating that a requested external memory cycle has been completed; for a read operation, it indicates that the requested data is ready on an input bus (not shown) and for a write operation, it indicates that the data has been written. The controller 700 receives the operation code 636 from the pipeline register 346 via a data line 714 and a valid instruction signal from the cache maintenance stage via the control line 34. The clock control signal on the clock control line 35 is inverted by a NOT gate 716. The inverted clock signal is then passed to a second NOT gate 718, and two NAND gates 720 and 722. The second NOT gate 718 reproduces the phase of the original clock signal which is passed to the controller 700 along a clock control line 724. The operand types of the operands in the pipeline register 346 may be either regAddr, memAddr, or constant, as given by Table 8b. The operation code may be either readMem, writeMem, a two operand instruction, or a three operand instruction. The controller 700 has two types of outputs: clock enables and general control signals. The clock enables are to ensure the correct operation of various registers within the ALU stage 27. A first clock enable is output via a control line 726 to the NAND gate 720. The gate 720 carries out a NAND operation on the first clock enable signal and the inverted clock control signal and passes the result via a control line 728 to a temporary register (not shown) in the ALU stage which holds popped data when a double pop operation is carried out, for example the instruction "add ToS, ToS, ToS" . A second clock enable signal is output via a control line 730 to the NAND gate 722. The gate 722 carries out a NAND operation on the second clock enable signal and the inverted clock control signal and passes the result to a register file in the ALU stage along a control line 731 as a WrReg signal. The WrReg signal controls the writing of the results of an instruction back into the register file. The general control signals are:- (i) a stall signal, which is output on the control line 36 to previous stages of the pipeline; (ii) a latch data in signal, which is output on a control line 732 to control a data latch of data coming from the external memory 21; (iii) a Read signal, which initiates an external memory read operation and is passed to the memory interface unit 23 via a control line 734; (iv) a Write signal, which initiates an external memory write operation and is passed to the memory interface unit 23 via a control line 736; (v) a Select Operand signal, which is output via a data line 738 to an arithmetic logic unit of the ALU stage and is used to determine what data is input into two ports of the ALU; (vi) an ALU operation signal, which is output via a data line 740 and is the instruction code for the ALU, the ALU operation signal may be different from the current operation code as this may need to be overwritten to pass data through the ALU; and (vii) a select address signal, which is output via a control line 7 2 and controls a multiplexer on an address bus to the external memory which can select either of the three operands. The controller 700 also generates a stall signal on the control line 34 to halt previous stages in the pipeline whilst the ALU stage 27 is processing an instruction. Figure 7 shows a diagram of the ALU stage 27 in which the controller 700 has been omitted for clarity. The ALU stage comprises the controller 700, a dual port register file 750, an arithmetic logic unit 76θ, and various other components. Operands are stored in the dual port register file 750 and accessed in pairs using a register file address presented in the incoming instruction stream as the address fields 628 and 620. These operands are taken through the ALU 76O, processed and returned to the register file 750 at an address specified by the address field 608 of operand C 610. As well as receiving operands from the register file 750, the ALU 76O may also receive operands from external memory 22 (not shown) or directly from the pipeline register 346 when the address fields of operands A or B 63O or 622 contain numerical constants. The address fields of operands A, B, and C 63O, 622, and 610 may either contain a register address, a constant or a memory address. The address field 628 of operand A may be passed via a data line 78O to the register file 750, via a data line 782 to a three port multiplexer 784 and via a data line 786 to a four input multiplexer 788 which is connected to a first port 790 of the ALU 760. The address field 620 of operand B 622 may be passed via a data line 792 to the register file 750, via a data line 79 to the multiplexer 784 and via a data line 796 to a four input multiplexer 798 which is connected to a second port 800 of the ALU 76O. The address field 608 of operand C 610 may be passed via a data line 802 to the register file 750 and via a data line 8θ4 to the multiplexer 784. The register file 750 puts the contents of the register location addressed by the address field on data line 78O onto an output data line 8l0 which passes the contents to the multiplexer 788. Similarly, the contents of the register location addressed by the address field on data line 792 are placed on an output data line 812 which passes the contents of the register location to the multiplexer 798. Data read from the external memory 21 (not shown) is passed via a data line 8l4 to a data latch 8l6. The data latch 8l6 is controlled by the controller 700 via the control line 732. The data is passed from the data latch 8l6 directly to the multiplexers 788 and 798 along data lines 8l8 and 820 respectively and to a temporary register 822 along a data line 824. The contents of the temporary register 822 are updated upon receipt of a control signal from the controller 700 via the control line 728 when an operation requires a double-pop of data from the external memory. The contents of the temporary register are passed to the multiplexer 788 along a data line 826 and to the multiplexer 798 along a data line 828. The multiplexer 788 receives a select operand signal from the controller 700 along a control line 738a and this signal is used to select an operand for the first port 790 of the ALU 76O from the operands supplied on the data lines 786, 810, 8l8, and 826. Similarly, the multiplexer 798 receives a select operand signal from the controller 700 along a control line 738b and this signal is used to select an operand for the second port 800 of the ALU 760 from the operands supplied on the data lines 796, 812, 820, and 828. The controller 700 receives the operand types of operands A, B, and C 630, 622, and 610 via data lines 710a to 710c and the operation code 636 via data line 7l4. The controller 700 then supplies the ALU 760 with an instruction code via data line 740. Acting on this instruction code, the ALU may pass one of the operands from either of the ports 790 or 800 through unchanged to an output 830 or it may operate on one or both of the operands according to the instruction code with which it has been supplied and pass the result of this operation to the output 83O. Data from the output 830 passes to the external memory along a data line 832 and to the register file 750 along a data line 83 . The data passed to the register file 750 along data line 834 is written at the address supplied on data line 802 under the control of the WrReg signal on the control line 73 . When an external memory operation is being performed, it is necessary to provide the memory with the correct address. This address is provided on a data line 836 from the multiplexer 784. In response to a signal received on the control line 742, the multiplexer 784 selects the address from one of the data lines 804, 794, and 782. Although the stack base address and the top of stack address indicated by a box 85O in the pipeline register 3 6 are supplied to the ALU stage 27, in the present embodiment they are not utilised by the stage. In alternative embodiments these addresses may be saved to the register file or the external memory. Whilst the ALU 760 is shown in Figure 7 as a single unit, it may comprise a plurality of individual processing elements such as a divider, a multiplier, a floating point processor and an integer arithmentic unit. The ALU 76O is a conventional register file based unit. Operands are stored in the two port register file 750 and accessed in pairs with a register file address presented 35 in the incoming instruction stream. These operands are taken through the ALU (when appropriate) , processed and returned to the register file (when appropriate) at an address specified in operand C in the instruction stream. If necessary, data may be taken from the external memory (popped) instead of the register file. By the time an instruction reaches the ALU stage, all operands have either been translated to a register address, a memory address or a constant. The controller logic ensures that the correct data paths are set up to provide the ALU with the correct operand value. There are no special cache management instructions within the ALU stage. The ALU stage knows nothing of the stack or pushes and pops to the stack. The only actions the ALU stage deals with are those that deal with the register 750 and the external memory. The operation of the ALU stage controller 27 may be described with the help of a state diagram shown in Figure 8. The controller has eight states: a normal state 900, a readMeml state 902, a readMem2 state 904, a readMeπβ state 906, a readMem4 state 908, a readMem5 state 910, a writeMeml state 912, and a writeMem2 state 1 . From the normal state 900, the controller may either proceed to readMeml state 902 or writeMeml state 912, as shown by arrows 916 and 18 respectively. The transition indicated by arrow 916 is dependent on Condition A of Table 9 being satisfied and the transition indicated by arrow 918 is dependent on Condition E being satisfied. From the readMeml state 902, the controller moves to the readMem2 state 904, as indicated by an arrow 920, provided Condition B is satisfied. From readMem2 the controller may either return to the normal state 900, as indicated by an arrow 922, or proceed to readMem3 state 906, as indicated by an arrow 24. If Condition C is satisfied the transition is that indicated by arrow 924, and if Condition C is not satisfied, the transition is that indicated by arrow 922. From readMem3 state 906, the controller may either proceed to readMem4 state 908, indicated by an arrow 926 if Condition D is not satisfied or to writeMeml state if Condition D is satisfied, as indicated by an arrow 928. From the readMem4 state 908, the controller proceeds to readMem5 state, indicated by an arrow 930 and thence to the normal state 900 as indicated by an arrow 932. From the writeMeml state, the controller proceeds to the writeMem2 state provided Condition B is satisfied, as indicated by an arrow 934, and thence to the normal state as indicated by an arrow 936. In Table 9, the conditions referred to regarding Figure 8 are set out. For each condition to be satisfied, a variety of input signals must have a particular value. For Condition A to be satisfied, the instrValidln signal on control line 34 must be true, and the operation code on data line 71 be either a read from memory code, or a write to memory code with the operand type of operand B on data line 710b being a memAddr type, or a two operand instruction with the operand type of operand B on data line 710b being a memAddr type, or a three operand instruction with either the operand type of operand A on data line 710a or the operand type of operand B on data line 710b being a memAddr type. Condition B is satisfied when the Done signal from the memory interface unit 23 on control line 712 is true. Condition C is satisfied when the operation code is a write to memory and the operand type of operand B is a memAddr type or when the operation code is a three operand instruction and both the operand types of operand A and B are memAddr types, in which case the temporary register 822 must be loaded. Condition D is satisfied when the operation code is a write to memory code and Condition E is satisfied when the operation code is a write to memory code and the operand type of operand B is not a memAddr type. There are eight routines associated with the state diagram of Figure 8 which give the actions to be performed by the controller 700 before moving from one state to the next. The eight routines are as follows. (i) normalCycle: actions carried out whenever the external memory is not used. The select address signal on line 742 does not require setting, since no data is sent to the external memory. The latch data in signal on control line 732 is held true since a read cycle may have occurred in a previous cycle and input data needs to be latched so it is stable for writing into the register file; otherwise, the latch data signal status is not relevant since data for the ALU is selected by the multiplexers 788 and 798. Data is only written to the register file 750 if operand C is a register address, and not a constant, and a valid instruction is being processed, as indicated by the valid instruction signal being true on the control line 3 . The outputs of the controller 700 are: Stall signal, control line 36 - false latch data in signal, control line 732 - true Read signal, control line 734 - false Write signal, control line 736 - false Select operand A, control line 738a - see Table 10 Select operand B, control line 738b - see Table 10 ALU operation signal, data line 740 - operation code 636 select address signal, control line 742 - irrelevant first clock enable signal, control line 726 - false second clock enable signal, control line 730 - if (type field 642 = regAddr and valid instruction signal on control line 34 = true) then true, else false. (ii) startReadCycle: Previous stages of the pipeline are stalled whilst the ALU accesses the external memory. The data latch 8l6 is opened and a memory read cycle is started. The address that is used for the read is dependent on the current instruction being run. Normally it is operand B except where a three operand instruction for which data for port 7 0 only is to be popped is being run, in which case operand A is used. The outputs of the controller 700 are as follows: Stall signal, control line 36 - true latch data in signal, control line 732 - false Read signal, control line 734 - true Write signal, control line 736 - false Select operand A, control line 738a - see Table 10 Select operand B, control line 738b - see Table 10 ALU operation signal, data line 7 0 - operation code 636 select address signal, control line 742 - if operation code 636 = three operand instruction, and type field 640 is not memAddr and type field 638 = memAddr then select data line 782, else data line 794 first clock enable signal, control line 726 - false second clock enable signal, control line 730 - false. (iii) completeReadCycle: release the stall to allow the pipeline to restart as well as returning the Read signal on control line 734 to false. If both operands A and B are being popped, use the temporary register 822 to supply the ALU port 800 with data; if the operation code is a readMem, the ALU port 800 is supplied with data from data line 820, otherwise Table 10 is followed. If the operation code is a readMem then the ALU 760 passes operand B straight through unchanged to the output 830. Operand B is used as the address to external memory, unless just the input to port 790 is being popped from memory, in which case operand A is used. The outputs of the controller 700 are as follows: Stall signal, control line 36 - false latch data in signal, control line 732 - true Read signal, control line 734 - false Write signal, control line 736 - false Select operand B, control line 738b - if operation code 636 = three operand instruction, and type field 640 = memAddr, and type field 638 = memAddr then select data line 828, else if operation code 636 = readMem then select data line 820, else see Table 10 Select operand A, control line 738a - see Table 10 ALU operation signal, data line 7 0 - if operation code 636 = readMem then passB, else operation code 636 select address signal, control line 7 2 - if operation code 636 = three operand instruction and type field 638 = memAddr then select data line 782, else data line 794 first clock enable signal, control line 726 - true second clock enable signal, control line 730 - if type field 642 = regAddr true, else false. (iv) completeTempCycle: keep the Stall signal true to stop the pipeline updating since the ALU stage has not yet finished. Use operand B as the address to external memory unless just the input to port 790 is being popped from memory, in which case operand A is used. The outputs of the controller 700 are as follows: Stall signal, control line 36 - true latch data in signal, control line 732 - true Read signal, control line 734 - false Write signal, control line 736 - false Select operand B, control line 738b - see Table 10 Select operand A, control line 738a - see Table 10 ALU operation signal, data line 740 - operation code 636 select address signal, control line 742 - if operation code 636 = three operand instruction and type field 638 = memAddr then select data line 782, else data line 794 first clock enable signal, control line 726 - true second clock enable signal, control line 730 - false. (v) startSecondReadCycle: start a second memory read cycle. When two operands are popped, the first is stored in the temporary register 822 and the second obtained directly from memory. The outputs of the controller 700 are as follows: Stall signal, control line 36 - true latch data in signal, control line 732 - false Read signal, control line 734 - true Write signal, control line 73 - false Select operand B, control line 738b - select data line 820 Select operand A, control line 738a - select data line 826 ALU operation signal, data line 740 - operation code 636 select address signal, control line 7 2 - if operation code 636 = three operand instruction and type field 638 = memAddr then select data line 782, else data line 794 first clock enable signal, control line 726 - false second clock enable signal, control line 730 - false. (vi) completeSecondReadCycle: complete the second read cycle. The outputs of the controller 700 are as follows: Stall signal, control line 36 - false latch data in signal, control line 732 - true Read signal, control line 734 - false Write signal, control line 736 - false Select operand B, control line 738b - select data line 820 Select operand A, control line 738a - select data line 826 ALU operation signal, data line 7 0 - if operation code 636 = readMem then passB, else operation code 636 select address signal, control line 7 2 - if operation code 636 = three operand instruction and type field 638 = memAddr then select data line 782, else data line 794 first clock enable signal, control line 7 6 - false second clock enable signal, control line 730 - true. (vii) startWriteCycle: start a write cycle. The outputs of the controller 700 are as follows: Stall signal, control line 36 - true latch data in signal, control line 732 - false Read signal, control line 734 - false Write signal, control line 736 - true Select operand B, control line 738b - if operation code 636 = writeMem and type field 640 = memAddr then select data line 828, else see Table 10 Select operand A, control line 738a - select data line 810 ALU operation signal, data line 7 0 - passB select address signal, control line 742 - select data line 804 first clock enable signal, control line 726 - false second clock enable signal, control line 730 - false. (viii) completeWriteCycle: complete the write cycle. The outputs of the controller 700 are as follows: Stall signal, control line 36 - false latch data in signal, control line 732 - true Read signal, control line 73 - false Write signal, control line 736 - false Select operand B, control line 738b - if operation code 636 = writeMem and type field 640 = memAddr then select data line 828, else see Table 10 Select operand A, control line 738a - see Table 10 ALU operation signal, data line 740 - passB select address signal, control line 742 - if operation code 636 = three operand instruction and type field 638 = memAddr then select data line 782, else data line 79 first clock enable signal, control line 726 - false second clock enable signal, control line 730 - false. Where an ALU operation signal on data line 740 is given as "passB" in the above cycles, this means pass operand B through the ALU unchanged. Where an output for the controller 700 has not been given in the above, it is the same as in a previous cycle, and has not been updated. Table 10 shows the data lines selected by the control lines 738a and 738b in response to the three types of operand held in type fields 638 and 640 respectively. For each of the states shown in the state diagram of Figure 8, which of the eight routines are implemented is determined by the satisfying of Conditions A to E given in Table 9- In the normal state 900, if Condition A is satisfied, then startReadCycle is implemented and the next state is state 902, if Condition E is satisfied startWriteCycle is implemented and the next state is state 912, otherwise normalCycle is implemented and the state stays as state 900. The controller stays in state 902 until condition B is satisfied, whereupon the latch data in signal on control line 732 is held true and the controller moves to state 904. If Condition C is satisfied then the completeTempCycle routine is implemented and the state moves to state 906, otherwise the completeReadCycle routine is implemented and the state moves to state 900. Once in state 906, if Condition D is satisfied, the startWriteCycle routine is implemented and the state moves to state 912, otherwise the startSecondReadCycle routine is implemented and the state moves to state 908. In state 908 if Condition B is satisfied, the latch data in signal on control line 732 is held true and the state moves to state 910, otherwise the state remains as state 908. In state 910, the completeReadCycle routine is implemented and the state moves to state 900. In state 91 if Condition B is satisfied, the latch data in signal on control line 732 is held true and the state moves to state 914, otherwise the state remains as state 912. In state 914, the completeWriteCycle routine is implemented and the state returns to state 900. Whilst a particular arrangement for the ALU stage has been described above, other implementations are possible. On each clock cycle, an instruction is passed from the cache maintenance stage to the ALU stage. The cache maintenance stage injects instructions into the instruction pipeline if memory read or memory write operations are required. The ALU stage is not aware as to whether the instructions it receives are instructions relating to program instructions or instructions relating to maintenance of the register 750. A person skilled in the design of computer processors would be capable of designing an alternative arithmetic logic unit stage. Such an alternative ALU stage would comprise a register equivalent to the register 750, an ALU, a controller for controlling the operation of the ALU, and connections for accessing the external memory.

Claims: CLAIMS 1. A data cache (22) for a pipelined processor, the data cache being arranged to provide an arithmetic logic unit (ALU) (760) with stored data, characterised in that the data cache (22) is included within and extends over a plurality of stages within the pipeline. 2. A data cache according to claim 1 characterised in that the data cache comprises a cache controller and a data store. 3- A data cache according to claim 2 characterised in that the cache controller and the data store are contained within different stages of the pipeline. 4. A data cache according to claim 3 characterised in that the data store is contained within the same stage as the ALU. 5- A data cache according to claim 1 characterised in that the pipelined processor is a stack based processor. 6. A data cache according to claim 4 characterised in that the pipelined processor is a stack based processor and the cache controller comprises an address calculation stage and a cache maintenance stage. 7. A data cache according to claim 6 characterised in that the data store is a register file. 8. A data cache according to claim 6 or 7 characterised in that the cache maintenance stage includes random access memory (RAM) arranged to store information concerning the storage of data within the data store, such information being used by the data cache to determine whether a particular instruction requires an external memory operation to be carried out prior to the ALU processing the instruction. 9. A data cache according to claim 8 characterised in that the RAM is three port, three access RAM. 10. A pipelined computer processor (20) incorporating a data cache (22) , the data cache being arranged to provide an arithmetic logic unit (ALU) (760) with stored data, characterised in that the data cache (22) is included within and extends over a plurality of stages within the pipeline. 11. A processor according to claim 10 characterised in that the data cache comprises a cache controller and a data store. 12. A processor according to claim 11 characterised in that the cache controller and the data store are contained within different stages of the pipeline. 13. A processor according to claim 12 characterised in that the data store is contained within the same stage as the ALU. 14. A processor according to any of claims 10 to 13 characterised in that the processor is a stack based processor. 15. A processor according to claim 13 characterised in that the processor is a stack based processor and the cache controller comprises an address calculation stage and a cache maintenance stage. 16. A processor according to claim 1 characterised in that the data store is a register file. 17. A processor according to claim 15 or 16 characterised in that the cache maintenance stage includes random access memory (RAM) arranged to store information concerning the storage of data within the data store, such information being used by the data cache to determine whether a particular instruction requires an external memory operation to be carried out prior to the ALU processing the instruction. 18. A processor according to claim 17 characterised in that the RAM is three port, three access RAM. 19- A data cache (22 ) for a stack based processor (20), the data cache being arranged to provide an arithmetic logic unit (ALU) (760) with stored data. 20. A data cache according to Claim 19 characterised in that the data cache is included within and extends over a plurality of stages of a pipelined processor. 21. A data cache according to Claim 20 characterised in that the cache comprises: (i) an ALU stage which includes the ALU and a register file for storing data; (ii) an address calculation stage for translating location references of operands; and (iii) a cache maintenance stage for maintaining data stored in the register file.

Inventors: FIELD-RICHARDS HUGH SHERWOOD, WISEMAN SIMON ROBERT, FIELD-RICHARDS, HUGH, SHERWOOD, WISEMAN, SIMON, ROBERT
Applicants: FIELD RICHARDS HUGH SHERWOOD, SECR DEFENCE, WISEMAN SIMON ROBERT, FIELD-RICHARDS, HUGH, SHERWOOD, THE SECRETARY OF STATE FOR DEFENCE, WISEMAN, SIMON, ROBERT
Application year: 1995
Main classification: G06F9
IPC codes: G06F9, G06F12