Synthesis subband filter

Abstract: A synthesis subband filter includes a matrixing value processor (10) for obtaining a shifted matrixing value and a mapping value by an input subband sample and matrixing value, a constant storing unit (30) for storing a matrixing constant value and an operational constant value, a multiplication operator (41) for a multiplication operation by data from the matrixing value processor and constant storing unit (42), an addition operator (51) for cumulatively adding the operation values from the multiplication operator to supply the matrixing value and a subband sample, and an output unit for supplying the subband sample from the additional operator. Thus, as compared with using a DSP or microprocessor, a program memory is not needed and the number of cycles required for obtaining one sample is decreased to enable high speed processing while operating necessary clocks at a low frequency. Furthermore, the filter is temporally divided for an audio signal of multichannel to be used per channel to apply a single synthesis subband filter to an audio decoder of multichannel.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synthesis subband filter, and more particularly to a synthesis subband filter for decoding a digital audio signal. 2. Description of the Prior Art There are several methods for coding a digital audio signal, in which a motion picture expert group (MPEG) employs a method for differing the quantization level in accordance with the properties per output signal of respective subbands through subband filters. The digital audio signal coded as mentioned above is subjected to an inverse quantization to be restored into the original audio signal via a synthesis subband filter. FIG. 1 is a flowchart illustrating the operational process of a general synthesis subband filter. When a band-pass filter is used to compressively code an audio signal, a synthesis filter must be formed to restore the audio signal. The general restoration process stipulated by the MPEG will be described with reference to FIG. 1. To begin with, 32 new subband samples Si (where i = 0, 1,..., 31) are newly-received (step 1). Using the received 32 subband samples Si, a matrixing value Vi is shifted by 64s (step 2), which can be written as: Vi = V [i - 64] where i is a number from 1023 to 64. After the shifting, the matrixing value Vi is calculated as below (step 3): where i is a number from 0 to 63, so that 64 matrixing values Vi are formed. After the matrixing, a mapping is performed to form a mapping value Ui as defined in equations (3) and (4). U[i * 64 + j] = V[i * 128 + j] U[i * 64 + 32 + 1] = V[i * 128 + 96 + i] where the mapping value Ui is obtained such that i is a number from 0 to 7, and j is a number from 0 to 31. Then, an operational process is carried to give an operational value Wi as expressed in the following equation (step 5). That is, Wi = Ui * Di where i numbers 512 from 0 to 511. Thereafter, 32 sample values Sj are calculated according to the following equation (step 6): where j is a number from 0 to 31. After the calculation of 32 samples, reconstructed 32 pulse-coded modulation (PCM) samples are supplied (step 7). In order to restore the audio signal coded according to the above algorithm, a general digital signal processor or microprocessor, a data memory and a program memory is used. In more detail, when an algorithm to be executed is written on a program memory, a processor decodes the program and reads out a subband-filtered signal on a data memory to perform an operation according to the decoding, and the result is supplied to the data memory, thereby carrying out the synthesis filtering. However, because the algorithm is conventionally embodied by means of the general processor, many cycles are required for operating to impede high speed processing, which, in turn, necessarily speeds up the clocks received into the processor for conducting a real-time processing. Therefore, the price of the processor is raised, and further increased when processing a signal of multichannel. Prior art document, Maturi G: 'Single chip MPEG audio decoder', IEEE Transactions on Consumer Electronics, US, vol.38, no.3,1 August 1992, pp348-355, discloses an audio decoder architecture as set out in the pre-characterising portion of claim 1. SUMMARY OF THE INVENTION Particular embodiments of the present invention are directed to solving the above-described problems. Accordingly, it is an object of these embodiments to provide a subband filter for performing a synthesis subband filtering in high speed and enabling the multichannel processing. The invention provides a synthesis subband filter as set out in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS The above objects and other advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: FIG. 1 is a flow chart illustrating the operational process of a general synthesis subband filter; FIG. 2 is a construction view showing one embodiment of a synthesis subband filter according to the present invention; FIG. 3 is a construction view showing another embodiment of the synthesis subband filter according to the present invention; FIG. 4A is a detailed construction view showing one embodiment of the matrixing value processor of FIGS. 2 and 3; FIG. 4B is a detailed construction view showing another embodiment of the matrixing value processor of FIGS. 2 and 3; FIG. 5A is a detailed construction view showing one embodiment of the output sample unit of FIGS. 2 and 3; FIG. 5B is a detailed construction view showing another embodiment of the output sample unit of FIGS. 2 and 3; FIG. 6A is a construction view showing the matrixing value processor in case of a multichannel; and FIG. 6B is a construction showing the output unit in case of the multichannel. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring FIG. 2, one embodiment of a synthesis subband filter will be described in detail. The synthesis subband filter shown in FIG. 2, includes a matrixing value processor 10, a first register (not shown), a constant storing unit 30, a multiplication operator 40, an addition operator 50 and an output unit 60. The matrixing value processor 10 obtains a shifted matrixing value Vi and a mapping value Ui as expressed by equations (7), (8) and (9) by means of 32 matrixing values V and subband samples Si from the addition operator 50, that is: Vi = V[i - 64] where i is a constant from 1023 to 64. U[i * 64 + j] = V[i * 128 + j] U[i * 64 + 32 + i] = V[i * 128 + 96 + i] where i is a constant from 0 to 7, and j is a constant from 0 to 31. The first register temporarily stores the output of the matrixing value processor 10 to be in tune with timing. The constant storing unit 30 stores a matrixing constant value Nik and an operational constant value Di, and supplies the stored constant values Nik and Di to the multiplication operator 40. The constant storing unit 30 is formed of two counters 31 and 32, two ROMs 33 and 34, and a multiplexer 35. The counter 31 counts a clock CLK1 as an input thereof to output the counted clock to the ROM 33. The ROM 33 stores the preset matrixing constant value Nik, and sequentially supplies the stored matrixing constant value Nik in accordance with the output of the counter 31. The counter 32 counts a clock CLK2 as an input thereof to output the counted clock to the ROM 34. The ROM 34 stores the preset operational constant value Di, and sequentially supplies the stored operational constant value Di in accordance with the output of the counter 32. The multiplexer 35 selectively receives the matrixing constant value Nik from the ROM 33 or the operational constant value Di from the ROM 34 to supply the selected value to the multiplication operator 40. The clock CLK1 allows the counter 31 to count to sequentially supply the matrixing constant value Nik stored in the ROM 33, and the clock CLK2 allows the counter 32 to count to sequentially supply the operational constant value Di stored in the ROM 34. The matrixing constant value Nik and operational constant value Di from the ROMs 33 and 34 are selected by the multiplexer 35 to be supplied to the multiplication operator 40. In other words, the multiplexer 35 selects the output of the ROM 33 to provide the matrixing constant value Nik to the multiplication operator 40 when the multiplication operator 40 conducts the multiplication for matrixing; otherwise it selects the output of the ROM 34 to provide the operational constant value Di when the multiplication operator 40 conducts the multiplication. More specifically, the multiplexer 35 selects the output of the ROM 33 when the operation defined in the following equation (10) is performed, or the output of the ROM 34 when performing the operation defined in equation (11): Ak = Nik * Sk Wi = Ui * Di The multiplication operator 40 carries out the multiplication by means of a subband sample Sk from the first register and the matrixing constant value Nik from the constant storing unit 30. Also, it carries out the multiplication as expressed in equations (12) and (13) by means of the mapping value Ui from the first register and the operational constant value Di from the constant storing unit 30. Ak = Nik * Sk where k is a constant from 0 to 31, and Wi = Ui * Di where i is a constant from 0 to 511. The multiplication operator 40 is formed of a multiplier 41 and a register 42. The multiplier 41 conducts the multiplication operation as expressed in equations (14) and (15) by means of the subband sample Sk and mapping value Ui from the matrixing value processor 10 via the first register and the constant value Nik or Di from the multiplexer 35 of the constant storing unit 30. Ak = Nik * Sk where k is a constant from 0 to 31, and Wi = Ui * Di where i is a constant from 0 to 511. The register 42 temporarily stores data from the multiplier 41. The subband sample Sk from the matrixing value processor 10 via the first register and the matrixing constant value Nik from the multiplexer 35 of the constant storing unit 30 are multiplied in accordance with the following equation (16) in the multiplier 41, that is: Ak = Nik * Sk where k is a constant from 0 to 31. In addition to this, the mapping value Ui from the matrixing value processor 10 via the first register and the operational constant value Di from the multiplexer 35 of the constant storing unit 30 are multiplied in accordance with the following equation (17) in the multiplier 41, that is: Wi = Ui * Di where i is a constant from 0 to 511. The data subjected to the multiplication operation in the multiplier 41 is temporarily stored in the register 42 prior to being output. The addition operator 50 adds the operational values from the multiplication operator 40 to complete the matrixing operation and sample calculation as equations (18) and (19) below: where i is a constant from 0 to 63, and where j is a constant from 0 to 31. The matrixing operation and 32 sample calculation are carried out as described above. The addition operator 50 is formed of two adders 51 and 56, a register 52, an output sampler 54, and a FIFO 53. The adder 51 passes intact the multiplied operation value Wi from the register 42 of the multiplication operator 40, and cumulatively adds the multiplied operational value Ak from the register 42 of the multiplication operation 40 to supply the matrixing values Vi as specified in equations (20) and (21). where i is a constant from 0 to 63. The register 52 supplies the values added in the adder 51 to the adder 51 to repeat the cumulative addition. The matrixing value Vi cumulatively added in the adder 51 to be supplied to the register 52 is provided to the FIFO 53 and the matrixing value processor 10. The FIFO 53 stores the multiplied operation value Wi unchanged even passing through the adder 51 and register 52, and supplies the unchanged value to the adder 56. The adder 56 cumulatively adds the multiplied operation value Wi stored in the FIFO 53 to output 32 subband samples Sj which is written as: where j is a constant from 0 to 31. The output sampler 54 stores an intermediately-calculated value of the subband sample from the adder 56. The multiplied operation value Ak from the register 42 of the multiplication operator 40 is primarily added with zero, stored in the register 52, and again supplied to the adder 51 to be continuously and cumulatively added through the adder 51 and register 52, so that the matrixing value Vi is produced as equation (23): where i is a constant from 0 to 63. The cumulatively added matrixing value Vi is provided to the matrixing value processor 10. The multiplied operation value Wi from the register 42 of the multiplication operator 40 passes through the adder 51 and register 52 intact prior to being stored in the FIFO 53, and cumulatively added through the adder 56 and output sampler 54, so that the subband sample Sj is produced as: where j is a constant from 0 to 31. In more detail, the multiplied operation value Wi from the register 42 of the multiplication operator 40 is stored in the FIFO 53 and is primarily added with zero in the adder 56. Then, the result is repeatedly supplied to the adder 56 via the output sampler 54 to continuously and cumulatively added via the adder 56, output sampler 54 and FIFO 53, finally supplying the subband sample Sj. The output unit 60 consists of a FIFO 61 to store 32 subband samples Sj finally supplied from the adder 56 of the addition operator 50 to provide the stored subband samples Sj to a digital/analog converter DAC. The previous 32 subband samples Si are temporarily stored in the matrixing processor 10 to be multiplied in the multiplication operator 40 by the matrixing constant value Nik from the constant storing unit 30, and cumulatively added in the adder 51 of the addition operator 50 to supply the matrixing value Vi to the matrixing value processor 10. The matrixing value Vi from the adder 51 of the addition operator 50 is shifted and mapped in the matrixing value processor 10 to be output as the mapping value Ui. The mapping value Ui from the matrixing value processor 10 is multiplied by the operational constant value Di from the constant storing unit 30, and cumulatively added in the adder 56 of the addition operator 50 to be output as 32 subband samples Sj via the output unit 60. FIG. 3 is a construction view showing another embodiment of the synthesis subband filter which includes a matrixing value processor 10, a constant storing unit 30, a multiplication operator 40, an addition operator 70 and an output unit 60. Since the operation and construction of the matrixing value processor 10, constant storing unit 30, multiplication operator 40 and output unit 60 are the same as those of one embodiment of the synthesis subband filter shown in FIG. 2, only the construction and operation of the addition operator 70 will be described in detail. The addition operator 70 adds the operational values from the multiplication operator 40 to complete the matrixing operation and sample calculation in accordance with the following equations (25) and (26): where i is a constant from 0 to 63, and where j is a constant from 0 to 31. The matrixing operation and 32 sample calculation are carried out as described above. The addition operator 70 is formed of two multiplexers 72 and 73, an adder 75, an output sampler 71, a FIFO 74 and a register 76. The multiplexers 72 and 73 serve for temporally multiplexing the operations of the matrixing value Vi and subband sample Sj. The multiplexer 73 selects the multiplied operation value Ak or Wi from the register 42 of the multiplication operator 40 to provide the selected value to the adder 75. The adder 75 cumulatively operates the multiplied operation value Wi and the multiplied operational value Ak both from the multiplexer 73, respectively, to output the matrixing value Vi and subband sample Sj. The FIFO 74 stores the multiplied operation value Wi from the multiplexer 73 to again supply the stored value to the multiplexer 73. The output sampler 71 stores the intermediately-calculated value of the subband sample from the adder 75 to supply the stored value to the multiplexer 72 in tune with timing. The register 76 stores the matrixing value Vi cumulatively added in the adder 75 to supply the stored value to the multiplexer 72, and supplies the finally-output matrixing value Vi to the matrixing value processor 10. Also, 32 subband samples Sj cumulatively added in the adder 75 prior to being finally output are stored in the register 76 to be supplied to the output unit 60. The multiplexer 72 selects the intermediately-calculated subband sample from the register 76 and output sampler 71 and the intermediately-calculated matrixing value from the register 76 to produce the selected value to the adder 75. First, in case that the 32 subband samples Sj are calculated, the multiplied operation value Wi from the register 42 of the multiplication operator 40 is selected by the multiplexer 73, added with zero in the adder 75, stored in the output sampler 71, and then stored in the output sampler 71 to be supplied to the multiplexer 72. Also the multiplied operation value Wi from the register 42 of the multiplication operator 40 passes through the adder 75 intact to be stored in the FIFO 74, and is supplied to the adder 75 via the multiplexer 73. The intermediately-calculated value of the subband sample from the output sampler 71 is input to be selected in the multiplexer 72 and output to the adder 75 to be cumulatively added to the multiplied operation value Wi of the FIFO 74 selected by the multiplexer 73 as below: where j is a constant from 0 to 31. The finally-output subband sample Sj having been cumulatively added in the adder 75 is stored in the register 76 to be supplied to the output unit 60. Second, in case that the matrixing value Vi is calculated, the multiplied operation value Ak from the register 42 of the multiplication operator 40 is selected by the multiplexer 73 to be primarily added with zero, stored in the register 76 to be provided to the multiplexer 72. The multiplied operation value Ak from the register 42 of the multiplication operator 40 is received via the multiplexer 73, and cumulatively added with the previously-added multiplied operation value from the adder 75 to the multiplexer 72 as defined in the following equation (28): where i is a constant from 0 to 63. The finally-output matrixing value Vi having been added in the adder 75 is produced to the matrixing value processor 10 via the register 76. FIG. 4A is a detailed construction view showing one embodiment of the matrixing value processor 10 of FIGS. 2 and 3, and FIG. 4B is a detailed construction view showing another embodiment of the matrixing value processor 10. The matrixing value processor 10 which utilizes a multiple FIFO, as illustrated in FIG. 4A, includes two multiplexers 11 and 13, a FIFO 12 for storing the subband sample Si, and multiple FIFO 14 consisting of 32 FIFOs 140 to 171 for storing the matrixing value Vi. The multiplexer 11 selects the subband sample from the FIFO 12 and newly-received subband sample Si to supply the selected sample to the FIFO 12. The FIFO 12 stores the subband sample Si from the multiplexer 11, and provides the stored subband sample Si in accordance with a subband sample output enable signal OE S to the multiplier 41 via the first register. The multiplexer 13 selects the matrixing value Vi from the multiple FIFO 14 or the matrixing value Vi from the adder 51 or 75 of the addition operator 50 or 70 to output the selected value to the multiple FIFO 14. The multiple FIFO 14 formed by the plurality of FIFOs 140 to 171 connected in parallel to one another stores the matrixing value Vi from the multiplexer 13 in response to matrixing value latch enable signal LE V-0 to LE V-31 , and supplies the stored matrixing value Vi to the multiplier 41 of the multiplication operator 40 in response to matrixing value latch enable signals OE V-0 to OE V-31 . Since the matrixing value Vi is mapped to the mapping value Ui in 32-sample unit by means of a sequential access of the multiple FIFO 14, the multiple FIFO 14 is formed of 32 FIFOs 140 to 171 capable of storing more than 32 samples. The matrixing value processor 10 which uses two FIFOs, as illustrated in FIG. 4B, is formed of two multiplexers 15 and 16, a FIFO 17 and a double FIFO 18. The multiplexer 15 selects the subband sample from the FIFO 17 or newly-received subband sample Si to supply the selected subband sample to the FIFO 17. The FIFO 17 stores the subband sample Si from the multiplexer 15 to provide the stored subband sample Si in accordance with a subband output enable signal OE S . The multiplexer 16 selects the matrixing value Vi from the double FIFO 18 or the matrixing value from the adder 51 or 75 of the addition operator 50 or 70 to provide the selected matrixing value to the double FIFO 18. The double FIFO 18 which is formed by two FIFOs 181 and 182 connected in parallel to each other stores the matrixing value Vi from the multiplexer 16 in accordance with matrixing value latch enable signals LE V-a and LE V-b , and supplies the stored matrixing value Vi to the multiplier 41 of the multiplication operator 40 in accordance with matrixing value output enable signals OE V-a and OE V-b . The matrixing value Vi is mapped to be the mapping value Ui by the sequential access of the double FIFO 18. For this reason, the double FIFO 18 can be embodied only by two FIFOs 181 and 182 when the matrixing value Vi is mapped to be the mapping value Ui by 512s. Provided that the number of subband sample Si is N, the multiple FIFO 14 consists of at least N FIFOs. More specifically, when 512 mapping values Ui are formed by means of 1024 matrixing values Vi, the matrixing value Vi is mapped to be the mapping value in 32-sample unit, so that the FIFOs constituting the multiple FIFO 14 number at least 32. If the mapping is performed in M-sample unit, the multiple FIFO is formed by at least M FIFOs. Also, if the sample of the matrixing value Vi numbers K, the multiple FIFO consists of FIFOs numbering K/M and below. FIG. 5A is a detailed construction view showing one embodiment of the output sample unit 54 or 71 of FIGS. 2 and 3, and FIG. 5B is a detailed construction view showing another embodiment of the output sample unit 54 or 71 of FIGS. 2 and 3. The output sample unit 54 or 71 by means of the multiple register is formed by 32 registers 5400 to 5431 as shown in FIG. 5A. Since 32 outputs are formed with respect to newly-received 32 subband sample signals Si, the intermediately-calculated values of the 32 subband samples are stored in 32 registers 5400 to 5431. The output sample unit 54 or 71 by means of the multiple FIFO is formed by one FIFO 5432 as shown in FIG. 5B. The intermediately-calculated values of the 32 subband samples are sequentially stored in the FIFO 5432 by using the sequential access of the intermediately-calculated values of the subband samples. FIG. 6A is a construction view showing the matrixing value processor 10 in case of a multichannel, and FIG. 6B is a construction view showing the output unit shown in FIGS. 2 and 3 in case of the multichannel. When the synthesis subband filter is applied to the multichannel, as shown in FIGS. 6A and 6B, just the matrixing value processor 10 and output unit 60 can be modified to be used as the matrixing value processor 10. That is, The matrixing value processor and output unit are connected in parallel to each other according to the number of channels. When the subband sample signal SNi of each channel is received from the adder 51 or 75, each matrixing value processor 111 to 11N calculates a matrixing value Vni by means of an input subband sample signal Sni as the following equation (29), and supplies the calculated matrixing value Vni to the multiplier 41. where n denotes nth channel, Sni is the subband sample signal Si of nth channel, and Vni is the matrixing value Vi of nth channel. The output unit 60 may be formed by connecting N FIFOs 511 to 51N in parallel to one another since it should store the output values of N channels. The input and output of the N FIFOs 511 to 51N are individually controlled. As compared with using the DSP or microprocessor, the synthesis subband filter formed to be operated as above does not require a program memory, reduces the number of cycles needed for obtaining one sample to allow for high speed processing, and operates necessary clocks at a low frequency. Furthermore, a multichannel audio signal is utilized per channel by temporally dividing the filter to apply a single synthesis subband filter to a multichannel audio decoder. While the present invention has been particularly shown and described with reference to particular embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be effected therein without departing from the scope of the invention as defined by the appended claims.

Claims: A synthesis subband filter for an MPEG audio signal decoder, comprising: matrixing value processing means (10) for obtaining a shifted matrixing value and a mapping value by means of an input subband sample and matrixing value; constant storing means (30) for storing a matrixing constant value and an operational constant value; multiplication operating means (40) for performing a multiplication operation by means of data from said matrixing value processing means and constant storing means; addition operating means (50) for cumulatively adding the operation values from said multiplication operating means to supply said matrixing value and a subband sample; and output means (60) for supplying said subband sample from said addition operating means, characterised in that the matrixing value processing means (10) comprises: a first multiplexer for receiving said subband sample (11,15) ; FIFO means (12,17) for storing said subband sample from said first multiplexer, and supplying the stored subband sample to said first multiplexer; a second multiplexer (13,16) for receiving said matrixing value from said addition operating means; and a plurality of FIFO means (14,18) for storing said matrixing value from said second multiplexer, and supplying the stored matrixing value to said multiplication operating means and second multiplexer. A synthesis subband filter as claimed in claim 1, wherein said constant storing means (30) comprises: a first counter (31) for counting a first clock as an input; a second counter (32) for counting a second clock as an input; a first ROM (33) for sequentially supplying said stored matrixing constant value in accordance with an output of said first counter; a second ROM (34) for sequentially supplying said stored operational constant value in accordance with an output of said second counter; and a multiplexer (35) for selectively supplying the constant values from said first and second ROMs. A synthesis subband filter as claimed in claim 1, wherein said multiplication operating means (40) comprises: multiplying means (41) for performing the multiplication operation by means of said matrixing value, mapping value and constant values from said matrixing value processing means and constant storing means; and register means (42) for storing the operation values from said multiplying means. A synthesis subband filter as claimed in claim 1, wherein said addition operating means (50) comprises: a first adder (51) for cumulatively adding said operation value from said multiplication operating means; a register (52) for storing an intermediately-calculated operation from said first adder, supplying said intermediately-calculated operation value to said first adder, and supplying the finally-calculated matrixing value to said matrixing value processing means; FIFO means (53) for storing the operation value from said multiplication operating means; a second adder (56) for cumulatively adding said operation value from said FIFO means, and supplying the finally-calculated subband sample to said output means; and output sampling means (54) for storing an intermediately-calculated value of said subband sample from said second adder. A synthesis subband filter as claimed in claim 1, wherein said addition operating means (70) comprises: a first multiplexer (73) for receiving said operation values from said multiplication operating means as inputs; an adder (75) for cumulatively adding said operation values from said first multiplexer; FIFO means (74) for storing said operation value from said multiplication operating means via said first multiplexer and adder to supply the stored value to said first multiplexer; output sampling means (71) for storing the intermediately-calculated value of said subband sample from said first adder; a register (76) for storing said subband sample and matrixing value from said adder, supplying the finally-calculated matrixing value to said matrixing value processing means, and supplying said finally-calculated subband sample to said output means; and a second multiplexer (72) for selecting the intermediately-calculated value from said output sampling means and register to supply the selected value to said adder. A synthesis subband filter as claimed in claim 1, wherein said output means (60) is formed by a FIFO (61). A synthesis subband filter as claimed in claim 1, wherein said multiple FIFO means (14) is formed by FIFOs (140,141... 171) connected in parallel as many as the number of said subband samples. A synthesis subband filter as claimed in claim 1, wherein said multiple FIFO means (18) is formed by two FIFOs (181,182) connected in parallel to each other. A synthesis subband filter as claimed in claim 4, wherein said output sampling means (54) is formed by registers (5400... 543.1) for respectively storing said intermediately-calculated values of said subband samples as many as the number of said subband samples. A synthesis subband filter as claimed in claim 5, wherein said output sampling means (71) is formed by registers (5400... 5431) for respectively storing said intermediately-calculated values of said subband samples as many as the number of said subband samples. A synthesis subband filter as claimed in claim 4, wherein said output sampling means (54) is formed by FIFO means (5432) for sequentially storing said intermediately-calculated values of said subband sample. A synthesis subband filter as claimed in claim 5, wherein said output sampling means (71) is formed by FIFO means (5432) for sequentially storing said intermediately-calculated values of said subband sample.

Inventors: HWANG SUNG BAE, RIM CHAI YEOL, HWANG, SUNG BAE, RIM, CHAI YEOL
Applicants: LG ELECTRONICS INC, LG ELECTRONICS INC.
Application year: 1995
Main classification: H04B1
IPC codes: H04B1