Method and circuit for controlling and monitoring a load

Abstract: A method and circuit is provided which controls and monitors a load (18) through a single I/O pin (12) of a microprocessor (12). A predriver circuit (10) including a level shifter (20) responds to a driver control signal from the microprocessor (14) to control energisation of a power driver connected in a load circuit. The predriver circuit also includes a monitor stage (22) for detecting fault conditions of the load circuit. The output of the monitor stage (22) is connected with the I/O pin (12) which is configured as either an input or an output pin under microprocessor program control.

Description: This invention relates to a method and circuit for interfacing a controller with a driver for controlling a load and for monitoring the status of the load. More particularly, this invention relates to controlling and monitoring a load through a predriver circuit connected with a single Input/Output (I/O) pin on a microprocessor chip which is configured as either and input or output under program control. Circuitry for interfacing a microprocessor with a load for both controlling energisation of the load and monitoring the condition of the load is well known in the art. In general such circuitry includes a power transistor for connecting and disconnecting the load with a source of voltage, and further including monitoring circuitry for sensing circuit conditions One of the problems with the prior art approach is that separate I/O pins on the microprocessor chip are employed, one for controlling the load and the other for monitoring the load. See for example U.S. Patent 5,119,312. The approach requires software routines to protect driver in the event of a load short circuit. Furthermore, as the number of loads increases, a point is reached where either a more expensive microprocessor with additional I/O pins is required, or a costly serial peripheral interface (SPI) circuit is used. In the Motorola Technical Developments, vol 16, August 1992, Schaumburg, IL, US, pages 85-86 (XP000310368) there is a short article by C E Cordonnier describing an MCU having an I/O port coupled to a power MOSFET device. The port functions in either an input read mode or an output write mode. The MCU has a comparator to determine during the input read mode whether the power device is operating correctly or at a faulty current limit. It is an object of the present invention to provide a method and circuit for both controlling and monitoring the condition of a load from a single controller I/O pin. According to the present invention, there is now provided a circuit for controlling the application of a source of voltage (Vcc) to a load and for monitoring the condition of said load, said circuit including a driver for connecting said source of voltage to said load, said circuit connected between one pin of a control device and said load, said control device adapted to configure said pin as an input or an output pin, said circuit being responsive to a driver control output signal applied to said pin by said control device while said pin is configured as an output pin for connecting a source of voltage to said load, said circuit providing an input signal to said pin indicative of the status of said load while said pin is configured by said control device as an input pin; characterised in that said circuit includes a level shifter connected between said pin and said driver, a monitor circuit connected between said pin and a sense point between said driver and said load for sensing a condition of said load and providing said input signal to said control device, said input signal providing a feedback to said level shifter to latch said level shifter in one state in the absence of a load fault and for disabling said latch and turning said driver OFF in response to a short circuit in said load. The invention will now be described further, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a circuit embodying the invention; Figure 2 is a detailed schematic diagram of the predriver circuit of the present invention; Figures 3a and 3b are flow charts of the method used to control the load and monitor for open and short circuit load condition. Referring now to the drawings, and initially to Figure 1, the predriver circuit of the present invention is generally designated 10 and is connected between an I/O pin 12 of a microprocessor 14 and a driver 16. The driver 16 connects a source of d-c voltage indicated as Vcc, to a load 18. The d-c source may be the battery of a motor vehicle and the load may be a lamp on the vehicle connected between the driver 16 and a reference potential such as ground. The circuit 10 includes a level shifter 20 which translates a 5 volt logic level control signal from the microprocessor 14 to a suitable voltage level for operating the driver 16. The circuit 10 further includes a monitor stage 22 which senses the voltage at a junction 24 and provides a feedback to the level shifter 20 over a conductor 26. The conductor 26 is also connected with I/O pin 12 over conductor 28 to provide an input to microprocessor 14 indicative of the status of the load 18. The predriver 10 and driver 16 form a latch. When the driver is turned ON by the level shifter in response to a control signal from the microprocessor 14 applied to the pin 12, the feedback from the output of monitor stage 22 over conductor 26 maintains the driver latched in the ON state as long as there is no short circuit fault at the load. While the circuit shows a high side driver 16 i.e. one connected between the source and the load, it will be appreciated by those skilled in the art that the invention is also applicable to a low side driver i.e. one connected between the load and ground. Referring now to Figure 2, a more detailed schematic of the predriver circuit 10 is shown. The output of the level shifter 20 is connected to a junction 30 between a gate driver resistor 34 and a pulldown resistor 32 connected to ground. Gate resistor 34 is also connected with the gate of an N-channel enhancement type power MOSFET 36. The MOSFET has its source connected with the junction 24 and its drain connected with Vcc. A protection circuit for the MOSFET 36 includes a zener diode 38 and diode 40 serially connected between the source and gate electrodes. A capacitor 42 provides a low impedance to ground for high frequency noise. While a MOSFET device is shown, other power drivers such as a suitable NPN transistor could be employed. The level shifter 20 includes an NPN transistor 44, a PNP transistor 46 and bias resistors 48-54. The base of transistor 44 is connected to the I/O pin 12 through resistor 48 and conductor 28 and to the grounded emitter through resistor 50. The collector of transistor 44 is connected to a boosted supply indicated at Vcc++ through resistors 52 and 54. The base of transistor 46 is connected to the junction between resistors 52 and 54. When transistor 44 is turned ON by the microprocessor 14 the transistor 46 is also turned ON and applies a suitable voltage to the gate of MOSFET 36 to turn the device 36 ON. The monitor stage 22 includes a pair of PNP transistors 60 and 62. The emitter electrodes of transistors 60 and 62 are connected with a regulated voltage supply indicated at Vcc while the collector electrodes are connected to ground through resistors 64 and 66. The base electrodes are connected to the junction between resistors 68, 70 and 72, 74 respectively. A current limiting resistor 76 is connected in series between the monitor stage 22 and the I/O pin 12. The monitor stage 22 uses the base emitter junction to monitor the drain to source voltage of the MOSFET 36. The overall operation of the predriver circuit 10 in response to commands from the microprocessor and to load circuit conditions will now be described. To detect a open circuit load condition the microprocessor 14 configures the pin 12 as an input pin and sets the voltage at the pin 12 low. The resistors 50 and 66 insure that the voltage remains low at pin 12 unless an open circuit at the load is detected. If an open circuit occurs i.e. the load 18 is disconnected from ground, the current path through base resistors 68 and 70 is interrupted and transistor 60 will be turned OFF. With transistor 60 OFF, transistor 62 is turned ON raising the voltage at the I/O pin to a logic level high. The check for an open circuit is preferably performed periodically whenever the MOSFET 36 is in an OFF state. An open circuit check may also be performed when switching the MOSFET from the ON state to the OFF state. If an open circuit is detected the check is repeated three times with a 100 msec. delay between checks to confirm the open circuit condition. If an open load is confirmed, the microprocessor 14 should maintain the I/O pin 14 as an output pin with low logic level voltage applied. To turn the MOSFET 36 ON the microprocessor must configure the pin 12 as an output pin and set the output voltage to a high logic level. With pin 12 high the transistors 44 and 46 are rendered conductive, establishing a turn-on voltage at the gate of the MOSFET 36 which connects the lamp 18 to Vcc. The transistor 60 monitors the drain to source or saturation voltage of MOSFET 36. As long as the voltage drop across the MOSFET is less than the V be of transistor 66 or about 0.7 volts, the transistor 60 will be nonconductive and transistor 62 will be turned ON. When transistor 62 turns ON it provides a current source through resistor 76 to latch the transistor 44 in an ON state. While the predriver circuit 10 is in a latched state the microprocessor reconfigures the pin 12 as an input pin and monitors the voltage at the pin 12. Normally the voltage at the pin 12 is held high due to conduction of the transistor 62. Should a short occur at the load 18, the current increase will cause the voltage drop across MOSFET 36 to increase. When the voltage exceeds 0.7 volt, the transistor 60 turns ON which renders the transistor 62 nonconductive, causing the voltage at the I/O pin 12 and at the base of transistor 44 to go low. Transistors 44 and 46 are thus turned OFF, unlatching the predriver circuit 10, removing voltage from the MOSFET 36, thereby protecting the MOSFET from excessive current. The microprocessor 14 is programmed to respond to the change in voltage at the I/O pin 12 from high to low by turning the MOSFET 36 back ON after a 500 msec. delay. The delay allows the MOSFET 36 to cool down. If the predriver circuit 10 unlatches three times in succession, the microprocessor 14 will assume a short exists and maintain the MOSFET in an OFF state. This fault condition is stored by the microprocessor for subsequent access during vehicle service. The predriver circuit 10 is shown as using discrete components, but it will be understood by those skilled in the art that an application specific integrated circuit (ASIC) could be developed incorporating the function performed by the discrete circuit. With reference to the flow charts of Figures 3a and 3b, the method of controlling and monitoring the load using a single I/O pin of the microprocessor is shown. Referring first to Figure 3a, the method of detecting an open circuited load is depicted. Preferably, the check for an open load is performed periodically whenever the MOSFET 36 is in the OFF state. Open circuits can also be checked when switching the MOSFET 36 from an ON to an OFF state. A counter is reset as indicated at block 78 and the I/O pin is configured as an output at block 80. After-configuring the I/O pin as an output, a low logic level is applied to the I/O pin at block 82. If the MOSFET 36 is ON, this turns the MOSFET OFF and unlatches the predriver 10. If the MOSFET device is already off, applying a low logic level has no effect on the circuit. After a delay of 10 microseconds as indicated at block 84, the I/O pin is configured as an input at block 86 and after another 10 microsecond delay at block 88, the state of the I/O pin is read, to determined whether it is a logic level low or high, as indicated by the decision block 90. If the I/O pin remains low, no further action is required. On the other hand, if the I/O pin switches to a high state, this is indicative of an open circuit in the load 18 and the counter is incremented at 92 after a 100 millisecond delay, indicated at block 94. The sequence of checking for an open circuit at the load is repeated three times, as indicated by the decision block 96 and return of control to the block 80. An open circuit condition is confirmed by three consecutive detections of the high logic level by the decision block 90 in which event an open circuit flag is set at block 98. The software for turning ON the power driver and detecting a short circuit in the load is depicted in the flowchart of Figure 3b. The counter is reset at 100 and the I/O pin is configured as an output at 102. A high logic level is applied to the I/O pin at 104 and after a delay of 100 milliseconds, indicated at 106, to permit the lamp 18 to heat up, to I/O pin is configured as an input at 108. After a delay of 10 microseconds at 110, the logic level on the I/O pin is read, to determined whether it is low or high, as indicated by the decision block 112. If the I/O pin remains high, no further action is taken. On the other hand, if the voltage at the I/O pin switches to a low logic level state, the counter is incremented at block 114, after a 500 millisecond delay to permit the MOSFET 38 to cool. If the counter is less than 3, as indicated by the decision block 118, the sequence is repeated by returning control to the block 102. After three consecutive detections of a short circuit condition, the short circuit flag is set at 120.

Claims: A circuit for controlling the application of a source of voltage (Vcc) to a load (18) and for monitoring the condition of said load (18), said circuit (10) including a driver (16) for connecting said source of voltage to said load (18), said circuit connected between one pin (12) of a control device (14) and said load (18), said control device (14) adapted to configure said pin (12) as an input or an output pin, said circuit (10) being responsive to a driver control output signal applied to said pin (12) by said control device (14) while said pin (12) is configured as an output pin for connecting a source of voltage to said load, said circuit providing an input signal to said pin indicative of the status of said load (18) while said pin (12) is configured by said control device (14) as an input pin; characterised in that said circuit includes a level shifter (20) connected between said pin (12) and said driver (16), a monitor circuit (22) connected between said pin (12) and a sense point (24) between said driver (16) and said load (18) for sensing a condition of said load and providing said input signal to said control device (14), said input signal providing a feedback to said level shifter (20) to latch said level shifter in one state in the absence of a load fault and for disabling said latch and turning said driver (16) OFF in response to a short circuit in said load (18). A circuit as claimed in Claim 1, wherein said circuit latches said driver (16) in an ON state in response to one state of said output signal while said pin (12) is configured as an output pin in the absence of a load fault. A circuit as claimed in Claim 1 or 2, wherein said driver (16) comprises a MOSFET device (36) with said load connected in the source and drain path of said MOSFET device (36), said level shifter (20) supplying a gate drive signal to said MOSFET device in response to a first output logic level signal supplied by said control device (14) at said pin (12), said monitor circuit (22) responsive to the source to drain voltage of said MOSFET device (36) for maintaining said first logic level signal at said pin (12) as long as said source to drain voltage is below a predetermined voltage level. A circuit as claimed in Claim 3, wherein said predetermined voltage level is the Vbe on a transistor (60) in said monitor circuit (22). A circuit as claimed in Claim 4, wherein said load (18) is connected between said driver (16) and a reference potential (ground). A circuit as claimed in Claim 5, wherein said control device (14) includes a microprocessor. A method of controlling and monitoring the condition of a load circuit (10) from a single input/output pin (12) of a microprocessor (14), said load circuit including a load (18) and driver means (16) connected with said pin (12) for controlling energisation of said load (18), said method comprising a sequence of the following steps; configuring said input/output pin (12) as an output pin and applying a high or a low logic level signal to said pin for causing said driver means (16) to place said load (18) in either an energised or de-energised state, configuring said input/output pin (12) as an input pin and monitoring the voltage level at said pin, storing a load fault condition in response to at least one change of the voltage level at said pin (12); characterised in that the method is applied to monitoring the condition of a load circuit (10) including a level shifter (20) connected between the pin (12) and the driver means (16) and a monitor circuit (22) connected between the pin (12) and a sense point (24) between the driver means (16) and the load (18) for sensing a condition of the load, the method further including the steps of; providing a feedback to said level shifter (20) to latch said level shifter in one state in the absence of a load fault, and disabling said latch and turning said driver means (16) OFF in response to a short circuit in said load (18). A method as claimed in Claim 7, comprising the further steps of; providing a high logic level from said microprocessor (14) at said input/output pin (12) to enable latching of said level shifter (20) to energise said load (18), and unlatching said level shifter (20) by providing a signal to said input/output pin (12) from the monitor circuit (22) at said low logic level in response to a short circuit in said load (18). A method as claimed in Claim 7 or 8, comprising the further steps of; providing a low logic level at said input/output pin (12) from said microprocessor (14) to disable latching of said level shifter to disable said load (18), and providing a signal at said high logic level from said monitor circuit (22) to said input/output pin (12) in response to an open circuit in said load (18).

Inventors: BILLS PETER JAMES, LANGER PETER, BILLS, PETER JAMES, LANGER, PETER
Applicants: FORD MOTOR CO, FORD MOTOR COMPANY
Application year: 1995
Main classification: H03K17
IPC codes: H03K17, G06F3, H02H3, H05B37