Method for producing a semiconductor substrate suitable for IGBTs

Abstract: A method for producing a semiconductor substrate is provided, whereby no autodoping occurs and slip dislocations in the substrate can be reduced. The method comprises the following steps: forming a silicon nitride film 11 on the backside surface of an n - -silicon substrate 10; growing epitaxially an n + -buffer layer 12 and p + -layer 13 on the frontside surface of the substrate 10 in sequence; processing and/or polishing the backside surface of the substrate 10 to decrease the thickness to a predetermined one A-A. In case that the thickness of the n - -silicon substrate 10 is 800 µm or larger, which range is larger than those generally used, formation of the silicon nitride film 11 is unnecessary. Further, when the p + -layer 13 is changed to a double structure inclusive of the same and an undoped silicon layer, where the uppermost layer is the latter, the silicon nitride film 11 is also unnecessary.

Description: The present invention relates to a method for producing a semiconductor substrate. More particularly, the present invention relates to the method for producing a semiconductor substrate suitable for IGBT ( an abbreviation for 'Insulated Gate Bipolar Transistor' ) used in an inverter, a small power converter or the like. IGBTs are used in, for example, an inverter or a small power converter as a power semiconductor element with capabilities both of high speed switching, characteristic of the power MOSFET and of high power handling, characteristic of the bipolar transistor. The substrate for fabricating an IGBT has a structure in which, on a p + -silicon substrate 40 of a high concentration ( a low resistivity ) of boron ( B ), a phosphorus ( P ) doped n + -silicon buffer layer 41 ( hereinafter referred to as 'n + buffer layer') and a n - -silicon layer 42 of a low concentration ( a high resistivity ) of phosphorous ( hereinafter referred to as 'n - layer' ) are grown in the sequence of the written order, for example as shown in FIG.2. FIGS.3(a) to 3(e) illustrate an example of a prior art process for producing a substrate for IGBT. The process has the following steps of: using a boron doped p + -silicon substrate 40 (FIG.3(a) ); protecting the backside surface of the substrate 40 by forming a silicon oxide film 43 in CVD on the backside surface (FIG.3(b) ); growing epitaxially a phosphorous doped n + buffer layer 41 ( FIG.3(c)); and a phosphorous doped n - layer 42 (FIG.3(d) )on the frontside surface; processing and/or polishing the backside of the p + -silicon substrate 40 to decrease the thickness to a predetermined one and thereby to expose a thickness-decreased and/or polished surface corresponding to a dash line D - D ( FIG.3(e) ), and, as a result, the substrate for IGBT is obtained. It is to prevent boron autodoping from the backside surface of the p + -silicon substrate 40 that the silicon oxide film 43 is formed on the backside surface of the substrate 40. In other words, in case wherein the backside surface of the p + -silicon substrate 40 is not protected by the silicon oxide film 43, boron is vaporized from the backside surface of the substrate 40 which is highly doped by boron during epitaxial growth, the boron has chances to get into the n + buffer layer 41 and the n - layer 42, which are relatively lower in dopant concentration and have the other conductivity, that is, so-called vapor-phase autodoping occurs, precise resistivity control of the n + buffer layer 41 and the n - layer 42 becomes impossible, and thus semiconductor devices with good electrical characteristics are hard to be produced. In order to prevent such autodoping, the backside surface of the p + -silicon substrate 40 is protected by the silicon oxide film 43 so that boron, which is a p-type dopant, may not be vaporized. In the method above mentioned, however, a phenomenon has not been able to be prevented that, at the beginning of epitaxial growth, boron also vaporizes from the frontside surface of the p + -silicon substrate 40 and it then gets into the n + -buffer layer 41 and n - -layer 42, though the vaporization of boron from the backside surface can be prevented. In consideration of such conditions, a new method has been proposed in an unexamined publication of Japanese Patent Application No. J P A 4-286163. This is a method to obtain a substrate for IGBT (FIG.4(d) ) comprising, as shown in FIGS.4(a) to 4(d), the following steps of: growing epitaxially a phosphorous doped n + -buffer layer 51 (FIG.4(b) ); and a p + - layer 52 with a high concentration of boron (FIG.4(c) ) on one of the main surfaces of an n - -silicon substrate 50 of a low concentration of phosphorous (FIG.4(a) ) in the sequence of the written order; and thereafter, grinding and/or polishing the backside surface of an n + -silicon substrate 50 up to a predetermined thickness to expose a ground and/or polished surface corresponding a dash line E - E. According to this method, no autodoping influence is observed, since the n - -silicon substrate 50 is lower in dopant concentration compared to the epitaxially grown p + - layer 52. The method above mentioned draws attention as an epoch-making method, but has a new problem that, when a p + - layer is epitaxially grown, slip dislocations of a high density occur in the n - -silicon substrate. It is an object of the present invention to provide an improved method for producing a substrate for IGBT wherein it is possible that no autodoping occurs and slip dislocations in the substrate are reduced. The present invention provides a method for producing a semiconductor substrate, which comprises the following steps of: growing a first silicon layer of a first conductivity type and of a lower resistivity than a single crystal silicon substrate, which is of the first conductivity type, of 800 µm or more in thickness and of a high resistivity, on a first main surface of the silicon substrate; growing a second silicon layer of a second conductivity type and of a lower resistivity than the first silicon layer on the first silicon layer; and processing and/or polishing a second main surface, which is the opposite of the first main surface, of the silicon substrate to decrease the thickness to a predetermined one. In the aforementioned method, it is preferred that: the resistivity of the single crystal silicon substrate is 30 Ω·cm or more; the resistivity of the first silicon layer is in the range of 0.05 Ω·cm to 0.5 Ω·cm; the resistivity of the second silicon layer is 0.1 Ω·cm or less. As for methods for processing to decrease the thickness, there are grinding, lapping, etching, combinations of them and the like. Any of them will do. Slip dislocations occurring at a high density in a silicon substrate of a low dopant concentration, in other words of a high resistivity, are greatly influenced by bow of the silicon substrate during the epitaxial growth of a second silicon layer of the opposite conductivity type and of a high dopant concentration, in other words of a low resistivity. For example, in accompanying with the epitaxial growth of a p + -second silicon layer, the second silicon layer generally shrinks and thus an n - -silicon substrate warps so that the side of the second silicon layer is concave. The bow of the substrate increases with increase in the thickness of the second silicon layer. It is thought that, when the internal stress grows beyond a limit by increase in the bow, slip dislocations will occur. Consequently, if the bow of the second silicon layer in epitaxial growth is decreased, the density of slip dislocations can be reduced. In the method recited in the present invention, since the thickness of a single crystal silicon substrate is set at 800 µm or more, which range is larger than a generally used range of 400 µm to 750 µm, the strength of the substrate itself against the bow becomes larger by the extent corresponding to increase in the thickness of the substrate, whereby the bow of the substrate is suppressed. The invention will be further described, by way of example only, with reference to the accompanying drawings, in which : FIGS.1(a) to 1(d) are a flow chart illustrating an example of the present invention; FIG.2 is a sectional view illustrating an example of a substrate for IGBT; FIGS.3(a) to 3(e) are a flow chart illustrating an example of a conventional method for producing a substrate for IGBT; and FIGS.4(a) to 4(d) are a flow chart illustrating an example of another conventional method for producing a substrate for IGBT. In the following description, examples of the present invention will be explained in reference to the accompanying drawings. EXAMPLE 1 FIGS.1(a) to 1(d) are a flow chart illustrating an example of the present invention. As for substrate wafers, phosphorous doped n - - silicon substrates 20, both of which were grown by a FZ method and had a surface orientation of ( 100 ), a resistivity of 80 Ω·cm, a diameter of 125 mm, but the initial thicknesses of which were respectively 1000 µm and 1500 µm, were used ( FIG.1(a) ). On the frontside surface of each substrate 20, a phosphorous doped n + -buffer layer 21 of a resistivity of 0.1 Ω·cm and of 10 µm thick ( FIG.1(b) ) and a boron doped p + - layer 22 of a resistivity of 0.015 Ω·cm and of 300 µm thick respectively were epitaxially grown ( FIG.1(c) ); and In the last step, the backside surfaces of the n - - silicon substrates 20 were ground and polished to thereby expose ground and polished surfaces corresponding to a dash line B - B, so that substrates for IGBT of the total thickness of about 500 µm thick were obtained ( FIG.1(d) ). The bow and slippage density of each of the substrates for IGBT produced by the aforementioned method were measured. These substrates both had bows on the order of 30 µm, though the bows each being concave on the p + - layer side, and the slip dislocation densities in the n - -silicon substrates were respectively 4 x 10 2 dislocations/cm 2 for the thickness of 1000 µm and 5 x 10 2 dislocations/cm 2 for the thickness of 1500 µm. COMPARATIVE EXAMPLE 1 A substrate for IGBT was produced under the following conditions. As for a substrate wafer, a phosphorous doped n - - silicon substrate, which was grown by a FZ method and had a surface orientation of (100), a resistivity of 80 Ω·cm, a diameter of 125 mm and an initial thickness of 550 µm, was used. Then, on the frontside surface of the substrate, a phosphorous doped n + - buffer layer of a resistivity of 0.1 Ω·cm and 10 µm thick and a boron doped p + - layer of a resistivity of 0.015 Ω·cm and 300 µm thick respectively were epitaxially grown; and in the last step, the backside surface of the n - - silicon substrate was ground and polished to thereby expose a ground and/or polished surface, so that a substrate for IGBT of total thickness of about 500 µm was obtained. The bow and slippage density of the substrate for IGBT produced by the aforementioned method were measured. In this substrate for IGBT, bow was as large as 75 µm, and was concave on the p + - layer side, and the slip dislocation density in the n - -silicon substrate was 1 x 10 4 dislocations/cm 2 . Although, in the aforementioned EXAMPLE 1 and COMPARATIVE EXAMPLE 1, n + - buffer layers (21 in EXAMPLE 1) were grown by an epitaxial growth method, but even when n + - buffer layers were formed by a diffusion method or ion implantation method instead of an epitaxial growth method, results similar to the aforementioned were obtained. As is clear from the above description, according to the method for producing a semiconductor substrate of the present invention, it is possible that the impurity concentration of each layer is precisely controlled and thereby the resistivity is also stabilised, since occurrence of autodoping can be prevented. Especially, as for a substrate for IGBT, production of a semiconductor substrate more suitable for IGBT becomes a real possibility, since fabrication of an IGBT having a high withstand voltage becomes easy due to the use of the silicon substrate of a high resistivity and besides the density of slip dislocations in the substrate can be reduced.

Claims: A method for producing a semiconductor substrate comprising the following steps of: providing a single crystal silicon substrate (20), which is of a first conductivity type, of 800 µm or more in thickness and of a high resistivity; growing a first silicon layer (21) of the first conductivity type and of a lower resistivity than said single crystal silicon substrate on a first main surface of the substrate (20); growing a second silicon layer (22), of a second conductivity type and of a lower resistivity than the first silicon layer (21), on the first silicon layer (21); and processing and/or polishing a second main surface, which is the opposite of the first main surface, of the silicon substrate (20) to decrease the thickness to a predetermined one (B-B). A method as claimed in Claim 1, characterised in that: the resistivity of the single crystal silicon substrate (20) is 30 Ω·cm or more; the resistivity of the first silicon layer (21) is in the range of 0.05 Ω·cm to 0.5 Ω·cm; the resistivity of the second silicon layer (22) is 0.1 Ω·cm or less.

Inventors: KASAHARA AKIO, KATAYAMA MASATAKE, KUMAKI YOUICHI, MOROGA ISAO, SHIRAI ISAO, KASAHARA, AKIO, KATAYAMA, MASATAKE, KUMAKI, YOUICHI, MOROGA, ISAO, SHIRAI, ISAO
Applicants: SHINETSU HANDOTAI KK, SHIN-ETSU HANDOTAI COMPANY LIMITED
Application year: 1995
Main classification: H01L21
IPC codes: H01L21, H01L29