Low-power, low-voltage four-quadrant analog multiplier, particularly for neural applications

Abstract: A multiplier (1) presenting four multiplying branches (2-5), each formed by a buffer transistor (21, 31, 41, 51) and by two input transistors (22, 23; 32, 33; 42, 43; 52, 53) arranged in series to one another and connected between two output nodes (12, 13) and a common node (65). A biasing branch (6) presents a diode-connected forcing transistor (61) with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node (65). The forcing transistor (61) forces the input transistors (22, 23; 32, 33; 42, 43; 52, 53) to operate in the triode (linear) region, i.e. as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.

Description: The present invention relates to a low-power, low-voltage analog multiplier, particularly for neural applications. As is known, four-quadrant analog multipliers are a basic element in the construction of audio and video signal processing systems, particularly as regards signal reception and transmission, and in the construction of adaptive filters such as correlators and convolvers. Recently, they have also been applied to the hardware construction of complex neural architectures requiring an analog multiplier (in this case, known as a synapse) as the basic element. Architectures such as Hopfield networks, multilayer perceptra and Kohonen maps make extensive use of analog multipliers, which may also be used to advantage in hand- or typewritten character recognition systems, selfteaching associative memories, image processing modules and texture analysing systems. In view of the high parallel computing capacity and hence the large number of single multiplying cells required by the neural networks in which they are employed, the current demand is for analog multipliers occupying a small integration area, presenting a good degree of modularity, and, above all, provide for low power dissipation per cell. Various embodiments are to be found in literature of integrated circuits implementing the four-quadrant analog multiplying function. Some known solutions are based on a variation in the transconductance of differential stages (e.g. Gilbert cells) or on the use of transconductors (see, for example, "A precise Four-Quadrant Multiplier with Subnonosecond Response", B. Gilbert, IEEE Journal Solid State Circuits, Vol. SC-3, p. 365-373, Dec. 68; "A 20 V Four-Quadrant CMOS Analog Multiplier", J.N. Babanezhad, G.C. Tems, IEEE Journal Solid State Circuits, Vol. SC-20, No 6, Dec. 1985; "A CMOS Four-Quadrant Analog Multiplier with Single-Ended Voltage Output and Improved Temperature Performance", Z. Wang, IEEE Journal Solid State Circuits, Vol. SC-26, No 9, Sept. 1991; "A ±5 V CMOS Analog Multiplier", Shi-Cai Qin, Randy L. Geiger, IEEE Journal Solid State Circuits, Vol. SC-22, No 6, Dec. 1987). Other known solutions are based on hardware implementation of the algebraic equation: 4 V a V b = (V a +V b ) 2 - (V a -V b ) 2 using the quadratic characteristic I/V of a MOS transistor (see, for example, "An MOS Four-Quadrant Analog Multiplier using Simple Two-Input Squaring Circuits with Source Followers", Ho-Jun Song, Choong-Ki Kim, IEEE Journal Solid State Circuits, Vol. SC-25, No 3, June 1990; "A MOS Four-Quadrant Analog Multiplier using the Quarter-Square Technique", J.S. Pena-Finol, J.A. Connely, IEEE Journal Solid State Circuits, Vol. SC-22, No 6, Dec. 1987). When formed using the bipolar technique, solutions based on traditional Gilbert cells present a limited input voltage range and high power dissipation (50 mW or more, depending on the desired frequency performance and input voltage range), require a high supply voltage (+5V to -5V), and occupy a large area. Improvements employing CMOS transistors provide for reducing power dissipation and supply, but nevertheless require a minimum supply voltage of 5 V and still occupy a generally large area. With a high input voltage range and high output linearity, solutions employing the quadratic characteristic of MOS transistors require a large area and involve high power dissipation, so that neither solution is suitable for use as a synapse in neural networks. GB-A-2 261 093, and ELECTRONICS LETTERS, vol. 30, no. 25, 8 December 1994, pages 2125/2126, LIU S -I: "LOW VOLTAGE CMOS FOUR-QUADRANT MULTIPLIER" disclose multipliers comprising transistors operating in the triode region. It is an object of the present invention to provide an analog multiplier of the above type, designed to overcome the drawbacks typically associated with known devices, and which in particular provides for a high input voltage range and low supply voltage and power dissipation, and is of compact size. According to the present invention, there is provided a low-power, low-voltage, four-quadrant analog multiplier as claimed in Claim 1. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a circuit diagram of the analog multiplier according to the present invention; Figure 2 shows a circuit diagram of part of the Figure 1 multiplier; Figures 3a and 3b show the DC characteristic of the multiplier as represented by the output current as a function of one of the two input voltages, and using the other input voltage as a parameter; Figure 4 shows a graph of total harmonic distortion as a function of input voltage. Figure 1 shows a multiplying cell 1 forming the analog multiplier according to the invention. Cell 1 comprises four identical multiplying branches 2, 3, 4, 5 connected to four input terminals 7, 8, 9, 10 and to two output nodes 12, 13; a biasing branch 6 interposed between a supply line 15 at V DD and a ground line 16, and connected to multiplying branches 2-5 as described below; and a subtracting circuit 17 connected to nodes 12, 13. Input terminals 7-10 are supplied with the two voltages V x , V y to be multiplied, and which are supplied differentially so that input terminal 7 presents voltage +V x /2 with respect to ground, terminal 8 presents voltage +V y /2, terminal 9 presents voltage -V x /2, and terminal 10 presents voltage -V y /2. Biasing branch 6 comprises a diode-connected N-channel MOS forcing transistor 61, the drain terminal of which is connected to supply line 15 via a first biasing current source 62 supplying current I p , the source terminal of which defines a node 65 and is grounded via a second biasing current source 63 (supplying current I b ), and the gate terminal of which defines a node 64. Multiplying branches 2-5 each comprise, respectively, a buffer transistor 21, 31, 41, 51, a first input transistor 22, 32, 42, 52, and a second input transistor 23, 33, 43, 53, all of which are N-channel MOS types, and the three transistors of each branch are pipelined between nodes 12, 13 and node 65 of biasing branch 6. More specifically, buffer transistor 21 of the first multiplying branch 2 has its drain terminal connected to node 12, its gate terminal connected to node 64, and its source terminal connected to the drain terminal of transistor 22; first input transistor 22 of branch 2 has its gate terminal connected to input terminal 7, and its source terminal connected to the drain terminal of transistor 23; and second input transistor 23 of branch 2 has its gate terminal connected to input terminal 8, and its source terminal connected to node 65. Buffer transistor 31 of the second multiplying branch 3 has its drain terminal connected to node 13, its gate terminal connected to node 64, and its source terminal connected to the drain terminal of transistor 32; first input transistor 32 of branch 3 has its gate terminal connected to input terminal 9, and its source terminal connected to the drain terminal of transistor 33; and second input transistor 33 of branch 3 has its gate terminal connected to input terminal 8, and its source terminal connected to node 65. Buffer transistor 41 of the third multiplying branch 4 has its drain terminal connected to node 12, its gate terminal connected to node 64, and its source terminal connected to the drain terminal of transistor 42; first input transistor 42 of branch 4 has its gate terminal connected to input terminal 9, and its source terminal connected to the drain terminal of transistor 43; and second input transistor 43 of branch 4 has its gate terminal connected to input terminal 10, and its source terminal connected to node 65. Buffer transistor 51 of the fourth multiplying branch 5 has its drain terminal connected to node 13, its gate terminal connected to node 64, and its source terminal connected to the drain terminal of transistor 52; first input transistor 52 of branch 5 has its gate terminal connected to input terminal 7, and its source terminal connected to the drain terminal of transistor 53; and second input transistor 53 of branch 5 has its gate terminal connected to input terminal 10, and its source terminal connected to node 65. Subtracting circuit 17 is a 1:1 current mirror comprising a first and a second PMOS transistors 17a, 17b. More specifically, transistor 17a has its source terminal connected to supply line 15, its drain terminal connected to node 12, and its gate terminal connected to its own drain terminal (diode connection) and to the gate terminal of transistor 17b, which has its source terminal connected to supply line 15, and its drain terminal connected to node 13. For the sake of clarity, Figure 1 also shows an intermediate node 18 between the drain terminal of transistor 17b and node 13, and at which the current I o + through transistor 17b (which mirrors the current in transistor 17a towards node 12) and the current I o - entering node 13 towards branches 3 and 5 are subtracted, so that node 18 supplies a current ΔI equal to the difference between currents I o + and I o - . Figure 1 also shows an operational amplifier 19 for adding the currents ΔI of a number of multiplying cells similar to cell 1. More specifically, operational amplifier 19 has its noninverting input grounded, its output feedback connected to the inverting input via a resistor 20, and its inverting input connected to node 18 of all the multiplying cells 1. Multiplying cell 1 in Figure 1 operates as follows. Forcing transistor 61 of biasing branch 6 operates as a diode and imposes a predetermined voltage drop between nodes 64 and 65 to force input transistors 22, 23; 32, 33; 42, 43; 52, 53 to operate in the triode (linear) region, i.e. as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the source and gate terminals. The buffer transistor 21, 31, 41, 51 of each multiplying branch is so sized as to operate in subthreshold mode (as is obvious to any technician in the field, given the current range of a transistor, the width/length W/L ratio may be so sized that the gate-source voltage drop is approximately equal to the threshold voltage) to minimize (practically eliminate) its overdrive voltage (i.e. the difference between the gate-source voltage drop and the threshold voltage of the transistor) so that the buffer transistor of each multiplying branch operates as a current buffer with improved performance as compared with devices operating in saturation mode. The total drain-source voltage drop of the two input transistors of each multiplying branch 2-5 is determined by the overdrive voltage (drain-source voltage drop minus threshold voltage) of forcing transistor 61, which in turn is determined by the biasing current set by current sources 62, 63, so that the drain-source voltage V ds of the input transistors is maintained below the corresponding overdrive voltage to ensure operation of the transistors in the linear region. To increase the dynamic range of the input transistors, they are so sized that the channel length is greater than the width. Operation of multiplying cell 1 is thus based on self-modulation of the drain-source voltage of the input transistors operating in the linear region, to obtain a variation in the equivalent transconductance of each branch, so that the output current of each current buffer depends on both the input voltages. Nonlinearity of the second and third order is eliminated or at any rate made negligible by cross-coupling the output. For a clear understanding of the operation of multiplying cell 1, reference will first be made to Figure 2, which shows multiplying branch 2 only and biasing branch 6, and in which the gate terminals of transistors 22, 23 are indicated as presenting respective voltages (V x /2+V cm ) and (V y /2+V cm ), the sum of the voltages in Figure 1 plus the common mode voltage V cm which, in the Figure 1 differential circuit, is rejected. As is known, the drain current I d of an NMOS transistor operating in the linear region is given by the equation: where Cost, V gs , V th and V ds are respectively a constant defining the transconductance parameter, the gate-source voltage drop, the threshold voltage (gate-source voltage above which the transistor is turned on), and the drain-source voltage drop. In the case in question, the drain-source voltage drop of transistors 22, 23 is determined by the gate-source voltage drop of forcing transistor 61, and is roughly twenty times less than the (V gs -V th ) term, i.e. the overdrive of transistors 22, 23, so that, for transistors 22, 23, the second term of (1) may be disregarded to give: Moreover, if V a is the voltage with respect to ground at node 70 between the source terminal of transistor 23 and the drain terminal of transistor 22; V b the voltage with respect to ground at node 71 between the source terminal of buffer transistor 21 and the drain terminal of transistor 22; V p the voltage between nodes 71 and 65; V s the voltage with respect to ground at node 65; and R the equivalent resistance of transistor 23 (operating, as stated, in the linear region) equal to the ratio between the drain-source voltage drop V ds and the current I d of transistor 23, then (1') gives, for transistor 22: and, for transistor 23: where K 22 and K 23 represent the value of the constant Cost for transistors 22 and 23, and: V a = I d · R + V s V b = V p + V s . Moreover, bearing in mind that the gate-source voltage drop of transistor 61 (operating in saturation mode) equals threshold voltage V th plus overdrive voltage V ov , and that buffer transistor 21 operates in subthreshold mode, i.e. with a gate-source voltage drop roughly equal to threshold voltage V th , and assuming the threshold voltage is roughly equal for all the transistors, the following equation applies: V gs,61 = V ov,61 + V th = V p + V gs,21 ≅ V p + V th so that V p ≅ V ov,61 where V gs,61 , V ov,61 and V gs,21 are respectively the gate-source voltage drop of transistor 61, the overdrive voltage of transistor 61, and the gate-source voltage drop of transistor 21. Bearing in mind that the current of a saturated MOS transistor is proportional to the square of the overdrive voltage (I=KV ov 2 ), equation (4) for transistor 61 gives: V p = I p K d where K d is a multiplication constant, and I p the current in transistor 61 (current of source 62). Combining equations (1'), (2) and (3), the current I d in branch 2 equals: Making the necessary simplifications, and assuming K 22 = K 23 = K (i.e. the transconductance parameter is the same for both transistors 22, 23) and V d = V cm - V th - V s = constant, equation (6) gives the four currents in branches 2, 3, 4 and 5: The difference between the output currents ▵I = I o + - I o - is given by the equation: Substituting equations (7), (8), (9) and (10) in (11) gives: In view of the fact that: applies for each V x and V y in the respective input voltage range, a few calculations give: which demonstrates the multiplying function of the Figure 1 circuit. Figures 3a, 3b and 4 show a number of simulations of the Figure 1 circuit. In particular, Figure 3a shows the transfer characteristic of the multiplier as represented by the output current ΔI as a function of V x in the -2.5 to 2.5 V range, with V y as a parameter (of predetermined value); similarly, Figure 3b shows the output current ΔI as a function of V y with V x as a parameter (of predetermined value); and Figure 4 shows total harmonic distortion (THD) as a function of a 1.2 V sinusoidal input voltage, and varying the other differential input (DC) in the 0 to 2.5 V range. The advantages of the multiplier according to the present invention are as follows. Firstly, it provides for a wide input voltage range by virtue of employing MOS transistors operating in the triode region. Secondly, it is capable of operating with low supply voltages. Though typically designed to operate with a supply voltage V DD of 3 V, it can also operate with a V DD of as low as 1.5 V, thanks to the presence of a small number of pipelined transistors in each branch, and to the fact that two of these operate in the linear region. Thirdly, it provides for very low power dissipation (6 µW with 1.5 V supply), and for harmonic distortion of less than 1% at both inputs with maximum peak-peak voltages in relation to the possible input voltage range. Fourthly, it presents an extremely simple configuration, and requires a very small area (cell 1 measures only 95 x 64 µm). Clearly, changes may be made to the circuit as described and illustrated herein without, however, departing from the scope of the present invention.

Claims: A four-quadrant analog multiplier comprising four multiplying branches (2-5), each multiplying branch formed by a buffer transistor (21; 31; 41; 51) and a first and a second input transistor (22, 23; 32, 33; 42, 43; 52, 53), the buffer and the input transistors being arranged in series and connected between one of two output nodes (12, 13) and a common node (65), wherein said first and second input transistor are MOS transistors and have a first and a second input terminal (7, 8) respectively receiving a first and a second input voltage, and wherein the output nodes (12, 13) are connected to corresponding inputs of a subtracting circuit (17), and wherein an output terminal (18) of said subtracting circuit (17) supplies an electric output quantity proportional to the product of said first and second input voltages, the multiplier further comprising a biasing branch (6) connected to said common node (65), said biasing branch (6) comprising a biasing means (61) connected to the control terminal of the buffer transistors in the multiplying branches, so as to determine in each multiplying branch the total drain-source voltage drop of the input transistors so that they are forced to operate in the triode region. A multiplier as claimed in Claim 1, characterized in that said biasing means comprise a diode-connected third transistor (61). A multiplier as claimed in Claim 2, characterized in that said third transistor (61) is a MOS transistor. A multiplier as claimed in Claim 2 or 3, wherein said first, second and third transistors (22, 23, 61) each comprise a first and second terminal and a control terminal; characterized in that the first terminal of said first transistor (22) is connected to the control terminal of said third transistor (61); the second terminal of said first transistor (22) is connected to the first terminal of said second transistor (23); and the second terminal of said second transistor (23) is connected to the first terminal of said third transistor (61). A multiplier as claimed in any one of the foregoing Claims, characterized in that the buffer transistor (21) is interposed between said first transistor (22) and said output terminal (18) of the multiplier (1). A multiplier as claimed in Claim 5, characterized in that said biasing means comprising means for forcing said buffer transistor (21) to operate in the subthreshold region. A multiplier as claimed in Claims 5 and 6, characterized in that said buffer transistor (21) has a first and second terminal and a control terminal; said control terminal of said third transistor (61) being connected to the control terminal of said buffer transistor (21); said first terminal of said buffer transistor being connected to said output terminal (18); and said second terminal of said buffer transistor (21) being connected to said first terminal of said first transistor (22). A multiplier as claimed in Claim 7, characterized in that said first, second and third transistors (22, 23, 61) and said buffer transistor (21) are N-channel MOS transistors. A multiplier as claimed in any one of the foregoing Claims, characterized in that it each multiplying branch comprises a respective first (32, 42, 52) and a respective second (33, 43, 53) MOS transistor arranged in series to each other and having a first and second terminal and a control terminal; in that it also comprises a third (9) and a fourth (10) input terminal, said first input voltage (V x ) being applied between said first (7) and said third (9) input terminal, and said second input voltage (V y ) being applied between said second (8) and said fourth (10) input terminal; and in that said control terminals of said first transistors (22, 52) of said first and fourth multiplying branches are connected to said first input terminal (7); said control terminals of said first transistors of said second and third multiplying branches (3, 4) are connected to said third input terminal (9); said control terminals of said second transistors of said first and second multiplying branches (2, 3) are connected to said second input terminal (8); and said control terminals of said second MOS transistors of said third and fourth multiplying branches (4, 5) are connected to said fourth input terminal (10). A multiplier as claimed in Claim 9, characterized in that said first and second output nodes being connected to said output terminal (18); said second terminals of said second transistors (23, 33, 43, 53) of said first, second, third and fourth multiplying branches (2-5) being connected to said common node (65); said first terminal of said first transistor (22, 42) of said first and third multiplying branches (2, 4) being connected together and to said first output node (12); and said first terminal of said first transistor (32, 52) of said second and fourth multiplying branches (3, 5) being connected to said second output node (13). A multiplier as claimed in Claim 10, characterized in that said subtracting circuit (17) comprises a current mirror (17a, 17b). A multiplier as claimed in Claim 11, characterized in that said current mirror comprises P-channel MOS transistors (17a, 17b).

Inventors: COLLI GIANLUCA, COLLI, GIANLUCA
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: G06G7
IPC codes: G06G7