FREQUENCY STABILIZED FSK TRANSMITTER

Abstract: A SAW stabilized FSK transmitter that is tuned by a varactor diode to particular center operating frequencies so as to distinguish between a "0" bit and a "1" bit. In one embodiment, a microprocessor applies an N-bit output signal to a digital-to-analog converter to alter the voltage applied across the varactor diode, and thus the center operating frequency of the transmitter. In an alternate embodiment, the microprocessor adjusts the duty cycle of a pulse-width modulation signal so as to change the voltage potential applied to the varactor diode.

Description: 96/19888 PCΪYUS95/16031 Frequency Stabi l ized FSK Transmitter BACKGROUND OF THE INVENTION 1. Field Of The Invention This invention relates generally to a SAW stabilized FSK transmitter and, more particularly, to a SAW stabilized FSK transmitter that is tuned to particular center operating frequencies to distinguish logical "0" and "1" data bits by a varactor diode, where a tune voltage to adjust the capacitance of the varactor diode is derived by a digital-to-analog converter or a pulse-width modulation signal. 1. Discussion of the Related Art Many applications exist for a low-cost radio frequency (RF) transmitter that has a tightly controlled output frequency tolerance so as to communicate with RF data receivers that have narrow RF or intermediate frequency (IF) filters that do not use automatic frequency control. One such application is in a remote keyless entry system for a vehicle where a vehicle operator can activate certain vehicle functions, such as locking and unlocking the vehicle doors, at a location remote from the vehicle. A portable transmitter carried by the vehicle operator transmits a coded signal that includes a sequence of coded data bits that are received and deciphered by a receiver within the vehicle. If the data bit sequence matches an expected data bit sequence within the receiver, the receiver will cause the vehicle function to be performed. In a typical remote keyless entry system, the coded data bit sequence is transmitted by frequency shift keying (FSK) , where the carrier frequency that transmits the data bit O 96/19888 PCI7US95/16031 sequence is shifted between two center operating frequencies to distinguish a "0** bit from a "l" bit. As is well understood, oscillator circuits are necessary to generate the carrier frequency for transmitting the coded signal from the portable remote transmitter. Surface acoustic wave (SAW) resonators are readily available devices, well known to those skilled in the art, that provide oscillation signals having adequate frequency tolerances acceptable for the applications mentioned above. The circuit matching components, i.e., transistors, capacitors, inductors and resistors, used in connection with the SAW resonator to construct the oscillator circuit increases the initial transmitter frequency tolerance as a result of component variances. In other words, even though the resonating frequency of a SAW resonator is predictable within rigid frequency tolerances, the matching components that are included as part of the oscillator circuit alter the resonating frequency in an unpredictable manner from one oscillator circuit to another. Therefore, to reduce the transmitter frequency tolerances back to an acceptable level for a particular application, some mechanism is generally required for adjusting the center operating frequency of the oscillator circuit. Known methods for adjusting the center operating frequency of a SAW resonating oscillator circuit include tuning a variable capacitor or variable inductor that is used as a matching component in the oscillator circuit. A varactor diode is a diode that changes its capacitance depending on a voltage potential applied across it. U.S. Patent No. 5,105,162 issued to Fleissner et al discloses an electrically tuned super- regenerative RF receiver circuit that includes a variable capacitor, namely a varactor diode, that is used to vary the center operating frequency of the oscillator circuit associated with the receiver. The varactor diode is connected between a variable tuning voltage and a reference potential in which the tuning voltage varies the voltage across the varactor diode. A microprocessor is used to control the tuning voltage applied to the varactor diode. What is needed is a mechanism for accurately providing a tuning signal to a variable capacitor in order to generate a stable operating frequency for an oscillator circuit. It is therefore an object of the present invention to provide such a mechanism. SUMMARY OF THE INVENTION In accordance with the teachings of the present invention, a SAW stabilized FSK transmitter is disclosed that is tuned to a particular center operating frequency by a varactor diode using a digital-to-analog converter or a pulse-width modulation signal. The transmitter includes an RF voltage- controlled oscillator circuit including an amplifier and a SAW resonator or SAW delay line feedback circuit. The varactor diode is included as one of the matching components of the oscillator circuit. The center operating frequency of the oscillator circuit is adjusted by changing the voltage potential across the varactor diode so that the oscillator circuit will output a center frequency f 0 for a "0" bit and a center frequency f, for a "1" bit. In one embodiment, the voltage potential across the varactor diode is switched for the different bits by applying different N-bit tune codes to a digital-to-analog (D/A) converter. In an alternate embodiment, the voltage potential across the varactor diode is switched by changing the duty cycle of a pulse-width modulation (PWM) output signal from a microprocessor. In order to originally tune the f 0 and f, center frequency signals to be within system tolerances, an RF spectrum analyzer or frequency counter and a controller are provided. The controller applies an initial N-bit tune code to a microprocessor for the D/A converter or a duty cycle tune code to a microprocessor for the FWM output signal. The oscillator circuit is then enabled, and a frequency signal transmitted by the oscillator circuit is received by an antenna associated with the RF spectrum analyzer. If the transmitted frequency signal is not within a predetermined tolerance, the controller will cause the N-bit tune code for the D/A converter or the duty cycle tune code for the PWM output signal to be incremented up or down in a manner that will cause the transmitted frequency received by the RF spectrum analyzer to be within the predetermined tolerance. This process is performed for both the f 0 and f, frequencies. The final tune codes for the f„ and f. frequencies are stored in the microprocessor for operation. Additional objects, advantages, and features of the present invention will become from the following description and appended claims, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a SAW stabilized FSK transmitter that is tuned by a digital-to-analog converter according to one embodiment of the present invention; Figure 2 is a block schematic diagram of the transmitter of Figure 1 showing how the digital-to-analog converter is initially tuned; Figure 3 is a schematic diagram of a SAW stabilized FSK transmitter that is tuned by a pulse-width modulation signal according to another embodiment of the present invention; Figure 4 is a schematic block diagram of the transmitter of Figure 3 showing how the pulse-width modulation signal is initially tuned; and Figures 5A and 5B are a flow chart diagram showing how the transmitters of Figures 1-4 are initially tuned. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following discussion concerning tuning the center operating frequency of a SAW stabilized FSK transmitter is merely exemplary in nature and is in no way intended to limit the invention or its applications or uses. Figure 1 shows a schematic diagram of a transmitter circuit 10 according to a preferred embodiment of the present invention. The transmitter circuit 10 is microprocessor controlled by a microprocessor 12. A voltage potential V cc from a battery 14, for example a nickel-cadmium battery, powers the transmitter circuit 10. A series of function switches S^S j are connected to input ports of the microprocessor 12 in order to activate the transmitter circuit 10 and cause it to transmit a predetermined signal. In one embodiment, the transmitter circuit 10 is a portable transmitter associated with a remote keyless entry system in which the function switches S^S j cause the microprocessor 12 to broadcast a predetermined encoded serial data bit message to be received by a receiver unit (not shown) associated with a vehicle (not shown) , where the receiver unit will cause the vehicle function to be performed if the coded message is valid. Clock (CLK) , write and data program ports are provided in order to program and apply data to the microprocessor 12. A crystal oscillator 16 provides a stable oscillation frequency for a clock input to the microprocessor 12 in order to control the operation of the microprocessor 12, as is well understood in the art. Capacitors C. and C- provide filtering for the crystal oscillator 16. The transmitter circuit 10 includes an RF voltage- controlled oscillator circuit shown generally at 18. The oscillator circuit 18 includes a common emitter amplifier comprising a linear bipolar transistor 20 and DC bias resistors R j ,, R-. and R 4 . It will be appreciated by those skilled in the art that the common emitter amplifier can be replaced with other amplifiers such as common base, common collector and field effect transistor amplifiers. The oscillator circuit 18 further includes a feedback circuit including a SAW resonator SAW delay line 22 electrically connected between the collector terminal and the base terminal of the transistor 20. The oscillator circuit 18 also includes matching components comprising inductors L 1 and L-,, capacitor C 6 , and a varactor diode 24. It is the matching components that vary the center operating frequency of the SAW resonator 22 from one transmitter to another in an unpredictable manner. The anode of the varactor diode 24 is connected to the battery 14 through an inductor L„ κ . The cathode of the varactor diode 24 is connected to the output of a digital-to-analog (D/A) converter shown generally at 26. The D/A converter 26 is an R-2R resistive ladder network connected to a series of N output data ports of the microprocessor 12. R-2R resistive ladder network acting as digital-to-analog converters are well known in the art. The inductor L SFC provides a high impedance device that passes a DC voltage to the varactor diode 24 from the battery 14, but acts as an open circuit at RF operating frequencies. The inductor L, acts as an antenna for radiating the frequency signal generated by the oscillator circuit 18, and can be an inductor trace on a printed circuit board that includes the components of the transmitter circuit 10. The oscillator circuit 18 is activated by a "high" signal from an RF enable output port of the microprocessor 12. The "high" signal from the RF enable output port is applied to the base terminal of the transistor 20 and to the SAW resonator 22 through a current limiting resistor R 4 . The signal on the base terminal of the transistor 20 and the SAW resonator 22 causes the oscillator circuit 18 to resonate at a center operating frequency that is determined by the center oscillation frequency of the SAW resonator 22 and the characteristics of the matching components. The voltage generated by the resonation of the oscillator circuit 18 is radiated by the inductor L,. Data bits transmitted by the transmitter circuit 10 are transmitted by frequency shift keying (FSK) modulation. In other words, the oscillator circuit 18 will output a frequency f 0 when a "0" bit is being transmitted, and will output a frequency f, when a "1" bit is being transmitted. The microprocessor 12 allows an adequate number of oscillation cycles at f 0 and f 1 to be transmitted for each "0" or "l" bit that will allow the receiver to decipher the serial data message. In order to change the output frequency of the oscillator circuit 18 from f 0 to t. , or from f, to f 0 , so as to change the bit being transmitted, the capacitance of the varactor diode 24 is adjusted accordingly. When the capacitance of the varactor diode 24 decreases, the oscillation frequency of the oscillator circuit 18 increases, and when the capacitance of the varactor diode 24 increases, the oscillation frequency of the oscillator circuit 18 decreases. In order to adjust the capacitance on the varactor diode 24, an appropriate voltage is applied to its cathode. The N-bit output applied to the D/A converter 26 determines the voltage potential across the varactor diode 24, and thus the amount of charge the diode 24 will store. The most significant bit (MSB) of the N output bits is applied through a resistor R. to the anode of the varactor diode 24, as shown. The larger the data word applied to the D/A converter 26, the greater the voltage potential applied to the varactor diode 24. For example, a minimum voltage will be applied to the anode of the varactor diode 24 if all of the bits are zero, and a maximum voltage will be applied to the anode of the varactor diode 24 if all of the bits are one. Consequently, by changing the data bit sequence applied to the D/A converter 26, a decrease or increase in the oscillation frequency of the oscillator circuit 18 can be achieved. The microprocessor 12 will store a tune bit code to apply to the D/A converter 26 for both the f 0 and f, frequencies. The microprocessor 12 monitors the function switches 3,-S j to determine whether they have been activated. When one of the switches S.-S 3 has been activated, the microprocessor 12 will generate a function code depending on which switch was pressed. The function code is combined with a unique identification (ID) code stored within a memory of the microprocessor 12. The combination of the function code bits and the ID code bits form a serial data bit message that is to be transmitted. For example, a vehicle operator wishing to unlock a vehicle door as he approaches the vehicle will activate function switch s, that has a function code having the bit sequence 01. This bit sequence is combined with an ID code bit sequence 0011 to generate a serial data message 010011. The microprocessor 12 reads the first bit of the serial data bit message. If the first bit is a 1, the tune code for a 1 bit is sent to the D/A converter 26. If the first bit were a 0 bit, the tune code for a 0 bit would be sent to the D/A converter 26. If the D/A converter 26 received five bits to make up the tune code, the tune code for f 0 could be, for example, 01111, and the tune code for f. could be 10000. The microprocessor 12 proceeds to transmit the entire serial data bit message in this manner. When the microprocessor 12 generates the serial data bit message, it also enables the oscillator circuit 18 by switching the enable port high. The N-bit output of the microprocessor 12 sends the serial data bit message to the D/A converter 26 one bit at a time until all of the data bits have been sent. The oscillator circuit 18 is then switched off by switching the RF enable port to "low". Figure 2 is a schematic block diagram of a tuning system 32 that is provided to show how the transmitter circuit 10 is initially tuned to the f 0 and f, frequencies to be within predetermined tolerances. In other words, the microprocessor 12 needs to be initially programmed to generate the appropriate N- bit tune code for the D/A converter 26 that causes the varactor diode 24 to have the appropriate capacitance so as to enable the oscillator circuit 18 to generate f 0 and f, within the necessary tolerances of the system. The system 32 includes a transmitter 34 intended to represent the transmitter circuit 10 discussed above. The transmitter 34 includes a microprocessor 36 being the same as the microprocessor 12 above. Likewise, switch inputs 38 represent the switches S^S j , a program interface 40 provides an interface to apply the clock, write and data program inputs to the microprocessor 36, and a clock circuit 42 represents the crystal oscillator 16 and the capacitors C, and C 2 . The oscillator circuit 18 is shown as an oscillator circuit 44 including a common emitter amplifier 46, a SAW resonator feedback circuit 48, a varactor diode 50, an inductor L 1 acting as an antenna, and matching components inductor L-, and a capacitor C,. The N data bits from the microprocessor 36 are applied to a D/A converter 52 representing the D/A converter 26. Each transmitter will have a unique ID code. Additionally, the "1" bit and "0" bit tune codes will be different for each individual transmitter since the SAW resonators, varactor diodes, inductors, and other frequency devices, will be different. In order to initially tune the f 0 and f, output frequencies of the transmitter 34 to be within acceptable tolerances, an RF spectrum analyzer 54 acting as a frequency counter is provided. A controller 56 controls and interfaces the RF spectrum analyzer 54 to the transmitter 34 through the program interface 40. The controller 56 writes the initial software program to operate the microprocessor 36 to a memory of the microprocessor 36 on the write line. The controller 56 also enters an initial N-bit tune codes f 0 and f, to the microprocessor 36. The controller 56 then instructs the microprocessor 36 to enable the oscillator circuit 44, and to output the initial N-bit tune code for f 0 to the D/A converter 52. It is possible for the controller 56 to set an initial f 0 tune code as the lowest bit sequence that will produce the lowest frequency value for f 0 , however, it is generally known approximately what the appropriate output bits should be for each tune code, and it is therefore more efficient to generate a series of output bits near this value. Once the N-bit tune code is applied to the D/A converter 52, the signal transmitted by the antenna L. is received by an antenna 58 associated with the spectrum analyzer 54. The spectrum analyzer 54 determines the frequency of the signal received by the antenna 58, and sends a signal indicative of this frequency to the controller 56. The signal received by the antenna 58 is compared with a desired f 0 frequency stored in the controller 56. The desired f 0 frequency stored in the controller 56 represents the frequency that a receiver will be looking for from the transmitter 34 when it is in use. The controller 56 determines if the frequency of the signal received by the antenna 58 is within a specified tolerance when compared with the desired frequency. If the received frequency signal is outside of the specified tolerance, the microprocessor 36 will increase or decrease the N-bit tune code accordingly. This procedure is repeated until the transmitted frequency is within the frequency tolerance limit for the f 0 frequency. The corresponding N-bit tune code is then saved in the microprocessor 36 as the f 0 frequency tune code. This procedure is repeated for the "1" bit. Once the "0" bit and the "l" bit tune codes have been determined and stored, these codes are written to a permanent memory within the microprocessor 36 along with a unique transmitter ID code. Figure 3 shows a schematic diagram of a transmitter circuit 68 that includes similar components to the transmitter circuit 10 discussed above. The transmitter circuit 68 includes a microprocessor 70 powered by a battery 72, function switches S^S-., CLK, write and data program input ports, and a crystal oscillator 74. Further, the transmitter circuit 68 includes an RF voltage-controlled oscillator circuit 76 including a common emitter amplifier comprising a bipolar transistor 78, DC bias resistors R., R 3 and R 4 , a SAW resonator feedback circuit 80, and a varactor diode 82. The feedback circuit 80 also includes matching components L,, L-, and C 6 , where I-, is a radiating antenna. The operation of these components, as well as other components not specifically mentioned, associated with the transmitter circuit 68 is identical to the like components of the transmitter circuit 10, discussed above. Instead of a D/A converter for providing the tuning signal to the varactor diode 82, the transmitter circuit 68 uses a pulse-width modulation (PWM) output signal derived from the microprocessor 70 that is applied to the anode of the varactor diode 82 through a voltage limiting resistor R, as shown. The width of the pulses of the pulse-width modulation output signal from the microprocessor 70 represents the duty cycle of the pulse-width modulation output signal. The duty cycle of the pulse-width modulation output is determined by a duty cycle tune code stored in a memory of the microprocessor 70. The duty cycle tune code can be represented by any appropriate number of bits that will give enough bit values to tune the frequency of the oscillator circuit 76 to a desired frequency within the acceptable tolerance. In one example, the tune code for the f 0 frequency is the bit sequence 011, and the tune code for the f 1 frequency is the bit sequence 100. The period of the pulses of the pulse-width modulation signal is much shorter than the period for transmitting a data bit. The pulse-width modulation output is low-pass filtered by the resistor R., and a capacitor C 4 before being applied to the varactor diode 82. The length of time that the pulses are high as they are applied to the anode of the varactor diode 82 determines how long the anode of the varactor diode 82 will be at the voltage potential of the PWM signal. The longer the voltage potential at the anode of the varactor diode 82 is high, the more charge will be stored in the varactor diode 82. Therefore, by applying PWM signals to the varactor diode 82 of different pulse widths, the capacitance of the varactor diode 82 is changed so as to adjust the center frequency of the oscillator circuit 76 and distinguish "0" and "1" bits. The pulse-width modulation output signal from the microprocessor 70 can be generated in software. Figure 4 shows a schematic block diagram of a tuning system 86 including a transmitter 88 representing the transmitter circuit 68 discussed above. The transmitter 88 includes a microprocessor 90 representing the microprocessor 70. The microprocessor 90 includes switch inputs representing the function switches S^S j , a program interface 94 for interfacing the clock, write and data program inputs applied to the microprocessor 70, and a clock circuit 96 representing the crystal oscillator 74 and the capacitor C 1 and C 2 . The transmitter 88 further includes an oscillator circuit 96 including a common emitter amplifier 98, a SAW resonator feedback circuit 100 and a varactor diode 102. An inductor L, acts as a radiating antenna. The system 86 further includes an RF spectrum analyzer 104 including an antenna 106. The spectrum analyzer 104 is controlled by a controller 108 that includes output lines to the clock, data and write input lines applied to the program interface 94. The spectrum analyzer 104 and the controller 108 operate in the same fashion as the spectrum analyzer 54 and the controller 56, discussed above. When the initial tune codes for either the f 0 frequency or the f, frequency are sent to the microprocessor 90 by the controller 108, and the controller 108 enables the microprocessor 90, the antenna 106 will receive the frequency signal radiated by the inductor L,. If the received frequency signal is not within the specified tolerances, the controller 108 will cause the microprocessor 90 to increase or decrease the tune code for the PWM output signal accordingly so as to increase or decrease the frequency signal radiated by the antenna L,. Once the signal received by the antenna 106 is within the predetermined tolerances, the corresponding duty cycle tune code is saved in the memory of the microprocessor 90 for f 0 and t. . Figures 5A and 5B show a flow chart diagram 112 describing the process of how the output frequency of both the transmitters 34 and 88 are initially tuned by a programming procedure. A block 114 represents the initiation of the tuning and programming procedure for providing predetermined tune frequencies f Q and f.. A block 116 represents the connection of the controller 56 to the microprocessor 36 or the controller 108 to the microprocessor 90. A block 118 represents loading the tuning program into the microprocessors 36 or 90. A block 120 represents enabling the oscillator circuits 44 or 96 at the RF enable port so as to activate the oscillator circuits 44 or 96. A block 122 represents setting the initial tune code for f. as the N-bit D/A converter initial tune code or the pulse-width modulation duty cycle initial tune code. A block 124 represents determining the transmitted frequency in the controllers 58 or 108 from the spectrum analyzers 54 or 104, respectfully, for the initial f. tune code. A decision diamond 126 determines whether the transmitted frequency is within a predetermined tolerance limit of f,. If the answer is no to the question of whether the transmitted frequency is within the tolerance limit, a decision diamond 128 determines whether the transmitted frequency is greater than or less than the predetermined frequency f.,. If the transmitted frequency is greater than f 1# then the N-bit tune code for the D/A converter 52 is decremented by one, or the tune code for the duty cycle of the pulse-width modulation output is decremented by one, as represented by block 130. If the transmitted frequency is less than the predetermined f,, then the N-bit tune code for the D/A converter 52 is incremented by one, or the tune code for the duty cycle of the pulse-width modulation output is incremented by one, as indicated by block 132. Of course it is possible to increment or decrement the tune codes by more than one if the transmitted frequency is significantly outside of the tolerance limit. Once the tune code f, is adjusted, the process returns to the step of reading the transmitted frequency at the block 124 until the answer of whether the transmitted frequency is within the tolerance limit at the decision diamond 126 is yes. Once the transmitted frequency is within the tolerance limit, the tune code for f 1 is saved in the controller 56 or 108 as indicated by block 134. The process is then initiated for the f 0 tune code. At block 136, the initial tune code for f„ for the N-bit D/A converter tune code or the duty cycle tune code is set. A block 138 represents determining the transmitted frequency in the controllers 58 or 108 from the spectrum analyzers 54 or 104, respectfully. A decision diamond 140 determines whether the transmitted frequency is within the predetermined tolerance limit of f 0 . If the answer is no to the question of whether the transmitted frequency is within the tolerance limit, a decision diamond 142 determines whether the transmitted frequency is greater than or less than the predetermined frequency f„. If the transmitted frequency is greater than the f 0 , then the N-bit tune code is decremented by one for the D/A converter 52, or the tune code for the duty cycle of the pulse-width modulation output is decremented by one, as represented by block 144. If the received frequency is less than f 0 , then the N-bit tune code for the D/A converter 52 is incremented by one or the tune code for the duty cycle of the pulse-width modulation output is incremented by one, as indicated block 146. Once the tune code for f Q is adjusted, the process returns to the step of reading the transmitted frequency at the block 138 until the answer of whether the transmitted frequency is within the tolerance limits at the decision diamond 140 is yes. Once the transmitted frequency is within the tolerance limit, the tune code for f 0 is saved in the controller 56 or 108 as indicated by block 148. The transmitter ID code is then written to the microprocessor 36 or 90 from a random number generated within the controller 58 or 108 as represented by block 150. Next, the controllers 58 or 108 load the transmitter program, the f 0 tune code, the f 1 tune code and the ID code into the memory of the microprocessor 36 or 90 as represented by block 152. Once the microprocessors 36 or 90 is programmed and the tune frequencies are set, the transmitter 38 or 88 is ready for operation, and the program procedure is finished as represented by block 154. The foregoing discussion discloses and describes merely exemplary embodiments of the present invention. One skilled in the art will readily recognize from such discussion, and from the accompanying drawings and claims that various changes, modifications and variations can be made therein without departing from the spirit and scope of the invention as defined in the following claims.

Claims: CLAIMS In the Claims: 1. A transmitter for transmitting a predetermined sequence of data bits by frequency shift keying (FSK) where the transmitter transmits a first frequency f 0 to represent a "0" bit and a second frequency f, to represent a "1" bit, said transmitter comprising: a microprocessor that controls the operation of the transmitter, said microprocessor generating the sequence of data bits; an oscillator circuit being responsive to the sequence of data bits from the microprocessor and generating a frequency output signal that includes the sequence of data bits, said oscillator circuit including a component that tunes the center operating frequency of the oscillator circuit; and a digital-to-analog (D/A) converter being responsive to an N-bit tune code from the microprocessor, said D/A converter having an output connected to the component that tunes the oscillator circuit, wherein the N-bit tune code applied to the D/A converter adjusts a control signal applied to the component that tunes the frequency of the oscillator circuit such that a first N-bit tune code is applied to the D/A converter to transmit the first frequency f Q and a second N-bit tune code is applied to the D/A converter to transmit the second frequency f.. 2. The transmitter according to Claim 1 wherein the component that tunes the oscillator circuit is a varactor diode and wherein the control signal is a voltage potential applied to the varactor diode. 3. The transmitter according to Claim 1 wherein the oscillator circuit includes an amplifier and a surface acoustic wave (SAW) feedback circuit. 4. The transmitter according to Claim 1 wherein the D/A converter is an R-2R resistive ladder network. 5. The transmitter according to Claim 1 wherein the transmitter is responsive to a controller so as to tune the transmitter, said controller being operable to cause the microprocessor to output an initial N-bit tune code to the D/A converter for the first frequency f 0 and to activate the oscillator circuit, a frequency counter being responsive to a first frequency signal transmitted by the transmitter, said controller being responsive to a signal indicative of the first transmitted frequency signal from the frequency counter, said controller comparing the first transmitted frequency signal to the first frequency f 0 so as to determine whether the first transmitted frequency signal is within a predetermined tolerance of the first frequency f 0 , said controller being operable to cause the microprocessor to either increase or decrease the initial N-bit tune code for the first frequency f 0 depending on whether the first transmitted frequency signal is greater than or less than the first frequency f 0 if the first transmitted frequency signal is not within the predetermined tolerance. 6. The transmitter according to Claim 5 wherein the controller is operable to cause the microprocessor to output an initial N-bit tune code to the D/A converter for the second frequency f,, said frequency counter being responsive to a second transmitted frequency signal from the transmitter, said controller being responsive to a signal indicative of the second transmitted frequency signal from the frequency counter, said controller comparing the second transmitted frequency signal to the second frequency f, so as to determine whether the second transmitted frequency signal is within a predetermined tolerance of the second frequency f,, said controller being operable to cause the microprocessor to either increase or decrease the initial N-bit tune code for the second frequency f, depending on whether the second transmitted frequency signal is greater than or less than the second frequency f_, if the second transmitted frequency signal is not within the predetermined tolerance. 7. A transmitter for transmitting a predetermined sequence of data bits by frequency shift keying (FSK) where the transmitter transmits a first frequency f 0 to represent a "0" bit and a second frequency f, to represent a "1" bit, said transmitter comprising: a microprocessor that controls the operation of the transmitter, said microprocessor generating a pulse-width modulation output signal that includes the sequence of data bits; and an oscillator circuit being responsive to the pulse- width modulation output signal from the microprocessor and generating a frequency signal that includes the sequence of data bits, said oscillator circuit including a component that tunes the center operating frequency of the oscillator circuit, said pulse-width modulation signal being applied to the component that tunes the oscillator circuit, said microprocessor switching the duty cycle of the pulse-width modulation signal so as to switch a control signal applied to the component that tunes the frequency of the oscillator circuit such that a first duty cycle is applied to the oscillator circuit to transmit the first frequency f Q and a second duty cycle is applied to the oscillator circuit to transmit the second frequency f,. 8. The transmitter according to Claim 7 wherein the component that tunes the oscillator circuit is a varactor diode and wherein the control signal is a voltage potential applied to the varactor diode. 9. The transmitter according to Claim 7 wherein the oscillator circuit includes an amplifier and a surface acoustic wave (SAW) feedback circuit. 10. The transmitter according to Claim 7 wherein the transmitter is responsive to a controller so as to tune the transmitter, said controller being operable to cause the microprocessor to output an initial duty cycle of the pulse-width modulation signal for the first frequency f 0 and to activate the oscillator circuit, a frequency counter being responsive to a first frequency signal transmitted by the transmitter, said controller being responsive to a signal indicative of the first transmitted frequency signal from the frequency counter, said controller comparing the first transmitted frequency signal to the first frequency f 0 and determining whether the first transmitted frequency signal is within a predetermined tolerance of the first frequency f„, said controller being operable to cause the microprocessor to either increase or decrease the initial duty cycle for the first frequency f 0 depending on whether the first transmitted frequency signal is greater than or less than the first frequency f 0 if the first transmitted frequency is not within the predetermined tolerance, said microprocessor storing a first duty cycle tune code for the first frequency f 0 when the first transmitted signal is within the predetermined tolerance. 11. The transmitted according to Claim 10 wherein the controller is operable to cause the microprocessor to output an initial duty cycle for the pulse-width modulation signal for the second frequency f,, said frequency counter being responsive to a second transmitted frequency signal from the transmitted, said controller being responsive to a signal indicative of the second transmitted frequency signal from the frequency counter, said controller comparing the second transmitted frequency signal so as to determine whether the second transmitted frequency signal is within a predetermined tolerance of the second frequency f,, said controller being operable to cause the microprocessor to either increase or decrease the initial duty cycle for the second frequency f 1 depending on whether the second transmitted frequency signal is greater than or less than the second frequency f, if the second transmitted frequency signal is not within the predetermined tolerance, said microprocessor storing a second duty cycle tune code for the second frequency f, when the second transmitted signal is within the predetermined tolerance. 12. A method of tuning a transmitter to transmit a first frequency f 0 and a second frequency f,, said method comprising the steps of: providing a microprocessor that controls the operation of the transmitter; providing an oscillator circuit that generates a predetermined frequency output signal, said oscillator circuit including a component that tunes the center operating frequency of the oscillator circuit; and providing a digital-to-analog (D/A) converter that receives an N-bit tune code from the microprocessor, said D/A converter applying the N-bit tune code to the component that tunes the center frequency of the oscillator circuit, wherein the N-bit tune code controls a control signal applied to the component that tunes the frequency of the oscillator circuit such that a first N-bit tune code is applied to the D/A converter to transmit the first frequency f 0 and a second N-bit tune code is applied to the D/A converter to transmit the second frequency f.,. 13. The method according to Claim 12 wherein the step of providing an oscillator circuit includes providing an oscillator circuit that includes a varactor diode that tunes the center operating frequency of the oscillator circuit. 14. The method according to Claim 12 wherein the step of providing an oscillator circuit includes providing an oscillator circuit having an amplifier and a surface acoustic wave (SAW) feedback circuit. 15. The method according to Claim 12 further comprising the steps of providing a frequency counter and providing a controller, said step of providing a controller including using the controller to cause the microprocessor to output an initial N-bit tune code to the D/A converter for the first frequency f 0 and to activate the oscillator circuit, said step of providing a frequency counter including using the frequency counter to receive a first frequency signal transmitted by the transmitter when the controller activates the oscillator circuit, said controller being responsive to a signal indicative of the first transmitted frequency signal from the frequency counter, said controller comparing the first transmitted frequency signal to the first frequency f 0 so as to determine whether the first transmitted frequency signal is within a predetermined tolerance of the first frequency f„, said controller causing the microprocessor to either increase or decrease the initial N-bit tune code for the first frequency f 0 depending on whether the first transmitted frequency signal is greater or less than the first frequency f 0 if the first transmitted frequency signal is not within the predetermined tolerance. 16. The method according to Claim 15 wherein the steps of providing a frequency counter and providing a controller includes using the controller to cause the microprocessor to output an initial N-bit tune code to the D/A converter for the second frequency f 1# said step of providing a frequency counter including using the frequency counter to receive a second transmitted frequency signal from the transmitter, said controller being responsive to a signal indicative of the second transmitted frequency signal from the frequency counter, said controller comparing the second transmitted frequency signal for the second frequency f, so as to determine whether the second transmitted frequency signal is within a predetermined tolerance of the second frequency f., said controller causing the microprocessor to either increase or decrease the initial N-bit tune code for the second frequency f, depending on whether the second transmitted frequency signal is greater than or less than the second frequency f, if the second transmitted frequency signal is not within the predetermined tolerance. 17. A method of tuning transmitter to transmit a first frequency f 0 and a second frequency f,, said method comprising the steps of: providing a microprocessor that controls the operation of the transmitter, said microprocessor generating a pulse-width modulation output signal; and providing an oscillator circuit that receives the pulse-width modulation output signal from the microprocessor and generates a frequency signal that includes the first frequency f 0 and the second frequency f,, said oscillator circuit including a component that tunes the center frequency of the oscillator circuit, said pulse-width modulation signal being applied to the component that tunes the oscillator circuit, said microprocessor switching the duty cycle of the pulse-width modulation signal so as to switch a control signal applied to the component that tunes the frequency of the oscillator circuit such that a first duty cycle is applied to the oscillator circuit to transmit the first frequency f 0 and a second duty cycle is applied to the oscillator circuit to transmit the frequency f t . 18. The method according to Claim 17 wherein the step of providing an oscillator circuit includes providing an oscillator circuit that includes a varactor diode that tunes the center operating frequency of the oscillator circuit. 19. The method according to Claim 17 wherein the step of providing an oscillator circuit includes providing an oscillator circuit having an amplifier and a surface acoustic wave feedback circuit. 20. The method according to Claim 17 further comprising the steps of providing a frequency counter and providing a controller, said step of providing a controller including using the controller to output an initial duty cycle of the pulse-width modulation signal for the first frequency f„ and to activate the oscillator circuit, said step of providing a frequency counter including using the frequency counter to receive a first frequency signal transmitted by the transmitter, said controller being responsive to a signal indicative of the first transmitted frequency signal from the frequency counter, said controller comparing the first transmitted frequency signal to the first frequency f 0 so as to determine whether the first transmitted frequency signal is within a predetermined tolerance of the first frequency f„, said controller causing the microprocessor to either increase or decrease the initial duty cycle for the first frequency f„ depending on whether the first transmitted frequency signal is greater than or less than the first frequency f 0 if the first transmitted frequency is not within the predetermined tolerance. 21. The method according to Claim 20 wherein the controller causes the microprocessor to output an initial duty cycle for the pulse-width modulation signal for the second frequency f_,, said frequency counter being responsive to a second transmitted frequency signal from the transmitter, said controller being responsive to a signal indicative of the second transmitted frequency signal from the frequency counter, said controller comparing the second transmitted frequency signal for the second frequency f, so as to determine whether the second transmitted frequency signal is within a predetermined tolerance of the second frequency f,, said controller causing the microprocessor to either increase or decrease the initial duty cycle for the second frequency f__, depending on whether the second transmitter frequency signal is greater than or less than the second frequency f, if the second transmitted frequency signal is not within the predetermined tolerance.

Inventors: BREHMER GERALD M, PROKUP JAMES M, BREHMER, GERALD, M., PROKUP, JAMES, M.
Applicants: UNITED TECHNOLOGIES AUTOMOTIVE, UNITED TECHNOLOGIES AUTOMOTIVE, INC.
Application year: 1995
Main classification: H04L27
IPC codes: H04L27