A high voltage analog switch

Abstract: A method and apparatus are provided that blocks the flow of injection currents in an analog switch caused by substrate biases. These biases are caused, in turn, by input signal voltages that reach or exceed the supply rails. A pair of transistors (M5, M6) having the same polarity as the switching transistors (M1, M2, M8, M9) are connected back-to-back in series and shunted across the analog switch's pass transistor (M7). These shunt transistors (M5, M6) function to block the flow of injection currents associated with the switching transistors (M1, M2, M8, M9) and thereby increase the dynamic range, speed and overall performance of the analog switch.

Description: TECHNICAL FIELD OF THE INVENTION This invention relates generally to the field of semiconductor integrated circuits, and more particularly, to integrated circuit analog switches. BACKGROUND OF THE INVENTION Semiconductor integrated circuits (ICs) can be designed to function as switches. In particular, digital logic switching and linear-signal switching are among the most important of applications in which field effect transistor (FET) circuits are used. A common use of MOSFETs is as analog switches. An ideal analog switch behaves like a mechanical switch. In the "ON" state, the analog switch passes a signal through to the load, while in the "OFF" state the switch acts as an open circuit. Analog switches are used in numerous applications, such as, for example, high-speed switches (e.g., MOS memory), linear switching devices, application-specific products (e.g., multiplexers), and analog-to-digital converters. A design problem with existing analog switches is that they are limited in dynamic range by the magnitude of the ICs' supply voltages. In other words, if the magnitude of the voltage being switched or "passed" by the device exceeds the magnitude of the supply voltage (commonly referred to as the "supply rails" or V dd ), then significant substrate/well biases (e.g., for the P-type FETs) are developed and substrate/well injection currents are introduced into the IC, which substantially decrease the switch's speed, linearity and overall performance. The existing analog switch designs typically use very complex well switching schemes to increase the dynamic range of the devices. Other existing analog switches are designed to handle analog signals that exceed the supply rail but work for only one "side" of the switch. However, these devices are not useful for certain applications where the analog voltages to be switched are being input from numerous different sources, such as, for example, in a signal multiplexing application. Typically, the above-described designs increase the complexity and costs of the analog switch ICs, do not significantly increase their dynamic range, and sometimes just cannot be used for certain applications. SUMMARY OF THE INVENTION Accordingly, a need exists in the semiconductor integrated circuit manufacturing industry for a relatively simple high voltage analog switch with an increased dynamic range. In accordance with the present invention, an apparatus is provided that blocks the flow of injection currents in the analog switch caused by substrate biases. These biases are caused, in turn, by input signal voltages that reach or exceed the supply rails. A pair of transistors having the same conductivity type as the switching transistors are connected back-to-back in series and shunted across the analog switch's pass transistor. These shunt transistors function to block the flow of injection currents associated with the switching transistors. An important technical advantage of the present invention is that by blocking the flow of injection currents caused by high input signal voltages, the dynamic range, speed and performance of the analog switch is significantly improved. Another important technical advantage of the present invention is that the process of adding shunt transistors to the integrated circuit does not increase the device's overall technical complexity. Yet another important technical advantage of the present invention is that the analog switch can be controlled by a single logic input. Still another important technical advantage of the present invention is that each analog switch circuit can be fabricated for use as a "drop-in" standard cell for many applications. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIGURE 1 is an electrical schematic circuit diagram of a high voltage analog switch structured according to a preferred embodiment of the present invention. FIGURE 2 is an electrical schematic circuit diagram illustrating a use of two of the analog switches "EESWITCH" depicted in FIGURE 1 in an exemplary switching application. DETAILED DESCRIPTION OF THE INVENTION The preferred embodiment of the present invention and its advantages are best understood by referring to FIGURES 1 and 2 of the drawings, like numerals being used for like and corresponding parts of the various drawings. FIGURE 1 is an electrical schematic circuit diagram of a high voltage analog switch structured according to a preferred embodiment of the present invention. The high voltage analog switch ("EESWITCH"), includes a pair of transistors (preferably MOSFETs) M1 and M2 cross-connected in parallel to form a "pole" of the switch. Preferably, the analog switch shown in FIGURE 1 is fabricated on a single IC chip. However, the invention is not intended to be limited only to a single IC. The sources and "back gates" of transistors M1 and M2 are connected together. The drain of transistor M1 is connected to the "front gate" of transistor M2 and the drain of transistor M3. The source of transistor M3 is connected to circuit "ground." The gate of transistor M3 is connected to an input of inverter INV1 and switch control line CTLB. One analog voltage (V1) to be switched or "passed" by the switch is coupled to the source and "back gate" of transistor M1. The signal at switch control line CTLB is at either a logic "high" or "low" value. The sources and "back gates" of transistors M1, M2 and M5 are all connected together. The drain of transistor M2 is connected to the "front gate" of transistor M1, the drain of transistor M4, and the "front gate" of transistor M5. The gate of transistor M4 is connected to the output of inverter INV1. The drain of transistor M4 is connected to circuit "ground." In the embodiment illustrated in FIGURE 1, transistors M1, M2 and M5 are shown as P-type devices, and transistors M3 and M4 are N-type devices. However, the invention is not intended to be so limited, and the conductivity types of the devices could be reversed in another embodiment, such as for n-type substrates. For example, transistors M1, M2 and M5 could be N-type devices, while transistors M3 and M4 could be P-type devices. The source and "back gate" of transistor M5 are also connected to the drain of "pass" transistor M7. Although "pass" transistor M7 is shown in FIGURE 1 as a NMOS device, its conductivity type also could be reversed to "pass" current in the opposite direction (from right to left in FIGURE 1) using, for example, an n-type substrate. The gate of "pass" transistor M7 is connected to the output of inverter INV1. The drains of transistors M5 and M6 are connected together. The drain of "pass" transistor M7 is connected to the drains and "back gates" of transistors M6, M8 and M9. A second analog voltage (V2) to be switched or "passed" by the switch is coupled to the drain and "back gate" of transistor M9. The "front gate" of transistor M6 is connected to the drains of transistors M8 and M10 and the "front gate" of transistor M9. The gate of transistor M10 is connected to the output of inverter INV1, and the source of transistor M10 is connected to circuit "ground." Transistors M8 and M9 are cross-connected to form the second "pole" of the analog switch. The drain of transistor M9 is connected to the "front gate" of transistor M8 and the drain of transistor M11. The gate of transistor M11 is connected to the input control line CTLB and the input of inverter INV1. The source of transistor M11 is connected to circuit "ground." Similar to the conductivity types of transistors M1-M5 and M7 described above, the conductivity types of the P-type devices M6, M8 and M9, and the N-type devices M10 and M-11 illustrated in FIGURE 1, could be reversed, for example, for n-type substrates in another embodiment of the invention. In operation, the switching function of the high voltage analog switch illustrated in FIGURE 1 is controlled by the logic level ("high" or "low") of the control signal CTLB. Control signal CTLB can be, for example, one bit of a byte or digital word. If control signal CTLB is "high," then transistors M3 and M11 are turned ON. The inverted control signal CTLBB is then "low," which turns transistors M4 and M10 and "pass" transistor M7 OFF. The voltages at nodes N1 and N2 go "low." Since transistors M4 and M10 are OFF, then transistors M5 and M6 are OFF. However, when control signal CTLB is "low," then transistors M3 and M11 are turned OFF. The inverted control signal CTLBB is now "high," which turns transistors M4 and M10 and "pass" transistor M7 ON. The voltages at nodes N3 and N4 are "low," which turns transistors M1 and M9, and M5 and M6 ON. Consequently, current can flow (from left to right in FIGURE 1) through "pass" transistor M7, and also via a parallel path through transistors M5 and M6. In this embodiment, when the control signal CTLB is "low," then the signal V1 is "passed" through transistor M7 and coupled as an output voltage to the connection labeled V2. Conversely, when the control signal CTLB is "high," then the present analog switch is OFF and no signal is "passed" through transistor M7. An important aspect of the invention is that a parallel current path is provided through transistors M5 and M6, which are arranged in a back-to-back configuration. In this embodiment, these P-type MOS/diffusion devices function as diodes to block injection currents caused by the substrate bias associated with the P-channel switching transistors M1, M2 and M8, M9. These injection currents are created by the biases set up across what are essentially "parasitic diodes" formed at the PN junctions in the P-channel switching transistors. Consequently, these "diodes" (M5 and M6) are configured to allow current flow only in a direction reverse to the injection current attempting to flow through the above-described "parasitic diodes," which functions to block the injection currents associated with the P-channel switching transistors. This blocking function of transistors M5 and M6 thus prevents the injection currents from shunting across the "pass" transistor M7. Therefore, the present analog switch can advantageously "pass" signal voltages linearly which are very close to zero volts or that exceed the supply rails, by blocking the flow of injection currents caused by substrate biases and thereby significantly improving the dynamic range of the present analog switch over existing devices. FIGURE 2 is an electrical schematic circuit diagram illustrating a use of two of the analog switches "EESWITCH" depicted in FIGURE 1 in an exemplary switching application. Referring to FIGURE 2, a first voltage to be switched is coupled to the input connection V1 of the present analog switch SW1. A second voltage to be switched is coupled to the input connection V2 of analog switch SW2. The outputs of switches SW1 and SW2 are connected together at connection VPRE. Operating in accordance with the present analog switch illustrated and described with respect to FIGURE 1, switch SW1 is ON whenever control signal CTL1B is "low," and switch SW2 is ON whenever control signal CTL2B is "low." Whenever switch SW1 is ON, then the voltage at connection V1 is "passed" through its respective transistor M7 and presented at connection VPRE. Whenever switch SW2 is ON, then the voltage at connection V2 is "passed" through its respective transistor M7 and presented at VPRE. If the control signals CTL1B and CTL2B are different bits in a byte or a word, for example, then the specific voltage at VPRE is determined by the presence of a "high" one of those bits in the control signal for one of the analog switches. Extending this concept, the switching arrangement illustrated in FIGURE 2 can be used, for example, in a signal multiplexer, in which each incoming voltage to be switched to an output of the multiplexer is applied to an input of a respective analog switch. If, for example, signals from eight different sources are to be multiplexed, then the eight signals can be applied to the respective inputs of eight of the analog switches shown in FIGURE 1. The output connections VPRE (FIG. 2) would be connected together. The switching function of each of the eight analog switches could be controlled by a respective control signal CTLB. In accordance with the teachings of the invention, each of the eight analog switches would prevent problems caused by substrate/well injection currents, and the dynamic range of each switch (and the multiplexer's overall performance) would be improved as a result. Furthermore, in accordance with the invention, each switch could be controlled advantageously by a single logical input, which decreases the complexity of such devices. Moreover, additional switches can be fabricated and added as "drop-in" standard cells for more complex switching or multiplexing applications. Also, even much higher signal voltages can be switched (e.g., up to 60V peak) if high voltage transistors such as, for example, DE NMOS, DE PMOS, or LDMOS devices are used in yet another embodiment of the present invention.

Claims: A semiconductor analog switch selectively connecting a first node (V 1 ) and a second node (V 2 ) in response to an input control signal (CTLB), comprising: a pass transistor (M7) including a first gate, a first source directly connected to said first node (V 1 ) and a first drain directly connected to said second node (V 2 ); a first shunt transistor (M5) of a first conductivity type, said first shunt transistor including a second gate, a second source connected to said first node (V 1 ) and a second drain; a second shunt transistor (M6) of said first conductivity type, said second shunt transistor including a third gate, a third source connected to said second node (V 2 ), and a third drain connected to said second drain of said first shunt transistor; and a drive circuit (M1, M2, M3, M3, M8, M9, M10, M1, INV1) having an input receiving the input control signal (CTLB), a first output (CTLBB) connected to said first gate of said pass transistor, a second output (SW1BP) connected to said second gate of said first shunt transistor and a third output (SW2BP) connected to said third gate of said second shunt transistor, said drive circuit (M1, M2, M3, M3, M8, M9, M10, M1, INV1) responsive to said input control signal (CTLB) to simultaneously render said pass transistor (M7), said first shunt transistor (M5) and said second shunt transistor (M6) conducting for first predetermined states of said input control signal (CTLB) and simultaneously render said pass transistor (M7), said first shunt transistor (M5) and said second shunt transistor (M6) nonconducting for second predetermined states of said input control signal (CTLB) opposite from said first predetermined states. The semiconductor analog switch of Claim 1, wherein: said pass transistor (M7) has a second conductivity type opposite to said first conductivity type. The semiconductor analog switch of Claim 2, wherein: said first conductivity type is P type, wherein said first shunt transistor (M5) and said second shunt transistor (M6) are PMOS transistors; and said second conductivity type is N type, wherein said pass transistor (M7) is an NMOS transistor. The semiconductor analog switch of Claim 2, wherein: said first conductivity type is N type, wherein said first shunt transistor (M5) and said second shunt transistor (M6) are NMOS transistors; and said second conductivity type is P type, wherein said pass transistor (M7) is a PMOS transistor. The semiconductor analog switch of claim 1, wherein: said pass transistor (M7) has said first conductivity type. The semiconductor analog switch of Claim 5, wherein: said first conductivity type is P type, wherein said pass transistor (M7), said first shunt transistor (M5) and said second shunt transistor (M6) are PMOS transistors. The semiconductor analog switch of Claim 5, wherein: said first conductivity type is N type, wherein said pass transistor (M7), said first shunt transistor (M5) and said second shunt transistor (M6) are NMOS transistors. The semiconductor analog switch of claim 1, wherein: said drive circuit includes an inverter (INV1) having an input receiving said input control signal and an output connected to said gate of said pass transistor (M7), a first drive transistor (M1) of said first conductivity type having a fourth gate, a fourth source connected to said first node (V 1 ), and a fourth drain, a second drive transistor (M2) of said first conductivity type having a fifth gate connected to said fourth drain of said first drive transistor (M1), a fifth source connected to said first node (V 1 ), and a fifth drain connected to said second gate of said first shunt transistor (M5) and said fourth gate of said first drive transistor (M1), a third drive transistor (M3) of a second conductivity type opposite to said first conductivity type having a sixth gate receiving said input control signal (CTLB), a sixth drain connected to said fourth drain of said first drive transistor (M1) and said fifth gate of said second drive transistor (M2) and a sixth source connected to ground (GND), a fourth drive transistor (M4) of said second conductivity type having a seventh gate connected to said output of said inverter (INV1), a seventh drain connected to said fourth gate of said first drive transistor (M1), said drain of said second drive transistor (M2) and said second gate of said first shunt transistor (M5) and a seventh source connected to ground (GND), a fifth drive transistor (M9) of said first conductivity type having an eighth gate, an eighth source connected to said second node (V 2 ), and an eighth drain, a sixth drive transistor (M8) of said first conductivity type having a ninth gate connected to said eighth drain of said fifth drive transistor (M9), a ninth source connected to said second node (V 2 ), and a ninth drain connected to said third gate of said second shunt transistor (M6) and said eighth gate of said fifth drive transistor (M9), a seventh drive transistor (M11) of said second conductivity type having a tenth gate receiving said input signal (CTLB), a tenth drain connected to said ninth gate of said sixth drive transistor (M8) and said eighth drain of said fifth drive transistor (M9) and a tenth source connected to ground (GND), and an eighth drive transistor (M10) of said second conductivity type having an eleventh gate connected to said output of said inverter (INV1), an eleventh drain connected to said eighth gate of said fifth drive transistor (M9), said ninth drain of said sixth drive transistor (M8) and to said third gate of said second shunt transistor and an eleventh source connected to ground (GND). The semiconductor analog switch of Claim 1, wherein said first control signal (CTLB) comprises a logic level signal. The semiconductor analog switch of Claim 1, wherein said first control signal (CTLB) comprises a binary digit.

Inventors: MAROTTA GIULIO GIUSEPPE, MAROTTA, GIULIO GIUSEPPE, Marotta, Giulio Giuseppe, Texas Inst. Italia S.p.A
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS ITALIA SPA, TEXAS INSTRUMENTS INCORPORATED, TEXAS INSTRUMENTS ITALIA S.P.A.
Application year: 1995
Main classification: H03K17
IPC codes: H03K17, H03K3