Structure of contact between wiring layers in semiconductor integrated circuit device and method for forming the contact

Abstract: An insulation film is interposed between a first-level wiring layer (12-1) and a second-level wiring layer (16-1). A contact hole (14) is formed in the insulation film on the first-level wiring layer (12-1) to electrically connect the first-level wiring layer (12-1) and second-level wiring layer (16-1). The contact hole (14) is larger than the width of the first-level wiring layer (12-1) and second-level wiring layer (16-1). The second-level wiring layer (16-1) is formed on a side wall and a bottom portion of the contact hole (14) and electrically connected to the first-level wiring layer (12-1) at the bottom portion of the contact hole (14).

Description: The present invention relates to a semiconductor device according to the preamble of claim 1, to a semiconductor device having a bit-line contact portion of a DRAM, to a method of manufacturing a semiconductor device having a contact portion at which a first-level wiring layer and a second-wiring layer interposing a first insulating film are contacted to each other, and a method of manufacturing a semiconductor device having a bit-line contact portion of a DRAM. A semiconductor device according to the preamble of claim 1 is known from IEEE VOLS. MULTILEVEL INTERCONNECTION CONFERENCE, SANTA CLARA, no. 1985, IEEE, p. 123-130, "A TWO-LEVEL METALLIZATION SYSTEM WITH OVERSIZED VIAS AND A TI:W ETCH BARRIER". More specifically, the present invention relates to a structure of contact between wiring layers in a semiconductor integrated circuit device manufactured at a high degree of integration and a method for forming the contact. A prior art structure of contact between wiring layers in a semiconductor integrated circuit device and a prior art method of forming the contact are described in, for example, IEDM 83, pp. 530-553 "A PLANAR METALLIZATION PROCESS - ITS APPLICATION TO TRI-LEVEL ALUMINUM INTERCONNCECTION" Moriya et al., and Jpn. Pat. Appln. KOKOKU Publication No. 2-577070. FIG. 1 is a pattern plan view showing a conventional contact portion of a semiconductor integrated circuit device, and FIG. 2 is a cross-sectional view taken along the line 2 - 2 of FIG. 1. As shown in FIGS. 1 and 2, an insulation film 101 such as a field oxide film is provided on a semiconductor substrate 100 constituted by silicon or the like. First-level wiring layers 102-1 and 102-2 are formed in the first direction on the insulation film 101. An insulation film 103 of BPSG or the like is provided on the insulation film 101 and wiring layers 102-1 and 102-2. A contact hole 104 is formed in the insulation film 103 located on the wiring layer 102-1 and filled with a conductive filler 105 such as tungsten. Second-level wiring layers 106-1 and 106-2 are provided on the insulation film 103 in the second direction perpendicular to the first direction. The first-level wiring layer 102-1 and the second-level wiring layer 106-1 are electrically connected to each other by the conductive filler 105. The regions around the contact portion of the wiring layers 102-1 and 106-1 are formed widely in order to prevent fail connection due to mask displacement at the time of forming the contact hole 104. The foregoing contact portion is formed through the following steps. First an insulation film 101 is formed on a semiconductor substrate 100. If the insulation film 101 is a field oxide film, it is obtained by selectively oxidizing the major surface of the substrate 100 by, e.g., LOCOS. Secondly polysilicon or the like is deposited on the insulation film 101 to form first-level wiring layers 102-1 and 102-2 by patterning. An insulation film 103 is then formed on the resultant structure and its surface is planerized by reflow, CMP (Chemical Mechanical Polishing), or the like. After that, a contact hole 104 is formed in the insulation film 103 on the wiring layer 102-1 by anisotropic etching such as RIE. Tungsten, or the like is selectively grown on the wiring layer 102-1 in the contact hole 104 by LPCVD, or a conductive layer is formed on the entire surface of the insulation film 103 and etched back to leave it in the contact hole 104, with the result that the hole 104 is filled with a conductive filler 105. Finally tungsten, aluminum, or the like is deposited on the insulation film 103 by CVD, sputtering, etc. to form second-level wiring layers 106-1 and 106-2 by patterning. However, according to the structure of the contact portion and the method of forming the same, as described above, the first-level and second-level wiring layers require a margin Δα for mask alignment at each contact portion between the wiring layers. Assuming that the minimum dimension determined according to a design rule is D, the width of each wiring layer is D, the interval between the wiring layers is D + Δα, and the wiring pitch is 2D + Δα which is an index of degree of integration. This margin Δα is a hindrance to high degree of integration. The object of the present invention is to provide a semiconductor device and a manufacturing method having a contact portion between wiring layers which is favorable for high degree of integration. This object is solved by a semiconductor device with the characterizing features of claim 1, a semiconductor device with the features of claim 9, a method of manufacturing a semiconductor device with the steps of claim 12, and a method of manufacturing a semiconductor device with the steps of claim 14. The present invention advantageously provides a semiconductor device having a contact portion which requires no mask alignment margin and allows an interval between wiring layers to be set to the minimum according to a design rule. Further, the present invention provides a method for manufacturing a semiconductor device having a contact portion between wiring layers which is favorable for high degree of integration. In addition to that, the present invention provides a method for manufacturing a semiconductor device having a contact portion which requires no mask alignment margin and allows an interval between wiring layers to be set to the minimum according to a design rule. Since the constitution of a semiconductor device described above does not need a margin for preventing a fail contact due to mask displacement at the contact portion of the first- and second-level wiring layers, high degree of integration can be achieved. According to the foregoing manufacturing method, in patterning the first- and second-level wiring layers, they need not be provided with a margin for mask alignment but can be patterned with the minimum width and at the minimum intervals determined according to a design rule, thus improving in high degree of integration. Consequently, according to the present invention, a semiconductor device having a contact portion between wiring layers favorable for high degree of integration and a method of manufacturing the same, can be provided. Furthermore, a semiconductor device which requires no mask alignment margin and allows the dimension of a contact portion to be set to the minimum according to a design rule, can be provided. Additional features of the invention are specified in sub-claims being dependent or independent claims 1, 9, 12 or 14, respectively. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a pattern plan view of a contact portion of a semiconductor integrated circuit device, for explaining a prior art contact portion between wiring layers and a method of forming the same; FIG. 2 is a cross-sectional view taken along the line 2 - 2 of FIG. 1; FIG. 3 is a perspective view of a contact portion between a first-level wiring layer and a second-level wiring layer of a semiconductor integrated circuit device according to a first embodiment of the present invention; FIG. 4 is a pattern plan view of the contact portion of the semiconductor device according to the first embodiment of the present invention; FIG. 5A is a cross-sectional view taken along the line 5A - 5A of FIG. 4; FIG. 5B is a cross-sectional view taken along the line 5B - 5B of FIG. 4; FIGS. 6A, 7A, 8A and 9A are cross-sectional views taken along the line 5A - 5A of FIG. 4, showing the steps of forming the contact portions shown in FIGS. 3, 4, 5A and 5B; FIGS. 6B, 7B, 8B and 9B are cross-sectional views taken along the line 5B - 5B of FIG. 4, showing the steps of forming the contact portions shown in FIGS. 3, 4, 5A and 5B; FIG. 10 is a perspective view of a contact portion between a first-level wiring layer and a second-level wiring layer of a modification to the semiconductor integrated circuit device of the first embodiment shown in FIG. 3; FIG. 11 is a pattern plan view of the contact portion shown in FIG. 10; FIG. 12A is a cross-sectional view taken along the line 12A - 12A of FIG. 11; FIG. 12B is a cross-sectional view taken along the line 12B - 12B of FIG. 11; FIG. 13 is a pattern plan view of a contact portion of a semiconductor device according to a second embodiment of the present invention; FIG. 14A is a cross-sectional view taken along the line 14A - 14A of FIG. 13 and showing a process of manufacturing the semiconductor device of the second embodiment; FIG. 14B is a cross-sectional view taken along the line 14B - 14B of FIG. 13 and showing a process of manufacturing the semiconductor device of the second embodiment; FIG. 15A is a cross-sectional view taken along the line 14A - 14A of FIG. 13 and showing another process of manufacturing the semiconductor device of the second embodiment; FIG. 15B is a cross-sectional view taken along the line 14B - 14B of FIG. 13 and showing another process of manufacturing the semiconductor device of the second embodiment; FIG. 16A is a plan view schematically showing the arrangement of memory cells of a DRAM having a bit-line contact portion to which the present invention is applied, for explaining a semiconductor device according to a third embodiment of the present invention; FIG. 16B is a pattern plan view of one cell unit, for explaining a BEST (Buried Strap) cell as one example of the memory cells shown in FIG. 16A; FIG. 16C is a cross-sectional view taken along the line 16C - 16C of FIG. 16B; FIGS. 17A, 18A, 19A and 20A are cross-sectional views taken along the line 17A - 17A of FIG. 16A and showing steps of forming the bit-line contact portion of the DRAM shown in FIGS. 16A, 16B and 16C; FIGS. 17B, 18B, 19B and 20B are cross-sectional views taken along the line 17B - 17B of FIG. 16A and showing steps of forming the bit-line contact portion of the DRAM shown in FIGS. 16A, 16B and 16C; FIG. 21A is a cross-sectional view taken along the line 17A - 17A of FIG. 16A and showing a step of forming part of the bit-line contact portion of the DRAM, for explaining another example (fourth embodiment) wherein the present invention is applied to the bit-line contact portion; FIG. 21B is a cross-sectional view taken along the line 17B - 17B of FIG. 16A and showing a step of forming part of the bit-line contact portion of the DRAM, for explaining another example (fourth embodiment) wherein the present invention is applied to the bit-line contact portion; FIG. 22 is a cross-sectional view of the bit-line contact portion which is over-etched in the step shown in FIG. 19B; FIG. 23 is a cross-sectional view showing a constitution of a semiconductor device according to a fifth embodiment of the present invention, which prevents a short circuit from being caused between a bit line and a P well region shown in FIG. 22; and FIGS. 24 and 25 are cross-sectional views showing some of steps of manufacturing a semiconductor device according to a sixth embodiment of the present invention, which prevents a short circuit from being caused between a bit line and a P-well region. FIGS. 3, 4, 5A and 5B are views for explaining a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a perspective view showing a constitution of a contact portion between first-level and second-level wiring layers of the semiconductor device, FIG. 4 is a pattern plan view of the contact portion, FIG. 5A is a cross-sectional view taken along the line 5A - 5A of FIG. 4, and FIG. 5B is a cross-sectional view taken along the line 5B - 5B of FIG. 4. As shown in these figures, the contact portion is formed at a right-angled intersection of the first- and second-level wiring layers. As illustrated in FIGS. 4, 5A and 5B, an insulation film 11 such as a field oxide film is provided on a semiconductor substrate 10 constituted of silicon or the like. First-level wiring layers 12-1 and 12-2 are formed in the first direction on the insulation film 11. An insulation film 13 constituted of BPSG or the like is provided on the insulation film 11 and wiring layers 12-1 and 12-2. A contact hole 14 is formed in the insulation film on the wiring layer 12-1 to a depth reaching the upper surface of the wiring layer 12-1. A second-level wiring layer 16-1 is formed on the bottom and side wall portions of the contact hole 14, and the contact hole 14 is filled with an insulative filler 15 of SOG (Spin On Glass) or the like. The second-level wiring layers 16-1 and 16-2 are formed on the insulation film 13 in the second direction perpendicular to the first direction. As illustrated in FIGS. 3, 4, 5A and 5B, the second-level wiring layer 16-1 extends from the bottom and side wall portions of the contact hole 14 onto the insulation film 13 and contacts the first-level wiring layer 12-1 at the bottom portion of the hole 14, with the result that the first- and second-level wiring layers 12-1 and 16-1 are electrically connected to each other. The contact hole 14 is provided with a mask alignment margin Δα in order to prevent bad connection due to mask displacement. If the width of each of the wiring layers 12-1, 12-2, 16-1 and 16-2 is D, each side of the contact hole is given by D + 2Δα. With the above constitution, the width of each of the wiring layers 12-1, 12-2, 16-1 and 16-2 and the interval between them are represented by the minimum dimension D determined according to the design rule. Therefore, neither the wiring layer 12-1 nor 16-1 requires the alignment margin Δα, and the wiring pitch is 2D, with the result that a contact portion suitable for high degree of integration can be formed between the wiring layers. In the constitution shown in FIGS. 3, 4, 5A and 5B, the mask alignment margin Δα is required for the contact hole 14, and the alignment margin Δα as well as the minimum dimension D is required for an interval between the contact hole 14 and its adjacent one (not shown). In this respect, the constitution is the same as that of FIGS. 1 and 2. A method of forming the above-described contact portion will now be described in detail, with reference to FIGS. 6A through 9B. FIGS. 6A, 7A, 8A and 9A are cross-sectional views taken along the line 5A - 5A of FIG. 4 and showing the steps of forming the contact portion having the structure shown in FIG. 5A, while FIGS. 6B, 7B, 8B and 9B are cross-sectional views taken along the line 5B - 5B of FIG. 4 and showing the steps of forming the contact portion having the structure shown in FIG. 5B. As illustrated in FIGS. 6A and 6B, an insulation film 11 is formed on a semiconductor substrate 10. If the insulation film 11 is a field oxide film, the surface of the substrate 10 is selectively oxidized by, e.g., LOCOS. A conductive layer constituted of polysilicon or the like is deposited on the insulation film 11 to form first-level wiring layers 12-1 and 12-2 by patterning. An insulation film 13 is then formed on the resultant structure and its surface is planerized by reflow, CMP, or the like. After that, as shown in FIGS. 7A and 7B, a contact hole 14 is formed in the insulation film 13 on the wiring layer 12-1 by anisotropic etching such as RIE. The contact hole 14 is formed to a depth reaching the upper surface of the wiring layer 12-1, and its sides each have margins Δα on the right and left with respect to the width D of each of the wiring layers 12-1, 12-2, 16-1 and 16-2 in order to prevent fail contact due to mask displacement. More specifically, the width W1 of each of two sides of the hole 14, which intersect the first-level wiring layer 12-1, is greater than the width D1 of the layer 12-1 by 2Δα, and the width D2 of each of two sides of the hole 14, which intersect the second-level wiring layer 16-1, is greater than the width D of the layer 16-1 by Δα. Thereafter, a conductive layer of tungsten or the like is formed on the resultant structure by CVD, and the contact hole 14 is filled with an insulative filler 15 of SOG, etc.,, thereby completing the contact structure shown in FIGS. 8A and 8B. As shown in FIGS. 9A and 9B, photoresist 18 is applied onto the insulation film 13, wiring layers 16-1 and 16-2, and insulative filler 15, and treatment such as exposure and development is carried out to form a mask for patterning. Using this mask, the conductive layer is patterned by anisotropic etching such as RIE to form second-level wiring layers 16-1 and 16-2. Consequently, the contact structure is obtained as shown in FIGS. 4, 5A and 5B. According to the method described above, when the contact hole is formed in the insulation film 13 on the first-level wiring layer 12-1, if mask displacement falls within a range of ±Δα, reliable contact can be obtained between the first- and second-level wiring layers 12-1 and 16-1. Similarly, when the second-level wiring layer 16-1 is patterned, if mask displacement falls within a range of ±Δα, the reliable contact can be obtained between them. Furthermore, it is only the contact hole 14 that requires the margin Δα, and the first-level wiring layers 12-1 and 12-2 and second-level wiring layers 16-1 and 16-2 can be formed so as to have the minimum width and the minimum pitch which are determined on the basis of the design rule. Consequently, a semiconductor device having the contact structure suitable for high-degree of integration can be manufactured. In the foregoing first embodiment, the first-level wiring layers 12-1 and 12-2 and the second-level wiring layers 16-1 and 16-2 cross at right angles. However, even if they are arranged in parallel with each other as shown in FIGS. 10, 11, 12A and 12B, the same advantage can be obtained. FIG. 10 is a perspective view of the structure of a contact portion between first- and second-level wiring layers 12-1 and 16-1 of a semiconductor integrated circuit device, FIG. 11 is a pattern plan view of the contact portion shown in FIG. 10, FIG. 12A is a cross-sectional view taken along the line 12A - 12A of FIG. 11, and FIG. 12B is a cross-sectional view taken along the line 12B - 12B. In FIGS. 10, 11, 12A and 12B, the same structural elements as those of FIGS. 3, 4, 5A and 5B are denoted by the same reference numerals, and their detailed description is omitted. FIGS. 13, 14A and 14B are views for explaining a semiconductor device according to a second embodiment of the present invention. FIG. 13 is a pattern plan view of a contact portion of the semiconductor device, FIG. 14A is a cross-sectional view taken along the line 14A - 14A of FIG. 13 and showing a process of manufacturing the semiconductor device, and FIG. 14B is a cross-sectional view taken along the line 14B - 14B of FIG. 13 and showing a process of manufacturing the semiconductor device. In the first embodiment, the contact hole 14 is filled with the insulative filler 15, whereas in the second embodiment, it is not filled with any insulative filler. In the second embodiment, the step of forming a conductive layer as a second-level wiring layer, that is, the steps shown in FIGS. 6A, 6B, 7A and 7B through the step of forming a conductive layer, are the same as those of the first embodiment. After the formation of the conductive layer, as shown in FIGS. 14A and 14B, the contact hole 14 is not filled with an insulative filler, but photoresist 18 is applied thereto, and treatment such as exposure and development is carried out to form a mask for patterning second-level wiring layers 16-1 and 16-2. Using the photoresist 18 as a mask, the conductive layer is patterned by anisotropic etching such as RIE to form second-level wiring layers 16-1 and 16-2. In the above manufacturing method according to the second embodiment, as illustrated in FIG. 14B, since an interval between photoresist 18 and contact hole 14 is considerably smaller than the minimum dimension, it does not exceed the resolution limit in the lithography process, with the result that an unexposed portion remains. The unexposed portion prevents a bottom region of the contact hole 14 on the second-level wiring layer 16-2 from being etched. Therefore, the contact hole 14 need not be filled with an insulative filler 15 but can be filled with the photoresist 18 when the second-level wiring layers 16-1 and 16-2 are formed. The same patterning can thus be achieved as in the case of using the filler 15. Even though the thickness ΔT of the second-level wiring layer 16-1 is considerably increased compared with each of the widths W1 and W2 of the contact hole 14 in accordance with an improvement in degree of integration, the hole 14 need not be filled with the insulative filler 15. The reason is as follows. If "2ΔT, which is two times the thickness ΔT of the second-level wiring layer 16-1, is larger than each of the widths W1 and W2 (2ΔT ≧ W1, 2ΔT ≧ W2), the contact hole 14 is filled with the second-level wiring layer 16-1 when a conductive layer serving as the layer 16-1 is formed, as shown in FIGS. 15A and 15B. Consequently, the same advantage as that of the first embodiment can be obtained from the constitution and manufacture method of the semiconductor device of the second embodiment shown in FIGS. 13, 14A, 14B, 15A and 15B. Needless to say, the second embodiment can also be applied to the contact portions between the first-level wiring layers 12-1 and 12-2 and the second-level wiring layers 16-1 and 16-2 arranged in parallel with each other, as in the first embodiment shown in FIGS. 10, 11, 12A and 12B. An example of applying the present invention to a bit-line contact portion of a DRAM, will now be described. FIG. 16A schematically shows the arrangement of memory cells of the DRAM to explain a semiconductor device according to a third embodiment of the present invention. As illustrated in FIG. 16A, word lines 22 are arranged in parallel and at regular intervals, and each bit-line contact portion 23 is interposed adjacent capacitors 21. A region 24 surrounded with a broken line corresponds to one unit of cell. IEDM Technical Digest, 1993, pp. 627-630 describes a 256 Mbit BEST (Buried Strap) cell as a cell structure of the DRAM. The BEST cell will be described in brief, with reference to FIGS. 16B and 16C. FIG. 16B is a pattern plan view showing one unit of cell, and FIG. 16C is a cross-sectional view taken along the line 16C - 16C of FIG. 16B. A burial N-well region 31 is formed on a surface region of a semiconductor substrate 30, and a P-well region 32 is formed on a surface region of the N-well region 31. A trench 33 is formed so as to extend from the surface of the P-well region 32 into the N-well region 31. A layered film (ON film) 34 of an oxide film and a nitride film is formed in the vicinity of a bottom portion of the trench 33. A first N + -type polysilicon layer 35 is buried in the bottom portion of the trench 33. An oxide film collar 36 is provided on the upper side wall portion of the trench 33. A second N + -type polysilicon layer 37 is buried in the trench 33 on the polysilicon layer 35. A third N + -type polysilicon layer 38 is buried in the uppermost portion of the trench 33. A burial strap 39 is formed so as to extend from a surface region of the P-well region toward the side wall portion of the trench 33. Gate electrodes (polysilicon layers) 41 serving as word lines are formed on the P-well region 32 and provided on an STI (Shallow Trench Isolation) 40 on the trench 33. SiN films 47 are formed on the gate electrodes 41. A spacer 48 of SiN film is formed on the gate electrodes 41, SiN films 47, and an exposed surface of the strap 39. An insulation film 42 of BPSG or the like is formed on the resultant structure. A bit-line contact portion 43 is provided in the insulation film 42 adjacent to the gate electrode 41 and filled with a fourth N + -type polysilicon layer 44. An N - -type diffusion layer 49 serving as a source/drain region is formed in the P-well region 32 on the bottom of the contact portion 43. A bit line 45 is formed on the insulation film 42 and electrically connected to the diffusion layer 49 through the polysilicon layer 44. A region between the gate electrode 41 and trench 33 is used as an active region 46. The BEST cell having the above constitution is manufactured through the following process. First a burial N well region 31 and a P-well region 32 are formed in a semiconductor substrate 30, and then a trench 33 is formed in the substrate 30. An ON (oxide/nitride) film 34 is formed on the inner wall of the trench 33, and the trench is filled with a first N + -type polysilicon layer 35, thus forming a capacitor in which the ON film 34 serves as a capacitor insulation film and the N + -type polysilicon layer 35 and burial N-well region 31 serve as electrodes. After that, the polysilicon layer 35 is etched back below the interface between the P- and N-well regions 32 and 31, and an oxide film collar 36 is formed on the N + -type polysilicon layer 35. A portion of the oxide film collar 36 located above the polysilicon layer 37 is removed by etching to form a third N + -type polysilicon layer 38 and a burial strap 39. An STI 40 is formed, and a gate electrode (polysilicon) 41 serving as a word line is formed on the substrate through a gate insulation film (not shown). An insulation film 42 of BPSG or the like is formed on the resultant structure and its surface is planerized by a method such as reflow and CMP. Thereafter, a bit-line contact portion (contact hole) 43 is self-aligned with the gate electrode 41, and the contact hole is filled with a fourth N + -type polysilicon layer 44. A conductive layer is formed on the insulation film 42 to form a bit line 45 by patterning. The bit line 45 is electrically connected to an N - -type diffusion layer 49, serving as a source/drain region, through the polysilicon layer 44. The application of the present invention to the bit-line contact portion of the DRAM shown in FIGS. 16B and 16C, will be described in detail, with reference to FIGS. 17A through 20B. The bit-line contact portion is common to two adjacent cells, and two selective MOS transistors connected to the bit-line contact portion are shown. FIGS. 17A, 18A, 19A and 20A are cross-sectional views taken along the line 17A - 17A of FIG. 16A and showing steps of forming the bit-line contact portion, and FIGS. 17B, 18B, 19B and 20B are cross-sectional views taken along the line 17B - 17B of FIG. 16A and showing steps of forming the bit-line contact portion. As shown in FIGS. 17A and 17B, the same process as that shown in FIGS. 16B and 16C is executed up to the step of forming the STI 40. After this step, a gate insulation film (not shown) is formed on a P-well region 32, and then an N + -type polysilicon layer and a SiN film are formed in sequence on the gate insulation film, thus forming a gate electrode 41 by patterning. A SiN film 47 remains on the gate electrode 41. Using the gate electrode 41 and SiN film 47 as a mask, impurities are ion-implanted into the P-well region 32 to form an N - -type diffusion layer 49 serving as a source/drain region. After that, a spacer 48 of SiN film is formed on the side wall portions of the gate electrode 41 and SiN film 47. A BPSG film 42 is deposited on the resultant structure and its surface is planerized (see FIGS. 18A and 18B). The BPSG film 42 and SiN film 47 are selectively etched by the RIE using a mask thereby to form a bit-line contact portion (contact hole) 50. Subsequently a film 45 of tungsten or a layered film 45 that of tungsten/titanium/nitride is formed on the resultant structure (FIGS. 19A and 19B). In the subsequent manufacturing step, as in the first embodiment described above, the bit-line contact portion 50 is filled with SOG 51, and the layered film is patterned by the RIE using photoresist 52 as a mask, thereby forming a bit line 45 (FIGS. 20A and 20B). In the third embodiment, as shown in FIGS. 21A and 21B, the bit line 45 can be formed by patterning, without filling the bit-line contact portion 50, as in the second embodiment. FIG. 22 shows the bit-line contact portion 50 which is over-etched in the etching step of the insulation film 42 after the step shown in FIG. 18B. If the bit line 45 is formed with the contact portion over-etched, it will be short-circuited with the exposed P-well region 32. To prevent this short circuit, in the fifth embodiment shown in FIG. 23, the N - -type diffusion layer (source/drain region) 49 is deeply formed in advance in view of over-etching. FIGS. 24 and 25 show steps of manufacturing a semi-conductor device according to a sixth embodiment of the present invention, which prevents a short circuit from being caused between the bit line 45 and P-well region 32. As shown in FIG. 24, ions are implanted diagonally two times in the contact portion 50, as indicated by the solid and broken lines, and the N - -type diffusion layer 49 is formed on the side wall portion of the P-well region 32 as well as on the upper surface of a projecting portion thereof. Consequently, the short circuit can be prevented since an N - -type diffusion layer 53 is interposed between the bit line 45 and the exposed portion of P-well region 32. As described above, in the contact portion between the wiring layers and the method of forming the same according to the present invention, the width of each of the first- and second-level wiring layers 12-1, 12-2, 16-1 and 16-2 and the interval between them can be set to the minimum dimension D determined on the basis of the design rule, as shown in FIG. 4. The wiring pitch, which is an index of degree of integration, is 2D and thus suitable for high degree of integration. The mask alignment margin Δα for forming the contact hole 14 is set to uniform the contact resistance, that is, the contact area between the first- and second-level wiring layers and does not have any influence on the wiring pitch. Since, in the second embodiment, the manufacturing process can be made simpler than that of the first embodiment, a low-cost semiconductor device can be obtained. If the present invention is applied to a DRAM as in the third embodiment, the most advance device is achieved and thus the greater advantages of high degree of integration and low cost can be obtained. The fifth embodiment produces an effect of preventing a short circuit from being caused between the bit line and P-well region, and the sixth embodiment produces a special effect of preventing a short circuit from being caused between them without increasing diffusion depth Xj of the N - -type diffusion layer. The present invention is not limited to the foregoing embodiments. It is needless to say that various changes and modifications can be made without departing from the scope of the subject matter of the present invention. As described above, according to the present invention, a semiconductor device having a contact portion between wiring layers suitable for high degree of integration, and a method for manufacturing the same can be obtained.

Claims: A semiconductor device comprising at least one first-level wiring layer (12-1) having a first width and being provided in a first direction above a semiconductor substrate; a first insulating film (13) formed on on said first-level layer (12-1); a contact hole (14) formed in said first insulating film (13), which is wider than said first width of said first-level wiring layer (12-1); and a second-level wiring layer (16-1) having a second width formed on said first first insulating film (13) in a second direction and at least on a side wall and bottom portion of said contact hole (14) and electrically connected to said at least one first-level wiring layer (12-1) through said contact hole (14), wherein said contact hole (14) reaches at least an upper surface of said at least one first-level wiring layer (12-1); and said at least one second-level layer (16-1) contacts said at least one first-level wiring layer (12-1) at the bottom portion of said contact hole (14); characterized in that : said second-level wiring layer (16-1) in said contact hole (14) has a first portion covering the bottom portion and the sidewalls of said contact hole (14) to a height lying below the surface of said first insulating film (13), and a second portion integrally connecting said first portion and said second-level wiring layer (16-1) on said first insulating film (13), thereby covering the entire height of the sidewall where said second-level wiring layer (16-1) extends into said contact hole (14). The semiconductor device according to claim 1, characterized in that said first direction and said second direction intersect, and said contact hole (14) is formed at an intersection of said at least one first-level wiring layer (12-1) and said at least one second-level wiring layer (16-1). The semiconductor device according to claim 1 or 2, characterized in that said first direction and said second direction are parallel;, and said contact hole (14) is formed at an overlap portion of said first-level wiring layer (12-1) and said second-level wiring layer (16-1). The semiconductor device according to any of claims to to 3, comprising a plurality of said first-level wiring layers (12-1, 12-2) formed in a first direction and in parallel with one another, with a minimum width; and a plurality of said second-level wiring layers (16-1, 16-2) formed on said first insulating film (13) in a second direction perpendicular to said first direction and in parallel with one another, with a minimum width; wherein a side of said contact hole (14) parallel with a first direction is longer than a width (D) of said second-level wiring layers (16-1, 16-2) and shorter than a length two times an interval (D) between said second-level wiring layers (16-1, 16-2) plus the width (D) of said second-level wiring layers, a side of said contact hole (14) parallel with a second direction being longer than a width (D) of said first-level wiring layers (12-1, 12-2) and shorter than a length two times an interval (D) between said first-level wiring layers (12-1, 12-2) plus the width (D) of said first-level wiring layers (12-1, 12-2). The semiconductor device according to any of claims 1 to 3, comprising a plurality of said first-level wiring layers (12-1, 12-2) formed in parallel with one another, with a minimum width, and a plurality of said second-level wiring layers (16-1, 16-2) formed in parallel with one another along said plurality of first-level wiring layers (12-1, 12-2), with a minimum width; wherein a side of said contact hole (14) perpendicular to said plurality of first-level wiring layers (12-1, 12-2) and said plurality of second-level wiring layers (16-1, 16-2) is longer than a width (D) of said plurality of first-level wiring layers (12-1) and (12-2) and said plurality of second-level wiring layers (16-1, 16-2) and shorter than a length two times an interval (D) between said plurality of first-level wiring layers (12-1, 12-2) and said plurality of second-level wiring layers (16-1, 16-2) plus the width (D) of said plurality of first-level wiring layers (12-1, 12-2) and said plurality of second-level wiring layers (16-1, 16-2). The semiconductor device according to any of the preceding claims, characterized in that said at least one first-level wiring layer (12-1) is formed on an second insulation film (11). The semiconductor device according to any of the preceding claims, characterized by further comprising a third insulation film (15) which is formed on said at least one second-level wiring layer (16-1) to fill said contact hole (14). The semiconductor device according to any of tghe preceding claims, characterized in that said at least one second-level wiring layer (16-1) fills at least said contact hole (14). A semiconductor device having a bit-line contact portion of a DRAM and comprising: element isolation regions (40) formed on a semiconductor substrate (30, 31, 32); a plurality of gate electrodes (41) formed on a surface of said semiconductor substrate (32) through a gate insulation film and connected to a word line; pairs of source/drain regions (49, 39) formed in said semiconductor substrate (32) on opposing sides of said plurality of gate electrodes; an insulation film (42) coating said source/drain regions (49; 39); a contact hole (50) formed in said insulation film (42) above one (49) of said source/drain regions (49, 39) so as to expose part of one of said plurality of gate electrodes (41) and part of one of one of said element isolation regions (40); a bit line (45) provided on said insulation film (42) and in contact to the one (49) of said source/drain regions (49, 39) and coating a side wall and a bottom of said contact hole (50); and a capacitor (21) electrically connected to another (39) of said source/drain regions (49, 39); characterized in that the width of the bit-line (45) on said insulation film (42) is smaller than the diameter of said contact hole (50); and said bit-line in said contact hole (50) has a first portion covering the bottom portion and the sidewalls of said contact hole to a height lying below the surface of said insulation film (42), and a second portion integrally connecting said first portion and said bit-line on said insulation film, thereby covering the entire height of the sidewall where said bit-line extends into said contact hole. The semiconductor device according to claim 9, characterized in that an upper surface of said one (49) of said source/drain regions (49, 39) is higher in level than an upper surface of said element isolation region (40) and the depth of said one (49) of said source/drain regions is greater than that of a step portion formed by a difference in level between the upper surface of said one (49) of said source/drain regions and said upper surface of said element isolation region (40). The semiconductor device according to claim 9, characterized in that an upper surface of the one (49) of said source/drain regions (49, 39) is higher in level than an upper surface of said element isolation region (40), a depth of the one (49) of said source/drain regions is smaller than that of a step portion formed by a difference in level between the upper surface of said source/drain regions (49, 39) and the upper surface of said element isolation region (40), and the one (49) of said source/drain regions extend onto a sidewall of the step portion. A method of manufacturing a semiconductor device having a contact portion at which a first-level wiring layer and a second-level wiring layer, interposing a first insulation film, are in contact to each other, comprising the steps of: forming said first-level wiring layer (12-1, 12-2), having a first width, in a first direction above a semiconductor substrate; forming a first insulation film (13) coating said first-level wiring layer (12-1, 12-2); forming a contact hole (14) in said first insulation film (13) to a depth reaching an upper surface of said at least one first-level wiring layer (12-1, 12-2), said contact hole (14) being larger than the first width of said first-level wiring layer (12-1, 12-2); forming at least one second-level wiring material on the resultant structure; applying photoresist (18) to the resultant structure and patterning said photoresist to leave a portion having a width which is smaller than a diameter of said contact hole (14) and covering a bottom portion of said contact hole; and patterning said at least one second-level wiring material using said photoresist (18) as a mask thereby to form said second-level wiring layer (16-1, 16-2); whereby said second-level wiring layer (16-1, 16-2) in said contact hole (14) has a first portion covering the bottom portion and the sidewalls of said contact hole (14) to a height lying below the surface of said first insulating film (13), and a second portion integrally connecting said first portion and said second-level wiring layer (16-1, 16-2) on said first insulating film (13), thereby covering the entire height of the sidewall where said second-level wiring layer (16-1, 16-2) extends into said contact hole (14). A method according to claim 12, wherein after providing at least one second-level wiring material on the resultant structure a second insulation film (15) is deposited on said second wiring layer in said contact hole (14); and said second insulation film and said photoresist (18) are used (15) as a mask to form said second-level wiring layer (16-1, 16-2). A method of manufacturing a semiconductor device having a bit-line contact portion of a DRAM, characterized by comprising the steps of: forming element isolation regions (40) on a semiconductor substrate (30, 31, 32) at minimum intervals determined according to a design rule; forming a gate insulation film on a surface of said semiconductor substrate (32) and forming a plurality of gate electrodes (41) on said gate insulation film and connected to a word line; forming pairs of source/drain regions (49, 39) in said semi-conductor substrate (32) on opposing sides of said plurality of said gate electrodes; forming an insulation film (42) coating said source/drain regions (49, 39); forming a contact hole (50) in said insulation film (42) above one (49) of said source/drain regions so as to expose part of one of said plurality of gate electrodes (41) and part of said element isolation region (40); forming a bit line (45) on said insulation film (42) and connected to the one (49) of said source/drain regions and coating a side wall and a bottom of said contact hole (50); and forming a capacitor (35) electrically connected to another (39) of said source/drain regions; characterized in that the width of the bit-line (45) on said insulation film (42) is smaller than the diameter of said contact hole (50); and said bit-line in said contact hole (50) has a first portion covering the bottom portion and the sidewalls of said contact hole to a height lying below the surface of said insulation film (42), and a second portion integrally connecting said first portion and said bit-line on said insulation film, thereby covering the entire height of the sidewall where said bit-line extends into said contact hole. The method according to claim 14, characterized by further comprising the step of etching part of said element isolation region (40) at the same time when said contact hole (50) is formed, and forming source/drain regions (49, 53) extending to an exposed sidewall of said semiconductor substrate (32). The method according to claim 15, characterized in that said step of forming said source/drain regions (49, 53) extending to the exposed side wall of said semiconductor substrate (32) is executed by implanting ions at least two times.

Inventors: KOHYAMA YUSUKE, KOHYAMA, YUSUKE, KOHYAMA, YUSUKE, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1995
Main classification: H01L23
IPC codes: H01L27, H01L21, H01L23