Image reader with high-resolution mode and high-speed mode

Abstract: A reader having a high-resolution mode and a high-speed mode is disclosed. The reader comprises a CCD sensor (40), a buffer (41), a first AD convertor (51), a second AD convertor (42), a data selector (53) and a control circuit (52). The input of the buffer (41) is connected to the CCD sensor (40) through a capacitor (C) and a 5 V power source through an analog switch, and an output of the buffer (41) is connected to the first AD convertor (51) for the high-resolution mode and the second AD convertor (42) for the high-speed mode in parallel. The data selector (53) is connected to the outputs of the first AD convertor (51) and the second AD convertor (42), in order to select one of outputs from the first or the second AD convertor and sends it out to the control circuit (52).

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reader having a high-resolution mode and high-speed mode with the features of the precharacterizing part of claim 1. Such a reader is known from EP-A-0 613 289. 2. Description of the related Art Recently, as means for inputting a document and drawing data or input means for digital copiers and facsimile, there has been widely used a reader using a CCD sensor. A CCD sensor used in this reader will be described by referring to Fig. 5. Analog shift registers arranged in odd rows and analog shift register arranged in even rows are finally combined into an output signal CCD OUT through buffers. Symbols S 1 , S 2 , ..., S N denote light receiving means, OSR 1 , OSR 2 , ..., OSR N/2 denote odd-row shift registers for shifting out the analog outputs of light receiving means on the odd side (light receiving means arranged in odd rows) and ESR 1 , OSR 2 , ..., OSR N/2 denote even-row shift registers for shifting out the analog outputs of light receiving means on the even side (light receiving means arranged in even rows). Furthermore, symbol SH denote a start pulse for the shift operation of the shift registers, symbols ⊘ 1 and ⊘ 2 denote transfer pulses, and symbol ⊘ R denotes a reset pulse. Then, referring to Fig. 3, the positional relationship between a line-shaped fluorescent lamp 33 and a CCD sensor 37 in a reader will be described. A manuscript 31 is laid on a glass table 32. In Fig. 3, the glass table 32 and the manuscript 31 are spaced from each other but actually are closely in contact with each other. The manuscript 31 is illuminated through the glass table 32 with a ray of light emitted from the fluorescent lamp 33 with the longitudinal direction placed vertically to the surface of a paper. The ray of light reflected from the manuscript passes again through the glass table and is reflected from the mirror 35. The ray of light reflected from the mirror 35 is focussed at a lens 36 and illuminated to the light receiving surface of the CCD sensor 37. Numeral 34 denotes an optical unit including the mirror 35, the lens 36 and the CCD sensor 37, while numerals 38 and 39 denote a pulse motor and a cabinet, respectively. As shown in Fig. 4, a conventional reader incorporates a CCD sensor 40 for converting a received light into an electrical signal and the CCD sensor 40 is connected via a capacitor C to an input of a buffer 41. The input of the buffer 41 is connected to a 5 V electric power source via an analog switch. The output of the buffer 41 is connected to the input of an AD convertor 42. The outputs D 0 - D 7 of the AD convertor 42 are connected to a control circuit 43. The output FLON of the control circuit 43 is connected to the input of a lighting device 47. The output of the lighting device 47 is connected to the input of a fluorescent lamp 33. When the FLON turns to "1", the fluorescent lamp 33 turns on. The outputs T STEP and FORWARD of the control circuit 43 are connected to the input of a pulse motor drive circuit 46. The output of the pulse motor drive circuit 46 is connected to the input of a pulse motor 38. If "FORWARD" is "1", the pulse motor 38 is rotated by the pulse motor drive circuit 46 so as to forward the optical unit 34 and the fluorescent lamp 33 by one step, when the pulse motor receives one time of T STEP pulse. Similarly, if "FORWARD" is "0", the pulse motor 38 is rotated so as to reverse the optical unit 34 and the fluorescent lamp 33, when the pulse motor receives the T STEP pulse. The control circuit 43 comprises an oscillator 44 and a clock generating circuit 45 connected thereto. A basic clock t 0 is oscillated by the oscillator 44 and divided in frequency by the clock generating circuit 45 to generate various control pulses SH, ⊘ 1 , ⊘ 2 , ⊘ R and T CLAMP . Control pulses SH, ⊘ 1 , ⊘ 2 and ⊘ R are supplied to the CCD sensor 40 and a control pulse T CLAMP is supplied to the analog switch. Fig. 2 shows drive signals SH, ⊘ 1 , ⊘ 2 and ⊘ R to the CCD sensor 40, a CCD output CCD out , a clamp signal T CLAMP for clamping the CCD out , a timing of ADIN which is an input signal to the AD convertor 42. Then, the operation of an analog switch and C shown in Fig. 4 will be described. Ordinarily, the CCD output CCD out is not defined as a DC signal, for example, outputted in the negative direction from a standard voltage of 4 V, as shown in Fig. 2. This standard varies between 3.5 V and 4.5 V according to each CCD sensors. However, since the AD convertor will digitalize an analog voltage of 5 V or less, it is necessary to shift the DC level in such a manner that a value of output voltage from the capacitor C and the analog switch may be 5 V or less. Thus, the capacitor C comes to be always charged to 1 V. Here, the CCD out has a load of long transmission path and is usually amplified in use, and accordingly noises in the relevant amplifier are randomly superimposed onto the CCD out . For example, the DC level of the CCD out is normally 4 V but is assumed to become 3.8 V due to the random noises mentioned above. At this time, C has to be rapidly charged to 1.2 V, that is 0.2 V higher than a normal 1 V. Thus, setting the clamp time to t = 300 nsec and the ON resistance of the analog switch to 50 Ω, the capacitance C becomes as follows: C Ω R << t C ≦ 300 nsec/50 Ω = 6000 pF. In conventional scanners, a value of 1000 pF or less is selected. By secure clamping of the DC level of each individual CCD signal outputs in this way, an image with reduced random noise is obtained as a reader. On the other hand, Japanese Patent Application Laying Open No. 5-48460 discloses a three-dimensional integrated circuit comprising an AD convertor for executing a digital to analog conversion with high-speed and high-resolution. However, in a reader described by referring to Figures 2 to 5, though an image with reduced random noise is obtained as a reader, by secure clamping of the DC level of each individual CCD signal outputs, the stable period for the CCD out is further needed before and after the clamp signal T CLAMP , thereby the operating speed becomes slower. In addition, a three-dimensional integrated circuit disclosed in Japanese Patent Application Laying Open No. 5-48460 comprises a complicated circuit and becomes slower in the rate of AD conversion than ordinary AD convertor. In order to solve these problems, as shown in EP-A-o 613 289 corresponding to the Japanese Patent Application Laying Open No. 6-253091, the Applicant of the present invention proposes a reader comprising: a CCD sensor for individually outputting an output of the light receiving section arranged in odd rows and an output of that arranged in even rows; a first AD converter corresponding to either one of the outputs of odd rows or even rows; a second AD converter corresponding to the other of the outputs of odd rows or even rows; and means for supplying the other of the outputs of odd rows or even rows to the first AD converter when a high-resolution mode is selected. The AD converters in the reader are outputting digital data having the same bit number. In the high-speed mode, the reader outputs the digital signal in high speed by switching the two AD converters alternatively. However, in the reader of EP-A-0 613 289 and the Japanese Patent Application Laying Open No. 6-253091, the quality in the high-resolution mode is equal to the quality of the ordinary reader, though the device becomes complicated. US-A-5 053 771 discloses a dual range AD converter having two AD converters 29 and 31 for outputting digital data in different bit numbers (L-bits, M-bits). The two outputs from the two AD converters are combined and modified into one output signal at the output circuit 33 in accordance with parameters set up via the input 35. JP-A-62-156611 discloses an automatic focus detector having a microprocessor for shortening the electric charge storage time and raising the transfer clock frequency of the CCD. US-A-4 733 217 discloses a subranging AD converter having a coarse AD converter and first and second fine AD converters being operated alternatively and a combining circuit for outputting a digital signal from the three AD converters. It is therefore an object of the present invention to provide a reader capable of selecting either the high-resolution mode or the high-speed mode and further enabling a reading performance at higher speed in the high-speed mode and/or at higher quality in the high-resolution mode. According to the present invention, the above object is achieved by a reader having a high-resolution mode and a high speed mode, comprising a CCD sensor for converting a received light into an electrical signal, a first and a second AD converter each for converting the output signal of said CCD sensor into a digital signal, respectively, selecting means and control means, characterized in that the bit number of the output digital signal from said second AD converter is less than that of said first AD converter, said selecting means selects the output signal from said first AD converter in said high-resolution mode, and selects the output signal from said second AD converter in said high-speed mode, and said control means controls each of the reading periods for said high-resolution mode and said high-speed mode and forwards the position of a reset pulse for said CCD sensor in the reading period for said high-speed mode so as to stabilize the output signal level of said CCD sensor. Preferably, the conversion period of the second AD converter 41 is shorter than that of said first AD converter 51. Further preferably, the ratio of the conversion period in the reading period of the high-speed mode is less than that of said high-resolution mode. In the reader according to the present invention, a ray of light reflected from a manuscript is received by the CCD sensor for converting the light into an electric signal, and an output of the CCD sensor is converted into a digital signal with a high-quality and accuracy by the first AD converter when a high-resolution mode is selected. On the other hand, when a high-speed read is selected, a ray of light reflected from a manuscript is received by the CCD sensor for converting the light into an electric signal, and an output of the CCD sensor is converted into a digital signal by the second AD converter in fewer bits than those of said first AD converter, thereby enabling the read to be performed at higher speed in the high-speed mode and at higher quality in the high-resolution mode. Accordingly, it is possible to obtain desired resolution corresponding to various images in a single scanner by switching the AD converters by the output selection means. Further preferably, the reader further comprises a buffer and an analog switch for clamping the output of said CCD sensor to a predetermined DC voltage supplied from the power source in accordance with the control signal from said control means. In a further preferred development, said control means includes an oscillator for generating a base clock signal and an clock generating circuit for generating a plurality of clock signals by dividing the base clock signal in its frequency. It is further preferred in the embodiment of the present invention that said first AD converter converts an analog signal to a digital signal of twelve bits and that said second AD converter converts an analog signal into a digital signal of eight bits. Accordingly, it is possible to perform a high-speed image reading process in the high-speed mode and obtaining a stable black level for enabling a stable output image to be obtained. Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiment of the invention as illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the constitution of a reader according to one embodiment of the present invention; Fig. 2 is the timing chart of a conventional reader; Fig. 3 is a schematic drawing of a reader; Fig. 4 is a block diagram showing the constitution of a conventional reader; Fig. 5 is a block diagram of a CCD used in a conventional reader; Fig. 6 is a circuit diagram showing a clock generating circuit in the embodiment of Fig. 1; Fig. 7A is a first timing chart showing the operation of the embodiment of Fig. 1 in the high-resolution mode; Fig. 7B is a first timing chart showing the operation of the embodiment of Fig. 1 in the high-speed mode; Fig. 8A is a second timing chart showing the operation of the embodiment of Fig. 1 in the high-resolution mode; Fig. 8B is a second timing chart showing the operation of the embodiment of Fig. 1 in the high-speed mode; and Fig. 9 is a timing chart showing the operation of the embodiment of Fig. 1 in different brightness cases of a manuscript. DESCRIPTION OF THE PREFERRED EMBODIMENT Next, the embodiment of the present invention will be described by referring to the drawings. As shown in Fig. 1, a reader according to the present invention comprises a fluorescent lamp 33 for illuminating light onto a manuscript, a control circuit 52 for controlling each section and a CCD sensor 40 for receiving a ray of light reflected from the manuscript and converting it into an electrical signal. The fluorescent lamp 33 is connected to the control circuit 52 through a lighting device 47 for controlling a lighting. The output FLON of the control circuit 52 is connected to the input of the lighting device 47. The output of the lighting device 47 is connected to the input of the fluorescent lamp 33. When the FLON turns to "1", the fluorescent lamp 33 is put on. On the other hand, the CCD sensor 40 is connected to the input of a buffer 41 through the capacitor C, and a 5 V electric power source is connected to the input of the buffer 41 through the analog switch. Because the black level of CCD signals is ordinarily approx. 4 V (varies between 3 V and 5 V with different CCDs), an output voltage value ADIN of the buffer 41 is adjusted accurately to 5 V under action of a clamp signal T CLAMP . To the output of the buffer 41, a 12-bit first AD convertor 51 for the high-resolution mode and an 8-bit second AD convertor 42 for the high-speed mode are connected in parallel, while a reset pulse ⊘ R is inputted to the first AD convertor 51 and the second AD convertor 42. Also, to the output of the first AD convertor 51 and that of the second AD convertor 42, a data selector 53 for selecting an output from the first AD convertor 51 or the second AD convertor 42 and for sending it out to the control circuit 52 is connected. Furthermore, to the control circuit 52, a pulse motor drive circuit 46 for driving and controlling a pulse motor 38 is connected, and outputs T STEP and FORWARD of the control circuit 52 are inputted to the pulse motor drive circuit 46. On receiving one time of T STEP pulse when FORWARD is "1", the pulse motor is rotated by the pulse motor drive circuit 46 in such a way that the optical unit 34 and the fluorescent lamp 33 advance by one step. Similarly, on receiving one time of T STEP pulse when Forward is "0", the pulse motor is rotated in such a way that the optical unit 34 and the fluorescent lamp 33 reverse. The control circuit 52 comprises an oscillator 44 and a clock generating circuit 45 connecting therewith. A basic clock t 0 is oscillated by the oscillator 44 and divided in frequency by the clock generating circuit 45, so that various control pulses SH, ⊘ 1 , ⊘ 2 , ⊘ R and T CLAMP are generated. Control pulses SH, ⊘ 1 , ⊘ 2 and ⊘ R are supplied to the CCD sensor 40, and the control pulse T CLAMP is supplied to the analog switch. Incidentally, the first AD convertor 51 and second AD convertor 42 convert the portion of 5 V or less in their input ADIN with 12 bits or 8 bits. That is, in the case of 8-bit AD conversion, D 0 , D 1 , ... ..., D 7 are equal to 0, 0, ... ..., 0 for ADIN = 5 V, 1, 1, ... ..., 1 for ADIN = 3 V, respectively; and in the case of 12-bit AD conversion, D 0 , D 1 , ... ..., D 11 are equal to 0, 0, ... ..., 0 for ADIN = 5 V, 1, 1, ... ..., 1 for ADIN = 1 V, respectively. Also, the first AD convertor 51 and the second AD convertor 42 use the rising of ⊘ R as an AD clock. That is, the instantaneous level of the rising of ⊘ R in ADIN is AD-converted. A 12-bit input A or input B is selected by the data selector 53. For example, an input A is selected when a FINE signal sent from the control circuit 52 to the SEL terminal is "1" and an input B is selected when a Fine signal is "0". However, the lower 4 bits of an input B are forcibly grounded, the 8-bit output of the second AD convertor 42 is converted into the 12-bit signal, and the output of the second AD convertor 42 is connected to the upper 8 bits of the 12-bit input of the data selector 53. As shown in Fig. 6, the clock generating circuit 45 located in the control circuit 52 is provided with a 4-bit binary counter 602 for dividing an 80-MHz reference clock sent from the oscillator 44 in frequency, to which the 4-bit binary counter a data selector 603 is connected. When a FINE signal is "1", the output of the data selector 603 is Y' = T = Q' B and its frequency is 20 MHz. When a FINE signal is "0", the output of the data selector 603 is Y' = T = Q' A and its frequency is 40 MHz. And, the 4-bit binary counter 604 for dividing an output T from the data selector 603 in frequency is connected to the data selector 603, and a decoder 605 is connected to the binary counter 604. Furthermore, a data selector 606 is connected to the decoder 605. The output of the data selector 606 is Y 2 = ⊘ R = T 4 when a FINE signal is "1", and the output of the data selector 606 is Y 2 = ⊘ R = T 2 when a FINE signal is "0". Also, an invertor 611 for inverting its output T 7 is connected to the output terminal Y 7 of the decoder 605, and a frequency divider 607 for dividing its output into 1/K in frequency is connected to the invertor 611. When the frequency divider 607 has counted the rising of outputs from the invertor 611 4096 times, T R begins to rise with that rising and keeps 5 V until T R itself is reset to its inverted value. That is, this frequency divider 607 is a type of 1/4096 frequency divider. Incidentally, the number of elements N in the CCD sensor 40 is 4095 or less. A D flip-flop 608 capable of setting and resetting is connected to the output terminal Y 0 of the decoder 605, and the D flip-flop 608 is arranged to output control pulses ⊘ 1 and ⊘ 2 . A D flip-flop 609 capable of setting and resetting is connected to the output terminal Y 3 of the decoder 605, and the D flip-flop 609 is arranged to output a start pulse SH. The D flip-flop 609 is also arranged to be reset by an output of the invertor 612 for inverting the output terminal Y 5 of the decoder 605. Then, the operation of the present embodiment shown in Fig. 1 will be described along the timing charts of Figs. 7A to 8B. In the present embodiment, there are two operational modes and the operation in the high-resolution mode will be first described. In the high-resolution mode, the FINE signal becomes "1". A basic clock t 0 is oscillated by the oscillator 44 and divided in frequency by the 4-bit binary counter 602, whose output is sent to the data selector 603. As shown in Fig. 8A, the output Y' = T = Q' B is issued in a frequency of 20 MHz by the data selector 603. And, an output T from the data selector 603 is divided in frequency by the 4-bit binary counter 604, whose output is outputted to the decoder 605. Furthermore, an output from the binary counter 604 is decoded by the decoder 605 and outputs T 0 - T 7 are outputted. Then, an output T 0 from the decoder 605 is inputted to the T input of the D flip-flop 608, from which transfer pulses ⊘ 1 and ⊘ 2 are outputted as shown in Figs. 7A and 8A. Also, outputs T 2 and T 4 from the binary counter 604 are issued to the data selector 606. When a FINE signal is "1", Y 2 = ⊘ R = T 4 holds and a reset pulse ⊘ R is outputted from the data selector 606. On the other hand, an output T 3 from the decoder 605 is inputted to the T input of the D flip-flop 609 and an output T 5 from the decoder 605 is inverted by the invertor 612 and inputted to the D input of the D flip-flop 609 and a clock SH is outputted from the Q output of the D flip-flop 609 as shown in Fig. 8A, while an output T 6 of the decoder 604 is outputted as T CLAMP as shown in Figs. 7A and 8A. Furthermore, an output T 7 from the decoder 605 is inverted by the invertor 611 and sent to the frequency divider 607. When the rising of outputs from the invertor 611 is counted 4096 times by the frequency divider 607, T R begins to rise and keeps 5 V until T R itself is reset to the inverted value. As shown in Fig. 7A, an output CCD out from the CCD sensor 40 is clamped to 5 V by the capacitor C and analog switch. The clamped signal is amplified by the buffer 41 and outputted as an ADIN signal as shown in Fig. 7A. The ADIN signal is converted into digital signal by the AD convertors 51 and 42. Furthermore, digital signals D 0 , D 1 , ... ..., D 11 outputted from the first AD convertor 51 are inputted to the 12-bit input A of the data selector 53, while digital signals D 0 , D 1 , ... ..., D 7 outputted from the second AD convertor 42 are inputted to the 12-bit input B of the data selector 53. Then, in accordance with the FINE signal "1", the input A is selected by the data selector 53 and outputted to the control circuit 52. Next, the operation in the high-speed mode will be described. If the clock period is simply halved in Fig .7A, ⊘ R and CCD out changed as indicated with dashed lines in Fig. 7B, so that the CCD black level in CCD out cannot be stabilized. Thus by forwarding the position of ⊘ R as indicated with a solid line, the stabilized period is secured. In the high-speed mode, the FINE signal becomes "0". As shown in Fig. 7B, the output CCD out from the CCD sensor 40 is clamped to 5 V by the capacitor C and the analog switch. The clamped signal is amplified by the buffer 41 and outputted as an ADIN signal as shown in Fig. 7B. The ADIN signal is converted into digital signal by the AD convertors 51 and 42. Furthermore, digital signals D 0 , D 1 , ... ..., D 11 outputted from the first AD convertor 51 are inputted to the 12-bit input A of the data selector 53, while digital signals D 0 , D 1 , ... ..., D 7 outputted from the second AD convertor 42 are inputted to the 12-bit input B of the data selector 53. Then, in accordance with the FINE signal "0", the input B is selected by the data selector 53 and outputted to the control circuit 52. Incidentally, as clearly seen from the timing chart of Fig. 7B, the timing for AD conversion is the time when the ADIN signal has just been settled in the high-resolution mode of Fig. 7A. At that time, the ADIN signal has still been unstable in the high-speed mode of Fig. 7B, but can be converted without error because of a lower accuracy of the 8-bit input in comparison with the 12-bit input in the high-resolution mode. It is important for a reader to accurately derive the black level, because this black level is a standard level for all operations. As shown in Fig. 9, if both the CCD output CCD out and the manuscript are dark, the CCD black level rapidly reaches to a stable level even after ⊘ R is added to it, but it takes much time to achieve stability if the manuscript is bright. This is because the response speed of the output buffer inside the CCD is not fast in comparison with an ideal speed. Consequently, in order to add T CLAMP to the manuscript from a dark region to a bright region at a stable timing of the black level, the reset pulse ⊘ R indicated with a solid line in Fig. 7B should be used.

Claims: A reader having a high-resolution mode and a high speed mode, comprising a CCD sensor (40) for converting a received light into an electrical signal, a first and a second AD converter (51, 42) each for converting the output signal of said CCD sensor into a digital signal, respectively, selecting means (53) and control means (52), characterized in that the bit number of the output digital signal from said second AD converter (42) is less than that of said first AD converter (51), said selecting means (53) selects the output signal from said first AD converter (51) in said high-resolution mode, and selects the output signal from said second AD converter (42) in said high-speed mode, and said control means (52) controls each of the reading periods for said high-resolution mode and said high-speed mode and forwards the position of a reset pulse (Φ R ) for said CCD sensor in the reading period for said high-speed mode so as to stabilize the output signal level (CCD out ) of said CCD sensor (40). The reader according to claim 1, characterized in that the conversion period of said second AD converter (42) is shorter than that of said first AD converter (51). The reader according to claim 1 or 2, characterized in that the ratio of the conversion period in the reading period of said high-speed mode is less than that of said high-resolution mode. The reader according to any one of claims 1 to 3, characterized in that the reader further comprises a buffer (41) and an analog switch for clamping the output of said CCD sensor to a predetermined DC voltage (5V) supplied from a power source in accordance with a control signal (T CLAMP ) from said control means (52). The reader according to any one of claims 1 to 4 characterized in that said control means (52) includes an oscillator (44) for generating a base clock signal and a clock generating circuit (45) for generating a plurality of clock signals (SH, Φ 1 , Φ 2 , Φ 3 , T CLAMP ) by dividing the base clock signal in frequency. The reader according to any one of claims 1 to 5, characterized in that said first AD converter (51) converts an analog signal into a digital signal of 12 bits, and said second AD converter (42) converts an analog signal into a digital signal of 8 bits.

Inventors: NAGANO FUMIKAZU, NAGANO, FUMIKAZU
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1995
Main classification: H04N1
IPC codes: H04N1, H03M1