Clock phase adjustment circuit in a RAKE receiver for spread spectrum signals

Abstract: For a Rake Receiver in which the received signal is sampled at only one sample per chip, the signal is energy collected from several multipath components by the Rake fingers. If any multipath component is not perfectly aligned with the sampling time, several Rake fingers will be needed to collect its energy. If the number of Rake fingers available is limited then more efficient collection of energy is possible if fine timing correction is applied to the sampling so that optimum sampling is applied to the strongest multipath component. In this way only one Rake finger is required and the other Rake fingers may be dedicated to the remaining multipath components. The present invention uses two types of control methods, a Tau dither phase control circuit or a pilot jitter clock circuit. The control circuit generates control signals for the various Rake fingers and also controls a clock phase adjuster which in turn controls a sample and hold circuit which receives the analogue complex baseband input signal which is fed via a digital to analogue converter into a complex shift register, each stage of which is connected to each Rake finger and is selectable by each Rake finger.

Description: The present invention relates to apparatus for use in equipment providing a digital radio link using direct sequence spread spectrum between a fixed and a mobile radio unit. In patent publication GB 2 278 983 (corresponding to patent application number 9316489.5), there is described a comprehensive Rake Receiver in which a contiguous set of Rake fingers is not required. The savings in cost and complexity are maximised if the fewest number of Rake fingers are used. The sampling of a received signal is performed at only one sample per chip and multiple Rake fingers are used. The Rake fingers referred to above may be assigned to a single multipath component in order to acquire most of its energy when the component is sampled at a non optimum time. When the number of available Rake fingers is limited (eg n), these are assigned to the n strongest responses to the multipath components. If the strongest multipath component is non optimally sampled then several Rake fingers will need to be assigned to its responses in order to recover most of its power. In this case fewer Rake fingers remain available for assignment to the other multipath responses. If the timing of sampling can be held such that the strongest multipath component is always sampled optimally, then only one Rake finger will be needed for its reception. This makes available more of the other Rake fingers for combining the signal from the other multipath components, permitting improved overall performance. Conversely, for the same performance a smaller number of Rake fingers could be used. International patent application WO91/07036 discloses apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit including a Rake receiver having a number of Rake fingers. In the context of CDMA cellular mobile radio systems, the present invention is only of benefit on the downlink (base station to mobile unit direction). The reason for this is that the base station receiver must handle signals received from many mobile units, all coming over different propagation paths so that the delays associated with the strongest path for every signal will be different. Since all signals pass through a single analogue to digital converter it is not possible to control the timing of the sampling for the different received signals independently. For the mobile unit receiver, however, the signal is received from only one base station so that alignment is possible. The saving from this is most beneficial, because there are far more mobile unit receivers than base station receivers and because power consumption is critical. Accordingly, an aim of the present invention is to provide apparatus in which a timing loop is closed around a single Rake finger which is experiencing the strongest signal, which is sampled at only one sample per chip thereby rendering arbitrary the timing of other Rake fingers with respect to their multipath components. According to the present invention, there is provided apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit, said apparatus comprising:- a Rake receiver having a plurality of Rake fingers, each Rake finger having means for selectively receiving the contents of each stage of a shift register; said shift register being arranged to receive an analogue complex baseband signal via a sample and hold circuit and an analogue to digital converter wherein said sample and hold circuit receives a control signal from a clock phase adjuster circuit which is controlled by control means in dependence upon an output signal received from each Rake finger. An embodiment of the present invention will now be described with a reference to the accompanying drawings wherein: Figure 1 shows a block diagram of a single finger aligned Rake receiver, Figure 2 shows a block diagram of the controller shown in Figure 1, and Figure 3 shows a block diagram of an alternative controller as shown in Figure 1. Referring to Figure 1 there is shown a basic single finger aligned Rake finger comprising three Rake fingers 2, 4, 6. It will be appreciated that each Rake finger is identical and the description hereafter refers to the Rake finger 2 only. Each Rake finger comprises a selectable switch 8 the output of which is connected to an input of a pilot correlator 10 and to an input of a signal correlator 12. Each correlator generates an inphase output signal and a quadrature phase output signal. Each output from the pilot correlator 10 is connected to a filter 14, 16 respectively, the outputs of which are connected to first and second inputs of a multiplying circuit 18, 20 respectively and to an input of multiplying circuits 22, 24 respectively. The outputs of the signal correlator 12 are each connected to an input of a delay circuit 26, 28, the output of which is connected to a further input of a respective multiplying circuit 22, 24. The outputs from the multiplying circuits 18, 20 are connected to a summator 27, and the outputs of the multipliers 22, 24 are connected to a summator 30. The output summator 30 is connected via a controlled switch 32 to a further summator 34. The output of the summator circuit 27 is connected to an input of the control circuit 36. The output from the summator 30 and of the summators in the other Rake fingers are similarly connected to an input of the summator 34, the output of which generates the demodulated data. The outputs from the summators 27 in the other Rake fingers are also connected to the input of the control circuit 36. The output of the control circuit 36 is connected to an input of a clock phase adjuster circuit 38, the output of which controls a sample and hold circuit 40 which receives at an input thereof, an analogue baseband signal on input lead 42. The output of the sample and hold circuit is connected to an analogue to digital converter 44, the output of which is connected to a first stage of a complex shift register 46. Each stage of the complex shift register 46 is connected to a respective input of the selectable switch 8 in each Rake finger. The control circuit 36 provides a signal to control the clock phase of the sample and hold circuit 40 via the clock phase adjuster circuit 38 to obtain optimum sampling. The control can be performed in either a digital or an analogue fashion. The functionality of the control circuit 36 either implements a Tau dither loop (as familiar to those versed in the art) or a jittered pilot receiver as described in GB-A-2 292 053 (corresponding to patent application number 9415191.7). The remainder of the circuit operation is as described in GB-A-2 291 567 (corresponding to patent application number 9413268.5). Referring to Figure 2, the control function implemented by a Tau Dither loop will now be described. The control circuit comprises several integrators 50, 52, 54 which receive the output signals from the summators 27 in each Rake finger of Figure 1. These signals are also connected to a plurality of control switches 56, 58, 60. These switches are controlled by a select largest circuit 62 which receives the outputs from the integrator circuits 50, 52 and 54. The output of each switch 56, 58, 60 is connected to an input of an inverter 64 and to an input of a switching circuit 66 the function of which is to short circuit the inverter 64. The output of the subtractor circuit 64 is connected to a further input of the switch 66, the output of which is connected to an integrator filter 68. The output of the integrator filter 68 is connected to the input of a summator 70. The switch 66 and the further switch 72 are controlled by a dither clock generator 74. The switch 72 is arranged to switch a positive or negative offset to a further input of the summator 70, the output of which is used to control a clock phase and is applied to the clock phase adjuster 38 in Figure 1. The integrators 50, 52, 54 average the signal power over a measured interval (several milliseconds) and the largest is selected and routed by the switches 56, 58, 60 to an inverter 64 and switch 66 which alternatively adds and subtracts the current measurement into the integrator 68. Synchronously with this operation, a Dither signal is generated and added to the output of the control signal. Operation is thus that the Dither signal causes the pilot power for the strongest Rake to be measured when the sample phase is early and when it is late. Alternate addition and subtraction of these into the integrator 68 is equivalent to feeding the difference of early and late measurements into the loop filter. When the timing is correct, the pilot signal in the early case will be the same is in the late case. Referring to Figure 3, a pilot jitter solution is shown. In Figure 3 like elements as in Figure 2 have been given the same reference numeral and operate in the same manner. It will be noted that the difference is the provision of pilot jitter clock 76 which is used directly to control the switch 66. There is no need for a summator 70 as shown in Figure 2 or the additional switch 72 for providing a positive and negative offset. As mentioned above, there is no need for a Dither circuit since this is implemented on the pilot in the transmitter. The pilot jitter clock is synchronised to the local pilot code, dividing between the early and late phases of the pilot jitter. It will readily be appreciated by those skilled in the art that various implementations are possible within the scope of the present invention, as defined by the claims.

Claims: Apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit, said apparatus comprising a Rake receiver having a plurality of Rake fingers (2, 4, 6), characterised by each Rake finger (2, 4, 6) having means (8) for selectively receiving the contents of each stage of a shift register (46), said shift register (46) being arranged to receive an analogue complex baseband signal, via a sample and hold circuit (40) and an analogue to digital converter (44), wherein said sample and hold circuit (40) receives a control signal from a clock phase adjuster circuit (38) which is controlled by control means (36) in dependence upon an output signal received from each Rake finger (2, 4, 6). Apparatus as claimed in claim 1, wherein each Rake finger (2, 4, 6) includes a pilot correlator (10) from which said output signal is generated. Apparatus as claimed in claim 1 or claim 2, wherein the control means (36) is a Tau dither phase control circuit (Figure 2). Apparatus as claimed in claim 1 or claim 2, wherein the control means (36) is a pilot jitter phase control circuit (Figure 3). Apparatus as claimed in claim 3, wherein the Tau dither control circuit (Figure 2) includes integration means (50, 52, 54) for averaging the signal power over an interval of time on each input line to the control means (36), means for selecting the largest signal (56, 58, 60), means (64, 66) for alternately adding and subtracting said selected signal into a further integrator (68), and means (74) for adding a dither signal to the output signal of said further integrator. Apparatus as claimed in claim 4, wherein the pilot jitter phase control circuit (Figure 3) includes integration means (50, 52, 54) for averaging the signal power over an interval of time on each input line to the control means (36), means for selecting the largest signal (56, 58, 60), and means (64, 66) for alternately adding and subtracting said selected signal into a further integrator (68) under the control of a pilot jitter clock signal.

Inventors: HULBERT ANTHONY PETER, KRUMPE ALFRED MICHAEL, HULBERT, ANTHONY PETER, KRUMPE, ALFRED MICHAEL
Applicants: ROKE MANOR RESEARCH, ROKE MANOR RESEARCH LIMITED
Application year: 1995
Main classification: H04B1
IPC codes: H04B1