FAULT TOLERANT DIGITAL TRANSMISSION SYSTEM

Abstract: In a transmission system a transmitter (12) is coupled to a receiver (13) via a transmission line comprising two wires (1, 2). The transmitter (12) generates on said wires two voltages with respect to a reference voltage being opposite in phase. To enable the transmission system to operate in case of a short circuit between the wires (1, 2), said two voltages are generated by sources having different short circuit currents.

Description: Fault tolerant digital transmission system The invention is related to a digital transmission system comprising a transmitter having a first source for generating in response to digital symbols a first voltage with respect to a reference voltage on a first wire of a transmission line, a second source for generating a second voltage with respect to said reference voltage on a second wire of the transmission line, said second voltage having an opposite phase with respect to the first voltage, the transmission system further comprises at least one receiver coupled to said trans¬ mission line, having a detector for deriving digital symbols from the voltage difference between the first and second wire. The invention is further related to a transmitter, a receiver and a transceiver for such a transmission system. A transmission system according to the preamble is known from the book "Digital Integrated Electronics" by H. Taub and D. Schilling, published by McGraw-Hill, 1977, ISBN 0-07-085788-1. Transmission systems according to the preamble can be used in local area networks, in several bus systems, and the local loop area of a digital telephone system. In the known transmission system, a first end of a transmission line consisting of two wires is connected to a transmitter. A first source is connected to a first wire of the transmission line, and a second source is connected to a second wire of the transmission line. The signals generated by the first and second source are opposite in phase. The receiver being connected to a second end of the transmission line is provided with a detector connected to the first wire and the second wire of the transmission line for deriving digital symbols from the voltage difference between the first wire and the second wire. Because the first and the second source generate voltages having opposite phases the information to be transmitted can be derived from the voltage difference between the two wires. This reduces the vulnerability of the transmission system to electromagnetic interference, resulting in an increase of electromagnetic compatibility (EMC) properties. In the known transmission system no transmission is possible if a short circuit arises between the first wire and the second wire, so the complete transmission system will fail. 2 The object of the invention is to provide a transmission system according to the preamble in which transmission is still possible if a short circuit arises between the first and the second wire. Therefor the transmission is characterised in that the first source and the second source have a differing short circuit current and in that the receiver comprises at least one additional detector for deriving digital symbols from the voltage between the first wire and the reference voltage. By making the short circuit currents of the two sources different, a voltage representing the symbols to be transmitted will be still available between the wires and the reference voltage. By using an additional detector for deriving digital symbols from the voltage difference between the wires and the reference voltage, communication remains possible. It is required that the reference voltage (or a voltage derived thereof) is available at the transmitter and the receiver. This can e.g. be obtained by using a shielded twisted pair cable, in which the shield is used for transferring the reference voltage. In local area networks to be used e.g. in cars the metal of the car (GROUND) can be used for transferring the reference voltage. An embodiment of the invention is characterised in that the receiver com¬ prises a further additional detector for deriving digital symbols from the voltage between the first wire and the reference voltage. By using a further additional detector it is possible to maintain transmission if one of the wires is interrupted. In this way a reliable system is obtained which remains functional under several faults of the transmission line. A further embodiment of the invention is characterised in that the receiver comprises means for deriving from the symbols derived by the detector and the additional detector, a signal indicating a short circuit between the first and second wire.. By deriving a signal indicating a short circuit, a message can be displayed indicating that servicing is required. It is also conceivable that the signal indicating a short circuit is transmitted to the transmitted to request a decrease in transmission rate, in order to cope with the increased vulnerability with respect to interfering signals. The present invention will now be explained with reference to the drawings. Herein shows: Fig. 1 , a transmission system in which the invention can be used; Fig. 2, an embodiment of a transceiver for use in the transmission according to the invention; Fig. 3, an alternative embodiment of the transmitter 12 of the transceiver according to Fig. 2. In the transmission system according to Fig. 1 the transmission line is constituted by a twisted pair with wires 1 and 2. Each of the transceivers 4, 6, 8, and 10 is provided with two terminals being connected to the wire 1 and to the wire 2. A third terminal of each of the transceivers 4, 6, 8, and 10 is connected to the reference voltage, here indicated as ground terminal. In the transmission system according to Fig. 1 only one transceiver can be in the transmitting mode. One ore more of the other transceivers are in the receiving mode. The access of the transmitters to the transmission line can be controlled by numerous well known multiple access methods, like random access such as (slotted) ALOHA, time division multiple access or bus arbitration schemes using a bus arbiter. The voltages with respect to the reference voltage put on the first wire 1 and the second wire 2 of the transmission are opposite in phase. In the transceivers in the receiving mode the symbols to be received are derived from the voltage between the wires 1 and 2. This results in a decreased vulnerability to interference by common mode voltages on both wires 1 and 2. In the transceiver according to Fig. 2, the digital signal to be transmitted is applied to an input of a drive circuit 20. A first output of a drive circuit 20 is connected to the base of a PNP transistor 16. The emitter of the PNP transistor 16 is connected to a positive supply voltage. The collector of the PNP transistor is connected to the anode of a diode 18. The cathode of the diode 18 is connected to the first input/output terminal of the transceiver, and to a first terminal of a resistor 26. A second terminal of the resistor 26 is connected to ground. The first source is constituted by the PNP transistor 16, the diode 18, the drive circuit 20 and the resistor 26. A second output of a drive circuit 20 is connected to the base of an NPN transistor 24. The emitter of the NPN transistor 24 is connected to ground. The collector of the NPN transistor 24 is connected to the cathode of a diode 22. The anode of the diode 22 is connected to the second input/output terminal of the transceiver, and to a first terminal of a resistor 14. A second terminal of the resistor 14 is connected to the positive supply voltage ground. The second source is constituted by the NPN transistor 24, the diode 22, the drive circuit 20 and the resistor 14. The first terminal is also connected to a first input of a receiver 13. Said first input is connected to an input of a low-pass filter 28 and a first input of a low-pass filter 30. The second terminal is also connected to a second input of the receiver 13. Said second input is connected to an input of a low-pass filter 32 and a second input of the low-pass filter 30. Two outputs of the low-pass filter 30 are connected to two corresponding inputs of the first detector being here a comparator 36. An output of the low-pass filter 28 is connected to a first input of an additional detector, being here a comparator 34. A second input of the comparator 34 is connected to a voltage V r . An output of the low-pass filter 32 is connected to a first input of a further additional detector, being here a comparator 38. A second input of the comparator 38 is connected to the voltage V r . The outputs of the comparators 34, 36 and 38 are connected to a processing circuit 40. The processing circuit 40 determines the values of the output symbols, and generates a first fault signal in the presence of a short circuit between die first and second wire, and generates a second fault signal in the presence of an interruption of one of the wires 1 or 2. The drive circuit 20 in the transceiver according to Fig. 2, generates drive signals for the NPN transistor 24 and the PNP transistor 16. The drive circuit 20 is arranged in such a way that the short circuit current (maximum current) that can be delivered by the NPN transistor 24 is different from the short circuit current (maximum current) that can be delivered by the PNP transistor 16. In practice a difference by a factor of two can be chosen. A suitable choice is a short circuit current of 50 mA for the PNP transistor 16 and a short circuit current of 100 mA for the NPN transistor 24. The values of the resistors may be the same, to obtain a symmetrical output voltage if the wires 1 and 2 are not short circuited. If the transmission system operates correctly, the NPN transistor 24 and the PNP transistor 16 are switched off if a digital symbol wim a logical value "0" is applied to the input of the drive circuit 20. Then the voltage on the wire 1 is approximately equal to the ground level, and the voltage on the wire 2 is approximately equal to the positive supply voltage. If a digital symbol with a logical value " 1 " is applied at the input of the drive circuit 20, die NPN transistor 24 and the PNP transistor 16 are conducting. In normal circumstances the maximum current in the NPN transistor 24 and die PNP transistor 16 will be limited by me external circuitry, resulting in that the NPN transistor 24 and d e PNP transistor 14 will be in the "bottomed" state. Then die voltage on die wire 1 will be equal to the positive supply voltage, and die voltage on die wire 2 will be equal to die ground level. In this way two signals having an opposite phase are available on the wires 1 and 2. The diode 22 is present to prevent reverse conduction of die NPN transistor 24 if die voltage at the wire 2 is forced below ground level due to external circumstances. If the transmitter is realised as integrated circuit such reverse conduction of -he NPN transistor 24 can cause substrate currents, which can cause erroneous operation of the complete integrated circuit. The diode 18 is present to prevent reverse conduction of die PNP transistor 16 if the voltage at the wire 1 is forced above die positive supply voltage. The signal generated in this way can be easily detected by the receiver 13 of anodier transceiver. The filter 30 eliminates interference and noise in me frequency range above the cut off frequency of the low-pass filter 30. The detector 30 determines die value of the received symbols by determining die sign of the signal between its inputs. If the wires 1 and 2 are short circuited die voltage on the wires 1 and 2 will be equal to half the supply voltage when the NPN transistor 24 and die PNP transistor 16 are switched off in die case the resistors 14 and 26 are equal. If die NPN transistor 24 and die PNP transistor 16 are switched on, half the difference between the maximum current in the NPN transistor 24 and die PNP transistor 16 will be added to die current in the resistor 14 and will be subtracted from die current in the resistor 26. This results in a decrease of die voltage on the wires 1 and 2. This decrease can be detected by the detectors 34 and 38 enabling the communication to continue during presence of a short circuit between die wires 1 and 2. If a transmission code widi error detection capabilities is used, the processing circuit can determine whedier d e symbols detected by the detector 36 are correct. If d ese symbols are correct no furdier action of die processing circuit is required. If d ese symbols are in error, die processing circuits checks whedier die symbols detected by die detector 34 and/or 38 are correct. If die symbols detected by die detectors 34 and 38 are bodi correct, diere must be a short circuit present between the first and second wire, and the first fault signal is activated. If die symbols detected by die detector 34 or 38 is not correct, an interruption of die corresponding wire is present, and die second fault signal is activated. In the transmitter according to Fig. 3, the digital signal to be transmitted is applied to an input of a drive circuit 20. A first output of a drive circuit 20 is connected to the base of a PNP transistor 16. The emitter of the PNP transistor 16 is connected to a positive supply voltage. The collector of the PNP transistor is connected to d e anode of a diode 18. The cathode of die diode 18 is connected to die first output terminal of die transmitter, and to a first terminal of a current source 44. A second terminal of me current source 44 is connected to ground. The first source is constituted by die PNP transistor 16, the diode 18, die drive circuit 20 and the current source 44. A second output of a drive circuit 20 is connected to the base of an NPN transistor 24. The emitter of the NPN transistor 24 is connected to ground. The collector of the NPN transistor 24 is connected to die cadiode of a diode 22. The anode of die diode 22 is connected to die second output terminal of me transmitter 12, and to a first terminal of a current source 42. A second terminal of die current source 42 is connected to die positive supply voltage. The second source is constituted by die NPN transistor 24, die diode 22, die drive circuit 20 and die current source 42. In die transmitter 12 according to Fig. 3, die drive circuit 20 generates drive signals for die NPN transistor 24 and die PNP transistor 16. The drive circuit 20 is arranged in such a way that die short circuit current (maximum current) mat can be delivered by die NPN transistor 24 is different from the short circuit current (maximum current) that can be delivered by die PNP transistor 16. In practice a difference by a factor of two can be chosen. A suitable choice is a short circuit current of 50 mA for the PNP transistor 16 and a short circuit current of 100 mA for the NPN transistor 24. The currents delivered by the current sources 42 and 44 is also different. A suitable choice is 2 mA for the current source 42 and 1mA for me current source 44. If the transmission system operates correctly, the NPN transistor 24 and d e PNP transistor 16 are switched off if a digital symbol widi a logical value "0" is applied to die input of the drive circuit 20. Then the voltage on the first output terminal is approxi¬ mately equal to ground level, and die voltage on the second output terminal of the transmitter 12 is approximately equal to positive supply voltage. If a digital symbol with a logical value " 1 " is applied at die input of die drive circuit 20, the NPN transistor 24 and die PNP transistor 16 are conducting. In normal circumstances the maximum current in the NPN transistor 24 and the PNP transistor 16 will be limited by me external circuitry, resulting in that the NPN transistor 24 and d e PNP transistor 14 will be in die "bottomed" state. Then the voltage on the first output terminal of the transmitter will be equal to die positive supply voltage, and die voltage on the second output of the transmitter 12 will be equal to the ground level. In diis way two signals having an opposite phase are available on the first and second terminal of the transmitter 12. If the output terminals of the transmitter 12 are short circuited the voltage on the said terminals will be equal to the positive supply voltage when the NPN transistor 24 and die PNP transistor 16 are switched off because die current delivered to the output terminals by current source 42 exceeds die current drawn by the current source 44 from said output terminals. If die NPN transistor 24 and die PNP transistor 16 are switched on, the voltage on the output terminals will be approximately equal to ground level, because the maximum collector current of the NPN transistor 24 exceeds die maximum collector current of me PNP transistor 16.

Claims: CLAIMS 1. Digital transmission system comprising a transmitter having a first source for generating in response to digital symbols a first voltage with respect to a reference voltage on a first wire of a transmission line, a second source for generating a second voltage widi respect to said reference voltage on a second wire of die transmission line, said second voltage having an opposite phase with respect to die first voltage, the transmission system further comprises at least one receiver coupled to said transmission line, having a detector for deriving digital symbols from the voltage difference between the first and second wire, characterised in diat die first source and die second source have a differing short circuit current and in diat die receiver comprises at least one additional detector for deriving digital symbols from the voltage between the first wire and the reference voltage. 2. Digital transmission system according to claim 1, characterised in d at die receiver comprises a fur er additional detector for deriving digital symbols from the voltage between the first wire and die reference voltage. 3. Transmission system according to claim 1 characterised in that die receiver comprises means for deriving from me symbols derived by me detector and die additional detector, a signal indicating a short circuit between die first and second wire. 4. Transmission system according to claim 2, characterised in that the receiver comprises means for deriving from me symbols derived by me detector, die additional detector and die further additional detector a signal indicating an interruption of die first or second wire. 5. Transmitter comprising a first source for generating in response to digital symbols a first voltage widi respect to a reference voltage on a first terminal , a second source for generating a second voltage with respect to said reference voltage on a second terminal, said second voltage having an opposite phase with respect to the first voltage, characterised in diat die first source and die second source have a differing short circuit current. 6. Receiver for a transmission system, having a detector for deriving digital symbols from die voltage difference between two terminals, characterised in that the receiver comprises at least an additional detector for deriving digital symbols from the voltage between the first terminal and a reference voltage, and in diat the receiver comprises means 9 for deriving from me symbols derived by the detector and die additional detector a signal indicating a short circuit between die first terminal and die second terminal. 7. Receiver according to claim 6, characterised in that the receiver comprises a further additional detector for deriving digital symbols from me voltage between the second terminal and die reference voltage, and in diat receiver comprises means for deriving from the symbols derived by die detector, me additional detector and die fur er additional detector a signal indicating die absence of a signal at die first or second wire. 8. Transceiver having a first source for generating in response to digital symbols a first voltage widi respect to a reference voltage on a first terminal , a second source for generating a second voltage widi respect to said reference voltage on a second terminal, said second voltage having an opposite phase widi respect to the first voltage, die transceiver furdier comprises a detector for deriving digital symbols from d e voltage difference between die first and second terminal, characterised in that die first source and die second source have a differing short circuit current and in diat die transceiver comprises at least one additional detector for deriving digital symbols from me voltage between the first wire and d e reference voltage. 9. Transceiver according to claim 8, characterised in that the transceiver comprises a furmer additional detector for deriving digital symbols from the voltage between die first terminal and d e reference voltage. 10. Transmission system according to claim 1 characterised in that die transceiver comprises means for deriving from die symbols derived by the detector and die additional detector, a signal indicating a short circuit between die first and second terminal.

Inventors: BOEZEN HENDRIK, EISELE HARALD, BOEZEN, HENDRIK, EISELE, HARALD
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS PATENTVERWALTUNG, PHILIPS ELECTRONICS N.V., PHILIPS PATENTVERWALTUNG GMBH
Application year: 1995
Main classification: H04L25
IPC codes: H03K19, H04L25