Circuit and method for generating a clock signal

Abstract: The invention provides for a clock generator method and circuit (10) which produces a clock signal which may have an adjustable steady state duty cycle and which has the same frequency as a crystal frequency. The clock generator circuit includes a drive circuit (16) coupled to a crystal (12) which converts the first signal to a clock signal, and a duty cycle control circuit (18) which generates a feedback signal to cause the duty cycle to automatically change to the steady state duty cycle. The clock generator circuit (10) may also include an output pad (22) for allowing a measuring instrument to determine the duty cycle.

Description: The present invention relates to a circuit and method for generating a clock signal. Digital systems typically require one or more clock signals which synchronize activities performed by different functional parts within the systems. It is desirable in such systems that the clock signals have fifty percent duty cycles. The term "duty cycle" is well known to mean the ratio of pulse width to total cycle time. Thus, for a fifty percent duty cycle clock signal, the clock signal is high for half the cycle time. Known methods of generating a clock signal having a fifty percent duty cycle involve generating a signal having a frequency equal to twice the desired frequency and dividing the signal by two to remove any duty cycle distortion. These methods suffer from high cost. For example, a 100 MHz crystal is more expensive than a 50 MHz crystal. These systems also consume high amounts of power, produce high amounts of radio frequency (RF) radiation, and degrade system performance. Further, they produce clock signals whose duty cycles are difficult to measure during production testing. WO-A-84 02621 discloses a circuit for adjusting the duty ratio of a CLOCK-IN signal in a feedback loop comprising an operational amplifier and an adjustable CMOS drive stage in which two complementary MOSFETs are arranged to receive the signal received at the clock-in terminal and which have their drain terminals coupled together. The drive stage provides an output clock signal which is connected to a clock output terminal. Therefore, the present invention seeks to provide a circuit and method for generating a clock signal which circuits and methods have advantages over and above known circuits and methods. A clock signal generator circuit having a crystal for generating a first signal having a frequency, a drive circuit coupled to the crystal for converting the first signal to a clock signal (CLOCK_OUT), receiving a feedback signal, and varying a duty cycle of the clock signal (CLOCK_OUT) in response to the feedback signal, and a duty cycle control circuit coupled to the drive circuit means for receiving the clock signal (CLOCK_OUT) and comprising a differential amplifier (DA1) for providing the feedback signal to cause the duty cycle of the clock signal (CLOCK_OUT) to automatically change to a steady state duty cycle, characterized in that the duty cycle control circuit comprises a voltage divider including first and second resistors connected in series which provide an output voltage at a connection point therebetween and first and second switches which alternately provide voltage from a voltage source to the first resistor when the clock signal (CLOCK_OUT) is in a first state and provide voltage from the second resistor to ground when the clock signal (CLOCK_OUT) is in a second stage that is different from the first state, whereby said differential amplifier receives the output voltage from the voltage divider and generates the feedback signal used to cause the duty cycle of the clock signal (CLOCK_OUT) to automatically change to the steady state duty cycle. In accordance with another aspect of the present invention there is provided a control circuit for a clock generator circuit, which converts a first signal from a crystal within said clock generator circuit into a clock signal having the same frequency as said first signal, and which has a duty cycle and a steady state duty cycle, characterised in that the steady state duty cycle is adjustable to a new steady state duty cycle. In accordance with yet another aspect of the present invention there is provided a control circuit for a clock generator circuit, which converts a first signal from a crystal within said clock generator circuit into a clock signal having the same frequency as said first signal, and which has a duty cycle and a steady state duty cycle, characterised by an output pad for allowing a measuring instrument to determine the duty cycle. The invention further provides for a system within a computer and having a circuit as defined above. The invention is advantageous in providing a clock generator circuit having a crystal which generates a first signal having a frequency, and a control circuit coupled to the crystal converts the first signal into a clock signal which has the same frequency as the first signal and which has a duty cycle and a steady state duty cycle. Thus, it is a particular feature of one embodiment of the present invention that the crystal frequency and the clock frequency are the same, i.e. no frequency divider is required. Preferably, the control circuit includes a drive circuit coupled to the crystal which converts the first signal to a clock signal and which has a clock signal output and a feedback signal input, and a duty cycle control circuit, which is coupled between the clock signal output and the feedback signal input, and which generates the feedback signal to cause the duty cycle to automatically change to the steady state duty cycle. Thus, it is a further advantageous feature of the present invention that variations from a steady state duty cycle are automatically corrected. The clock generator circuit of the present invention may also include a circuit element which changes the steady state duty cycle to a new steady state duty cycle. The steady state duty cycle may be changed without changing the circuit. The clock generator circuit may also include an output pad for allowing a measuring instrument to determine the duty cycle. Advantageously the present invention may provide a circuit and method for generating a clock signal which automatically adjusts the duty cycle to a steady state duty cycle. Further, the present invention may also provide for a circuit and method for generating a clock signal in which the steady state duty cycle is adjustable without modification to the circuit. It is another advantage of the present invention that a circuit and method for generating a clock signal can be provided for measurement of the duty cycle. The invention is described further hereinafter, by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a circuit diagram of one embodiment of the present invention; Fig. 2 is a waveform diagram illustrating the operation of a circuit embodying the present invention; and Fig. 3 is a block diagram of a system incorporating a circuit embodying the present invention. Referring now to Fig. 1, a clock signal generator 10 is illustrated and which includes a crystal 12 and a control circuit 14. Crystal 12 produces a signal CLOCK_IN to control circuit 14. Signal CLOCK_IN is substantially constant in frequency. Control circuit 14 includes a driver circuit 16 and a duty cycle control circuit 18. Driver circuit 16 amplifies signal CLOCK_IN, converts signal CLOCK_IN to signal CLOCK_OUT, and adjusts the duty cycle of signal CLOCK_OUT in response to control signals from duty cycle control circuit 18. Driver circuit 16 includes field effect transistors (FETs) MP1, MP2, MN1, and MN2, which are connected in series between VDD and ground. FETs MP1 and MP2 are p-channel FETs. FETs MN1 and MN2 are n-channel FETs. The gates of FETs MP2 and MN1 are also connected with each other and with an input terminal providing signal CLOCK_IN. A centre tap between FETs MP2 and MN1 provides output clock signal CLOCK_OUT. The gates of FETs MP1 and MN2 are connected together and to a bias voltage VB from duty cycle control circuit 18. Duty cycle control circuit 18 monitors the voltage VC of signal CLOCK_OUT at the connection of FETs MN1 and MP2 and produces bias voltage VB at the gates of FETs MP1 and MN2 to control the duty cycle of signal CLOCK_OUT. With reference to Fig. 2, the following will be appreciated about the relationship between bias voltage VB and voltage VDD for a fifty percent duty cycle: 1. When bias voltage VB is half of voltage VDD, the charge current through FETs MP1 and MP2 is the same as the discharge current through FETs MN1 and MN2. The rise and fall times of signal CLOCK_OUT are the same and a fifty percent duty cycle results (waveform (a)). 2. When bias voltage Vb is larger than half of voltage Vdd, the charge current is smaller than the discharge current. The rise time is greater than the fall time and a less than fifty percent duty cycle results (waveform (b)). 3. When bias voltage Vb is smaller than half of voltage Vdd, the charge current is larger than the discharge current. The rise time is less than the fall time and a greater than fifty percent duty cycle results (waveform (c)). Referring back to Fig. 1, duty cycle control circuit 18 includes a differential amplifier DA1, and resistors R1-R4, FETs MN3, MP3, MN4, and MP4, and capacitors C1 and C2. Differential amplifier DA1 has a gain G. Resistors R1 and R2, FETs MN3 and MP3, and capacitor C2 form a first adjustment circuit which is connected between ground and a first input of amplifier DA1. Resistors R1 and R2, and FETs MN3 and MP3 are connected in series between voltage Vdd and ground. A tap point between resistors R1 and R2 provides voltage V1 to amplifier DA1. The gate of FET MP3 is connected to ground. The gate of MN3 is connected to voltage VDD. Capacitor C1 is a decoupling capacitor which filters out any noise from voltage VDD and ground and reduces any overshoot in feedback response. Resistors R3 and R4, FETs MN4 and MP4, and capacitor C1 form a second adjustment circuit which is connected between the output clock terminal of driver circuit 16 and a second input of amplifier DA1. Resistors R3 and R4, and FETs MN4 and MP4 are connected in series between voltage VDD and ground. A tap point between resistors R3 and R4 provides voltage V2 to amplifier DA1. The gates of FETs MP4 and MN4 are connected together to the output clock terminal of driver circuit 16. Capacitor C2 is a decoupling capacitor which filters out any noise from voltage VDD and ground and reduces any overshoot in feedback response. Bias voltage VB is determined by the input voltages of differential amplifier DA1: VB = VDD / 2 + G(V1 - V2) If the resistances of FETs MP3 and MN3 are much smaller than resistors R1 and R2, and the resistances of FETs MP4 and MN4 are much smaller than resistors R3 and R4, then voltages V1 and V2 are determined by the following equations: V1 = VDD • R2 / (R1 + R2), V2 = VDD • R4 / (R3 + R4). For a fifty percent duty cycle, resistor R1 equals resistor R2 and resistor R3 equals resistor R4. Thus, V1 = V2 = VDD / 2 The amounts of charge being delivered from voltage VDD to voltage V2 and from voltage V2 to ground during each clock cycle are: Q1 = [(VDD - V2) / R3] • T • (1 - D), Q2 = [(V2 - 0) / R4] • T • D , where T is the clock cycle time and D is the duty cycle of signal CLOCK_OUT. Charge Q1 equals charge Q2 under steady state conditions. Thus, V2 = (1 - D) • VDD. Thus, voltage V2 is directly proportional to (1-D) of signal CLOCK_OUT. Since V1=V2=VDD/2 for R1=R2 and R3=R4, the duty cycle D must equal fifty percent. Advantageously, duty cycle control circuit 18 is capable of generating a fifty percent duty cycle without using an expensive crystal having a frequency of twice the clock frequency in combination with a divide-by-two circuit. It is a feature of the present invention that duty cycle control circuit 18 seeks a steady state duty cycle D. If the instantaneous duty cycle were larger than D, voltage V2 would be smaller than V1. Consequently, bias voltage VB would be larger than D•Vdd, which, in turn, would reduce the duty cycle towards D. It is another feature of the present invention that duty cycle control circuit 18 may also be used to adjust the steady state duty cycle D to any number other than fifty percent. Steady state duty cycle D may be adjusted by adjusting resistors R1-R4 as follows: R3 = R4 and R2 = (1 - D) (R1 + R2). If the desired duty cycle D is very much larger or smaller than fifty percent, several adjustment circuits may be cascaded to achieve the desired duty cycle D without suffering from a very slow rise or fall time. Finally, it is another feature of the present invention that duty cycle control circuit 18 provides an easy and cost-effective way to determine the duty cycle D of signal CLOCK_OUT. Since voltage V2 is directly proportional to (1-D) and voltage VDD is known, duty cycle D is determined by measuring voltage V2 at bonding pad 22. Referring to Fig. 3, it can be seen that control circuit 14 is suited for use within any system 30 within a computer. System 30 also includes a logic element 32 which employs signal CLOCK_OUT.

Claims: A clock signal generator circuit (10) having a crystal (12) for generating a first signal, having a frequency, a drive circuit (16) coupled to the crystal (12) for converting the first signal to a clock signal (CLOCK_OUT), receiving a feedback signal, and varying a duty cycle of the clock signal (CLOCK_OUT) in response to the feedback signal, and a duty cycle control circuit (18) coupled to the drive circuit means (16) for receiving the clock signal (CLOCK_OUT) and comprising a differential amplifier (DA1) for providing the feedback signal to cause the duty cycle of the clock signal (CLOCK_OUT) to automatically change to a steady state duty cycle, characterized in that the duty cycle control circuit (18) comprises a voltage divider including first (R3) and second (R4) resistors connected in series which provide an output voltage at a connection point therebetween and first (MP4) and second (MP3) switches which alternately provide voltage from a voltage source to the first resistor (R3) when the clock signal (CLOCK_OUT) is in a first state and provide voltage from the second resistor (R4) to ground when the clock signal (CLOCK_OUT) is in a second state that is different from the first state, whereby said differential amplifier receives the output voltage from the voltage divider and generates the feedback signal used to cause the duty cycle of the clock signal (CLOCK_OUT) to automatically change to the steady state duty cycle. A circuit (10) as recited in Claim 1, wherein the steady state duty cycle is adjustable to a new steady state duty cycle. A circuit (10) as recited in Claim 1 or 2, wherein said steady state duty cycle is fifty percent. A circuit (10) as recited in any one of the preceding claims, wherein the clock signal (CLOCK_OUT) has the same frequency as the first signal. A circuit (10) as recited in any one of the preceding claims, wherein said duty cycle control circuit (18) includes an output pad (22) for allowing a measuring instrument to determine the duty cycle of said circuit (10). A circuit (10) as recited in any one of the preceding claims, wherein said duty cycle control circuit (18) further comprises a capacitor coupled between the connection point between the first and the second resistors and the ground for removing noise from the output voltage and reducing feedback overshoot in the output voltage. A circuit (10) as recited in any one of the preceding claims, wherein the differential amplifier having first and second inputs receiving said output voltage and a reference voltage, respectively. A circuit (10) as recited in Claim 7, wherein the duty cycle control circuit (18) further comprises a reference voltage generating means including third and fourth resistors connected in series between the voltage source and the ground which produce the reference voltage at a connection point between the third and fourth resistors by performing a voltage dividing process. A circuit (10) as recited in Claim 8, wherein the reference voltage generating means further includes a capacitor coupled between the connection point between the third and fourth resistors and the ground for removing noise from the reference voltage and reducing feedback overshoot in the reference voltage.

Inventors: CHEN DAO-LONG, CHEN, DAO-LONG
Applicants: HYUNDAI ELECTRONICS AMERICA
Application year: 1995
Main classification: H03K3
IPC codes: H03K3, H03K19, H03K5