MOS CIRCUIT WITH DYNAMICALLY REDUCED THRESHOLD VOLTAGE, AS FOR USE IN AN OUTPUT BUFFER OF A HEARING AID AMPLIFIER

Abstract: A buffer circuit, such as for use with a low voltage hearing aid, is disclosed. The hearing aid comprises a microphone, a receiver and an amplifier. The amplifier is disposed between the microphone and the receiver. The buffer circuit has a MOS device including a well terminal and a gate terminal equipotentially coupled together to reduce the effective threshold voltage of the MOS device, thereby reducing the gate-to-source voltage of the MOS device. This permits a greater linear output signal range for the amplifier.

Description: MOS CIRCUIT WITH DYNAMICALLY REDUCED THRESHOLD VOLTAGE, AS FOR USE IN AN OUTPUT BUFFER OF A HEARING AID AMPLIFIER D E S C R I P T I O N Technical Field The present invention relates to a circuit for dynamically adjusting the threshold voltage of a MOS device, as for use in an output buffer of a hearing aid amplifier. Background Prior Art In certain signal processing applications, such as an amplifier, a buffer circuit is required to reduce the output impedance of the amplifier to more closely match the input impedance of the device to which the amplifier is connected. For example in a hearing aid, an amplifier is coupled between a microphone and a receiver. The microphone receives sound energy and converts the received sound energy to a corresponding electrical signal. The amplifier then amplifies the received electrical signal and the receiver converts the amplified electrical signal to amplified sound energy. In many such systems, the amplifier has a relatively high output impedance, and an output buffer is uti¬ lized to match the input impedance of the receiver. In fact, the closed loop gain of the amplifier is proportional to the output impedance of the amplifier. Thus the greater the closed loop gain of the ampli- fier, the greater the likely mismatch between the output impedance of the amplifier and the input imped¬ ance of the receiver. In many circuits, conventional buffer circuits are satisfactory. However, many circuits operate at extremely low voltages. For example, circuits such as for hearings aids are designed for operation with a 1.1 volt battery. Thus V GS for the CMOS device in the buffer effectively limits the linear output range of the amplifier. For- CMOS devices, the surface potential in the channel can be modulated by either the gate or well potential. Normal operation usually biases the well (or bulk) at the same potential as the source (i.e., V SB =0) , or the well to source junction is maintained in reverse bias. Maintaining zero or reverse bias from the source to well ensures that no carriers are injected laterally across the IC, which is a mechanism which leads to latch-up in CMOS circuits. However, if the source to well (or bulk) poten- tial, V SB , is forward biased and any laterally injected carriers are collected by heavily doped guard rings around the well, then latch-up is inhibited. This is especially true if the lateral current density is kept low, such as for small forward bias voltages for V SB (ie., <<0.5v) . The well could then be used directly to modulate the surface potential in the channel region of an MOS device in a useful and enhanced manner. When the well is tied directly to the gate and the MOS device is operated in weak inversion (sub- threshold) , the ideality factor in the exponential I-V relation becomes nearly unity (as in the case of a bipolar transistor) since the surface potential becomes modulated directly by the gate to source voltage, instead of by an "effective" gate to source voltage formed by a capacitive divider between C ox and Cdepie ion wherein: "effective" = V GS x C ox /(C ox + C depl ) . This will result in improved g m for MOS devices operated in weak inversion. Thus an effective, or dynamic, lowering of the threshold voltage, V τ , for MOS transistors can be obtained in circuits by forward bias of the well to source junction. Enhanced transconductance equal to that of bipolar transistors can be expected if the well is tied to the gate and the MOS device is ope¬ rated in weak inversion. The present invention is provided to solve these and other problems . Summary of the Invention It is an object of the present invention to provide a buffer circuit, such as for use with a hearing aid. The buffer circuit is adapted to be coupled between first and second electronic devices and substantially matches the output impedance of the first device with the input impedance of the second device. In accordance with one aspect of the invention, the hearing aid comprises a microphone, a receiver and an amplifier. The amplifier is disposed between said microphone and said receiver. The buffer circuit has an MOS device including a well terminal and a gate terminal which are equipotentially coupled together. By coupling the well terminal to the gate terminal, the threshold voltage V τ of the MOS device is reduced, thereby reducing the gate-to source voltage V GS of the MOS device. The invention is especially applicable in low power supply voltage circuits, such as hearing aids which are designed to operate on battery supply voltages as low as 1.1 v. Other features and advantages of the invention will be apparent from the following specification taken in conjunction with the following drawing. Brief Description of Drawings Figure 1 is a block diagram illustrating a circuit for a hearing aid incorporating the present invention; and Figure 2 is a schematic circuit of a portion of the hearing aid circuit illustrating the present invention in greater detail. Detailed Description While this invention is susceptible of embodi¬ ments in many different forms, there is shown in the drawings and will herein be described in detail, a preferred embodiment of the invention with the under¬ standing that the present disclosure is to be consi¬ dered as an exemplification of the principles of the invention and is not intended to limit the broad aspects of the invention to the embodiment illus¬ trated. A device, generally designated 10, for con¬ verting received sound to a corresponding amplified signal, and subsequently converting the amplified signal to a corresponding amplified sound is illus¬ trated in Figure 1. The device 10 comprises a battery 12 and an electret microphone 14. The battery 12 functions as a low voltage power supply, providing a nominal l.lv. The electret microphone 14 is as utilized in the commercially available Model EZ microphone, sold by Knowles Electronics of Itasca, Illinois. As is well known, the electret microphone includes a charged plate (not shown) which is coupled to the gate of an FET 18. Though not required for a complete understanding of this invention, a more detailed explanation is contained in co-pending patent applications 328 P 131 and 1860 P 017. As is also well known, the FET 18 has an input, herein the gate, and an output. The charged plate 14 is coupled to the gate of the FET. The device further comprises an amplifier 20 having an input 20a and an output 20b. The amplifier input 20a is coupled to the output of the FET 18. The amplifier output 20b has an output impedance which is proportional to the closed loop gain of the amplifier 20. The device further comprises a buffer, gener- ally designated 24, which is coupled to the output 20b of the amplifier 20. The buffer has a buffer input impedance substantially equal to the output impedance of the amplifier 20 and a buffer output impedance substantially less than the amplifier output impe- dance. The device also comprises a receiver 26 which converts the signal amplified by the amplifier 20 to an amplified sound, as is well known. The buffer 24 matches the relatively high output impedance of the amplifier 20 to relatively low input impedance of the receiver 26 to prevent gain attenuation. The device 10 also includes a constant current source, or refer¬ ence, 30. As discussed in greater detail below, the buffer 24 includes a MOS device and means for reducing the threshold voltage V τ of the MOS device to reduce the gate-to-source voltage of the MOS device. This minimizes the voltage drop across the buffer 24, permitting use of greater signal amplitudes from the amplifier 20 at the low voltage provided by the battery 12. The amplifier 20, buffer 24 and current refe¬ rence 30 are illustrated in greater detail in Figure 2. The signal from the FET 18 (Figure 1) is coupled to the amplifier at terminal V IN , and the amplifier 20 has a gain K of As noted above, the output impedance of the amplifier 20 is propor¬ tional to the amplifier 20. In the present illustra¬ tion, the gain K is twelve and the output impedance is 100 kΩ. Terminal V ouτ is coupled to the receiver 26. The term "receiver" is used herein, but could also include such other devices which potentially could be coupled thereto, such as additional amplifiers or other signal processing devices having relatively low input impedances. The voltage at V ouτ has a dc level of 0.4v, due to the required V GS of device MN1. When using conven¬ tional gate, source, drain and bulk connections, ie., with the bulk tied to the source, an n-channel MOS device has a nominal threshold voltage of 0.5v, which corresponds to a gate-to-source voltage of 0.4v, when operated in weak inversion. Assuming a design crite- rium of a battery voltage of l.lv, and assuming that all MOS devices require a source-to-drain voltage of 0.lv for linear operation, then the linear output range of the amplifier 20 is limited to 0.4v, peak-to- peak, for a sinusoidal input. In accordance with the present invention, and referring in particular to the output buffer 24 portion thereof, it has been found that by placing the bulk terminal of the n-channel MOS device 36 at the same potential as the gate potential of the n-channel MOS device 36, the effective threshold voltage is reduced dynamically, and hence the gate-to-source voltage, of the n-channel MOS device 36 is lowered to 0.25v. This reduction permits an increase in the linear output range of the amplifier from 0.4v to 0.6v for a sinusoidal input, an increase of 50%. It was noted above that such n-channel devices have a nominal threshold voltage of approximately 0.5 v. However in'practice this voltage varies device to device. Accordingly, circuits conventionally must have been designed to a certain extent to the worst possible case. It has been found that by dynamically reducing the effective threshold voltage as described above, the actual device to device variance is les¬ sened. It has also been found that by dynamically reducing the threshold voltage, the conductance g m of the n-channel device is increased by 33% above the conventional bulk connection methods, thereby further reducing the output impedance of the output buffer 24, typically to 300 Ω. It will be understood that the invention may be embodied in other specific forms without departing from the spirit or central characteristics thereof. The present examples and embodiments, therefore, are to be considered in all respects as illustrative and not restrictive, and the invention is not to be limited to the details given herein.

Claims: C L A I M S 1. A buffer circuit for a hearing aid, the hearing aid comprising a microphone, a receiver and an amplifier, said amplifier disposed between said microphone and said receiver, the buffer circuit having an MOS device including a well terminal and a gate terminal equipotentially coupled together. 2. A buffer circuit for a hearing aid, the hearing aid comprising a microphone, a receiver and an amplifier, said amplifier disposed between said microphone and said receiver, the buffer circuit for substantially matching output impedance of said amplifier with said input impedance of said receiver, the buffer device having an MOS device including a well terminal and a gate terminal equipotentially coupled together. 3. A buffer circuit for a hearing aid, the hearing aid comprising a microphone, a receiver and an amplifier, said amplifier disposed between said microphone and said receiver, the buffer circuit for substantially matching output impedance of said amplifier with said input impedance of said receiver, the buffer device having a MOS device and means for reducing the threshold voltage V τ of said MOS device to reduce the gate-to-source voltage of said MOS device. 4. A device for converting sound to a corre¬ sponding amplified signal, the device comprising: an electret microphone including a charged plate and an FET, the FET having an input and an output, said charged plate being coupled to said input of said FET; an amplifier having an input and an output, said amplifier input being coupled to said output of said FET, said amplifier output having an output impedance; buffer means coupled to said output of said amplifier, said buffer means having a buffer input impedance substantially equal to the output impedance of said amplifier and a buffer output impedance substantially less than said amplifier output impe¬ dance, said buffer means including a MOS device and means for reducing the threshold voltage V τ of said MOS device to reduce the gate-to-source voltage of said MOS device. 5. A device for converting sound to a corre¬ sponding amplified signal, the device comprising: a low voltage power supply; an electret microphone including a charged plate and an 'FET, the FET having an input and an output, said charged plate being coupled to said input of said FET; an amplifier having an input and an output, said amplifier input being coupled to said output of said FET, said amplifier output having an output impedance; buffer means coupled to said output of said amplifier, said buffer means having a buffer input impedance substantially equal to the output impedance of said amplifier and a buffer output impedance substantially less than said amplifier output impe¬ dance, said buffer means including a MOS device and means for reducing the threshold voltage V τ of said MOS device to reduce the gate-to-source voltage of said MOS device such that the voltage drop across said buffer means is minimized. 6. The device of claim 5 wherein said low voltage power supply comprises a battery having a voltage of 1.5v or less. 7. The device of claim 5 wherein said MOS device has a gate terminal and a well terminal, and said threshold voltage reducing means comprises said gate terminal and said well terminal equipotentially coupled together.

Inventors: BOOR STEVEN E, BOOR, STEVEN, E.
Applicants: KNOWLES ELECTRONICS INC, KNOWLES ELECTRONICS, INC.
Application year: 1995
Main classification: H04R25
IPC codes: G05F3, H04R25