Method for fabricating reverse-staggered thin-film transistor

Abstract: A method for a thin-film transistor employed as a liquid crystal display includes the steps of selectively forming a gate electrode on a substrate, covering the gate electrode and the substrate with a gate insulating film, forming a semiconductor channel layer on the gate insulating film, forming on the channel layer a semiconductor contact layer of a first conductivity type having first, second and third portions, forming source and drain electrodes respectively on the first and second portions of the contact layer, removing the third portion of the contact layer to expose a part of the channel layer, and forming a semiconductor region of a second conductivity type at the part of the channel layer.

Description: Background of the Invention Field of the Invention The present invention relates to a method for fabricating a thin-film transistor and, more particularly, to a method for fabricating a reverse-staggered thin-film transistor employed in a liquid crystal display device. Description of the Prior Art Fig. 1 shows a conventional thin-film transistor of an amorphous silicon. This thin-film transistor is constituted by a gate electrode 2, a gate insulating film 3 made of a silicon nitride film, an intrinsic amorphous silicon layer 4 and an n-type amorphous silicon contact layer 5, a drain electrode 6 and a source electrode 7. A protective layer 9 made of silicon nitride is further formed to cover the transistor. In this structure, the surface portion 10 of the amorphous silicon layer 4 between the drain electrode 6 and the source electrode 7 is sometimes called a "back channel" and has one of key factors determining the characteristics of the transistor. Specifically, if back channel 10 is contaminated and thus charged prior to the formation of the protective film 9, a leak current is caused to increase and thus flows between the source and drain. Even if the back channel 10 is not contaminated, the positive electric charges due to the contamination on the protective film 9 increase an electric field applied the back channel 10 up to or more than the threshold of the back channel. A leakage current thereby flows. Besides, the protective film 9 itself may be charged positively, so that the leak current also flows. In order to overcome such a problem, such a thin-film transistor is disclosed in Japanese Patent Laid-Open No. Hei 2-163972 that a back channel covered with an oxide film obtained from hydrogen peroxide or with an alumina film formed by the CVD process. Such a film can convert the back channel into a p-type one. The leakage current is thereby decreased. However, the p-type back channel thus converted depends on the quality of the oxide or the alumina film and is thus inferior in controllability. Moreover, when hydrogen peroxide is used, the drain and source electrodes are damaged by the hydrogen peroxide. In the case of the alumina film, on the other hand, alumina in the alumina film may be diffused into the amorphous silicon layer to change the property of a thin-film transistor. Another thin-film transistor is disclosed in Japanese Patent Laid-Open No. Hei 4-321275 to reduce the leakage current. In this transistor, an aluminum oxide layer is formed on a back channel. For this reason, this transistor also has the same problems as mentioned above. Turning to Fig. 2, there are shown another thin-film transistor which is disclosed in Japanese Patent Publication No. Hei 5- 083197, in which the same constituents as those shown in Fig. 4 are denoted by the same reference numerals. A similar method for fabricating a thin-film transistor is known from US-A-5 114 896. In this device, a portion of the n-type contact layer 5 which is not covered with the drain and source electrodes 6 and 7 is converted into a p-type region 11 by adding p-type impurities therein. The back channel is thereby covered with the p-type region 11. However, the contact layer 5 has a considerably high impurity concentration of 10 20 atoms/cm 3 or more. For this reason, it is necessary to dope the p-type impurities at a very high concentration. Such very highly doping lacks in controllability, however. Moreover, the very highly doped region 11 results in increase of the leakage current. Summary of the Invention It is therefore an object of the present invention to provide a method for fabricating a thin-film transistor of a low leakage current without deteriorating the characteristics thereof. It is another object of the present invention to provide a method for fabricating a thin-film transistor having a low leakage current by a simplified process. According to the thin-film transistor fabrication method of the present invention, it is possible to provide a structure in which a p-type amorphous silicon layer or a p-type polysilicon layer is formed uniformly on an intrinsic amorphous silicon layer directly. Therefore, the method has an advantage of preventing the leak current of a transistor which is increased due to contamination by cations coming from the outside and electron generation in a back channel by electrification of the protective film. Moreover, because p-type amorphous or p-type polysilicon can selectively be deposited on amorphous or polysilicon by exposing it to the gaseous phase of disilane containing diborane or silane, and there is no such side reaction as wiring is affected, aluminum diffuse in an amorphous or polysilicon layer, or process control is difficulty, a large advantage can be obtained. When using the plasma CVD process, there is an advantage that the film forming rate is high though the selectivity is low. Furthermore, there is an advantage that a high reliability is obtained because a p-type silicon layer directly contacts an amorphous or polysilicon layer and a silicon-nitride protective film and thereby a stable interface is obtained. The method of the present invention for fabricating a thin-film transistor is characterized in that p-type amorphous silicon layer with a thickness of 100 Å or less containing no n-type doped impurities is formed on a back channel of the intrinsic amorphous silicon directly. Because of containing no n-type doped impurities, impurity density of the p-type amorphous silicon layer is not so high that prevents current leakage according to uniformless ion distribution of the layer. Furthermore, it gets more uniformal ion distribution according to obtaining by gaseous phase of disilane or silane gas containing diborane. Moreover, the method of the present invention is characterized in that the p-type amorphous silicon layer can be obtained by exposing the intrinsic amorphous silicon layer to the gaseous phase of disilane or silane gas containing diborane. Furthermore, it is possible to use polysilicon instead of amorphous silicon. Brief Description of the Drawings The above-mentioned and other objects, features, and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, wherein: Fig. 1 is a sectional view of a thin-film transistor according to a prior art; Fig. 2 is a sectional view of a thin-film transistor according to another prior art; Fig. 3 is a sectional view illustrative of a thin-film transistor fabricated by a method according to an embodiment of the present invention; Figs. 4(a) to 4(d) are sectional views illustrative of respective steps of a method according to the embodiment of the present invention; and Fig. is a graph indicative of comparison in a source-drain current between the thin-film transistor shown in Fig. 1 and that shown in Fig. 1 or Fig. 2. Description of the Preferred Embodiments Referring now to Fig. 3, a thin-film transistor fabricated by a method according an embodiment of the present invention has a gate electrode 2 selectively formed on an insulating substrate 1, a gate insulating film 3 an intrinsic or non-doped amorphous silicon layer 4, an n-type amorphous silicon contact layer 5, a drain electrode 6, and a source electrode 7. This transistor further has a p-type amorphous silicon layer 8 on the back channel portion of the amorphous silicon layer 4 between the drain electrode 6 and the source electrode 7 in accordance with the present invention. The thickness of p-type amorphous silicon layer 8 is 100 Å or less. A protective such as silicon-nitride covers the p-type amorphous silicon layer 8 and a the source and drain electrodes 6 and 7. Turning to Fig. 4, the above thin-film transistor is fabricated as follows: First, as shown in Fig. 4(a), the gate electrode 2 made of a metal such as chromium is selectively formed on the insulating substrate 1 made of a glass or the like, followed by forming the gate insulating film 3 made of silicon nitride over the entire surface. The intrinsic or non-doped amorphous silicon layer 4 and the n-type amorphous silicon contact layer 5 are thereafter deposited in that order by the plasma CVD method. Then, the amorphous silicon layer 4 and the n-type amorphous silicon contact layer 5 are selectively etched to form an island by the lithography art, as shown in Fig. 4(b). Subsequently, a metal film made of chromium or the like is deposited over the entire surface by the sputtering method and then patterned to form the drain electrode 6 and the source electrode 7 as shown in Fig. 4(c). Thereafter, the portion of the n-type amorphous silicon contact layer 5 between the drain electrode 6 and the source electrode 7 is removed by using the electrodes as a mask by the wet etching method or the dry etching method in accordance with the present invention. This etching process is carried out until the surface portion of the amorphous silicon layer 4 is removed. That portion of the contact layer 5 is thus completely removed, the surface of the amorphous silicon layer 4 thus exposed serves as a back channel 10, as shown in Fig. 4(d). Turning back to Fig. 3, the p-type amorphous silicon layer 8 is then selectively deposited between the drain electrode 6 and the source electrode 7 in accordance also with the present invention. Finally the silicon-nitride protective film 9 is formed. The selective deposition of the p-type amorphous silicon layer 8 only on the exposed amorphous silicon layer is performed by mixing disilane Si 2 H 6 , hydrogen H 2 and diborane B 2 H 6 at the ratio of 3:2:6, setting the pressure of the mixed gas to 200 Pa and the substrate temperature to 350°C, and exposing the thin-film transistor shown in Fig. 4(d) to the mixed-gas atmosphere. The thickness of the layer 8 is several tens of angstroms though it cannot accurately be measured because the deposition rate is very low. Under the above conditions, the depositing time for the layer 8 can be approx. 15 min. Thereafter, the layer 8 is annealed in the nitrogen atmosphere at 250°C for 30 min. In the case of the above vapor-phase epitaxy, it is possible to use silane instead of disilane in the mixed gas. However, silane is not easily decomposed only by raising temperature. Therefore, it is better to use disilane. The ratio of disilane Si 2 H 6 to diborane B 2 H 6 of the mixed gas is set to 1:2. The ratio of hydrogen gas can be changed within the range of 0 to 10 when assuming the ratio of disilane as 1. Moreover, it is possible to add an inert gas such as argon to the mixed gas in order to adjust the pressure of the mixed gas. It is possible to properly changae the temperature of the substrate in the range of 300 to 400°C. However, the temperature goes out of the range, it is difficult to perform the vapor-phase epitaxy. Because it is enough to deposit a p-type amorphous silicon layer up to the thickness of 10 to 100 Å in a vapor phase, the layer can be deposited for 10 to 30 min. If the layer is too thick, there is a problem that leak current may flow. If the layer is too thin, it can not be formed uniformly. The annealing time is enough for 30 min to 2 hr. Because the p-type amorphous silicon layer 8 is obtained at a very low deposition rate, it is easily influenced by a substrate due to the same effect as the epitaxial art for single-crystal silicon and thus it is selectively deposited only on the intrinsic amorphous silicon layer 4. Therefore, the layer 8 is preferable because it is hardly deposited on areas of the substrate other than the intrinsic amorphous silicon layer 4. Presence of the p-type amorphous silicon layer 8 can be confirmed by measuring the depth profile through the SIMS element analysis and it is found that boron is present in layers with a thickness of 50 Å or less at a concentration of 10 18 to 10 19 atoms/cm 3 . Fig. 5 shows the property of the thin-film transistor of this embodiment. In particular, there is shown the current between drain and source to the gate voltage when applying the voltage of 10 V between the drain and source. From Fig. 5, it is understood that the current between the drain and the source is decreased for the gate voltage of -10 v to 0 V compared to the case of the prior art. That is, the leak current is decreased when the thin-film transistor is off. Moreover, in this embodiment, increase of the off current is not recognized even by applying +30 V to the gate electrode and 0 V to the source electrode for 90 min in the air of 80°C. This is because the p-type silicon layer directly contacts the silicon-nitride protective film 9 and a stable interface is formed. It is also possible to form a p-type amorphous silicon layer by using the plasma CVD process as another means. When using the plasma CVD process, the p-type amorphous silicon layer 8 with a thickness of several tens of angstroms is formed by mixing silane SiH 4 , hydrogen H 2 , and diborane B 2 H 6 at a mixing ratio of 1:1:2, setting the pressure of the mixed gas to 100 Pa (0.75 Torr), the substrate temperature to 300°C, and the electric power to 25 mW/cm 2 , and discharging electricity for 10 sec. When using the plasma CVD process, an advantage is obtained that a p-type amorphous silicon layer can be formed for several tens of seconds though the selectivity is low. It is previously described that it is preferable to use disilane and diborane for the vapor-phase epitaxy process. In the case of plasma CVD, however, it is better to use silane and diborane. Of course, it is possible to use disilane for the plasma CVD. However, because disilane is more easily decomposed than silane and therefore it is extremely decomposed due to plasma, disilane is not suitable for the plasma CVD. In the case of the plasma CVD, plasma serve as an assistant to decompose silane. Therefore, the combination of disilane and diborane in the vapor-phase epitaxy process corresponds to the combination of silane and diborane in the plasma CVD process. The mixing ratio of silane SiH 4 to diborane B 2 H 6 is set to 1:2 and hydrogen H 2 is mixed with the mixture of them in the range of 0 to 5. The pressure, substrate temperature, and electric power can be changed in the ranges of 80 to 120 Pa, 250 to 320°C, and 10 to 30 mW/cm 2 respectively. It is necessary to set the discharge time to several seconds to 1 min.

Claims: A method of fabricating a thin-film transistor comprising the steps of: forming a intrinsic or non-doped channel layer (4) of a semiconductor material on a gate insulating film (3); said semiconductor material is either amorphous silicon, or polycrystalline silicon; forming an n-type contact layer (5) on said channel layer; said contact layer having a first portion, a second portion and a third portion between said first and second portions; forming source and drain electrodes (6,7) on said first and second portions of said contact layer, respectively; and removing said third portion of said contact layer to expose a part of said channel layer; characterized in that said method further comprises the step of selectively depositing a p-type layer (8) of said semiconductor material which has no n-type impurities and a thickness of 10 nm or less on said part of said channel layer. The method as claimed in claim 1, further comprising the step of forming a protection layer (9) on said source and drain electrodes, and said p-type layer. The method is claimed in claim 1, characterized in that said p-type layer has a thickness in a range of 1 to 10 nm. The method as claimed in claim 1, wherein said p-type layer is formed by a plasma CVD method. The method as claimed in claim 4, wherein said plasma CVD method uses a mixed gas containing B 2 H 6 and SiH 4 as source gases. The method as claimed in claim 1, wherein p-type layer is formed by a vapor-phase epitaxy method. The method as claimed in claim 6, wherein said vapour-phase epitaxy method uses a mixed gas containing B 2 H 6 and Si 2 H 6 as source gases.

Inventors: KOIDE SHIN, OHI SUSUMI, KOIDE, SHIN, OHI, SUSUMI, KOIDE, SHIN, C/O NEC CORPORATION, OHI, SUSUMI C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1995
Main classification: H01L21
IPC codes: H01L21