BUS-TO-BUS BRIDGE

Abstract: A computer system that has two buses (30, 32) with different memory addressing capacities and a first bus master (36) that generates M-bit addresses is provided with a bridge (34) between the two buses. In order to generate N-bit addresses for use on the second bus (30), a direct memory access (DMA) controller (50) on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus (30) to address memory (40). The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.

Description: BUS-TO-BUS BRIDGE The present invention relates to a digital computer system, and more particularly, to the accessing of memory segments in a system which has two or more buses. In computer systems, electronic chips and other components are connected with one another by buses. A variety of components can be connected to the bus providing intercommunication between all of the devices that are connected to the bus. One type of bus which has gained wide industry acceptance is the industry standard architecture (ISA) bus. The ISA bus has twenty-four (24) memory address lines which therefore provides support for up to sixteen (16) megabytes of memory. The wide acceptance of the ISA bus has resulted in a very large percentage of manufactured devices being designed for use on the ISA bus. However, higher-speed input/output devices, such as video controllers, commonly used in current computer systems, require faster buses. A solution to the general problem of sending and receiving data from the processor to any high-speed input device is a local bus. Unlike the ISA bus, which operates relatively slowly with limited bandwidth, a local bus communicates at system speed and carries data in 32-bit blocks. Local bus schemes remove from the main system bus those interfaces that need quick response, such as memory, display, and disk drives. One such local bus that is gaining wide acceptance in the computer industry is the peripheral component interconnect (PCI) bus. The PCI bus can be a 32 or 64-bit pathway for high-speed data transfer. Essentially, the PCI bus is a parallel data path provided in addition to an ISA bus. The system processor and memory can be attached directly to the PCI bus, for example, or through a host bridge. Other devices such as graphic display adapters, disk controllers, etc. can also attach directly to the PCI bus. A bridge chip is coupled between the PCI bus and the ISA bus in order to provide communication between devices on the two buses. The bridge chip essentially translates the ISA bus cycles to PCI bus cycles, and vice versa. Many of the devices attached to the PCI bus and the ISA bus are master devices that are able to conduct processing independently of the bus or other devices. Slave or target devices accept commands and respond to requests of a master. The PCI bus has an addressing capability of thirty-two (32) bits that provide for four (4) gigabytes of memory access. Although it is possible for a master on the ISA bus to access a memory location in the memory on the PCI bus, the ISA bus master is normally limited to accessing only regions of memory from zero to 16 megabytes on the PCI bus, due to the 24-bit addressing capability of the ISA bus master. This renders a large portion of the 32-bit memory map inaccessible to ISA bus masters. Furthermore, some operating systems allocate the lower 16 megabytes of memory for purposes other than ISA bus masters. An arrangement that attempts to solve this problem sets the most significant bit of a 32-bit PCI address high, using external circuitry, when a master signal is detected on the ISA bus. This re-allocates the memory access to a specific 16 megabyte segment (or block) in a predefined region above the lowest 16 megabytes in the memory map. A disadvantage of this approach is the requirement of external circuitry, and inflexibility due to the limitation on reallocating the 16 byte memory block to the same location in the 4 gigabyte memory map. There is a need for an arrangement that provides programmable reallocation of memory blocks within a memory map in a system that has first and second buses with different memory accessing limits. This need is met by the invention claimed in claim 1. The present invention has the advantage of not requiring external circuitry to provide accesses above the lower megabytes of memory addressable by the M-bit addresses. Instead, a number of bits stored in a register are merely concatenated with the M-bit address to form the N-bit memory address capable of accessing any location in memory. Also, the concatenation of a plurality of bits to the M-bit address removes the prior art limitation on the reallocation of a memory segment to only one location in the memory map. In certain preferred embodiments, the register is programmable to respectively store specified values of the P bits in a storage location in the register. This feature permits dynamic reallocation of a memory segment to different locationβ in the memory map. An embodiment of the present invention will now be deβcribed, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a perspective view of a computer system to which the present invention is applicable, Figure 2 is a block diagram of the computer system of Figure 1 constructed in accordance with the prior art, Figure 3 is a block diagram of a memory map with a memory segment reallocated according to the prior art, Figure 4 is a block diagram of a memory map with a memory segment reallocated according to the present embodiment, Figure 5 is a block diagram of the computer system of Figure 1 constructed in accordance with the embodiment of the present invention, and Figure 6 is a block diagram of a DMA controller constructed in accordance with an embodiment of the present invention. With reference now to the Figures and in particular with reference to Figure 1, a conventional computer, or PC, designated 10, is of the type with which the invention has particular utility. Computer 10 which preferably, but not necessarily, is of a type utilizing an IBM personal computer or a similar system, includes a console housing 12 in which a circuit board containing the necessary circuitry including a microprocessor and BIOS chips, controllers, random access memory and other hardware are arranged. The computer alβo includes a video display 14 and a keyboard 16 connected to the housing 12 through cable 18. Mass storage media includes a hard disk drive within the housing and is non-accessible to the user, and user-accessible floppy disks, as well as, optionally, CD- ROM drives 20 and 22. Figure 2 is a block diagram of a prior art arrangement of a computer system. A local bus 30, such as a peripheral controller interconnect (PCI) bus 30, has a PCI memory slave 40 coupled to the PCI bus 30. The computer system also has a second bus serving as an expansion bus 32. This expanβion bus 32 can be, for example, an industry standard architecture (ISA) bus. Although the ISA bus 32 is much slower than the PCI bus 30, the ISA bus 32 is useful since many currently available devices that can be coupled to the ISA bus 32 are not able to perform at a rate of speed commensurate with the speed of the PCI bus 30. The configuration of Figure 2 therefore provides a first bus 30 which allows the use of high-speed devices, and a second bus 32 which allows the use of lower-speed devices. A bridge chip 34 provides an interface between the PCI bus 30 and the ISA bus 32. A plurality of ISA bus masters 36 and ISA memory slaves 38 are coupled to the ISA bus 32. The bridge chip 34 provides an interface between the PCI bus 30 and the ISA bus 32. An ISA bus interface 42 in the bridge chip 34 translates ISA bus cycles into a system bus cycle for use by the bridge chip 34. A PCI bus interface 46 converts PCI bus cycles from the PCI bus 30 into system bus cycles for the bridge chip 34. A DMA controller circuit 50 provides DMA control of memory accesses within the system. The DMA controller circuit 50 provides a plurality of separate DMA channels over which memory accesses involving the individual ISA masters 36 are respectively communicated. The DMA controller circuit 50 also provides system arbitration for the ISA bus masters 36 when they desire to perform a DMA transfer. As stated earlier, the addressing capability of the PCI bus 30 provides an addressing capability in memory of 4 gigabytes. Figure 3 is a map of the 4 gigabytes of memory and shows the reallocation of 16 megabytes of memory according to the prior art within the 4 gigabytes. Since the ISA bus master 36 can only generate 24-bit addresses, it is limited to addressing memory within a 16 megabyte segment. This is shown as the lower 16 megabytes of memory in Figure 3. It has been found desirable to reallocate the memory above this lower 16 megabyte segment. The prior art solution used external circuitry to set the most significant bit of a 32-bit PCI address high when a master signal was detected on the ISA bus 32. This reallocated the 16 megabytes of memory to a different location within the 4 gigabytes of memory aβ indicated in Figure 3. However, all accesses to the memory on the PCI bus 30 by the ISA bus masters 36 would be to this same reallocated segment. By contrast, as seen in Figure 4, the present embodiment provides dynamic reallocation of the 16 megabyte memory segment to any specified 16 megabyte segment of memory within the 4 gigabytes of memory. Each of the separate ISA bus masters 36 can have a separate 16 megabyte segment of memory within the 4 gigabytes of memory. An exemplary allocation of 16 megabyte segments according to the present embodiment is depicted in the memory map of Figure 4. For purposes of explanation, only certain elements of the system of the present embodiment according to Figure 2 are depicted in the block diagram of Figure 5. A single ISA bus master 36 is shown connected via the ISA bus 32 to the bridge chip 34. A single PCI memory slave 40 is coupled via the PCI bus 30 to the bridge chip 34. The DMA controller circuit 50 located on the bridge chip 34 includes a high page register 66 which contains the high byte of the ISA bus master memory address (an exemplary embodiment of the DMA controller 50 will be described in more detail later with respect to Figures 5 and 6. ) When the DMA channel is placed into cascade mode, as is known in the art, this implies that a given DMA channel of the DMA controller circuit 50 will be used for system arbitration by the ISA bus master 36. When the DMA controller circuit 50 detects a DMA arbitration request on the cascade mode channel, DMA controller circuit 50 attempts to gain control of the system for the ISA bus master 36. Once control is given to the cascade mode channel, the DMA controller 50 loads the contents of the high page register for that specific channel into a DMA transfer counter 68. When the DMA controller circuit 50 asserts an acknowledge signal, the ISA bus master 36 will begin its transfers to and from the PCI 32-bit memory. The high byte contained in the transfer counter 68 is concatenated with the 24-bit ISA bus master address to form the full 32-bit PCI memory address. The ISA bus master 36 operates in a conventional manner to address 16 megabytes. The accessing of memory above the 16 megabyte limit is transparent to the ISA bus masters 36, and is performed by the bridge chip 34 using the DMA controller 50 to concatenate a high byte to the ISA bus master address. Before describing a specific embodiment of a DMA controller that can be used to provide the upper eight bits of the 32-bit PCI address, a brief description of DMA controllers in general is provided below. In a digital computer, a microprocessor operates on data stored in a main memory. Since there are practical size limitations on the main memory, bulk memory storage devices are provided in addition to and separately from the main memory. When the microprocessor wants to make use of data stored in bulk storage, for example, a hard disk, the data is moved from the hard disk into the main memory. This movement of blocks of memory inside the computer is a very time consuming process and would severely hamper the performance of the computer system if the microprocessor were to control the memory transfers itself. In order to relieve the microprocessor from the chore of controlling the movement of blocks of memory inside the computer, a direct memory access (DMA) controller is used. The DMA controller receives information from the microprocessor as to the base location from where bytes are to be moved, the address to where these bytes should go, and the number of bytes to move. Once it has been programmed by the microprocessor, the DMA controller oversees the transfer of the memory data within the computer system. Normally, DMA operations are used to move data between input/output (I/O) devices and memory. A commercially available DMA controller is the 8237 DMA controller manufactured by Intel. Each 8237 DMA controller provides four separate DMA channels which can be used independently for memory transfers. Certain well-known computer systems, such aβ the IBM PC/AT design, contain two 8237 DMA controllers. The DMA controller circuit 50 of Figure* 5 and 6 uses these conventional DMA controllers 60, 62. One channel of the first DMA controller 60 is used to cascade the second DMA controller 62, as is known in the prior art. The pair of DMA controllers 60, 62 therefore provide a total of seven DMA channels, with four channels provided by the first controller 60, and three channels provided by the second controller 62. A number of different signals, such as the clock signal, etc., have not been shown in Figure 6 so as not to obscure the embodiment. However, one of ordinary skill in the art would recognize that these conventional signals would be used in practice. The first and second DMA controllers 60, 62 produce sixteen (16) bits of the memory address to the PCI bus 30 when the DMA controllers 60, 62 act as bus masters. The DMA controller circuit 50 also has a low page register 64 and a high page register 66. The low page register 64 has been used in prior art designs (such as the IBM PC/AT) to furnish another eight (8) bits of memory addressing capability, to produce a total of twenty-four (24) bit addressing capability, or 16 megabytes. The present embodiment provides an additional eight bits of memory addressing capability for a total of thirty-two (32) bit addressing capability, or 4 gigabytes. These additional 8 bits are provided on the PCI bus 30 (concatenated with the lower 24 bits of the memory address) by the high page register 66 when an ISA bus master 36 gains control of a DMA channel. The contents of the high page register 66 can be different for each of the seven different DMA channels, so that the seven ISA bus masters 36 are able to access seven different 16 megabyte segments of memory within the 4 gigabytes of memory on the PCI bus 30. The high page register 66 is programmable, so that the allocation of a specific memory location for a 16 megabyte segment for an individual ISA bus master 36 can be changed. The addition of a high page register to the existing design of a DMA controller circuit used in the IBM PC/AT computer system allows 32-bit addressing to a PCI bus, while using well-known and tested technology to provide the lower 24 bits of the memory addresses.

Claims: CLAIMS 1. A computer system comprising: a first bus having a memory addressing capacity of M bits; a first bus master, coupled to the first bus, that generates M-bit addresses for memory accesses; a second bus coupled to the first bus and having a memory addressing capacity of N bits, where N is greater than M; a second bus memory target coupled to the second bus; and a direct memory access (DMA) controller coupled to the first bus, the DMA controller having a register for storing high order P bits, where N = M + P, and logic for concatenating the high order P bits stored in the register with the M-bit address generated by the first bus master to form an N-bit address for addressing memory in the second bus memory target on the second bus. 2. The system of Claim 1, further comprising a plurality of first bus masters, wherein the DMA controller has a plurality of DMA channels over which memory addresses are communicated, each first bus master communicating over a different DMA channel, the register having a plurality of storage locations, each storage location corresponding to a different one of the DMA channels. 3. The system of Claim 2, wherein the register is programmable to respectively store specified values of the P bits in the individual storage locations. 4. The system of Claim 3, wherein the specified values of the P bits are different in each individual storage location, such that the N-bit addresses formed for the individual first bus masters are different to thereby access different blocks of memory in the second memory target. 5. The system of Claim 4, wherein the firβt bus is an industry standard architecture (ISA) bus, and the second bus is a peripheral component interconnect (PCI) bus. 6. The system of Claim 5, wherein M is 24, N is 32, and P is 8. 7. The system of Claim 6, wherein the DMA controller is a cascaded DMA controller. 8. A computer system comprising: a first bus having a memory addressing capacity of M bits; a first bus master, coupled to the first bus, that generates M-bit addresses for memory accesses to X-bytes of memory; a second bus coupled to the first bus and having a memory addressing capacity of N bits, where N is greater than M, for memory accesses to Y- bytes of memory, where Y is greater than X; a second bus memory target coupled to the second bus; and logic for programmably directing the first bus master to access X- byte size blocks of memory at any specified location within the Y-bytes of memory.

Inventors: BLAND PATRICK MAURICE, CRONIN DANIEL RAYMOND, HOFMANN RICHARD GERARD, MOELLER DENNIS, VENARCHICK LANCE MICHAEL, BLAND, PATRICK, MAURICE, CRONIN, DANIEL, RAYMOND, HOFMANN, RICHARD, GERARD, MOELLER, DENNIS, VENARCHICK, LANCE, MICHAEL
Applicants: IBM, IBM UK, IBM UNITED KINGDOM LIMITED, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1995
Main classification: G06F13
IPC codes: G06F12, G06F13