High-speed switch and high-speed switching method

Abstract: An electrical switch (116) is disclosed having multiple inputs (214) and switching means (312) operable to switch a signal from an input (214) via respective amplifiers (310). Amplifiers (310) are continuously operable and are provided with an auxiliary switching circuit (412) which provides the amplifier with a fixed voltage input signal when the associated input (214) is not selected. Response time upon selection of an amplifier (310) and crosstalk from any non-selected amplifier is minimised.

Description: The present invention relates to high speed electrical switches equipped with amplifiers and in particular relates to such switches in asynchronous transfer mode (ATM) switch arrangements. Asynchronous transfer mode is a standardised data communications protocol and method for transferring information within a telecommunications network, e.g between two telephone exchanges. ATM operates as a cell relay mechanism wherein data is grouped into fixed length packets or cells. The cells comprise a header and a payload. The header identifies the payload and the payload can comprise video, image, bursty data or voice communications. By providing fixed length cells, information can be handled in a more reliable fashion by switches. ATM is becoming a common technology for local area networks, metropolitan area networks and wide area networks, since all traffic types can be mixed in the same network, bandwidth can be rapidly reassigned on demand and information rates are scalable to very high speeds. Data transmission speeds are increasing: switches need to cope with the increased data rates. Switches determine the transmission path followed by a signal e.g. a signal from a telephone is directed via a private branch exchange to a particular communications link towards a destination telephone. The switches will have, typically, a number of inputs and a number of outputs. Obviously other types of switches occur having a single input or output. In an m x n electrical switch, signals arrive at an input and are routed to any one of n output. The input signals however need to be amplified before further processing and thus, associated with each input there is an amplifier to amplify the signal before being routed across the switch by transistor switching means to a desired output. Two arrangements are presently in use. In the first case, when a signal is input through a particular input, the associated amplifier is switched on and a certain delay is apparent before the amplifier becomes fully operational due to reactive effects in the amplifier circuit. As switching speeds increase to nano-seconds this delay can be a serious problem. In the second case, the amplifier remains switched on so as to reduce amplifier initialisation problems; this method, however, incurs reactive coupling effects between adjacent amplifiers and signal quality is diminished. As data rates increase, reactive coupling effects increase. JP-A-58-159024 discloses a high-speed electrical switch with amplifiers, each having an auxiliary switching circuit providing an amplifier node with a fixed power potential which turns off the amplifier when the respective input is not selected, thereby reducing crosstalk. US-A-5 196 733 discloses a high-speed electrical switch with amplifiers, each having an auxiliary switching circuit providing an amplifier input node with a reference potential and a further switch which turns off the amplifier, thereby reducing crosstalk when the respective input is not selected. The present invention seeks to provide a switch whereby the aforementioned problems are minimised. In accordance with the invention there is provided a high-speed electrical switch comprising multiple inputs, signal amplifying means associated with each input and switching means operable to switch an amplified signal from an input to an output, each amplifying means being provided with an auxiliary switching circuit, which auxiliary switching circuit provides the amplifying means with a fixed voltage input when the respective input is not selected and wherein the amplifying means are continuously biased in an operable state at their operating voltage whereby response time upon selection of an input to an amplifying means and crosstalk from any non-selected amplifying means is minimised. The amplifiers are thus continuously operable but do not affect operation or couple with data transmission through other inputs, yet when an amplifier is switched to an operational mode, there is no time delay and use of a particular data path is effective simultaneous with the switching of the appropriate amplifier. Such an switch may be used in an ATM arrangement, for example in telecommunications. In accordance with a further aspect of the invention there is provided a method of operating a high-speed multiple input switch having amplification means associated with each input comprising the steps of: maintaining any non-selected amplification means at a fixed input voltage; upon selection of an input, disabling the connection of the fixed input voltage to the respective amplification means, thereby allowing the signal from said selected input to be amplified; switching an amplified signal to an output; and, maintaining the amplification means continuously biased in an operable state at their operating voltage. In order that a better understanding of the invention will be obtained reference will now be made to the Figures, wherein: Fig. 1 shows a schematic layout of a high speed ATM switch; Fig. 2 details a selector having a select chip incorporating an electrical switch in accordance with the invention; Figure 3 shows amplifiers and switches on the chip selector; and Figure 4 shows an amplifier arrangement as shown in Fig. 3. For convenience, the description of the invention refers to a high-speed switch in an ATM switch arrangement, although the switch of the present invention can be used in any switch arrangement requiring both high switching speeds and signal amplification. Referring to Figure 1, there is shown a typical ATM switch arrangement. The switch can carry ATM cells from input buffers 120 to appropriate output buffers 126 through the switch 110. Since there are no cell buffers in the core, transmission into the core from the individual buffer modules must be coordinated such that cells do not collide at the space switch outputs. This is achieved by a controller circuit 118 which receives status information from the buffers 120, 126. It periodically sets up space switch connections through an optical 'shuffle' matrix 114 and sends control information back to the buffers to schedule the transmission of cells from the buffers, to coincide with the switching of the signals. The shuffle matrix 114 receives signals from each input buffer 120 via input fibres 122 and splitters 112, and distributes a signal portion to each selector 116. In the switch the control paths and the data paths are separated both functionally and physically. The selector 116 outputs an electrical signal which controls laser 224 (Fig. 2) which provides an optical signal which outputs through the output buffer 126 via output fibre 124. Cell routing information, provided in the ATM header is conveyed to the core controller over the control paths. The high speed data paths carry cells transparently from buffer to buffer through the switch; the switch does not inspect cell headers for routing. This requires synchronisation between control and data paths: the core must establish and hold connections in time with the passage of cells. Because of the high bit rates involved, in certain instances connections are set-up for durations much longer than 1 cell period, to allow sufficient guard time between cell streams, of the order of 1 or 2 cell periods (1 cell period = 40nsec approximately) wherein WDM or other means are employed to provide a predictable limit on time skew between control and data paths. ATM cells accumulate in buffers, segregated by intended output, until a path is set up by the core controller. Then, once a switch path exists, all or a specified number of cells in the buffer are transferred in a single batch to the output buffer and the connection is realised. It is the function of the controller to arbitrate requests for connections, and satisfy them in a fair and timely manner to achieve performance objectives. ATM cell buffers provide temporary storage between a random or a high speed source of cells, and a constrained sink such as a switch. The average outflow must equal the average inflow, or the buffer overflows or underflows. Underflow cannot occur in an ATM system since idle cells can (and must) be generated whenever the buffer is empty. The functions of the input and output buffers are quite distinct, although it is envisaged that they could be combined in a single in-out buffer for each link, with a time divided buffer control circuit serving both functions. The purpose of the input buffer is twofold, to provide a logical segregation of incoming traffic into pages according to destination (and possibly priority) and to ensure delivery of cells from the selected page to the space switch at the link rate. The function of the output buffer is primarily to accept all cells that come down the high speed link from the space switch core. Referring now to Fig. 2, there is shown a sixteen-input-one-output (M = 16; N = 1) selector switch 116 wherein an optical signal from one fibre of a number of input fibres 210 is converted to an electrical signal by a photodiode arrangement 212. The photo-diodes convert received optical signals to electrical signals and output the electrical signals via wire bond connections 214 to amplifiers on a selector chip 216. Typically the photodiodes are formed on an indium phosphide chip. Signals from the photodiodes are amplified and then selectively connected to a particular output by a series of switches such as 2:1 binary switches whereby only one input signal is connected to an output at any one time. Figure 3 details a switch arrangement having 16 electrical inputs 214 (this figure shows only the first two and last two inputs), amplifiers 310 serving each input 214 which outputs to switches 312. Switches 312 are shown as binary switches which are cascaded to a single output 314 which outputs via an electrical wire 220. Switches 312 are under the control of control means 118 (see Fig. 1). Binary switches 312 could be replaced by, for example, 4 x 1 switches or other known types. Output signals control laser driver 222 (see Fig. 2) which controls laser 224 which, in turn, outputs a data signal via fibre 124 to output buffer 126. Known amplifiers, as discussed earlier, are either operational at all times and are thus susceptible of causing cross-talk or are operational only when required, requiring reactive charge-up time. In the arrangement shown in Fig. 4, amplifier 410 receives an input signal IS from input 214, with the input line also being connected to a disabling circuit 412 at node 414. Amplifier 410 and disabling circuit 412 are controlled by control signals from controller 118. Amplifier 410 remains connected to the input 214 and powered-up at all times, but by reason of node 414 being connected to disabling circuit 412, when disabling circuit 412 is operated, node 414 is held to a fixed voltage whereby input signal IS is not amplified and accordingly minimal cross-talk is produced between selected and non-selected signals. Since the amplifier is biased in an operable state at its operating voltage, when it is desired to route a signal through a particular amplifier 410, a control signal is enabled to switch off the associated disabling circuit 412 whereby the input signal IS is amplified by amplifier 410 without any appreciable delay (more than a few nano-seconds). The output signal OS from the amplifier can be switched through binary switch arrangement 312 to output 314. The disabling circuit conveniently comprises a transistor circuit whereby when activated, node 414 is connected to a voltage source which disables the amplifier. The use of transistors as a switch is well known in the art and those skilled in the art will have no difficulty in designing a suitable arrangement. Control means 118 can comprise an auxiliary bias circuit to hold the amplifier at a correct voltage, as is known.

Claims: A high-speed electrical switch comprising multiple inputs (214), signal amplifying means (410) associated with each input and switching means (312) operable to switch an amplified signal (OS) from an input (214) to an output (314), each amplifying means (410) being provided with an auxiliary switching circuit (118, 412), which auxiliary switching circuit provides the amplifying means (410) with a fixed voltage input when the respective input is not selected and wherein the amplifying means (410) are continuously biased in an operable state at their operating voltage whereby response time upon selection of an input to an amplifying means and crosstalk from any non-selected amplifying means is minimised. A switch as claimed in claim 1 wherein the switch is an m x n switch comprising m inputs (214) and n outputs (314) and wherein the switching means (312) is operable to switch an input signal from any input to any output. An ATM switch comprising an electrical switch as claimed in claim 1 or 2. A switch for use in a telecommunications network comprising an electrical switch as claimed in claim 1 or 2. A switch as claimed in claim 4 wherein each input receives a signal from a photodiode receptive to optical communication signals. A method of operating a high-speed multiple input switch having amplification means (410) associated with each input (214), comprising the steps of: maintaining any non-selected amplification means at a fixed input voltage; upon selection of an input, disabling the connection of the fixed input voltage to the respective amplification means, thereby allowing the signal from said selected input to be amplified; switching (312) an amplified signal (OS) to an output (314); and, maintaining the amplification means (410) continuously biased in an operable state at their operating voltage.

Inventors: DAWE PIERS JAMES GEOFFREY, DAWE, PIERS JAMES GEOFFREY
Applicants: NORTHERN TELECOM LTD, NORTEL NETWORKS CORPORATION
Application year: 1995
Main classification: H03K17
IPC codes: H04Q3, H03K17