NON-VOLATILE MEMORY STRUCTURE INCLUDING PROTECTION AND STRUCTURE FOR MAINTAINING THRESHOLD STABILITY

Abstract: An improved non-volatile memory device (10) is provided, in which the threshold voltage variations (Vts) and transconductance degradation are significantly reduced. The NVM (10) includes protection structure (200) for limiting the process induced damage incurred during the manufacturing process. The protection structure (200) is utilized to provide reliable and stable dielectrical characteristics for the NVM device (10). The protection structure (200) is easy to implement and will not affect the conventional NVM (10) performance.

Description: NON- VOLATILE MEMORY STRUCTURE INCLUDING PROTECTION AND STRUCTURE FOR MAINTAINING THRESHOLD STABILITY FIELD OF THE INVENTION The present invention relates to an improved non-volatile memory (NVM) device, and more particularly to an NVM device which allows for a stable threshold voltage (V J and allows for a high transconductance and improved reliability. BACKGROUND OF THE INVENTION Nonvolatile memories (NVMs) are utilized in integrated circuits to provide storage of data when power is removed from the integrated circuit. It has been found that in NVMs, the threshold voltage (VJ can vary over a wide range due to in-line process related stress and damage. It has also been found that the threshold voltage of one type of NVM known as a FLASH cell, that the threshold voltage of the FLASH device in a mini array test structure is approximately .3 to .8 volts lower than the actual threshold voltage of the product cell. It has also been found that the threshold voltage for the reference cell can also be 0.3 to 0.8 vohs below the threshold voltage (W_) of the product. This difference causes the V„ of that given NVM device in the integrated circuit to be about a few tenths volt lower than the expected specification. Accordingly, this V B variation in reference cell of NVM product can create large column leakage currents that can cause a integrated circuit to function in an improper manner. In addition, it has also been found that this V B variation is not uniform from NVM to NVM in the manufacturing process. This variation therefore causes product reliability issues in the NVMs. The V β variation therefore requires that more complex synching and verifying circuitry be utilized with the NVM. The complex circuitry significantly increases the cost of the non- volatile memory. The V B variation also causes extensive product testing and analysis, significantly increases the cost of manufacturing and oftentimes limits the fabrication flexibility of the particular circuit. Finally, this problem causes problems with the process control, as well as significantly decreasing product yield. When the process induced damage is large, the transconductance of the -l- yield. When the process induced damage is large, the transconductance of the NVM can be seriously degraded and hence the device performance can be severely affected. What is needed therefore is a protection structure for non-volatile memory and the like that solves the threshold voltage instability problem. This system should be easy to implement, should improve product reliability, should significantly improve the performance of the non-volatile memory. The present invention addresses such a need. SUMMARY OF THE INVENTION It has been discovered that the V u instability is due to plasma induced charging damage on the dielectric layers of a nonvolatile memory device. Accordingly, in a first aspect, a non-volatile memory (NNM) comprises a metal layer,a first pohsilicon (p) layer coupled to the metal layer, and a dielectric layer coupled to the first p layer. The ΝNM further includes a second p-layer coupled to the dielectric layer, a tunnel oxide region coupled to the second p-layer, a source region coupled to the tunnel oxide region, and a drain region coupled to the tunnel oxide region The ΝNM in accordance with the present invention further includes protection means coupled to the metal layer for preventing plasma induced damage to the dielectric layer. In another aspect, the protection means comprises a porysilicon or metal fuse coupled between the metal layer and a p-substrate. In yet another aspect, the protection means comprises a diode coupled to the metal layer. In yet another aspect, the protection means comprises a transistor coupled to the metal layer. In a final aspect of the present invention, the protection means comprises a first diode coupled to the metal layer, a P well coupled to the first diode, a second diode coupled to the metal layer, and a Ν well coupled to the second transistor. The protection means in accordance with the present invention is utilized advantageously to prevent a process-induced charge build up and hence the stress voltage on the dielectric layers of the NVM and thereby provides for V α stability, high G m and better reliability. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a block diagram of conventional FLASH and poly-1 transistor devices. Figure la is a table showing antenna ratios for typically NVM devices. Figures 2-4 are charts that show the transconductance (G B ) degradation and V„ variation for the various poly-1 transistor and FLASH NVMs of Table 1. Figure 5 is a diagram of a physical model for plasma-induced ONO charging. Figure 6 is a first protection structure for preventing process induced damage in accordance with the present invention. Figure 7 is a second protection structure for preventing process induced damage in accordance with the present invention. Figure 8 is a third protection structure for preventing process induced damage in accordance with the present invention. Figure 9 is a fourth protection structure for preventing process induced damage in accordance with the present invention. Figure 10 is a fifth protection structure for preventing process induced damage in accordance with the present invention. Figure 11 is a sixth protection structure for preventing process induced damage in accordance with the present invention. DETAILED DESCRIPTION OF THE DRAWINGS The present invention relates to an improvement in non-volatile memory NVM structures which provides for the NNM reliability. The following description is presented to enable one of ordinary skill in the art to make an use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiments will be readily apparent to those skilled in the art, and the generic principles defined here may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. Referring now to Figure 1, what is shown is a block diagram of a nonvolatile memory cell (NNM) 10. The ΝNM 10 includes a metal layer (V^) 12, and a first polysilicon (p) layer 14 coupled to the metal layer 12. A dielectric layer 16 is coupled to the first p-layer 14. The dielectric layer 16 in this embodiment as shown in the cutaway view is an oxide/nitride/oxide (OΝO) layer. A second p-layer 18 is coupled to the OΝO layer 16. A tunnel oxide region 20 is coupled to the second p-layer 18. Source and drain regions 22 and 24 are coupled to the tunnel oxide region 20. Typically the first p-layer is between 1500 A - 5000 A thick. The dielectric layer is between 80 A to 500 A. The second p-layer is typically between 1000 A - 3000 A. Finally, the tunnel oxide is typically less than 150 A. Plasma-induced oxide damage is a critical issue in CMOS device scaling and reliability. It has been determined that plasma induced damage to the OΝO dielectric layer 16 is the principal reason for the instability of the threshold voltage (V„). Figure la shows a table of FLASH and POLY ΝVMs with different antenna ratios. Figures 2 and 3 are charts that show the transconductance (G m ) degradation for the various poly-1 transistors and FLASH ΝNMs of Figure la. Referring now to Figures 2 and 3, significant transconductance (G m ) degradation has been observed on devices with high antenna ratios. In addition, referring now to Figure 4, UN-erased threshold voltage (V Λ1IΪ ) increased with increasing antenna ratio for both poly-1 transistors and FLASH ΝNM devices. The pronounced difference in shifts of V ftuv between FLASH and Poly-1 devices is a result of the charge trapping in the OΝO dielectric layer 20 (Figure 1). Accordingly, it has been determined that a build-up of charges on the gate (polysilicon 14) during plasma processing is the reason for the V„ instability. These charges induce electric fields across the OΝO dielectric layer 16 and the tunnel oxide region 20 which are inversely proportional to the OΝO dielectric thickness (layer 16) and tunnel oxide thickness (region 20), respectively. As the NVM device is scaled or shrinked, this problem becomes more acute. Moreover, it has been found that there are enhanced electron trapping in the larger antenna ratio capacitor. It has also been found that the level of plasma damage in the ONO dielectric layer and tunnel oxide layer is proportional to the antenna ratio. (These results are consistent with the plasma stress data shown in Figures 3 and 4). A physical model for plasma-induced ONO charging has been proposed as shown in Figure 5. At low field plasma stressing, hole-dominated Frankel- Poole conduction (process A) results in the initial positive charge trapping in the ONO film and hence the V ΛUV reduction. At high field stressing, electrons will tunnel into the Poly-1 gate (process-B), and then the ONO dielectric (process C). Tunnel oxide damage during process B and electron trapping at the bottom SiO j /SiN, interface in process C lead to the observed G m degradation and V^,, increase. Therefore, all the V ΛBV and G m dependencies on different structu res can be interpreted with this model. Therefore the plasma-induced ONO charging and tunnel oxide damage were responsible mechanisms for V ΛUV instability and G m degradation in non¬ volatile memories. The degree of plasma damage in the ONO dielectric and tunnel oxide increased with increasing device antenna ratio. The present invention is directed toward providing protection structures to limit the plasma induced charging and stress damage to the dielectric layer 16 and the tunnel oxide 20, and to eliminate V ΛUV stability and G m degradation in NVMs. To more particularly, describe the advantages of the present invention refer now to Figures 6-11 in conjunction with the following discussion. Figures 6-11, show schematic diagrams of various protection structures for NVMs that would limit process induced damage on protected NVMs and would therefore provide a more stable V„ than in known NNMs. Figure 6 shows a first protection structure 200 which comprises a polysilicon or metal fuse 202 between metal layer 14 and a p-substrate 204. This protection structure is simple and very easy to manufacture. For example, a polysilicon fuse (l x w x d = 5μm X lμm X 0.20μm) can easily be blown out at a current of 50MA and a voltage of 1.5V. For the metal fuse 202, the fuse fabrication process is further simplified and can be combined together with the device metal etch process. Also if the metal width can be optimized so that it will broken by the end of the etch process, it becomes a self-fusing type of fuse device. Figure 7 shows a second protection structure 300 which includes multiple fuses 302 coupled to a P-substrate 304. Figure 8 shows a third protection structure 400 which comprises P + diode 404 connecting to the gate of the NNM 10. In this case, some leakage current may pass through the P + diode 404 when the voltage on the control gate is positive. The Ν-well 406 coupled to the P + diode 404 can be made large enough to drain all the generated charge. Figure 9 shows a fourth protection structure 500 which comprises a PMOSFET transistor 504 connecting to the gate of the ΝNM 10. In this case, some leakage current may pass through the transistor 504 when the voltage on the control gate is positive. The Ν-well 506 coupled to the transistor 504 can be made large enough to drain all the generated charge. This protection structure 500 can be used in any type of circuit if a PMOSFET as a buffer transistor is allowed. Figure 10 shows a fifth protection structure 600 which comprises the control gate (or metal) of the ΝNM 10 coupled to a self-turn-on transistor 604. During plasma etch, the gate voltage of the ΝMOS device increases due to plasma-induced voltage and then turn-on the transistor to discharge the charges on the control gate 602 automatically. Figure 11 shows a sixth protection structure 700 which comprises the control gate for the ΝNM 10 coupled to both Ν + and P + diodes 704 and 706 which include a deep P-well 708 and large N-well 710, respectively (a self-turn on NMOS 712 can be added if P-well cannot drain negative charge efficiently into big N-well). Now, both positive and negative induced charges can be discharged into large N-well 708 and deep P-well 710. The advantage of this structure is that both leakage paths can be blocked by biasing deep P-well and N-well properly. Another protection structure that could be utilized with the NVM 10 is a combination of the structures of Figures 8-10. In addition, another protection structure could comprise any of the protection structures coupled to different layers (such as poly-1, poly-2; Ml, M2, etc) of non-volatile memories to fully protect the NVM during the entire fabrication process. Measuring the V„ of NVMs utilizing the above-identified protection structures coupled to each of the critical layers can provide useful information for etch process optimization, manufacturing and diagnostic tests to improve reliability and yield. A NNM device 10 which includes a protection structure in accordance with the present invention has several advantages over known ΝNM devices. Firstly, a ΝNM device 10 with a protection structure in accordance with the present invention will limit V u instability through the elimination of in-line process induced damage. As a consequence product reliability will be greatly enhanced. V„ sensing and verifying circuitry will therefore be simplified which will in turn significantly reduce product cost. There will also be a significantly less product testing and analysis time required. Also, the G m improvement by eliminating the plasma-damage can significantly improve product reliability and performance. Manufacturing constraints will be eased and product fabrication flexibility will be greatly improved. By utilizing a protection structure in accordance with the present invention key etching problems can be identified and etch processes can then be optimized. As a result the process control and product yield for a ΝNM can be significantly enhanced. Although the present invention has been described in accordance with the embodiments shown in the figures, one of ordinary skill in the art recognizes there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skills in the art without departing from the spirit and scope of present invention, the scope of which is defined solely by the appended claims.

Claims: CLAIMS 1. A non-volatile memory (NVM) which provides for improved reliability comprising: at least one metal layer; a first polysilicon (p) layer coupled to the at least one metal layer; a dielectric layer coupled to the first p layer; a second p layer coupled to the dielectric layer; a tunnel oxide region coupled to the second p layer; a source region coupled to the tunnel oxide region; a drain region coupled to the tunnel oxide region; protection means coupled to the at least one metal layer for preventing process induced damage to the dielectric layer and the tunnel oxide region. 2. The NVM of claim 1 which includes multiple metal layers. 3. The NNM of claim 1 in which the first p-layer comprises a thickness of between 1500 A - 5000 A. 4. The ΝNM of claim 1 in which the dielectric layer comprises a thickness of between 80 A to 500 A. 5. The ΝNM of claim 1 in which the second p-layer comprises a thickness of between 1000 A - 3000 A. 6. The ΝNM of claim 1 in which, the tunnel oxide region comprises a thickness of less than 150 A. 7. The ΝNM of claim 1 in which the dielectric layer comprises an oxide/nitride/oxide (OΝO) layer. 8. The NVM of claim 1 in which the protection means comprises a polysilicon fuse coupled between the at least one metal layer and a p-substrate region. 9. The NVM of claim 8 in which the polysilicon fuse is self fusing. 10. The NVM of claim 1 in which the protection means comprises a plurality of polysilicon fuses coupled between each metal layer and a p-substrate. 11. The NNM of claim 1 in which the protection means comprises a metal fuse coupled between each metal layer and a p-substrate region. 12. The ΝNM of claim 1 in which the protection means comprises a plurality of metal fuses coupled between the at least one metal layer and a p- substrate. 13. The ΝNM claim 11 in which the metal fuse is self fusing. 14. The ΝNM of claim 1 in which the protection means comprises a diode coupled to the at least one metal layer. 15. The ΝNM of claim 1 in which the protection means comprises a transistor coupled to the metal layer. 16. The ΝNM of claim 14 in which the transistor comprises a PMOSFET buffer transistor in a big Ν-well connected to the at least one metal layer. 17. The ΝNM of claim 1 in which the protection means comprises a self-turn-on transistor coupled between the at least one metal layer and a p- substrate. 18. The NVM of claim 1 in which the protection means comprises: a first diode coupled to the at least one metal layer; a P well coupled to the first diode; a second diode coupled to the at least one metal layer; and a N well coupled to the second transistor. 19. The NVM of claim 18 in which the first diode comprises an N diode and the second diode comprises a P diode. 20. The NNM of claim 19 in which the P well comprises a deep P well and the Ν well comprises a large Ν well. 21. The ΝNM of claim 1 in which the protection means comprises a self turn on ΝMOS between deep P well and p-substrate. 22. A non-volatile memory (ΝNM) which provides for threshold voltage (V„) stability comprising: a metal layer; a first polysilicon (p) layer coupled to the at least one metal layer, the first p-layer comprising a thickness of between 1500 A - 5000 A; an oxide/nitride/oxide (OΝO) layer coupled to the first p-layer, the OΝO layer comprising a thickness of between 8θA to 50θA; a second p-layer coupled to the OΝO layer, the second p-layer comprising a thickness of between 1000 A - 3000 A; a tunnel oxide region coupled to the second p layer, the tunnel oxide region comprising a thickness of less than 150 A; a source region coupled to the tunnel oxide region; a drain region coupled to the tunnel oxide region; protection means coupled to the at least one metal layer for preventing process induced damage to the dielectric layer and the tunnel oxide region. 23. The NVM of claim 22 in which the protection means comprises any combination of: a polysilicon fuse coupled between the metal layer and a p-substrate region; a plurality of polysilicon fuses coupled between each metal layer and a p- substrate; a metal fuse coupled between each metal layer and a p-substrate region; a plurality of metal fuses coupled between the metal layer and a p- substrate; a diode coupled to the metal layer and a transistor coupled to the metal layer; a self -turn-on transistor coupled between the metal layer and a p-substrate; and a first diode coupled to the metal layer; a P well coupled to the first diode; a second diode coupled to the metal layer and a N well coupled to the second transistor.

Inventors: CHANG CHI, FANG HAO, HADDAD SAMEER, CHANG, CHI, FANG, HAO, HADDAD, SAMEER
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1995
Main classification: H01L27
IPC codes: H01L27