Off-chip driver circuit

Abstract: An off-chip driver circuit having circuitry for providing protection against high voltages when the off-chip driver circuit is disabled is described. The circuitry for providing protection against high voltages utilises a minimum number of transistors and therefore minimises the chip area utilised by the off-chip driver circuit.

Description: This invention relates to an off-chip driver circuit and is particularly but not exclusively concerned with an off-chip driver circuit implemented in CMOS technology and which has a supply voltage less than the supply voltage of external circuits which may be connected to the output of the off-chip driver circuit. An off-chip driver circuit should be designed not only to successfully drive logic levels relating to the supply voltages of the circuit off-chip but to be protected against any high voltages which may occur when the off-chip driver circuit is disabled and its output terminal is coupled to an external circuit operating at a higher supply voltage. It is desirable to provide this protection while minimising the number of transistors and therefore the chip area utilised by the off-chip driver circuit. Figure 1 is a circuit diagram of a known off-chip driver circuit. This circuit is described in US Patent 5,151,619 assigned to International Business Machines Corporation but is described in the following by way of background to the present invention. The off-chip driver circuit has first and second input terminals, IN,IN' which are connected to a pre-driver circuit. The off-chip driver circuit is arranged in an output mode to drive a signal at the input terminals IN,IN' to an output terminal OUT. When the off-chip driver circuit is used in this mode, the signal level on the first input terminal IN is the same as the signal level on the second input terminal IN'. A first p-channel field effect transistor 2 acting as a pull-up transistor and a second n-channel field effect transistor 4 acting as a pull-down transistor are serially arranged between a supply voltage Vdd and a point of reference potential Vss. The reference potential will generally be at ground. The output terminal OUT is taken at a point between the pull-up transistor 2 and the pull-down transistor 4. A pass gate 6 is formed by an n-channel transistor 8 having its gate connected to receive the supply voltage Vdd and its drain/source path connected between the input terminal IN and the gate of the pull-up transistor 2. The n-channel transistor 8 acts in cooperation with a p-channel transistor 10 connected with its drain/source path in parallel with the drain/source path of the n-channel transistor 8 and its gate connected to the output terminal OUT. The pull-down transistor 4 has its gate connected to the second input terminal IN'. The off-chip driver circuit includes a control transistor 12 which has its gate connected to a control potential Vref and its drain/source path connected in series between the pass gate p-channel transistor 10 and the output terminal OUT. The pass gate p-channel transistor 10 and the control transistor 12 are formed in a common n-well 16. A further p-channel transistor 14 is connected to act as an n-well bias transistor and is connected between the supply voltage Vdd and the n-well 16, with its gate connected to the output terminal OUT. The off-chip driver circuit has its output terminal OUT selectively connectable to an external circuit 18 which has a separate supply voltage Vcc and which is used in an input mode of the off-chip driver circuit to supply signals onto the chip via the output terminal OUT which is connected to an input signal line (not shown). The voltage supply for the off-chip driver circuit is typically about 3.3V±0.3V. However, the external circuit may operate at a higher voltage, for example conventional CMOS levels of about 5V. When used as an off-chip driver circuit, the circuit should be capable of driving the output terminal at 0V (for a logical zero) or 3.3V±0.3V (for a logical one). However, when not being used, the circuit needs to be able to tolerate voltages in the range of 0 to 5V which may be supplied at the output terminal OUT from the external circuit 18. The off-chip driver circuit should also be able to tolerate breakdown conditions in the external circuit 18, which may take the voltage applied to the output terminal OUT as high as about 7V. As is well known, and more fully discussed in the above-referenced US 5,151,619, with the input terminals IN,IN' at a logical zero the voltage at the output terminal OUT will be at Vdd. With the first and second input terminals IN,IN' at 3.3±0.3V the voltage at the output terminal OUT will be at a low voltage of approximately 0V. To disable the off-chip driver circuit, the pre-driver circuit attached to the first and second input terminals IN,IN' is tristated so that with the first input terminal IN high, the second input terminal IN' is low. Typically, with the off-chip driver circuit in a disabled condition, the input terminal IN is at 3.3V±0.3V and the input terminal IN' is at 0V. In this condition, the pull-down n-channel transistor 4 is off. The circuit of Figure 1 is designed to operate when disabled as follows. With a voltage of 0V at the output terminal OUT, the pass gate p-channel transistor 10 is turned on and passes the voltage of 3.3V±0.3V on the first input terminal IN to the gate of the pull-up transistor 2, thus turning it off. Thus, there is no leakage current through the pull-up transistor 2. When a high voltage, for example of 5V is applied to the output terminal OUT by the external circuit 18, the p-channel pass gate transistor 10 is turned off. However, the p-channel control transistor 12 is turned on because the voltage applied at its source exceeds the control voltage Vref at its gate. This thus presents the voltage at the output terminal OUT to the gate of the pull-up p-channel transistor 2, likewise turning it off. In this condition, the voltage at the gate of the p-channel transistor 2 is roughly the same as the voltage on the source of the p-channel transistor 2 and therefore the oxide of the p-channel transistor is not subject to any significant stress. Therefore, in these conditions at the extreme ends of the likely voltages to be imposed by the external circuit 18, the prior art circuit of Figure 1 works well. However, problem arise at median conditions and in transition states. Consider first the state where the voltage at the output terminal OUT is changing from 5V to 0V. As described above, at 5V the control transistor 12 is on, the pass gate p-channel transistor 10 is off and thus 5V is passed to the gate of the pull-up p-channel transistor 2. On the assumption that the control voltage Vref at the gate of the control transistor 12 is about the same as Vdd, namely 3.3V + 10%, the transistor 12 will cease to be on at a voltage which is the control voltage Vref plus a threshold voltage Vtp (0.7V, say), namely about 4V. In this condition, about 4V will remain floating at the gate of the pull-up p-channel transistor 2 while the source of that transistor coupled to the output terminal OUT will see a lowering voltage as the voltage on the output terminal OUT drops down to zero. Thus, the gate to source voltage of the pull-up transistor 2 may exceed the prescribed values permitted for stresses applied to the oxide. This state will endure until the voltage on the output terminal OUT has dropped to a sufficiently low level to turn on the pass gate p-channel transistor 10 which will then provide a discharge path to balance the voltage at the gate of the pull-up transistor 2 with the voltage on the first input terminal, which is at about 3.3V + 10%. There is thus a window or "dead zone" of Vref±Vtp where neither the pass gate transistor 10 nor the control transistor 12 is ON. During this dead zone, the voltage at the gate of the pull-up transistor 2 is not tracking either the supply voltage Vdd or the output voltage. Another difficulty arises at a so-called median condition. In order to turn the control transistor 12 on, the voltage at the output terminal must be at least a threshold voltage Vtp above the control voltage Vref at the gate of the control transistor 12. If this condition is not satisfied, the control transistor 12 will remain off. Consider the case where the voltage at the output terminal is slightly above or slightly below the reference voltage, normally 3.3V. Thus, the voltage is not low enough to turn on the p-channel pass gate transistor 10 nor is it high enough to turn on the control transistor 12. Thus, both the transistors 10 and 12 are off. The n-channel transistor 8 of the pass gate will try and pull up the gate of the p-channel transistor 2 but it will only be able to pull it up to a threshold below the voltage on the input, namely to about 2.6/2.7V. This is inadequate to reliably turn off the pull-up p-channel transistor 2 and therefore there will be a leakage current through that transistor. Thus, during transition states and at voltages within a threshold voltage of the supply voltage Vdd, the prior art circuit of Figure 1 has several disadvantages. One solution proposed to the problem of over-stressed gate oxide is to provide transistors with thicker oxides for those which are likely to be subject to stress. However, this increases the process costs because it requires two oxide deposition steps. Another solution is proposed in an article entitled "3.3V-5V Compatible I/O Circuit without Thick Gate Oxide" by Takahashi, et al in IEEE 1992 Custom Integrated Circuits Conference, 23.3.1 - 23.3.4. In that solution, different types of transistors are introduced to exclude undesirable leakage paths and to prevent oxide stresses. This solution also suffers from the disadvantage that it requires different fabrication techniques. IBM Technical Disclosure Bulletin, Vol. 34, No. 4B, September 1991, pages 147-149 discloses a scheme for mixed technology overvoltage protection. Circuitry for protecting a low voltage output driver device from a high voltage environment is disclosed, in particular with the objective of ensuring the output of the output driver is free from leakage current in a high-impedance state. It is an object of the present invention to provide an off-chip driver circuit which overcomes the disadvantages outlined above using circuit techniques and without significantly increasing the amount of area required for the circuit. According to the present invention there is provided an off-chip driver circuit having an input terminal and an output terminal: a pull-up transistor having a controllable path connected between a first power supply voltage and the output terminal of the off-chip driver circuit and a control terminal connected to the input terminal via a pass gate connected to isolate the input terminal from high voltages applied to the output terminal; a control transistor having a controllable path connected between the control terminal of the pull-up transistor and the output terminal and a control terminal connected to a control potential; an auxiliary pass transistor having a control terminal and a controllable path connected between the control terminal of the pull-up transistor and a voltage node which is at the same logical value as the said input terminal (IN); an auxiliary control transistor, the auxiliary control transistor having a control terminal connected to receive said control potential and a controllable path connected between the output terminal and the control terminal of the auxiliary pass transistor; auxiliary circuitry for holding the control terminal of the auxiliary pass transistor in a state determined by the auxiliary control transistor; and the pass gate including an isolation transistor connected between the input terminal and the control terminal of the pull-up transistor and a control terminal connected to the output terminal. The auxiliary circuitry can comprise an auxiliary pull-down transistor having a controllable path connected between the control terminal of the auxiliary pass transistor and a reference potential, and a control terminal connected to a voltage selected to maintain the auxiliary pull-down transistor on. Alternatively, the auxiliary circuitry can comprise first and second auxiliary pull-down transistors connected in series between the control terminal of the auxiliary pass transistor and a reference potential, said auxiliary pull-down transistors having control terminals connected respectively to a power supply voltage for the driver circuit and a voltage selected to maintain the auxiliary pull-down transistor on. In the preferred embodiment, the voltage node of the auxiliary pass transistor is connected directly to the data input terminal. In the preferred embodiment, the pull-up transistor, isolation transistor, control transistor, auxiliary pass transistor and auxiliary control transistor are all p-channel transistors. It is particularly advantageous if they are formed in a common n-well which is biased by a further p-channel transistor having a control terminal coupled to the output terminal. In the drawings: Figure 1 is a circuit diagram of a known off-chip driver circuit; and Figure 2 is a circuit diagram of an off-chip driver circuit according to an embodiment of the present invention. For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to Figure 2. In Figure 2, like numerals denote like parts as in Figure 1. As these components have already been discussed, they will not be referred to again in the following except insofar as their operation is affected by the additional components introduced by way of the invention. The circuit of Figure 2 additionally includes an auxiliary p-channel pass transistor 20 and an auxiliary control p-channel transistor 22. The auxiliary pass transistor 20 and the auxiliary control transistor 22 are, like the p-channel transistors 10 and 12 formed in the common n-well 16 biased by the transistor 14. The auxiliary control transistor 20 has its source/drain path connected between a voltage node 32 and the gate of the pull-up transistor 2, and its gate connected to a pull-down device 24. In the illustrated embodiment the voltage node 32 is connected directly to the data input terminal IN. The gate of the auxiliary pass transistor 20 is also connected to the output terminal OUT via- the auxiliary control transistor 22. The auxiliary control transistor 22 has its gate connected to the control voltage Vref which is the same as the voltage applied to control the gate of the control transistor 12. In the preferred embodiment, Vref is the same as the supply voltage Vdd (3.3V±0.3V). In the embodiment illustrated in Figure 2, the pull-down device 24 is formed by two n-channel transistors 26,28 in series between the gate of the auxiliary pass transistor 20 and a point of reference potential Vss, such as ground. The gates of the n-channel transistors 26,28 are both tied to the supply voltage Vdd. The circuit of Figure 2 also additionally includes an n-channel transistor 30 in series between the pull-up p-channel transistor 2 and the pull-down n-channel transistor 4, with its gate tied to the supply voltage Vdd. This transistor merely serves to limit the voltage swings on the pull-down n-channel transistor 4, as discussed for example in IEEE Journal of Solid-state circuits, Vol. 23 No. 5, October 1988, Wong et al, pps 110-1102. The auxiliary pass transistor 20 and the auxiliary control transistor 22 are both relatively small devices, of the same order of magnitude as the p-channel pass transistor 10 and the control transistor 12. The function of these transistors to overcome the problems discussed above will now be described. Consider first the situation where the voltage applied to the output terminal OUT is switching from 5V to 0V. At 5V, the control transistor 12 is turned on, thereby presenting 5V to the gate of the pull-up p-channel transistor 2, firmly holding it off. Moreover, the pass gate transistor 10 is held off, isolating the input terminal from the high voltage. In this condition, the auxiliary control transistor 22 is also on, ensuring that the auxiliary pass transistor 20 is off. As the voltage at the output terminal reduces, it reaches a point, as discussed above, where it no longer holds the control transistor 12 on. As the control transistor 12 turns off, so too does the auxiliary control transistor 22 because it is subject to the same conditions as the control transistor 12. As the auxiliary control transistor 22 turns off, it causes the auxiliary pass transistor 20 to turn on. The pull-down device 24 holds the gate of the auxiliary pass transistor 20 low. This provides a discharge path for the voltage at the gate of the p-channel pull-up transistor 2 to the first input terminal to reduce the voltage at the gate of the p-channel pull-up transistor 2 to a value approximately equal to that at the input terminal, namely 3.3V±0.3V. Note that during this time, the p-channel pass gate transistor 10 is still off. Thus, the auxiliary pass transistor 20 provides an additional discharge path in the situation of transiting voltages on the output terminal to ensure that the pull-up p-channel transistor 2 is not subject to excessive gate source voltages and therefore excessive stresses on the oxide. Another problem arose with the prior art circuit of Figure 1 at so-called median voltages, within a threshold voltage of the control voltage Vref. Consider now such a voltage, of for example, just above or just below 3.3V. When this voltage is applied to the output terminal OUT, the control transistor 12 is not turned on. Therefore, the auxiliary control transistor 22 is also not turned on. Thus, the auxiliary pass transitor 20 is turned on and provides a path from the first input terminal to the gate of the p-channel transistor 2 to allow it to pass more or less its full 3.3V±0.3V to the gate of the pull-up p-channel transistor 2, thus firmly turning it off. This prevents leakage current in this condition. It will readily be appreciated that there may still be a small amount of leakage current even while using the invention, but this will be maintained well below specification levels of about 20-30 uA. -In contrast, the prior art circuit of Figure 1 could have a leakage current of the order of milliamps. Although the pull-down device 24 is shown as being implemented by two n-channel transistors 26,28 connected in series, it will readily be apparent that a single n-channel transistor could be used instead, or, indeed, any other implementation of a suitable pull-down device. In particular an ideal current sink could be used. Such an ideal current sink could be implemented with the transistor 26 having its gate connected to Vdd and with the transistor 28 having its gate connected to another voltage level, for example between 1 and 1.5V. The provision of two n-channel transistors in series limits the voltage swing across each of the transistors individually and therefore serves to protect them. It will readily be appreciated that the pull-down device 24 holds the gate of the auxiliary pass transistor 20 low when the auxiliary control transistor 22 is off. The auxiliary pass transistor 20 is shown with its source/drain channel connected in parallel with that of the pass gate p-channel transistor 10, between the first input terminal and the gate of the pull-up transistor 2. However, it will readily be appreciated from the foregoing discussion that the auxiliary pass transistor 20 could instead have its voltage node 32 connected to a potential of the order of Vdd to satisfy the protection requirements when the off-chip driver circuit is disabled and is in a tristate mode as discussed above. However, the circuit must also function in a conventional off-chip driver mode, where input signals are applied to the first and second input terminals from a pre-driver circuit. In this mode, the circuit operates substantially as described already with reference to Figure 1. That is, with a logical one (about 3.3V±0.3V) the first and second input terminals IN,IN' the p-channel transistor 2 is turned off and the output terminal OUT is pulled down to zero by the n-channel transistors 30 and 34. With a logical zero (0V) on the input terminal IN,IN', the n-channel pass transistor 8 presents 0V to the gate of the p-channel transistor 2, thus turning it on. The output terminal OUT is therefore pulled up to Vdd. In the first case (of a logical one being input), the auxiliary pass transistor 20 is on and therefore acts in parallel with the pass gate transistor 10, although it is substantially redundant. For this situation, it is of course important that the voltage at voltage node 32 is at the same logical value to that at the first input terminal IN. In a second situation, of a logical zero at the first input terminal, the control transistor 22 is still off because the voltage Vdd does not exceed the control voltage Vref by an adequate amount to turn it on, so that the auxiliary pass transistor 20 is on. In this situation however the pass transistor 20 must act with the n-channel transistor 8 to pass 0V to the gate of pull-up transistor 2. Therefore, the voltage node 32 in this situation needs to be connected to the logical equivalent of 0V. These logical requirements are ideally satisfied by connecting the voltage node 32 to the first input terminal IN. It will nevertheless be appreciated however that the invention could be implemented by connecting the voltage node 32 of the auxiliary pass transistor 20 to logic circuitry coupled to the first input terminal IN to satisfy these logical requirements. The described embodiment of the present invention thus provides an off-chip driver circuit which can tolerate excessive voltages in its disabled mode. All source to drain voltages on output transistors are limited so as not to exceed Vdd and all gate to drain/souce/bulk voltages are limited. Furthermore, input leakage during a disabled or tristate mode cna be limited to below about 30 microamps in the preferred embodiment and to below 10 microamps when driven by signals in the 0 to Vdd range.

Claims: An off-chip driver circuit having an input terminal (IN) and an output terminal (OUT) : a pull-up transistor (2) having a controllable path connected between a first power supply voltage (Vdd) and the output terminal (OUT) of the off-chip driver circuit and a control terminal connected to the input terminal (IN) via a pass gate connected to isolate the input terminal from high voltages applied to the output terminal (OUT) ; a control transistor (12) having a controllable path connected between the control terminal of the pull-up transistor (2) and the output terminal (OUT) and a control terminal connected to a control potential (Vref); an auxiliary pass transistor (20) having a control terminal and a controllable path connected between the control terminal of the pull-up transistor (2) and a voltage node which is at the same logical value as the said input terminal (IN); an auxiliary control transistor (22), the auxiliary control transistor (22) having a control terminal connected to receive said control potential (Vref) and a controllable path connected between the output terminal (OUT) and the control terminal of the auxiliary pass transistor (20); auxiliary circuitry (24) for holding the control terminal of the auxiliary pass transistor (20) in a state determined by the auxiliary control transistor (22); and the pass gate including an isolation transistor (10) connected between the input terminal (IN) and the control terminal of the pull-up transistor (2) and a control terminal connected to the output terminal (OUT). A driver circuit according to claim 1, wherein said auxiliary circuitry (24) comprises an auxiliary pull-down transistor (26,28) having a controllable path connected between the control terminal of the auxiliary pass transistor (20) and a reference potential (Vss), and a control terminal connected to a voltage selected to maintain said pull-down transistor on. A driver circuit according to claim 1, wherein the auxiliary circuitry (24) comprises first (26) and second (28) auxiliary pull-down transistors connected in series between the control terminal of the auxiliary pass transistor (20) and a reference potential (Vss), said auxiliary pull-down transistors (26,28) having control terminals connected respectively to the first power supply voltage and a voltage selected to maintain the auxiliary pull-down transistor on. A driver circuit according to any preceding claim, wherein said voltage node (32) of said auxiliary pass transistor (20) is connected directly to said input terminal (IN). A driver circuit according to any preceding claim, which further comprises a main pull-down transistor (4) connected in series between said pull-up transistor (2) and a reference potential (Vss), the control terminal of said main pull-down transistor (4) being connected to a second input terminal (IN') of the driver circuit. A driver circuit according to claim 1, wherein the pull-up transistor (2), control transistor (12), auxiliary pass transistor (20) and auxiliary control transistor (22) are p-channel transistors formed in a common n-well, said driver circuit including a further p-channel transistor (14) for biasing said n-well and having a control terminal coupled to said output terminal (OUT). A driver circuit according to claim 1, wherein the isolation transistor (10) is of a first conductivity type and the pass gate further comprises a transistor (8) of a second conductivity type in parallel with said transistor (10) of said first conductivity type and having a control terminal connected to the first power supply voltage (Vdd).

Inventors: DICKY CURTIS, MONK TREVOR, DICKY, CURTIS, MONK, TREVOR
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS LIMITED
Application year: 1995
Main classification: H03K19
IPC codes: H03K19