Active matrix display device with precharging circuit and its driving method

Abstract: To restrict an oscillation in potential of a video line, caused by a high speed sampling rate, the active matrix display device is comprised of gate lines X in row, signal lines Y in column and liquid crystal pixels LC of matrix arranged at each of the crossing points of both lines. The V driver 1 scans in line sequence each of the gate lines X and selects the liquid crystal pixels LC in one row for every respective one horizontal period. The H driver 2 performs, in sequence, samplings of the video signal VSIG within one horizontal scanning period at each of the signal lines Y and performs a writing of the video signal VSIG by dot sequential scanning to the liquid crystal pixels LC in a respective selected row. The precharging means 4 supplies in sequence a predetermined precharging signal VPS prior to the sequential sampling of the video signal VSIG for each of the signal lines Y. This precharging means 4 is comprised of a plurality of switching elements PSW connected to an end part of each of the signal lines Y, and of a P driver 5 for supplying the precharge signal VPS to each of the signal lines Y through sequential controlling of ON or OFF of each of the switching elements PSW.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to an active matrix display device and its driving method. More particularly, this invention relates to a technology for countering oscillation in the potential of a video line in a spot sequential driving operation. Description of Related Art Referring now to Fig. 8, a configuration of the prior art active matrix display device will be described in brief. The active matrix display device is comprised of gate lines X constituting rows, signal lines Y constituting columns and liquid crystal pixels LC in a matrix arranged at crossing points of the gate and signal lines. Each of the liquid crystal pixels LC is driven by a thin film transistor Tr. V driver (a vertical scanning circuit) 101 performs a line sequential scanning of each of the gate lines X and selects the liquid crystal pixels LC on one row for every one horizontal period (1H). The H driver (a horizontal scanning circuit) 102 samples in sequence the video signals VSIG of one video line within 1H at each of the signal lines Y and writes the video signals VSIG in the liquid crystal pixels LC in one selected row in spot sequence. More practically, each of the signal lines Y is connected to the video line through a respective horizontal switch HSW, receives a supplying of the video signal VSIG from the signal driver 103 and in turn the H driver 102 outputs horizontal sampling pulses  H1 ,  H2 ,  H3 ,...  HN in sequence and controls ON or OFF of each of the horizontal switches HSW. Fig. 9 represents waveforms of sampling pulses. As the active matrix display device is made to be highly accurate in operation, the sampling rate is made fast and the sampling pulse width τ H becomes disturbed. As the sampling pulse is outputted, its corresponding horizontal switch HSW is turned on or off and the video signal VSIG from the video line is sampled held in the corresponding signal line Y. Each of the signal lines Y has a capacitor component and its charging or discharging is produced by the sampling of the video signal VSIG. As a result, the potential in the video line is varied. As described above, as the sampling rate is made fast, the sampling pulse width τ H is disturbed, so that a charging or discharging with respect to each of the signal lines Y is not constant and the potential of the video line is caused to oscillate. There occurs a problem that this state appears as a vertical fixed pattern and noticeably degrades the quality of the displayed video image. In the case of displaying in accordance with the normal NTSC Standards, the sampling rate is relatively low and shows a timing in which a next sampling pulse is raised after ending of the potential oscillation in the video line, so that a vertical fixed pattern does not appear due to no bad influence from the previous signal line. However, in the case of HDTV or a double-speed NTSC, the sampling rate is rapidly increased and an effective restriction of a potential oscillation in the video line is difficult to perform. The sampling pulse is in general generated by the H driver comprised of shift registers or the like constituted by thin film transistors (TFTs). Since a TFT has a lower mobility as compared with that of a monolithic silicon transistor and also has a higher disturbance in each of the physical constants, it is difficult to perform an accurate control over the sampling pulses generated by this circuit. In addition, a certain disturbance may occur in the ON resistance of the horizontal switch HSW in addition to the disturbance of the sampling pulse width. With such an arrangement as above, there occurs a variation in the charging or discharging characteristic of the signal line Y and the video line potential is caused to oscillate, so that this overlaps with the actual video signal VSIG, appears as a vertical line to cause a remarkable degradation in quality of the displayed video signal. SUMMARY OF THE INVENTION In view of the aforesaid technical problems found in the prior art, it is an object of the present invention to perform an effective restriction of an oscillation in the potential of the video line generated as the sampling rate is increased. In order to accomplish the aforesaid object, the present invention has provided an active matrix display device in accordance with that claimed in claim 1. More practically, the precharging means is comprised of a plurality of switching elements connected to each of the terminal ends of the respective signal lines and a control means for controlling in sequence ON or OFF of each of the switching elements and supplying a precharging signal to each of the signal lines. This control means is comprised of an additional horizontal scanning circuit separately installed from the horizontal scanning circuit, wherein each of the switching elements is controlled in sequence in its ON or OFF state. Alternatively, the control means may be constructed such that its output is distributed and each of the switching elements is controlled in sequence for its ON or OFF state. The precharging means supplies a precharging signal having a grey level with respect to the video signal varying between the white level and the black level, the precharging signal having the same polarity and the same waveform as those of the video signal. The present invention also includes a method for driving the active matrix display device as defined in claim 7. That is, the driving method in accordance with the present invention performs a vertical scanning for scanning linearly in sequence each of the gate lines and selecting pixels in a respective row for every one horizontal period, a horizontal scanning for sampling in sequence the video signals in one horizontal period at each of the signal lines and writing the video signals by dot sequential scanning in the pixels in the respective selected row, and a precharging for supplying in sequence a predetermined precharging signal to each of the signal lines prior to the sequential sampling of the video signals with respect to each of the signal lines. According to the present invention, the charging or discharging of each of the signal lines is almost completed with the precharging signal, and the charging or discharging in case of performing the sampling of the video signals is carried out such that it can occur using just the difference between the precharging level and the signal level. Accordingly, the potential oscillation in the video line for supplying the video signals is more restricted as compared with the prior art, as disclosed in Japanese Application 22-04718 in which the potential of a signal line is precharged with all signals being sample held in all signal lines to reduce the load of the switching element for impressing an image signal and to prevent the picture quality of a display image from being deteriorated. Accordingly, the vertical fixed pattern which degrades video quality can be eliminated. In particular, in the present invention, the precharged signals are sampled by so-called dot sequential scanning to each of the signal lines. As compared with the case where precharged signals are all sample held in all signal lines, the potential oscillation at the gate lines or power source line can be reduced. In addition, a lower driving capability of the precharging means can also give satisfactory performance. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram for showing the first preferred embodiment of the active matrix display device. Fig. 2 is a timing chart applied for illustrating an operation in the first preferred embodiment. Fig. 3 is a circuit diagram for showing the second preferred embodiment of the active matrix display device of the present invention. Fig. 4 is a timing chart applied for illustrating an operation of the second preferred embodiment. Fig. 5 is a circuit diagram for showing an example of practical configuration of the second preferred embodiment. Fig. 6 is a circuit diagram for showing another practical example of configuration of the second preferred embodiment. Fig. 7 is a timing chart applied for illustrating an operation of the configuration shown in Fig. 6. Fig. 8 is a circuit diagram for showing the configuration of the prior art active matrix display device. Fig. 9 is a waveform view applied for illustrating the problem of the Fig. 8 apparatus. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, the preferred embodiments of the present invention will be described in detail. Fig. 1 is a circuit diagram for showing the first preferred embodiment of the active matrix display device of the present invention. The active matrix display device is comprised of gate lines X constituting rows, signal lines Y constituting columns and liquid crystal pixels LC in a matrix arranged at each of the crossing points of the gate and signal lines. In this preferred embodiment, there are provided pixels LC utilizing liquid crystal as the electro-photo substance. However, the present invention is not limited to this embodiment, but other electro-optical substances may be utilized. There are provided thin film transistors Tr for use in driving each of the liquid crystal pixels LC. The source electrode of the thin film transistor Tr is connected to the corresponding signal line Y, the gate electrode is connected to the corresponding gate line X and the drain electrode is connected to the corresponding liquid crystal pixel LC. There is provided a V driver 1 so as to constitute the vertical scanning circuit, and each of the gate lines X is scanned in line at a time and the liquid crystal pixels LC in one row are selected for a respective one horizontal period. More practically, the V driver 1 transfers the vertical start signal VST in sequence in synchronism with the vertical clock signal VCK and outputs the selection pulses  V1 ,  V2 , ...  VM to each of the gate lines X. With such an arrangement as above, the thin film transistor Tr is controlled in its ON or OFF state. In addition, there is provided a H driver 2 so as to constitute the horizontal scanning circuit in which the video signals VSIG are sampled in sequence at each of the signal lines in one horizontal period and the video signals VSIG are written by dot sequential scanning to the liquid crystals LC of a respective selected row. More practically, one end of each of the signal lines Y is provided with horizontal switching elements HSW1, HSW2, HSW3, HSW4, ... HSWN, each connected to the video line 3 so as to receive the video signals VSIG. In turn, the H driver 2 transfers in sequence the horizontal start signal HST in synchronism with the predetermined horizontal clock signal HCK and outputs the sampling pulses  H1 ,  H2 ,  H3 ,  H4 ··· HN . These sampling pulses control ON or OFF of the corresponding horizontal switching elements and sample hold the video signals VSIG at each of the signal lines Y. As a feature of the present invention, there is provided a precharging means 4, a predetermined precharging signal VPS is supplied in sequence to each of the signal lines Y prior to the sequential sampling of the video signal VSIG with respect to each of the signal lines Y, and thus a charging or a discharging of each of the signal lines Y through sampling is restricted. With such an arrangement as above, a smaller potential oscillation of the video line 3 occurs. More practically, the precharging means 4 has additional switching elements PSW1, PSW2, PSW3, PSW4, ... connected to the terminal end of each of the signal lines Y. In addition, there is provided a P driver 5 so as to constitute a control means for controlling in sequence ON or OFF of the additional switching elements PSW and supplying the precharging signal VPS to each of the signal lines Y. More practically, the P driver 5 has a similar configuration to that of the H driver 2, wherein the horizontal start signal PST is transferred in sequence in synchronism with the horizontal clock signal PCK, and then precharging sampling pulses  P1 ,  P2 ,  P3 ,  P4 , ...  PN are outputted. The additional horizontal switching elements PSW are controlled in sequence for their ON or OFF state in response to these precharging sampling pulses. In this first preferred embodiment, the control means is comprised of a horizontal scanning circuit having an additional P driver 5 separate from the H driver 2, wherein each of the switching elements PSW is controlled in its ON or OFF state in sequence. In addition, the horizontal scanning circuit such as the H driver 2 or the P driver 5 has as its basic configuration shift registers, wherein either thin film transistors or monolithic silicon transistors are integrated. The switching element HSW for the video signal sampling or the switching element PSW for the precharging signal sampling can be constructed by NMOS, PMOS and CMOS. In the preferred embodiment, although the H driver 2 and the P driver 5 are separately arranged at both ends of the signal line Y, the H driver 2 and the P driver 5 may be integrated at the same side. In this case, the horizontal switches HSW and PSW are also arranged at one end of the signal line Y. Now, referring to Fig. 2, operation of the active matrix display device shown in Fig. 1 will be described in detail. As described above, the P driver 5 transfers in sequence the start signal PST in synchronism with the horizontal clock signal PCK and outputs the precharging sampling pulses  P1 ,  P2 ,  P3 , and  P4 . Similarly, the H driver 2 also transfers the horizontal start signals HST in synchronism with the horizontal clock signal HCK and outputs the sampling pulses  H1 ,  H2 , and  H3 . In this preferred embodiment, as the signals HCK and PCK, the same horizontal clock signals are used. In turn, the horizontal start signal is operated such that its PST occurs first and then its HST occurs. With such an arrangement as above, the sampling pulse for the precharging signal is always in advance only by 1 sampling timing as compared with the sampling for the video signal. The video signal VSIG is supplied to the H driver 2 and a precharging signal VPS is supplied to the P driver 5. As shown in the timing chart of Fig. 2, the video signal VSIG has a waveform varying between a white level and a black level. In turn, the precharging signal VPS has a specified potential of a grey level. In the light of this situation, the precharging signal VPS having the same polarity and the same waveform as the video signal VSIG may be used. Applying the same waveform in VSIG and VPS reduces remarkably a charging or discharging amount at the signal line and the potential oscillation at the video line 3 can be effectively restricted. However, in the case where the same waveform is used in VSIG and VPS, the signal should not be branched from a common video driver, it is necessary to prepare a respective separate signal source. In turn, in the case where the specified voltage waveform of grey level is used as the precharging signal, a slight charging or discharging is produced at the sampling time of the video signal, although the charging or discharging amount of the signal line can still be remarkably reduced as compared with the case in which the video signal has an opposite polarity such as in the case of 1H reversing driving operation. At the lowest stage of the timing chart shown in Fig. 2 are expressed variations of potentials VY1, VY2 and VY3 of each of three signal lines Y1, Y2 and Y3. Taking account of the initial signal line Y1 shows that  P1 is outputted before  H1 is outputted, so that at first the precharging level is sampled at the signal line Y1 and then the video signal level is sampled. This operation is performed in sequence to the second and subsequent signal lines to enable a high quality displaying having no vertical stripe to be attained. In the present invention, the charging or discharging at Y1, Y2, Y3 .... is almost finished by the precharging signal VPS and the charging or discharging with VSIG is produced only by the difference between the precharging level and the video signal level. At this time, the precharging signal VPS is sampled by so-called dot sequential scanning of each of the signal lines Y. Merits of this system consist in the fact that the precharging signal VPS is sample held at all signal lines, resulting in that the gate line X and the power source line are not oscillated. Since the load capacity as viewed from the line of the precharging signal VPS is reduced, as is a resistance in the precharging signal line, a size of the added switching element PSW and a driving capability of the P driver and the like can be reduced. In the preferred embodiments, although the vertical scanning circuit is constructed to output selection pulses to gate lines in such a manner that each of the gate lines is scanned in sequence in a linear way and some pixels in one row are selected for every respective horizontal period, it may also be applicable that the pixels in two or more rows are concurrently selected. Fig. 3 is a circuit diagram for showing the second preferred embodiment of the active matrix display device of the present invention. Basically,the second preferred embodiment has the similar configuration to that of the first preferred embodiment shown in Fig. 1, wherein the corresponding reference numerals are used for the corresponding portions and their understanding is facilitated. In this second preferred embodiment, one end of each of the signal lines Y is provided with the sampling switching element HSW for the video signal VSIG and the sampling switching element PSW for the precharging signal VPS. These switching elements HSW and PSW are commonly controlled by the H driver 2 for their ON or OFF state. That is, the second preferred embodiment is different from the previous preferred embodiment, in that the P driver used in the sampling hold of the precharging signal VPS is eliminated, and thus its configuration is made more simple. A sampling pulse D outputted from each of the stages of the H driver 2 is applied for use in controlling ON or OFF of HSW corresponding to each of the stages and concurrently it performs a control over ON or OFF of the PSW belonging to the next stage. In other words, the control means is assembled in the horizontal scanning circuit, its sampling pulse output is properly distributed to control in sequence ON or OFF of each of the switching elements HSW, PSW. Referring now to the timing chart shown in Fig. 4, operation of the second preferred embodiment shown in Fig. 3 will be described in detail. At first, as the H driver 2 outputs the first sampling pulse D1, PSW1 is controlled for its ON or OFF state. Subsequently, as the second sampling pulse D2 is outputted, HSW1 and PSW2 are concurrently controlled for their ON or OFF state. As apparent from these facts, considering the first signal line Y1, PSW1 is first driven for its ON or OFF state, thereafter HSW1 is driven for its ON or OFF state. In addition, as the third sampling pulse D3 is outputted, HSW2 and PSW3 are concurrently driven for their ON or OFF state. Lastly, as DN is outputted, HSWN-1 and PSWN are concurrently driven for their ON or OFF state and, as DN+1 is outputted, HSWN is driven for its ON or OFF state. The video signal VSIG supplied from the video line 3 and the precharging signal VPS supplied from the precharging line 6 are sampling held at each of the signal lines Y in response to the driving for ON or OFF state of these switching elements HSW and PSW. For example, taking into account the potential VY1 appearing at the first signal line causes VPS to be sampling held during a precharging period in which PSW1 is made to be ON and subsequently VSIG is sampled for a video writing period in which HSW1 becomes ON. In addition, taking into account the potential VY2 appearing at the second signal line causes the precharging level to be written at a timing of making PSW2 ON and then the video signal level is written at a timing in which HSW2 subsequently becomes ON. As described above, in this preferred embodiment, the charging or discharging of the signal line Y is almost completed through the precharging line 6, the charging or discharging through the video line 3 merely corresponds to a difference between the precharging level (VPS) and the video signal level (VSIG), resulting in that the potential oscillation of the video line 3 can be reduced and the vertical fixed pattern can be improved. In the second preferred embodiment described above, although the sampling pulse for driving PSW is taken out from the immediately-preceding stage of the H driver 2, the present invention is not limited to such an operation. As long as the time band is one in which a polarity of the video signal is not changed, it is satisfactory that the sampling pulse can be taken from any earlier stages of the H driver 2. In the second preferred embodiment as described above, since the precharging is carried out by dot sequential scanning for each of the signal lines, no sub-effect on the video quality is seen as would be caused by writing of the precharging signal VPS to all lines at once. For example, if the precharging signals are all sampling held for all signal lines at once, a potential at the gate signal is oscillated due to a capacitance coupling, resulting in that a leak of the video signals written into the liquid crystal pixels may occur to cause a shading or a lateral stripe to be generated. In the worst case, a lack of bright point may occur in the case of normal white mode due to a leakage of electrical load written into it. By way of contrast, according to the present invention not only potential oscillation at the gate lines can be restricted, but also no oscillation occurs at the power source line or the earth line and an operating margin is expanded. In addition, since the capacity as viewed from the precharging line 6 is less in its value, a design margin can be expanded. With such an arrangement as above, a high quality video can be obtained and a driving margin can be expanded. Fig. 5 is a circuit diagram for illustrating a practical example of the second preferred embodiment shown in Fig. 3. As shown in this figure, HSW and PSW are constructed as transmission gates in this implementation. In addition, the H driver 2 is comprised of an H shift register 7 and an output gate 8 connected to each of the stages. The output gate 8 forms the sampling pulse and its reversing pulse in response to the output of the H shift register 7 so as to drive for ON or OFF of each HSW and PSW. As described above, the sampling pulse applied to PSW is supplied from one stage before in the H shift register 7, so that the point sequential sampling hold of the precharging signal VPS is carried out prior to the point sequential sampling of the video signal VSG. Fig. 6 shows a modified form of the implementation shown in Fig. 5, wherein some corresponding reference numerals are applied to the corresponding portions so as to facilitate understanding. The basic configuration is similar to that of the implementation shown in Fig. 5. The different points are that the sampling pulse to be applied to PSW is not from the immediately-preceding stage, but supplied from the H shift register 7 section two stages before. In general, if there is a time in which polarities of VSIG and VPS are not reversed, the sampling pulse applied to PSW may be taken from any earlier stages of the H shift register. Lastly, referring now to Fig. 7, operation of the implementation shown in Fig. 6 will be described in detail. As described above, the sampling pulses D1, D2, D3, D4, ... DN are outputted in sequence from the H register 7 through the output gates 8. When D1 is outputted, PSW1 is turned ON. Then, when D2 is outputted, PSW2 is turned ON. Subsequently, when D3 is outputted, PSW3 and HSW1 are turned ON. In addition, when D4 is outputted, PSW4 and HSW2 are turned ON. Lastly, when DN is outputted, PSWN and HSWN-2 are turned ON, when DN+1 is outputted, HSWN-1 is turned ON, and when DN+2 is outputted, HSWN is turned ON. In turn, VSIG has a waveform in which the signal level is changed in response to a video signal. In the preferred embodiment described above, since 1H reversing driving is carried out, its polarity is reversed for every 1H. In compliance with this operation, VPS having a predetermined precharging level is also reversed for every 1H. Taking into account the potential VY1 appearing at the first signal line shows that a precharging level is written for a precharging period in which D1 is outputted and PSW1 is turned ON. Subsequently, after 1 sampling timing has elapsed, the signal level is sampling held during a period of writing the actual video signal in which HSW1 is turned ON in response to the output of D3. In this case, a charging or a discharging amount of the first signal line becomes a difference between the precharging level and the signal level and it can be restricted to a low quantity. In particular, the aforesaid difference is almost eliminated in the case that the same waveform as that of the video signal VSIG is used as the precharging signal PS. Then, taking into account the potential VY2 appearing at the second signal line shows that the precharging level is written during a precharging period in which PSW2 is turned ON in response to D2, and the signal level is sampling held during an actual video signal writing period in which HSW2 is turned ON in response to D4 1 sampling timing later. The potential VY3 appearing at the third signal line is also similarly produced, etc.. As described above, according to the present invention, predetermined precharging signals are supplied in sequence prior to the sequential sampling of the video signals for each of the signal lines so as to restrict the charging or discharging of each of the signal lines through the sampling. With such an arrangement, since the potential oscillation in the video line (noise) is substantially reduced, it has an effect that the vertical fixed pattern can be removed from the displayed image. Since the precharging is carried out by dot sequential scanning, rather than simultaneous precharging of signal lines, the shooting or lateral stripe pattern can be restricted and similarly the image quality can be improved. For similar reasons, according to the invention an operating margin can be expanded and potential oscillation at the power source line or the earth line is not found. Since the vertical fixed pattern can be removed by the pre-charging, the present invention renders it less necessary to consider the problem of minute disturbance of the sampling pulse width and that a design margin of the horizontal scanning circuit is expanded. For a similar reason, the power source voltage can be reduced and the power consumption can be reduced.

Claims: An active matrix display device comprising: a plurality of gate lines (X) arranged in row; a plurality of signal lines (Y) arranged in column; pixels arranged at each of crossing points of said gate lines and signal lines; a vertical scanning circuit (1) for scanning each of the gate lines in sequence and selecting pixels of at least one row; a horizontal scanning circuit (2) for sampling video signals in sequence and writing the video signals in sequence in the pixels in the selected row(s); a precharging circuit (4) for supplying precharging signals to each of the signal lines, characterised in that said precharging circuit (4) sequentially supplies the precharging signals in sequence to each of the signal lines prior to a sequential sampling of video signals at each of the signal lines, and in that said precharging signals have the same polarity as that of the video signal and have a specified potential of a grey level in respect to a video signal varying between a white level and a black level. An active matrix display device according to claim 1 in which said precharging circuit (4) is comprised of: switching elements (PSW) connected to an end part of each of the signal lines; and a control circuit (5) for controlling the switching elements and supplying a precharging signal to each of the signal lines. An active matrix display device according to claim 2 in which said control circuit (5) is an additional horizontal scanning circuit arranged independently from said horizontal scanning circuit (2). An active matrix display device according to claim 2 in which said control circuit is assembled in said horizontal scanning circuit (2), distributes its output, and controls each of the switching elements (PSW) in sequence for its ON or OFF state. An active matrix display device according to claim 1 in which said precharging circuit (4) is arranged in opposition to said horizontal scanning circuit (2). An active matrix display device according to claim 1 in which said precharging circuit (4) is arranged at the same side as that of said horizontal scanning circuit (2). A method of driving an active matrix device comprising gate lines (X) arranged in row, a plurality of signal lines (Y) arranged in column, and pixels arranged at the crossing parts between said gate lines and signal lines, comprising the following steps of: line scanning in sequence of each of the gate lines and selecting pixels for at least one row; sampling in sequence the video signals and writing the video signals by dot sequential scanning to the pixels in the respective selected row(s); providing a precharging signal to each of the signal lines characterised in that said precharging signal is sequentially supplied in sequence to each of the signal lines prior to a sequential sampling of the video signal for each of the signal lines, and in that said precharging signal is a signal having the same polarity as that of the video signal and having a specified potential of a grey level.

Inventors: MAEKAWA TOSHIKAZU, UCHINO KATSUHIDE, MAEKAWA, TOSHIKAZU, UCHINO, KATSUHIDE
Applicants: SONY CORP, SONY CORPORATION
Application year: 1995
Main classification: G09G3
IPC codes: G02F1, G09G3