A method and apparatus for detecting an input signal

Abstract: A low signal detection circuit (24) for use in an electronic tolling system which wakes up a receiver circuit associated with the tolling system based upon the type of signal received detects incoming RF signals and counts the rising and falling edges of the baseband signal and applies the counts to a threshold circuit (36) which will compare the number of counts to a predetermined value. If the number of counts falls within a predetermined range, then a signal present signal will be output from the wake-up circuit (24). A power management circuit (32) receives a clock signal from an oscillator (30) and provides a power signal which wakes up the detection circuitry for only a minimum predetermined period of time.

Description: This invention relates to a method and apparatus for detecting a predetermined input signal, for example a low current RF signal detection circuit for use in electronic tolling. As any seasoned traveller or commuter knows, toll roads, toll bridges and the like are a significant part of the highway transit system. In order to provide funds for the maintenance and upkeep of toll roads and bridges, users are required to pay a fee related to the use of these roads and bridges. Generally, at a toll area, a series of toll booths extend across a roadway, and users are obligated to pay the toll rate in order to pass. Alternately, in a toll road situation, travellers will receive toll cards at toll booths as they enter a toll area, and then will pay the required fee depending on the point of exit of the toll area. In either of these situations, the commuter is required to stop his or her vehicle either to receive the toll card or pay the toll fee. Sometimes, depending on traffic congestion, users must wait significant periods of time before arriving at the toll booths. As a result, toll road and toll bridge users are inconvenienced beyond that of the extraction of funds. In order to alleviate the inconvenience to the commuter, and reduce the expense of the tolling system, and thus hopefully the toll, it is known to use electronic tolling in which tolling booths, as well as the personnel required to operate them, are substantially eliminated. Electronic tolling is a process by which communications between a transponder associated with a vehicle and a roadside reader make a record of the vehicle operator's use of the toll road or toll bridge. In these types of systems, the roadside reader will continuously emit an RF signal which will be received by the transponder of the vehicle when the vehicle enters the tolling area. Upon receipt of the transmitted signal from the roadside reader, the transponder of the vehicle will emit an encoded signal to the roadside reader such that the roadside reader can identify the vehicle. Upon identification of the vehicle, the roadside reader will initiate a billing sequence. Different protocols for determining and billing the toll are known in the art. The transponder in the vehicle is battery powered, usually by a 3 volt lithium battery. As a result of this, it is important to attempt to limit the power drain on the vehicle transponder to times when the transponder is receiving a valid signal from the roadside reader in order to conserve battery life, and thus the need to replace the battery. For this reason, the vehicle transponders will generally include a signal detection circuit which monitors RF frequency signals, and when a valid tolling signal is present, cause power to be delivered to the transmitter and data analysis circuitry associated with the vehicle transponder. Figure 1 shows a prior art signal detection circuit 10 which is applicable to be used in a vehicle transponder (not shown) in order to wake-up subsequent data analysing circuitry and a transmitter (not shown) when a valid tolling signal is present. An antenna (not shown) associated with the vehicle transponder receives RF signals and applies the signals to a band pass filter (not shown). The detection circuit 10 receives the RF signals from the filter. The signals are rectified by a rectifying diode 12 such that the carrier is removed and only the modulation signals will reach a positive terminal of a comparator 14. A signal is applied to the comparator 14 on an input power line 16 from a data analyser circuit (not shown) at an intermittent rate in order to periodically power up the comparator 14. Typically, this rate is at about a 10% duty cycle of a clock signal associated with the data analysing circuit. The power signal is also applied as a DC bias through a resistor R1 along with the RF input signal to the positive terminal of the comparator 14. The power signal is further applied to a negative terminal of the comparator 14 through a resistor R2. A potentiometer 18 adjusts the sensitivity of the comparator 14. The sensitivity of the comparator 14 is generally set for a relatively strong signal level. A second diode 20 is provided to compensate for temperature differences, and is matched to the diode 12. A capacitor C1 is used as a by-pass filter. Once the voltage on the positive terminal of the comparator 14 falls below the voltage on the negative terminal of the comparator 14, a signal present signal is outputted from the comparator 14. Once the signal detection circuit 10 determines that a valid signal is present, the data analysing circuit will wake up and will receive the input from the positive terminal input of the comparator 14 in order to determine the tolling information. Although the detection circuit 10 offers a number of advantages for waking up the data analysing circuit of the transponder of the vehicle, it involves increased costs associated with providing matched diodes. A more serious problem involves the variability in turn on level over temperature and false wake-ups associated with the sensitivity requirements. If the potentiometer 18 is adjusted to increase the sensitivity too much, the circuit 10 may indicate a signal is present on noise or weak RF interference and drain the battery. Likewise, too low of a sensitivity may result in no detection when a valid roadside transponder message is being sent. Both of these factors affect the battery life of the vehicle transponder. EP 00 32 130 A discloses a signal detector circuit wherein an input signal is mixed with a local oscillator signal to produce beat difference frequency pulses which are input to a counter. The counter value indicates whether the frequency of interest is present at the input. The present invention seeks to provide an improved method and apparatus for detecting the presence of a predetermined signal. According to an aspect of the present invention, there is provided a signal detection circuit as specified in claim 1. According to another aspect of the present invention, there is provided a method of determining the presence of a predetermined input signal as specified in claim 10. Preferred embodiments can provide a signal detection circuit for use in electronic tolling systems which distinguishes between the desired RF transmission and other RF transmission in order to only wake up the data analysing circuitry when a valid signal is present. A preferred embodiment for use in a tolling system includes a low current RF signal detection circuit which provides a wake-up signal to a receiver and data analysing circuit depending on the known transmission features of an RF input signal. RF input signals are applied through a rectifying diode to a positive terminal of a comparator. The rectifying diode provides a baseband signal. An oscillator provides a clock signal to a power management circuit and to a counter circuit. The power management circuit intermittently applies power to the comparator, the counter circuit, and a threshold circuit at a five percent duty cycle of the oscillator. During the time the comparator receives the timing signal from the power management circuit, baseband data signals from the rectifying diode are combined with a bias signal and applied to the comparator to be amplified. The counter circuit counts either rising or falling edges of the baseband signal from the comparator and applies a count of this value to the threshold circuit. The threshold circuit compares the counts from the counter circuit to a predetermined range of counts in order to determine if the incoming RF signal falls within the range and is thus valid. Since RF signals in electronic tolling systems are Manchester encoded, it is possible to determine what the minimum and maximum frequency of the baseband signal will be so as to set the threshold counts to a desirable range. An embodiment of the present invention is described below, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a prior art schematic diagram of a signal detection circuit for use in an electronic tolling system; Figure 2 is a pair of waveforms showing the maximum and minimum frequencies for a Manchester encoded electronic tolling data signal; and Figure 3 is a schematic block diagram of an embodiment of low signal detection circuit. Roadside readers associated with current electronic tolling systems generally transmit a Manchester encoded RF data signal to be received by a receiver associated with a vehicle as it enters a tolling area. Manchester encoded data is a popular method of encoding data bits for transmission, well known to those skilled in art, in which a clock signal and the data bits are encoded on a single signal. A signal that is Manchester encoded is a square wave in which a falling mid-bit transition represents a "1" bit and a rising mid-bit transition represents a "0" bit. Manchester encoded electronic tolling signals from the Roadside reader will transmit RF data signals at 500 kilobits per second (kbps). Since the number of bits being transmitted is the same regardless of the bit values, the highest bit value that can be achieved under Manchester encoding is 111...1. This bit sequence results in a 500 kHz square waveform as shown by the top waveform of Figure 2. Likewise, the minimum bit value that can be achieved under Manchester encoding is 0101...01. This is a 250 kHz square wave as shown by the bottom waveform of Figure 2. As is apparent by viewing these waveforms, falling mid-bit transitions are shown as "1", rising mid-bit transitions are shown as "0", and the number of bits transmitted is the same. For the example of signal detection circuit 24 shown in Figure 3, RF signals are received by an antenna (not shown), sent through a band pass filter (not shown), and are applied as input signals to a detector diode 26 and associated resistor R1. Input signals are stripped of their carrier by the diode 26 and the detected signal is applied to the positive terminal of a comparator 28. A 32.768 kHz crystal oscillator 30 applies a clock output signal to a power management circuit (PMC) 32 and a counter circuit 34. The PMC 32 provides a power signal to the comparator 28 only at predetermined times during the clock cycle, as will be discussed below. The signal from the PMC 32 is also a DC bias voltage applied to the positive terminal of the comparator 28. Signals which pass the diode 26 are baseband signals which are combined with the DC bias voltage. An output of the comparator 28 is an amplified baseband signal which is applied to the counter circuit 34. During the appropriate clock times, as determined by the clock input signal to the counter circuit 34, the counter circuit 34 counts the rise or fall of the pulses in the baseband signal. An output of the number of counts from the counter circuit 34 is applied to a threshold circuit 36. The threshold circuit 36 compares the counts to a predetermined count range stored in the threshold circuit 36 in order to determine if a valid signal is present. If the number of counts is within the predetermined range, an output of the threshold circuit 36 will indicate a signal is present to the receiver circuit (not shown) in the same manner as the signal above with reference to the comparator 14 of Figure 1. In order to minimise power consumption, the proposed system operates at about a five percent duty cycle of the 32.768 kHz oscillator. In this regard, the system is powered on for two clock cycles, where each clock cycle is about 30.52 ms (microseconds). During the first clock cycle of the oscillator 30, the PMC 32 causes the comparator 28 and the counter circuit 34 to stabilise because one clock cycle does not give enough time for the circuit components to recover data. During the next clock cycle, the comparator 28 amplifies the signal at its input to complementary metal oxide semiconductor (CMOS) logic levels and the counter circuit 34 asynchronously counts the edges of pulses being output from the comparator 28. By this, the circuit 24 is on for a period of approximately 61.04 ms, and then is off for approximately 1.16 ms (milliseconds), where 6.04 is 5% of 1.22 ms. Every 1.22 ms the comparator will be analysing RF input signals for one clock cycle. If the threshold circuit 36 determines that a valid signal is present, the power management circuit 32 will maintain power to the positive terminal of the comparator 28 until the transaction between the vehicle transponder and the roadside reader is complete. Then the PMC 32 will return to a 5% duty cycle operation. The threshold circuit 36 compares the number of counts being output from the counter circuit 34 during the second clock cycle to determine whether a valid signal is present. The threshold range of the threshold circuit 36 is determined by the maximum and minimum counts given the range of clock tolerances and the circuit settling times. The maximum frequency of a valid incoming signal is set as 525 kHz. 525 kHz is the maximum expected Manchester encoded frequency, discussed above, plus a five percent error. The maximum count time is 30.55 ms. This is the five percent 30.52 ms of the frequency of the oscillator 30 plus a 0.1% error. Therefore, the maximum count value would be 16.04, which is then rounded up to 17. The minimum count value is based on the expected Manchester encoded minimum frequency. That value would be 250 kHz minus a five percent error or 237.5 kHz. The minimum count is 20.48 ms. This is 10 ms additional settling time and 32.768 kHz minus 0.1% clock error. This result is a minimum clock value of 4.86 which is then rounded down to 4. Therefore, if the counter circuit 34 determines a count from 4 to 17, then the output of the threshold circuit 36 will cause the receiver and data analysing circuit to wake up. The circuit 24 is much less susceptible to false wake-up signals because amplitude shift keying data must be present with a signal spectral content between 131 kHz and 830 kHz before the signal present signal is set. Most other communications in or near the 915 MHz band are a constant carrier, either binary phase shift keying or frequency shift keying for a system such as cellular telephones, automatic vehicle monitoring, spread spectrum, etc. Further, these communications do not switch on or off at the required high frequency data rate. Therefore, the probability of false wake-up can be reduced considerably if not eliminated entirely and the transponder in the vehicle will operate up to its rated battery life. RF level sensitivity of the circuit 24 is not critical since it is not based on received signal strength. All that is required is that the minimum level of sensitivity is met in order to guarantee the functionality of the counter circuit. The maximum sensitivity is not critical, and can be at any level. This fact eliminates the need for an adjustment and allows the circuit to eliminate the temperature effects. Quiescent current is reduced by using a 32 kHz low power oscillator, low power CMOS digital circuitry and a 5% duty cycle. The on time is 61.04 microseconds resulting in a fast signal detection time (less than 1.22 milliseconds). The fast detection time provides tolling system advantage by increasing the time the strength tag is communicating in the reader zone and this results in more system throughput. It is to be understood that any range or any specific device value given herein can be varied without losing the effects sought, as will be apparent to the skilled person. The disclosures in United States patent application no. 08/208,177, from which this application claims priority and in the abstract,accompanying this application are relevant to the present subject-matter.

Claims: A signal detection circuit for indicating the presence of a predetermined input signal, said signal detection circuit comprising a comparator (28) coupled to a circuit input and operative to receive via a detector means an input signal at the circuit input and to generate an amplified output baseband signal; a counter circuit (34) coupled to the comparator output and operative to count the number of predetermined edges of the amplified output baseband signal; and a threshold circuit (36) coupled to the counter circuit and operative to compare the number of edges counted by the counter circuit during a predetermined time period to a threshold range of counts stored in said threshold circuit and to determine therefrom whether a valid signal is present. A signal detection circuit according to claim 1, comprising a diode (26) coupled between the comparator and the circuit input and operative to detect the input signal. A signal detection circuit according to claim 1 or 2, comprising an oscillator (30) coupled to the counter circuit for providing a clock signal therefor. A signal detection circuit according to claim 3, wherein the oscillator (30) is a 32.768 kHz crystal oscillator. A signal detection circuit according to claim 3 or 4, comprising a power management circuit (32) coupled to the oscillator and the comparator and operative to output a power signal to the comparator at predetermined intervals. A signal detection circuit according to claim 5, wherein the power management circuit (32) is operative to feed a power signal to the comparator at approximately a 5% duty cycle of the oscillator. A signal detection circuit according to claim 5 or 6, wherein the power management circuit is operative to apply a power signal to the comparator for approximately 61.1 microseconds approximately every 1.22 milliseconds. A signal detection circuit according to any preceding claim, wherein the threshold range of counts is from 4 to 17 counts. A transponder for an electronic tolling system comprising a signal detection circuit according to any preceding claim, the threshold circuit being operative to output a signal present indication to circuitry of the transponder. A method of determining the presence of a predetermined input signal comprising the steps of applying input signals via a detector means to a comparator so as to generate an amplified output baseband signal from the comparator; counting predetermined edges of the amplified output baseband signal; and comparing the number of edges counted during a predetermined time period to a threshold range of counts; and determining that the predetermined input signal is present when the number of edges counted falls within the threshold range. A method according to claim 10, comprising the step of providing a power signal to the comparator at a predetermined interval. A method according to claim 11, wherein the power signal is generated at approximately a five percent duty cycle of a clock signal. A method according to claim 12, wherein the power signal is generated for approximately 61.1 microseconds every 1.22 milliseconds and the clock signal oscillates at approximately 32.768 kHz. A method according to any one of claims 10 to 13, wherein the predetermined input signal is determined to be present when the number of edges counted falls within a range of 4 to 17 counts. A method according to any one of claims 10 to 14, wherein the input signals include a carrier modulated signal, the method including the step of detecting a modulation envelope of the carrier modulated signal and inputting the modulation envelope to the comparator.

Inventors: KADY MARK A, WENOS VINCENT MICHAEL, KADY, MARK A., WENOS, VINCENT MICHAEL
Applicants: DELPHI TECH INC, DELPHI TECHNOLOGIES, INC.
Application year: 1995
Main classification: G01R23
IPC codes: H04B1, G06K19, G07B15