REVERSE CURRENT PREVENTION CIRCUITS

Abstract: A reverse current limited regulator for coupling an input node (NODE A) and an output node (NODE B) for limiting a reverse current through a pass transistor (P1) which connects the input and output nodes. The regulator comprises a voltage comparator (N1, N2, R1) which compares the voltages at the input and output nodes and biasing circuitry (P4, P5) which is controlled by the outputs of the comparator to bias the substrate of the pass transistor with one of the two voltages.

Description: REVERSE CURRENT PREVENTION CIRCUITS BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of power supply circuits, low dropout regulators, linear regulators, pass elements and the like wherein protection of electrical components is required when the output voltage is greater than the input voltage. 2. Prior Art Although there are many MOS and CMOS linear voltage regulators currently available in monolithic form, none of these regulators is protected against the situation where the output voltage can be greater than the input voltage. Although there are many applications where this is not a concern, new multiple powered systems using batteries and line operated power sources require that the system voltage (s) be maintained under discharge, failure or turn-off of one or possibly more of the input power supplies. This means that if an input power supply is connected to a system through a linear regulator having a MOS pass element, reverse current could flow through the pass element from the output of the linear regulator to the input power supply. At the least, this is undesirable since it wastes power and at the worst, if the reverse current is high, component or system damage may result. Although this discussion will use the linear regulator as an example, the invention is not limited to linear regulators since there are other regulator topologies such as buck switching regulators that could benefit from the invention. To date the most popular monolithic linear voltage regulators have been fabricated using bipolar semiconductor technologies where the reverse characteristics (reverse current gain etc.) of a pass transistor are generally much inferior to the forward characteristics. Consequently, for a given base current, the reverse collector current would be a couple of orders of magnitude less than the forward collector current. In addition, most bipolar regulators detect when the pass transistor goes into saturation and automatically reduce the base drive current. The result of this is that, although reverse current may flow, it is often of a relatively low value and, for most applications, is not a problem. BRIEF SUMMARY OF THE INVENTION The present invention discloses a reverse current limited circuit for coupling between first and second terminals for providing a reverse current limited low dropout output having an MOS pass transistor coupled in series between the first and second terminals, means for connecting the substrate of the MOS pass transistor to either one of the first terminal and the second terminal based on the relative magnitudes of the voltages of the first and second terminals, means for turning on and off the MOS pass transistor based on the relative magnitudes of the voltages of the first and second terminals, and means for comparing the voltages of the first and second terminals and controlling the means for turning on and off the MOS pass transistor and the means for connecting the substrate of the MOS pass transistor to either of the first and second terminals. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A is a cross sectional view of a PMOS transistor. Figure IB is a symbol of a PMOS transistor. Figure 1C is a cross sectional view of an NMOS transistor. Figure ID is a symbol of an NMOS transistor. Figure 2A presents a symbol of a PMOS transistor having the source and the substrate of the PMOS transistor being tied together and showing a parasitic diode at the junction of the drain and the substrate of the PMOS transistor. Figure 2B presents typical I-V characteristics of a PMOS transistor. Figure 2C presents a symbol of an NMOS transistor having the source and the substrate of the NMOS tranεistor being tied together and showing a parasitic diode at the junction of the drain and the substrate of the NMOS transistor. Figure 2D is typical I-V characteristics of an NMOS transistor. Figure 3 presents a simple substrate snatcher circuit for MOS transistors connected to varying supply terminals . Figure 4 is a block schematic of a practical implementation of a low dropout regulator incorporating the substrate snatcher circuit of Figure 3 and a medium precision polarity detector circuit in accordance with the present invention. Figure 5 is a circuit diagram for the regulator circuit of Figure 4 with an improved precision polarity detector circuit. Figure 6 is a circuit diagram for the regulator circuit of Figure 5 with a hysteresis circuit. Figure 7 is the effect of a hysteresis circuit in Figure 6. Figure 8 is a block schematic of a practical implementation of a low dropout negative series regulator incorporating an NMOS substrate snatcher circuit and a medium precision polarity detector circuit in accordance with the present invention. DETAILED DESCRIPTION OF THE INVENTION The invention relates to linear voltage regulators that use MOS pass transistors. In general, these will be fabricated using silicon monolithic processes whereby most, if not all components, will be integrated together on a single chip. There will be occasions where total integration will not be used. For example, in high power applications, the pass transistor may be a discrete transistor separate from the control circuitry which usually takes the form of an IC, and the discrete transistor has its substrate as a separate terminal instead of being connected to its source. The essence of the invention is 1) to detect whether the output node voltage of a regulator is higher than the input node voltage of the regulator, 2) if so, to turn off a pass transistor, which couples the input and the output nodes of the regulator, by turning off its gate, 3) to connect the substrate terminal of the pass transistor to the output node of the regulator and 4) if relevant, to connect the substrates of PMOS transistors and components of the control circuitry to the output node of the regulator. This type of linear regulator is called a positive series regulator. The invention applies also to negative series regulators where the input voltage polarity is reversed and where an NMOS pass transistor (Nl) would be used as shown in Figure 8. The detailed operation of the circuit will be discussed later in this section. An MOS transistor is a four terminal device having a source, a drain, an insulated gate and a substrate. Figure 1A shows a cross sectional view of a PMOS transistor. Because a drain 12 and a source 14 are the same in structure, they are interchangeable. Drain 12 and source 14 are P-type, while a substrate 10 is an N- type material. A PMOS transistor has two inherent diodes formed between drain 12 and substrate 10 and between source 14 and substrate 10. However, in many applications, because substrate 10 is connected to source 14, only one inherent diode exists between drain 12 and substrate 10. Figure IB shows a symbol of a PMOS transistor including a gate 20, a source 21, a substrate 22 and a drain 23. Because a source and a drain are interchangeable as stated above, if node 21 iε a drain, then node 23 is a source. Thus, it should be noted that for the discussions that follow and the claims, a drain and a source may be recited interchangeably. Figure IC presents a cross sectional view of an NMOS transistor. A substrate 30 is a P-type material while a drain 33 and a source 31 are N-type materials. Again, two inherent diodes are formed between drain 33 and substrate 30 and between source 31 and substrate 30. However, if substrate 30 is connected to source 31, then only one diode exists between drain 33 and substrate 30. Figure ID is a symbol of an NMOS transistor. Figure 2A presents a symbol of a PMOS transistor having a source 51 and a substrate 52 being tied together and showing a parasitic diode 54 at the junction of a drain 53 and substrate 52. Figure 2C presents a symbol of an NMOS transistor having a source 73 and a substrate 72 being tied together and showing a parasitic diode 74 at the junction of a drain 71 and substrate 72. During a normal operation, source 51 of the PMOS transistor is the most positively biased of either of drain 53 or source 51, while in an NMOS transistor, drain 71 is the most positively biased of either of drain 71 or source 73. In many applications, a substrate is connected to a source resulting in one parasitic pn diode such as 54 or 74 being placed between a drain and a source. Consequently, if the drain-to- source voltage is reversed, diode 54 or 74 becomes forward biased and conducts. Figure 2B shows the forward and reverse biased characteristics of a PMOS transistor. During a normal operation, VΓJS is negative. But when V DS is positive, as VQS becomes more negative, high drain current flows due to parasitic diode 54. Figure 2C shows similar I-V characteristics for an NMOS transistor. During a normal operation of a NMOS transistor, VDS is positive. But when Vrjs is negative, as VQ S becomes more positive, high drain current flows due to parasitic diode 74. If one desires to block current in the reverse direction which is drain-to-source current in a PMOS and source-to-drain current in an NMOS, two conditions must be met: 1) In a PMOS transistor, the source-to-gate voltage must be less than the absolute value of the turn-on voltage of the PMOS transistor. In an NMOS transistor, the gate-to-source voltage must be less than the turn-on voltage of the NMOS transistor. 2) The substrate must be connected either to the source or to a voltage similar to that of the source so as not to affect the turn-on voltage of a PMOS or an NMOS transistor. The invention uses a comparator to detect the biasing of a PMOS pass transistor coupled between the input and the output nodes of a regulator to determine whether the PMOS pass transistor is being used in the forward or reverse mode. The comparator connects the substrate of the PMOS pass transistor to either of the two terminals named drain and source (which ever is most positive) , and if the transistor is biased in the reverse mode, the source-to-gate voltage is forced to zero. Also if there are PMOS transistors on the chip containing the control circuitry of the linear regulator, their substrate(s) are also switched to the most positive of the input or output voltage. The above discussion applies equally to whether the PMOS pass transistor is contained on a chip or whether it is a separate discrete transistor. An extremely simple circuit is shown in Figure 3 for connecting a common substrate 80 of the three transistors PI*, P2* and P3* to the most positive of the terminals A 91 and B 92. If transistor PI* is assumed to be the pass transistor, P2* and P3* can aptly be called the substrate snatchers. If node A 91 is significantly more positive than node B 92 and is higher than the turn-on voltages of the PMOS transistors, transistor P2* will be turned on and will connect common substrate (s) 80 of all three transistors to node A 91. Similarly if node B 92 iε significantly more positive than node A 91, transiεtor P3* will be turned on, connecting the common substrate (s) 80 to node B 92 . The circuit works well if the voltage difference between nodes A 91 and B 92 iε greater than the turn-on voltage of the PMOS tranεiεtorε and also if the voltages on nodes A 91 and B 92 are low, but at least one of them is greater than the turn-on voltage of a PMOS transistor. This circuit is not adequate by itself for substrate control but complements other circuits because of its excellent low voltage performance and simplicity. A medium preciεion polarity detector iε εhown in Figure 4. The detector includes transistors Nl, N2, P8, P9 and P10. The detector is a conventional differential comparator whose outputs drive two substrate snatcher transistors P4 and P5 that connect common substrate (s) 108 for the PMOS transistors to either node A 100 or B 101. Additionally, the outputs from the comparator either connect the gate of PI to node B 101 through P6 (turning PI off) or when node A 100 is more positive than node B 101, to a dr ve 103 from the output of an error amplifier or other suitable driver. In more detail, the inputε from nodeε A 100 and B 101 drive the gateε of Nl and N2 of the firεt εtage of the differential comparator. The first stage iε self biasing such that the current in RI is defined as approximately the voltage on node A 100 less the turn-on voltage of Nl (taking into account the reverse bias of the substrate of Nl) divided by the value of RI. The output of the first stage of the comparator is taken from the drains of N2 anc. P9 and drives the gate of P10. The εecond stage consist.- of P10 and R2 and provideε an anti-phase signal to that of the first stage. These two output signalε drive the gateε of P4, P5, P6 and P7. Note that the common εubstrate node 108 supplieε the bias current for the comparator. Initially at power on, this current is supplied through the parasitic diodes being the inherent PN junctionε formed by the εubεtrate and sources of P4 and P5 (either Dl or D2 depending on whether node A 100 is higher than node B 101 or visa versa) and, in normal operation, through P4 or P5 whichever is on. The operation of a medium precision polarity detector shown in Figure 4 is described in detail below: when the voltage of node A 100 (VA) and the voltage of node B 101 (Vβ) are lesε than the turn-on voltage of Nl (VTi) and the turn-on voltage of Nl (VT2) reεpectively, common substrate terminal 108 is connected to node A 100. Because the gate-to-source voltage of Nl, VGSNI, and the gate-to-source voltage of N2, VGSN2, are less than VTi and VT2 respectively, tranεiεtorε Nl and N2 are off. Accordingly, transistorε P5, P6 and P10 will be off, and tranεiεtorε P4 and P7 whoεe gateε are connected to ground 105 through R2 will be on. Therefore, a gate control 103 for PI will control the gate of PI through P7, and common substrate terminal 108 will be connected to node A 100 through P4. When VA and Vβ are greater than VTi and VT2 respectively, and VA is greater than Vβ (normal operation) , common substrate terminal 108 is connected to node A 100. Initially, common substrate terminal 108 is connected to node A 100 through a parasitic diode Dl, but during normal operation, common εubstrate terminal 108 iε connected to node A 100 through the subεtrate snatcher transiεtor P4 aε described below. When transistors Nl, N2, P8 and P9 turn on, initially a current flows from node A 100 through Dl and splits into two branches. One branch follows through P8, Nl, RI and to ground 105 while the other branch goeε through P9, N2, RI and finally to ground 105. Since VGSN2 is lesε than VGSNI, the drain-to-εource voltage of N2 , VDSN2# tends to increase to maintain the same amount of current through N2 as through Nl. Because the source-to-gate voltage of P6, VSGpβ, which is VT2 - VDSN2 ' should be smaller than the turn-on voltage of P6, VTβ, transistor P6 will be off, disconnecting the pass transiεtor PI from node B 101. Transiεtorε P5 and P10, whoεe gateε are connected to the drain of N2, like the gate of P6, will be off for εimilar reasons. Since the gates of transiεtorε P4 and P7 are connected to ground 105 through R2, and P5 and P10 are off, P4 and P7 will be turned on. At thiε point, common εubstrate terminal 108 will be connected to node A 100 through P4, and PI will be controlled by gate control 103 through P7. On the other hand, when Vβ iε larger than VA, and V and Vβ are greater than VTi and VT2 respectively, common substrate terminal 108 is connected to node B 101. Initially, common subεtrate terminal 108 iε connected to node B 101 through D2 , but in normal operation, common substrate terminal 108 is connected to node B 101 through transistor P5. When transiεtors Nl, N2, P8 and P9 turn on, initially a current flows from node B 101 through D2 and splits into two branches. One branch continues through P8, Nl, RI and to ground 105 while the other branch goes through P9, N2, RI and finally to ground 105. Since VGSN2 i larger than VGSNI • VDSN2 tends to decrease to maintain the same amount of current through N2 as through Nl . Because the value VDSN2 small, VSGpδ, which is V 2 - VDSN2. should be larger than the turn-on voltage of P6, V 6, and conεequently tranεistor P6 will be on, connecting the gate of the pasε transistor PI to node B 101. Transiεtorε P5 and P10 will turn on for εimilar reasons. Now the current will flow from node B 101 through P5 and εplit at common substrate terminal 108 into three branches. One branch will continue through P8, Nl, RI and to ground 105. Another branch will continue through P9, N2 , RI and to ground 105, and the third branch will continue through P10, R2 and to ground 105. Since P5 and P10 are on, the drain voltage of P10 approximately equals Vβ, and thus, P4 and P7 whose gates are connected to the drain of P10 will be off. Since P7 is off, and P6 is on, the gate of PI is disconnected from gate control 103 and is connected to node B 101. Thuε, PI iε off, and common εubεtrate terminal 108 iε connected to node B 101 through P5. The relatively εimple circuit of Figure 4 is shown to demonstrate the invention and is obviously only one of many circuits that could provide the same function. Figure 5 showε an improved precision polarity detector which differs from the circuit shown in Figure 4 by replacing RI and R2 of Figure 4 by N3 ' and N4 ' , and by adding P2 ' and P3 ' to provide a more complex but improved bias scheme. R3 ' together with N5 ' set up a bias current which iε mirrored in N3 ' and N4 ' . This provides significantly more gain for the second stage of the comparator and subsequently more precise detection of which input--node A 110 or node B lll--iε higher in voltage. A further improvemei. iε εhown in Figure 6 which includeε a hyεtereεiε circuit for the comparator with modified input offset voltage. The hysteresiε circuit includeε tranεistors Pll ' ' and P12 ' ', and the input offset voltage is modified to provide a controlled input offεet voltage by having i.l ' ' with larger gate width-to- length ratio (W/L) than that of N2 ' ' . The reaεon for these two features is to compenεate for the natural deficiencies of the comparator in terms of its equivalent input noise voltage and the inherent mismatch of components which always results in a non zero input offset voltage for the comparator. The reason why a hysteresiε circuit is so desirable is that it prevents false outputs from the comparator when the difference in the applied input voltageε (nodes A 120 and B 121) iε of the same magnitude aε the equivalent input noiεe voltage of the comparator. Thiε effect iε εhown in Figure 7 where the hystereεiε voltage (VS1-VS2) iε greater than the input noiεe voltage. Similarly the high trip point of the comparator iε offεet by an amount equal or greater than the worεe case value of its offset voltage. Typically VS2 would be set about 15 millivolts from ideal matching and VS1 about 25 millivolts. The down side of this technique is that reverse current will flow in the pass tranεiεtor when the output iε higher than the input voltage by not more than about 25 millivolts. The closer the two trip points VS1 and VS2 are to ideal matching the better. Therefore, for best performance the design of the comparator should be optimized for low offset voltage and low noise. Figure 8 is a block εchematic of a practical implementation of a low dropout negative εerieε regulator incorporating an NMOS εubεtrate εnatcher circuit and a medium preciεion polarity detector circuit in accordance with the preεent invention. The circuit in Figure 8 iε similar in structure and function to that of Figure 4 except that (1) NMOS transistorε are replaced with PMOS transistors, (2) PMOS transiεtors are replaced with NMOS transistors, (3) input and output voltages at nodes 150 and 151 are lower than the voltage at 155, and (4) the circuit in Figure 8 is up-side-down with respect to the circuit in Figure 4. The circuit in Figure 4 has an NMOS pass transistor Nl ' " having a source, a drain, a gate and a substrate. When the voltage of an input 150 is less than the voltage of an output 151, a node 156 may be considered to be the source, and a node 157 can be considered to be the drain of Nl ' " . However, when the voltage of output 151 is lesε than the voltage of input 151, node 157 may be conεidered to be the εource, and node 156 may be viewed aε the drain of Nl ' " . Thuε, because a MOS transistor is bi-directional, a drain and a source are interchangeable. The drain and the source of Nl ' " are coupled in series between input 150 and output 151. NMOS transiεtorε N4 ' " and N5"' are used to connect the subεtrate of Nl ' " to either input 150 or output 151. When the voltage of input 150 iε lower than the voltage of output 151, the substrate of Nl ' " iε connected to input 150 through N4 ' " . When the voltage of output 151 is lower than the voltage of input 150, the substrate of Nl ' " is connected to output 151 through N5 ' " . NMOS transistors N7 ' " and N6 ' " are used to turn on or off Nl ' " baεed on the relative magnitudeε of the voltages of input 150 and output 151. When the voltage of input 150 is less than the voltage of output 151, N7 ' " is on, connecting Nl ' " to a gate drive 153. Gate drive 153 controls the gate of Nl ' " , turning on or off Nl ' " . When the voltage of output 151 is lesε than the voltage of input 150, N6 ' " is on, connecting Nl ' " to output 151 through N6 ' " . Since the gate of Nl ' " is connected to output 151 through N6 ' " and node 157 is also connected to output 151, Nl ' " iε off. Continuing to refer to Figure 8, a comparator conεiεting of PMOS transistorε PI'" and P2 ' " with NMOS transiεtors N8 ' " and N9"' iε connected to an inverter N10 ' " to compare the voltages of input 150 and output 151 and to control the gates of N4 ' " , N5 ' " , N6 ' " and N7 ' " . A reference voltage 155 may be ground or some other voltage level. When reference voltage is ground, input 150 and output 151 are negative values. When input 150 is less than output 151, the absolute value of the voltage of input 150 iε greater than the absolute value of the voltage of output 151. One should note that improvements similar to those shown in Figures 5 and 6 may be made to the circuit in Figure 8. Thus, while the present invention has been disclosed and described with reεpect to a certain preferred embodiment thereof, it will be underεtood to thoεe εkilled in the art that the preεent invention may be varied without departing from the spirit and scope of the invention.

Claims: AMENDED CLAIMS [received by the International Bureau on 28 August 1995 (28.08.95); original claims 1, 3-4, 6-14 and 16-21 amended; remaining claims unchanged (12 pages)] 1. A circuit for coupling between a first and a second terminals for providing a minimum reverse current low dropout voltage output comprising: a MOS paεs transistor having a source, a drain, a gate and a substrate, the source and the drain of the MOS pass transistor being coupled in series between the first terminal and the second terminal; connection means for connecting the substrate of the MOS pass transiεtor to either one of the first terminal and the second terminal baεed on relative magnitudeε of voltageε of the firεt terminal and the εecond terminal, the connection means coupled to the MOS pass tranεistor, to the first terminal and to the second terminal; εwitch meanε for controlling the gate of the MOS pass transiεtor based on the relative magnitudes of the voltageε of the firεt terminal and the second terminal, the switch means coupled to the MOS pasε tranεistor; and comparison and control means for (1) comparing the voltage of the firεt terminal and the voltage of the second terminal and for (2) controlling the connection meanε and the εwitch means, the comparison and control means coupled to the connection means, to the switch means, to the first terminal and to the second terminal. 2. The circuit of claim 1 wherein the MOS pass transistor iε a PMOS transistor, and the first terminal is a positive power supply terminal. 3. The circuit of claim 1 wherein the connection means includes: a first MOS transistor having a source, a drain, a gate and a substrate wherein the substrate and the drain of the first MOS transistor are both coupled to the substrate of the MOS pass transistor and the source of the first MOS transiεtor is coupled to the first terminal; and a second MOS transistor having a εource, a drain, a gate and a substrate wherein the substrate and the drain of the second MOS transistor are both coupled to the substrate of the MOS pasε tranεiεtor and the source of the firεt MOS tranεiεtor iε coupled to the εecond terminal. 4. The circuit of claim 3 wherein the switch means includes: a third MOS transiεtor having a εource, a drain, a gate and a εubεtrate wherein the εource of the third MOS tranεiεtor is coupled to a gate control circuit of the MOS pasε tranεiεtor, the εubstrate of the third MOS transistor is coupled to the substrate of the MOS pass transiεtor, and the drain of the third MOS transistor is coupled to the gate of the MOS pass transistor; and a fourth MOS transistor having a source, a drain, a gate and a substrate wherein the source of the fourth MOS tranεiεtor iε coupled to the gate of the MOS pass transistor, the subεtrate of the fourth MOS tranεistor is coupled to the substrate of the MOS pass transistor, and the drain of the fourth MOS transistor is coupled to the second terminal; wherein the MOS pasε transistor is on when an absolute value of the voltage of the first terminal is greater than an absolute value of the voltage of the second terminal, and the MOS pass transistor is off when the absolute value of the voltage of the second terminal is greater than the absolute value of the voltage of the first terminal. 5. The circuit of claim 4 wherein the comparison and control means includes a differential comparator circuit and an inverter circuit . 6. The circuit of claim 5 wherein the differential comparator circuit includes: a fifth MOS transistor having a source, a drain, and a gate wherein the drain of the fifth MOS transistor is coupled to an intermediate circuit, the intermediate circuit is coupled to the drain of the first MOS transistor, and the gate of the fifth MOS tranεiεtor iε coupled to the firεt terminal so that the fifth MOS tranεiεtor iε on when the voltage of the first terminal exceeds a turn-on voltage of the fifth MOS transistor; and a sixth MOS transistor having a source, a drain, a gate and a substrate wherein the source of the sixth MOS transiεtor is connected to the source of the fifth MOS transistor, the drain of the sixth MOS transistor is coupled to the gates of the second and fourth MOS transiεtors, and the gate of the sixth MOS tranεistor iε coupled to the second terminal so that the sixth MOS transistor is on when the voltage of the second terminal exceeds a turn-on voltage of the sixth MOS transistor. 7. The circuit of claim 6 wherein the inverter circuit includes a seventh MOS tranεiεtor having a source, a drain, a gate, and a subεtrate wherein the source and substrate of the seventh MOS transiεtor are both coupled to the drain of the εecond MOS transistor and to the substrate of the MOS pass tranεistor, the gate of the seventh MOS transiεtor is coupled to the drain of the sixth MOS transiεtor, and the drain of the seventh MOS transiεtor iε coupled to the gates of the firεt and third MOS tranεiεtorε. 8. The circuit of claim 4 wherein the εubεtrate of the MOS paεε transistor iε connected to εome of the substrates of the connection means and to some of the substrates of the switch means wherein the subεtrateε of the MOS pass tranεiεtor, of the connection meanε and of the switch means are part of either of discrete components and integrated components. 9. The circuit of claim 3 wherein the first MOS transiεtor iε on, and the second MOS tranεiεtor iε off when an abεolute value of the voltage of the firεt terminal iε greater than an abεolute value of the voltage of the εecond terminal wherein the substrate of the MOS pasε transiεtor iε connected to the first terminal through the first MOS transistor; and the first MOS transistor is off, and the second MOS transistor is on when the absolute value of the voltage of the second terminal is greater than the absolute value of the voltage of the firεt terminal wherein the subεtrate of the MOS paεε tranεiεtor iε connected to the εecond terminal through the εecond MOS tranεistor. 10. The circuit of claim 4 wherein the fourth MOS transiεtor iε off, and the third MOS transistor is on when an absolute value of the voltage of the first terminal iε greater than an absolute value of the voltage of the second terminal so that the gate control circuit of the MOS pasε tranεiεtor controls the gate of the MOS pasε tranεiεtor; and alternatively the third MOS tranεiεtor iε off, and the fourth MOS tranεiεtor is on when the absolute value of the voltage of the second terminal is greater than the absolute value of the voltage of the firεt terminal so that the gate of the MOS pasε tranεiεtor iε connected to the second terminal, and thus the MOS pasε tranεiεtor iε off. 11. The circuit of claim 7 wherein the εeventh MOS tranεiεtor provideε to each of the gate of the firεt MOS tranεiεtor and the gate of the third MOS tranεistor a signal that is inverted from a signal to each of the gate of the second MOS transiεtor and the gate of the fourth MOS tranεiεtor εo that when the firεt and third MOS transiεtorε are on, the second and fourth MOS transiεtorε are off. 12. The circuit of claim 1 wherein the MOS pass transiεtor iε a NMOS tranεistor, and the firεt terminal iε a negative power supply terminal. 13. A method for providing a minimum reverse current low dropout voltage output through a circuit comprising a MOS pass tranεistor having a source, a drain, a gate and a substrate between the first and the second terminals by coupling the source and the drain of the MOS pasε transistor in serieε between the two terminals, said method comprising the steps of: comparing a voltage of the first terminal with a voltage of the second terminal; connecting the subεtrate of the MOS paεε tranεiεtor to either one of the first terminal and the second terminal through a second circuit based on relative magnitudes of voltages of the first terminal and the second terminal,* and controlling the gate of the MOS pasε transistor based on the relative magnitudes of the voltages of the firεt terminal and the second terminal. 14. A circuit for coupling between a first terminal and a second terminal for providing a minimum reverse current low dropout voltage output comprising: a MOS paεε tranεiεtor having a εource, a drain, a gate and a εubεtrate, the source and the drain of the MOS pasε tranεiεtor being coupled in εeries between the first terminal and the second terminal; a first and a εecond transistors, each having a source, a drain, a gate, and a subεtrate; the drainε of the firεt and the εecond tranεistors and the subεtrateε of the firεt, the εecond, and the MOS pasε tranεiεtorε being coupled together; the εource of the first transiεtor coupled to the firεt terminal; the εource of the εecond tranεiεtor coupled to the second terminal; the gate of the first transistor coupled to a firεt intermediate circuit, the firεt intermediate circuit coupled to the εecond terminal; the gate of the εecond transistor coupled to a second intermediate circuit, the second intermediate circuit coupled to the first terminal; and the gate of the MOS pass transiεtor coupled to a third intermediate circuit wherein the εubstrate of the MOS pasε tranεiεtor iε coupled to the firεt terminal when the firεt tranεistor is on, and the subεtrate of the MOS pasε tranεistor is coupled to the εecond terminal when the εecond tranεiεtor iε on; wherein relative voltageε of the firεt terminal and the εecond terminal control the gateε of the firεt transistor and the second transiεtor. 15. The circuit of claim 14 wherein the substrate of the MOS pasε transistor is connected to the first terminal when an absolute value of the voltage of the first terminal is greater than an absolute value of the voltage of the second terminal and is connected to the second terminal when an absolute value of the voltage of the second terminal is greater than an absolute value of the voltage of the first terminal to minimize the reverse current through the MOS pass transistor. 16. The circuit of claim 14 wherein the third intermediate circuit compriseε: a third tranεistor and a fourth transiεtor, each having a εource, a drain, a gate, and a εubεtrate; the substrates of the third and fourth transiεtorε both being coupled to the εubεtrateε of the MOS paεε, the first and the second transiεtorε; the drain of the third transistor coupled to the gate of the MOS pasε transistor; the εource of the fourth transistor coupled to the gate of the MOS pasε transistor; the source of the third tranεiεtor coupled to a gate control circuit; the drain of the fourth transiεtor coupled to the εecond terminal; the gate of the third tranεistor coupled to the gate of the first transiεtor; and the gate of the fourth tranεiεtor coupled to the gate of the second transistor wherein relative voltages of the first terminal and the second terminal control the gates of the third transistor and of the fourth transiεtor. 17. The circuit of claim 16 wherein the third tranεiεtor iε on, and the fourth tranεiεtor iε off when an abεolute value of the voltage of the firεt terminal iε greater than an abεolute value of the voltage of the second terminal so that a gate control circuit of the MOS pass transiεtor controlε the gate of the pasε tranεiεtor; and the third tranεiεtor iε off, and the fourth tranεiεtor is on when the absolute value of the voltage of the second terminal is greater than the absolute value of the voltage of the first terminal so that the gate of the MOS pasε tranεiεtor iε connected to the εecond terminal, and thuε the MOS paεε tranεiεtor iε off. 18. The circuit of claim 16 wherein the firεt intermediate circuit iε identical to the εecond intermediate circuit, the firεt intermediate circuit comprising: a fifth transiεtor, a εixth tranεiεtor, and a εeventh tranεiεtor, each having a source, a drain, and a gate; the sourceε of the fifth and the εixth transistors being coupled together and the source of the seventh transiεtor being coupled to the drain of the εecond tranεiεtor; the gate of the fifth transiεtor coupled to the first terminal; the gate of the εixth tranεiεtor coupled to the second terminal; and the drain of the fifth transistor being coupled to a fourth intermediate circuit, the fourth intermediate circuit coupled to the drain of the first transistor, the drain of the sixth transistor being coupled to the gates of the second, the fourth, and the seventh transistors, and the drain of the seventh transistor being coupled to the gates of the first and the third transiεtorε. 19. The circuit of claim 18 wherein the εeventh tranεiεtor provideε to each of the gate of the first transistor and the gate of the third transiεtor a εignal that iε inverted from a εignal provided to each of the gateε of the second and the fourth transistors so that when an absolute value of the voltage of the firεt terminal iε greater than en absolute value of the voltage of the second terminal, the first and the third transistors are on, and the second and the fourth transistors are off, and when the abεolute value of the voltage of the εecond terminal iε greater than the abεolute value of the voltage of the firεt terminal, the first and the third transiεtorε are off, and the εecond and fourth tranεistorε are on. 20. The circuit of claim 18 wherein the first intermediate circuit further comprises: an eighth transiεtor, a ninth tranεiεtor, a tenth tranεistor, and an eleventh transistor, each having a subεtrate, a source, a drain, and a gate, the eighth transistor being the fourth intermediate circuit; the sources of the eighth, the ninth, and the tenth transiεtorε and the εubεtrates of the eighth, the ninth, the tenth and the eleventh transiεtors being connected to the substrate of the MOS pasε tranεistor and the εource of the eleventh transistor being connected to the drain of the tenth transiεtor; and the drain of the eighth tranεiεtor being coupled to the gateε of the eighth, the ninth and the tenth tranεiεtorε and to the drain of the fifth tranεiεtor; the drainε of the ninth and eleventh tranεiεtorε being coupled to the gate of the εeventh tranεiεtor and to the drain of the sixth transiεtor; and the gate of the eleventh transiεtor coupled to the drain of the εeventh tranεiεtor wherein detection of a difference in voltageε between the firεt and εecond terminalε iε improved. 21. A reverεe current limited circuit coupled between a firεt and a second terminalε compriεing: a first circuit including a pasε tranεiεtor coupled between the firεt and the εecond terminalε; a second circuit coupled between the first and the εecond terminalε and to the paεε tranεiεtor in order to minimize the reverεe current flowing through the pass tranεiεtor in reεponεe to a relative magnitude difference of voltages of the first and the second terminals; a third circuit coupled to the pasε tranεiεtor and the εecond terminal in order to activate and deactivate the pasε tranεistor in response to the relative magnitude difference of the voltages of the first and the second terminals; and a fourth circuit for detecting the relative magnitude difference of the voltages of the first and second terminals and for controlling the second and the third circuits, the fourth circuit coupled to the first terminal, to the second terminal, to the second circuit and to the third circuit.

Inventors: BINGHAM DAVID, BINGHAM, DAVID
Applicants: MAXIM INTEGRATED PRODUCTS
Application year: 1995
Main classification: H03K17
IPC codes: G01R19