ELECTRONIC CIRCUIT FOR DETERMINATION OF DISTANCES BETWEEN REFERENCE AND DATA POINTS

Abstract: An electronic circuit for Euclidean distance determination includes two floating gate transistors (M1, M2) connected in parallel. Voltages representing a reference point and its complement are applied to input lines (22, 24) and corresponding charges become stored on the transistors' floating gates (F1, F2). Voltages representing a data point and its complement are input to control gates (G1, G2). The transistors (M1, M2) produce a combined output current which is a quadratic or exponential function of the distance between the data and reference points according to whether the transistors are above or below threshold. The circuit (10) includes a diode-connected load device (M3) for deriving the square root of the output current, which is proportional to Euclidean distance when the transistors are operated above threshold. Refresh means (M44, M45) may be provided for resetting reference points. An array of circuits of the invention is employed for determination of distances between vector quantities.

Description: ELECTRONIC CIRCUIT FOR DETERMINATION OF DISTANCES BETWEEN REFERENCE AND DATA POINTS This invention relates to an electronic circuit. More particularly, although not exclusively, it relates to an electronic circuit for determination of distances between reference and data points. Electronic circuits for determining Euclidean distances are known in the prior art. Such a circuit incorporates a stored quantity corresponding to a reference point and accepts as input a signal representing a data point. It produces a measure of the distance between the input signal and the stored quantity. Such circuits are useful in applications in which calculations of Euclidean distance would consume a substantial amount of computing capacity. In visual and speech recognition, together with other forms of pattern recognition, it is necessary to determine Euclidean distances between large numbers of input data points and each point in a large database of reference points. In "Programmable Analogue VLSI for Radial Basis Function Networks", Electronics Letters 29 (18), pages 1663-1665, September 1993, Churcher et al describe a transconductance amplifier which produces an output current proportional to the square of the difference (distance) between an input voltage and a stored voltage maintained by a capacitor. The amplifier produces an approximation to the square of the Euclidean distance between the input and stored voltages. It is not suitable for applications such as pattern recognition requiring a large number of distance measuring circuits. It incorporates four transistors; two of the transistors are considerably wider than the other two, and they give rise to difficulty as regards formation of large arrays and because of high power consumption when operating in their saturation region. In "A Neural Network Capable of Forming Associations by Example", Neural Networks Vol 2 pages 395-403, 1989, Hartstein and Koch disclose a two- transistor circuit used in a neural network to represent a difference between a voltage input and a stored or learned value. The circuit incorporates two metal oxide semiconductor field effect transistors (MOSFETs), an n-channel MOSFET and a p-channel MOSFET. The MOSFETs are connected in parallel in a symmetric arrangement in order to obtain a symmetric output function for the neural network. Hartstein and Koch are not concerned with Euclidean distance determination, but instead output function symmetry. This symmetry requires close matching of the characteristics of the p-channel and n-channel devices, but this is extremely difficult because of differing carrier mobilities and other physical characteristics. If matching is not achieved the output of the circuit is not symmetric and not suitable for Euclidean distance determination. A two-transistor cell has been designed by Castro and Park (US 4,999, 525). It employs two floating gate transistors to implement an exclusive- or-operation between two digital patterns. Cells are cascaded together to calculate a Hamming distance between an input vector and a stored reference vector. The cell requires a separate high-gain inverter to complement the input vector, restricting the cell to digital operation. In "An Analog VLSI Chip for Radial Basis Functions", Advances in Neural Information Processing Systems 5, Morgan Kaufmann 1993, Anderson et al disclose a distance determination chip employing an inverter with an adjustable threshold. The threshold is set using a floating gate device such as that described by S M Sze in "Physics of Semiconductor Devices", Wiley 2nd edition 1981, page 496. This device is programmed using a combination of non-avalanche injection and tunnelling. The Anderson et al circuit has a major disadvantage in that its output does not correspond to a true Euclidean distance or square of a Euclidean distance; Instead, output current approximates to a quadratic function only in the region of a peak current value. The approximation is only valid over a very short range of input voltages, less than 0.35V in the implementation of Anderson et al. Each of the foregoing prior art techniques suffers from at least one of the following disadvantages, large chip area requirements, high power consumption, and restriction to a short range of input voltages or to digital implementation only. There is a perceived need for a circuit which admits of compact construction, is operative over a useful range of input voltages, and is suitable for analogue implementation. It is an object of the invention to provide an alternative form of electronic circuit suitable for use in distance determination such as the Euclidean norm. The present invention provides an electronic circuit incorporating: (i) first and second programmable threshold voltage transistors, a drain of each transistor being connected to a common output; (ii) input means for supplying analogue input voltages to a control gate of the first programmable threshold transistor, the analogue voltages corresponding to positions of reference and data points, characterised in that the circuit also incorporates: (i) means for supplying an analogue complement voltage to a control gate of the second programmable threshold transistor when the analogue input voltage is applied to the first programmable threshold transistor, the complement voltage being substantially the complement of the analogue input voltage supplied to the first programmable threshold transistor; (ii) programming means for supplying a predetermined programming voltage to the first and second programmable threshold voltage transistors, such that the supply of an analogue input voltage representing a reference point in conjunction with the supply of the programming voltage, and the subsequent supply of an analogue input voltage representing a data point causes a current on the common output which is a function of the distance between the reference and data points. Current output from the transistors is a quadratic or exponential function of the difference between input and reference voltages according to whether the transistors are above or below threshold. The invention has the advantage that it provides a measure of distance between data and reference points represented as input and reference voltages, and it is capable of construction in compact form with low power requirements. It is well suited to replication to form an array of circuits for performing multiple and multidimensional Euclidean distance determinations. The invention may include a diode-connected load transistor arranged to receive current from the common output and produce a voltage output which is proportional to the difference between input and reference voltages. The invention may also include means for periodically refreshing charges representing reference points on the floating gates of the first and second transistors. The refreshing means may include refresh transistors arranged to couple charges to the floating gates of the first and second transistors in response to activation. The invention may be arranged for sub-threshold operation and low power consumption. In another aspect, the invention provides an electronic circuit including two programmable threshold transistors, characterised in that the circuit also includes: (1) means for programming the transistor thresholds such that each transistor is operative to exhibit an output current proportional to a quadratic or exponential function of the difference between a reference voltage and an input voltage according to whether it is operated above or below threshold; (2) means for applying respective input voltages to the transistors simultaneously, one input voltage being the complement of the other; and (3) means for summing the output currents of the transistors. In a preferred embodiment, the invention provides an electronic circuit including two metal oxide silicon field effect transistors (MOSFETs) each of the kind incorporating a control gate and a floating gate, characterised in that the circuit also includes: (a) means for storing charge on both floating gates such that each MOSFET is operative to exhibit a drain-source current proportional to a quadratic or exponential function of the difference between a reference voltage and an input voltage according to whether it is operated above or below threshold; (b) means for applying input voltages to the control gates of the MOSFETs simultaneously, one input voltage being the complement of the other; and (c) means for summing the drain-source currents of the MOSFETs. Each transistor may have a current output connected to switching means, the switching means being connected to threshold programming means and to current summing means and being operative to switch the transistor output current from the threshold programming means to the current summing means in response to attainment of a predetermined programmed threshold. Circuits of the invention may be connected to form rows and columns of an array, each circuit being connected to a pair of data input lines associated with its column and to a threshold programming line and a switching activation line both associated with its row. In another aspect, the invention provides an array of electronic circuits each incorporating a pair of programmable threshold transistors, characterised in that the array includes: (a) a respective programming means for altering the threshold of each transistor to provide for transistor output current to be a quadratic or exponential function of the difference between a reference voltage and an input voltage according to whether the transistor is above or below threshold, the programming means being responsive to the output current of the respective transistor; (b) input means for applying respective input voltages to the transistors in each pair simultaneously, one of the input voltages to each pair being the complement of the other; (c) summing means for adding the output currents of the transistors; (d) a respective switching means connected to receive the output current of each transistor and operative to switch the transistor output current from the programming means to the summing means in response to attainment of a predetermined threshold by the transistor. In a further aspect, the invention provides an array of electronic circuits each incorporating a pair of MOSFETs each of the kind incorporating a control gate and a floating gate, characterised in that the array includes: (a) a respective programming means for storing charge on each floating gate to provide for MOSFET drain-source current to be a quadratic or exponential function of the difference between a reference voltage and an input voltage according to whether the MOSFET is above or below threshold, the programming means being responsive to the drain-source current of the respective MOSFET; (b) input means for applying respective input voltages to the MOSFETs in each pair simultaneously, one of the input voltages to each pair being the complement of the other; (c) summing means for adding the drain-source currents of the MOSFETs. (d) a respective switching means connected to receive the drain- source current of each MOSFET and operative to switch that current from the programming means to the summing means in response to attainment of a predetermined threshold by the MOSFET. In an alternative aspect, the invention provides a method for determining a distance between two points represented by analogue voltages, and comprising the steps of:- (a) providing a circuit incorporating two programmable threshold voltage transistors connected to a common current output, (b) programming the threshold voltages of the transistors to provide for output current from the transistors to be a function of the difference between a programmed reference voltage and subsequent transistor input voltages in complementary form, and (c) applying analogue input voltages to the transistors, one such voltage being the complement of the other. In a further alternative aspect, the invention provides a method for determining a distance between two points represented by analogue voltages, and comprising the steps of:- (a) providing a circuit incorporating two programmable threshold voltage transistors connected to current summing means, (b) arranging the transistors to provide for their output current to be a quadratic or exponential function of the difference between a programmed reference voltage and subsequent transistor input voltages in complementary form, and (c) applying analogue input voltages to the transistors, one such voltage being the complement of the other. In order that the invention might be more fully understood an embodiment thereof will now be described with reference to the accompanying drawings in which: Figure 1 is a schematic diagram of a circuit of the invention; Figure 2 is a graph of drain-source current against input voltage for the circuit of Figure 1; Figure 3 is a graph of output voltage against input voltage for the circuit of Figure 1; Figure 4 is a graph of output current against input voltage for sub- threshold operation of the circuit of Figure 1; Figure 5 is a schematic diagram of a circuit of the invention adapted for refreshable programming; Figure 6 is a schematic diagram of an array of circuits illustrating use of feedback in programming; Figures 7, 8 and 9 are graphs illustrating progress in programming the circuit of Figure 6; and Figure 10 is a schematic diagram of a further embodiment of the invention designed to employ feedback in programming. Referring to Figure 1, there is shown an electronic circuit of the invention indicated generally by 10. The circuit 10 incorporates first and second metal-oxide semiconductor field effect transistors (MOSFETs) Ml and M2. The MOSFETs Ml and M2 are floating gate devices, generally as outlined by S M Sze in "Physics of Semiconductor Devices", 2nd Ed Wiley 1981, page 496. MOSFET Ml has a floating gate Fl and a control gate Gl, and likewise MOSFET M2 has floating and control gates F2 and G2. In IEEE Electron Device Letters, Vol.12 No 3, March 1991, Thomsen and Brooke have estimated that a floating gate in a silicon MOSFET would lose charge at the rate of 0.1Z in 26 years. Data represented by charge on the floating gates Fl and F2 is therefore expected to persist. The MOSFETs Ml and M2 are parallel NMOS transistors which are used to determine the distance between a data point and a reference point. The data point is represented by input signals consisting of a voltage and its complement, these being applied to the control gates Gl and G2 respectively. The reference point is represented by charges stored on the floating gates Fl and F2. The MOSFETs Ml and M2 have respective drains Dl and D2 connected together at a common drain node 12. They also have respective sources SI and S2 connected together and to earth at a common source node 14. A third MOSFET M3, a conventional PM0S device, has a drain D3 connected to the common drain node 12 and to an control gate G3. It therefore constitutes a diode-connected load for both MOSFETs Ml and M2 connected in parallel. It has a source S3 connected to a power supply line 16 voltage V DD which is positive with respect to earth at the common source node 14. The floating gates Fl and F2 have coupling capacitors Cl and C2 connected to respective reference input lines 18 and 20. The lines 18 and 20 are arranged to provide a voltage V^,.^ to respective capacitors Cl and C2 and thence to floating gates Fl and F2. The circuit 10 has a UV opaque coating (not shown) through which are formed ultra-violet (UV) transparent windows UV1 and UV2 located over floating gate/capacitor combinations Fl/Cl and F2/C2 respectively. The windows UV1 and UV2 facilitate UV illumination of the floating gate Fl and capacitor Cl in combination and floating gate F2 and capacitor C2 in combination respectively. Data input lines 22 and 24 are connected to respective control gates Gl and G2. Data input line 22 is arranged to provide a voltage V dat8 to control gate Gl, and data input line 24 is arranged to provide a voltage equal to (V DD - V data ) to control gate G2. V data corresponds to the voltage of a data point and (V D - V data ) to its complement. The value V data is in the range 0 to V DD . The complement voltage may be generated by a conventional differential amplifier arranged to subtract V data from V DD with unity gain. A suitable amplifier is shown at page 99 of P. Horowitz and W. Hill, Cambridge University Press, 1980, ISBN 0521 23151 5. The operation of the electronic circuit 10 will now be described in general terms, a theoretical analysis being given later. The objective is to determine the Euclidean distance d between a data point and a set reference point. The MOSFET floating gates Fl and F2 have the function of analogue memory devices to which electric charge is injected and stored. The stored charge corresponds to a predetermined reference point. Charge is introduced on to the floating gates Fl and F2 by a UV-enabled conduction process. The circuit 10 is illuminated with UV radiation which passes through the windows UV1 and UV2 only. This renders the capacitors Cl and C2 conducting; ie they develop leakage current because of UV- activated conduction in their dielectric material. The voltages on the reference input lines 18 and 20 consequently become applied to the floating gates Fl and F2 via the now conducting capacitors Cl and C2 respectively. The process is described in more detail by D A Kerns et al. in "CMOS UV-Writable Non-Volatile Analog Storage": "Advanced Research in VLSI: Proceedings of Santa Cruz Conference 1991, Santa Cruz CA, March 25- 29 1991", page 245. The MOSFETs Ml and M2 are programmed as follows. A voltage V^,.,. } . is applied to reference input lines 18 and 20. It is of sufficient magnitude to establish the channel surface potential of MOSFETs Ml and M2 at the "turn-on" voltage (threshold voltage V t ) at which strong inversion occurs. Strong inversion is defined by Sze (see reference above) at page 373. The exact value chosen for V- aa ,.^ is not critical so long as it is a little above V t in the present embodiment of the invention. Simultaneously with application of V^^ , a voltage V ref and its complement (V DD - V rβf ) are applied to the data input lines 22 and 24 respectively, and the circuit 10 is illuminated with UV radiation. This combination of applied voltages results in a charge corresponding to the position of a reference point y being stored on floating gates Fl and F2. The theoretical basis for this is described in detail later. The UV illumination is now switched off, and the voltages V-^,.^, V ref and (V DD - V ref ) are removed from lines 18/20, 22 and 24 respectively. The theoretical basis for the invention is as follows. Generally for an NMOS MOSFET with gate-source voltage V gs and threshold voltage V t a conducting channel between source and drain is formed when V gs is greater than V t . When the voltage between the source and drain, V ds , is greater than (V gs - V t ) the MOSFET operates in its saturation region, and its drain-source current I ds is substantially independent of V ds . For a MOSFET in saturation, the equation for the drain-source current I ds is as follows:- I ds = | (V gs - V t ) 2 (1) where β is a proportionality constant given by:- β = • μC 0X (2) In equation (2), L is the length of the conduction channel between source and drain, W is the width of the conduction channel, μ is the charge carrier mobility and C ox is the capacitance of oxide between the MOSFET gate and associated conduction channel. Ignoring constants, equation (1) has the same form as the equation for the Euclidean distance d between two points x and y: d 2 = (x - y) : (3) Comparison of equations (1) and (3) indicates that MOSFET drain-source current I ds provides a measure of the square of the Euclidean distance d between two points x and y represented by gate-source voltage V gs and threshold voltage V t respectively. However, V t is a fixed quantity for any individual MOSFET, and equation (1) does not enable use of a range of values of both x and y. In order to use the circuit 10 for determining the Euclidean distance in accordance with the invention, it is necessary to provide for a range of values of both x and y to be accommodated. To achieve this, the circuit 10 is first programmed with the voltages V.^,.,. ! ., V ref and (V DD - V ref ) by UV illumination as described earlier. A voltage V data , representing the position of a data point, is then input on line 22 to control gate Gl, and its complement (V DD - V data ) is input on line 24 to control gate G2. At this point the potential V fg on the floating gate Fl is given by:- V ' f fg, = i∑ (V data -V ref ) +V Mteh (4) ■ 'tot- where V data , V ref and V Mtl , ll are as previously defined, C pp is the capacitance between the floating gate Fl and the control gate Gl and C tot is the total capacitance of the floating gate Fl. Equation (4) shows that the floating gate voltage V fg is equal to V mt . h when V data and V ref are equal, which corresponds to the Euclidean distance between locations x and y being zero. It is emphasised that the quantity V ref is a reference voltage used in programming the circuit 10, and it affects the charge stored on the floating gates Gl and G2; however, this quantity is not in fact explicitly stored on either of these gates nor elsewhere in the circuit 10. The equation for the drain-source current treats V ref as a voltage retained by the circuit 10 for subtraction from input voltages. The drain-source current in the MOSFET Ml is responsive to the signal on the floating gate Fl, and the gate-source voltage V gs is equal to V fg . Consequently, equation (4) can be substituted in equation (1) for V gs : β . f -.2 " *-ds ■PSP- (v data - V ref ) + v mteh - v t ( 5 ) " Z ((• "T TOOTT Where V t is the threshold voltage of the MOSFET Ml. By selecting V,,,^ to be substantially equal to V t , equation (5) becomes T . - βf C PP (V data " V ref ) 2 ( 6 ) ds — If V data and V ref are proportional to points distant x and y respectively from an origin, then from equations (3) and (6) the drain-source current I ds of the MOSFET Ml is proportional to the square of the Euclidean distance d between those points. Similar remarks apply to the MOSFET M2. The circuit 10 is therefore suitable for use in Euclidean distance determination. Equation (6) is one-dimensional; it applies to Euclidean distance determination when x and y are scalars. When x and y are vectors in n dimensions, one pair of MOSFETs Ml and M2 is required for each dimension as will be described later. There is substantially no conduction channel in the MOSFET Ml when V data is less than V ref , and I ds is zero from equations (6). In consequence the MOSFET Ml provides a measure of Euclidean distance only when V dat:a is greater than V re£ , which corresponds to x being greater than y in equation (6). A Euclidean distance cannot therefore be determined using a single MOSFET for locations x closer to an origin than the reference location y. For this reason the circuit 10 has two MOSFETs Ml and M2, the former for values of x greater than y and the latter for values of x less than y. As regards the former, MOSFET Ml is operating in its saturation region; from equation (6), adding a subscript index of 1 to the terms β M , C pp , C toc and I ds to indicate that they are associated with MOSFET Ml:- L dsl V data - V ref ) 2 ( 7 ) From equation (7), I dsl provides a measure of the square of the Euclidean distance between x represented by V data and y represented by V ref . When x is less than y, V data is less than V ref . From equation (7) there is therefore no conduction channel for MOSFET Ml and drain-source current I dsl is substantially zero. For MOSFET M2, (V DD - V data ) is the complement of x, and the complement of y is (V DD - V ref ). (V DD - V data ) is greater than (V DD - V ref ) when the value of x, represented by V daCa , is less than that of y. Consequently, from equation (6), adding a subscript index of 2 to the terms β M , C pp , C tot and I ds to indicate that they are associated with MOSFET M2, the drain-source current I ds2 in saturation is given by: _ βHMM2 2 || r c% - * p*_pτ_2 2 2 ds2 ((V D D- v data ) - (V DD -V ref )) 2 (8) -tot2, For x greater than y, V data is greater than V ref , (V D - V ref ) is less than (V DD - V data ); the drain-source current I ds2 of MOSFET M2 is therefore substantially zero. Consequently, Euclidean distance squared (d 2 ) is proportional to the drain- source current of MOSFET Ml when x is greater than y, and to that of MOSFET M2 when x is less than y. Since each of I dsl and I ds2 is substantially zero when the other is non¬ zero, d 2 is also proportional to the sum of I dsl and I s2 ; this sum is I out> the drain-source current of the third MOSFET M3. The common drain node 12 acts as a summing junction which sums the drain-source currents of the MOSFETs Ml and M2 flowing to the third MOSFET M3. The circuit of Figure 1 was manufactured by a commercial chip foundry, which produced floating gate MOSFETs with a typical value of V t of 0.75V. Suitable values of V^,.^ are in the range 0.5V to 1.5V, preferably 0.75 V to 1.0 V, and are dependent on the MOSFET technology and threshold voltage used. It was found by experiment that a suitable value of V,,^ for the MOSFETs used in the foregoing example was 0.85V. Figure 2 shows a graph of current at the common drain node 12 against V data for three values of V ref . The current at the common drain node 12 is the sum of the drain-source currents I dsl and I ds2 of MOSFETs Ml and M2 respectively. Figure 2 shows three curves 200, 201 and 202 which represent values for V ref of 1.5V, 2.5V and 3.5V. Each of the curves 200 to 202 is parabolic and provides verification that a current I out at node 12 is proportional to the square of the difference between V daca and V ref . In this manner the MOSFETs Ml and M2 are employed in the determination of the square of the distance between points x and y, ie. they provide d 2 in equation (3). MOSFET M3 is then operated in its saturation region in order to obtain d from the current I out at node 12. A current I OAD flowing from the common drain node 12 to the drain D3 produces an output voltage V ouτ at the gate G3 given by:- T-LOAD = —r- TOUT ~ V T3 ) (9) In equation (9), β^ is a proportionality constant given by equation (2) and V T3 is the threshold voltage, for MOSFET M3 in each case. When the data point x and reference point y are coincident, i.e when the Euclidean distance between them is zero, ILQAD i- 3 a small offset current I 0 : i e = P» (v 0 - V T3 ) 2 (10) where V 0 is the output voltage resulting from the offset current I 0 As the Euclidean distance between points x and y increases, the output voltage V ouτ increases by δV 0UT from V 0 to (V 0 + δV 0UT ) , and ILOAD becomes: _ βM3 L I_0AD ((V 0 + δV 0UT ) - V T3 ) 2 ( 11 ) For values of x greater than that of y, MOSFET M2 has substantially zero drain-source current I ds2 and MOSFET Ml supplies non-zero drain current I dsl to MOSFET M3. In*^ is then given by •• LOAD (Vdata - V ref ) 2 ( 12) Combining equations (11) and (12), βM3 ((v 0 + δv ouτ ) - v T3 ) 2 βMl C ppl T (Vdata " V ref ) 2 ( 13 ) When the Euclidean distance between points x and y is zero, IL O A D is substantially zero and thus from equation (10) (V 0 - V T3 ) is substantially zero. Thus from equation (13), and therefore As V data and V ref represent the data and reference points x and y, then from equation (3) the term in brackets on the right hand side of equation (15) corresponds to the square of the Euclidean distance d between points x and . Thus, Consequently the Euclidean distance d between data point x and reference point y can be obtained from a measurement of the change in output signal Vouτ from the MOSFET M3, and from knowledge of the values of constants β M1 and β^ j , and C ppl and C tot . Alternatively the proportionality constant which relates δV 0UT to d can be obtained by calibration. It is frequently unnecessary even to calibrate, since for many purposes all that is required is a value proportional to d. When data point x has a value lower than that of reference point y the drain-source current I dsl of MOSFET Ml substantially zero . From equation (8):- i-LOAD = U£ ( E2-1 ((V DD - V^) - (V DD - V ref )) 2 (17) and from considerations equivalent to those in equations (13) to (15) (18) Thus from equation (18) the Euclidean distance d between points x and y can be obtained from a measurement of the change in output signal δV 0UT from MOSFET M3, with knowledge of the values of C pp2 and C cot2 and proportionality constants β M2 and _ . If MOSFETs Ml and M2 are identical then β M1 is equal to β M2 , and C ppl and C pp2 are equivalent, as are C totl and C tot2 . δV 0UT provides a direct measure of Euclidean distance d without determining which of MOSFETs Ml or M2 is operative. In these circumstances equations (15) and (18) can be written as where β is the proportionality constant for both MOSFETs Ml and M2, C pp and C cot are capacitance values for both MOSFETs Ml and M2, and Δ is a representation of the voltage differences between points x and y, for values of x both smaller and larger than y. Figure 3 shows a graph of voltage output V 0 uτ at node 12 with respect to ground against V data . The graph has curves 300, 302 and 304 corresponding to V ref of 1.5V, 2.5V and 3.5V respectively. The MOSFET M3 is a PMOS enhancement-mode device and is arranged for maximum output voltage when IL OA D s at a minimum. Consequently, curves 300 to 304 have output peaks, rather than minima, when V data is equal to V re£ . If MOSFET M3 is replaced by an NMOS enhancement mode device and MOSFETs Ml and M2 with PMOS devices, then with power supply polarities inverted equivalent curves would be obtained with minima when V data is equal to V ref . The curves 300 to 304 have regions of lower gradient below output voltages V ouτ of IV. This is because MOSFETs Ml and M2 are no longer operating in saturation. However, the circuit 10 provides a good linear voltage response V ouτ to IL OA D over a 3V range of input values V daca . Slight deviations from linearity are due to small differences between V^,.^ and MOSFET Ml and M2 threshold voltages. MOSFET M3 can be designed to provide a substantially linear response over a higher voltage range by increasing its channel width W. This results in a smaller swing in output voltage to give the required linear response over larger range. The curves 300 to 304 have respective peaks each with linear regions on either side having gradients Pl m ) S-__ ] and -(β/ rø) 15 (_ ____ A linear region on the right or left of such a peak corresponds respectively to increasing or decreasing Euclidean distance d between points x and y as V data increases. The electronic circuit 10 has significant advantages over prior art devices for distance calculation. It is more compact than the circuit of Churcher et al and can be operated at lower current levels. The circuit 10 employs the operating characteristics of the MOSFETs Ml and M2 (when programmed with V ref ) to provide an output current proportional to the square of the Euclidean distance between points x and y. This enables the circuit 10 to accept analogue voltages in respect of x and y. The compactness, speed and low power requirements of the circuit 10 mean that it is advantageous for applications which would otherwise require substantial computing resources, such as pattern recognition. The circuit 10 may also be operated in its sub-threshold region, i.e. when the channel surface potentials of MOSFETs Ml and M2 are below threshold voltage V t , and in the weak inversion region. For this to occur, v^,.^ is much less than the threshold voltage V t . A typical value is 0.4V. More generally, V„. tch is in the range 0.2 V to 0.7 V for sub-threshold operation. Trends in semiconductor technology indicate that threshold voltages will reduce in future, and therefore a suitable range for V mtc is 0 V to 0.7 V. In weak inversion the drain-source current I ds of a MOSFET is given by:- I ds = I offset exp(V ge /V a ) (20 ) where V gs is the gate-source voltage, I offSβt is an offset current parameter and V n is the change in gate voltage required to increase current I ds by a factor of e. For the MOSFET Ml, substituting V £g from equation (4) for V gs in equation (20) gives In ( I dsl ) - | , * - * pp_. (V data " V r e ) + mtch + ln ( I o££sβt ) ( 21 ) -•tot ^ Similarly , for the MOSFET M2 , the same analysis results in the equation In (I ds2 ) = (V re£ - V data ) + V Mtβh j. _j + ln (I o£f8βt ) (22) When the source-drain currents I dsl and I ds2 are added at the common drain node 12, both MOSFETs Ml and M2 make a substantial combined contribution only when V data is substantially equal to V ref ; otherwise, one of the MOSFETs Ml and M2 will provide a dominant current, ie I dsl or I ds2 generally dominates. From equations (21) and (22), a current I ouτ is produced at the common drain node 12 given by:- ln ( IQUT ) 'data - V ref l + V, match J_- + ln ( I o££ββt ) ( 23 ) In sub-threshold operation therefore I ouτ is an exponential function of the distance between the data and reference points, as shown by the term I v data 'ref in equation 23. Figure 4 shows a curve 350 of output current I 0 uτ drawn on a logarithmic scale against V aca on a linear scale. The ordinate is graduated with expressions of the kind "le-n", where n is in the range 5 to 12; this expression means 10" n . The curve 350 is quasi- linear between points 352 and 354 at voltages of 1.25 V and 3 V, a range of 1.75 V comfortably in excess of 1 V or even 1.5 V. Between points 352 and 354 therefore, the logarithm of I ouτ varies close to linearly with V data - i e I OU T approximates to an exponential function of V data . The curve 350 was determined for V ref of 3.3 V, which corresponds to the position of a minimum at 356 on the curve 350. Changing V ref shifts the position of the minimum 356. The curve 350 demonstrates that the circuit 10 operated sub-threshold is suitable for use with a 3.3 V power supply, as employed in conventional digital logic. The modulus of (V^^- V ref ) would be required to be between 0 V and 3.3 V. The quasi-linear region 352-354 of the curve 350 extends over four orders of magnitude in current, from 2xl0" u Amp to 2xl0" 7 Amp. This can be altered by altering V^^. Figure 4 was obtained using MOSFETs optimised for above-threshold operation. For sub-threshold operation, the ratio (C pp /C tot ) can be reduced to reduce the capacitative coupling between the MOSFET control gate and floating gate. This has the effect of reducing the average slope of the quasi-linear region 352-354 of the curve 350. Output current I ouτ in sub-threshold operation is very low, about two orders of magnitude below that in saturation. This makes sub-threshold operation particularly suitable for low voltage applications, such as in battery powered equipment. It is also possible to operate the third MOSFET M3 sub-threshold to reduce power supply voltage further. The circuit 10 may therefore be optimised for operation with a 1.5 V battery, the permissible range for the modulus of (V^^.- V ref ) being 0 to 1.5 V. Referring to Figure 5, there is shown an alternative circuit of the invention indicated generally by 400. The circuit 400 is arranged for electronic resetting of reference point voltage. It incorporates first and second floating-gate MOSFETs M41 and M42 equivalent to those described earlier with reference to Figure 1. The MOSFETs M41 and M42 have respective floating and control gates F41/G41 and F42/G42. They have the same function as MOSFETs Ml and M2. They are parallel transistors for determining the distance between a reference voltage programmed with the aid of floating gates F41 and F42 and an input voltage and its complement input to control gates G41 and G42. The MOSFETs M41 and M42 have respective drains D41 and D42 connected to a common drain node 402 and respective sources S41 and S42 connected to an earthed common source node 404. A third MOSFET M43 has a drain D43 connected to the common drain node 402. It is equivalent in function to the third MOSFET M3 of the circuit 10, and provides a diode connected load for both MOSFETs M41 and M42. It has a source S43 connected to a power supply line 406 at a positive potential V DD . The circuit 400 incorporates refresh MOSFETs M44 and M45, these being NMOS pass transistors arranged as switches connected to floating gates F41 and F42 of respective MOSFETs M41 and M42. The MOSFETs M44 and M45 have respective control gates G44 and G45 connected to refresh lines 408 and 410, which provide these gates with an activating voltage, V rβ£resh . The MOSFETs M44 and M45 are also connected to respective voltage lines 412 and 414, which provide a substantially constant voltage MOSFETs M41 and M42 have respective data input lines 416 and 418 connected to respective control gates G41 and G42. Data input line 416 is arranged to provide a voltage V in the range 0 to V DD to control gate G41, and data input line 418 is arranged to provide a complement voltage (V DD - V) to control gate G42. The operation of the circuit 400 will now be described. As described earlier in relation to Figure 1, the MOSFETs M41 and M42 provide a current at the common drain node 402 which is a function of the distance between a data point and a reference point. Referring now also to Figure 2, there are shown graphs of output current at the common drain node 402 against input V data . These graphs illustrate the quadratic relationship between input voltage and current. The third MOSFET M43 produces output voltage and current characteristics which are as shown in Figures 3 and 4. The circuits 10 and 400 differ in that the latter has MOSFETs M44 and M45 for periodic resetting of charge corresponding to a reference point stored on floating gates F41 and F42. To store a reference point on the floating gates F41 and F42, a voltage Vm at c h is applied to the voltage lines 412 and 414. The voltage V refresh is then applied to refresh lines 408 and 410 and appears on control gates G44 and G45. V re£resh is a higher voltage than the threshold voltages of MOSFETs M44 and M45, which in consequence have conduction channels formed in them to switch them on. Since they are pass transistors, they become effectively short circuits causing floating gates F41 and F42 to become at voltage V.- t ,.,,. Voltage V re£ representing reference point y is now applied to input line 416 and appears on gate G41. Similarly, its complement (V DD - V rβf ) is applied to input line 418 and appears on gate G42. Voltage V re£resh is removed from refresh lines 408 and 410, bringing MOSFETs M44 and M45 below their threshold voltages and switching them off. Consequently, floating gates F41 and F42 are isolated, causing voltage V,,.^ to be stored on capacitors C41 and C42. Capacitors C41 and C42 include several contributions, eg junction capacitances to ground of MOSFETs M44 and M45, together with capacitances of floating gates F41 and F42 to control gates G41 and G42 and to conduction channels of MOSFETs M41 and M42. Voltage V data corresponding to data point x is then applied to input line 416, and its complement voltage (V DD - V data ) is applied to input line 418. These voltages appear on gates G41 and G42 respectively. When data point x and reference point y are coincident and the Euclidean distance d between them is zero, floating gates F41 and F42 are both at the voltage ^^. This defines the level of current at match. For x and y non-coincident, a capacitative divider effect couples the voltages V data and (V DD - V data ) on the control gates G41 and G42 to the floating gates F41 and F42 respectively. This changes the floating gate voltages and the MOSFETs' drain-source currents. The circuit now programmed for operation to determine Euclidean distances. The circuit 400 is larger than the circuit 10 because it has extra MOSFETs M44 and M45 for refresh purposes. However, it has the advantage that it can be programmed with voltage V re£ with greater accuracy and repeatability. UV illumination is useful for applications in which the positions of reference points rarely change, and for initialisation to remove unwanted charge. The circuit 400 is suitable for applications in which the positions of reference points are required to be changed electronically. Typical applications for arrays of circuits such as 10 and 400 are radial basis function networks, density estimation circuits and vector quantisation circuits. The invention is relevant to these applications because of its capability for rapid determination of distance together with its relatively small size and low power consumption. The circuits 10 and 400 are employed individually to determine the distance between two scalar quantities. When it is required to determine the distance between two multidimensional quantities, ie two vectors, one of these circuits may be employed repeatedly using successive elements from each of the vectors. Output currents corresponding to pairs of vector elements are summed prior to square rooting. However, this would require circuit reprogramming with a further element of a reference vector after each determination. It is therefore preferable to employ an array of circuits each of the form of the circuit 10 or 400, with each circuit in the array being associated with a respective stored reference vector element. Elements of a data vector are then presented to respective circuits in the array, and subtraction from respective reference vector elements is carried out. The squared differences (see equation (3)) between vector element pairs produced by the circuits are summed by summing their output currents. To express this in algebraic terms, it is required to determine the Euclidean distance between two n-dimensional vectors, a data vector X , with elements and a reference vector Y_ with elements y i( where i has values 1 to n and indicates the i th dimension. An array of n circuits is employed as aforesaid, with one circuit per dimension. The i th circuit is programmed with V i#rβ£ representing the i th element of the reference vector, and receives input (as V daca and its complement) of the i ch element of the data vector. The output currents of all n circuits are summed to produce a total current I tot given by:- I« = S∑ ( a-i- i ) ' (24) By applying the summed current I tot to a single load MOSFET connected as the MOSFET M3 or M43, the Euclidean distance between the multidimensional data and reference vectors is represented by δV 0UT given by:- This may be implemented using a one-dimensional array of circuits such as 10 or 400; such an array would require modification to implement current summing. One approach to so doing involves removal of the MOSFETs M3 or M43 and their replacement by a single common MOSFET of sufficient capacity to sum the array's entire current output. Alternatively, all MOSFETs equivalent to M3 or M43 may be retained and connected in parallel, with all current summing nodes being connected directly together. A two- dimensional array of such circuits may be used for simultaneous Euclidean distance determinations involving several data vectors and/or reference vectors, with each row of the array being used for a respective pair of data and reference vectors. The foregoing programming schemes for the circuits 10 and 400 involve the use of a voltage V j - atch in setting MOSFET floating gate potentials. Since a floating gate is isolated, it is difficult to determine the degree of accuracy to which a desired floating gate potential might be reached. Furthermore, supposedly identically produced MOSFETs such as Ml and M2 exhibit inter-device variations leading to differing threshold voltages. An additional consideration is that the efficiency of charge injection on to a floating gate changes with use, so that programming characteristics alter. It has been discovered that it is possible to compensate for all these variations by programming a MOSFET until it has a desired drain- source current, with the aid of additional circuitry described below. Referring to Figure 6, there is shown an array 600 of four floating-gate MOSFETs M61, M62, M63 and M64 arranged in two rows RR1 and RR2 and two columns CC1 and CC2. The first floating-gate MOSFET M61 has a control gate G61 and a floating gate F61 connected to a UV - activatable coupling capacitor C61 under a UV - transparent window UV61. Other floating-gate MOSFETs M62 etc have like parts (unreferenced). The coupling capacitance ratio (C pp /C tot ) of all control gates such as G61 is approximately 0.5. The capacitance of all coupling capacitors C61 etc is much smaller than this. The first floating-gate MOSFET M61 is connected drain-to-source to two switching MOSFETs, n-channel and p-channel devices MN61 and MP61 with switching gates GN61 and GP61 respectively. As indicated at FB and SC, the MOSFETs MN61 and MP61 have drains connected to a feedback loop (not shown) and a summing circuit (not shown) respectively. The feedback loop FB incorporates a current comparator. The columns CC1 and CC2 have respective data lines Vdatal and Vdata2 each connected to all control gates in the respective column, such as control gate G61 in the first column CC1. The rows RRl and RR2 have respective injector lines Vinjl and Vinj2 each connected to all coupling capacitors in the respective row, such as coupling capacitor C61 in the first row RRl. The rows RRl and RR2 also have respective programming lines Vprogl and Vprog2 each connected to all switching gates in the respective row, such as switching gates GN61 and GP61 in the first row RRl. The array 600 comprises four floating-gate and switching MOSFET circuits each incorporating one floating-gate MOSFET such as M61 and two switching MOSFETs such as MN61 and MP61. Each such circuit is connected in parallel with a second like circuit (not shown) as will be described later. The two p-channel switching MOSFETs of each row (eg MOSFET MP61 in first row RRl) are connected to a respective current summing circuit such as SC. The array 600 is programmed as follows. One row RRl or RR2 is programmed at a time, with all the floating-gate MOSFETs in that row being programmed in parallel. When the programming line Vprogl is at a high voltage, the n-channel switching MOSFET MN61 is switched ON and the p-channel switching MOSFET MP61 is switched OFF. Current then flows through the n-channel device and into the feedback loop FB. One feedback loop FB serves all the circuits of each column. When the programming line Vprogl is at a low voltage, the n-channel and p-channel switching MOSFETs MN61 and MP61 are switched OFF and ON respectively. The current is then directed into the current summing circuit SC for operation of the circuit after programming. To program the first row RRl with the elements of a reference vector, voltages representing those elements are applied to lines Vdatal and Vdata2. The first programming line Vprogl is held at high voltage to switch the drain-source currents of the floating-gate MOSFETs M61 and M62 into their respective feedback loops such as FB. A high voltage is then applied to the first injector line Vinjl, and the second injector line Vinj2 is grounded. This injector line high voltage is in the range 15 V to 17 V, and is optionally continuous or a train of pulses. It produces charge tunnelling at both first row floating gates such as F61 as electrons are removed therefrom. Electron removal changes the floating gate potential and the drain-source current of each of the first row floating-gate MOSFETs M61 and M62. The comparator in the feedback loop of each of these MOSFETs is designed to change state and to switch the associated Vdatal or Vdata2 line to a high voltage of 15 V when the MOSFET M61 or M62 reaches the desired drain- source current. If for example the first row, first column MOSFET M61 reaches the desired drain-source current first, then Vdatal becomes switched to 15 V. Moreover, because (C pp /C toc ) is 0.5, by capacitative divider effect the floating gate potentials of the MOSFETs M61 and M63 connected to Vdatal change by up to half of the Vdatal voltage, ie by up to 7.5 V. By virtue of the 15 V potential on line Vinjl and that now on the first MOSFET floating gate F61, an electric field arises across the coupling capacitor C61. However, this field is not sufficiently high to cause significant charge tunnelling involving the floating gate F61, and programming of the first MOSFET M61 ceases. A similar field of opposite polarity arises between the grounded line Vinj2 and the floating gate of the third MOSFET M63, but this is also insufficient to cause tunnelling and it does not affect the third MOSFET's programming. However, the injector line Vinjl remains at high voltage, and programming continues for the remaining second (and final) MOSFET M62 in the first row RRl. When the comparator in the feedback loop of this MOSFET has changed state, the first row RRl is fully programmed. Programming of the second row RR2 is carried out in a like manner. As before, voltages representing the elements of a reference vector are applied to lines Vdatal and Vdata2. A high voltage is applied to the second programming line Vprog2 and to the second injector line Vinj2, and the first injector line Vinjl is grounded. This situation is maintained until both the comparators in the feedback loops of the second row MOSFETs M63 and M64 have changed state, at which point the second row RR2 and the entire array 600 are fully programmed. The array 600 is now ready for input of the elements of a data vector to respective data lines Vdatal and Vdata2. Arrays with more than two rows and/or columns are programmed likewise row by row, all the feedback comparators in each row changing state before programming of the subsequent row begins. The foregoing programming scheme may be unidirectional; it might not be capable of both increasing and reducing the charge on a floating gate such as F61. This is because the process employed to produce the MOSFET may not be able to tolerate both positive and negative high voltages in programming. In the present example it was only possible to remove charge from a floating gate such as F61. Charge removal raises the potential of a floating gate, lowers the effective MOSFET threshold voltage and hence increases the MOSFET drain-source current. In consequence the desired current to be programmed is approached from below. However, MOSFET floating gates have an arbitrary charge placed on them during manufacture, and it is therefore necessary to ensure that each of them has an initial potential which is below that required in use. This is also necessary if the array 600 is ever to be reprogrammed. It is achieved by UV illumination through the windows such as UV61. An alternative initialisation approach would involve relocated UV windows enabling UV illumination of control gates such as G61. This provides for ageing during initialisation to be confined to the gate region, leaving the capacitors (eg C61) unaffected. The array programming technique described above has been verified in a test using two floating gate MOSFETs configured as the first row RRl of the array 600 except that switching transistors MN61 etc were not employed. Instead external switches were used. The initial drain- source current to be programmed was chosen to be 164 nA. The test MOSFETs were programmed using a train of high-voltage pulses, the drain-source current in each being checked after each pulse. Referring now to Figure 7, there is shown the response of the two test MOSFETs to programming with high-voltage pulses. There were very significant differences between the capacitors of these two devices, which made them difficult to program by any method which assumed them to be equivalent. The input reference voltages Vdatal and Vdata2 were set to 0.8 V and 0.9 V respectively, and the train of high-voltage pulses was applied as Vinjl to both coupling capacitors. The first test MOSFET reached the desired drain-source current of 164 nA after just two pulses, as indicated by the uppermost horizontal line 702 and thereafter its gate voltage was pulled to a high voltage as described earlier. The second test MOSFET had a severely damaged injector which took much longer to program; it required eight hundred and fifty-five pulses before it reached the desired drain-source current. This is indicated by the succession of four lines and part line 704 in the lower region of Figure 7, where the number of pulses is expressed on a modulo 200 basis. The abscissa value therefore returns to zero after each set of two hundred pulses and each complete line 704 represents such a set. Referring now to Figures 8 and 9, there are shown drain-source current/voltage curves for the first and second test MOSFETs respectively. Current is plotted on a logarithmic scale and voltage on a linear scale. In these drawings, solid curves 720/740 and dotted curves 722/742 relate to MOSFETs before and after programming respectively; horizontal dotted lines 724/744 indicate the desired drain-source current of 164 nA, and vertical dotted lines 726/728 and 746/748 indicate the MOSFET gate voltages at which the desired current was reached before/after programming. Line 726 in Figure 8 shows that, before programming, the first test MOSFET exhibited the desired current at a gate voltage of 1.044 V. From Figure 9, line 746, the equivalent for the second test MOSFET was 1.159 V. These values correspond to unprogrammed stored data points. Curves 722 and 742 show that, after programming, the stored data points of the test MOSFETs were 0.799 V and 0.900 V, very close and identical respectively to the desired values previously input as reference voltages Vdatal and Vdata2. In programming the first test MOSFET there was a minor overshoot of 1 mV, which could have been avoided by using lower voltage programming pulses. Referring now to Figure 10, there is shown a single Euclidean distance circuit indicated generally by 800. It is suitable for replication to produce an array as previously described with reference to Figure 6. It incorporates two floating gate MOSFETs M81 and M82 each connected drain- to-source to a respective pair of n-channel and p-channel switching MOSFETs MN81/MP81 and MN82/MP82. The n-channel switching MOSFETs MN81 and MN82 are connected to respective feedback circuits indicated by FBI and FB2. The p-channel switching MOSFETs MP81 and MP82 are connected to a p-channel diode-connected load MOSFET M83. The floating-gate MOSFETs M81/M82 have respective control gates G81/G82, floating gates F81/F82 and coupling capacitors C81/C82. The control gates G81 and G82 are respectively connected to input lines Vdata and V*data, which are for input of voltages and their complements respectively. The coupling capacitors C81 and C82 are connected to a charge injection line Vinj. The switching MOSFETs MN81/MP81 and MN82/MP82 are connected to a programming line Vprog. The circuit 800 is programmed as described earlier for the circuit 600, except that the input line V*data receives the complement (as defined earlier) of the voltage applied to the input line Vdata, and these voltages are applied simultaneously. When programming is complete, the n-channel switching MOSFETs MN81 and MN82 turn OFF and the p-channel switching MOSFETs MP81 and MP82 turn ON. This switches both the floating gate MOSFETs M81 and M82 from connection to respective feedback circuits FBI and FB2 to connection jointly to the load MOSFET M83, and the circuit 800 is ready for use to receive an input data value x as described earlier with reference to Figure 1. In an array of circuits 800, there is one pair of input lines Vdata and V*data for each column, and for each row an injection line Vinj and a programming line Vprog. The arrangement of these lines is similar to that shown in Figure 6 with provision for the additional MOSFETs MN82 etc and associated circuitry.

Claims: CLAIMS 1. An electronic circuit incorporating: (i) first and second programmable threshold voltage transistors, a drain of each transistor being connected to a common output; (ii) input means for supplying analogue input voltages to a control gate of the first programmable threshold transistor, the analogue voltages corresponding to positions of reference and data points, characterised in that the circuit also incorporates: (i) means for supplying an analogue complement voltage to a control gate of the second programmable threshold transistor when the analogue input voltage is applied to the first programmable threshold transistor, the complement voltage being substantially the complement of the analogue input voltage supplied to the first programmable threshold transistor; (ii) programming means for supplying a predetermined programming voltage to the first and second programmable threshold voltage transistors, such that the supply of an analogue input voltage representing a reference point, in conjunction with the supply of the programming voltage, and the subsequent supply of an analogue input voltage representing a data point causes a current on the common output which is a function of the distance between the reference and data points. 2. An electronic circuit according to Claim 1 characterised in that the programming voltage is of sufficient magnitude to establish the first and second transistors at the onset of strong inversion, and the corresponding current on the common output is substantially proportional to the square of the Euclidean distance between the reference and data points. 3. An electronic circuit according to Claim 2, characterised in that it includes a diode-connected load transistor having a drain connected to the common output and arranged to produce an output voltage substantially proportional to the Euclidean distance between the reference and data points. 4. An electronic circuit according to any preceding claim characterised in that the first and second transistors have respective first and second floating gates. 5. An electronic circuit according to Claim 4 characterised in that it incorporates refreshing means for periodically refreshing charge stored on the floating gates. 6. An electronic circuit according to Claim 5 characterised in that the refreshing means includes first and second refresh transistors arranged to supply programming voltages to the floating gates. 7. An electronic circuit according to Claim 5 characterised in that the refreshing means includes respective conducting means connected to the first and second floating gates and activatable to conduct when exposed to ultra-violet light, ultra-violet window means arranged over the conducting means, and means for illuminating the conducting means with ultra-violet radiation. 8. An electronic circuit according to any preceding claim, characterised in that the programming voltages supplied by the programming means to each of the first and second programmable threshold voltage transistors are substantially equal. 9. An electronic circuit according to Claim 8 characterised in that the programming matching voltage is in the range 0.5V to 1.5V. 10. An electronic circuit according to Claim 9 characterised in that the programming voltage is in the range 0.75 V to 1.0 V. 11. An electronic circuit according to Claim 10 characterised in that the programming voltage is substantially 0.85 V. 12. An electronic circuit according to Claim 1, characterised in that the transistors are arranged for sub-threshold operation and the programming voltage is in the range 0.2 V to 0.7 V. 13. An electronic circuit according to Claim 1, characterised in that the transistors are arranged for sub-threshold operation and the programming voltage is in the range 0 V to 0.7 V. 14. An electronic circuit comprising (i) a programmable threshold transistor pair of like channel conductivity type and common output connection, (ii) means for programming the thresholds of the transistor pair to provide for output current to be a function of the difference between a programmed reference and subsequent transistor pair input voltages in complementary analogue form, and (iii) means for applying complementary analogue input voltages to the transistor pair. 15. An electronic circuit according to claim 14 including means for deriving square roots connected to the common output. 16. An electronic circuit including two programmable threshold transistors, characterised in that the circuit also includes: (a) means for programming the transistor thresholds such that each transistor is operative to exhibit an output current proportional to a quadratic or exponential function of the difference between a reference voltage and an input voltage according to whether it is operated above or below threshold; (b) means for applying respective input voltages to the transistors simultaneously, one input voltage being the complement of the other; and (c) means for summing the output currents of the transistors. 17. An electronic circuit including two metal oxide silicon field effect transistors (MOSFETs) each of the kind incorporating a control gate and a floating gate, characterised in that the circuit also includes: (a) means for storing charge on both floating gates such that each MOSFET is operative to exhibit a drain-source current proportional to a quadratic or exponential function of the difference between a reference voltage and an input voltage according to whether it is operated above or below threshold; (b) means for applying input voltages to the control gates of the MOSFETs simultaneously, one input voltage being the complement of the other; and (c) means for summing the drain-source currents of the MOSFETs. 18. An electronic circuit according to any preceding claim characterised in that each transistor has a current output connected to switching means, the switching means is connected to threshold programming means and to current summing means, and the switching means is operative to switch the transistor output current from the threshold programming means to the current summing means in response to attainment of a predetermined programmed threshold. 19. An electronic circuit according to any preceding claim characterised in that it is incorporated in an array of like electronic circuits. 20. An electronic circuit according to Claim 19 characterised in that each transistor has a current output connected to switching means, the switching means is connected to threshold programming means and to current summing means, the switching means is operative to switch the transistor output current from the threshold programming means to the current summing means in response to attainment of a predetermined programmed threshold and the circuit is connected to a pair of data input lines associated with a column of the array and to a threshold programming line and a switching activation line both associated with a row of the array. 21. An electronic circuit according to Claim 20 characterised in that the array is a one-dimensional and arranged for Euclidean distance determination involving a multidimensional data vector. 22. An electronic circuit characterised in that it is arranged for determination of distance between points represented in terms of analogue voltages. 23. An array of electronic circuits each incorporating a pair of programmable threshold transistors, characterised in that the array includes: (a) a respective programming means for altering the threshold of each transistor to provide for transistor output current to be a quadratic or exponential function of the difference between a reference voltage and an input voltage according to whether the transistor is above or below threshold, the programming means being responsive to the output current of the respective transistor; (b) input means for applying respective input voltages to the transistors in each pair simultaneously, one of the input voltages to each pair being the complement of the other; (c) summing means for adding the output currents of the transistors; (d) a respective switching means connected to receive output current from each transistor and operative to switch the transistor output current from the programming means to the summing means in response to attainment of a predetermined threshold by the transistor. 24. An array of electronic circuits each incorporating a pair of metal oxide semiconductor field effect transistors (MOSFETs) each of the kind incorporating a control gate and a floating gate, characterised in that the array includes: (a) a respective programming means for storing charge on each floating gate to provide for MOSFET drain-source current to be a quadratic or exponential function of the difference between a reference voltage and an input voltage according to whether the MOSFET is above or below threshold, the programming means being responsive to the drain-source current of the respective MOSFET; (b) input means for applying respective input voltages to the MOSFETs in each pair simultaneously, one of the input voltages to each pair being the complement of the other; (c) summing means for adding the drain-source currents of the MOSFETs. (d) a respective switching means connected to receive the drain- source current of each MOSFET and operative to switch that current from the programming means to the summing means in response to attainment of a predetermined threshold by the MOSFET. 25. An array according to Claim 23 or 24 characterised in that the circuits are connected to form rows and columns of the array, the circuits in each column have inputs connected to a respective pair of data input lines, and each row incorporates a respective programming line connected to the programming means of circuits therein and a respective switching activation line connected to the switching means of circuits therein. 26. An array according to Claim 23, 24 or 25 characterised in that the array is a one-dimensional and arranged for Euclidean distance determination involving a multidimensional data vector. 27. A method for determining a distance between two points represented by analogue voltages, and comprising the steps of:- (a) providing a circuit incorporating two programmable threshold voltage transistors connected to a common current output, (b) programming the threshold voltages of the transistors to provide for output current from the transistors to be a function of the difference between a programmed reference voltage and subsequent transistor input voltages in complementary form, and (c) applying analogue input voltages to the transistors, one such voltage being the complement of the other. 28. A method for determining a distance between two points represented by analogue voltages, and comprising the steps of:- (a) providing a circuit incorporating two programmable threshold voltage transistors connected to current summing means, (b) arranging the transistors to provide for their output current to be a quadratic or exponential function of the difference between a programmed reference voltage and subsequent transistor input voltages in complementary form, and (c) applying analogue input voltages to the transistors, one such voltage being the complement of the other.

Inventors: COLLINS STEPHEN, MARSHALL GILLIAN FIONA, COLLINS, STEPHEN, MARSHALL, GILLIAN, FIONA
Applicants: COLLINS STEPHEN, MARSHALL GILLIAN FIONA, SECR DEFENCE, COLLINS, STEPHEN, MARSHALL, GILLIAN, FIONA, THE SECRETARY OF STATE FOR DEFENCE
Application year: 1995
Main classification: G06G7
IPC codes: G06G7