Recovery of the propagation delay in a PWM circuit

Abstract: Switching and propagation delays in generating a PWM control signal by a circuit that generally includes an error amplifier, a sawtooth oscillator and a comparator for comparing the error signal with said sawtooth signal, is compensated by generating a second sawtooth signal synchronous with the master sawtooth signal but having a reduced discharge time and by applying said second synchronous sawtooth signal to the respective input of the PWM comparator.

Description: The so-called pulse width modulator circuit (PWM) constitutes a building block in many regulation and control circuits. A typical application of this circuit is in switching mode regulators including a voltage mode control loop. According to the diagram shown in Fig. 1, a sawtooth signal generated by a local oscillator and the output signal of an error amplifier are customarily applied to the inputs of the pulse width modulator (PWM). The function of a PWM is that of providing as output a turn-on or a turn-off command or information for opening or dosing a device, for example a power switch, depending on whether the error amplifier output is at a higher or lower potential than that of the sawtooth signal. This information is "stored" by the system and, if at the end of the oscillator discharge phase, that is of the descending portion of the sawtooth signal, the PWM output state is such as to impose the turn-off of the driven device, the power switch remains turned off until the next cycle. This function is illustrated by way of the signal diagrams shown in Fig. 2. The driving logic circuit of the device controlled by the PWM loop, which essentially comprises a bistable or flip-flop circuit, can be realized according to the embodiment shown in Fig. 3. In reality, both the PWM circuit and the driving logic circuit of the power device introduce a nonnull generation and propagation time of the PWM control signal, which is commonly due in a large measure commonly due to the triggering delay of the comparator of the PWM circuit and in a small measure to the propagation delay of the signal through the logic gates of the driving circuit. This propagation delay may, under certain operating conditions, create problems to the correct functioning of the system. The discharge phase of the oscillator, that is the discharge or descending ramp of the sawtooth signal produced by the oscillator, is generally faster than the charge or rising ramp, under conditions of a very low duty cycle, the output voltage of the error amplifier is relatively low. Such a voltage is approximately determined by the following expression: Under low duty-cycle conditions, the error amplifier output is low and it may occur that the propagation delay of the PWM signal be such as to provide a switch-on command to the power switch after the high-to-low transition of the clock signal. The occurrence of such situation is illustrated in the diagrams of Fig. 4. Therefore, in order to store the information (PWM output), the propagation time of the PWM signal must comply with the following expression: t PWM delay ≤ t 0 = t discharge OSC xD.C. This implies the need of employing a very fast comparator to prevent the occurrence of the above stated situation, in which a missed storing of the tum-on command of the power switch may cause the circuit to function at an irregular frequency the circuit. In order to avoid this problem linked to speed limitations of the circuits, the information supplied by the comparator of the PWM circuit should be allowed to be stored even in at an instant successive to the high-to-low transition of the clock signal. An usual method is that of employing instead of the system's clock signal, a modified clock signal whose duration is longer (delayed clock) so as to ensure the storing of the information provided by the output by the PWM comparator even under critical operating conditions of the circuit This solution is schematically shown in Fig. 5. Even though it is relatively simple to generate a "delayed clock" signal having appropriate characteristics for overcoming the aforementioned problem, this well known solution may introduce another problem. While the basic circuit either does or does not force the opening of the power switch in coincidence with the high-to-low transition of the clock signal, the use of a delayed clock signal permits the turn-on of the power switch at any instant of the time interval that elapses between the high-to-low transient of the master clock and that of the delayed clock. This causes repeated nonsynchronous turns-on that may create problems to the correct functioning of the entire system. Object of the present invention as it is defined in the appended claims is that of providing a better method and device for recovering or compensating the propagation delay of the signal produced by the comparator of a pulse width modulator circuit while safeguarding the maintenance of a perfect synchronism of the repeated switching-on with system's the clock signal. This purpose is fully attained by the method and by the relative device object of the present invention defined in the appended claims that are based on a modifying intervention of the discharge ramp of the sawtooth signal generated by the local oscillator. The modification introduced allows the application to the relative input of the PWM comparator of a sawtooth signal whose discharge ramp is made steeper, that is its duration is reduced by a fraction of time, sufficient to recover the propagation delay of the PWM signal. Although it would be sufficient to reduce the duration of the discharge ramp by a fraction of the expected maximum delay of (generation and) propagation of the PWM signal, it is more practical and effective to reduce the duration of the discharge ramp by an amount abundantly larger than the expected maximum propagation delay. For example, if an 80 ns propagation delay of the PWM signal is established, a time reduction of 100 ns of the duration of the discharge ramp of the sawtooth signal will assure the correct functioning even under particularly critical conditions. In this way, the propagation delay will always be amply and positively compensated or recovered, by anticipating the crossing instant between the so-modified sawtooth signal and the output signal of the error amplifier. The system of the invention eliminates any need of employing a second (delayed) clock signal. The way by which the descending portion of the sawtooth signal produced by the local oscillator is made steeper can be different. Basically it is sufficient to accelerate the discharge process by forcing a certain discharging current higher than that of the sawtooth oscillator would provide for. The various aspects and relative advantages of this invention will become even more evident by way of the following description of some important embodiments and by referring to the attached drawings, wherein: Figure 1 shows, as mentioned above, a typical scheme of a voltage mode regulation loop that includes a pulse width modulator; Figure 2 , depicts the functioning of the PWM regulation loop by illustrating the forms of the respective signals; Figure 3 is an example of a driving logic circuit of a power switch controlled by a PWM loop; Figure 4 highlights the problem of a missed storing of the turn-on command under particularly critical operating conditions of the PWM controlled loop; Figures 5a and 5b show a well known solution based on the use of a dedicated delayed clock signal, as already described above; Figure 6 is a block diagram of a PWM circuit realized according to the present invention; Figure 7 shows the functioning of the circuit of this invention by illustrating the respective signals; Figure 8 illustrates a possible embodiment of the speeding up block of the discharge ramp of the basic scheme of Fig. 6. By referring to the diagram of Fig. 6, the system of the invention is practically realized by introducing a speeding up circuit block of the discharge or descending ramp of the sawtooth signal generated by the oscillator. In practice, the circuit block SPEED UP OF DISCHARGE FRONT receives as an input the sawtooth signal OSC generated by the oscillator and produces as an output a new sawtooth signal NEW_OSC, substantially synchronous with the OSC input signal, but having the discharge or the descending ramp made steeper and such as to reach the minimum value in a reduced time interval as compared to that of the input sawtooth signal OSC, as generated by the local oscillator. The period of the NEW_OSC signal remains substantially unchanged and identical to the period of the input signal OSC. The first diagram of Fig. 7 shows the effect produced by the circuit block SPEED UP OF DISCHARGING FRONT on the sawtooth signal OSC generated by the oscillator. The speeding up of the discharge, that is of the discharge ramp of the sawtooth signal, anticipates the crossing with the output signal of the error amplifier E/A, thus practically preventing the occurrence of a missed storage of a turn-on command, even under conditions of accentuated delay of the PWM signal and of a particularly low value of the output voltage of the error amplifier E/A. For sake of immediate comparison, the original discharge ramp of the sawtooth signal OSC produced by the oscillator is indicated by way of dashed lines in the diagram of Fig. 7. It will be evident to the expert reader that the speeding up of the discharge ramp of the sawtooth signal may be circuitally implemented in many ways. Fig. 8 shows a particularly appropriate embodiment of such a circuit. By referring to the scheme of Fig. 8, the sawtooth signal OSC, generated by the oscillator, is applied to the input of the circuit represented by the base of transistor Q1, whose current is identical to that flowing through M4, M9 and M10 by realizing, together with Q3 and Q4, a voltage follower. The current levels are such as to produce a substantially negligible phase shift between OSC and NEW_OSC, at the frequencies of operation. The particular input structure (Q1 and Q2) is substantially due to the need of ensuring an appropriate voltage withstanding capability when, under particular operating conditions, the OSC pin would become tied to the supply voltage. For similar reasons, M8 is used as a level shifter in order to prevent possible breakdowns of M6. The PMOS M5 limits the maximum current that M10 may carry. Indeed, when the OSC discharge phase starts, the signal OSC_DISCHARGE goes high so that M11 anticipates the discharge signal of the NEW_OSC. While the NEW_OSC level drops rapidly, the source of M10 follows it, causing an increase of the Vgs of the VDMOS, which therefore delivers a higher current. This higher current partly or totally compensates the discharge current of the NEW_OSC (which is obtained by an appropriate dimensioning of M11), thus nullifying the effect of the entire circuit at a certain point of the discharge ramp. Q6, Q7, M12, M13 and M14 realize a "clamp" capable of fixing the amplitude of the NEW_OSC signal which in the embodiment of the example is equal to 0.89V, while the minimum threshold of the OSC signal is 0.9V. M15, M16, M17 and M1 realize a circuit capable of increasing the current through the "clamp" circuit during the discharge ramp in order to avoid that the amplitude of input signal NEW-OSC may decrease excessively.

Claims: A method of compensating the generation and propagation delay of a control signal generated by a pulse width modulation circuit that includes an error amplifier, a sawtooth oscillator (oscillator) and a comparator capable of comparing an error signal amplified by said amplifier with a sawtooth signal generated by said oscillator, characterized in that comprises generating a second sawtooth signal synchronous with the sawtooth signal generated by said oscillator but having a discharge time shorter than the discharge time of the first sawtooth signal by an interval of time sufficient to compensate such delay; (speed up of discharge front) applying said second sawtooth signal to a respective input of said comparator. Method according to claim 1, characterized in that said time interval is substantially greater than said delay. A pulse width modulator circuit comprising an error amplifier, a sawtooth oscillator (oscillator) controlled by a timing clock signal (CK), a comparator of an amplified error signal with a sawtooth signal generated by said oscillator and at least a logic circuit capable of receiving as input an output signal of said comparator and said clock signal and capable of producing as output a logic drive signal for a controlled device, characterized in that comprises a circuit (speed up of discharge front) for speeding up the discharge ramp of said sawtooth signal having an input coupled to the output of said oscillator and an output coupled to the respective comparator input. The circuit according to claim 3, characterized in that said speeding up circuit reduces the duration of the discharge ramp of the sawtooth signal by a time interval equal or greater than the sum of the triggering delay of said comparator and of the propagation delay throughout said logic circuit.

Inventors: CAPICI SALVATORE V, MAGAZZU ANTONIO, CAPICI, SALVATORE V., MAGAZZU, ANTONIO
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO - CORIMME
Application year: 1995
Main classification: H03K3
IPC codes: H03K7, H02M3, H03K5, H03K6