A METHOD AND AN APPARATUS FOR ENABLING A PROCESSOR TO ACCESS AN EXTERNAL COMPONENT THROUGH A PRIVATE BUS OR A SHARED BUS

Abstract: A method and apparatus for enabling a processor (156) to access an external component (158a-n) through either a private bus (146) or a shared bus (148). One embodiment of the present invention is an external memory access apparatus which includes an external memory access unit (144). This external memory access unit (144) couples to the processor (156) through an external memory access unit bus (142). In addition, the external memory access unit (144) couples to external memory (158a-n) through a private bus (146). The external memory access unit (144) also couples to the external memory (158a-n) through a shared bus (148), which also couples an external component, one of (150), (152) or (154), to the external memory (158a-n).

Description: A METHOD AND AN APPARATUS FOR ENABLING A PROCESSOR TO ACCESS AN EXTERNAL COMPONENT THROUGH A PRIVATE BUS OR A SHARED BUS BACKGROUND OF THE INVENTION 1 • Field £_£ _£ invention The present invention relates to the field of computer systems, and particularly to a method and an apparatus for enabling a processor to access an external component through either a private bus or a shared bus . 2. Art Background ' In recent years, an increasing nurruoer of (e.g., digital signal processors that use a RIC like architecture) have increased tne r instructions execution speed by simplifying or eliminating their microcodes. For instance, one a t at this simplification/eliminat on, r.as increased tne pr c^ε cr instruction execution speeds is r reducing ::.- instruction decoding and execution time. In fact, presently, a number of processors, that use a FISC iι - architecture, can αecode ana execute an instruction w; in just one clock cycle. To take advantage of this reduced instruction decode and execution time, and to increase further the processor instruction execution speed, a method for reducing the data access time (i.e., the time needed to provide a processor requested data word to the processor) is needed. In addition, a method for reducing the data access time nas been long-sought in digital signal processing applications which require tne digital signal processor to receive a maximum amount of multi-media data in real time. Figure 1 presents one prior art data accessing method. As shown in this figure, this prior art approach reduces the data access time by placing an internal data memory bank 100 in processor 1C2. Arithmetic logic unit (i.e., ALU) 1C4 can then access a data word in a few clock cycles by supplying aααresses cf particular memory cells (storing tne data word) tc the internal data memory bank. In turn, the internal data memory bank decodes these addresses, ana provides the requested data word (at tne supplied addresses) tc the ALU by driving tne appropriate bit l re. ar.d cer.E- amplifiers. However, since tne space on a - c c is limited and since memory cell arrays consume a relatively large amount of die space, only a I rritea amount of data can be stored internally, wnicn tnereny iirr.i s the amount cf data that tne ALU can ccess under this prior art data accessing method. Consequently, this prior art data accessing method does not sufficiently reduce the data access time because it only enables the ALU to access a limited amount of data in this manner. In addition, this prior art internal data accessing method does not provide the shortest data access time because at times ALU 104 has to terminate its data access to allow other components of the computer to access the data memory. Thus, as prior art internal data storage methods do not sufficiently reduce the data access time, several prior art external data accessing methods have been developed. Figure 2 presents one example of a prior art external data accessing method. As shown in this figure, this prior art approach stores data in the surplus memory of the program memory. However, this prior art data accessing method also αoes not sufficiently reduce the data access time, because it uses one instruction bus 110 to relay botn instructions and data to processor 112. More specifically, this prior art approach requires tnree entire clcc cycles t: access a data word, where (1) ouring tne first ilock cycle, processor 112 receives an instructicn word, (2) during the second clock cycle, processor 112 decodes tne instruction, and (3) during the third clock cycle processor 112 Generates a data address and react the data. In addition, this prior art approach does not sufficiently reduce the data access time because often processor 112 has to terminate its data access to allow other components of the computer to use the instruction bus to access the data memory. For example, occasionally the processor has to terminate its data access so as to allow an external system memory to store additional information in the data memory. Figure 3 presents a second prior art method for accessing external data. This prior art method uses separate instruction bus 120 and data bus 122 to respectively couple a processor 124 with separate instruction memory 126 and data memory 128. However, for several reasons, this prior art external data accessing method also does not provide the shortest data access time. First, this prior art external data accessing method does not provide the shortest data access time as it requires the processor (1) tc make a separate data request for each individual data word to data memory cell array 128, and (2) to wait idly by until the data memory cell array supplies the requested data. Second, the access time is adversely affected because, in order tc communicate to data memory 128, processor 124 has to drive a data bus which s highly capacitive due to the large number of components that are coupled to it . Third, the prior art external memory accessing method of Figure 3 does not sufficiently reduce the access time because at times the processor has to terminate its data access to allow other components of the computer to use the data bus to access the data memory. For example, the processor has to occasionally terminate its data access so as to allow an external system memory to access the data memory. This prior art data accessing method increases the size of the data memory cell array, in order to reduce the data access time by reducing the number of times that processor 124 has to terminate its data access to allow an external system memory to store additional data in data memory bank 128. However, this prior art solution is not an optimal solution because increasing the size of the data memory cell array increases the cost of the computer system. In addition, this prior art soluticn cannot re¬ used when due to design constraints a d space limitations, the size of the data memory cell array cannot be enlarged. SUMMARY OF THJ? INVENTION The present invention provides a method and an apparatus for enabling a processor to access an external component through either a private bus or a shared bus . One embodiment of the present invention is an external memory access apparatus which includes an external memory access unit. This external memory access unit couples to the processor through an external memory access unit bus. In addition, the external memory access unit couples to external memory through a private bus. The external memory access unit also couples to the external memory through a shared bus, which also couples an external component to the external memory. BRIEF DESCRIPTION OF THE DRAWINGS The objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, wherein: Figure 1 presents one prior art data accessing method that reduces the data access time by internally storing the data. Figure 2 presents one prior art external data accessing method that stores the data in the surplus memory of the program memory . Figure 3 presents another prior art external data accessing method which stores the data in an external data memory. Figure 4 presents a computer system architecture which incorporates one embodiment of the external memory- access apparatus of the present invention. Figure 5 presents one embodiment of an external memory access unit bus, an external memory access unit, a private bus, ana a shared bus used in memory access apparatus of Figure 4. Figure 6 presents one embodiment of a private and shared bus interface used in the external memory access unit of Figure 5. Figure 7 present one embodiment of the timing diagram for a block read access operation of the shared and private bus interface of Figure 6. Figure 8 presents one embodiment of the timing diagram for a block write access operation cf the shared and private bus interface of Figure 6. Figure 9 presents one embodiment of a state machine block used in the external memory access unit of Figure 5. Figure 10 presents one embodiment of a state diagram for a private bus state machine of the state machine block of Figure 9. Figure 11 presents the timing diagrams for the operation of one embodiment of a state machine output generator of the state machine block of Figure 9, during a block read access through the private bus. Figure 12 presents the timing diagrams for the operation of one embodiment of tne state machine output generator of the state machine block cf Figure 9, during a block write access through the private bus. Figure 13 presents the timing diagrams for the operation of one embodiment of the state machine output generator of the state machine block of Figure 9, during a read after write access through the private bus . Figure 14 presents one embodiment of a state diagram for a shared bus state machine of the state machine block of Figure 9. Figure 15 presents the timing diagrams for the operation of one embodiment of the state machine output generator unit of the state machine block of Figure 9, during a block read access through the shared bus . Figure 16 presents the timing diagrams for the operation of one embodiment of the state machine output generator unit of the state machine block of Figure 9, during a block write access through the shared cus . Figure 17 presents the timing diagrams fcr the operation of one embodiment cf the state machine output generator unit of the state machine block of Figure 9, during a read after write acce s s tnrough tne snared bus . Figure 18 presents the timing diagrams f- r the operation of one embodiment of the state machine output generator unit of the state macnine block of Figure 9, durinσ a write access tnrouαh the snared ru. w.-.e tne shared bus grant signal is removed and the processor has not locked the shared bus . DETAILED DESCRIPTION OF THE INVENTION In the following description, numerous details are set forth in order to provide a thorough understanding of the present invention. However it will be understood by one of ordinary skill in the art that these specific details are not required in order to practice the invention. For example, although for purposes of explanation the following description pertains to a method and an apparatus to access external data memory, it will be understood by one of ordinary skill in the art that the present invention can be used by a processor to access any external memory (e.g., an instruction memory) or any other external componen . In other instances, well-known electrical structures and circuits are shown in block diagram form in orαer not tc obscure the present invention with unnecessary detail. 1. External Memory Acces s Apparatus The present invention provides a method and an apparatus for enabling a processor tc access an external component through eitn r a private D S or a snared DUS . Figure 4 presents a computer system architecture tnat incorporates one embodiment cf the external component accessing apparatus of the present invention. In the embodiment cf the present invention tnat is set forth in Figure 4, the external component accessing app aratus is an external memory accessing apparatus for enabling processor 156 to access N data memory banks 158. However, it is to be understood that the external component accessing apparatus of the present invention can enable the processor to access any number of alternative external memory banks (e.g., N instruction memory banks) or any number of alternative external components . As shown in Figure 4, external memory accessing apparatus 140 includes external memory accessing unit bus 142, external memory accessing unit (EMAU) 144, private bus 146, shared bus 148, shared bus arbiter 150, direct memory access unit 152, data memory bank controller 154, and N data memory banks 158. Processor 156 uses external memory access apparatus 140 to minimize its data access time. More specifically, processor 156 is an ordinary processor with limited internal data storage capacity and with limited addressing capability for accessing data. In one embodiment of the present invention, processor 156 is a digital signal processor (DS?) with a RISC like architecture, which allows the DSP to decode and execute an instruction word in just one CICO cycle. Consequently, in order to take advantage cf this reduced instruction decode and execution time, and tc increase further the instruction execution speed cf the DSP, DSP 156 uses external memory access apparatus 140 to minimize its data access time. In addition, program instructions are stored externally in program RAM 160, while data words are stored externally in data memory banks 158. Processor 156 then uses program bus 162 tc access program RAM 160, while using external memory access apparatus 140 to access data memory banks 158. Processor 156 also uses EMAU bus 142, EMA'J 144, and shared bus 148 to access numerous external components that are coupled to shared bus 146. Some examples of these external components coupled to the shared bus are an external processor, an external system memory, or an external serial port communicating information to/from other external components not coupled to the shared bus from/to external components coupled to the shared bus. In addition, in the embodiment of the present invention set forth in Figure 4, processor 156 communicates to shared bus arbiter 15C, data memory controller 154, ana direct memory access unit (DMA) 152, through EMAU bus 142, EMAU 144, and shared bus 148. Shared bus arbiter 150 allocates control of tne shared bus among a nu oer of bus masters (e.g., EMAU 1 4 and DMA 152) , by determining whether another bus master is accessing th- shared bus, and if so oy then determining whetner that particular accessing bus master has a higher priority status than a bus master requesting access to the shared bus . Numerous well known bus arbiters can be used as shared bus arbiter 150. For example, one embodiment of shared bus arbiter 150 is the system arbitration logic unit used in computer system architectures that use a PCI bus . Some of these bus arbiters are coupled to each bus master through an individual request line and an individual grant line. Other bus arbiters couple to all the bus masters through a common request line and a common grant line, by time multiplexing each bus master's access time to each of these lines. Yet other arbiters also use a common request line and a common grant line to couple to all the bus masters, but (rather than using time multiplexing techniques) use decoders in the arbitrators and the bus masters to determine which bus master has made a request on the request line and which bus master has been granted a shared bus access o the grant line . Irrespective of the way snared bus arbiter 150 couples to the bus masters through the request and grant lines, for one embodiment of the present inventis:., trit arbiter operates in the following manner . In .rάe to gain access to the snareα pus, a pus master forces the signal on its request line tc a first logical state (e.g., a "1" logic level) . When arbiter 1 0 decides to grant access to the shared bus to the requesting bus master, the arbiter forces the signal on the grant line to a second logic state (e.g., a "1") for that bus master. When the arbiter later wants to terminate a particular access to the shared bus, the arbiter forces the signal on the grant line of the accessing bus master to a third logic state (e.g., a "0") , which in turn causes the accessing bus master to terminate its access to the shared bus and to force the signal on its request line to a fourth logic state (e.g., a "0") in the next clock cycle. Consequently, before initiating a communication through the shared bus, processor 156 initiates a communication with shared bus arbiter 150 in order to obtain permission to drive the shared bus. More specifically, to gain access to the shared bus, processor 156 requests the EMAU to initiate an external access through the shared bus. EMAU 144 then forces the signal on its request line to the first logica- state, and awaits until the arbiter forces the signal on its grant line to the second logical state (which signifies that the arbiter has granted access to tne snared PUS t; the EMAU) . Tne EMAU ' s access to the snared ru_ can be terminated by the arbiter, if tne aroiter forces the signal on the grant line of tne EMAU tc tne tmrd logical state, which in turn causes the EMAU to terminate its access to the shared bus and to force the signal on its request line to the fourth logical state in the next clock cycle. As mentioned below, however, the processor can program the EMAU to refuse to terminate its access to the shared bus (i.e., can program the EMAU to lock the shared bus), by refusing to force the signal on its request line to the fourth logical state in response to the arbiter forcing the signal on the grant line to the third logical state. Processor 156 also communicates through EMAU bus 142, EMAU 144, and shared bus 148 to data memory bank controller 154. Through activating a particular number of control lines (not shown in Figure 4) that couple data memory bank controller 154 to N data banks 158, the data memory bank controller allocates the data memory banks to a particular bus (i.e., causes the data memory- banks to receive information from either the s ared bus or the private bus) . The bus masters access data memory- bank controller 154 through the shared bus in order to request controller 154 to allocate a particular data memory bank to a particular bus. If the data memory- bank controller decides to allow a particular bus master to access a particular data bank, it transmits control signals through the control lines that couple _t to the data banks. The data banks then decode these control signals in order to determine whether they are going to be accessed and if so whether they should receive information from the shared bus or the private bus. After informing the requested data bank that it will be accessed through either the shared or private bus, the data bank memory controller signals its permission to the bus master on the shared bus. Upon receiving permission to access the particular data bank, the requesting bus master initiates a data access to the requested data bank through either the shared bus or the private bus . For the embodiment of the present invention that is shown in Figure 4, EMAU 144 is the only bus master that is allowed to access the data memory bank through either the private bus or the shared bus. In other words, the only bus master that can access a particular data memory- bank through the private bus is EMAU 144. This embodiment of the present invention only allows the EMA " to access the data banks through the private bus, in order to reduce the data acces s time of processor 15c ry preventing interruptions in tne processor's data access that are due to the other components accessing a particular data bank. More specifically, the processor's data access time is minimized because processor 156 does not have terminate its αata access t: allow other components of the computer system to access the data banks. Rather, processor 156 can acc-=ss a particular data bank through the private bus, while allowing another component to access another data bank through the shared bus. In addition, this embodiment of the present invention only allows the EMAU to access the data banks through the private bus in order to reduce the data access time of processor 156 by preventing the private bus from being heavily loaded. For the embodiment of the present invention set forth in Figure 4, processor 156 also uses EMAU bus 142, EMAU 144, and shared bus 148 to communicate to direct memory access unit (DMA) 152. Direct memory access unit 152 couples a number of external components (e.g., an external system memory, which is not snown in Figure 4) to the data banks tnrough shared Pus 148. In turn, these external components can access a particular data bank through this shared bus coupling when EMAU 144 is not accessing it through private bus 146. In addition, processor 156 communicates tc DMA 152 in order to program the DMA to cause external components tc access a data bank that the processor wants them tc access. For example, when tne processor finisnes accessing a data bank, it may wisn that the contents of that data bank be examined by an external component. Consequently, it accesses the direct memory access unit (through the external memory access unit ar.α tne snared bus) and programs this unit to provide the contents of this data bank to the external component . As mentioned before, in order to minimize its data access time, processor 156 uses EMAU bus 142, EMAU 144, and either private bus 146 or shared bus 148 to access N data memory banks 158. In other words, the external memory access apparatus of the present invention allows the processor to have a short data access time. For example, when processor 156 accesses a data memory bank 158 through private bus 146, the external memory access apparatus 140 enables the processor to access X locations in the data memory in X+Y clock cycles when a write operation is undertaken and X + Y i- Z clock cycles when a read operation is undertaken, where (I) X represents the number of locations accessed in the data memory, (2) Y represents the number cf clock cycles needed to program the EMAU, and (3) Σ represents the number of clock cycles needed to prefetch data for the read operation. For the embodiment cf the present invention set forth in Figure 4, programming clock cycles Y equals two, and prefetching clock cycles Z equals two. In addition, when processor 156 uses snared bus 148 to access a particular data memory ban.-:, external memory access apparatus 140 allows the processor to access Y location in the data memory in X - Y + W clock cvcles when a write operation i; undertaker. and X + Y + Z + W clock cycles when a read operation is undertaken, where W represents the number of clock cycles that the EMAU awaits until the arbiter grants it access to the shared bus. As further discussed below, when processor 156 wishes to initiate an external access through either the private bus or the shared bus, the processor first programs the EMAU during an initial program phase. For instance, during the initial program phase, processor 156 informs the EMAU of an initial address of an external component for the EMAU to access through either the shared or private bus. During the initial program phase, processor 156 also informs the EMAU whether it requires the EMAU to initiate a block external access operation or a single external access operatic:.. If processor 156 requests a block external access operation, the processor also informs the EMAU cf the size of the block, the step size, and the particular block mode accessing method (i.e., incremental or decremental accessing method) . Furthermore, processor 156 also informs the EMAU wnetner after initiating an access through the shared bus, the EMAU should refuse t" release its access in response tc tne arbiter removing its grants signal (i.e., whether the EMAU should locκ the shared bus) . If the external access, that processor 156 reαuests EMAU 144 to initiate, is an external data access, the programmed information also informs the EMAU whether it should access the data banks through the private or the shared bus . After the EMAU is programmed, the processor then initiates a communication between the processor and the external component through the EMAU, by providing an external read or write command (e.g., a read or write command directed to one of the external data registers of EMAU 144) . 2. External Memory Access Unit Bus For one embodiment of the present invention, Figure 5 presents a more detailed view of EMAU bus 142, EMAU 144, private bus 146, and shared bus 148 of Figure 1. As shown in this figure, the EMAU bus includes external data bus lines 18C, external input/output access bus line 182, EMAU register bus lines 164, read/write bus line 186, and stop processor bus line 188. For the embodiment of the present invention shown in Figure 5, external data bus lines 180 are 16-bit lines used to transmit 16-bit data words between processor 156 and EMAU 144. In addition, external input/output access bus line 162 is a 1-bit line, wnicr. processor 156 uses to supply an external input output access signal to the external memory access unit . This external input/output access signal in turn informs the external memory access unit that the processor wishes tc initiate an external input/output access, and thereby causes the external memory access unit to examine the other signals that the processor transmits over the EMAU bus . EMAU register bus 184 is a 2-bit line bus, which the processor uses in order tc communicate to particular registers in the EMAU. In otner words, processor 156 uses EMAU register bus 184 to direct its communications with specific EMAU registers. The EMAU bus also includes read/write bus line 186 which the processor uses to inform the EMAU that its external access involves a read operation (i.e., an input operation) or a write operation (i.e., an output operation) . Finally, the EMAU bus includes a stop processor bus line 188, which the EMAU uses to halt tne operations of Processor 156. Fcr ample, for e err.ccd mentc o processor 156 that α: not have a wait state ma:nme, tn- EMAU uses step processor line 168 tc senα a stop processor clock signal tc clock gating circuitry in fh~ processcr m order to stop tne operation of tr. processor. On the other nand, for tne emncαimer.t cf processor 156 that αo nave a wait state m cn n- , EMAU 144 sends a wait signal to the wait state m cnine in order to cause the wait state machine to force processor into an idle state. Tne EMAU sends the stop processor clock signal or the wait signal to the processor either (1) when clock module 202 sends a stop request signal to the EMAU, in order to power down the processor and the EMAU, or (2) when, during an initial prefetch phase of the read operation, the EMAU has to stop the processor for two clock cycles . Although for purposes of explanation Figure 5 sets forth particular bit lines nu oers for EMAU pus 142, it should be understood that in alternative embodiments of the present invention the EMAU bus has different widths. For example, although for purposes of explanation Figure 5 presents a 16-bit line external data bus transmitting 16-bit data wards, it should be understood that for alternative emnodiments of the present invention external data bus 180 can have alternative widths or can transmit data words having different bit sizes. Consequently, one embodiment of EMAU 144 receives 8-bit data words and uses sign extension techniques tc relay 16-bit data wcrαs to processor 156. 3. Private an. Shared £^s_££ For one embodiment cf tne present invention, Figure 5 also presents a more αetaiied view cf the private bus and shared bus cf tne present invent ior.. As shown in this figure, each of tnese puses _r.eludes a read bus line 256 a.oα a write PUS lιr.~ 2C r . Tnese read and write bus lines are used in the private ana shared buses in order to inform an external component, which the processor is accessing through the EMAU, tnat the processor wishes to perform a read or a write operation In addition, the private bus and tne shared bus both have 16-bit line address buses 210, which they use to transmit the address of the externally accessed component. Finally, both these puses nave 16-bit line bi-directional data buses 212, w.oicr. art used ~ c relay- data signals between processor 156 ana tne externally accessed component . Although for purposes of explanation Figure 5 presents specific widths for the private and of the shared bus, it should oe understood that for alternative embodiments of tne presert invention these buses can have alternative widtns. 4. External Memory Access U_nϋ Figure 5 also presents one ernoαimer.t of tne external memory access unit cf tne present :r.-" r.t:cr.. As shown m this figure, tne external mere y a,cetc u it includes EMAU cloc generator 192, snare ^ ana ; πvate bus interface 190, and state r.acnine r_-.ee-. 1.- Tne EMAU cloc generator receives ccc.-: sιgna_c fr r syste m - clock module 202, strengtnens tnese dec--, oicr.αls, ana provides (along lines 198) t ese strengtneneu signals t: state machine b!oc. 194 and to snares and pr.vate PUS interface 190. As shown in Figure 5, state machine bloc.-i 194 receives the shared bus grant and shared bus request signals from arbiter 150, in order to determine when processor 156 can access the shared bus througn the external memory access unit. Also, as mentioned before, state machine block 194 receives a stop request signal (on stop request line 200) from system clock module 202, in order to cause the processor and the EMAU to power down. Furthermore, as further αescribed below, state machine block 194 receives tne signals en external I/C access bus 182, EMAU register PUS 184, read 'write bus 186, EMAU control bus 204, ana the shared bus grant line, in order to determine when an external access can be initiated. Upon determining that an external access can be initiated, state machine block 194 then transmits (on EMAU control bus 204) enable signals to sr. reα and private bus interface 190, in orαer to cause it tc initiate an external data access in response to an external read or write command from the processor. In other words, state machine bloc.-'. 194 monitors tne signals that processor 156 transmits to shared and private bus interface 195, εc tnat it ear. G n rate enable signals which control ::.t operation cf ...tared and private bus interface 195 (and there:;.- centre-, tne operation of EMAU 144) . Shared and private bus interface 190 houses a number of registers that processor 156 programs during the initial program phase. Processor 156 controls the programming of the registers of shared and private bus interface 190 through control signals transmitted along external I/O access 182, EMAU register 184, and read/write bus 186. In addition, through external data bus 180, processor 156 transmits programming signals tc particular registers of shared and private bus interface 190. Furthermore, shared and private bus interface 19C uses external data bus 180 to relay information to/ from processor 156 from/to external components (e.g., external data memory banks 158) . Finally, shared and private bus interface 190 uses EMAU control PUS 204 to transmit/receive control signals to 'from state machine block 194. . Shared nd p jyate &_S Interfaςe Figure 6 presents a mere detailed view of one embodiment of shared and private PUS interface 1 5 of EMAU 144 of Figure 5. As snewn in tr.is figur- , snare:; and private Pus interface 195 includes cos ir.t-rfac-r control unit 220, external access control register (EACR) 222, external read address unit (ERAU) 124, external write address unit (Ξ AU) 235, extern.-- data rea: reqi st e r ε ( EDRR ) 22 6 , rec . ste r ( EDV:? ) processor 156 through the external data bus 180, external I/O access bus 182, EMAU register bus 184, and read/write bus 186. Control unit 220 is a decoder that controls the communications between processor 156 and the external registers of shared and private bus interface 190. For instance, control unit 220 prevents any signals on the EMAU bus 142 from reaching the registers of shared and private bus interface 190 until the processor indicates the initiation of an external access on external I/O acces s ouε line 182. Upon detecting an external access signal on external I/O access bus 132, control unit 220 then determines whicn register tne processor wishes to communicate with by examining the signals on the EMAU register bus 184. As mentioned before, for one embodiment of the present invention, the EMAU register ΓJUΞ has two bit lines. Consequently, for this embodiment of tne present invention, Table 1 sets forth the decoding logic used by control unit 220 to determine the external register 'of bus interface ISO) that processor 156 is comrr.unicatmσ with Once control unit 220 determines which external register of shared and private bus interface processor 156 wishes to communicate with, control unit 220 enables the requested external register while disabling tne rest of the external registers of bus interface 190. Control unit 220 then directs the signals on the external data bus 180 and the read/write bus 186 to the requested register, in order to initiate communication between the reσuested register and the processor. As further shown in Figure 6, control unit 220 receives clock signals on clock bus 193. Control un t 220 uses the clock signals for its operation and transmits (v a bus interface control bus 2ΞZ the clock signals to the external registers of the shared and private bus interface. As further shown in Figure 6, control unit 22C also receives signals from state machine block 194 along EMAU ccr.trcl bus 204. As shown, in this figure, the control lines that state machine block 194 uses to communicate with shared and private bus interface 190 include a counter enable line, which the cor.tr:! unit -uses tc transmit a counter enable signal to external address units 224 or 230 after processor 156 has initiated a communication with external address units 224 or 230. The control lines that state machine bloc.-: 194 uses to communicate with shared and private bus interface 190 also include shared and private bus read and write enable lines. The signals on these lines are transmitted by the control unit to external memory interface unit 238 along Duε interface ccr.tr:! cus 232 and enable bus 234. Based on these snareα ana private read and write enable signals, external memory interface unit 238 determines whether the shared bus or the private bus is being requested for a external access and if so whether the external access involves a read or write operation. Consequently, if external memory interface unit determines that the private bus is oeir. request far an external read, external memory interface unit 225 tri- stateε ail the bus lines on tne snared bus, deactivate; the private bus write nuε line, ana activates tne private bus address DUE, αata DUE, ana reaα ti line. On the other hand, if the processor requests tne pπvatr- bus for an external write, external memory interface unit 23δ tri-states all the bus lines on the snared bus, deactivates the private bus read bus line, ana activates the private bus address nu: , αata cus, ana wri" e cus line. However, if processor 156 has requested an external read along the shared bus, external memory interface unit 238 deactivates all the bus lines on the private bus, deactivates the shared bus write bus line, and activates the shared bus address bus, data bus, and read bus line.. Finally, if the processor requests an external write along the shared bus, external memory interface unit 238 deactivates ail the bus lines on the private bus, deactivates the shared bus read bus line, and activates the shared bus data bus, address bus, ana write bus line . a . External Access Control Register As mentioned before, in order tc initiate an external data access, processor 156 initially programs EMAU 144 during an initial programming phase. Fcr the embodiment of shared and private bus interface 191 wnicr. is shown in Figure 6, the programming operatic, is as follows. During the first cycle cf tne two-cycle initial programming phase, prccesεcr 156 prcgrarrε external access control register 222. Frccess : 156 initiates r.is crcαrammir,α cf t al acceε: i€αist r 222 by first indicating an external input tr : .tput access on external I 'C access line 181. Frccesscr 156 also transmits a "CO" on tne EKA ' l register bus, in αrαer to inform control unit 220 that it wishes tc cr.mmur.icate witn P 1-e>rr;a1 cc 156 then programs in EACR 222 a first control word by asserting a write on read/write bus 186 and transmitting the first control word to shared and private bus interface 190 through external data bus 180. Table 2 sets forth one example of the first control word. The ninth and tenth bits of the first control word indicate whether the processor plans to initiate a single access or block access operation. If a block access operation is desired, these ninth and tenth bits also indicate whether the processor wishes an incremental or decremental block mode operation. Table 3 sets forth one manner through which the ninth and tenth bits are used to indicate the mode of access operation. EACR 222 then informs either address counter unit 244 or 247 (in either the ERAU 224 or EWAU 230) of the type of access operation processor 156 has requested. If processor 156 requests either type of block mode access operation (i.e., the auto-increment or auto- decrement block mode access operation) , the first 8-bits (i.e., the loop size bits) of the first control word determine the size of the accessed block (i.e., the loop size) . These first 8-bits allow the processor to select any block size from 1 to 256. External access control register 222 provides this block size tc either address counter unit 244 or 247. Processor 156 also uses the eleventh bit of the first control word to program the mode of accessing. More specifically, if processor 156 has reσuested a block mode access, the eleventh bit informs the EMAU that the step size cf the increment cr aecrement will re either one or two. This ability cf the present invention to allow the processor to program the step size of two is advantageous in OS? application.,, because it allows the processor tc access either only real or only imaginary data, wner. real and imaginary αata components are stored in tne data memory as a - ' asent data words. External access control register _22 in turn informs either adαress counter 224 cr 247 cf this step size . The twelfth bit of the first control word determines whether the EMAU will lock the shared bus. More specifically, if this shared bus lock bit is set (i.e., has a value of "1") and if sixteenth bit of a second control word (which, as mentioned below, processor 156 programs into either ERAU 224 or EWAU 230) indicates that the EMAU should initiate a data transfer through the shared bus, the EMAU will lock the shared bus after its request has been granted by arbiter 150. Consequently, if the EMAU accesses the shared DUS after processor 156 has requested it to lock the shared bus, the EMAU will not bring its shared bus request signal low (lowering the shared bus request signal would allow the arbiter to grant access to the shared bus tc another bus master) even after the arbiter removes its shared bus grant signal. After locking the shared bus, the EMAU does not unlock the shared bus automatically after the processor finishes its access through the snared bus. More specifically, in order fcr the EMAU to release its lock on the snared bus, processor 156 has tα re-program the external access central register (i.e., processor 156 has to write another central ward in the EACR 221, whose 12-bit is clear (nas a value α " " ") ) . This ability cf the procesεcr tc retain it: -.: :/. an the shared bus is useful curing a reaα mcaify-writ- operation. Finally, when tr.is snared cut lcc tit is net set (i.e., has a valαe cf "C", , tne εr.areα r.uε iε not locked and the EMAU relinquishes its access to the shared bus (i.e., lowers its request signal) after the arbiter lowers the signal on its grant line. Processor 156 also can read the first control word stored in external access control register 222, Jay (1) asserting an active signal on external I/O access line 182, (2) transmitting a "00" signal on EMAU register bus 184 to indicate to bus interface control unit 220 that it wishes to communicate with external access control unit 222, and (3) asserting a read operation on read/write bus line 186. In response to these signals, EACR 222 then places the programmed first control word on bus interface control bus 222, which then transfers this information to processor 156 through control unit 220 and external data bus 180. b . External Address Unϋ In the last clock cycle of the two-clocκ cycle initial programming phase, proceεscr 156 programs one cf the external address units. During this dec.-; cycle, processor 156 maintains the active signal cr. external input/output access line 162 and transmits e tner a "01" or a "10" signal on the EMA register cus :: i.nαicace tc bus interface control unit 220 t at it w sr.ee tc communicate with one cf the external adareε: units 224 or 230. Prααesscr 156 programs externa- reaα ,-αdress unit 224 when it wishes to initiate an external read operation, while it programs external write address unit 230 when it wishes to initiate an external write operation. In order not to obscure the description of the present invention with unnecessary detail, the following discussion pertains to the programming of the external read address unit. However, it is to be understood that the following discussion is equally applicable to the programming of the external write address unit. After selecting ERAU 224, processor 156 then transmits a second 16-bit control word to the external address unit through external data bus 180 and causes external read address unit 224 to record this signal by asserting a write operation on read/ write bus line 186. The sixteenth bit of the second control word is used to indicate whether the EMAU should initiate a read operation through the shared bus cr tne private DUS. This sixteenth bit is stored in second address register 246 in ERAU 224. The ERAU supplies tnis sixteenth bit to state machine 194, which later generates enable signals that select the bus tnrough wnich tne EMAU should initiate an external access. Fcr tne embodiment of the present invention shown in Figure 6, a value cf "1" for the sixteenth bit causes the EMAU to access an external component tnrouαh tne snared bus, whι_e a value of "0" for the sixteenth bit causes the EMAU to initiate an external data access through the private bus. Bits one through fifteen of the second control word are used by the processor to indicate an address of an external component coupled to either the shared or private bus. During an external data access, bit one through fifteen indicate (1) the address of the requested data word when the EMAU undertakes a single access operation, or (2) the initial address of a requested block of data words when the EMAU undertakes a block access operation. Bits nine through fifteen of the second control word are stored in second address register 246 of external read address unit 224. These seven bits in combination with the original lower eight bits define an external register location (e.g., a memory location in one of the N data bank 158) . The lower eight bits of the second control word are supplied to address counter unit 244 cf EFAU 224. In turn, wnen state machine b!ocκ 195 supplies an active counter enable signal to address counter unit 544, the address counter unit uses tnese lower eight bits and the control signals that EACR 222 supplies te it (e.g., step size, loop size, and decrement/ increment mode signals) to generate up to 256 external partial aα resseε . In other words, if processor 156 requests a :!::•; mode access, address counter unit 244 generates up tc 256 external partial addresses, by counting up or down by 1 or 2 starting from the initial eight bits that are supplied to it (i.e., bits one through eight cf the second control word) . As shown in Figure 6, address counter unit 244 also receives counter enable signal (from state machine block 194 via bus interface control unit 22C and bus interface control bus 232), which activates ana deactivates the counter. The operation cf external read address unit 224, during the first two clock cycles that counter unit 244 receives an active counter enable signal, will now be described. During the high phase of the first clock cycle, second address register 246 stores bits nine through sixteen cf tne second control word, while first address register 245 stores bits one through eight of the second control word. During the low phase cf the first clock cycle, first aaαreεε register 245 supplies the first eight cits ef tne second control word to second address register 246 whicr. crier, produces a complete first external aααreεε ry ccmcinmα these lower eight bits with bits nine tnrougn sixteen and stores this complete first external aaureε... In addition during this low phase, counter 244 generates a first eight bit partial adaresε . During tne .:.:: pnase of the second clock cvcie, counter 244 eαt lie. tr.- f i -?* ■ J second address register 246 transmits the first external address along address output bus 236. During the low phase of the second clock cycle, address counter 244 generates a second eight bit partial address, and second address register 246 receives the first partial address from first address register 245, in order to produce a complete second external address by combining the first partial address with bits nine through sixteen cf the second control word and tc store this complete εecond external address . It should be noted that processor 156 can also read the second control word or a current address stored in the address register of ERAU 224, by (1) asserting an active signal on external I/O access line 182, (2) transmitting a "01" signal or. EMAU register bu„ 184 tc indicate to control unit 220 tnat it wishes tc communicate with ERAU 224, and (3) asserting a read operation on the read/write bus line 186. In response to these signals, ERAU 224 then places the contents of its second address register 246 en central Dus 232, which in turn transfers tmε mfcrmatiαn tc or ceεscr c . External Data Registers After the initial two-clock cycle programming phase, processor 156 tnen initiates a external input (i.e., read) or output (i.e., write) operation. Processor 156 uses external data read registers (i.e., EDRR) 226 during a read operation, and uses external data write register (i.e., EDWR) 228 during a write operation. The use of this register data accessing method reduces the data access time of processor 156. More specifically, as mentioned before, when processor 156 accesses a data memory bank 158 tnrough private Dus 146, external memory access apparatus 140 enables the processor to access X locations in the data memory in X + Y clock cycles when a write operation is undertaken and X + Y + Z clock cycles when a read operation is undertaken, where (1) X represents the number of locations accessed in tne data memory, (2) Y represents the number of clock cycles needeα tc prograrr the EMAU, and (3) Z represents the number of clock cycles needed to prefetch data for tne read operation. As mentioned before, for one embodiment of the present invention, programming clock cycles Y equals two and prefetching clock cycles Σ equals two. In tne otner hand, when processor 156 uses stare: nαε 148 t access a particular data memory pan/., external memory access apparatus 140 allows the processcr tc acceεε X . catior. in the data memory in X + Y + W clock cycles when a write operation is undertaken ana X ^ Y t Z + ' .-. " clock cvcles when a reaα operation is undertaker., w.nere W represents the number of clock cycles that the EMAU awaits until the arbiter grants it access to tne shared bus . The operation of shared and private bus interface 190 during a read operation will now be described with reference to Figure 7, which shows a block read access mode along the private bus. The following description is equally applicable to a block read access a_ong the shared bus, except that during a shared bus reaα operation there will exist a delay of W clock cycle, until the arbiter grants the EMAU ' s shared bus request. State machine block 194 receives external I '0 bus 182, EMAU register bus 184, and read/write bus 186, m order to determine when processor 156 requests an external read operation from second external data read register 226a. Upon detecting this request (w icn is represented by an external I/O access signal, - reaα signal, and EMAU register signal selecting external data registers 226a or 228), state machine bloc-; 194 activates the stop processor signal supplied tc processor 156 in order tc cause tne procesεcr 156 eitner to stop or idle fcr twc doc/, cyc.es, v.- icn ir tarn allows EMAU 144 to prefetcn two data worαs ana store them in the external data registers. More specifically, during the first clock cycle that state machine block 194 detects that processor 156 has requested an external read from second EDRR 226a, state machine block 194 activates the counter enable signal for as long as the processor accesses the external data registers 226a or 228. In addition, during the low phase of this first clock cycle, state machine block 194 (1) asserts a stop processor signal on the stop processor line 188 and maintains this signal for two clock cycles (i.e., maintains this signal until the low phase of the third clock cycle after state machine block 194 detects an external read), and (2) activates the private read enable signal bus and maintains this signal until one half clock cycles after the processor terminates its communication wit EDRR 226a. The second clock cycle is a first prefetcn cycle during which ERAU 224 transmits a first external address along address out bus 236 to external memcry interface unit 236. Interface unit 226 m turn transmits tne first external addreεs along private nuε aaαreαε DUS 210p. In addition, aurmg tne εeccr.α c.::-; cycle, shared a c private DUS interface 195 activate: tne private bus reaa signal (on private DUS reaα i-r.e 206p) and maintain this active signal until one dec/, cycle after processor terminate its communicatic wi-r. ELP? 226a. Finally, during the second clock cycle, first EDRR 226b begins to store the data that is retrieved from the specified first data location. The third clock cycle is a second prefetcn cycle, during which (1) ERAU 224 transmits a second external address along address out DUS 236 and address bus 210p, (2) first external data read register 226b finishes storing the first data word retrieved from the first address location and begins to store the seccnα data retrieved from the second data location, (3) second EDRR 226a stores the first data word which was stored in first EDRR 226b, (4) state machine block 194 deactivates (i.e., pulls to ground) the stop processor signal, and (5) processor 156 begins to receive the data stored in the second external data read register 226a. As shovnn in Figure 7, the operation cf tne EMAU αuring tne fourth, fifth, ana sixth dec/, eyei-ε are identical. During these three d c .-: cycles, (-) state machine block 194 supplies active read enable ana counter enable signals to snarea ana private bus interface 190, (2) ERAU 224 transmits a third, a fcurtn, and a fifth external addresses alcng address e -t DUS 25-- ' an address DUS 21Cp, (3, firεt EL.FR 12ft fmicneε storing tne second data wcra from the seccnα aααreεε location, stores the third and fearth aata wens. retrieved frc the tr.ird and fourth data locations, ana begins to store the fifth data word retrieved from the fifth data location, (4) second EDRR 226a stores the second, third, and fourth data words that were stored in the first EDRR 226b, and (5) processor 156 finishes receiving first, second, and third data words stored in second EDRR 226a, and starts receiving the fourth data word stored in the second EDRR 226a. During the seventh clock cycle, (1) state machine block 194 deactivates the private bus read enable and counter enable signals, (2) ERAU 224 transmits a six external address along address out bus 226 and address bus 210p, (3) first EDRR 226b finishes storing the fifth data word from the fifth address location, and begins storing the sixth data word retrieved from the sixth data location, (4) second EDRR 226a stores the fifth data word that was stored in the first EDRR 226b, and (5) processor 156 finishes receiving tne fcurtn data word stored in the second EDRR 226a. Consequently, by the end of the eightn clock cycle (after state machine block 194 detects the processor 156 is accessing external data register 226a; , EMAU 144 nas suprlied tc processor 156 four data words and has prefetcneα and stored two additional data words (i.e., aata -words five and six) in external data read regiεterε 216. The operation of a shared and private DUS interface ISO durinα a sinαle access read operation is very much similar to the above-described block read operation, except that during a single access read operation (1) private address bus only transmits three addresses (during the second, third, and fourth clock cycles), (2) first EDRR 226b only latches three data words during the second, third, fourth, and fifth clock cycles), (3) second EDRR 226a only latches two data words (during the third and fourth clock cycles) , and (4) processor 156 only reads one data word along external data bus 180 (during the third and fourth clock cycles) . In addition, since during a single access read operation counter 244 generates the same partial address three times, private bus address DUS 210p transmits the same address three times, external data read registers 226a stores the same data word three times, and external data read registers 226b stores the same data word two times. On the other hand, if processor 156 supplies a write signal over read/write bus line 166, while supplying an external 1 ' Z access signal and an EMAU register signal selecting external data registers 226a or 228, bus interface 19C allows processor 156 to initiate an output (i.e., write) operation throug.o external data write register 226. More specifically, a; mentioned before, if tne sixteen::, bit of tne ..econd control word indicates an external acceεε tnrouαn the private bus, external memory aαcesε apparatus 14! enables processor 156 to undertake an external write operation in X + Y clock cycles, where (1) X represents the number of locations accessed in the data memory, and (2) Y represents the number of clock cycles needed to program the EMAU. In addition, when the sixteenth bit of the second control word indicates an external write operation to a particular data memory bank through the shared bus, external memory access apparatus 140 allows the processor to undertake this operation in X - Y + W clock cycles, where W represents the number cf clock cycles that the EMAU awaits until the arbiter grants it access to the shared bus . The operation of a shared and private ' interface 190 during a write operation will now De described with reference to Figure 8, which shows a block write access operation along the private bus. The fcliowing description is equally applicable to a block write access along the shared bus, except that for a shared bus write there will exist a delay of V. eck cycles until the arbiter grants the EMA ' s snared DUS request. State machine block 194 receives external I ' 2 bus 182, EMAU register bus 164, and read/ rite DUS 186, in order tc determine when processor 156 requests an external write operation fret, external data v.-r-t÷ register 226. Upon detecting this request ( . er. is represented bv an external I 0 aocesε oigr.a., .-: write signal, an EMAU register signal selecting external data registers 226a or 228), state machine block 194 activates the counter enable signal for as long as the processor accesses external data write register 228. In addition, during the low phase of the first clock cycle that state machine block 194 detects an external write, state machine block 194 activates the private DUS write enable signal and maintains this active signal until one-half clock cycles after tne processor terminates its communication with EDWR 228. During the seconα clock cycle that processor 156 accesses EDW? 228, (1> EWAU 235 transmits the first external address along address out bus 236 and private bus address bus 210p, (2) external memory interface unit 238 activates the private bus write bus 208p and maintains this active signa_ until one clock cycle after the processor terminates its communication with EDWR 228, (2) EDWR 226 transmits a first data wcrd tc tne addressee data Dan/ along private bus data bus 212p. As shown in Figure 8, the operatio of shared and private DUS interface 195 curing t e third clock cycle is identical to its operation curing the second clock cycle . Dunne the fourtn clccx cycle, (1) state racnine block 194 deactivates tne private DuS write enable signal and the counter enade signal, (1) EWAU 231 transmits a third external aααresε along aααre : out bαc 236 and address bus 210p, (3) external memory interface unit 238 maintains an active private bus write signal, and (4) EDWR 228 transmits a third data word tc the addressed data location along private bus data bus 212p. Consequently, as set forth in Figure 8, external memory access apparatus 140 of the present invention enables processor 156 to complete its part of a write operation in X + Y clock cycles, where X represents the number of locations accessed in the data memory (e.g., tne three data locations accessed m Figure 8) and Y represents the number of clock cycles needed to program tne EMAU (e.g., the two clock cycles necessary to program EDRR and EWAU as shown in Figure 8) . 6 • State Machine Block Figure 9 presents one embodiment of state machine block 194. The function of this block is (1) to monitor the signals that the processor transmits to tr.- snareα and private bus interface througn external I 0 access bus 182, EMAU register bus 164, ana read write cus 186, (2) to monitor the grant signals that shared DUS arbiter 150 supplies to it, and (2) to generate tne snared and private bus enable signals, counter enable signals, a a stop processor signals, which central tne operation cf the shared and private bus interface curing an external input/Output operation. In addition, as mentioned • before, state machine clock 194 also couples to clock module 202 to receive stop request signals, which cause the state machine to generate stop processor and EMAU clock signals. As shown in Figure 9, state machine bioc 194 includes state machine control unit 250, shared bus state machine 252, private bus state machine 254, state machine control DUS 256, and state machine cutout generator unit 258. Control unit 250 directs tne clock signals on clock bus 198 to state machines 252 and 254 and output generator unit 255. Control unit 250 is a decoder that prevents signals on the EMAU bus 142 frorr reaching state machines 252 and 254 and output generator unit 258, until processor 156 indicates an external input/output access (on external I/O access DUO 182) . Once processor 156 initiates an external input cαtput access, state machine control unit 250 then awaits for ERAU 224 or EWAU 230 to supply to it tne sixteer.tr, bit of the second control word. As mentioned before, this sixteenth bit informs state macr.ine block 194 v.-netner processor 156 wishes tc initiate an external access through either the private Dαs cr tne snared bus . Control unit 250 then awaits prccesser 155 to -r.aicate a read or write operation directea toward tne external data registers 226a cr 226 (or EMAU register c :ε 184) . Upon receiving tniε indication, centre! ur.-t 2 5 ill enables one of the state mac.tir.es 252 or 2:4, cr.ι_e disabling the other, based on the value of the second control word's sixteenth bit, and (2) enables state machine output generator unit 258. After control unit 250 enables a particular state machine, control unit 250 directs toward this state machine the signals that appear on external Id access bus 182, EMAU register DUS 184, read/write bus 186, stop request line 200, and the DIOC mode line of EMAU control bus 204. In addition, if control unit 250 enables shared bus state machine 252, control unit 250 not only directs towards this state machine the signals mentioned above, but also directs towards this state machine the shared bus Ioc signal (appearing on EMAU control bus 204) and the shared bus grant signal. These inputs to the state machines cause the state machines to undergo various state transitions. For tne embodiment of state machine block 194 tnat Figure 9 sets fcrtn, state machines 252 a a 254 transition frcrr state-to-state on tne rising dock edge . In ether words, each state machine examines its input signals t" determine whether it needs to undergo a state tranεitior at the rising edge cf the clocx signal. Ir. addition, when a state machine is enabled, tne state macr.ine generates a tnree digit control cede (bl, d, and bC * his generator 258. State machine output generator 258 also receives through control bus 256 signals appearing on the read/write bus 186, EMAU register bus 184, EMAU control bus 204, stop request bus 200, and clock bus 198. These signals along with the three bit state codes then drive state machine output generator 258 to produce the bus enable signals, the counter enable signals, the stop clock signals, and the snared bus request signals. a_. Private B_U_S state Machine If processor 156 indicates (through the sixteenth bit of the second control word) that it wishes to initiate an external access through private bus 146 and indicates (on the EMAU register bus) that it wishes to access external data registers 226a or 228, state machine block control unit 250 enables private bus state machine 254, while disabling shared bus state machine 252. The operation cf private bus state achin- 254 will now be described with reference to Figures 10-13. Figure 10 presents the state diagram for one embodiment of private bus state acnine 254 cf Figure 9. Figure 11 presents the timing diagrams for the operation cf one embodiment of state machine output generator 256 of state machine block 194 of Figure 9, during a block read access through the private bus . Figure 12 presents the timing diagrams for the operation of one embodiment of state machine output generator 258 of state machine block 194 of Figure 9, during a block write access through the private bus . Figure 13 presents the timing diagrams for the operation of one embodiment of state machine output generator 258 of state machine block 194 of Figure 9, during a read after write access through the private bus . As shown in Figure 10, the operation of private bus state machine 254 is defined by tne value cf three signals, which are: (1) private bus access enable signal, (2) read with data in second EDRR 226a (i.e., EDRR2) not valid signal, and (2) the stop request signal. The private bus access enable signal is the private bus state machine enable signal generated by state machine control unit 250. More specifically, state machine control unit 250 generates an active private bus enable signal when processor 156 indicates (tnrough signals on external input cutput access cus 161, EMAU register bus 184, read/write cus 166, and the sixteer.tr. bit of a second control worα) an external read cr write operation through external data registers 226a or 226 and through private bus 146. In addition, an input forming logic of private ru: state machine 254 alεc generates an active rea : with data in second EDRF. 226a not valid signal, wr.er. processor initiates a single access read operation. The input forming logic detects that the processor has initiated a single access read operation when the block mode signal is deactive and the processor requests an external read of EDRR 226a. Furthermore, the input forming logic of private bus state machine 254 also generates an active read with data in second EDRR 226a not valid signal, when the processor directs the EMAU to initiate an initial prefetch read of a block read operation. The input forming logic detects that the processor has directed the EMAU to initiate an initial read of a block read operation when the input forming logic detects a first request from processor 156 to read EDRR 226a after the processor writes the second control word into ERAU 22 . On the other hand, the input forming logic maintains an inactive read with data in second EL5FF 22 c not valid signal (i.e., this signal has a value of "0") when processor 156 has requested a write operation (i.e., has initiated communication with tne external data write register 226) . Tne input forming logic also maintains an inactive read witr. data in second EI F 226a invalid signal, wr.en processor 156 resumes a r. ~ oe,-. reaα access after interrupting an initial bloc read access in mid-access. As further shown in Figure 10, private bus state machine 254 remains (i.e., loops) in idle State A as long as the stop request and private bus access enable signals are inactive. However, after sensing that processor 156 has initiated an external access and currently is accessing external data registers 226a or 228 (i.e., after generating an active P-bus access enable signal), private Dus state machine 254 transitions to either State C cr State F. For example, the transition of private bus state machine 254 from State A tc State C (which occurs if processor 156 requests a single access reaα cr an initial read of a blocκ read operation frorr second EDRR 226a) will now be described with reference to Figures 10, 11 and 13. As shown in these figures, if processor 156 requests an initial block read from second EDRR 226a while private bus state machine 254 is in idle State A, output generator 258 activates the counter enable signal for as long as the processor accesses tne external data registers 226a cr 228. In addition, during tr.e low phase of this initial clock cycle, output generator 256 (1) asserts a stop processor signal on tne stop processor clock line 156 a a maintain: two clock cycler, and (1< ao signal of the private rcαs ana maintains tr..: eigna! until one half clock cycles after the processor terminates its communication with second EDRR 226a. At the rising edge of the next clock cycle, private bus state machine 254 senses that the private bus access enable signal and the read with data in EDRR2 invalid signal are active, and therefore transitions from State A to first prefetch State C. During the clock cycle that private bus state machine 254 remains in first prefetch State C, the output generator 258 maintains the private bus read enable signal in order to allow bus interface 190 to begin storing a first data word in first EDRR 226b. In the next clock cycle, private bus state machine 254 then transitions to second prefetch State E, during whose clock cycle output generator 258 deactivates the stop processor signal to allow processor 156 to begin to receive the data stored in second EDRR 226a. In the next clock cycle, private bus stat- machine 254 transitions to access State F. In this state, processor is running, a a state macr.ine 254 monitors tne signals on external input output access DUS 182, EMAU register bus 184, and read' .-rite DUS 166, in order to determine if the processor currently is requesting another external read/write operation through external data registers 226a cr 228. If tne current processor instruction is net an externa. aeceεε tnroααn -xter.nal data registers 226a or 228 (i.e., private bus access enable signal is not active), the private bus state machine transitions to idle State A. For example, if the current processor instruction is program ERAU 224 or EWAU 230, the private bus state machine transitions from State F to State A because the private bus access enable signal is deactivated (as the processor no longer is accessing either EDRR 226a or EDWR 228) . On the other hand, if the current instruction is another access to second external data register 226a (i.e., another read access), private bus state machine 254 remains in State F and performs the read access. In addition, as shown in Figures 10 and 13, if the current instruction is an access to external data write register 228 (i.e., a write access), private DUS state machine 254 remains in State F and performs tr.e write operation based on the address m EWAU 230. Finally, state machine 254 transitions from State F tc State C when both the private bus access enable signal and the read with data in EDRR2 invalid signal are active (e.g., when processor 156 requests an external read after previously interrupting a reaα operation prior to prefetching any data woras cut after programming ERAU 224) . The direct transition cf private bus stat- machine 254 from State A tc State F in one clock cvce (w.nich - D occurs when processor 156 has requested an external write to EDWR 228 while state machine 254 is in State A or processor 156 resumes a block read access after interrupting a prior block read access) will now be described with reference to Figures 10, 12 and 13. As shown in these figures, if while state machine 254 idles in State A processor 156 requests an external write to EDWR 228, output generator 258 activates the counter enable signal for a s long as tne processor accesses the external data registers 226a cr 226. In addition, during the low pnase of this initial clocκ cycle, output generator 258 activates the private bus enable write signal and maintains this signal until one half clock cycles after the processor terminates its communication with EDWR 228. In the next clock cycle, private bus state machine 254 senses that the private bus access enable signal is active (i.e., has a value of "1") while the reac with data in EDRR2 invalid signal is inactive (i.e., nas a value cf "0") , and therefore transitions tc access State F. In tnis state, state macni e 254 monitors tne signals on external meet Out ut a c ce s s Out 16_, ΞMA register bus 164, and read/ rite DUS 156 ir, orαer to determine if the processor Currently is requesting another external read or write operation tr.rougn external data registers 226a or 226. If tne c rer.t processor instruction is not an external access through external data registers 226a or 228 (i.e., private bus access enable signal is not active), the private bus state machine transitions to idle State A. On the other hand, if the current instruction is another access to external data write register 228 (i.e., another write operation), the private bus state machine 254 remains in State F and maintains generating the enable signals (i.e., counter enable signal and private bus write enable signal), which allow bus interface 190 to perform the write operation. In addition, as shown in Figures 10 and 13, if the current instruction is an access to second external data read register 226a (i.e., a read access), private bus state machine 254 still maintains an active counter enable signal for as long as the processor accesses the external data registers 225a cr 228. However, daring the low phase of the clock cycle fcr the current instruction, output generator 258 deactivates the private bus enable write signal, while activating the enable read signal of the private bus ana maintaining this signal :nt c.c_e processor terminates its communication witn second EDR1 226a. The EMAU then in tne next clock cycle initiates read operation based cr. the address in ERAU 224. In this manner, the external accessing apparatus -f the present invention can transition from a write to a read operation in just one clock cycle when the processor does not load a new address into ERAU 224. The above discussion of the state transitions of state machine 254 assumes that the stop request signal is inactive (i.e., has a value of "0") . If this stop request signal becomes active while state machine 254 is in idle State A or access State F, tne state machine 254 transitions to stop State H on tne rising edge of the next clock cycle. State macnine 254 remains in State H until the clock module removes the stop request signal, before transitioning to either State G or State C in the following clock cycle. State machine 254 transitions to State C, if the stop request signal becomes inactive and processor 156 requests an initial external read from second EDRR 226a (i.e., if the P-DUS acceεε er.aole signal and the read witn data in ΞDRRl mvaliα signal are active while the stop request signal is inactive) . On the other hand, if processor 156 does net request an initial external reaa from second EFFF 226a, state machine 254 transitions frer State H t: date 3 during the next clock cycle. Fret State 3 iv:r..::. is a start processor after a glonal stop state) , εtate machine 254 then transitions to eitner idle State A cr access State F. More specifically, εtate macnine 254 transitions from State G to State F if tne rπvate DUS enable signal is active while the read with data in EDRR 226a invalid is inactive. On the other hand, state machine 254 transitions from State G to State A if the private bus enable signal is inactive. The operation of private bus state machine 254 after the processor interrupts an external access will now described. If the processor nas to interrupt an external block read operation, but wishes to later resume this operation, tne processor first has to store the address of the data contained in second external data read register 226a. If during the interrupt the processor uses external data read registers for alternative read operations, the processor has to reprogra the stored address cf the original data in EDRR 226a into external read address unit 224 Defore resuming its original block read operation. Or. the other hand, if during the interrupt the processor does not perform other read operations, tr.e processor can later resume its original Dlocx read operation DV simply reaccessing EDRR 226a without any further programming cf ERAU 224. On the other hano, if tne procesεor nas t interrupt an external DICCK write cperation in rr.ic- access, in order to later resume its external ; LOCK write operation the processor first nas to store the address stored in EWAU 235. After the interrupt, tne processor has to reload the stored original value of the EWAU back into this address unit, if during the interrupt the processor performed alternative external write operations. On the other hand, if during the interrupt the processor did not perform alternative write operations, after the interrupt the processor can simply resume its block write access by accessing EDWR 228. Finally, it should be noted that private DUS state machine 254 is designed in such a manner so as to allow processor 156 to repeatedly perform the same single access read operation without the delay due to the two prefetch cycles. More specifically, whenever processor 156 requests a single access read operation by deactivating the block mode signal, the processor has tc wait three clock cycles before receiving its requested data word. This delay remains unchanged ever. _n those situations where the processor has requested n subsequent clock cycles that the same data word be supplied to it because, whenever the processcr requests a single read operation by deactivating tne block mode signal, the processor causes private bus εtate machine 254 to transition from. State A to prefetcn States C ana E. However, the processcr car. also repeated: access the same data word (i.e., can repeatedly perform the same single read operation) bv indicating a deck read operation with a loop size of one, which in turn allows the processor to access EDRR 226a to obtain the data word after one and only one two clock cycle prefetch stage . b Shared Bus SJS ≤ M hin If processor 156 indicates (through the sixteenth bit of the second control word) that it wishes to initiate an external access through shared bus 146 and indicates (on the EMAU register bus) that it wishes to access external data registers 226a or 228, state machine block control unit 250 enables shared bus state machine 252 while disabling private bus state machine 254. The operation of shared bus state machine 252 will now be described with reference to Figures 14-18. Figure 14 presents the state diagram for one embodiment of shared bus state machine 252 cf Figure 9. Figure 15 presents the timing diagra .s for the operation cf one embodiment of state machine cutput generate: 256 of state machine block 194 cf Figure 9, curing a dock read accesε through the shared bus . Figure 16 presents the timing diagrams for tne operation of one emnoaimer,t of state machine output generator 255 of εtate machine block 194 of Figure 9, during a block write aoeeεs through the shared bus. Figure 17 presents tne timing diagrams for the operation cf one embodiment of state machine output generator 258 of state machine block 194 of Figure 9, during a read after write access through the shared bus. Figure 18 presents the timing diagrams for the operation of one embodiment of state machine output generator 258 cf state machine block 194 of Figure 9, during a write access througn the snared bus when the shared bus grant signal is removed and the processor has not locked the shared DUS . As shown m Figure 14, tne operation of shared bus state machine 252 is defined py tne value cf dve signals, which are: (1) the shared bus access enable signal, (2) the read with data in EDRR2 226a not valid signal, (3) the stop request signal, (4) the snared bus grant signal, and (5) the lock snared bus signal. The shared bus access enable signal is tne snared DUS εtate machine enable sigral generated Dy state macnir e contrc- unit 250. Mere specifically, control unit 250 generates an active access enable signal when processcr 156 indicates (tr.rough signals or. external input/ output access bus 162, EMAU register DUS 164, reaα write bus 186, ana tne sixteer.tr. tit cf tne εeeor.a centr _. wore) an external read cr operation tnrougr. external data registers 226a or 226 anc tnrougr. snared DUS 148. In addition, an inp :mι sha re d bu s state macnine 252 als: ■"= a ; with data in second EDRR 226a not valid signal, when the processor initiates a single access read operation. The input forming logic detects that the processor has initiated a single access read operation when the block mode signal is deactive and the processor requests an external read of EDRR 226a. Furthermore, the input forming logic of the shared bus state machine 252 also generates an active read with data in second EDRR 226a not valid signal, when the processor directs the EMAU to initiate an initial prefetch read of a block read operation. The input forming logic detects that the processor has directed the EMAU to initiate an initial read of a block read operation when the input forming logic detects a first request from processor 156 to read EDRR 226a after the processor has previously written the second control word into ERAU 224. On the other hand, the input forming logic maintains an inactive read with data in second EDRR 226a not valid signal when processcr 156 has requested a write operation (i.e., has initiated communication with the external data write register 228) . The input forming logic also maintains an inactive reac with data in second EDRR 226a invalid signal, when processor 156 resumes a block read access after interrupting an initial block read access in mid-access. As further shown in Figure 14, shared bus state machine 252 remains (i.e., loops) in idle State A as long as the stop request and shared bus access enable signals are inactive. However, after sensing that processor 156 has initiated an external access and currently is accessing external data registers 226a or 228 (i.e., after generating an active S-bus access enable signal) , output generator 258 stops the processcr clock. More specifically, when output generator 258 senses that processor 156 has requested an initial external access and currently is accessing external data registers 226a or 228 while shared bus state machine 252 is in idle State A, output generator 258 activates a stop processor signal on the stop processor line 186 during the low phase of this initial sensing clock cycle . At the rising edge of the next clock eye!.-, snare: bus state machine 252 transitions to request State 5 and activates its shared bus request signal (which it supplies to arbiter 150 in order to orctain permission tc access the shared bus) . The shared bus state machine then remains (i.e., loops) in this state until arbiter 150 grants access tc the shared to tne EMAU. After tn- arbiter grantε tne EMAU ' s snared c us request (-.e., after shared bus state machine 252 receives an active shared bus grant signal), shared bus εtate machine 251 remains in State B for one more full clock cycle. During this final clock cycle in State B, output generator 258 activates the counter enable signal. At the rising edge of the clock cycle after this final State B clock cycle, state machine 252 transitions to either State C or State D based on the value of the read with data in second EDRR 226a invalid signal. For example, the transition cf shared state machine 252 from State B tc State C (which occurs if processor 156 requests a single access reac or an initial external read from second EDRR 226a) will now ce αescriπed with reference to Figures 14, 15 and 17. As shown in these figures, if processor 156 requests an initial nlock read from second EDRR 226a, (1) output generator 256 activates the shared bus read enable signal, during the low phase cf the final State 3 clock cycle, and (2) shared bus state m.achine 252 transitions from, request State B to first prefetch State C, at tne rising edge of the clock cycle after this final State Ξ clock cycle. During tne clock cycle that snared PUS εtate macnine 255 remains in. first prefetch State Z , tne output generator 258 maintains the shared tuθ reaα er.at-e eiαr.a. in order to allow Dus interface 1 ^ to Degir. storing a first αata word in first EDRR 226D. In the next .e, snared D: a: hlne then transitich; " in; whose clock cycle output generator 258 deactivates the stop processor signal to allov; processor 156 to begin to receive the data stored in second EDRR 226a. During the subsequent clock cycle, shared bus state machine 252 moves to access State F. In this state, the processor is running, and state machine 252 monitors the signals on external input/output access bus 182, EMAU register bus 184, and read/write bus 186, in order to determine if the processor currently is requesting another external read/write operation through external data registers 226a or 226. If tne current processor instruction is not an external access through external data registers 226a or 228 (i.e., shared bus access enable signal is not active) , the shared bus εtate machine transitions to idle State A. For example, when the current processor instruction is program. ΞF.AU 224 or EWAU 235, tne shared Dus εtate macnir.÷ transitions for State F tc State A because the shares bus acceoε enable signal is deactivated (as the prccessor no longer is accessing either EDRR 226a or EDWR 226) . Or. the other hand, if tne current instruct icr. is another access to seccr.α extern-- αata re iste. 226a (i.e ~ ne^h^*" r^aα acc c s) = oareα DUΞ s ^ a^e racnine 252 r main ir. State F ana performs tne reaa aceesε. In addition, as shown in Figures 14 and 17, if tne n r rp - • ^ *- v n '-' - -l r ^ r — ''j ~ "- > — o - c ■ *- - ΕC ' C ^ 1 V. - — G -Le t *~ i .17 .1 ^ or - 66- register 228 (i.e., a write access), shared bus state machine 252 remains in State F and performs the write access based on the address in EWAU 230. The transition of shared bus state machine 252 from State B to State D (which occurs when processcr 156 has requested an external write to EDWR 228 while εtate machine 252 is in State A or processor 156 resumes a block read access after interrupting a prior block read access) will now oe described by reference to Figures 14, 16 and 17. As shown in these figures, if (while state machine 252 idles in State A) processor 156 requests an external write to EDWR 226, shared bus state machine 252 transitions from request State B t , start State D, at the rising edge of the clock cycle after this final State B clock cycle. During the lew phase of the clock cycle that shared bus εtate machine 252 remains in start State Z , output generator 256 (iι activates a shared bus write er.a e signal ar.α maintains this signal active until cne-nalf clocκ cycles after tne processor terminates its cemmudcacior. with EDV. ' F 225, and (2) starts the processcr dock ny deactivating the stop processor signal. In addition, during to* doc/ cycle that shared bus εtate machine 255 remain, in εtart State , output generator 258 deactivates tne -tenter enable signal . In the next clock cycle, shared DUS state machine 252 transitions to State F and output generator 258 reactivates the counter enable signal and maintains this signal active until the processor stops communicating with EDWR 228. In this state, state machine 252 monitors the signals on external input/output access bus 182, EMAU register bus 164, ana read/ write bus 186 in order to determine if the processor currently iS requesting another external read or write operation through external data registers 226a or 226. If the current processor instruction is not an external access through external data registers 226a or 225 (i.e., shared bus access enaDle signal s net active) , tne shared bus state machine transitions to iαle State A. On the other hand, if tne current instruction is another access to external data write register 228 (i.e., another write operation) , shared bus state machine 252 remains in State F a a maintains generating th- enable signals (i.e., counter enable εigr.a- and snared cus write enaDle signal) which allow DUS interface 1 0 tc perform the write operation. In addition, as εnewn in Figures 14 ana 17, if the current instruction is an aeeeεε tc second external data read register 226a (i.e., a reaα access ι , εnareα bus state machine 252 stιl_ .maintains an activ counter enable signal fcr as ior.α as tne processor accesses tne external data registers 226a or 228. However, during the low phase of the clock cycle for the current instruction, output generator 258 deactivates the shared bus enable write signal while activating the enabie read signal of the shared bus and maintaining this signal until one half clock cycles after the processor terminates its communicaticn with second EDRR 226a. The EMAU then in the next clock cycle initiates a read operation based on the address in ERAU 224. In this manner, the external accessing apparatus cf the present invention can transition, from a write to a read operation m just one clock cycle when tne processor does not load a new address into ERAU 224. The operation cf shared bus state machine 252 when the processcr interrupts a block operation is similar to the operation of private bus state machine 254 curing such interrupts. In addition, the above discussion of the state transitions of state machine 255 assures (1) that tne step request signal is inactive, and (5 ) that the arbiter does not remove its grant signal t tne EMAU in middle of an external aeceεε. Aε tnese two assumptions are net always accurate, a description cf the operation of the εtate machine 252 is necessary wnen either the εtop reαu εt εignai tε activ cr tr." artiter removes its grant signal in :αά.e of an external access. If the stop reαueεt signal becorr.es at ive while state machine 252 is in idle State A or access State F, state machine 252 transitions to stop State H on the rising edge of the next clock cycle. State machine 252 remains in State H until the clock moduie removes the stop request signal before transitioning to either State G or State B in the following clock cycle. State machine 252 transitions tc State B, if the step request signal becomes inactive while tne snared bus access enable signal is active. On tne other r.ar.d, if the shared bus access enable signal is active, state machine 252 transitions from State H to State G when the stop request signal is removed. From State G, state machine 252 then transitions to idle State A on the rising edge of the next clock cycle . Figure 18 presents the timing diagrams for the operation of one embodiment cf output generate. 256, during a write access through the shared bus wn.en the shared bus grant signal is removed and the processcr nas not locked the shared bus. As sr.cwr. in t.tiε f .gure, if the arbiter removes its snared DUS grant ειgna_ while shared bus state machine is in access State F and processor 156 is requesting an external access, snared bus state machine 252 steps tne processor dee -., pulls its shared bus request lev, a.nα transitions t, idle State A ana trier, request State Ξ. Once tne ar; iter returns tne EMA ' s εr.ar-α ncε grant signal, εncr÷α DO: state machine then transitions from State B to either State C or D, based on the criteria discussed above. It should be noted that if shared bus 148 is locked (i.e., if the twelfth bit of the first control word and the sixteenth bit of the second control word are set) and EMAU has started a shared bus access, shared bus state machine 252 will not pull its request low (i.e., shared Dus state machine 252 will remain i State F or will transition tc State C then State E), ever, if the shared bus grant is taken awan . Shared bus state machine 252 will only pull its request low if the processor clears this twelfth bit. Thus, by placing state machine 252 in State F and locking the snared DUS, processor 156 can later initiate (1) an external write operation without seeking the arbiter's permission, or (2) an external read operation without seeking tne arbiter's permission (this operation is snown aε a transition from State F to State Z in Figure 14) . Consequently, external memory aoceεs apparatus 141 of the present invention reduces tne αata accede time of processor for several reasons. First, ty separating the program memory and the αata memory, tne αata ceeeε time cf processor 156 is net affected ry tne communica ions Between processcr 156 and program memory 165. Second, as data words are prefetcneo for tne processor curing by until the data memory bank can supply a data word tc it, but rather can have the EMAU fetch a subsequent data word while it decodes and executes a previous data word. Third, since the EMAU is not forced to drive a highly capacitive bus to access the data memory banks, the access time is reduced. Fourth, the data access time is also minimized because processor 156 does not have to terminate its data access to allov; other components of the computer system to access the data oanks, nut rather can access a data bank through the private bus while allowing another component to access another data bank through the shared bus . Finally, the external memory accessing apparatus of the present invention is advantageous because it requires a minimal amount cf memory capacity as it allows the processor to access a particular data ban/. through the private bus while having DMA 152 refresh another memory bank through tne shared bus .

Claims: CLAIMS I Claim: 1. An external memory component apparatus for enabling a processor to access a first component, said external component access apparatus comprising: a) an external component access unit; b) an external component access unit bus for coupling said external component access unit to said processor, c) a private bus coupling tc said external component access unit, said private DUS fcr coupling said external component access unit to said first external component; and d) a shared bus coupling to said external component access unit, said shared cuε fcr coupling εaiα external component access unit tc saiα first external component and for coupling a seccnα external component to said first external component .

Inventors: HATAMI PARVIZ, REGENOLD DAVID, HATAMI, PARVIZ, REGENOLD, DAVID
Applicants: INTEL CORP, INTEL CORPORATION
Application year: 1995
Main classification: G06F13
IPC codes: G06F13