A semiconductor IC chip with electrically adjustable resistor structures

Abstract: The present invention relates to a resistor structure the resistance value of which can be electrically adjusted after fabrication by the tester during the test operation so that its equivalent resistance closely approximates the desired nominal value. In essence, the novel resistor structure consists of a main resistor (R1) and a determined number of trimming resistors (R1-1 to R1-4) that are connected in parallel thereon. Each trimming resistor can be connected in parallel on the main resistor independently of one another thanks to a switch (PG1-1w to PG1-4), typically a pass-gate NFET device, that is serially connected therewith. This switch is enabled or not via a control line (16-1 to 16-4). Each control line is connected to a binary storage cell (17-1 to 17-4) which includes a fuse (F1 to F4) that can be electrically blown by the tester. Because, the resistance value of the main resistor (and trimming resistors as well) changes as a result of the fabrication process variations, these trimming resis tors are designed so that whatever the main resistor value, there is an appropriate combination of trimming resistors to reach the said desired nominal value. This resistor structure is perfectly adapted to the fabrication of semiconductor integrated circuits terminator chips.

Description: FIELD OF INVENTION The present invention relates to electrical resistors and more particularly to a resistor structure the value of which can be electrically adjusted after fabrication by the tester during the test operation so that its equivalent resistance is approximately made equal to the desired nominal value. In essence, the novel resistor structure consists of a main resistor and a plurality of trimming resistors that can be connected in parallel thereon independently of one another thanks to a switch serially connected with each trimming resistor. Each switch is enabled or not via a control line. The values of the main and trimming resistors are designed so that there is an appropriate combination of trimming resistors to reach the said desired nominal value in spite of resistance variations caused by the fabrication process. This resistor structure is perfectly adapted to play the role of a termination resistor, in particular in semiconductor integrated circuits (IC) terminator chips which incorporate a plurality thereof. BACKGROUND OF THE INVENTION Semiconductor IC terminator chips are extensively used to date for bus impedance matching. In particular, the SCSI bus that is well adapted to high speed data transfer between a CPU and an attachment (e.g. a hard-disk drive) includes a determined number P of such termination resistors. In this case, the standard requirement is to put eighteen (P = 18) termination resistors on each terminator chip having a nominal value of 110 Ω with a tolerance target of about +-3%. For practical reasons, these termination resistors are generally built in polysilicon. Unfortunately, there is a non negligible tolerance in the value of the sheet resistivity of polysilicon films produced in a semiconductor manufacturing line due to inevitable process variations. For instance, using a conventional 1,2 µm CMOS fabrication process, the polysilicon sheet resistivity PRS ranges from 21 to 29 Ω/sq (25 Ω/sq nominal) for wafers of different lots, i.e. with a resistivity tolerance of about +- 16%. As a result, the value of standard termination resistors fabricated in different wafers of a same lot according to this process ranges from about 92 Ω to about 128 Ω. To get an acceptable final test yield, it is thus mandatory to trim somehow every termination resistor to reach this desired nominal value of 110 Ω with a tolerance better than +-3%. Up to now, the adjustment of the value of each termination resistor has been performed by a complex equipment combining test and laser trimming capabilities. During the test, a laser trimmer corrects in real time the value of the resistor. Basically, all the termination resistors come out of the manufacturing line with a target value lower than the desired nominal value of 110 Ω, for instance, with a target value of 90 Ω. The tester performs the resistance measurement and depending on the difference between the desired nominal value and the value that is measured, the laser beam tailors the termination resistor so that its resistance increases. The trimming operation continues until the nominal resistance value of 110 Ω is obtained. This way of trimming the termination resistor is really accurate. However, this technique is time consuming. Indeed, for any terminator chip such as described above, the trimming operation must therefore be repeated eighteen times. In addition, this step is also expensive because a sophisticated laser equipment (which includes precise optics, the laser system and the like) is required to be associated to the tester. Consequently, this prior art laser trimming technique is adequate for low volumes of expensive chips, but not for mass production of low cost chips. EP-A- 0327078 is an example of the art related to the resistor trimming by laser. OBJECTS OF THE INVENTION It is therefore a primary object of the present invention to provide a semiconductor integrated circuit (IC) chip defined by the features of claim 1. It is another object of the present invention to provide a method for electrically adjusting the equivalent resistance value of resistor structures defined by the features of claim 9. SUMMARY OF INVENTION According to the teachings of the present invention, the novel resistor structure is comprised of a main resistor and a selected number N of trimming resistors that are connected in parallel thereon. Each trimming resistor can be connected in parallel on the main resistor independently of one another thanks to an enabling element, typically a switch, serially connected therewith. Each switch is activated or not via a dedicated control line. Therefore, there are N control lines to control the N switches associated to said N trimming resistors. Preferably, said main and trimming resistors are made of polysilicon and said switch consists of a pass-gate NFET device. The resistance of the main resistor (and trimming resistors as well) varies between a minimum value and a maximum value that are determined by the specifications as a result of the resistivity variations due to the fabrication process. The main resistor is designed so that its minimum value is made equal to the nominal value that is finally desired (e.g. its value is made equal to 110 Ω which is the minimum value for a termination resistor adapted to the SCSI bus with the said conventional CMOS process mentioned above). As to the trimming resistors, their respective resistance values preferably vary according to a geometric progression. In other word, a binary weight (1, 2, 4, ... ) in accordance with a geometric progression is assigned to each trimming resistor. Basically, these resistance values are determined according to the following rules. When the resistance of the main resistor is equal to the maximum value, all the trimming resistors are connected in parallel on the main resistor by the tester, so that the resistor structure equivalent resistance is decreased down to the said desired nominal value. When the resistance of the main resistor is equal to the minimum value (it is then equal to the said desired nominal value by construction) none of the trimming resistor is connected in parallel on the main resistor. When the resistance of the main resistor is equal to an intermediate value, the tester determines which combination (among 2 N ) is the most adequate to reach the desired nominal value. The number N is determined by the precision that is sought (typically N is equal to 3 or 4). Still according to another important feature of the present invention, each control line is connected to a binary storage cell which includes a fuse that can be electrically blown by the tester during the test operation. Blowing a fuse will therefore enable corresponding trimming resistor to be connected in parallel on the main resistor. This resistor structure is perfectly adapted to the fabrication of semiconductor integrated circuits (IC) terminator chips which include a plurality P of termination resistors. In this case, the novel resistor structure of the present invention plays the role of a termination resistor. Still according to another further important feature of the present invention, a determined control line controls the corresponding P trimming resistors of the same rank or weight in each of said resistor structures, by enabling or not the switch associated therewith, so that there are N control lines and N binary storage cells for said plurality P of resistor structures. The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows the schematic circuit architecture of a semiconductor IC terminator chip adapted to a SCSI bus that includes eighteen termination resistors each having the resistor structure of the present invention and the control circuitry thereof. Fig. 2 shows a graph depicting the polysilicon sheet resistivity variations that result of a conventional CMOS manufacturing process when divided in sixteen (2 N ) sectors to cover the whole range thereof. Fig. 3 shows a physical implementation of the main and trimming resistors when they are all made of polysilicon for integration in a semiconductor IC terminator chip for a SCSI bus according to a conventional CMOS manufacturing process. DESCRIPTION OF THE PREFERRED EMBODIMENTS The following description will be directed to the archi-tecture of a terminator chip for a SCSI bus which includes P = 18 termination resistors produced by the conventional CMOS fabrication process mentioned above. It has also been indicated above that the polysilicon resistivity may sub- stantially vary from wafers of different lots (+- 16%). As a result, although the desired nominal value is 110 Ω, the real value of these termination resistors for wafers of different lots would be in the 92-128 Ω range due to process variations. However, applicant's inventor has noticed that there is a relatively good resistivity tracking across a given wafer (+- 5%) and further better track ing across a given chip, e.g. lower than +- 0,5%. Consequently, we can consider that resistors having the same geometry will have approximately the same resistance value on any given chip of a given wafer. The present invention is based on this observation. In Fig. 1, there is shown the circuit architecture of a semiconductor IC terminator chip 10 which incorporates eighteen innovative resistor structures according to the teachings of the present invention. Now turning to Fig. 1, resistor structures are referenced RS1 to RS18 incorporating respective main resistors R1 to R18. It is to be noted that all the main resistors have the same value, i.e. R1 = ... = R18 = R (within +- 0,5%). One end of each main resistor, e.g. R1, is connected to an output pad, e.g. 12-1 while the other end thereof is connected to a voltage regulator 13 via a common supply line 14. As a result, the voltage outputted by the regulator 13 is applied on one end of each main resistor R1 to R18. According to a first essential feature of the present invention, to each main resistor is associated an array of N branches, each branch being comprised of a trimming resistor serially connected with an enabling element, typically a switch. In the preferred embodiment illustrated in Fig. 1, this switch is physically implemented with a NFET device connected in a pass-gate configuration. For instance, to main resistor R1 is associated array 15-1 comprised of four branches connected in parallel thereon, each branch being in turn comprised of a trimming resistor R1-1, R1-2, R1-4 and R1-8 (this notation emphasizes the geometric progression mentioned above) and a pass-gate NFET device PG1-1, PG1-2, PG1-4 and PG1-8 respectively that is serially connected therewith. In addition, trimming resistors of the same rank (or weight) in each array also have the same value i.e. R1-1 = ... = R18-1. Within each array, the gates of pass-gate NFET devices of the same rank are tied to a common control or trimming line which in turn is connected to a binary storage cell. For instance, all pass-gate NFET devices PG1-1 to PG18-1 are connected via trimming line 16-1 to the output of storage cell 17-1. Thus, there are four (N = 4) trimming lines 16-1 to 16-4 (all together forming bus 16) connected to respective storage cells 17-1 to 17-4 respectively. Note that the number N of trimming resistors has been chosen equal to 4, however, it must be understood that this number depends on the specific application in consideration. All storage cells have the same construction. For instance, storage cell 17-1 first comprises a resistor RA1 and an electrical fuse F1 that are connected in series between a first supply voltage (Vdd) and a second supply voltage (Gnd). The common node formed therebetween, referred to as the input node, is connected to an input pad 18-1 on the one hand and to the gate electrode of a NFET device T11 on the other hand. NFET device T11 is connected in series with a second resistor RB1 between said first and second supply voltages Vdd and Gnd. Finally, the common node between NFET device T11 and resistor RB1 is connected to the common gate of an output inverter comprised of a pair of complementary FET devices T12 and T13 still biased between said first and second supply voltages Vdd and Gnd. The common output node of the output inverter of storage cell 17-1 is connected to trimming line 16-1. According to an essential feature of the present invention, the value of the main resistor R is set so that its resistance value is equal to the desired nominal value (e.g. 110 Ω) when the polysilicon sheet resistivity is at the low end of the specification (i.e. PRS = 21 Ω/sq). In this case, the main resistor will remain alone after fabrication without any trimming resistor connected in parallel thereon. The number N of trimming resistors is determined by the application in consideration and the precision that is sought. The criteria for determining the resistance value of each trimming resistor will be now given. For sake of simplicity, they are designed to have a resistance value in a 1-1/2-1/4-1/8- ... geometric progression to assign a binary weight to each of them. For instance, if R1-1 is the resistor of weight 1, the value of R1-2 will be half the value of R1-1, ... etc. Still with the conventional CMOS process mentioned above, at nominal centering, the value of the main resistor is equal to 131 Ω (PRS = 25 Ω/sq). If the value of the main resistor after fabrication is at the maximum value, i.e. 152 Ω at the high end of the polysilicon sheet resistivity specification (i.e. PRS = 29 Ω/sq), all the trimming resistors are connected in parallel on the main resistor to reach an equivalent resistance equal to the said desired nominal value. As result, whatever is the resistance value of the main resistor between said minimum value and maximum value, there is a combination (one among 2 N ) of trimming resistors to reach said desired nominal value. Since all the main resistors have the same value R with a precision of about +- 0,5%, the same combination of trimming resistors applies to each resistor structures RS1 to RS18. However, an implementation requiring P*N control lines for an individual personalization of the P*N trim ming resistors could be theoretically envisioned. Now, the detailed method for calculating the resistance values of the main and four trimming resistors will be given, in the case where, according to a preferred embodiment of the present invention, all main and trimming resistors are made of polysilicon which is standard practice in the field of IC chip manufacturing to date. The same figures given above i.e. a value of the polysilicon sheet resistivity PRS equal to about 25 +/-4 Ω/sq are used. First, we will consider that this value varies from 20 to 30 Ω/sq to add a guard band. Therefore, the main resistor will be designed so that its resistance value is equal to 110 Ω when PRS is equal to 20 Ω/sq. This resistance value will thus increase up to 165 Ω when PRS is equal to the maximum value, i.e. 30 Ω/sq. Next, the 20-30 Ω/sq PRS specification range is split into sixteen (2 N ) bands or sectors as illustrated in Fig. 2. To make calculations easier, because the main resistor value has been made equal to 110 Ω as explained above, a length L = 110µ has been chosen for sake of illustration. In this case, the relation between the equivalent resistance value Req of the resistor structure, the length L and the equivalent width Weq of the main resistor structure is simply given by: Weq (in µm) = (PRS x L) / Req = PRS (in Ω/sq). Therefore the width of the main resistor is equal to 20 µm. With this relation it is very easy to calculate the value of the resistor structure equivalent resistance width Weq, because it will be equal to PRS. For instance, when PRS = 20,66 Ω/sq (see sector 2 in Fig. 2), the width Weq of this equivalent resistor Req becomes 20,66 µm. In turn, the width of the trimming resistor of weight 1 labelled R1-1 (or W1), i.e. the one which has the greatest value, i.e. the one which produces the least significant correction when connected in parallel on the main resistor, can be easily determined. The width of trimming resistor R1-1 is equal to 20,66 - 20 = 0,66 µm. The TABLE below describes in more details the splitting of the PRS specification range into sixteen sectors and for each case, provides the value of the main resistor when alone. It further indicates which trimming resistor or combination of trimming resistors are to be connected in parallel on the main resistor to reach the said desired nominal value of 110 Ω. It is also used to determine the respective widths of trimming resistors R1-1 (W1), R1-2 (W2), R1-3 (W3) and R1-4 (W4). Sect. numb. 1 2 3 4 5 ... 16 PRS (Ω/sq) (cent. val.) 20.00 20.66 21.33 22.00 22.66 ... 30.00 Main resist. (alone) 110.0 113.6 117.3 121.0 124.6 ... ... 165.0 Weq (µm) 20.00 20.66 21.33 22.00 22.66 ... ... 30.00 Combin. of trim. resist. none W1 W2 W1+W2 W3 ... all In summary, the respective dimensions of the trimming resistors such as determined from the TABLE are given below. R1-1 (W1) weight 1 : 110 µm long and 0.66 µm wide R1-2 (W2) weight 2 : 110 µm long and 1.33 µm wide R1-3 (W3) weight 4 : 110 µm long and 2.66 µm wide R1-4 (W4) weight 8 : 110 µm long and 5.33 µm wide With nominal (center) PRS value, i.e. 25 Ω/sq, they respectively correspond to the following resistance values: R1-1 (W1) weight 1 : 25 x 110 / 0.66 = 4125 Ω R1-2 (W2) weight 2 : 25 x 110 / 1.33 = 2062 Ω R1-3 (W3) weight 4 : 25 x 110 / 2.66 = 1031 Ω R1-4 (W4) weight 8 : 25 x 110 / 5.33 = 516 Ω With these values, when PRS is minimum, the main resistor the value of which is equal to 110 Ω, is let alone. When PRS is maximum, all four trimming resistors are connected in parallel on the main resistor to have its value fall from 165 Ω to 110 Ω. Finally, when PRS has an interme diate value, a determined combination of the four trimming resistors according to the TABLE is connected in parallel thereon. For instance, if the measured value of the main resistor is 121 Ω, it will be required to connect trimming resistors of weights W1 and W2. For resistor struc ture RS1, the relative physical dimensions of main resistor R1 with its four associated trimming resistors R1 to R1-8 are shown in Fig. 3. The above calculations are based on the assumption that a pass-gate NFET offers a negligible ON-resistance (Ron) versus the trimming resistor value for sake of simplicity. However, in practice, this ON-resistance which depends on the NFET type and size (and more generally of the switch being used) should be taken into account for greater accuracy. For instance, still with the conventional CMOS technology mentioned above, we have set the ON-resistance of pass-gate NFET device PG1-1 equal to about 1/4 of the theoritical value, so that in reality R1-1 is made equal to about 3000 Ω with PG-1 resistance equal to 1000 Ω. A lot of wafers has been manufactured according to said conventional CMOS process and the chips diced therefrom have demonstrated that all termination resistors after adjustment were equal to 110 Ω with a precision of about +- 2%. Different techniques may be envisioned to select the desired pass-gate NFET devices. According to another important feature of the present invention, electrically blown fuses will be used to activate or not the control lines, which in turn enable or not the trimming resistors. The fuse blowing operation can be done in two different ways. A first method would consist in measuring a few main resistors alone (without any trimming resistor connected in parallel thereon) and, knowing their average value, blow the adequate fuses according to the above TABLE to reach the target value, i.e. the desired nominal value. The other method thanks to a special design of the fuses, would consist in simulating some combination of trimming resistors by the tester without physically blowing the fuses, and then select the one that would give the best results. The second method is a little bit longer but it allows more precise results. These two methods will be now described in more details. It has been seen that all eighteen main resistors substantially have the same value at +- 0,5% on a given chip (and corresponding trimming resistors as well). Hence, to adjust the eighteen main resistors of a same chip, it just suffices to measure one main resistor and to determine which combination of trimming resistors will be used. However, still pursuant to the first method, the tester starts by measuring the value of a few main resistors and computes their average (or center) value for increased precision. Then, the tester compares this average value with the resistance values corresponding to the boundaries of the 18 sectors of the PRS specifications given in the above TABLE (see also Fig. 2). As soon as the right sector has been determined, the tester knows which fuses have to be blown to activate the correct set of trimming lines to finally select the desired combination of trimming resistors. As a result, once the best combination has been determined, it is then possible to enable all the 4*18 pass-gate NFET devices by only four trimming lines the activation of which is only dependent upon the binary state of four storage cells. Measuring main resistors is possible when no fuse has been blown or with applying low voltage levels on all input pads. In the present case, all the 4x18 pass-gate NFET devices are off so that none of the trimming resistors is connected. To blow a fuse, a 10 V pulse is applied on the input pad which is tied to the fuse in question (e.g. input pad 18-1 for fuse F1). The fuse resistance being around 80 Ω, the current spike that is created in the fuse is in the range of 100/120 mA, and the thermal effect it causes therein vaporizes the fuse structure without any residue. To introduce the second method, it must be said that to neatly blow a fuse, an at least 7V amplitude pulse is applied to the fuse. If the pulse amplitude is between 5 and 7 V, the fuse is not well destroyed, and the reliability of the fuse blow is not guaranteed. If the pulse is below 3 V, then the fuse just heats without damage. The principle of this second method therefore consists in applying a 2.5 V level on the selected fuses so that the circuitry just behind the fuse will consider this voltage as a high logic level, just like if the fuses were blown. Hence, this way to operate allows the tester to measure the resistance value of the main resistor with various combinations of the trimming resistors and then choose the one that gives the best precision. The input pads 18-1 to 18-4 that control all the pass-gate NFET devices are normally at a low voltage since fuses tie them to Gnd. When calculation shows that a trimming line must be raised to a high voltage to enable the corresponding set of pass-gate NFET devices, the corresponding fuse structure is blown, so that the potential of the input pad that is tied to this fuse is pulled up, which in turn causes the trimming line to be activated (set high) by the two succesive inverters (e.g. T11, RB1 and T12, T13 in binary cell 17-1). Depending on the combination that the tester will find the best, adequate fuses will be blown to definitely set the chosen combination. Unlike the prior art solution, where fuses are generally blown by a laser beam, in this case, they are blown by current surges generated by the tester. The key advantage of electrically blown fuses over laser blown fuses is that a single pass operation is now permitted. In addition, there is no need for a laser tool and better chip quality is obtained since it would be probed once instead of twice (in case of pre/post fuse tests). Fuses that can be electrically blown are widely used in micro-electronics. They usually are metal made. Since the metal is naked in the fuse window to allow easy vaporization, the unblown fuses are subject to corrosion. Unlike, polysilicon material is not normally subject to corrosion, and moreover it will be covered by a boro-phospho-silicate glass (BPSG) layer which protects it. For all these reasons, polysilicon fuses that are electrically blown are by far preferred in the fabrication of the terminator chips of the present invention, so that unblown fuse structures will remain integer and conductive for ever. This invention offers several major advantages in terms of cost, accuracy, easiness of use and reliability. There is no more need for a complex and costly laser trimming apparatus. Now the tester does everything: it determines the best trimming combination, blows the fuses, and checks that the termination resistors exhibit the desired resistance value after fuse blow. In addition, as mentioned above, the tolerance of the post-fuse resistance of a resistor structure is close to 2% which results of 0.5% for the on-chip tracking and 1.5% for the trimming resolution. Because the best combination search, fuse blowing, and post-fuse test are performed in a single operation, the test step becomes a fast (below three seconds) and easy operation as a whole. Also, because no wafer transfer is required between equipments, the overall test/fuse/test turn-around-time (TAT) is improved. Finally, the present technique is highly reliable because the fuses are cleanly blown, with no risk that some residue remains or that an unblown fuse becomes corroded. These advantages are obtained just at the cost of integrating the four storage cells (with input pads) to allow the tester to access the fuses and eighteen arrays of four small trimming resistors and associated pass-gate NFET devices. Note that these input pads are not connected at the module level. Many variants may be envisioned still according to the teachings of the present invention. In particular, the number N of trimming resistors may be different to meet any desired precision. For instance, three trimming resistors per trimming array (with thus three storage cells), that offer eight combinations (in stead of sixteen with N = 4), may reveal to be sufficient in some applications.

Claims: A semiconductor integrated circuit (IC) chip including a plurality P of resistor structures (RS1 ...) each of said resistor structures comprising a main resistor (R1) and a resistor array, each array (15-1, ... ) consisting of a plurality N (N >= 2) of trimming resistors (R1-1, ... ) connected in parallel thereon, the equivalent resistance value of which can be electrically adjusted by a tester; wherein each trimming resistor has a fixed weight value and can be electrically connected in parallel on the main resistor independently one of another by a switch (PG1-1, ... ) serially connected therewith; and said semi conductor IC chip further comprising N binary storage cells, each storage cell (17-1, ... ) being provided each with a programmable fuse (F1, ... ) to control a trimming line (16-1) connected to the switch (PG-1) associated thereto to enable or disable it so that all trimming resistors having the same fixed weight value in said resistor arrays are connected in parallel on their respective main resistor or not. The IC chip of claim 1 wherein the main resistor is designed to have its minimum resistance value made equal to the desired nominal resistance value; the trimming resistors are designed so that when the resistance value of the main resistor is equal to the maximum value, all the trimming resistors are connected in parallel on the main resistor to have the resistor structure equivalent resistance equal to the desired nominal value with a precision of +- 2%; the trimming resistors are designed so that when the resistance value of the main resistor is equal to the minimum value, none of the trimming resistors are connected in parallel on the main resistor to still have the resistor structure equivalent resistance equal to the desired nominal value with a precision of +- 2%; and, the trimming resistors are designed so that when the resistance value of the main resistor is between said minimum and said maximum value, there is an adequate combination of trimming resistors to be connected in parallel on the main resistor to have the resistor structure equivalent resistance equal to the desired nominal value with a precision of +- 2%. The IC chip of claim 1 wherein the respective values of said trimming resistors are weighted in a geometric progression. The IC chip of claim 1 wherein said main and trimming resistors are made of polysilicon whose sheet resistivity (PRS) varies as a consequence of process variations. The IC chip of claim 4 wherein the polysilicon sheet resistivity PRS range is divided into 2 N sectors and a combination of trimming resistors (between none and all included) is assigned to each sector. The IC chip of claim 1 wherein said programmable fuse can be electrically blown by the tester during the test operation. The IC chip of claim 1 where said programmable fuse can withstand a moderate high voltage on sake of simulating the fuse blowing without actually blowing the programmable fuse, the resistance of which being in the order of 80 ohms. The IC chip resistor structure of claim 1 wherein said switch is a pass-gate NFET. Method for electrically adjusting the equivalent resistance value of a resistor structures included in a semiconductor IC chip according to any of claims 1 to 8 after fabrication by a tester during the test operation to approximate the desired nominal values comprising the steps of: providing P resistor structures, each comprising a main resistor (R1) and a resistor array, each array (15-1, ... ) consisting of a plurality N (N >= 2) of trimming resistors (R1-1, ... )connected in parallel thereon, the equivalent resistance value of which can be electrically adjusted by a tester; wherein each trimming resistor has a fixed weight value and can be electrically connected in parallel on the main resistor independently one of another by a switch (PG1-1, ... ) serially connected therewith; providing N binary storage cells, each storage cell (17-1, ... ) being provided each with a programmable fuse (F1, ... ) to control a trimming line (16-1) connected to the switch (PG-1) associated thereto to enable or disable it; measuring the resistance value of the main resistors; determining which combination of said trimming resistors is the most adequate to approximate the desired nominal value; applying moderate high voltage on the programmable fuses that correspond to said combination of trimming resistors to ensure that the desired nominal value is approximated; correcting said combination if this one reveals not close enough to the desired nominal value; and, definitely setting the combination that reveals the most accurate by applying much higher voltage on the programmable fuses that correspond to said combination, thus activating the correct set of switchs means to have said adequate combination of trimming resistors be connected in parallel on said main resistors, so that all trimming resistors having the same fixed weight value in said resistor arrays are connected in parallel on their respective main resistor.

Inventors: PETIT DOMINIQUE A, PETIT, DOMINIQUE A.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1995
Main classification: H01C17
IPC codes: H01C17, H01C13