Semiconductor integrated circuit

Abstract: In a semiconductor integrated circuit device, a MOS transistor has a relatively high built-in threshold, and in operation, a substrate bias is applied to the MOS transistor so as to cause the MOS transistor to forcibly have a reduced threshold, so that the MOS transistor operates at a high speed with the reduced threshold. When noise is detected, application of the substrate bias is stopped so that the MOS transistor restores the relatively high built-in threshold, and simultaneously, the MOS transistor is put in a standby condition, so that a malfunction can be prevented with the relatively high built-in threshold.

Description: Background of the Invention Field of the invention The present invention as it is defined in the appended claims relates to a semiconductor integrated circuit, and more specifically a semiconductor integrated circuit having a function of preventing a malfunction caused by noise. Description of related art In general, a high speed operation and a high integration of a semiconductor integrated circuit are being advanced with demands for a high speed operation and a high integration of a system because of advanced information processing technology. Recently, semiconductor integrated circuits have become to be used in a variety of devices, apparatuses and machines also because of advanced information processing technology. For example, the semiconductor integrated circuits are now widely used not only in in-house machines such as a rice cooker and electric washing machines, but also in large scaled machines such as automobiles, signals and crossing gates, which closely relate to human life. At present, the semiconductor integrated circuits themselves are deeply integrated into human activity and have become insensible to a human being. The reason for the fact that the semiconductor integrated circuits themselves are widely utilized in human activity, is that, machines and apparatuses incorporating therein the semiconductor integrated circuits, typified by a microcomputer in most cases, has intelligence, so that a comfortable environment is realized by the intelligent machines and apparatuses. On the other hand, because the semiconductor integrated circuit in incorporated in a machine, accident has become to happen. For example, it was reported that an accident resulting in injury or death occurred because a semiconductor integrated circuit constituting a program controlled device for an automatic speed controlling in an automobile having an automatic transmission caused a program runaway for an unknown reason. This is an example indicating that the semiconductor integrated circuits deeply integrated in human activity must have high reliability and high operation accuracy. In most cases, however, environment in which the semiconductor integrated circuits are actually used in various machines is large in temperature change and in moisture change and is filled with electric noise and mechanical vibration. This is opposite to the demands for high reliability and high operation accuracy. In addition, this is common in an operating environment of the semiconductor integrated circuits used for an engine control in automobile and aircraft. Therefore, when it is attempted to design a semiconductor integrated circuit to be used in a very severe environment as mentioned above, the circuit is designed with high reliability and high operation accuracy of the circuit being given a top priority. As a result, a high speed operation of the circuit is sacrificed not a few. Since the conventional semiconductor integrated circuits are exposed to electric noises as mentioned above, for example, Japanese Patent Application Laid-open Publication No. JP-A-4-367945 proposed to detect a noise in a signal line so as to put a microprocessor into a standby condition when the noise is detected and to maintain the microprocessor into the standby condition until the noise becomes not detected, in order to ensure that the microprocessor does not mistake the noise for a signal. In addition, Japanese Patent Application Laid-open Publication No. JP-A-1-20438 proposed to trigger a system setting when there is detected a noise which cannot be sufficiently attenuated by a noise attenuation circuit in a program controlled apparatus, in order to avoid a program runaway. These conventional semiconductor integrated circuits have been manufactured with a MOS transistor gate length being on the order of 1 µm and a MOS transistor threshold being on the order of 0.7 V (in N-channel MOS transistor). Accordingly, the above mentioned methods are effective in semiconductor integrated circuits which cause a simple control program to run with a clock on the order of 10MHz. However, characteristics of semiconductor integrated circuits generally used in control systems has become not limited to only the high reliability and a high accurate operation, and has been now required to meet with a high speed operation and a complicated operation. This demand for the high speed operation and the complicated operation is now increasing rapidly. As a result, semiconductor integrated circuits incorporated in control systems can no longer be accepted if they cannot realize the high speed operation and the complicated operation, similarly to semiconductor integrated circuits used in information processing systems such as EWS, and apparatuses incorporating therein a semiconductor integrated circuit cannot become a salable product. Under the above mentioned background, an effort for increasing the operation speed of semiconductor integrated circuits incorporated in general control systems has been advanced in a manner similar to that made in the semiconductor integrated circuits used in information processing systems. Namely, in accordance with a scaling rule in a design standard of the semiconductor process, efforts have been made to microminiaturize the semiconductor integrated circuits and to lower a supply voltage and a threshold of transistors and the temperature of operating environment. For example, the gate length of N-channel MOS transistors has been shortened to 0.35 µm from 1 µm in the prior art, and the supply voltage has been lowered from 5 V to 3 V. In addition, the threshold of MOS transistors has been lowered from 0.7 V to 0.4 V. With these improvements, the semiconductor integrated circuits have been constituted of N-channel MOS transistors intended for the high speed operation. However, it has been known that the above mentioned high-speed N-channel MOS transistors has poor resistance to noise on a ground (GND) line and a supply voltage (VDD) line and to a rapid change in the supply voltage in comparison with the prior art -channel MOS transistors, and therefore, is easily broken. This is because the supply voltage and the transistor threshold have been lowered but the noise on the GND line and the VDD line and the rapid change in the supply voltage are unchanged almost, with the result that the noise and the rapid change of the supply voltage having a conventional magnitude becomes large in comparison with the reduced supply voltage and the reduced threshold. Thus, a state hold in a semiconductor integrated circuit constituted of the high speed MOS transistors is easily flipped by noises that had not been a problem in the prior art semiconductor integrated circuit. Because of this, a malfunction of semiconductor integrated circuit constituted of the high speed MOS transistors cannot be completely prevented by a malfunction preventing circuit disclosed in Japanese Patent Application Laid-open Publication No. JP-A-4-367945 so configured to to put a microprocessor into a standby condition when possibility of the malfunction occurs, and to maintain the microprocessor into the standby condition until the possibility of the malfunction disappears. In this connection, it may be considered to apply a substrate bias in the standby condition so as to elevate a threshold voltage of the MOS transistors included in the semiconductor integrated circuit, for the purpose of preventing the malfunction. In this manner, since a substrate biasing circuit ceaselessly consume an electric power in a standby period, the power consumption in the standby condition becomes large in comparison with the conventional semiconductor integrated circuit. Examine a system proposed by Japanese Patent Application Laid-open Publication No. JP-A-1-20438 to trigger a system setting for preventing the malfunction of the semiconductor integrated circuit. A program for controlling the semiconductor integrated circuit becomes complicated year after year, and therefore, the number of program steps from the system resetting until the system start to actually operate. Accordingly, the method of No. JP-A-1-20438 becomes difficult to apply excepting for a limited application. As mentioned above, in the semiconductor integrated circuits required to have high reliability and a high accurate operation, the malfunction caused by the GND noise and VDD noise generated by noises generated by the semiconductor integrated circuits themselves or by external disturbance has become a large problem. In particular, in the case that the semiconductor integrated circuits are constituted of MOS transistor having a reduced threshold for meeting with the demands of the device size reduction and the supply voltage reduction so as to realize a high speed operation and a high integration degree, the malfunction occurrence percentage in logic gate circuits and other circuits constituted of low threshold MOS transistors, caused by the GND noise, the VDD noise and the rapid variation in the supply voltage, is higher than that in logic gate circuits and other circuits constituted of conventional high threshold MOS transistors, regardless of whether a circuit system is static or dynamic. As a result, even if a static circuit is put into a standby condition for suppress malfunction which might be caused by the GND noise, the VDD noise and the rapid variation in the supply voltage, since a noise level similar to the conventional circuit is relatively large in comparison with the reduced threshold of the low threshold transistor, a state holding capability is weakened. Accordingly, the state before the circuit is put into the standby condition cannot be held by only movement to the standby condition, with the result that when the circuit is returned from the standby condition, a malfunction occurs. Summary of the Invention Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit which has overcome the above mentioned defect of the conventional ones. Another object of the present invention is to provide a semiconductor integrated circuit capable of preventing a malfunction caused by noise such as the GND noise, the VDD noise and the rapid variation in the supply voltage. The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor integrated circuit device having a function of preventing malfunction caused by noise, comprising at least one MOS transistor having a relatively high built-in threshold, a substrate biasing means for applying a predetermined substrate bias to the at least one MOS transistor in operation so that the at least one MOS transistor has a reduced threshold lower than the built-in threshold, whereby the at least one MOS transistor can operate at a high speed, a noise detecting means for generation a noise detection signal when noise exceeding a predetermined level occurs, and a control means responding to the noise detection signal to put the semiconductor integrated circuit device into a standby condition and to cause the substrate biasing means to stop application of the predetermined substrate. bias to the at least one MOS transistor so that the at least one MOS transistor restores the built-in threshold in the standby condition. In one embodiment, the at least one MOS transistor is of an N-channel type and the substrate biasing means applies a predetermined positive substrate bias to the N-channel MOS transistor. In another embodiment, the semiconductor integrated circuit device is of a CMOS type including at least one N-channel MOS transistor formed in a P-well and at least one P-channel MOS transistor formed in a N-well, and the substrate biasing means applies a first predetermined voltage to the P-well so as to positively bias to the P-well and a second predetermined voltage to the N-well so as to negatively bias to the N-well. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a block diagram of a first embodiment of the semiconductor integrated circuit device in accordance with the present invention; Figure 2 is a diagrammatic sectional view of the semiconductor integrated circuit device of the first embodiment shown in Figure 1; Figure 3 is a timing chart illustrating an operation of the semiconductor integrated circuit device of the first embodiment shown in Figure 1; Figure 4 is a graph illustrating the characteristics of the substrate voltage (Vsub) to the threshold voltage (Vt) in a N-channel MOS transistor; Figure 5 is a graph illustrating the characteristics of the gate voltage (Vg) to the drain current (Id) in a N-channel MOS transistor; Figure 6 is a block diagram of a second embodiment of the semiconductor integrated circuit device in accordance with the present invention; Figure 7 is a diagrammatic sectional view of the semiconductor integrated circuit device of the second embodiment shown in Figure 6; Figure 8 is a timing chart illustrating an operation of the semiconductor integrated circuit device of the second embodiment shown in Figure 6; Figure 9 is a block diagram of the comparator incorporated in the semiconductor integrated circuit device of the first embodiment; Figure 10 is a detail circuit diagram of the substrate biasing circuit incorporated in the semiconductor integrated circuit device of the first embodiment; Figure 11 is a detail circuit diagram of the resetting circuit incorporated in the semiconductor integrated circuit device of the first embodiment; Figure 12 is a detail circuit diagram of the clock generator incorporated in the semiconductor integrated circuit device of the first embodiment; Figure 13 is a block diagram of the comparator incorporated in the semiconductor integrated circuit device of the second embodiment; Figure 14 is a detail circuit diagram of the substrate biasing circuit incorporated in the semiconductor integrated circuit device of the second embodiment; Figure 15 is a detail circuit diagram of the resetting circuit incorporated in the semiconductor integrated circuit device of the second embodiment; Figure 16 is a detail circuit diagram of the clock generator incorporated in the semiconductor integrated circuit device of the second embodiment; Figure 17 is a detail circuit diagram of the N-well substrate biasing circuit incorporated in the semiconductor integrated circuit device of the second embodiment; and Figure 18 is a detail circuit diagram of the P-well substrate biasing circuit incorporated in the semiconductor integrated circuit device of the second embodiment. Description of the Preferred embodiments Referring to Figure 1, a first embodiment of the semiconductor integrated circuit device in accordance with the present invention includes an N-channel MOS transistor 110 formed in a P-type semiconductor substrate. This N-channel MOS transistor 110 should be understood to represent a great large number of N-channel MOS transistors constituting a semiconductor integrated circuit device. The N-channel MOS transistor 110 is manufactured to have a threshold voltage Vt of 0.7 V. The shown semiconductor integrated circuit device also includes a substrate biasing circuit 106 for causing the threshold voltage Vt to 0.4 V when the semiconductor integrated circuit device is put in an operating condition, so that a high speed operation can be achieved. In addition, the shown semiconductor integrated circuit device also includes a noise level detecting circuit 101 for detecting a ground noise (GND noise) when a noise having a level not less than a predetermined level (for example 0.7 V) occurs on a ground line 100. In order to prevent a malfunction of the first embodiment of the semiconductor integrated circuit device caused by a chattering signal generated by a high frequency noise which would be generated for an overshooting of the operation in an input/output buffer, for example, this noise level detecting circuit 101 may includes a low pass filter having a cutoff frequency of 80 MHz, which is the same as that of a system clock, and a discriminating circuit including a resistor type voltage divider used for comparing a noise level with a reference voltage Vref of 0.7 V, a flipflop and a comparator, which are connected in sequence. These elements are not shown in the drawing. Furthermore, the shown semiconductor integrated circuit device includes a static latch 121 composed of an inverter 102 having a large driving power and having an input connected to an output signal 122 of the noise level detecting circuit 101 and another inverter 103 having a small driving power and an input connected to an output of the inverter 102 and an output connected to the input of the inverter 102. With this arrangement, when the output signal of the noise level detecting circuit 101 is brought to a high level indicative of generation of a noise, it is held in the static latch 121, and this condition is maintained until the output signal of the noise level detecting circuit 101 is brought to a low level indicating that the noise disappears or becomes negligible. Therefore, the static latch 121 notifies that an unnegligible noise is generating. An output 123 of the static latch 121 is connected to a comparator 104. Referring to Figure 9, the comparator 104 includes a shift register 132 receiving and holding the output 123 of the static latch 121, a watch dog timer 131 for driving this register 132, and a comparison circuit 133 triggered by an output 134 of the watch dog timer 131, for comparing the current output 123 of the static latch 121 with the output 123 of the static latch 121 before two clocks, stored in the shift register 132. When the result of comparison indicates inconsistency, if the output 123 of the static latch 121 is indicative of generation of a noise, the comparator 104 outputs a high level signal from its output 105. This high level signal 105 of the comparator is maintained until the content of the static latch changes. The first embodiment of the semiconductor integrated circuit device also includes a reset circuit 107 responding to a rising edge of the output signal 105 of the comparator 104 for returning from a standby condition to an operating condition, and a clock generator 108 responding to a rising of a reset signal 113 generated by the reset circuit 107, so as to cause an internal oscillating circuit 151 (shown in Figure 12) to start its oscillation. This clock generator 108 responds to a rising edge of the output signal 105 of the comparator 104, so as to stop its control clock output 109 at a first falling of the clock 109 after the rising edge of the output signal 105. Namely, the semiconductor integrated circuit is put into the standby condition. With the above mentioned arrangement, when the ground noise occurs on the ground line 100, the semiconductor integrated circuit is caused to stop its operation and is brought into the standby condition. A the same time, the substrate biasing circuit 106 responds to the rising edge of the output signal 105 so as to return the threshold Vth of the N-channel MOS transistor 110 to 0.7 V determined by the manufacturing process. If the noise disappears, the substrate biasing circuit 106 changes the threshold Vth of the N-channel MOS transistor 110 to 0.4 V, and the semiconductor integrated circuit is returned to the operating condition from the standby condition. The semiconductor integrated circuit is so configured that, in order to realize a high speed operation in the normal operating condition, the substrate potential is controlled by the substrate biasing circuit 106 so that the threshold Vth of the N-channel MOS transistor 110 is changed from 0.7 V determined by the manufacturing process to another threshold of 0.4 V which is desired in the operating condition. In combination with a 0.35 µm gate length MOS structure, this feature realizes a high speed operation. Referring to Figures 2 and 4, the substrate biasing circuit 106 corresponds to a substrate biasing variable voltage supply 208 shown in Figure 2. If a P-type semiconductor substrate 207 is biased to be positive in comparison with a potential (ground) of an N + diffusion region (source) 202, the threshold Vt of the N-channel MOS transistor 110 lowers in accordance with a characteristics curve of the threshold Vt to the substrate potential Vsub of the N-channel MOS transistor 110 as shown in Figure 4. Respective detailed circuit structures of the substrate biasing circuit 106, the resetting circuit 107 and the clock generator 108 are shown in Figures 10, 11 and 12. However, since the substrate biasing circuit 106, the resetting circuit 107 and the clock generator 108 can be constructed of well known circuits by a person skilled in the art, a detailed explanation will be omitted. As mentioned above, since the N-channel MOS transistor 110 can have a desired threshold Vt, the semiconductor integrated circuit composed of the N-channel MOS transistors 110 can realize a high speed operation. Here, the threshold Vt of the N-channel MOS transistors 110 can be set by the substrate biasing potential, but the threshold Vt of the N-channel MOS transistors 110 is required to be within a range capable of ensuring a proper operation of the semiconductor integrated circuit. As shown in Figure 5, the relation of the drain current Id to the gate voltage Vg in an enhancement N-channel MOS transistor is such that the threshold Vt of the N-channel MOS transistor is higher than a built-in voltage Vf between the P-type semiconductor substrate 207 and the N + diffusion region (source) 202. If the threshold Vt is in this range, the ON/OFF of the MOS transistor can be controlled by a gate voltage Vg. Accordingly, the substrate bias potential is set to ensure that the substrate potential Vsub is lower than the built-in voltage Vf. Now, operation of the first embodiment when the noise is detected, will be explained. Referring to Figure 3 illustrating various input and output waveforms and internal conditions in the first embodiment, in operation, noise caused by external disturbance appearing on the ground line 100 or noise caused by all-bit simultaneous operation of input/output buffers, is filtered in the noise level detecting circuit 101 for eliminating unnecessary high frequency components, and the noise level (or noise strength) is discriminated. When the noise level detecting circuit 101 outputs a high level signal 122 indicative of generation of the noise, this is held in the static latch 121 until the output signal 122 of the noise level detecting circuit 101 is brought to a low level. The output 123 of the static latch 121 is supplied to the comparator 104, where the shift register 132 stores the output 123 of the static latch 121, and the output 123 of the static latch 121 is compared with the output 123 of the static latch 121 before two clocks stored in the shift register 132 by the comparison circuit 133 If the result of the comparison in the comparison circuit 133 is inconsistency, and if the output 123 of the static latch 121 indicates the generation of the noise, the comparator 104 outputs the high level output signal 105. In response to a rising edge of the output signal 105 of the comparator 104, the substrate biasing circuit 106 stops application of a positive substrate bias voltage to the N-channel MOS transistor 110. The substrate bias voltage lowers within a half period of a system clock and becomes stable. At the same time, namely, in response to a rising edge of the output signal 105 of the comparator 104, the clock generator 108 stops its controlling clock output 109 at a first falling of the controlling clock with the highest priority. Thereafter, the clock generator 108 stops oscillation of the internal clock oscillator. The internal clock oscillator in the clock generator 108 is formed of large-size transistors, and therefore, has possibility of giving large influence on the level of the ground line. The internal clock oscillator is stopped before the rising of the oscillation waveform, so that the internal condition is maintained at a fallen-down condition. As a result of the stop of the clock generation, the semiconductor integrated circuit of the first embodiment is put in the standby condition for avoid the malfunction which would otherwise be caused by the ground noise. This first embodiment is constructed of a completely static circuit having no dynamic signal path, the circuit operation is stopped by only stopping the supplying of the controlling clock. Accordingly, the semiconductor integrated circuit of the first embodiment is put in the standby condition with requiring a processing for entering the standby condition other than stopping the supplying of the controlling clock. In the standby condition, the threshold Vt of the N-channel MOS transistors 110 realizing the high speed operation with a lowered threshold, is returned to 0.7 V built in accordance with the manufacturing process, since application of the substrate bias is stopped. Accordingly, there is obtained the standby condition having the ground noise resistance property similar to that of a semiconductor integrated circuit device formed of well-known N-channel MOS transistors widely used at present. Therefore, the break of register contents and flipflop contents caused by the ground noise, which becomes a problem in N-channel MOS transistors having a low built-in threshold for the high speed operation, can be effectively prevented. The good state holding characteristics in the standby condition is realized, not by an external voltage supply, but by the build-in voltage set in accordance with the manufacturing process. Therefore, the power consumption in the standby condition can be greatly reduced. In particular, since application of the substrate bias is stopped in the standby condition, differently from, rather contrary to, the conventional method, the power consumption can be reduced to a half or less. Now, operation returning to the operating condition from the standby condition will be described. Referring to Figures 1, 11 and 12 again, in response to the falling of the comparator output 105, a watch dog timer internally provided in the reset circuit 107 is reset to start its counting operation. the reset circuit 107 samples the comparator output 105 one at four system clocks. If the reset circuit 107 detects that the comparator output 105 is brought to the low level, the reset circuit 107 brings the reset signal 113 to the high level. The high level period of the reset signal 113 is controlled by the watch dog timer internally provided in the reset circuit 107 so as to correspond to one period of a system clock TCYK. In response to the rising of the reset signal 113, the clock generator 108 causes the internal oscillator 151 to start its oscillation operation. By further utilizing the watch dog timer internally provided in the reset circuit 107, the reset circuit 107 brings the reset signal 112 to a high level delayed from the rising of the reset signal 113 by a delay corresponding to ten periods of the system clock TCYK. The high level period of the reset signal 112 corresponds to one period of the system clock TCYK. In response to the rising edge of the reset signal 112, the substrate biasing circuit 106 starts to apply the positive substrate bias to the N-channel MOS transistor 110. The positive substrate bias becomes stable after a half period of the system clock TCYK. Furthermore, in response to the falling of the reset signal 113, the clock generator 108 starts to output the controlling clock 109 from the rising of the clock firstly outputted from the internal oscillator 151 in the clock generator 108. With this, the semiconductor integrated circuit device of the first embodiment is returned to the operating condition from the standby condition, with no possibility of malfunction caused by the ground noise. Assuming that the number of malfunctions caused by the ground noise is 100, malfunctions caused by a first noise of noises generated on the ground line are 50, and malfunctions triggered by a counteraction of the noise caused by a parasitic capacitance and similar phenomena are 30. The remaining 20 malfunctions is sorted to be due to a cause which becomes a problem in a low threshold MOS transistor. Specifically, these 20 cases can be exemplified by malfunctions caused by leakage or inversion of data held in MOS transistors which will occur even if the circuit is put into the standby condition. Therefore, the semiconductor integrated circuit device of the first embodiment can prevent the malfunctions directly caused by the ground noise. In addition, the semiconductor integrated circuit device of the first embodiment could prevent 85% of malfunctions other than the malfunctions directly caused by the ground noise. The remaining 15% of malfunctions include for example a malfunction caused by a counteraction of the ground noise generated during a short time before the semiconductor integrated circuit device of the first embodiment is put in the standby condition. As seen from the above, the semiconductor integrated circuit device of the first embodiment is so configured that, in the operating condition, the threshold of the N-channel MOS transistor is controlled by the substrate biasing circuit, so that the circuit operates at a high speed with a reduced threshold of the N-channel MOS transistor, and when a ground noise is detected, the application of the substrate bias is stopped so that the threshold of the N-channel MOS transistor is returned to a high built-in threshold determined in accordance with the manufacturing process, and at the same time, the circuit is put in the standby condition so as to hold the state of the circuit. Therefore, since the N-channel MOS transistor assumes the high built-in threshold determined in accordance with the manufacturing process, the N-channel MOS transistor is hardly subjected to the ground noise. In addition, a special voltage supply for holding the state of the circuit in the standby condition is not required, and the electric power consumption in the standby condition does not occur other than a minute leak current. Accordingly, the power consumption in the standby condition can be reduced to 50% or less of that required in the conventional semiconductor integrated circuit device. In the above mentioned embodiment, the semiconductor integrated circuit device formed of N-channel MOS transistors has been explained. It would be apparent to persons skilled in the art that a similar advantage can be obtained in a semiconductor integrated circuit device formed of P-channel MOS transistors. Referring to Figures 6 and 7, a second embodiment of the semiconductor integrated circuit device in accordance with the present invention includes an N-channel MOS transistor 615 formed in a P-well 709 formed in a P-type semiconductor substrate 716 having a twin-well CMOS structure and a P-channel MOS transistor 614 formed in an N-well 706 formed in the P-type semiconductor substrate 716. The N-channel MOS transistor 615 and the P-channel MOS transistor 614 should be understood to represent a great large number of N-channel MOS transistors and a great large number of P-channel MOS transistors which constitute a COMS semiconductor integrated circuit device. The N-channel MOS transistor 615 is manufactured to have a threshold voltage Vtn of +0.7 V, and the P-channel MOS transistor 614 is manufactured to have a threshold voltage Vtp of -0.7 V, The shown semiconductor integrated circuit device also includes a substrate bias control circuit 606, a P-well substrate biasing circuit 613, controlled by the substrate bias control circuit 606, for causing the threshold voltage Vtn of the N-channel MOS transistor 615 to 0.4 V when the semiconductor integrated circuit device is put in an operating condition, and an N-well substrate biasing circuit 612, controlled by the substrate bias control circuit 606, for causing the threshold voltage Vt- of the P-channel MOS transistor 615 to -0.4 V when the semiconductor integrated circuit device is put in an operating condition. With this arrangement, a high speed operation can be achieved. In addition, the shown semiconductor integrated circuit device also includes a noise level detecting circuit 601 for detecting that a noise (VDD noise) occurs on a supply voltage line 600.and/or that an abrupt level variation occurs on the voltage supply voltage. Similarlly to the first embodiment, in order to prevent a malfunction of the second embodiment of the semiconductor integrated circuit device caused by a chattering signal generated by a high frequency noise which would be generated for an overshooting of the operation in an input/output buffer, for example, this noise level detecting circuit 601 may includes a low pass filter having a cutoff frequency of 100 MHz, which is the same as that of a system clock, and a discriminating circuit including a resistor type voltage divider used for comparing a noise level with a reference voltage Vref of 0.7 V, a flipflop and a sequential comparator, which are connected in sequence. These elements are not shown in the drawing. Furthermore, the shown second embodiment of the semiconductor integrated circuit device includes a static latch 621 composed of an inverter 602 having a large driving power and having an input connected to an output signal 622 of the noise level detecting circuit 601 and another inverter 603 having a small driving power and an input connected to an output of the inverter 602 and an output connected to the input of the inverter 602. With this arrangement, when the output signal of the noise level detecting circuit 601 is brought to a high level indicative of generation of a noise, it is held in the static latch 621, and this condition is maintained until the output signal of the noise level detecting circuit 601 is brought to a low level indicating that the noise disappears or becomes negligible. Therefore, the static latch 621 notifies that an unnegligible noise is generating. An output 623 of the static latch 621 is connected to a comparator 604. Referring to Figure 13, the comparator 604 includes a shift register 632 receiving and holding the output 623 of the static latch 621, a watch dog timer 631 for driving this register 632, and a comparison circuit 633 triggered by an output 134 of the watch dog timer 631, for comparing the current output 623 of the static latch 621 with the output 623 of the static latch 621 before two clocks, stored in the shift register 632. When the result of comparison indicates inconsistency, if the output 623 of the static latch 621 is indicative of generation of a noise, the comparator 604 outputs a high level signal from its output 605. This high level signal 605 of the comparator is maintained until the content of the static latch changes. The second embodiment of the semiconductor integrated circuit device also includes a reset circuit 607 responding to a rising edge of the output signal 605 of the comparator 604 for returning from a standby condition to an operating condition, and a clock generator 608 responding to a rising of a reset signal 611 generated by the reset circuit 607, so as to cause an internal oscillating circuit 751 (shown in Figure 16) to start its oscillation. This clock generator 608 responds to a rising edge of the output signal 605 of the comparator 604, so as to stop its control clock output 609 at a first falling of the clock 609 after the rising edge of the output signal 605. Namely, the semiconductor integrated circuit is put into the standby condition. Similarly to the first embodiment, respective detailed circuit structures of the substrate bias control circuit 606, the resetting circuit 607, the clock generator 608 the N-well substrate biasing circuit 612 and the P-well substrate biasing circuit 613 are shown in Figures 14, 15,m 16, 17 and 18. However, since these circuits can be constructed of well known circuits by a person skilled in the art, a detailed explanation will be omitted. With the above mentioned arrangement, when a noise exceeding a predetermined level occurs on the VDD line 600, or when a abrupt level variation occurs in the voltage supply voltage, the semiconductor integrated circuit is caused to stop its operation and is brought into the standby condition. A the same time, the P-well substrate biasing circuit 613 returns the threshold Vtn of the N-channel MOS transistor 615 to a built-in threshold of 0.7 V determined by the manufacturing process, and the N-well substrate biasing circuit 612 returns the threshold Vtp of the P-channel MOS transistor 614 to a built-in threshold of -0.7 V determined by the manufacturing process. If the noise or the supply voltage variation disappears, the P-well substrate biasing circuit 613 changes the threshold Vtn of the N-channel MOS transistor 615 to 0.4 V, and the N-well substrate biasing circuit 612 changes the threshold Vtp of the P-channel MOS transistor 614 to -0.4 V. In addition, the semiconductor integrated circuit is automatically returned to the operating condition from the standby condition so as to succeed the operation. The semiconductor integrated circuit of the second embodiment is so configured that, in order to realize a high speed operation in the normal operating condition, the N-well in which the P-channel MOS transistor 614 is formed and the P-well in which the N-channel MOS transistor 615 is formed, are controlled by the N-well substrate biasing circuit 612 and the P-well substrate biasing circuit 613 both controlled by the substrate bias control circuit 606 in connection with a bias potential and an application timing of the bias potential, so that the threshold Vtn of the N-channel MOS transistor 615 is changed from the built-in threshold of 0.7 V determined by the manufacturing process to another threshold of 0.4 V which is desired in the operating condition, and the threshold Vtp of the P-channel MOS transistor 614 is changed from the built-in threshold of -0.7 V determined by the manufacturing process to another threshold of -0.4 V which is desired in the operating condition. In combination with a 0.35 µm gate length MOS structure, this feature realizes a high speed operation. Referring to Figures 6 and 7, the N-well substrate biasing circuit 612 corresponds to an N-well substrate biasing variable voltage supply 703 shown in Figure 7, which biases the N-well 704 formed in the P-type semiconductor substrate 716 to a potential negative to the potential of the P + diffusion layer (source) 705. The P-well substrate biasing circuit 613 corresponds to a P-well substrate biasing variable voltage supply 714 shown in Figure 7, which biases the P-well 709 formed in the P-type semiconductor substrate 716 to a potential positive to the potential of the N + diffusion layer (source) 713. Thus, the threshold of the N-channel MOS transistor 615 is set to a desired low threshold (+0.4 V) from the built-in threshold (+0.7 V) determined in accordance with the manufacturing process, and the threshold of the P-channel MOS transistor 614 is set to a desired low threshold (-0.4 V) from the built-in threshold (-0.7 V) determined in accordance with the manufacturing process. As a result, the CMOS semiconductor integrated circuit composed of the N-channel MOS transistors 615 and the P-channel MOS transistor 614 can realize a high speed operation. Now, operation of the second embodiment when the VDD noise is detected or when the abrupt supply voltage variation is detected, will be explained. Referring to Figure 8 illustrating various input and output waveforms and internal conditions in the second embodiment, in operation, noise caused by external disturbance appearing on the VDD line 600 or noise caused by all-bit simultaneous operation of input/output buffers, or an abrupt supply voltage variation of 1 V or more, is filtered in the noise level detecting circuit 601 so that unnecessary high frequency components are eliminated, and the noise level (or noise strength) is discriminated. When the noise level detecting circuit 601 outputs a high level signal 622 indicative of generation of the VDD noise or abrupt supply voltage variation, this is held in the static latch 621 until the output signal 622 of the noise level detecting circuit 601 is brought to a low level. The output 623 of the static latch 621 is supplied to the comparator 604, where the shift register 632 stores the output 623 of the static latch 621, and the output 623 of the static latch 621 is compared with the output 623 of the static latch 621 before two clocks stored in the shift register 632 by the comparison circuit 633 If the result of the comparison in the comparison circuit 633 is inconsistency, and if the output 623 of the static latch 621 indicates the generation of the VDD noise or the abrupt supply voltage variation, the comparator 604 outputs the high level output signal 605, which is maintained until the content of the static latch 612 changes. In response to a rising edge of the output signal 605 of the comparator 604, the substrate bias control circuit 606 causes the N-well substrate biasing circuit 612 and the P-well substrate biasing circuit 613 to stop application of their substrate bias voltage. Namely, the N-well substrate biasing circuit 612 stops application of the substrate bias voltage to the N-well in which the P-channel MOS transistor 614 is formed, and the P-well substrate biasing circuit 613 stops application of the substrate bias voltage to the P-well in which the N-channel MOS transistor 615 is formed. The stopping of the application of the substrate bias voltage to the N-well and the stopping of the application of the substrate bias voltage to the P-well can be performed in an arbitrary order but may be simultaneously performed. In any case, if a time from the stopping of the application of the substrate bias voltage until the threshold of the MOS transistors becomes stable at the built-in threshold, does not exceed a half of one period of the system clock, no adverse influence occurs. Simultaneously to the substrate bias control circuit 606, in response to a rising edge of the comparator output signal 605, the clock generator 608 stops its controlling clock output 609 at a first falling of the controlling clock with the highest priority. Thereafter, the clock generator 608 stops oscillation of the internal clock oscillator. The internal clock oscillator in the clock generator 608 is formed of large-size transistors, and therefore, has possibility of giving large influence on the level of the VDD line. The internal clock oscillator is stopped before the rising of the oscillation waveform, so that the internal condition is maintained at a fallen-down condition. As a result of the stop of the clock generation, the semiconductor integrated circuit of the second embodiment is put in the standby condition for avoid the malfunction which would otherwise be caused by the noise on the VDD line and the abrupt variation of 1 V or more on the VDD line. Now, operation returning to the operating condition from the standby condition will be described. Referring to Figures 6, 15 and 16 again, in response to the falling of the comparator output 605, a watch dog timer internally provided in the reset circuit 607 is reset to start its counting operation. the reset circuit 607 samples the comparator output 605 one at four system clocks. If the reset circuit 607 detects that the comparator output 605 is brought to the low level as the extinction of the VDD noise or the depression of the abrupt supply voltage variation, the reset circuit 607 brings the reset signal 611 to the high level. The high level period of the reset signal 611 is controlled by the watch dog timer internally provided in the reset circuit 607 so as to correspond to one period of a system clock TCYK. In response to the rising of the reset signal 611, the clock generator 608 causes the internal oscillator 751 to start its oscillation operation. By further utilizing the watch dog timer internally provided in the reset circuit 607, the reset circuit 607 brings the reset signal 610 to a high level delayed from the reset signal 611 by twenty periods of the system clock TCYK. The high level period of the reset signal 610 corresponds to one period of the system clock TCYK. In response to the rising edge of the reset signal 610, the substrate bias control circuit 606 causes the N-well substrate biasing circuit 612 and the P-well substrate biasing circuit 613 to restart the application of their substrate bias voltage. Namely, the N-well substrate biasing circuit 612 starts to apply the negative substrate bias in relation to the P-channel MOS transistor 614, and the P-well substrate biasing circuit 613 starts to apply the positive substrate bias in relation to the N-channel MOS transistor 615. Applications of the two substrate biases are simultaneously restarted in order to prevent the waveform distortion and the operation timing deviation in relation to the clock generator 608 which has already restarted its oscillation operation of 100 MHz (which is the same as the frequency of the system clock). The substrate biases becomes stable within a half period of the system clock TCYK. Furthermore, in response to the falling of the reset signal 610, the clock generator 608 starts to output the controlling clock 609 from the rising of the clock firstly outputted from the internal oscillator 751 in the clock generator 608. With this, the semiconductor integrated circuit device of the second embodiment is returned to the operating condition from the standby condition, with no possibility of malfunction caused by the VDD noise or the abrupt supply voltage variation. Therefore, the thresholds of N-channel MOS transistors and P-channel MOS transistors in the CMOS type semiconductor integrated circuit device are, in operation, controlled to desired reduced thresholds by the substrate biasing, respectively, so that the circuit operates at a high speed with a reduced threshold of the N-channel and P-channel MOS transistors. When occurs an external or internal disturbance on the VDD line or an abrupt supply voltage variation occurs in the CMOS type semiconductor integrated circuit device, the thresholds of N-channel MOS transistors and P-channel MOS transistors are returned to their respective built-in thresholds which are higher than the reduced thresholds desired for the high speed operation. At the same time, the circuit is put in the standby condition so as to hold the state of the circuit. Accordingly, there is obtained the standby condition having the VDD noise resistance property similar or superior to that of a semiconductor integrated circuit device formed of well-known high-threshold MOS transistors, widely used at present. Also in this second embodiment, since a special voltage supply for holding the state of the circuit in the standby condition is not required, and since the substrate bias circuits do not consume an electric power in the standby condition, the power consumption in the standby condition can be reduced to 50% or less of that required in the conventional semiconductor integrated circuit device. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A semiconductor integrated circuit device having a function of preventing malfunction caused by noise, comprising at least one MOS transistor (110) having a relatively high built-in threshold, a substrate biasing means (106) for applying a predetermined substrate bias to said at least one MOS transistor in operation so that said at least one MOS transistor has a reduced threshold lower than said built-in threshold, whereby said at least one MOS transistor (110) can operate at a high speed, a noise detecting means (101) for generation a noise detection signal when noise exceeding a predetermined level occurs, and a control means (104) responding to said noise detection signal to put the semiconductor integrated circuit device into a standby condition and to cause said substrate biasing means (106) to stop application of said predetermined substrate bias to said at least one MOS transistor (110) so that said at least one MOS transistor restores said built-in threshold in said standby condition. A semiconductor integrated circuit device claimed in Claim 1 wherein said at least one MOS transistor (110) is of an N-channel type and said substrate biasing means (106) applies a predetermined positive substrate bias to said N-channel MOS transistor. A semiconductor integrated circuit device claimed in Claim 1 wherein the semiconductor integrated circuit device is of a CMOS type including at least one N-channel MOS transistor formed in a P-well and at least one P-channel MOS transistor formed in a N-well, and said substrate biasing means (106) applies a first predetermined voltage to said P-well so as to positively bias to said P-well and a second predetermined voltage to said N-well so as to negatively bias to said N-well.

Inventors: HIRAYAMA TAKESHI, HIRAYAMA, TAKESHI
Applicants: NEC ELECTRONICS CORP, NEC ELECTRONICS CORPORATION
Application year: 1995
Main classification: H03K17
IPC codes: G06F11, H01L21, H01L27, H03K19