Semiconductor memory device

Abstract: A semiconductor memory device includes first and second MOS transistors connecting a pair of data lines with a specific potential supplying node (14). A power transmitting circuit (17, 18) connects the specific potential supplying node with a first power supply circuit (5) supplying an equalizing potential (HVcc), and a second power supply circuit (8, 9) supplying a precharge potential (VPL, VPH), the power transmitting circuit supplying the precharge potential until both the first and second MOS transistors are turned on, and supplying the equalizing potential after the first and second MOS have been turned on.

Description: The present invention relates to a semiconductor memory device, such as a dynamic random access memory (hereinafter referred to as DRAM), and in particular to a memory device which includes a precharge and equalization circuit for quickly bringing a pair of data lines to a fixed potential. An example of a conventional equalizing circuit is shown in US-A-5,036,492. The equalizing circuit is formed of two transistors provided between a pair of bit lines connected to a precharge circuit for supplying a predetermined potential. -The two transistors have their sources connected respectively to the data lines, their drains connected with each other, and gates to which complementary equalizing signals are supplied. A bleeder current device is also connected to the drains. With such a configuration, the two transistors are concurrently activated, by means of the complementary equalizing signals, to set the bit lines to the same potential. The bleeder current device absorbs or supplies current so that the potentials on the bit lines do not depart from the set potential. The above-described equalizing circuit requires a precharge circuit, and two control signals are required to control the precharge circuit and the equalizing circuit, so that the control system is complicated, and it is difficult to increase the overall operation speed of the device. US-A-4,494,221 discloses a bit line precharging and equilibrating circuit, in which a transistor is coupled to the common node of a pair of precharge/equalizing transistors to establish a momentary reduction of the potential at the common node, so as to expedite the conduction of the precharge/equalizing transistors. The transistor circuit is configured so that its source is coupled to the common node and its gate and drain are coupled to the same voltage source (Vcc). JP-A-58 035 795 and Patent Abstracts of Japan, vol. 7, no. 117 (P. 198), 21 May 1983 discloses another type of bit line precharge and equalizing circuit according to the pre-characterised portion of claim 1. In accordance with the invention, there is provided a semiconductor memory device comprising a pair of data lines for transferring complementary signals, said complementary signals assuming a first potential (Vcc) and a second potential (GND) respectively, an equalizing circuit having a first MOS transistor connected between one of said pair of data lines and a specific potential supplying node, and a second MOS transistor connected between the other of said pair of data lines and the specific potential supplying node, said first and second MOS transistors being made conductive in accordance with a control signal to electrically connect said pair of data lines together, and a power transmitting circuit for connecting said specific potential supplying node to an equalizing potential and a precharge potential respectively, said power transmitting circuit supplying the precharge potential to said specific potential supplying node until both of said first and second MOS . transistors are turned on, and supplying the equalizing potential to said specific potential supplying node after said first and second MOS transistors are turned on, said power transmitting circuit comprising a first switching element having a first terminal connected to said specific potential supplying node and a second terminal connected to a first power supply circuit for supplying the equalizing potential, characterised in that said equalizing potential (HVcc) is substantially half of said first potential (Vcc), and in that said power transmitting circuit further comprises a second switching element having a first terminal connected to said specific potential supplying node and a second terminal connected to a second power supply circuit separate from the first power supply circuit for supplying the precharge potential. Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram showing a precharge and equalization circuit. Figure 2 is a waveform diagram showing the operation of the circuit of Figure 1. Figure 3 is a circuit diagram showing an example of a precharge and equalization circuit according to the invention. Figure 4 is a waveform diagram showing the operation of the circuit of Figure 3. Figure 5 is a circuit diagram of a VPL potential generating means for the circuit of Figure 3. Figure 6 is a circuit diagram showing a further example of a precharge and equalization circuit according to the invention. Figure 7 is a circuit diagram showing yet a further example of a precharge and equalization circuit according to the invention. Figure 8 is a waveform diagram showing the operation of the circuit of Figure 7. Figure 9 is a circuit diagram showing a still further example of a precharge and equalization circuit according to the invention. In the various figures of the drawings, identical reference numerals denote identical or corresponding elements or components. Figure 1 is a circuit diagram of a precharge and equalization circuit described and claimed in European patent application number 95300038.7 (EP-A-0 662 689), from which this application is divided. The precharge and equalization circuit shown in Figure 1 comprises an equalizing circuit 10, which is disposed between a pair of data lines 1 and 2 connected to an amplifier 3, such as a sense amplifier, via switches 4. The equalizing circuit 10 comprises a pair of switching elements, in the form of N-channel MOS transistors 11 and 12 having their drains connected to the data lines 1 and 2, respectively, their sources both connected to 2 specific potential supplying node 14, and their gates connected to a control signal line 6. The precharge and equalization circuit further comprises a power transmitting circuit which is formed of an N-channel MOS transistor 13 having a gate connected to a second control signal SE. The drain of the transistor 13 is connected to the specific potential supplying node 14, and the source of the transistor 13 is connected to an equalizing potential power supply circuit 5 supplying an equalizing potential HVcc (Vcc/2). The second control signal SE makes the MOS transistor 13 non-conductive while the control signal 6 changes from the inactive state to the active state, and making the MOS transistor 13 conductive after the first and second switching elements 11 and 12 are made conductive. The data lines 1 and 2 are driven by the amplifier 3 via the switches 4 to transfer complementary information (Vcc level or the GND (ground) level). For reading data from a memory cell not shown, the switch 4 is turned on to drive the pair of data lines 1 and 2 by means of the amplifier 3 for the purpose of information transfer. They are assumed to be set at the Vcc level and the GND level, respectively. The control line 6 is at the Low level (GND level), so that the transistors 11 and 12 are off, and the control signal SE is at the High level, and the transistor 13 is on, and the potential of a node 14, which is the specific potential supplying node, is at HVcc. After the information transfer is completed, the switches 4 are turned off to isolate the amplifier 3 from the data lines 1 and 2, and the control signal SE is brought to the Low level to turn off the transistor 13, and the potential of the control line 6 is raised to the High level to commence the equalizing operation, in preparation for the next cycle of data transfer operation. When the potential of the control line 6 exceeds the threshold potential Vth of the transistor 12, the transistor 12 is turned on, and the potential level of the node 14 is lowered. This is because the node 14 is isolated from the power supply circuit 5, and the parasitic capacitance of the node 14 is small compared with the data line 2 at the GND level, so that the charge is drawn from the node 14. Because of the lowering of the potential level of the node 14, the gate voltage of the transistor 11 becomes sufficient, i.e., exceeds the threshold, also denoted by Vth, of the MOS transistor 11, and the transistor 11 is turned on. As a result, the potential level of the data line 1 is lowered. Thereafter, the control signal SE is raised to the High level at a predetermined timing, the node 14 is connected to the power supply circuit 5, to equalize the potentials of the data lines 1 and 2 to HVcc. Because the potential of the node 14 is lowered before the transistor 11 turns on, it takes less time for the MOS transistor 11 to turn on, than if the potential of the node 14 is fixed at the equalizing potential HVcc. If the potential of the node 14 is fixed at HVcc, the MOS transistor 11 is not turned on until the potential on the control line 6 exceeds HVcc + Vth (Vth being the threshold of the MOS transistor 11). Accordingly, the MOS transistors 11 and 12 are turned on in a shorter time than if the node 14 is not isolated from the equalizing potential power supply circuit 5. The pair of data lines are quickly equalized by means of a relatively simple configuration. Moreover, the number of transistors connected to the control line 6 is two per pair of data lines, so that delay in the rise of the data lines due to parasitic gate capacitances can be avoided. Furthermore, increase in the power consumption in the equalizing circuit is small. Referring to Figure 3, the precharge and equalization circuit according to the invention comprises a plurality of equalizing circuits, all denoted by 10. The equalizing circuits 10 are provided between respective pairs of data lines, all denoted by 1 and 2. Each of the equalizing circuits 10 is disposed between the corresponding pair of data lines 1 and 2, which are connected to an amplifier, such as a sense amplifier, not shown via switches, in the same way as in Figure 1. The equalizing circuit 10 comprises first and second switching elements, in the form of N-channel MOS transistors 11 and 12 having their drains connected to the data lines 1 and 2, respectively, their sources connected together at the specific potential node 14, and their gates connected to a common control line 6. The precharge and equalization circuit further comprises third and fourth switching elements 17 and 18 connected to the respective equalization circuits, and are disposed between the corresponding pair of data lines 1 and 2. First terminals of the switching elements 17 and 18 are connected to the node 14. A second terminal of the switching element 17 is connected to the power supply circuit 5 supplying the equalizing potential HVcc (Vcc/2). A second terminal of the switching element 18 is connected to a second, or precharge potential power supply circuit 8 supplying a precharge potential VPL. The potential VPL is set be lower than HVcc and is higher than ground potential (GND). The power supply circuits 5 and 8 are provided in common for a plurality of equalizing circuits, and connected to the plurality of the third and fourth switches 17 and 18 for the respective equalizing circuits 10. The switching elements 17 and 18 may be formed of transistors, such as N-channel MOS transistors. In such a case, the second control signals are applied to the gates of the transistors, to control their conduction and non-conduction. The operation of this embodiment will next be described with reference to FIG. 4. First, the pair of data lines 1 and 2 are driven by an amplifier, such as a sense amplifier, not shown, for the purpose of information transfer, and respectively set at the Vcc level and the GND level. The control line 6 is at the Low (GND) level. Accordingly, the transistors 11 and 12 are off. The switching element 18 is on, and the switching element 17 is off. The potential of the node 14 is at VPL. When information transfer is completed, the amplifier, such as a sense amplifier, not shown, is isolated from the pair of data lines, and the potential level of the control line 6 is raised to the High level, to commence the equalizing operation in preparation for the next cycle of data transfer operation. That is, when the control line 6 exceeds the threshold potential Vth of the transistor 12, the transistor 12 is turned on, to raise the potential level of the data line 6. At the same time, the node 14 is at the precharge potential VPL, lower than the equalizing potential HVcc, so that when the potential level of the control line 6 exceeds VPL + Vth, (Vth being the threshold of the transistor 11,) the transistor 11 is turned on and the level of the data line 1 is lowered. After that, at a predetermined timing, the switching element 18 is turned off, and the switching element 17 is turned on, to equalize the pair of data lines to the potential HVcc. In this embodiment, before the commencement of the equalizing operation, the node 14 is set at a potential VPL lower than the equalizing potential, and the on-resistances of the transistors 11 and 12 at the time of commencement of the equalization are made equal to each other. Accordingly, the operation is quicker than in the case of the circuit of Figure 1 in which the MOS transistor connected to the data line having the GND potential is turned on, to lower the node 14. Moreover, it is desirable that the second power supply circuit 8 has a larger driving capability than the first potential power supply circuit 5 to quickly precharge the node 14, and thereby expedite the conduction of the switching elements 11 and 12. In addition, the power consumption can be reduced. Furthermore, since the equalizing circuit is formed of an N-channel transistors, the area occupied by the device as a whole can be reduced. The precharge potential power supply circuit 8 may be formed as shown in FIG. 5. The illustrated power supply circuit 8 provides a potential VPL lower than the equalizing potential HVcc and higher than the ground potential (GND). This power supply circuit 8 comprises two comparators 32 and 33, and resistance elements 33 and 34. The positive terminal of the comparator 32 is connected to a signal line 31 for supplying the potential Vcc, and the negative terminal of the comparator 32 is connected to one end of the resistance element 33, and the output of the comparator 32. The other end of the resistance element 33 is connected to one end of the resistance element 34 and the positive terminal of the comparator 36, and the other end of the resistance element 34 is connected to the ground. The negative terminal of the comparator 36 is connected to the output signal line 37 of the comparator 36. The output of the comparator 36, at its output signal line 37 provides the potential VPL. Referring to FIG. 6, this example is similar to that shown in FIG. 3, but the switching elements 17 and 18 are not provided for the respective equalizing circuits 10, but are provided in common for a plurality of equalizing circuits 10, and away from the data lines 1 and 2 and the equalizing circuits 10. Specifically, first terminals of the switching elements 17 and 18 are connected to the nodes 14 of a plurality of equalizing circuits 10. A second terminal of the switching element 17 is connected to the power supply circuit 5, and a second terminal of the switching element 18 is connected to the power supply circuit 8. Thus, the switching element 17 connects, when conductive, the power supply circuit 5 with the nodes 14 of a plurality of equalizing circuits 10. The switching element 18 connects, when conductive, the power supply circuit 8 with the nodes 14 of a plurality of equalizing circuits 10. The switching elements 17 and 18 are controlled, in the same way as the switching elements 17 and 18 in FIG. 3 The operation of the circuit of Figure 6 is therefore similar to the operation of the circuit of Figure 3. An additional advantage of this embodiment is that the number of the switching elements and the number of wiring conductors of the equalizing circuits can be reduced, and the area occupied by the device as a whole can be reduced. Figure 7 shows a further example of a precharge and equalization circuit. Figure 8 is a waveform diagram showing the operation of the equalizing circuit of Figure 7. This embodiment is similar to the circuit of Figure 3, but the switching elements forming each equalizing circuit 10 comprise P-channel MOS transistors 21 and 22. The gates of the P-channel MOS transistors 21 and 22 are connected to a common control line 6, the potential on which is lowered to the ground when the transistors 21 and 22 are to be made conductive. In place of the power supply circuit 8 of Figure 3, a power supply circuit 9 is provided. The power supply circuit 9 provides a potential VPH which is higher than HVcc and lower than Vcc. The operation will next be described with reference to Figure 8. First, for the purposes of a reading operation, the pair of data lines 1 and 2 are driven by an amplifier, such as a sense amplifier, not shown, for the purpose of information transfer, and respectively set at the Vcc level and the GND level. The control line 6 is at the High (Vcc) level. Accordingly, the transistors 21 and 22 are off. The switching element 18 is on, and the switching element 17 is off. The potential of the node 14 is therefore at VPH. When information transfer is completed, the amplifier, such as a sense amplifier, not shown, and is isolated from the pair of data lines, and the control line 6 is lowered to the Low level, to commence the equalizing operation, in preparation for the next cycle of data transfer operation. That is, when the control line 6 falls below Vcc - Vtp (Vtp being the threshold of the transistor 21), the transistor 21 is turned on, to lower the potential level of the data line 1. At the same time, the node 14 is is at the precharge potential VPH, higher than the equalizing potential HVcc, so that when the the control line 6 falls below VPH - Vtp, (Vtp being the threshold of the transistor 22) the transistor 22) is turned on and the level of the data line 2 is raised. After that, at a predetermined timing, the switching element 18 is turned off, and the switching element 17 is turned on, to equalize the pair of data lines 1 and 2 to the potential HVcc. This configuration replaces the MOS transistors contained in each equalizing circuit of Figure 3 with P-channel MOS transistors, and yet realises similar operations. In this embodiment, like Figure 3 (although the equalizing circuit of Figure 3 uses a low VPL), before the commencement of the equalizing operation, the circuit is in a stand-by state, in which the node 14 is set at a potential VPH higher than the equalizing potential, and high-speed equalization is achieved, by having the on-resistances of the transistors 21 and 22 at the time of commencement equal to each other. Moreover, since the equalizing circuits are formed of P-channel MOS transistors, if the equalizing potential is set near Vcc to eliminate the effect of noises of the GND level, equalization of an even higher speed can be achieved. Figure 9 shows another embodiment. This embodiment is similar to the circuit of Figure 7, but the switching elements 17 and 18 are provided in common for a plurality of equalizing circuits 10, and away from the data lines 1 and 2, and the equalizing circuits 10. Specifically, first terminals of the switching elements 17 and 18 are connected to the nodes 14 of a plurality of equalizing circuits 10. A second terminal of the switching element 17 is connected to the power supply circuit 5, and a second terminal of the switching element 18 is connected to the power supply circuit 9. Thus, the switching element 17 connects, when conductive, the power supply circuit 5 with the nodes 14 of a plurality of equalizing circuits 10. The switching element 18 connects, when conductive, the power supply circuit 8 with the nodes 14 of a plurality of equalizing circuits 10. The switching elements 17 and 18 are controlled, in the same way as the switching elements 17 and 18 in Figure 7. The operation of this circuit is therefore similar to the operation of the circuit of Figure 7. An additional advantage of this embodiment is that the number of the switching elements and the number of the wiring conductors of the equalizing circuits can be reduced, and the area occupied by the device as a whole can be reduced. The invention is not limited to the examples described above. The switching elements may be all formed of transistors. If the transistors are all of the same channel type, fabrication of the device is simpler. The inventive concept described in connection with Figure 3 can also be applied to a situation where the switching elements of the equalizing circuit are formed of P-channel MOS transistors. In such a case, the control signal is at a high level when it is in an active state, and is at a low level when it is in an inactive state. As the potential of the control signal line is lowered (below a threshold of the MOS transistor) one of the MOS transistors (first MOS transistor) connected to one of the data lines which has transferred the signal of a higher potential level is made conductive, so that the potential of the specific potential supplying node is raised. Because of the potential increase in the specific potential supplying node, the MOS transistor (second MOS transistor) connected to the data line having a lower potential is made conductive when the potential of the control signal becomes sufficiently low. The potential sufficiently low to turn on the second MOS transistor is the sum of the threshold of the transistor and the potential of the specific potential supplying node, which is higher than if the specific potential supplying node is fixed at the equalizing potential. Accordingly, the MOS transistors are made conductive in a shorter time, than if the specific potential supplying node is not isolated from the equalizing power supply circuit.

Claims: A semiconductor memory device comprising: a pair of data lines (1,2) for transferring complementary signals, said complementary signals assuming a first potential (Vcc) and a second potential (GND) respectively; an equalizing circuit (10) having a first MOS transistor (11, 21) connected between one (1) of said pair of data lines and a specific potential supplying node (14), and a second MOS transistor (12, 22) connected between the other (2) of said pair of data lines and the specific potential supplying node (14), said first and second MOS transistors (11, 12, 21, 22) being made conductive in accordance with a control signal (6) to electrically connect said pair of data lines (1,2) together; and a power transmitting circuit (17,18) for connecting said specific potential supplying node (14) to an equalizing potential (HVcc) and a precharge potential (VPL, VPH) respectively, said power transmitting circuit (17, 18) supplying the precharge potential (VPL, VPH) to said specific potential supplying node (14) until both of said first and second MOS transistors are turned on, and supplying the equalizing potential (HVcc) to said specific potential supplying node (14) after said first and second MOS transistors are turned on; said power transmitting circuit comprising a first switching element (17) having a first terminal connected to said specific potential supplying node (14) and a second terminal connected to a first power supply circuit (5) for supplying the equalizing potential (HVcc), characterised in that said equalizing potential (HVcc) is substantially half of said first potential (Vcc), and in that said power transmitting circuit further comprises a second switching element (18) having a first terminal connected to said specific potential supplying node (14) and a second terminal connected to a second power supply circuit (8, 9) separate from the first power supply circuit for supplying the precharge potential (VPL, VPH). A semiconductor memory device according to claim 1, wherein said first and second switching elements (17, 18) are disposed away from the data lines. A semiconductor memory device according to claim 1 or 2, wherein said first and second switching elements (17, 18) are provided in common for a plurality of equalizing circuits for respective pairs of data lines. A semiconductor memory device according to any one of the preceding claims, wherein said first and second MOS transistors (11,12, 21, 22) of said equalizing circuit have their gate electrodes connected to receive said control signal. A semiconductor memory device according to any one of the preceding claims, wherein said first and second MOS transistors comprise N-channel MOS transistors (11, 12), said precharge potential (VPL) is lower than the equalizing potential and higher than the second potential (GND), and said power transmitting circuit (17, 18) causes the potential of said specific potential supplying node (14) to be lowered at least for a period after one of said first and second MOS transistors becomes conductive and before the other of said first and second MOS transistors has become conductive. A semiconductor memory device according to any one of claims 1 to 4, wherein said first and second MOS transistors comprise P-channel MOS transistors (21, 22), said precharge potential (VPH) is higher than the equalizing potential and lower than the first potential (Vcc), and said power transmitting circuit (17, 18) causes the potential of said specific potential supplying node (14) to be raised at least for a period after one of said first and second MOS transistors becomes conductive and before the other of said first and second MOS transistors has become conductive. A semiconductor memory device according to any one of the preceding claims, wherein said first and second switching elements (17, 18) comprise MOS transistors.

Inventors: TANABE TETSUYA, TANAKA YASUHIRO, TANABE, TETSUYA, TANAKA, YASUHIRO, Tanabe, Tetsuya, c/o Oki Electric Industry Co Ltd, Tanaka, Yasuhiro, c/o Oki Electric Industry Co Ltd
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1995
Main classification: G11C11
IPC codes: G11C7, G11C11