Redundancy scheme for memory circuits

Abstract: A redundancy scheme for memory circuits that eliminates the need for physical disconnection or logical deselection of defective elements. The invention does not rehire disabling a defective element and allows it to operate and generate bad data. The circuit is designed such that the redundant element is able to override the defective element. Various approaches to row and column redundancy based on this principal are disclosed for memory circuit such as dynamic and static random access memories.

Description: BACKGROUND OF THE INVENTION The present invention relates in general to integrated circuit memories, and in particular to an improved redundancy scheme used in memory circuits. To reduce manufacturing costs, manufacturers of integrated circuits search for ways to improve yields and reduce the rejection rate for defective individual parts. One method of reducing the rejection rate is to provide redundant or auxiliary circuit components on the integrated circuit. This method is practical where testing can locate the defective component, and the circuit is readily reconfigurable to substitute a redundant equivalent for the defective component. This method is widely used in integrated circuit memory arrays such as random access memories. Memory circuits are characterized by the regular repetition of multitudes of memory cells. The location of each memory cell is defined by a unique address which typically identifies a particular row and column in the memory matrix arrays. The memory circuit includes row and column decoders that decode different combinations of signals at an address input to the memory circuit. Memory circuits provide for redundancy by including on the same circuit several duplicate rows and/or columns of memory cells to replace any row or column having defective memory cells. Separate decoders are provided for the redundant rows or columns that are programmable using programming elements such as fusible links. Once the integrated circuit is tested and the locations of the defective memory cells are determined, the programmable redundancy decoders are programmed to decode those addresses that correspond to the rows or columns with defective cells. The defective rows or columns are subsequently disabled. This way every time a defective row or column is addressed, a redundant equivalent is selected instead. To disable the defective rows or columns, existing memory circuits typically either physically disconnect the defective element using laser blown fuses, or logically deselect the defective row or column. There are problems associated with both these methods. Physically disconnecting a defective row or column typically requires laser zapping of fuse elements that are spaced at the pitch of the column or row. The close spacing between the fuse elements makes them very difficult targets to hit and requires great accuracy in laser zapping. Fuse elements also tend to take a large silicon area adding to the size and cost of the integrated circuit. Logical deselection of the defective element requires adding a disable input to the main decoders. This input is driven by the output of the programmable redundancy decoder such that when a redundant row or column is selected, the output is asserted, logically disabling the main decoders. This approach, however, slows down the device by adding to the memory access time. Because there are a few gate delays between the time a redundant element is selected to the time the main decoders are disabled, there is a short interval during which the main decoder selects the defective element, and the redundant decoder selects a spare row or column. Therefore, the access must be delayed until the defective element is cleared before reading data. One redundancy method that does not require disabling the defective memory elements is proposed in the IBM Technical Disclosure Bulletin, September 1991, vol. 34, Nº4A, pp 271-273. This method, however, requires designing a different redundant memory cell that is larger in size than the regular memory cell. This results in increased area and power consumption, layout complexity (arrays having different pitch), additional yield concerns, longer recovery time after a read operation, among other drawbacks. There is therefore a need for improved redundancy schemes for use in memory circuits. SUMMARY OF THE INVENTION The present invention as defined in independent claims 1 and 8, provides two circuit embodiments that eliminate the need for deselection either with fusible links or with logical deselection. The invention allows the contents of a selected equivalent redundant element to override the contents of a selected defective element. The defective element need not be disabled, and is allowed to generate bad data. Therefore, the circuit neither requires laser zapping of fuse elements at the pitch of the column line, nor does it suffer from delays caused by the logical deselection circuitry. A better understanding of the nature and advantages of the redundancy circuit of the present invention may be had by referring to the detailed description and the diagrams below. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit schematic of a section of a dynamic random access memory circuit showing column redundancy according to the present invention as claimed in claim 1; Figure 2 shows a second embodiment for row redundancy in static random access memory circuits according to the present invention as claimed in claim 8. DESCRIPTION OF SPECIFIC EMBODIMENTS The redundancy scheme of the present invention can be employed in both static and dynamic random access memory circuits that use redundant rows and/or columns. Figure 1 is an exemplary circuit schematic of a section of a dynamic random access memory (DRAM) showing a column redundancy scheme according to the present invention. Each of a plurality of column lines 100 in a main memory array include BIT and BIT lines that are precharged to a predetermined voltage. BIT and BIT connect to a plurality of memory cells (not shown). Once a memory cell is accessed, a voltage differential develops between BIT and BIT in response to the contents of the accessed memory cell. A sense amplifier 104 connects to each column line 100 and detects the voltage differential across BIT and BIT . The sense amplifier 104 amplifies the differential voltage to develop full complementary logic levels at BIT and BIT . The source/drain terminals of a pair of select transistor 108 and 110 connect the BIT and BIT lines in each column 100 to a pair of complementary input/output (I/O) lines, respectively. A global column decode line 106 connects to the gate terminals of select transistors 108 and 110 in each column 100, such that when asserted a selected BIT and BIT connect to I/O and I/O lines. I/O and I/O are connected to the positive supply via PMOS transistors 112 and 114, respectively. The length and width of transistors 112 and 114 are selected to obtain an effective source to drain resistance of, for example, 400 ohms. During memory read cycles, the gate terminals of PMOS transistors 112 and 114 are at the negative power supply voltage VSS. I/O and I/O connect to differential inputs of a differential I/O sense amplifier 120 through a pair of resistors 116 and 118, respectively. When a global column decoder is asserted, a pair of bit lines connects to the I/O lines, and a voltage differential develops across the I/O lines. Assume that upcn accessing a memory cell in column 100i, BIT i and BIT i move to the positive supply VDD and the negative supply VSS, respectively. With global column decode line 106i at VDD, NMOS select transistor 110 will have a large gate to source voltage. Select transistor 110 thus turns ON and its conductive channel connects I/O to BIT 1 . Current starts to flow from VDD, through PMOS transistor 114 and select transistor 110, and to VSS through sense amplifier 104i. The amount of this current is fixed and limited by the saturation current of select transistor 110. Assuming a saturation current of 1mA and an effective resistance value of, for example, 400 ohms for PMOS transistor 114, the voltage at I/O drops from VDD to VDD-0.4v. The voltage at I/O remains unchanged at VDD. If the redundant column decode is not selected, there are no voltage drops across resistors 116 and 118 since the inputs of I/O sense amplifier 120 draw zero current. Thus, a voltage differential of 0.4 develops at the inputs of I/O sense amplifier 120. With 0.4 volts lower voltage at the negative input of I/O sense amplifier 120 as compared to its positive input, the output of I/O sense amplifier 120 will be high, signaling a logical "1." Now, assuming column 100i is a defective column, redundant column decoders are programmed to select a redundant column 102 when column 100i is addressed. Thus, when global column decode line 106i is asserted, redundant column decode 122 is also asserted. Redundant select transistors 124 and 126 connect BIT and BIT lines of redundant column 102 to I/O and I/O , respectively. The connection is similar to the main column lines except that redundant select transistors connect the redundant BIT and BIT lines to the I/O lines at the other side of resistors 116 and 118 (i.e., directly at the inputs to differential I/O sense amplifier 120). That is, while all main column lines 100 connect to I/O lines at nodes 128 and 130, redundant column lines 102 connect to I/O lines at nodes 132 and 134. Assume that the correct data in the accessed redundant memory cell is opposite in polarity to the data accessed in the memory cell in column 100i. When column 100i is selected, in addition to the 1mA current flowing through PMOS transistor 114 from defective column 100i, there will be a 1mA current flowing from VDD, through PMOS transistor 112 and resistor 116, through redundant column select transistor 124, and into VSS via redundant sense amplifier 136. If the value of the resistance for resistor 116 is also 400 ohms, then the lmA through transistor 124 causes a voltage drop of 0.4v across 400 ohm resistor 116 and a second 0.4v drop across 400 ohm PMOS transistor 112. Thus, the voltage at node 132 would equal VDD-0.8 volts. As a result, the voltage at the positive input of differential I/O sense amplifier 120 will be 0.4 volts less than the voltage at its negative input. Data out, therefore, signals a logical "0" instead of a faulty logical "1." Thus, the contents of redundant column 102 override the contents of defective column 100i, eliminating the need to disconnect or deselect defective column 100i. The delay caused by the addition of resistors 116 and 118 is negligible since the amount of parasitic capacitance at nodes 132 and 134 is minimal. Given a typical value of, for example, 0.05pF for the amount of parasitic capacitance at nodes 132 and 134, the delay caused by the RC time constant of resistor 116 or 118 driving node 132 or 134 would be approximately 400Ωx0.05pF=0.02ns. A very similar approach to the above embodiment precharges the I/O lines to VDD by turning PMOS transistors 112 and 114 on between cycles, and then turning them off at the beginning of the read cycle. PMOS transistors 112 and 114 are turned off at substantially the same time as when select transistors 108 and 110 are turned on. The basic principals of operation are the same, except unlike the above embodiment where the voltage on the I/O lines exponentially decays to a minimum of VDD-0.4 volts, by disconnecting the I/O lines from VDD, the circuit of this embodiment would allow the voltage on the I/O lines to ramp all the way down to VSS if enough time were allowed. But the select transistors 108, 110, 124 and 126 are deselected long before this occurs. In both embodiments, however, the current through resistors 116 or 118 cause a predominating voltage drop across the I/O lines when a redundant element is selected. Thus, the redundancy circuit of the present invention does not disturb the operation of the defective element, and allows the defective element to generate bad data. By adding a pair of small resistors as shown in Figure 1, however, the data from the redundant element simply overrides the bad data. This circuit therefore eliminates the need for fuses on the pitch of the column, or additional circuitry for logical deselection. An alternative embodiment of the present invention based on the same principal increases the size of redundant select transistors 124 and 126, and eliminates the need for resistors 116 and 118. Larger redundant select transistors increase the amount of saturation current flowing through transistors 124 or 126 compared to the saturation current of normal select transistors 108 and 110. Thus, when a redundant column 102 is selected, it causes more current to flow through one of the PMOS transistors 112 or 114 than that caused by the (defective) normal column. This in turn causes a larger voltage drop across it's PMOS transistor 112 or 114 than that caused by the normal column. When a redundant column is selected, the larger voltage drop simply overrides the smaller voltage drop on the I/O lines due to the bad data from the defective column. Depending on the stability requirements of redundant sense amplifier 136, this approach may require increasing the transistor sizes in redundant sense amplifier 136 as well. Another embodiment of the present invention based on the same principal can be employed for row redundancy. Equivalents to these techniques can be applied to static random access memory (SRAM) circuits. In a first embodiment, dominant redundant rows can be obtained by including a pair of resistors on BIT and BIT lines with SRAM redundant rows connecting to the other side of the resistors. Referring to Figure 2, there is shown a memory cell 400 and a redundant memory cell 402. The two memory cells are constructed similarly except that main memory cells connect to BIT and BIT at nodes 418 and 420 while redundant memory cells connect to BIT and BIT at nodes 422 and 424, on the other side of resistors 408 and 410. The operation of this embodiment is similar to the column redundancy circuit shown in Figure 1. When a defective row 424 is selected, a corresponding redundant row 426 is also selected. One memory cell from each row (400 and 402) connects to a selected pair of BIT and BIT lines. Similar to the column redundancy circuit described in connection with Figure 1, current flows through resistor 408 or 410 only when redundant memory cell 402 is selected. This generates a larger voltage drop which overrides the impact of the defective memory cell on BIT and BIT . A differential sense amplifier 416 connecting to nodes 422 and 424, thus responds to the contents of redundant memory cell 402. This circuit eliminates the need for disabling the defective row and allows the correct output data to predominate over the bad data contained in a defective row. In conclusion, the present invention provides a redundancy scheme for memory circuits that eliminates the need for physical disconnection or logical deselection of defective elements. Defective elements are allowed to operate and generate bad data. The redundancy circuit of the invention provides a mechanism for the redundant element to override the impact of the defective element. Several different means have been described for providing a dominant redundant element in connection with integrated circuit memories. While the above is a complete description of specific embodiments of the present invention, various modifications, variations and alternatives may be employed. The scope of this invention, therefore, should not be limited to the embodiments described, and should instead be defined by the following claims.

Claims: A memory circuit including a plurality of main memory cells arranged in an array of main row lines and main column lines (100) and a plurality of redundant memory cells arranged in an array of redundant column lines (102), characterized by: a main column line (100) coupled to a first segment (128) of an I/O data line (I/O); a redundant column line (102) coupled to a second segment (132) of the data line (I/O); a data sense amplifier (120) coupled to the second segment of the data line (I/O); means coupling the first segment to the second segment of the I/O data line (I/O) for generating on the I/O data line (I/O) a redundant signal from a redundant column line (102) that is stronger than a signal from a main column line (100) when a redundant column line (102) is selected, wherein the means for generating is located outside the array of main memory cells and the array of redundant memory cells, and wherein, the stronger redundant signal overrides the defective signal, eliminating the need for disabling the defective memory element. The memory circuit of claim 1 wherein the means for generating is a resistive element (116) coupling the first segment (128) of the I/O data line (I/O) to the second segment (132) of the data line, where the main memory cells couple to the first segment (128) and redundant memory cells couple to the second segment (132) and to the data sense amplifier (120). The memory circuit of claim 2 further comprising a load element (112) coupling the first segment (128) of the I/O data line (I/O) to a reference voltage. The memory circuit of claim 2 wherein the memory circuit is a dynamic random access memory, and wherein the main column line (100) includes a complementary pair of bit lines, and the I/O data line includes a complementary pair of I/0 lines whose respective first segments (128, 130) respectively couple to the complementary pair of bit lines through a respective pair of column select transistors (108, 110), and wherein, the redundant column line (102) includes a complementary pair of redundant bit lines respectively coupled to second segments (132, 134) of the complementary pair of I/O lines via a respective pair of redundant column select transistors (124,126). The memory circuit of claim 4 further comprising a second load element (114) coupling the first segment (130) of the complement I/O line to a reference voltage. The memory circuit of claim 1 wherein the means for generating is a redundant column select transistor (124) coupling a redundant column to the second segment (132) of the I/O data line (I/O) that is larger in size than a main column select transistor (108) coupling a main column line (100) to the first segment (128) of the data line (I/O). the memory circuit of claim 6 further comprising a main column sense amplifier (104) coupled to a main column line (100) and a redundant column sense amplifier (136). A memory circuit including a plurality of main memory cells (400) coupled to a plurality of main row lines (424) and a plurality of redundant memory cells (402) coupled to a plurality of redundant row lines (426), the memory circuit being characterized in comprising: a main row line coupled to a first segment (418) of a bit line (BIT); a redundant row line (426) coupled to a second segment (422) of the bit line (BIT); a sense amplifier (416) coupled to the second segment of said bit line (BIT); and a resistive element (408) coupling the first segment (418) to the second segment (422) of the bit line (BIT), wherein, the resistive element causes a redundant signal from a redundant row line (426) to be stronger than a signal from a main row line (424) when a redundant row line is selected simultaneously with said main row line (424).

Inventors: PROEBSTING ROBERT J, PROEBSTING, ROBERT J.
Applicants: PROEBSTING ROBERT J, PROEBSTING, ROBERT J.
Application year: 1995
Main classification: G06F11
IPC codes: G11C11, G11C29, G11C7