Data transfer device and method for reducing electrical transitions

Abstract: A data transfer device connected to a bus and a control signal line, includes: a judgment circuit for judging whether or not a state change of the bus, which occurs in a case where the data is manipulated to be output to the bus, is smaller than the state change of the bus, which occurs in a case where data is output to the bus without manipulating the data; a first manipulation circuit for manipulating the data in accordance with the result of judgment; a first output circuit for selectively outputting one set of the data and the data manipulated by the first manipulation circuit to the bus in accordance with the result of judgment; and a second output circuit for outputting a control signal indicating the result of judgment to the control signal line.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates to a data transfer device and a data transfer method for transferring data with low power consumption according to the preamble of claims 1, 11 and 14. Such device and method are known from the document EP-A-0 444 774. 2. Description of the Related Art: Dynamic power consumption (P) of a data transfer line is generally expressed by the expression: P = fCV 2 where f is the number of times of charge and discharge, C is a load capacitance, and V is a voltage applied to the load capacitance. Bus structures are adopted as data transfer lines in many integrated circuits for processing data for simplification of internal structures. However, since the bus is long and a number of resources are connected to the bus, the load capacitance of the bus is large in many cases. This results in an increase in power consumption. Japanese Laid-Open Patent Publication No. 4-128914 discloses a data transfer device for reducing the load capacitance of an internal bus. In the data transfer device, the internal bus is divided into two parts: a main data bus and an input/output bus. The main data bus and the input/output data bus are connected to each other via a bidirectional buffer only when data is output to the exterior of the integrated circuit. However, the external bus has a remarkably larger load capacitance than that of the internal bus. This is because while the internal bus of the integrated circuit has a line width of a micrometer order and a line length of a millimeter order, the external bus which is connected to an terminal of the integrated circuit has a line width of a millimeter order and a line length of a centimeter order. Therefore, in kinds of integrated circuits which should transfer data to the exterior of the integrated circuits, a power, which is consumed at the terminal, increases. As described above, the integrated circuit suffers a problem that remarkable reduction in the consumption power cannot be expected only by reducing the load capacitance of the internal bus. SUMMARY OF THE INVENTION The data transfer device of this invention connected to a bus and a control signal line, includes: judgment means for judging whether or not a state change of the bus, which occurs in a case where the data is manipulated to be output to the bus, is smaller than the state change of the bus, which occurs in a case where data is output to the bus without manipulating the data; first manipulation means for manipulating the data in accordance with the result of judgment; first output means for selectively outputting one set of the data and the data manipulated by the first manipulation means to the bus in accordance with the result of judgment; and second output means for outputting a control signal indicating the result of judgment to the control signal line, wherein the first manipulation means executes bit order transposition. In one embodiment of the invention, the judgment means further includes: first holding means for holding a preceding result of judgment; second holding means for holding the preceding data upon receiving current data; and determination means for determining whether the current data is to be manipulated or not in accordance with the preceding result of judgment, the preceding data and the current data. In another embodiment of the invention, the determination means further comprises: disagreeing number detection means for outputting the number of bits disagreeing between the preceding data and the current data; and means for outputting a signal indicating whether the current data is to be manipulated or not in accordance with the preceding result of judgment and the output of the disagreeing number detection means. In still another embodiment of the invention, the determination means further includes: pattern detection means for outputting the number of patterns agreeing with a relationship between the current data and the preceding data, out of a predetermined number of patterns which are previously prepared in accordance with the preceding result of judgment; and means for outputting a signal indicating whether the current data is to be manipulated or not in accordance with the output of the pattern detection means. In still another embodiment of the invention, the judgment means further includes determination means for determining whether the current data is to be manipulated or not in accordance with a current state of the bus and the current data. In still another embodiment of the invention, the determination means further includes: disagreeing number detection means for outputting the number of bits disagreeing between the current state of the bus and the current data; and means for outputting a signal indicating whether the current data is to be manipulated or not in accordance with the output of the disagreeing number detection means. In still another embodiment of the invention, the determination means further includes: pattern detection means for outputting the number of patterns agreeing with a relationship between the current state of the bus and the current data, out of the predetermined number of patterns which are previously prepared; and means for outputting a signal indicating whether the current data is to be manipulated or not in accordance with the output of the pattern detection means. In still another embodiment of the invention, the data is part of data supplied to the data transfer device via an entire bus, and the bit width of the bus is smaller than that of the entire bus. In still another embodiment of the invention, a data transfer device further includes second manipulation means for receiving data output from the first output means via the bus and the control signal indicating the result of judgment output from the second output means via the control signal line, and for manipulating the data in accordance with the control signal. Alternatively, the data transfer device includes; a transmission section for transmitting data and a control signal; a bus connected to the transmission section, for carrying the date; a control signal line connected to the transmission section, for carrying the control signal; and a receiving section connected to the bus and the control signal line, for receiving the data via the bus and the control signal via the control signal line, wherein the transmission section includes: judgment means for judging whether or not a state change in the bus, which occurs in a case where the data is manipulated to be output to the bus, is smaller than a state change in the bus, which occurs in a case where the data is output to the bus without manipulating the data; first manipulation means for manipulating the data in accordance with the result of judgment; first output means for selectively outputting one set of the data and data manipulated by the first manipulation means, in accordance with the result of judgment; and second output means for cutputting a control signal indicating the result of judgment to the control signal line, and wherein the receiving section includes: second manipulation means for receiving data output from the first output means via the bus and the control signal indicating the result of judgment output from the second output means via the control signal line, and for manipulating the data in accordance with the control signal, wherein the first manipulation means executes bit order transposition and the second manipulation includes bit order transposition. In one embodiment of the invention, the judgment means of the transmission section further includes: first holding means for holding a preceding result of judgment; second holding means for holding the preceding data upon receiving current data; and determination means for determining whether the current data is to be manipulated or not in accordance with the preceding result of judgment, the preceding data and the current data. In another embodiment of the invention, the judgment means of the transmission section further includes determination means for determining whether current data is to be manipulated or not in accordance with a current state of the bus and the current data. In another aspect of the present invention, a data transfer method includes the steps of: judging whether or not a state change in the bus, which occurs in a case where the data is manipulated to be output to the bus, is smaller than a state change in the bus, which occurs in a case where data is output to the bus without manipulating the data; performing a first manipulation of the data in accordance with the result of judgment; and transferring the manipulated data in accordance with the result of judgement, wherein the first manipulation includes bit order transposition. In another embodiment of the invention, the data transfer method further includes a step of reproducing the data by performing a second manipulation of the data in accordance with the result of judgment, the second manipulation being opposite to the first manipulation. Thus, the invention described herein makes possible the advantages of (1) providing a data transfer device for transferring data with low consumption power and (2) providing a data transfer method for transferring data with low power consumption. These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagram illustrating the background art of the present invention. Figure 2 is a flow-chart showing a procedure for a data transfer method. Figure 3 is a diagram showing a configuration for a data transfer device according to Example 1. Figure 4 shows the principle of reducing the power consumption by transposing a bit order of data. Figure 5 is a diagram showing a configuration for a data transfer device according to Example 2 of the present invention. Figure 6 shows the logic defining the operation of a judgment circuit 1506 in the data transfer device of Example 2. Figure 7 is a diagram showing a configuration for a pattern detecting circuit 1505 and the judgment circuit 1506 in the data transfer device of Example 2. Figure 8 is a diagram showing a configuration for a bit order transposing circuit 1508 in the data transfer device of Example 2. Figure 9 shows an example of the operation of the data transfer device of Example 2 in a time series. Figure 10 is a diagram showing a configuration for a data transfer device according to Example 2 of the present invention. Figure 11 is a diagram showing a pattern detecting circuit 2005 in the data transfer device of Example 5. DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the background art of the present invention is described with reference to Figure 1 . A unit 801 and a unit 802 are connected to each other through a wiring 803 . It is assumed that data, which is composed of a plurality of bits, is transferred from the unit 801 to the unit 802 via the wiring 803 . Since the wiring 803 has a load capacitance, charge and discharge occur due to such data transfer, resulting in consumption of power. For example, when b'10101010 (hereinafter, b' represents a binary notation) is transferred from the unit 801 to the unit 802 through the wiring 803, followed by transfer of b'01010101 from the unit 801 to the unit 802 through the wiring 803, the power consumption of the wiring 803 becomes maximum. This is because the charge and discharge occur in all of the bits of the wiring 803 due to inversion of all bits of the transfer data. The present invention provides a data transfer device and a data transfer method, for transferring data obtained by manipulating the data b' 01010101 and information indicating that true data is data obtained by manipulating the data b'01010101, instead of transferring the data b'01010101. For example, the data transfer device and the data transfer method transfer, instead of the data b' 01010101, data b' 10101010 obtained by inverting the data b' 01010101 and information of 1 bit indicating that true data is data obtained by inverting the bits of this data. With this operation, the power consumption of the wiring 803 becomes minimum. It is for this reason that the state of each bit of the wiring 803 does not change before and after the transfer of data. This data processing is not limited to bit inversion. In the present specification, "manipulation of data" includes transposition of bit order, and includes any manipulations as long as the state change of the wiring 803 is reduced by the manipulation. The wiring 803 may be either an internal bus or an external bus. As described above, however, the external bus has a remarkably larger load capacitance than that of the internal bus. Therefore, the present invention is particularly effective in the case where the wiring 803 is the external bus. When the unit 801 and the unit 802 are included in one integrated circuit, the wiring 803 is referred to as an internal bus. When the unit 801 is included in one integrated circuit and the unit 802 is included in another integrated circuit, the wiring 803 is referred to as an external bus. Figure 2 shows a procedure of data transfer according to the prior art. At Step S1 , it is judged whether or not a state change (SC1) of the bus, which occurs in the case where data is output to the bus without manipulating the data, is smaller than a state change (SC2) of the bus, which occurs in the case where manipulated data is output to the bus. If the state change (SC2) of the bus is judged to be smaller than the state change (SC1) of the bus, the data is manipulated (Step S2 ), the manipulated data is output to the bus (Step S3 ), and information (for example, b'l) indicating the result of judgment at Step S1 is output to a control signal line (Step S4 ). If the state change (SC2) of the bus is judged to be equal to or larger than the state change (SC1) of the bus, the data is output to the bus without being manipulated (step S3 ), and information (for example, b'0) indicating the result of judgment at Step S1 is output to the control signal line (Step S4 ). The order of Steps S3 and S4 may be reversed. Example 1 Figure 3 shows a configuration for a prior art example of a data transfer device similar to the present invention. The data transfer device includes integrated circuits 101 and 113. The integrated circuit 101 is connected to an external bus 119 via a terminal 111 , and is further connected to a signal line 120 via a terminal 112 . The integrated circuit 113 is connected to the external bus 119 via a terminal 114 , and is further connected to a signal line 120 via a terminal 115 . The bus 112 is composed of, for example, 8 bits. The signal line 120 is composed of, for example, 1 bit. The integrated circuit 101 includes an internal bus 102 , an output latch 103 , a judgment section 10 , a logic inversion circuit 108 , terminal driving circuits 109 and 110 , and a data processing circuit 201 . The internal bus 102 , which is provided in the integrated circuit 101 , is for transferring data. The output latch 103 is connected to the internal bus 102 and temporarily holds data to be output to the exterior of the integrated circuit 101 . The output latch 103 is composed of, for example, 8 bits. For example, data is given to the output latch 103 from the data processing circuit 201 via the internal bus 102 . The judgment section 10 judges whether or not the state change of the external bus 119 , which occurs in the case where data, whose logic level is inverted, is output to the external bus 119 , is smaller than that which occurs in the case where data is output to the external bus 119 without inverting the logic level of the data, thereby outputting a judgment signal 107 indicating the result of judgment. The judgment section 10 has a temporery latch 104 , a disagreeing number detection circuit 105 and a judgment circuit 106 . Each time new data is written to the output latch 103 , the temporary latch 104 latches the data which is latched in the output latch 103 until the new data is written. The temporary latch 104 is composed of, for example, 8 bits. The disagreeing number detection circuit 105 compares an output of the output latch 103 with an output of the temporary latch 104 for each bit, and outputs the number of disagreeing bits between the output of the output latch 103 and the output of the temporary latch 104 . The judgment circuit 106 outputs a judgment signal 107 based on an output of the disagreeing number detection circuit 105 and a preceding self-output. The operation of the judgment circuit 106 will be described below. The logic inversion circuit 108 manipulates the output of the output latch 103 in accordance with the judgment signal 107 output from the judgment circuit 106 . In the case where the judgment signal 107 is at a logic 1 , the logic inversion circuit 108 inverts the logic level of the output of the output latch 103 . In the case where the judgment signal 107 is at a logic 0, the logic inversion circuit 108 allows the output of the output latch 103 to pass through without inverting the output. The terminal driving circuit 109 drives the terminal 111 in order to output the output of the logic inversion circuit 108 to the exterior of the integrated circuit 101 . The terminal driving circuit 110 drives the terminal 112 in order to output the judgment signal 107 output from the judgment signal 106 to the exterior of the integrated circuit 101 . The integrated circuit 113 has the logic inversion circuit 116 , the internal bus 117 and a data processing circuit 202 . The logic inversion circuit 116 receives an 8-bit signal via the terminal 114, and manipulates the 8-bit signal in accordance with the logic level of the terminal 115 . In the case where the logic level of the terminal 115 is 1, the logic inversion circuit 116 inverts the logic level of the 8-bit signal. In the case where the logic level of the terminal 115 is 0, the logic inversion circuit 116 allows the 8-bit signal to pass through without inverting the signal. The internal bus 117 , which is provided in the integrated circuit 113 , is for transferring data. The output of the logic inversion circuit 116 is given to the data processing circuit 202 via the internal bus 117, for example. Example 2 Hereinafter, Example 2 of a data transfer device according to the present invention will be described. The data transfer device of Example 2 is an example of a data transfer device for reducing the power consumption by transposition of bit order. Figure 4 shows the principle of reducing the power consumption by transposition of bit order in the case where two sets of data are sequentially transferred. Assuming that 2-bit data (d0, d1) is transferred. In the case where bit order of the data (d0, d1) is not transposed, the data (d0, d1) is transferred. In the case where bit order of the data (d0, d1) is transposed, data (d1, d0) is transferred. For example, case g shows the case where the preceding transfer data is (0, 1) and the current transfer data is (1, 0). In case g , the number of state changes of bits in the case where the bit order is transposed, is smaller than that in the case where the bit order is not transposed. Therefore, the reduction effects in the power consumption can be obtained by transposition of bit order. Case j shows the case where the preceding transfer data is (1, 0) and the current transfer data is (0, 1). In case j , the number of state changes of bits in the case where the bit order is transposed, is smaller than that in the case where the bit order is not transposed. Therefore, the reduction effect in the power consumption can be obtained by transposition of bit order. Figure 5 shows a configuration of Example 2 of the data transfer device according to the present invention. The data transfer device of Example 2 is based on the above-mentioned principle of reducing the power consumption by transposition of bit order. In Figure 5, the same components as those shown in Figure 3 are denoted by the same reference numerals, and the description thereof is herein omitted. A judgment section 1500 judges whether or not the state change of the external bus 119 , which occurs in the case where 8-bit data (d6, d7, d4, d5, d2, d3, d0, d1) obtained by transposing the bit order every two adjacent bits is output to the external bus 119 , is smaller than the state change of the external bus 119 , which occurs in the case where 8-bit data (d7, d6, d5, d4, d3, d2, d1, d0) is output to the external bus 119 without transposing the bit order. Then, the judgment section 1500 outputs a judgment signal 1507 indicating the result of judgment. The-judgment section 1500 includes the temporary latch 104 , a pattern detecting circuit 1505 and a judgment circuit 1506. The pattern detecting circuit 1505 outputs the number of pairs of bits out of four pairs of bits (d7, d6), (d5, d4), (d3, d2) and (d1, d0), which corresponds to the case g or j shown in Figure 4, based on the preceding judgment signal 1507 , the output of the output latch 103 and the output of the temporary latch 104. The judgment circuit 1506 outputs the judgment signal 1507 , based on the output of the pattern detecting circuit 1505. The operation of the judgment circuit 1506 will be described below. A bit order transposing circuit 1508 manipulates the output of the output latch 103 in accordance with the judgment signal 1507 output from the judgment circuit 1506. In the case where the judgment signal 1507 is at a logic 1, the bit order transposing circuit 1508 transposes the bit order of the output of the output latch 103. As a result, data (d6, d7, d4, d5, d2, d3, d0, d1) is output. In the case where the judgment signal 1507 is at a logic 0, the bit order transposing circuit 1508 allows the output of the output latch 103 to pass through without transposing the bit order. As a result, data (d7, d6, d5, d4, d3, d2, d1, d0) is output. The terminal driving circuit 109 drives the terminal 111 in order to output the output of the bit order transposing circuit 1508 to the exterior of the integrated circuit 101 . The terminal driving circuit 110 drives the terminal 112 in order to output the judgment signal 1507 output from the judgment circuit 1506 , to the exterior of the integrated circuit 101. The terminal 111 is connected to the terminal 114 via the external bus 119 . The terminal 112 is connected to the terminal 115 via the signal line 120 . A bit order transposing circuit 1516 receives 8-bit data via the terminal 114 , and manipulates the 8-bit data in accordance with the logic level of the terminal 115. In the case where the logic level of the terminal 115 is 1, the bit order transposing circuit 1516 transposes the bit order of the 8-bit data. In the case where a logic level of the terminal 115 is 0, the bit order transposing circuit 1516 allows the 8-bit data to pass through without transposing the bit order. Figure 6 shows the logic defining the operation of the judgment circuit 1506 . As defined in Figure 6 , the operation of the judgment circuit 1506 is defined, depending on cases A and B . Case A shows the operation of the judgment circuit 1506 in the case where the pattern detecting circuit 1505 outputs either 0 or 1. In this case, the judgment circuit 1506 outputs the judgment signal 1507 of 0. The case B shows the operation of the judgment circuit 1506 in the case where the pattern detecting circuit 1505 outputs either 2 or 3. In this case, the judgment circuit 1506 outputs the judgment signal 1507 of 1. Figure 7 shows a circuit configuration of the pattern detecting circuit 1505 and the judgment circuit 1506 . The pattern detecting circuit 1505 is realized by, for example, a flip-flop 1701 , logic gates 1702 through 1709 and 1710 through 1713 . The judgment circuit 1506 is realized by, for example, a programmable logic array 1714. The flip-flop 1701 delays the judgment signal 1507 output from the programmable logic array 1714. The logic gates 1702 through 1709 determine whether the bit order of the output of the temporary latch 104 should be transposed or not, depending on the output of the flip-flop 1701 . In the case where the output of the flip-flop 1701 is a logic 1, the logic gates 1702 through 1709 transpose the bit order of the output of the temporary latch 104 . As a result, data (d6, d7, d4, d5, d2, d3, d0, d1) is output from the logic gates 1702 through 1709. In the case where the output of the flip-flop 1701 is a logic 0, the logic gates 1702 through 1709 allow the output of the temporary latch 104 to pass through without transposing the bit order. As a result, data (d7, d6, d5, d4, d3, d2, d1, d0) is output from the logic gates 1702 through 1709. The logic gates 1710 through 1713 compare the output of the logic gates 1702 through 1709 with the output of the output latch 103 to output the number of pairs of bits out of four pairs of bits (d7, d6), (d5, d4), (d3, d2) and (d1, d0), which corresponds to the case g or j shown in Figure 4 . For example, the number of pairs of bits corresponding to the case g or j is represented by the number of output signal lines having a logic level of 1, out of four output signal lines from the logic gates 1710 through 1713 . The programmable logic array 1714 outputs the judgment signal 1507 , based on the output of the logic gates 1710 through 1713. The logic shown in Figure 6 is realized by the programmable logic array 1714 . Figure 8 shows an example of a circuit configuration of the bit order transposing circuit 1508 . The bit order transposing circuit 1508 is realized by, for example, logic gates 1801 through 1808 . The logic gates 1801 through 1808 determine whether the bit order of input data (d7, d6, d5, d4, d3, d2, d1, d0) should be transposed or not, based on the judgment signal 1507 . In the case where the judgment signal 1507 is at a logic 1, the logic gates 1801 through 1808 transpose the bit order of the input data. As a result, data (d6, d7, d4, d5, d2, d3, d0, d1) is output from the logic gates 1801 through 1808. In the case where the judgment signal 1507 is at a logic 0, the logic gates 1801 through 1808 allow the input data to pass through without transposing the bit order. As a result, data (d7, d6, d5, d4, d3, d2, d1, d0) is output from the logic gates 1801 through 1808. The circuit configuration of the bit order transposing circuit 1516 is the same as that shown in Figure 8 . Figure 9 shows examples of the operation of the data transfer device according to Example 2 in a time series. Hereinafter, how the data transfer device operates at times 1, 2, 3, 4 and 5 will be respectively described. Time 1 ) Assuming that b'10101010 is stored in the output latch 103 and the judgment signal 1507 is 0 at time 1 . The output of the output latch 103 passes through the bit order transposing circuit 1508 without transposing the bit order. As a result, the terminal driving circuit 109 drives the external bus 119 with the value of b'10101010. The judgment signal 1507 of 0 is transferred to the interior of the integrated circuit 113 via the terminal driving circuit 110 and the terminals 112 and 115 . Since the bit order transposing circuit 1516 does not perform a transposition operation of bit order, the signal on the external bus 119 passes through the bit order transposing circuit 1516 via the terminal 114 , and is transferred to the internal bus 117 . In this way, b'10101010, which is stored in the output latch 103 , is output to the internal bus 117. The judgment signal 1507 of 0 is held in the flip-flop 1701 . Time 2 ) Data b'01010100 is written to the output latch 103 via the internal bus 102 at time 2 . Simultaneously with the writing to the output latch 103, b'10101010, which is stored in the output latch 103 until then, is stored in the temporary latch 104. Since the output of the flip-flop 1701 is 0, the logic gates 1702 through 1709 allow the output of the temporary latch 104 to pass through. The output b'10101010 of the logic gates 1702 to 1709 and the output b'01010100 of the output latch 103 are input to the logic gates 1710 through 1713 . As a result, logic levels of three output signal lines out of four output signal lines from the logic gates 1710 through 1713 become 1. The judgment signal 1506 judges that the current state corresponds to the case B of Figure 6 , and outputs the judgment signal 1507 of 1. The bit order of the output of the output latch 103 is transposed by the bit order transposing circuit 1508 . As a result, the terminal driving circuit 109 drives the external bus 119 with the value of b'10101000. Since the state of the external bus 119 at time 1 is b'10101010, the state of the external bus 119 is changed by 1 bit due to the current output of b'10101000. As a result, the power corresponding to the state change of 1 bit is consumed. The judgment signal 1507 of 1 is transferred to the interior of the integrated circuit 113 via the terminal driving circuit 110 and the terminals 112 and 115 . Since the bit order transposing circuit 1516 performs a bit order transposition operation, the bit order of the signal on the external bus 119 is transposed by the bit order transposing circuit 1516 via the terminal 114, and is transferred to the internal bus 117 . In this way, b'01010100, which is stored in the output latch 103 , is output to the internal bus 117 . The judgment signal 1507 of 1 is held in the flip-flop 1701 . Time 3 ) Data b'01010111 is written to the output latch 103 via the internal bus 102 at time 3 . Simultaneously with the writing to the output latch 103, b'01010100, which is stored in the output latch 103 until then, is stored in the temporary latch 104. Since the output of the flip-flop 1701 is 1, the logic gates 1702 through 1709 transpose the bit order of the output of the temporary latch 104. As a result, b'10101000 is output from the logic gates 1702 through 1709. Herein, b'10101000 is the same data as that output to the external bus at time 2 . The output b'10101000 of the logic gates 1702 through 1709 and the output b'01010111 of the output latch 103 are input to the logic gates 1710 through 1713. As a result, logic levels of three output signal lines out of four output signal lines from the logic gates 1710 through 1713 become 1. The judgment circuit 1506 judges that the current state corresponds to the case B of Figure 6 , and outputs the judgment signal 1507 of 1. The bit order of the output of the output latch 103 is transposed by the bit order transposing circuit 1508. The terminal driving circuit 109 drives the external bus 119 with the value of b'10101011. Since the state of the external bus 119 is b'10101000 at time 2 , the state of the external bus 119 is changed by 2 bits due to this output of b'10101011. As a result, the power corresponding to the state change of 2 bits is consumed. The judgment signal 1507 of 1 is transferred to the interior of the integrated circuit 113 via the terminal driving circuit 110 and the terminals 112 and 115 . Since the bit order transposing circuit 1516 performs a bit order transposing operation, the bit order of the signal on the external bus 119 is transposed by the bit order transposing circuit 1516 via the terminal 114, and is transferred to the internal bus 117. In this way, b'01010111, which is stored in the output latch 103 , is output to the internal bus 117. The judgment signal 1507 of 1 is held in the flip-flop 1701 . Time 4 ) Data b'10101001 is written to the output latch 103 via the internal bus 102 at time 4 . Simultaneously with the writing to the output latch 103, b'01010111, which is stored in the output latch 103 until then, is stored in the temporary latch 104. Since an output of the flip-flop 1701 is 1, the logic gates 1702 through 1709 transpose the bit order of the output of the temporary latch 104. As a result, b'10101011 is output from the logic gates 1702 through 1709. Herein, b'10101011 is the same data as that output to the external bus at time 3 . The output b'10101011 of the logic gates 1702 through 1709 and the output b'10101001 of the output latch 103 are input to the logic gates 1710 through 1713. As a result, all logic levels of four output signal lines from the logic gates 1710 through 1713 become 0. The judgment circuit 1506 judges that the current state corresponds to the case A of Figure 6 , and outputs the judgment signal 1507 of 0. An output of the output latch 103 passes through the bit order transposing circuit 1508 . As a result, the terminal driving circuit 109 drives the external bus 119 with the value of b'10101001. Since the state of the external bus 119 at time 3 is b'10101011, the state of the external bus 119 is changed by 1 bit due to the current output of b'10101001. As a result, the power corresponding to the state change of 1 bit is consumed. The judgment signal 1507 of 0 is transferred to the interior of the integrated circuit 113 via the terminal driving circuit 110 and the terminals 112 and 115 . Since the bit order transposing circuit 1516 does not perform a bit order transposing operation, the signal on the external bus 119 passes through the bit order transposing circuit 1516 via the terminal 114 and is transmitted to the internal bus 117 . In this way, b'10101001, which is stored in the output latch 103 , is output to the internal bus 117 . The transposition of the bit order is not limited to adjacent bits. It is possible to transpose arbitrary bits. As described above, in the data transfer device of Example 2, the judgment circuit 1506 judges to which of cases A and B in Figure 6 the current state corresponds, and outputs the judgment signal 1507 indicating the result of judgment. The bit order transposing circuit 1508 manipulates the output of the output latch 103 in accordance with the logic level of the judgment signal 1507 . In the case where a logic level of the judgment signal 1507 is 1, the bit order of the output of the output latch 103 is transposed by the bit order transposing circuit 1508 . Then, the signal, whose bit order is transposed, is output to the external bus 119 . In the case where a logic level of the judgment signal 107 is 0, the signal is output to the external bus 119 without transposing the bit order of the output of the output latch 103 . In this way, it is possible to diminish the state change of the external bus 119 . As a result, the power consumed in the external bus 119 can be reduced. Example 3 Figure 10 shows a configuration of Example 3 of a data transfer device according to the present invention. In Figure 10, the same components as those shown in Figure 5 are denoted by the same reference numerals, and the description thereof is herein omitted. The configuration of the data transfer device of Example 3 is effective in the case where the state of the external bus 119 is maintained until the next data is written to the output latch 103. In Example 3, a pattern detection circuit 2005 and the judgement circuit 1506 function as a judgment section 2000. The judgment section 2000 judges whether or not the state change of the external bus 119 , which occurs in the case where data whose bit order is transposed is output to the external bus 119, is smaller than that which occurs in the case where data is output to the external bus 119 without transposing the bit order of the data. Then, the judgment section 2000 outputs judgment signal 1507 indicating the result of judgment. The pattern detecting circuit 2005 differs from the pattern detecting circuit 1505 shown in Figure 5 in that the pattern detecting circuit 2005 directly feedbacks the state of the external bus 119 to input the state, instead of inputting the output of the temporary latch 104. However, since the operation of the pattern detecting circuit 2005 is the same as that of the pattern detecting circuit 1505 shown in Figure 5 , the description thereof is herein omitted. Figure 11 shows an example of a circuit configuration of the pattern detecting circuit 2005. The pattern detecting circuit 2005 is realized by, for example, logic gates 2101 through 2104 . The logic gates 2101 through 2104 compare the output of the external bus 119 with the output of the output latch 103 , thereby outputting the number of pairs of bits out of four pairs of bits (d7, d6), (d5, d4), (d3, d2) and (d1, d0) shown in Figure 16 , which corresponds to the case g or j . For example, the number of pairs of bits, which corresponds to the case g or j , is represented by the number of output signal lines whose logic levels are 1, out of four output signal lines from the logic gates 2101 through 2104 . In the case where cyclic data is sequentially transferred as key scan, it is preferable that the data transfer devices of Examples 2 and 3 are used because the state change of the external bus 119 can be reduced by transposing the bit order of the transfer data. For example, a series of data such as b'10001000, b'01000100, b'00100010, and b'00010001 can be given as an example of cyclic data. Furthermore, some data transfer devices can be obtained by combining the data transfer device of Example 1 with the data transfer device of Example 2 or 3. The bit inversion operation and the bit order transposing operation may be performed at the same time so as to transfer data by either of the operations, in which the state change of the external bus 119 is smaller than that in the other operation. In this case, the signal line 120 is required to have not 1-bit width but 2-bit width because the signal line 120 should distinguishably designate the bit inversion operation and the bit order transposing operation. Alternatively, the bit inversion operation may be followed by the bit order transposing operation, or the bit order transposing operation may be followed by the bit inversion operation so as to transfer data by either of the operations, in which the state change of the external bus 119 is smaller than that in the other operation. Also in this case, the signal line 120 is required to have not 1-bit width but 2-bit width because the signal line 120 should distinguishably designate the bit inversion operation and the bit order transposing operation. Furthermore, if the integrated circuit 101 prepares a plurality of kinds of date compression methods and the integrated circuit 113 prepares a plurality of kinds of data expansion methods, the compressed data may be transferred via the external bus 119, and the kind of data compression method used for compressing the data may be transferred via the signal line 120 . The integrated circuit 113 receives the compressed data, and expands the data by using an expansion method corresponding to the compression method, thereby recovering the original data. In the case where the integrated circuit prepares 2 n kinds of data compression methods, the signal line 120 is required to have at least an n-bit width. According to the data transfer device and the data transfer method of the present invention, it is judged whether or not the state change of the bus, which occurs in the case where the data is manipulated to be output to the bus, is smaller than the state change of the bus, which occurs in the case where data is output to the bus without manipulating the data. The data is manipulated based on the result of judgment. Moreover, either the unmanipulated data or the manipulated data is selectively output to the bus. With this operation, it is possible to reduce the state change of the bus accompanied by data transfer. As a result, the power, which is consumed in the bus, is reduced.

Claims: A data transfer device (101, 113) connected to a bus (119) and a control signal line (120), comprising: judgement means (1500) for judging whether or not a state change of the bus, which occurs in a case where the data is manipulated to be output to the bus, is smaller than a state change of the bus, which occurs in a case where data is output to the bus without manipulating the data; first manipulation means (1508) for reversibly manipulating the data in accordance with the result of judgement; first output means (111) for selectively outputting one of the data and the data manipulated by the first manipulation means (1508) to the bus (119) in accordance with the result of judgement; and second output means (112) for outputting a control signal indicating the result of judgement to the control signal line (120), characterised in that the first manipulation means (1508) executes bit order transposition. A data transfer device according to claim 1, wherein the judgement means comprises: first holding means (410) for holding a preceding result of judgement; second holding means (104) for holding the preceding data upon receiving current data; and determination means (106) for determining whether the current data is to be manipulated or not in accordance with the preceding result of judgement, the preceding data and the current data. A data transfer device according to claim 2, wherein the determination means comprises: disagreeing number detection means (105) for outputting the number of bits disagreeing between the preceding data and the current data; and means for outputting (106) a signal indicating whether the current data is to be manipulated or not in accordance with the preceding result of judgement and an output of the disagreeing number detection means. A data transfer device according to claim 2, wherein the determination means comprises: pattern detection means (1505) for outputting the number of patterns agreeing with a relationship between the current data and the preceding data, out of a predetermined number of patterns which are previously prepared in accordance with the preceding result of judgement; and means for outputting (1506) a signal indicating whether the current data is to be manipulated or not in accordance with an output of the pattern detection means. A data transfer device according to claim 1, wherein the judgement means comprises determination means (506) for determining whether the current data is to be manipulated or not in accordance with a current state of the bus and the current data. A data transfer device according to claim 5, wherein the determination means comprises: disagreeing number detection means (505) for outputting the number of bits disagreeing between the current state of the bus and the current data; and means for outputting (506) a signal indicating whether the current data is to be manipulated or not in accordance with the output of the disagreeing number detection means. A data transfer device according to claim 5, wherein the determination means comprises: pattern detection means (2005) for outputting the number of patterns agreeing with a relationship between the current state of the bus and the current data, out of the predetermined number of patterns which are previously prepared; and means for outputting (1506) a signal indicating whether the current data is to be manipulated or not in accordance with the output of the pattern detection means. A data transfer device according to claim 1, wherein the data is part of data supplied to the data transfer device via an entire bus (1202), and a bit width of the bus (102) is smaller than that of the entire bus. A data transfer device according to claim 1, further includes second manipulation means (116) for receiving data output from the first output means (111) via the bus (119) and the control signal indicating the result of judgement output from the second output means (112) via the control signal line (120), and for reversibly manipulating the data in accordance with the control signal. A data transfer device according to claim 9, wherein the second manipulation means (1516) executes bit order transposition. A data transfer device according to claim 1 further comprising: a receiving section (113) connected to the bus and the control signal line, for receiving the data via the bus and the control signal via the control signal line, and wherein the receiving section (113) includes: second manipulation means (1516) for receiving data output from the first output means via the bus and the control signal indicating the result of judgement output from the second output means via the control signal line, and for reversibly manipulating the data in accordance with the control signal, characterised in that the second manipulation means (1516) executes bit order transposition. A data transfer device according to claim 11, wherein the judgement means of the transmission section includes: first holding means (410) for holding a preceding result of judgement; second holding means (104) for holding the preceding data upon receiving current data; and determination means (106) for determining whether the current data is to be manipulated or not in accordance with the preceding result of judgement, the preceding data and the current data. A data transfer device according to claim 11, wherein the judgement means of the transmission section (101) includes determination means (506) for determining whether current data is to be manipulated or not in accordance with a current state of the bus and the current data. A data transfer method comprising the steps of: judging whether or not a state change in a bus, which occurs in a case where the data is manipulated to be output to said bus, is smaller than a state change in a bus, which occurs in a case where data is output to the bus without manipulating the data; performing a first reversible manipulation of the data in accordance with the result of judgement; and transferring the manipulated data in accordance with the result of judgement together with a signal indicative of the result of the judgement on the bus, the method being characterised in that the step of performing a first manipulation includes bit order transposition. A data transfer method according to claim 14, further comprising a step of reproducing the data by performing a second reversible manipulation of the data in accordance with the result of judgement, the second manipulation being opposite to the first manipulation. A data transfer method according to claim 15, wherein the second manipulation includes bit order transposition.

Inventors: UEDA KATSUHIKO, UEDA, KATSUHIKO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1995
Main classification: G06F13
IPC codes: G06F13