Process for the manufacturing of integrated circuits comprising lateral low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells

Abstract: A process for the manufacturing of an integrated circuit comprising lateral DMOS-technology power devices and non-volatile memory cells provides for: forming respective laterally displaced isolated semiconductor regions (R1,R2,R6), electrically insulated from each other and from a common semiconductor substrate (1), inside which the devices will be formed; forming conductive insulated gate regions (33,34,37) for the lateral DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions (R1,R2,R6); inside the isolated semiconductor regions (R1,R2) for the lateral DMOS-technology power devices, forming deep body regions (25,26) aligned with edges of the insulated gate regions (33,34), and channel regions (29,30) extending under the insulated gate regions (33,34). The deep body regions (25,26) are formed by means of a first implantation of a first dopant in a direction substantially orthogonal to a top surface of the integrated circuit, performed with an energy and with a dopant dose such that the concentration of the first dopant has a peak located at a prescribed distance from the surface of the isolated semiconductor regions (R1,R2). The channel regions (29,30) are formed by means of a second implantation of a second dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that said channel regions (29,30) are formed directly after the implantation of the second dopant without performing a thermal diffusion at a high temperature of the second dopant.

Description: The present invention relates to a process for the manufacturing of integrated circuits comprising lateral low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells. In the field of integrated circuits there is a trend towards the integration in a same semiconductor chip of different kinds of devices, such as DMOS-technology power devices, bipolar power devices, low-voltage bipolar and CMOS devices. The known manufacturing processes of DMOS-technology power devices (vertical or lateral DMOS transistors, IGBTs) involve long thermal processes at high temperatures. In fact, the channel region of the DMOS structure is formed by means of the difference in the lateral diffusion of dopants. In order to obtain DMOS devices with threshold voltages in the range of 1-2V and with a breakdown voltage not limited by channel punchthrough, the temperature of the diffusion process must be higher than 1000 °C. On the contrary, in the field of VLSI circuits there is a trend towards a reduction of the thermal budgets of the diffusion processes: high temperature and/or long duration thermal processes are not suitable to achieve the desired reduction in the dimensions of the devices, and would increase the defectivity in the thinner oxide layers. This is particularly true for non-volatile memory devices, where oxide thicknesses lower than 80 Angstroms are typical. Consequently, the known manufacturing processes for DMOS-technology power devices, involving such a high thermal budget, are not compatible with current manufacturing processes used in the fabrication of VLSI circuits. The patent US 5,296,393 discloses a process for the simultaneous fabrication of different devices, for example of vertical and lateral annular DMOS transistor and EEPROM cells. The patent application JP 05036719 discloses a process for implanting impurities obliquely at a specified angle to the surface of a semiconductor substrate, forming low-concentration and middle-concentration impurity layers. In view of the state of the art described, it is an object of the present invention to provide a manufacturing process suitable for the fabrication of integrated circuits comprising lateral DMOS-technology power devices and non-volatile memory cells. According to the present invention, such object is achieved by means of a process for the manufacturing of an integrated circuit comprising lateral DMOS-technology power devices and non-volatile memory cells according to claim 1. In the manufacturing process according to the present invention long thermal diffusion processes at high temperatures are not required for the formation of the deep body regions and of the channel regions of the power devices. The process is therefore suitable to integrate in a single semiconductor chip DMOS-technology power devices and non-volatile memory cells. The process according to the invention also allow the integration, without additional steps, of MOSFETs and bipolar junction transistors, as well as of other kinds of devices. These and other features of the present invention will be made more evident by the following detailed description of two particular embodiments, described as non-Limiting examples with reference to the annexed drawings, wherein: Figures 1A-3A, 4, 5A, 6A are cross-sectional views showing initial manufacturing steps, common to both the embodiments of the process of the present invention, of a first group of integrated devices; Figures 1B-3B, 5B, 6B are cross-sectional views of said initial manufacturing steps of a second group of integrated devices; Figures 7A-9A and 7B-9B are cross-sectional views showing successive manufacturing steps of the first and second group of integrated devices, respectively, according to a first embodiment of the invention; Figures 10A, 11A and 10B, 11B are cross-sectional views showing alternative successive manufacturing steps of the first and second group of integrated devices, respectively, according to a second embodiment of the invention; Figures 12A and 12B are cross-sectional views showing a further manufacturing step for the first and second group of integrated devices, respectively, common to both the embodiments of the invention. Two alternative embodiments of a process according to the present invention will be hereafter described; the initial and final process steps are common to both the embodiments. In the following description there is described the manufacturing of a Lateral low-voltage Double-diffused MOS (DMOS) transistor, of a Lateral high-voltage DMOS transistor, of an EEPROM memory cell, of an NPN and a PNP bipolar junction transistors (BJTs) and of an N-channel and a P-channel MOSFETs. These, however, are not the only devices which can be integrated by means of the process of the invention: other devices, such as diodes, condensers, resistors, and so on can be integrated in a straightforward way in a same semiconductor chip. The manufacturing process of the present invention starts with a P type substrate 1. Over a top surface of the substrate 1 an oxide layer 2 ("pad oxide") is formed, and a silicon nitride Layer 3 (Si 3 N 4 ) is deposited over the oxide Layer 2. The silicon nitride Layer 3 and the oxide layer 2 are then maskedly etched and selectively removed from the surface of the substrate 1, to open windows 4. A heavy dose of an N type dopant, typically arsenic in a dose of 10 15 -10 16 atoms/cm 2 , is then implanted with an energy of about 120 keV into the substrate 1, through the windows 4; the dopant is then made to diffuse into the substrate 1 by means of a thermal process at 1100-1200 °C for about three hours, to form N+ regions 5 (Figs. 1A and 1B). Thick oxide areas 6 are then formed over the N+ regions 5, by means of the so-called "LOCOS" technique; the silicon nitride layer 3 is then completely removed from the oxide layer 2, and a P type dopant, typically boron, is implanted in a dose of the order of 10 13 atoms/cm 2 and with an energy of about 25 keV into the substrate 1 through the oxide layer 2; the greater thickness of the oxide areas 6 with respect to the oxide layer 2 prevents the P type dopant from penetrating in the N+ regions 5. The dopant is then made to diffuse into the substrate 1 by means of a thermal process at 600-700 °C for about one hour, to form P isolation regions 7 between the N+ regions 5 (Figs. 2A and 2B). The oxide layer 2 and the thick oxide areas 6 are then completely removed. A lightly doped N type (N-) layer 8, with resistivity of about 15 Ohms*cm and thickness of about 4-5 um, is then epitaxially grown over the P type substrate 1; during this step, the N+ regions 5 and the P isolation regions 7 partially diffuse laterally and vertically. After the growth of the N-layer 8, the N+ regions 5 and the P isolation regions 7 are buried under the N- layer 8 (Figs. 3A and 3B): the N+ regions 5 form so-called "buried Layers" and the P regions 7 form so-called "bottom isolation regions". An oxide layer 9 (pad oxide) is formed over a top surface of the N- layer 8, and a silicon nitride layer 10 is deposited over the oxide layer 9; the silicon nitride layer 10 and the oxide layer 9 are then maskedly etched and selectively removed from the surface of the N- Layer 8, to open windows 11. An N type dopant, for example phosphorous, is then implanted in a dose of about 10 12 -10 13 (preferably 8*10 12 ) atoms/cm 2 and with an energy of about 155 keV into the N- layer 8 through the windows 11, to form low-voltage N well regions 12 (Figs. 3A and 3B). The silicon nitride layer 10 is then selectively removed from an area of the oxide layer 9 under which a high-voltage lateral DMOS transistor (with breakdown voltage BV ≥ 40V)is to be formed, to open a further window 13; an N type dopant, for example phosphorous, is then implanted in a lower dose (preferably 10 12 atoms/cm 2 ) at an energy of about 155 keV into the N- layer 8 through the window 13 to form a high-voltage N well region 14 (Fig. 4). A heavy dose of an N type dopant is selectively implanted to form N+ sinker regions 15 (visible in Fig. 5B) used as collectors for the NPN BJT. The dopants are then made to diffuse by means of a thermal process at about 1100-1200 °C for about three hours. The remaining of the oxide layer 9 and of the nitride layer 10 is then removed. Thick oxide areas 16 are then formed by means of the LOCOS technique. A P type dopant, for example boron, is then selectively implanted in a dose of about 10 12 -10 13 atoms/cm 2 with an energy of about 25 keV into the N- layer 8, between the N+ buried regions 5, to form P well regions 17 over the P bottom isolation regions 7 (Figs. 5A and 5B); this implantantion step is also used to form P type well regions 80, 81 and 82 for the N-channel MOSFETs, the EEPROM memory cell and the PNP BJT, respectively; the thick oxide areas 16 acts as a mask for the implanted dopant. A thermal process at about 1100 °C for about two hours is then performed. During this step, the P well regions 17 diffuse downwardly and merge with the P bottom isolation regions 7; also, the low-voltage N well regions 12, the high-voltage N well region 14 and the N+ sinker region 15 diffuse downward in the N- layer 8. In this way, laterally displaced semiconductor regions R1-R6 electrically isolated from each other, by means of the P bottom isolation regions 7 and the P well regions 17, and from the substrate 1, by means of the N+ buried regions 5, can be formed (Figs. 5A and 5B). In regions R1 and R2 a high voltage lateral DMOS transistor and a low voltage lateral DMOS transistor will be respectively formed; in region R3 an N-channel and a P-channel MOSFETs will be formed; in regions R4 and R5 an NPN and a PNP BJTs will be respectively formed; and in region R6 an EEPROM cell will be formed. After this, the oxide layer made up of the oxide areas 9 and 16 is completely removed. Active areas are then defined on the top surface of the N-Layer 8: as known to anyone skilled in the art, this provides for selectively implanting a P type dopant, such as boron, in a dose of about 10 12 -10 13 atoms/cm 2 with an energy of about 120 keV to form top field isolation regions 83. Thick field oxide areas 19 are then selectively formed by means of the LOCOS technique. (Figs. 6A and 6B). Thin gate oxide areas 18, with a thickness of about 200 Angstroms, are then formed between the field oxide areas 19; also, a tunnel oxide area 84, about 80 Angstroms thick, is selectively formed over region R6 wherein the EEPROM memory cell must be formed (Figs. 6A and 6B). In region R6 wherein an EEPROM memory cell has to be formed, an N type dopant is implanted in the P well region 81 to form two N+ regions 22 and 23 (Fig. 6B): region 22 forms a control gate diffusion for the EEPROM memory cell; region 23 forms a tunnel region. A polysilicon layer 21, with thickness of about 2500 Angstrom, is then deposited over the whole surface (Figs. 6A and 6B). On the polysilicon layer 21, a silicide layer (e.g. tungsten silicide) can also be deposited, to enhanche the conductivity. The steps previously described are common to both the embodiments of the process of the present invention. According to a first embodiment of the present invention, a photoresist layer 24 is then formed over the polysilicon layer 21 (Figs. 7A and 7B). The photoresist layer 24 and the underlying polysilicon layer 21 and gate oxide 18 are then maskedly etched and selectively removed from the chip regions R1 and R2, wherein the high voltage lateral DMOS transistor and the low voltage lateral DMOS transistor must be formed, to open windows through which a P type dopant, such as boron, is then implanted to form P deep body regions 25 for the high voltage lateral DMOS transistor and deep body regions 26 for the low voltage lateral DMOS transistor (Figs. 7A and 78); the P deep body regions 25 and 26 thus obtained are substantially aligned with the edges of the windows in the photoresist, polysilicon and gate oxide layers 24, 21 and 18. The dopant is implanted orthogonally to the surface of the photoresist layer 24 in a dose of about 7*10 13 atoms/cm 2 and with an energy of 150-250 keV. Such a high energy is sufficient to locate the peak dopant concentration at a suitable distance from the surface of the N type wells 14 and 12; the presence of the photoresist layer 24 over the polysilicon Layer 21 prevents the dopant from penetrating in the underlying oxide layer 18: thanks to this, the thin gate oxide layer 18 is not damaged, and the concentration of dopants at the surface of the regions 14 and 12 under the oxide layer 18 is not altered. At the same time, the photoresist layer 24 and the underlying polysilicon layer 21 are also maskedly etched and selectively removed from the chip regions R4 and R5, wherein the NPN and PNP BJTs have to be formed; the orthogonally implanted P type dopant gives rise to two P deep body regions 27 and 28 (Figs. 7A and 7B): region 27 will form a base region for the NPN BJT; region 28, formed inside the P well region 82, will form part of a collector region for the PNP BJT. The photoresist layer 24 is then completely removed, and a P type dopant (e.g. boron) is implanted through the windows in the polysilicon layer 21 in a direction tilted of about 30-45 degrees with respect to the direction orthogonal to the surface of the polysilicon layer 21. With an implantation dose of about 7.5 * 10 12 atoms/cm 2 and an implantation energy of about 150 keV, it possible to form P channel regions 29 and 30 over and at the sides of the P deep body regions 25 and 26, respectively, extending under the gate oxide 18 (Figs. 8A and 8B). At the same time, P regions 31 and 32 are formed over and at the sides of the P deep body regions 27 and 28 for the NPN and PNP BJTs, respectively. A thermal process of about two hours at a temperature not higher than 900 °C is then performed to activate the dopants (thermal annealing). This thermal process has a thermal budget much lower than that required in known processes, in which the channel regions 29 and 30 are formed by lateral dopant diffusion from the deep body regions instead of by means of the tilted implant as in the present invention. Thanks to this, the thermal process provided in the present invention is compatible with the manufacturing of, for example, EEPROM memory cells, whose tunnel oxides cannot be submitted to too high temperatures for a long times without introducing defects. After the thermal annealing, the concentration of P type dopants at the surface of the N type well regions 12 and 14 is of the order of 1-2*10 17 atoms/cm 3 : this allows to obtain a threshold voltage of the order of 1 V for the high voltage and low voltage lateral DMOS transistors. The polysilicon layer 21 is then maskedly etched and selectively removed to define polysilicon gates 33, 34, 35 and 36 for the high voltage lateral DMOS transistor, the low voltage lateral DMOS transistor, and the P-channel and N-channel MOSFETs, respectively, and a polysilicon floating gate 37 for the EEPROM memory cell (Figs. 9A and 9B). Over regions R1 and R2, drain windows 70 and 38 are also opened in the polysilicon layer 21. The process continues in a per-se known way with the two implant steps of an N type and a P type dopant to form light-doped drain regions at the sides of the polysilicon gates 33-37, the formation of oxide sidewall spacers at the sides of the polysilicon gates 33-37, and the formation of N+ source regions 39 and 40 for the lateral DMOS transistors, N+ drain regions 71 and 41 for the lateral DMOS transistors, N+ source and drain regions 42 for the N-channel MOSFETs, P+ source and drain regions 43 for the P-channel MOSFETs, an N+ emitter region 44 and an N+ collector contact region 45 for the NPN BJT, P+ emitter and collector regions 46 and 47 for the PNP BJT and an N+ base contact region 48, and N+ source and drain regions 49 and 50 for the EEPROM memory cell (Figs. 12A and 12B). All N+ regions are formed by means of a same implantation of an N type dopant, e.g. arsenic, in a dose of about 10 15 -10 16 atoms/cm 2 with an energy of about 60 keV, and all P+ regions are formed by means of a same implantation of a P type dopant, e.g. BF 2 , in a dose of about 10 15 atoms/cm 2 and with an energy of about 70 keV. Coming back to Figures 6A and 6B, a second embodiment of the process of the present invention provides for the deposition of a first photoresist layer 50 on the polysilicon layer 21. The first photoresist layer 50, the underlying polysilicon layer 21 and gate oxide 18 are then maskedly etched and selectively removed to define the gates 33-37 of the lateral DMOS transistors, the N-channel and P-channel MOSFETs, and the EEPROM memory cell, and the drain windows 70 and 38 for the lateral DMOS transistors (Figs. 10A and 10B), and emitters, bases and collectors for the BJTs. A second photoresist layer 52 is then deposited over the whole surface of the chip (Figs. 10A and 10B). The photoresist layer 52 is removed from the chip regions where the deep body regions of the lateral DMOS transistors must be formed, but not from over the drain contact windows 70 and 38 for the lateral DMOS transistors, and from the regions where the base of the NPN BJT and the collector of PNP BJT must be formed (Figs. 11A and 11B). Similarly to the process according to the first embodiment, a heavy dose of a P type dopant is then implanted in a direction orthogonal to the surface of the chip, to form the P+ deep body regions 25-28, and then a P type dopant is implanted with implantation angles tilted of about 30-45 degrees with respect to the orthogonal direction, to form the P regions 29-32 at the sides of the P+ deep body regions 25-28 (Figs. 11A and 11B). The second photoresist layer 52 and the remaining first photoresist layer 50 are then completely removed. From now on, the process steps are the same as those previously described. It should be noted that, as known to the skilled technician, the P deep body regions 25 and 26 of the DMOS transistors are not strictly necessary, and could be omitted. However, their provision allows to increase the devices ruggedness

Claims: Process for the manufacturing of an integrated circuit comprising lateral DMOS-technology power devices and non-volatile memory cells comprising the steps of: forming respective laterally displaced isolated semiconductor regions (R1,R2,R3,R4,R5,R6), electrically insulated from each other and from a common semiconductor substrate (1), inside which semiconductor regions (R1-R6) devices will be to formed; forming conductive insulated gates (33,34,37) for the lateral DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions (R1,R2,R6); inside the isolated semiconductor regions (R1,R2) for the lateral DMOS-technology power devices, forming channel regions (29,30) extending under the insulated gates (33,34), characterized in that said channel regions (29,30) are formed by means of an implantation of a first dopant along directions tilted of a prescribed angle with respect to a direction orthpgonal to a top surface of the integrated circuit, in a dose and with an energy such that said channel regions (29,30) are formed after the implantation of the first dopant by performing a thermal diffusion of the dopants at a temperature not higher than 900°C during about two hours. Process according to claim 1, comprising the steps of forming, inside the isolated semiconductor regions (R1,R2) for the lateral DMOS technology power devices, deep body regions (25,26) aligned with edges of the insulated gates (33,34), said deep body regions (25,26) being formed by means of an implantation of a second dopant in said direction substantially orthogonal to the top surface of the integrated circuit, performed with an energy and with a dopant dose such that the concentration of the first dopant has a peak located at a prescribed distance from the surface of the isolated semiconductor regions (R1,R2) for the lateral DMOS-technology power devices, said channel regions (29,30) and said deep body regions (25,26) being formed by two implantation steps after the formation of a tunnel oxide area (84) for the non-volatile memory cells, both implantation steps being carried out in the same opening defined in one masking step. Process according to claim 2, characterized in that said prescribed angle has a value of about 30°-45°. Process according to claim 2 or 3, characterized in that said second dopant is implanted in a dose of the order of 10 13 atoms/cm 2 and with an energy of about 150-250 keV, and said first dopant is implanted in a dose of the order of 10 12 atoms/cm 2 and with an energy of about 150 keV. Process according to anyone of the preceding claims, characterized in that said isolated semiconductor regions (R1,R2,R3,R4,R5,R6) of a second conductivity type are semiconductor regions isolated from a semiconductor substrate (1) of a first conductivity type by means of respective heavily doped buried regions (5) of a second conductivity type, and isolated from each other by means of vertically extending semiconductor regions (7,17,83) of the first conductivity type. Process according to claim 2, comprising the steps in the sequence set forth: a) forming a insulated conductive layer (21) on the top surface of the integrated circuit; b) forming a photoresist material layer (24) over the insulated conductive layer (21); c) selectively removing portions of the photoresist material layer (24) and of the underlying insulated conductive layer (21), disposed on the isolated semiconductor regions (R1,R2) to open windows for said implantation of the second dopant, with the photoresist material layer (24) and the insulated conductive, layer (21) acting as a mask in the formation of said deep body regions (25,26) in a self-aligned manner with edges of said windows; d) removing the photoresist material layer (24) after the formation of said deep body regions (25,26) by said implantation of said second dopant; e) performing said implantation of the first dopant through said windows; f) selectively removing portions of the remaining insulated conductive layer (21) to form the insulated gates (33,34,37) for the Lateral DMOS-technology power devices and for the non-volatile memory cells, and to open drain windows (70,38) for the formation of drain regions (71,41) of the lateral DMOS-technology power devices; g) forming source regions (39,40) for the lateral DMOS-technology power devices, inside said channel regions (29,30), forming drain regions (71,41) for the lateral DMOS-technology power devices, and forming source and drain regions (49,50) for the memory cells. Process according to claim 2, comprising the steps in the sequence set forth: a) forming a insulated conductive layer (21) on the top surface of the integrated circuit; b) forming a first photoresist material layer (50) over the insulated conductive layer (21); c) selectively removing portions of the first photoresist material layer (50) and of the underlying insulated conductive layer (21) to define insulated gates (33,34,37) for the lateral DMOS-technology power devices and for the non-volatile memory cells, and to open drain windows (70,38) for the formation of drain regions (71,41) of the lateral DMOS-technology power devices; d) forming a second photoresist material layer (52) on the surface of the integrated circuit; e) selectively removing the second photoresist material layer (52) from the regions where the deep body regions of the lateral DMOS-technology power devices must be formed, except from over said drain windows (70,38), to open windows for the implantation of the second and first dopants, to form said deep body regions (25,26) and channel regions (29,30) in a self-aligned manner with edges of the insulated gates (33,34); f) performing said implantations of the second and first dopants through said windows in the second photoresist material layer (52); g) removing said second and first photoresist material layers (50,52); h) forming source regions (39,40) for the lateral DMOS-technology power devices, inside said channel regions (29,30), forming drain regions (71,41) for the lateral DMOS-technology power devices, and forming source and drain regions (49,50) for the memory cells. Process according to anyone of the preceding claims, characterized in that it also provides for forming bipolar junction transistors inside respective isolated semiconductor regions (R4,R5). Process according to anyone of the preceding claims, characterized in that it also provides for forming N-channel and P-channel MOSFETs inside respective isolated semiconductor regions (R3).

Inventors: CONTIERO CLAUDIO, GALBIATI PAOLA, PALMIERI MICHELE, CONTIERO, CLAUDIO, GALBIATI, PAOLA, PALMIERI, MICHELE
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29