Circuit for biasing epitaxial regions

Abstract: A circuit (30) for biasing epitaxial wells of a semiconductor integrated circuit comprises a first transistor (T1) and a second transistor (T2) driven in phase opposition to the first; when the supply voltage is positive, the first transistor (T1), being connected between the power supply and the epitaxial well, is conducting whereas the second transistor (T2) is cut off. When, on the contrary, the supply voltage is negative, the second transistor (T2), being connected between the epitaxial well and the ground reference GND, goes into saturation, thereby holding the epitaxial well biased to ground since, at that time, it is the highest potential present on the device. In this way, it becomes possible to always ensure reverse biasing of the parasitic diodes which form at the junctions between the epitaxial wells and the adjacent regions thereto.

Description: Field of the Invention This invention relates to a circuit for biasing epitaxial wells of an integrated circuit on a substrate of semiconductor material. The invention concerns, particularly but not solely, a circuit for biasing wells which contain passive elements, resistors and capacitors, in order to also provide secure isolation between elements in the same well and/or between different wells should the supply voltage, by its own nature or due to induced disturbation, drop to a lower potential than the ground reference. For a better understanding of the phenomenon, reference can be made to Figure 1, which shows a cross-section through a die of semiconductor material, denoted by 1, comprising a substrate 2 of the P type and two epitaxial wells 3 and 5 of the N type which house two passive elements, in particular a resistor 6 and capacitor 7, on their interiors. The epitaxial wells 3 and 5, if maintained at a higher potential than the adjacent regions of the P type, provide electric isolation from the substrate 2 and between the passive elements 6, 7 themselves. The bias voltage applied to the two wells 3 and 5, denoted by Vb in Figure 1, actually provides reverse bias for parasitic diodes D1 and D2 present at the junctions between the region of the N type, forming the wells 3 and 5, an the adjacent regions of the P type. To have these diodes D1, D2 reverse biased, the isolation wells are usually connected to the supply potential Vcc, since this would normally be the highest potential available on the integrated device. However, in certain particular applications, such as driver circuits for fluorescent lamps or electronic transformers, the supply voltage, being sinusoidal in nature, periodically drops below the ground reference. Also, with circuits which operate in electrically much disturbed environments, such as motor cars, the supply voltage may undergo sudden positive or negative variations, or even drop, albeit for short periods only, to a lower potential than the ground potential. In such cases, where the supply voltage goes negative, the parasitic diodes D1 and D2 become forward biased, resulting in a sudden flow of current and large dissipation of power. These factors can seriously harm, not infrequently in an irreparable way, the integrated circuit. Prior Art A first technical solution to the above problem consists of applying the supply voltage to the regions to be biased through a forward-biased diode. In this way, the flowing of current from ground back to the power supply can be prevented. This solution, although quite simple to implement, has some drawbacks. In fact, on the occurrence of a voltage drop of 0.6-0-7 Volts across the diode, the potential applied to the isolation wells would no longer be the highest potential present on the circuit. Accordingly, the reverse biasing of junctions comprised of the well-forming regions and any adjacent regions of the P type biased to the supply voltage Vcc, cannot be ensured. By the use of a diode of the Schottky type having a threshold voltage within the range of 0.2 to 0.3 Volts, that is below the threshold voltage of a standard diode, a closer biasing potential to the supply voltage could be provided. However, the implementation of a Schottky diode on an integrated circuit involves technological steps which are not always compatible with standard manufacturing processes currently in use and whose incorporation to the process would entail complicated and cost-intensive modifications. A particular circuit for biasing epitaxial isolation wells is described in the European Patent Application EP-A-0 577 906. That Application addresses in particular the problem of holding in the off state the parasitic diode which forms at the junction between the well and the region contained inside the well in the event that this region, or a portion thereof, becomes connected to a higher potential than that of the isolation well. The proposed circuit comprises two transistors of the PNP type, and its operation may be summarized as follows: during normal operation, a first of the transistors holds the N-well connected to the supply voltage Vcc, while the second transistor is at cutoff; as the P-region within the well is brought to a higher potential than the supply voltage Vcc, the second transistor goes into saturation and connects the isolation well to the P-region. Under such conditions, the circuit would prevent the parasitic diodes from being turned on in the event of the supply voltage Vcc dropping, even for a short period only, to a lower potential than the ground reference potential. Since the P-regions contained in the N-well, used for implementing passive elements, e.g. resistors, have a terminal connected to ground, such biasing of the isolation well would result in the parasitic diode formed by the P-N junction between the P-region and the isolation N-well being turned on. A known integrated semiconductor circuit with polarity reversal protection is described in the International Patent Application, published under No. WO 90/06012. This application discloses a circuit for biasing a well region comprising a two transistors, where the first transistor is connected between the well and a first potential reference and with its base connected to a second potential, while the second transistor is connected between the well and the second potential reference and with its base connected to the first potential. Also known is a circuit construction protective bias as described in the International Patent Application, published under No. WO 93/18550. In this application a circuit for biasing a pocket containing a power supply potential circuit element in a junction-isolated circuit is disclosed. This circuit construction comprises a transistor for protecting the junction between the substrate and the pocket from being forward biased. The underlying technical problem of this invention is to provide a biasing circuit for epitaxial wells, which has such structural and functional features as to ensure reverse biasing of the parasitic diodes formed by the junctions between the well, of the N type, and regions of the P type adjacent thereto, in the event of the voltage supply to the device dropping, however momentarily, to negative values with respect to the ground reference. Summary of the Invention The solutive idea on which this invention stands provides for the use of a first electronic switch, connected between the power supply and the epitaxial well, which is closed while the supply voltage is positive. Under this condition, a second electronic switch, connected between the epitaxial well and a ground reference, would be open because driven in phase opposition to the first. On the other hand, as the supply voltage goes negative, the second switch closes to hold the epitaxial well at the ground potential, whereas the first switch opens. That potential now is, in fact, higher than the supply voltage. In this way, reverse biasing of the parasitic diode is always ensured. The features and advantages of the device according to the invention will be apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings, in which: Figure 1 shows, in vertical section and to an enlarged scale, a portion of a prior art integrated circuit including two epitaxial isolation wells; Figure 2 shows a circuit diagram of a first epitaxial well biasing circuit according to the invention; and Figure 3 shows a circuit diagram of a second epitaxial well biasing circuit according to the invention. Detailed Description With reference to the drawing figures, and in particular to Figure 2, generally shown at 20 is a circuit illustrating a first embodiment of the biasing structure according to the invention. The structure 20 comprises an electronic switch, implemented by a bipolar transistor T1 of the PNP type, and two resistors R1 and R2. In detail, the transistor T1 has its emitter terminal E1 connected to the supply voltage Vcc, base terminal B1 connected to a first end of one resistor R1 the other end whereof is connected to a ground potential reference GND, and collector terminal C1 connected to a bias contact 8 of an epitaxial well 3. The second resistor R2 has a first end connected to the bias contact 8 of the epitaxial well 3 and a second end connected to ground, GND. The electronic switch T1 could also be implemented by a transistor of MOS type, without involving any special modifications to the circuit. The principle of operation of the structure 20 will now be described. As the voltage at the node 10, corresponding to the supply voltage Vcc, exceeds the value of the voltage Vbel present between the emitter E1 and the base B1 of the transistor T1, the latter, having its base terminal B1 connected to ground through the resistor R1, goes into conduction and the node 8, being connected to the bias contact of the well, attains the same potential as the node 10 but for the saturation voltage of the transistor T1, which voltage is on the order of a few tens milliVolts and, therefore, quite low. As the supply voltage, and hence the voltage at the node 10, drops below the conduction threshold of the transistor T1, the transistor is cut off and the epitaxial well biased to ground via the resistor R2; at that time, in fact, the ground potential is the highest available potential, and this biasing allows the parasitic diodes to be held in an off state. Figure 3 shows a circuit illustrating a second embodiment, generally denoted by the numeral 30, of the biasing structure according to the invention. The structure 30 comprises two electronic switches, each implemented by a bipolar transistor T1, T2 of PNP type, and three resistors R1, R2 and R3. In detail, the transistor T1 has its emitter terminal E1 connected to the supply voltage Vcc, base terminal B1 connected to one end of a first resistor, R1, the other end whereof is connected to a ground potential reference GND, and collector terminal C1 connected to a bias contact 8 of an epitaxial well 3. The second transistor T2 has its emitter terminal E2 connected to the bias contact 8 of the epitaxial well 3, base terminal B1 connected to one end of a second resistor, R3, having the other end connected to the supply voltage Vcc, and collector terminal C2 connected to the ground potential reference GND. A third resistor, R2, has one end connected to the bias contact 8 of the epitaxial well 3 and the other end connected to ground GND. Both electronic switches could also be implemented by two transistors of MOS type, without this entailing any special modifications to the circuit. The operation of the circuit of Figure 3 is similar in part to that of the previous circuit embodiment. In fact, if the supply voltage Vcc applied to the node 10 is higher than the value of the threshold voltage Vbe1 of the first transistor T1, the latter, having its base terminal B1 connected to ground via the resistor R1, would be conducting and the node 8, being connected to the bias contact of the well, attain the same potential as the node 10 but for the saturation voltage of the transistor T1. Under this condition, the second transistor T2 is at cutoff because the voltage applied between its base terminal B2 and emitter terminal E2 is below its conduction threshold. If the supply voltage Vcc is less than 0.7 Volts, the conduction threshold of the transistor T1, but more than -0.7 Volts, then both transistors T1, T2 would be at cutoff, and the epitaxial well biased to ground via the resistor R2. On the other hand, if the supply voltage Vcc drops below the value of -0.7 Volts, the first transistor T1 is cut off, but the second transistor T2 goes into saturation to firmly connect the bias contact 8 of the epitaxial well 3 to the ground potential reference GND. Thus, reverse biasing of the parasitic diodes is once again ensured. In fact, should the supply voltage decrease enough to become negative, the ground potential is at that time the highest available potential on the device. The following chart summarizes the three different conditions of operation of the circuit of Figure 3 as the supply voltage Vcc changes; in particular, the states of the two transistors T1 and T2, and the value of the output voltage of the circuit Vb applied to the well to be biased, are shown. Vcc T1 T2 Vb >0.7 at saturation at cutoff =Vcc -0.7<Vcc<0.7 at cutoff at cutoff =GND <-0.7 at cutoff at saturation =GND In conclusion, the circuit of this invention does provide, in a simple manner from the standpoint of its construction, a solution to the problem of the parasitic diodes being turned on in the case of the supply voltage to the device becoming negative with respect to the ground reference.

Claims: A semiconductor integrated circuit comprising at least one epitaxial well (3) of a first conductivity type and superposed on or adjacent to at least one region (2,4) of a second conductivity type and a biasing circuit for biasing said epitaxial well, characterized in that said biasing circuit comprises at least one electronic switch (T1) having first (E1) and second (C1) terminals and a control terminal (B1), said first terminal (E1) being connected to a first potential reference (Vcc), said second terminal (C1) being connected to said epitaxial well (3) and, via a first resistive element (R2), to a second potential reference (GND), and said control terminal (B1) being connected, via a second resistive element (R1), to said second potential reference (GND). An integrated circuit according to Claim 1, characterized in that said electronic switch (T1) is a bipolar transistor, said first terminal (E1) is an emitter terminal, said second terminal (C1) is a collector terminal, and said control terminal (B1) is a base terminal. An integrated circuit according to Claim 2 comprising a substrate (2) of the P type, wherein said epitaxial well (3) is of the N type and said region (2,4) is of the P type, characterized in that said bipolar transistor (T1) is a transistor of the PNP type. An integrated circuit according to Claim 1, characterized in that it further comprises at least a second electronic switch (T2) having first (E2) and second (C2) terminals and a control terminal (B2), said first terminal (E2) of said second switch (T2) being connected to the epitaxial well (3), said second terminal (C2) being connected to the second potential reference (GND), and said control terminal (B2) being connected, via a third resistive element (R3), to the first potential reference (Vcc). An integrated circuit according to Claim 4, characterized in that said second (T2) electronic switch is a bipolar transistor, said first terminal (E2) is an emitter terminal, said second terminal (C2) is a collector terminal, and said control terminal (B2) is a base terminal. An integrated circuit according to Claim 5 , comprising a substrate (2) of the P type, wherein said epitaxial well (3) is of the N type and said region (2,4) is of the P type, characterized in that said second (T2) bipolar transistor is of the PNP type.

Inventors: AIELLO NATALE, AIELLO, NATALE
Applicants: CONS RIC MICROELETTRONICA, CO.RI.M.ME.
Application year: 1995
Main classification: H01L27
IPC codes: H01L27, H03K19, H01L21