A CACHE FLUSH MECHANISM FOR A SECONDARY CACHE MEMORY

Abstract: An effective mechanism for cache flushing that can be applied to a memory system operated in dual-mode is disclosed. The dual-mode is composed of two modes using two physically distinguished main memory space respectively at a common logical address in at least a portion of whole address. The interruption of the signal (SMIACT#) that represents the switching of the mode by secondary cache is provided. When SMIACT# is generated by CPU and it is detected by the system core, the system core switches the memory bank for the cache memory to write back, resulting into violating memory consistency between the cache and main memory. But this invention just interrupts the SMIACT# to reach to the system core before the cache flushing is over, assuring the content of the cache memory to be written back to a correct memory bank where the data originally resided, since the system core believes that the mode has not yet been switched though the CPU actually generated SMIACT#.

Description: DESCRIPTICN A CACHE FLUSH MECHANISM FOR A SECONDARY CACHE MENEKY TEXBNICAL FIELD The present invention relates to a mechanism for cache flushing hardware for PCs having secondary cache. Particularly, this mechanism is well applicable to a system having plurality of modes, using plurality of address system for the memory location. BACKGROUND A CPU has a signal input named FTJUSHtt for flushing the internal cache system. The FTJUSHtt signal, when it is driven low by the system core, which controls and manages accessing to the memory, the CPU is forced to flush the entire contents of the on-chip cache. The CPU system is usually made up of a few component other than the CPU itself, for example, a main memory to store information and being accessed by the CPU to derive the data stored therein, a first cache memory which reside between the CPU and the main memory and provides a relatively very fast access to a recjuired data and storing a flick portion of data which is occasionally accessed by the CPU and is duplicatedly stored in the main memory, and preferably a second cache which resides between the first cache memory and the main memory, which is not as fast as the first cache memory, but has an ability to store more data. The second cache memory also has a signal input line named FTJUSHtt, having similar purpose and function. There are wo ways for data write handling between the CPU and the secondary cache. One is write-through operation, which writes data to secondary cache and the main memory at the same time even if the CPU wanted the data to be written only into the secondary cache. The other is write-back operation, which only writes the data to the secondary cache when the CPU wanted the data to be written only into the secondary cache. In other words, there will be no back-up data in main memory in the case of write-back operation. As is easily imagined, the write-back operation is more efficient in view of data transfer, but it has a disadvantage that the contents of the secondary cache have to be transferred or "write-back" to the main memory at the occasion of cache flush for back-up purpose. These components of the system are being connected by a common data transfer line called a CPU bus. Since the bus is common to all the coπponents of the system, an access conflict may occur in the case of starting write-back cycles in response to FTJUSHtt signal. Therefore, an arbitration mechanism is needed to avoid this conflict. Before writing back the modified lines, the secondary cache must obtain ownership of the CPU bus in order to start write back cycle. The CPU system • typically mentioned herewith is shown in figure 1. In this figure, the first cache is included within the CPU and is not shown. Toe main memory is supposed to be connected to the secondary cache, but it is also not shown. The secondary cache is connected to both of the CPU and the system core by FTJUSHtt. The system core is a component which controls the input/output operation between the CPU, the secondary cache and the main memory. The FTJUSHtt provides the request to flush the first and secondary cache from the system core to the CPU.Te CPU and the system core is connected via HOTJD and HEDA. The HOTJD is driven when the system core requests the CPU to release the bus. In turn, the CPU releases the bus after it has finished with the current tasks using bus, asserts HLDAtt through HLDA to inform of the fact that the bus has been released. However, the secondary cache cannot obtain the ownership of the bus by itself in this system, since it can not transfer a signal to obtain the bus to the CPU nor the system core. This results into a conclusion that write-back operation can not be achieved in this system, because in order to achieve write-back operation, the secondary cache has to intensively obtain the ownership of the bus prior to starting write-back cycles. This is the primary problem in the prior art. To solve this problem, BOFFtt line is added to the system. This line connects the secondary cache to the CPU, and when this is asserted, the CPU will instantly release the bus line, in turn the secondary cache obtains the ownership of the bus at the next CPU cycle. BOFFtt forces the CPU to abort the current task and regenerate it later on from the first. However, this method may cause a problem if the secondary cache asserts BOFFtt line while the CPU is working in a history sensitive manner. For example, if CPU is in a I/O cycle, the CPU should not cease its operation to release the bus because releasing bus in the midst of I/O operation , eg. data transfer, will cause an inconsistency of the data, and even if the cycle is regenerated later, the inconsistency may not be recovered. It should be also noted that it is not possible for the secondary cache to detect whether the CPU is working in a history sensitive manner or not, nor selectively assert BOFFtt in the timing window in which the CPU is not working in history sensitive manner. Another way for obtaining the bus ownership for the secondary cache is to assert BOFFtt when the CPU generates a dummy I/O cycle as shown in a document "Look-Aside Store In Cache Functional Specification, by Phil Milling and Jorge Lenta, PreLuninary revision 1.1 (Jan, '93)". This method will solve the problem caused in the first way, since the secondary cache will go into the flush pending state when it detects the system core asserting FTJUSHtt. In this pending state, the secondary cache waits for a dummy I/O cycle, which the CPU is assumed to generate later. However, in this method, the flush cycle must be initiated by the CPU since the CPU have to generate the dummy I/O cycle, actually being stimulated by a system program. The problem here is that it can not be applied to a system in which the system core initiates the flush. One alternative for this method is to assert BOFFtt when the CPU generates a flush acknowledge cycle. This method is, when the secondary cache detects the system core asserting FTJUSHtt, the secondary cache goes into the flush pending state and waits for the flush acknowledge cycle, which the CPU generates after it has completed the on-chip cache flush. But this method is inoperable to the type of the CPU that does not generates the flush acknowledge cycle. Actually, very limited types of the CPU generates flush acknowledge cycle, which implies that this method is not corπmonly processed in various systems. Recently, many CPUs used in a personal computer (PC) system are applying a dual-mode memory management for application-transparent system services, such as power saving facility. For example, Intel x86 CPU chip adopts a mode which utilizes two apparently distinguished memory system using a common unique addresses at least a portion of the entire address region. This means that a specific address corresponds to two different physical locations and either one of the two different physical location is defined by detecting the current mode of which the system runs. This additional mode is usually called a "system management mode" which is often abbreviated as SMM, on the contrary to the standard mode. When the system has to get into the SMM, the system core will interrupt normal program execution and invoke the SMM by generating a System Management Interrupt (SMItt) request to the CPU. Tπis dual mode system is schematically shown in figure 7. In this system, the operation is made in two modes of standard mode and system management mode, which is defined by SMIACTtt generated by the CPU. For example, when the SMIACTtt is driven high, the whole system is operated in the standard mode, which means that memory access will be made to standard RAM. In turn, when the SMIACTtt is driven low, the whole system goes into the SMM, which means that memory access can be possibly made to the SMAM. It should be noted, that in this figure 7, SMRAM exist in the range of logical address of 1000 to 2000, so an access to the address within this range will be made to the SMRAM and an access to the other memory address will be made to standard RAM, even if the whole system was operated in the SMM. SMRAM is a physical memory dedicated for use by CPU while in the SMM, and having size of 32KB to 4GB, containing SMM handler codes, relevant system specific SMM data, and the processor state information representing the processor state prior to entering into the SMM. When the CPU enters into the SMM, it asserts SMIACTtt low thus alerting the system core to switch into SMRAM space. The CPU then stores its cπrrrent register state information into SMRAM in a stack-like fashion beginning at the top of the SMRAM space. This is referred to as the processor state dump, context switch or state save. Upon completion of the state save sequence, execution of the SMI handler will then begin. Toe CPU ass* -ts the SMIACTtt output to indicate to the memory controller that it is operating in SMM. The system logic should be ensured that only this area is being accessed by the CPU and SMI handler. No existing system has allowed the system core to use FTJUSHtt for flushing a CPU-on-chip cache and a secondary cache both in the standard mode and the SMM. This is because the dual mode machines are previously not using write-back ways at the occasion of cache flush. But it is assumed that co-existence of dual mode and the write-back ways will upgrade the performance of personal computers, thus the cache flush problems with write-back and SMM has to be solved. The request for cache flushing is frequently made when the CPU wants to switch the mode. Without any special effort, it is likely that the data consistency between the secondary cache and the main memory is violated, since SMIACTtt is generated from the CPU almost at the same time with the actual cache flushing operation. This means that if SMIACTtt is already generated and the system core has changed its memory bank one from the other (eg. SMRAM to standard RAM), the write-back from the cache memory will be made into wrong memory which the content of the cache memory did not originally belong. SUMMARY OF THE INVENTION Accordingly, it is one object of this invention to provide an efficient mechanism to achieve a cache flush not violating write-back cycles or no need to pay attention to the turnings between the flush operation and the write-back cycles. It is another object of the invention to perform flush cycle not initiated by the CPU, or more specifically, initiated by the system core. It is another object of this invention to provide an efficient mechanism to achieve a cache flush in a system having dual mode such as standard mode and system management mode. It is another object of this invention to provide a cache flush mechanism fully compatible to Intel x86 CPU's bus interface, which the system core does not have to pay attention to the tunings between the cache flush operation and the write-back cycles. In one aspect of the invention, a signal generated by secondary cache to the CPU requesting to obtain the ownership of the bus to start cache flushing is provided into the system. In another aspect of this invention, the interruption of the signal(SMIACTtt) made by secondary cache to prevent from system core to detect the mode switch is provided. When SMIACTtt is generated by CPU and it is detected by the system core, the system core switches the memory bank for the cache memory to write back, resulting into violating memory consistency between the cache and main memory. But this invention just interrupts the SMIACTtt to reach to the system core before the cache flushing is over, assuring the content of the cache memory to be written back to a correct memory bank where the data originally resided, since the system core believes that the mode has not yet been switched though the CPU actually generated SMIACTtt. BRIEF DESCRIPTION OF THE DRAWINGS Fig.l is a memory system ccπmonly implemented in a prior art. Fig.2 is a schematic diagram of the memory system of first embodiment of the present invention. Fig.3 is a signal turning chart of the memory system shown in Fig.2. Fig.4 is a schematic diagram of the memory system of second embodiment of the present invention. Fig.5 is a signal tuning chart of the memory system shown in Fig.4, when the bus access from the CPU and the secondary cache is not conflicted. Fig.6 is another signal timing chart of the memory system shown in Fig.4, when the bus access from the CPU and the secondary cache is conflicted. Fig.7 is a schematic diagram of dual-mode memory system for explanatory purpose. EMBODIMENTS One embodiment of this invention is implemented as shown in figure 2. The system includes a CPU, a system core, and a secondary cache connected to both of the CPU and the secondary cache. In this embodiment of the invention, the HOLD and BTJDA signals are controlled to achieve a cache flush. When the secondary cache starts flushing, it asserts L2H0LD, which is ORed with SHOLD which is being an output from the system core. The secondary cache receives HTJDA from the CPU and passes it to the system core as L2HLDA. The HOLD and HLDA are signals having same function mentioned in the background. The HOLD requests the CPU to release the bus, but in this invention, the HOLD is created by SHOLD and L2H0LD ORed. This means that the secondary cache can make a request of releasing the bus to the CPU by asserting L2H0TJD, as well as the system core by using SABDLD. Typically, the system core asserts the SAHOLD when it wants to use bus for snooping, or to detect the consistency between the cache memories and the main memory. The HLDA is a permission from the CPU that the secondary cache can obtain the bus. On contrary to figure 1, the secondary cache can detect this permission prior to the system core, since HLDA is interrupted by the secondary cache. This means that bus request from the secondary cache is superior to that from the system core, which enables the write-back cycles to start right after the permission has made. The flush operation is well described by referring to the turning chart shown in figure 3. In cycle 1, the system core asserts FTJUSHtt to be low, which is a request from the system core to start flush operation. Toe secondary cache detects the FTJUSHtt at the end of cycle 1 thus driving L2HOLD high in cycle 2.Toe L2HOLD is ORed with SHOLD to be the output being fed to the CPU as a HOLD forcing the CPU to float the CPU bus. When the CPU releases the bus, HLDA is asserted to be high in cycle 3, and the secondary cache starts write-back cycles from the beginning of cycle 4, by detecting the HLDA being high. The HLDA being high is taken as a permission of the CPU to the secondary cache to start it's operation, since the bus had been released by the CPU. At cycle 20, the secondary cache finishes the write-back cycles, and deasserts the L2H0LD resulting the HOLD to be low. This will let the CPU deasserts HLDA in cycle 21 for the secondary cache to receive this signal and to pass it to the system core as L2HLDA. It should be noted, however, that the CPU does not always release the bus at the cycle immediately subsequent to the cycle which the HOLD is asserted. The CPU will only release the bus when it's outstanding task finishes at a certain cycle. So in figure 3, the CPU happened not performing a task that hangs on after cycle 3. But if the CPU had been processing something history-sensitive, it would have continued its task till it had been finished, and then assert HLDA high probably in cycle 10 or 100. The decision of whether the CPU should pass the bus immediately to the secondary cache for flush operation, or the CPU should continue its task till it is over depends solely on to the CPU. In this manner, a proper write-back cycles can achieved even though the CPU was doing scπething history sensitive, solving one of the primary problem the prior art had. This mechanism can prevent the system core from accidentally starting snooping operations since the HLDA is interrupted by the secondary cache, resulting the L2HLDA kept low during the write-back cycles. The snooping can start only after the system core knows the L2HLDA is asserted by the secondary cache, which means that the write-back cycles have finished. In this manner, the secondary cache can initiatively starts its write-back operation upon flush request, thus solving another one of the problems prior art had. Another embodiment of this invention is performed in a system operating in dual modes, such as standard mode and system management mode. Things are being more complicated when dual modes are available in a system, since secondary cache has to write back to the correct physical memory exactly in correspondence with the current operating mode. This is, in more detail, on occasion of cache flush during the standard mode, the write-back has to be made to the standard RAM, not to the system management RAM (SMRAM). If a write-back is made to the SMRAM in the standard mode by mistake, the data consistency will be violated. In same words, if the cache flush was performed during the system management mode (SSM), the write-back has to be made to the SMRAM, not to the standard RAM. Again, if the write-back was made to the standard RAM by mistake, the data consistency will be violated. In this embodiment, the mentioned objects of this invention are achieved by controlling AHOLD, BOFFtt and SMIACTtt signals. Signal lines connect components of the system as shown in the figure 4. The secondary cache can drive L2AHOLD and L2BOFF# which is ORed and invertedly ORed to SAHOLD and inverted BOFFtt respectively, both being outputs from the system core. When system core wants to perform the flush operation, the system core asserts FTJUSHtt low, which is also detected by the secondary cache and forces it to assert L2AH0LD high, forcing the CPU to float its address bus and to prevent the CPU from getting into subsequent tasks consuming a certain range of bus cycles. But as mentioned in the previous embodiment, if the CPU was performing a history-sensitive task, the CPU does not have to give up the bus right after the secondary cache asserted the L2AH0LD. The secondary cache maintains IL2EMIACTtt at its level despite of the CPU driving SMIACTtt low. This prevents the system core from switching the memory bank from the standard memory to the SMRAM, ensuring the data to be written back to a correct memory which it belongs. In other words, when dual mode operation is applied to a system, SMIACTtt is the signal to change one mode into another, and if the change of SMIACTtt were directly transferred to the system core, system core assumes that the operation mode has been changed and switches the memory bank, resulting into writing back into a wrong memory. This occurs if the SMIACTtt is directly transferred to the system core without any control by the secondary cache. So, as shown in figure 4, the SMIACTtt is intercepted by the secondary cache, to make the system core believe that the mode has not yet been changed by maintaining the L2SMIACTtt at the same level. By this way, system core considers that the mode has not yet been changed, thus not switehing the memory bank, and the data in the secondary cache will be successfully written back to the standard RAM, achieving consistency of the data. This mechanism will follow either one of two scenarios. (i) The CPU asserts ADStt not at the same time with secondary cache asserts L2AH0LD, or (ii) The CPU asserts ADStt at the same time with L2ABDLD assertion. The ADStt is a signal generated by the CPU, the secondary cache and the system core, appealing to the other components of the system to request the bus. When the CPU was not intending to use the bus at the timing that the secondary cache wanted to start write-back operation, which means that ADStt is not asserted at the same time with L2AH0LD, then follows scenario 1. When the CPU intended to use the bus at the same timing with the secondary cache intending to start write-back cycles, which means that ADStt is being asserted at the same time with L2AH0LD, then follows scenario 2. In other words, scenario 2 is the case that two bus access requests from the CPU and the secondary cache conflicts. As for scenario 1, the turning chart is hereby shown in figure 5. a) The system core asserts FTJUSHtt in cycle 1. This is the notice of system core to the CPU to start flush operation. The FTJUSHtt is also detected by the secondary cache at the end of cycle 1. b) When the secondary cache detects the FTJUSHtt being low, it drives L2AH0LD high in cycle 2 to make the CPU float the address bus in the next cycle. L2AH0LD is ORed with SAHOLD and fed to the CPU as AHOLD. c) If the CPU does not start the next bus cycle, then the write-back operation can be started. This is detected by the stated ADStt. If the CPU does not drive ADStt low simultaneously with AHOLD in cycle 2, the secondary cache assumes that the write-back cycles can be started since the CPU is not using the bus, thus driving LZBOFFtt low in cycle 3. d) Then the secondary cache successfully starts the write-back cycles in cycle 4 (ADStt driven by secondary cache). e) It should be noted that though the SMIACTtt is asserted low in cycle 2, the secondary cache does not assert the 112SMIACTtt low in correspondence. Tnis shows that the write-back operation can be achieved to an appropriate memory, even if the mode has been changed. Speaking more into detail, the FTJUSHtt is asserted by the system core when it wants to change the operation mode. This signal makes the CPU assert SMIACTtt low in the subsequent cycle, which informs of the change of the operation mode to the secondary cache. The secondary cache will start its write-back cycle as soon as it is confirmed that the CPU cycles are over, which are shown in step (a) to (d), but since the change of the operation mode is not informed to the system core, by the secondary cache not asserting L2SMIACTtt low at this stage, the system core does not switch the memory bank to be written-back. This results in the secondary cache writing back to the original memory bank that the information was originally resident or to the memory bank that the CPU intended the information to be stored. This deferred switxhing of SMIACTtt to I^SMIACTtt is the key of this invention, in aspect of applying write-back cycle in dual operation mode system. Also, by making operation as described, it is guaranteed that the CPU will not drive ADStt low in cycle 3, since AHOLD is active in the previous cycle. As for the scenario 2, which is the case that two bus requests from the CPU and the secondary cache are conflicting, the operation should be modified to scenario 2 as described as follows, as well as shown in figure 6. As mentioned, this is the case that ADStt, which is a bus request signal from the CPU, and the AHOLD, which is the bus request from either the seconds y cache or the system core, are simultaneously asserted. The first two steps are the same, which are: a) The system core asserts FLUSHtt in cycle 1. This is the notice of system core to the CPU to start flush operation. The FLUSHtt is also detected by the secondary cache at the end of cycle 1. b) When the secondary cache detects the FTJUSHtt being low, it drives L2AH0LD high in cycle 2 to make the CPU float the address bus in the next cycle. L2AH0LD is ORed with SAHOLD and fed to the CPU as AHOLD, appealing to the CPU of the secondary cache willing to occupy the bus for write-back cycles. But in this scenario, the ADStt is happened to be asserted simultaneously with the AHOLD, which is distinctive from the case in scenario 1, thus the modified steps come, which are: c) The CPU drives ADStt low simultaneously with the AHOLD being high in cycle 2. The AHOLD is kept high until RDYtt becomes low, which shows that the CPU is finished with the current task using the bus. It shall be noticed, that RDYtt indicates the end of the CPU occupying the bus. d) When the secondary cache detects the RDYtt being lew at the end of cycle 4, the AHOLD is being dropped at the same time with BOFFtt. e) Then the secondary cache successfully starts the write-back cycles in cycle 4 (WBADStt). As for the relationship between the SMIACTtt and the L2SMIACTtt, it is just the same as scenario 1. By making operation as described, it is guaranteed that the CPU will not drive ADStt low in cycle 5, because AHOLD is active in cycle 4. It should be noted that though this embodiment is referred in accordance with dual mode system, this can be also applied to a single mode system. While embodiments of this invention that have been described are the preferred implementations , those skilled in the art will understand that variations thereor may also be possible. Therefore, the invention is entitled to protection within the full scope of the claims.

Claims: CLAIMS 1. A computer memory system having a CPU, a system core and a cache memory connected to said CPU and said system core via bus, comprising: A first signal means generated by said system core to said CPU and said cache memory to flush the content of said cache memory; A second signal means generated by said cache memory to said CPU in response to said first signal means for requesting said CPU to release said bus; A third signal means generated by said CPU in response to said second signal means to inform of said cache memory that CPU has released said bus. 2. A computer system of claim 1 further comprising: A fourth signal means generated by said cache memory to said system core after said cache memory finished a flush operation. 3. A computer system of claim 1 wherein said second signal means is ORed with a fifth signal means generated by said system core for requesting said CPU to release said bus. 4. A computer system of claim 3 wherein said fifth signal means is also fed to said cache memory. 5. A computer memory system having a CPU, a system core, a cache memory connected to said CPU and said system core via bus, and a signal line enabled by any one of said CPU, said system core or said cache memory indicating request for said bus, comprising: A first signal means generated by said system core to said CPU and said cache memory to flush the content of said cache memory; A second signal means generated by said cache memory to said CPU in response to said first signal means for requesting said CPU to release said bus; wherein said cache memory obtain the ownership of said bus when said signal line is not enabled by any one of said CPU or said system core. 6. A computer memory system having a CPU, a system core, a cache memory connected to said CPU and said system core via bus, and a signal line enabled by any one of said CPU, said system core or said cache memory indicating request for said bus, comprising: A first signal means generated by said system core to said CPU and said cache memory to flush the content of said cache memory; A second signal means generated by said cache memory to said CPU in response to said first signal means for requesting said CPU to release said bus; wherein said cache memory obtain the ownership of said bus after said CPU finishes its current task when said signal line is asserted by said CPU at the same time said second signal means is generated. 7. A method for cache flushing in a computer memory system having a CPU, a system core, a cache memory connected to said CPU and said system core via bus, and a signal line enabled by any one of said CPU, said system core or said cache memory indicating request for said bus, said memory system operating in a plurality of modes using a plurality of physically distinguished main memory spaces respectively having a common logical address at least in a portion of whole logical address, comprising the steps of: Said system core generating a first signal means to said CPU and said cache memory to flush the content of said cache memory; Said cache memory generating a second signal to said CPU in response to said first signal means for requesting said CPU to release said bus; Said CPU generating a third signal means to said cache memory indicating that said mode has been switched; Said cache memory generating a fourth signal means to said system core indicating that said mode has been switched; wherein said fourth signal means is generated after flushing of said cache memory has been completed. 8. A method for cache flushing in a computer memory system having a CPU, a system core, a cache memory connected to said CPU and said system core via bus, and a signal line enabled by any one of said CPU, said system core or said cache memory indicating request for said bus, said memory system operating in a plurality of modes using a plurality of physically distinguished main memory spaces respectively having a common logical address at least in a portion of whole logical address, comprising the steps of: said system core generating a first signal for requesting said mode to be changed from a first node to a second mode; said cache memory generating a second signal requesting said CPU to release said bus in response to said first signal; said CPU generating a third signal for switching said mode in response to said second signal wherein said third signal is interrupted by said cache memory to defer the system core detecting said third signal after said cache memory has completed cache flushing. 9. A method for cache flushing in a computer memory system of claim 8 further ccπprising the step of said CPU releasing said bus after it has completed its current task. 10. A method for cache flushing in a computer memory system of claim 9 wherein said CPU does not generate said third signal prior to said CPU releasing said bus. 11. A computer memory system having a CPU, a system core, a cache memory connected to said CPU and said system core via bus, said memory system operating in a plurality of modes using a plurality of physically distinguished main memory spaces respectively having a common logical address at least in a portion of whole logical address, wherein the signal generated from said CPU indicating that said mode has been switched is interrupted by said cache memory, to defer said system core detecting said signal for at least one clock cycle from the clock cycle that said signal is generated. 12. A computer memory system claimed in claim 11, wherein said system core detecting said signal being defered till flushing of said cache memory is over. 13. A computer memory system claimed in claim 11, wherein said cache system writes back the content of said cache memory to a main memory which is accessed in the prior mode that the memory system used to be before mode switching.

Inventors: NAKADA TAKEO, OHBA NOBUYUKI, NAKADA, TAKEO, OHBA, NOBUYUKI
Applicants: IBM, NAKADA TAKEO, OHBA NOBUYUKI, INTERNATIONAL BUSINESS MACHINES CORPORATION, NAKADA, TAKEO, OHBA, NOBUYUKI
Application year: 1995
Main classification: G06F12
IPC codes: G06F12