Memory control method and device suitable for information processing system comprising a buffer memory unit

Abstract: The present invention relates to a memory control method and a memory control device each suitable for information processing systems such as multiprocessing systems where plural data processing systems execute concurrently an operating process, and particularly to a memory control method and a memory control device each of which controls the data holding state of a buffer memory unit (7) arranged in each of data processing units on a store-in basis to gain high speed access to the main storage unit. The memory control device issues a predetermined process command to be sent to the buffer memory unit (7) to the data processing unit (2), and sets a flag showing a process under request, to a portion to be processed by the predetermined process command in the tag copying unit (5). This structure can reduce the amount of hardware and improve the port use efficiency, thus realizing the system constructing cost reduced and the processing speed improved.

Description: The present invention relates to a memory control method and a memory control device each suitably used for information processing systems such as multiprocessing systems where plural data processing unit's execute concurrently an operating process. Particularly, the present invention relates to a memory control method and a memory control device each of which controls the state of data held in a buffer memory unit on a store-in basis, the buffer memory unit arranged in each of data processing units, to gain high speed access to a main storage unit. Recently, various research and development has been made to improve the processing capability of information processing equipment. Particularly, in order to realize improved processing speed, it has been desired to gain a high speed access of the memory device. One of approaches is to construct the hierarchical memory system. The information processing equipment consists of plural data processing units (central processing units (CPUs)) each of which executes a data operation process, a main storage unit that stores data, and a memory control unit that stores temporarily data information that the data processing unit has accessed the main storage unit, into a buffer memory unit, and then controls it. Particularly, a remarkable progress has been made in the multiprocessing system where plural CPUs operate concurrently and in parallel to execute operation using data processing equipment. The conversion into a multiprocessor tends to increase the number of reading or writing requests which are issued simultaneously from plural CPUs to the memory control unit. High speed processing leads to gaining high speed access to a request. Hence, it has been desired to deal concurrently with requests to addresses which do not contend with each other. In the case where the buffer memory unit is controlled on a store-in basis, since the latest data of an address to be processed is stored in the top-level buffer memory unit, a data transfer or an invalidating process is needed between plural buffer memory units. It must be limited to gain an interrupt access to a block including an address to be processed during processing. Hence it is required to shorten an access waiting time to a request and to improve an access throughput. Fig. 12 is a block diagram showing an information processing device that processes concurrently in response to requests to addresses which do not contend with each other to gain access at high speed. Referring to Fig. 12, the main storage unit 101 stores data sets. Numeral 102 is a data processing unit (or CPU) which can execute concurrently and in parallel an operation process and numeral 103 is a data processing unit (or CPU) which can execute concurrently and in parallel an operation process. The data processing unit 102 includes a buffer memory unit (BS) 106 and the data processing unit 103 includes a buffer memory unit (BS) 107. The buffer memory unit 106 includes a data region 108 that holds a piece of data stored in the main storage unit 101 and a tag region 109 that holds tag information including the address of data stored in the data region 108. The buffer memory unit 107 includes a data region 110 that holds a piece of data stored in the main storage unit 101 and a tag region 111 that holds tag information including the address of data stored in the data region 109. The input/output control unit (IOP) 104 outputs a request to be sent to the data processing units 102 and 103 to the memory control unit 105. The memory control unit (MCU) 105 controls data transfer between the main storage unit 101 and the buffer memory units 106 and 107 on a store-in basis. The memory control unit 105 includes acceptance ports 112 to 114, a priority circuit 115, a tag copying unit (a second tag unit, TAG 2) 116, an address comparing unit 117, an order issuing unit 118, a response waiting control port 119, and an order response processing unit 120. The acceptance port 112 stores a process request from the data processing unit 102; the acceptance port 113 stores a process request from the acceptance port 103; and the acceptance port 114 stores a process request from the input/output control unit 104. The priority circuit 115 outputs selectively either one of process requests from the acceptance ports 112 to 114. The tag copying unit 116 stores the copies of the tag regions 109 and 111 in the buffer memory unit and then retrieves whether an address corresponding to a process request selected with the priority circuit 115 is stored in the buffer memory unit 106 or 107. The address comparing unit 117 compares the address corresponding to a process request selected with the priority circuit 115 with the addresses corresponding to all process requests in a waiting state stored in the acceptance ports 112 to 114. The order issuing unit 118 captures the retrieval result (refer to numeral 126 in Fig. 12) from the tag copying unit 116 and the comparison result (refer to numeral 127 in Fig. 12) from the address comparing unit 117, and then issues an order (MCU order) corresponding to a request if either the buffer memory units 102 or 103 stores an address to be processed, or an address corresponding to a process request input from the priority circuit 115 while a block including a target address is not in a response waiting state of an order once issued. The order is a general term of a data transfer request or a process request which invalidates entries existing in the buffer memory units 106 and 107, issued from the memory control unit 105 to the buffer memory units 106 and 107. The response waiting control port (BCP) 119 sets bits as order-issuing sources respectively corresponding to the data processing units 102 and 103. The order response processing circuit 120 inputs a response to an order and then resets a bit corresponding to a request source set by the response control port 119. The operation of the information processing device will be described below with reference to the flowchart shown in Fig. 13 and the time chart shown in Fig. 14. For a brief explanation, it is assumed that all responses to process requests have been returned during the duration t6 shown in Fig. 14. For example, a process request (or request) issued from the data processing unit 102 (refer to the step A1 shown in Fig. 13 and the duration t1 shown in Fig. 14) is stored in the request acceptance port 112 within the memory control unit 105 (refer to the step A2 in Fig. 13 and the duration t2 shown in Fig. 14). When the priority circuit 115 selects a process request stored in the acceptance port 112 (refer to YES route in the step A3 shown in Fig. 13 and the duration t3 shown in Fig. 14), the tag copying unit 116 retrieves the address corresponding to the process request (refer to the step A4 shown in Fig. 13 and the duration t4 shown in Fig. 14) to decide whether the address of interest is held in the buffer memory unit 109 or 111 (refer to the step A5 in Fig. 13). At the same time, the address comparing unit 117 compares the address with the process request addresses of all requests (refer to the step A6 in Fig. 13) and decides whether an address of interest is in a waiting state (refer to the step A7 in Fig. 13). The order issuing unit 118 receives the retrieval result 126 from the tag copying unit 116 and the comparison result 127 from the address comparing unit 117, and then issues an order in response to the process request when an address of interest exists in either the buffer memory unit 106 or 107 and data block including the address of interest is not in a response waiting state to the order of a data block previously issued (refer to the steps A8 and A9 in Fig. 13 and the duration t5 in Fig. 14). In the step A9, a bit (refer to numeral 121 in Fig. 12) which corresponds to the data processing unit of the order issuing source within the response waiting control port 45 is set at the same time when an order corresponding to a process request is issued (refer to the step A10 in Fig. 13). Thereafter, after the data processing units 102 and 103 have responded to the issued order (refer to numerals 122 and 123 in Fig. 12 and the duration t6 in Fig. 14) (YES route in the step A11), the order responding circuit 120 resets the bit 121 in the order issuing unit 118 (refer to the numeral 124 in Fig. 12 and the step A12). After all the bits in the bit 121 have been reset (YES route in the step A13), the response-wait control port 119 outputs a port reset signal (refer to numeral 125 in Fig. 12), thus releasing the acceptance port 112 (refer to the step A14 in Fig. 13). When the order issuing unit 118 decides that an address of interest exists in the buffer memory unit 106 or 107 and in the waiting state of an order previously issued, based on the retrieval result 126 from the tag copying unit 116 and the comparison result 127 from the address comparing unit 117, it is decided that the order issuing unit 118 cannot issue an order. Thus, the process request selected by the priority circuit 115 is canceled (refer to the steps A8 to A15 in Fig. 13). Since the acceptance port 112 holds the process request, the priority circuit 115 can select it again (refer to the step A3 in Fig. 13). When an address of interest does exist in neither the buffer memory unit 106 or 107, based on the retrieval result 126 from the tag copying unit 116 and the comparison result 127 from the address comparing unit 117, the order issuing unit 118 requests the main storage unit 101 to read out the data block of the address of interest (refer to the step A16 in Fig. 13). The response waiting control port 119 outputs a port reset signal 125 to release the acceptance port 112 (refer to the step A14 in Fig. 13). With the recent multiprocessor-oriented technologies, a memory protection checking that checks whether an access to a requested address is possible is generally performed to prevent plural programs and data from being destroyed due to an input and output operation. In the case of a store request to the main storage unit accompanying the memory protection checking, the checking must be completed before a writing operation is instructed to the main storage unit. In some store-in-type information processing equipment, the latest data does not exist in a main storage unit, but exists only in the buffer memory unit in the data processing unit. In this case, when a store request in a data unit smaller than the minimum move-out unit in the buffer memory unit is issued from the input/output control unit to the main storage unit, a data block with an address to be subjected to a store request must be moved from the data processing unit to the main storage unit before data is stored from the input/output control unit to the main storage unit. Hence, when a store request to the main storage unit issued from the input/output control unit to the memory control unit, together with a memory protection checking, and issued to the data unit smaller than the minimum move-out unit of the buffer memory unit, the input/output control unit stores data to the main storage unit after both the result of the memory protection checking and the retrieval result of the tag copying unit (the second tag region) have been reported. Fig. 15 is a block diagram showing an information processing device with a memory protection checking function. Referring to Fig. 15, the information processing device includes the main storage unit 101, the data processing units 102 and 103, and the input/output control unit 104, each of which functions in a manner similar to the corresponding element in the information processing device shown in Fig. 12. The memory control unit 205 includes the acceptance ports 112 to 114, the priority circuit 115, and the tag copying unit 116, each of which functions in a manner similar to the corresponding element in the memory control unit 105. The memory control unit 205 includes a memory protection key storing unit (KSU) 212 which stores data (key) to perform a memory protection check according to a process request from the input/output unit 104. The process request described above is a store request with a memory protection check to be issued to the main storage unit 101 from the input/output control unit 104 to the memory control unit 205. The store request is issued to the data unit smaller than the minimum move-out unit of the buffer memory units 106 or 107 and issued to an address with the latest data to the main storage unit 101. The memory protection checking circuit (KCHK) 213 performs a memory protection checking, based on the data for the memory protection check read out of the memory protection key storing unit 212 according to the address corresponding to the process request from the priority circuit 115. When the checking result shows an accessible state, the priority circuit 115 resumes its selecting operation and at the same time outputs a releasing control signal to the acceptance port 114. Moreover, numeral 216 represents a queue which stores a store request issued from the memory control unit 205 to the main storage unit 101, and 217 represents a priority circuit which selects the priority of the store request. The operation of the information processing equipment having the above-configuration will be described below with reference to the flowchart shown in Fig. 16 and the time chart shown in Fig. 17. In other words, when a store request accompanying the memory protection check which is issued to data unit smaller than the minimum move-out unit of each of the buffer memory units 106 and 107 is issued to the main storage unit 101 via the input/output control unit 104 (refer to the step B1 shown in Fig. 16 and the duration t21 shown in Fig. 17), it is stored into the acceptance port 114 (refer to the step B2 shown in Fig. 16 and the duration t22 shown in Fig. 17). When the priority circuit 115 selects the store request (refer to the step B3 in Fig. 16 and the duration t23 in Fig. 17), it reads out data used for a memory protection checking (refer to duration t26 in Fig. 17). Then the memory protection checking circuit 213 performs the memory protection checking (refer to the step B4 in Fig. 16 and the duration t27 in Fig. 17). In other words, the memory protection key storing unit 212 reads out a key corresponding to the address to be subjected to the store request. The memory protection checking circuit 213 compares the key with the key-checking key associated with the store request. The result of the memory protection checking is informed to the acceptance port 114. If the access is not allowed (refer to the NO route of the step B4 in Fig. 16), the store request is canceled (in the step B14 in Fig. 16). As a result, the acceptance port 114 is released. When the access is allowed, the fact is reported to the acceptance port 114 (the step B5 in Fig. 16). Then till the priority circuit 115 participates in a selecting operation, the acceptance port 114 queues and holds the store request from the input/output control unit 104. When the priority circuit 115 selects the store request held by the acceptance port 114 (refer to the step B6 in Fig. 16 and the duration t28 shown in Fig. 17), the acceptance port 114 is released (in the step B7 in Fig. 16). Then by retrieving the tag copying unit 116, it is decided whether the latest data of the corresponding address exists in the buffer memory unit 106 or 107 (in the step B8 in Fig. 16 and the duration t29 in Fig. 17). If it is decided that the latest data exists in neither the buffer memory units 106 or 107 (an erroneous hit, the NO route in the step B8 shown in Fig. 16), the store data from the input/output control unit 104 is stored into the main storage unit 101 (in the step B13 shown in Fig. 16). If it is decided that the latest data exists in the buffer memory unit 106 or 107 (a data hit, the YES route of the step B8 shown in Fig. 16) the memory control unit 205 issues a move-out order to the data processing unit 102 or 103 having the latest data (refer to the duration t30 shown in Fig. 17). When the acceptance port 112 or 113 stores a response (refer to the duration t33 in Fig. 17) to the order issued from the data processing unit 102 or 103 (refer to the step B10 in Fig. 16 and the duration t32 in Fig. 17), the priority circuit 115 takes part in a priority selection (in the step B11 shown in Fig. 16). Thereafter, when the priority circuit 115 selects the response to the order (refer to the duration t34 in Fig. 17), the acceptance port 112 or 113 storing the response is released. The main storage unit 101 is accessed with an address corresponding to a store request via the queue 216 and the priority circuit 217. Then the main storage unit 101 stores the move-out data from the data processing unit 102 or 103 (refer to the step B12 in Fig. 16 and the duration t35 in Fig. 17) as well as the store data from the input/output control unit 104 (in the step B13 in Fig. 16). However, according to the memory control method applied to the information processing equipment shown in Figs. 12 to 14, an address comparison detects whether the address of a process request selected by the priority circuit 115 is in the contention condition, or in the waiting condition on a request previously issued. Therefore in order to execute a high speed comparing operation to plural process requests in a response waiting state, the plural circuits (or the address comparing units 117) must be arranged to execute a parallel comparing operation. An increasing number of data processing units require many ports 112 to accept process requests. Hence there has been disadvantage in that the prior-art information processing equipment leads to an increased amount of hardware in need, an increased system constructing cost, and a complicated system construction. Moreover, there is an advantage in that since the acceptance port 112 must hold an address for comparison till all responses return to process requests (till the time t6 in Fig. 14), it is occupied for a long period of time, whereby the use efficiency and the processing rate are decreased. In the information processing system which performs the memory protection checking shown in Figs. 15 to 17, where the input/output control unit 104 issues a store request, together with a memory protection checking, the memory protection checking process and the retrieving process in the tag copying unit 116 are independently performed along the different flows, as shown in Fig. 17. The memory protection checking is performed along the first flow in which the priority circuit 115 selects the store request from the acceptance port 114. As a result, when accessing is allowed, the tag copying unit 116 performs the retrieving process along the flow which starts when the priority circuit 115 selects the store request from the acceptance port 114. Hence, the tag copying unit 116 cannot be retrieved till the result of the memory protection checking is known, whereby the memory protection key storing unit 212 takes much time to perform the key reading in the memory protection checking operation. Particularly, when the retrieval result from the tag copying unit 116 is a hit, the move-out is issued very slowly. This means that the use efficiency is very poor because the memory protection checking rarely inhibits an access operation. The acceptance port 114 once stores and holds a store request from the input/output control unit 104 till at least the result of the memory protection checking is known. Moreover, if the memory protection checking shows an allowable access, the store request is maintained till the tag copying unit 116 starts the retrieval process flow. That is, there is a disadvantage in that the acceptance port 114 cannot be released till the memory protection checking at least is ended. Hence, the following request cannot be received for a long time, whereby the use efficiency and the high speed process are degraded. The present invention may overcome the above mentioned problems. An embodiment of the present invention may provide a memory control method which can reduce the amount of hardware and improve the port use efficiency, thus reducing system constructing costs and improving processing speed. A further embodiment may provide a memory control device which can reduce the amount of hardware and improve the port use efficiency, again reducing the system constructing costs and improving processing speed. According to the present invention as defined in appended claims 1 and 7, the above advantages may be achieved basically by applying the features laid down in said independent claims. Further enhancements are provided by the dependent claims. The memory control method or the memory control device can set a process request showing flag in the tag copying unit, whereby whether a block including a process request address exists in the buffer memory unit, and whether the block is being processed currently, are concurrently obtained by retrieving only the tag copying unit. This feature allows the address comparing circuit to be omitted, thus reducing the system constructing cost. When the input/output control unit executes a store request to the memory unit, together with a memory protective checking, the referencing process to the store request of the tag copying unit may be performed in synchronism with the memory protective checking of the memory protective deciding means. Thus, where the memory protective checking cannot inhibit an accessing or a hit or erroneous hit is found in the tag copying unit, a high speed storing operation into the storage unit can be established. Moreover, this feature enables a large processing speed, a high port-use efficiency, and a large system throughput. For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, purely by way of example, to the accompanying drawings, in which:- Fig. 1 is a block diagram showing an aspect of the present invention; Fig. 2 is a block diagram showing an aspect claimed in divisional application EP-A-903 669; Fig. 3 is a diagram showing the first embodiment according to the present invention; Fig. 4 is a diagram showing the outline of an information processing system according to the first embodiment of the present invention; Fig. 6 is a diagram showing the entry configuration of the second tag unit according to the first embodiment of the present invention; Fig. 6 is a flowchart used for explaining the operation of the information processing device according to the first embodiment of the present invention; Fig. 7 is a time chart used for explaining the operation of the first embodiment according to the present invention; Fig. 8 is a functional diagram showing the second embodiment according to the present invention; Fig. 9 is a block diagram showing the detail configuration of the memory control unit according to the second embodiment of the present invention; Fig. 10 is a flowchart used for explaining the operation of the second embodiment according to the present invention; Fig. 11 is time chart used for explaining the operation of the second embodiment according to the present invention; Fig. 12 is a block diagram showing a conventional information processing system Fig. 13 is a flow chart used for explaining the operation of a conventional information system; Fig. 14 is a flow chart used for explaining the operation of a conventional information system; Fig. 15 is a block diagram showing a conventional information processing system; Fig. 16 is a flow chart used for explaining the operation of a conventional information processing system; and Fig. 17 is a time chart used for explaining the operation of a conventional information operation system. (a) An Aspect of the Invention: Fig. 1 is a block diagram showing an aspect of the present invention. In the information processing system shown in Fig. 1, numeral 1 represents a data storage unit and 2 represents at least one of data processing units. The data processing unit 2, which operates according to data stored in the storage unit 1, includes a buffer memory unit 7. The buffer memory unit 7 includes a data region 3 that holds a piece of data stored in the memory unit 1 and a tag region 4 that holds tag information including the address of data stored in the data region 3. The memory control unit 13 controls a data transfer between the memory unit 1 and the buffer memory unit 7 on a store-in basis. The memory control unit 13 includes a tag copying unit 5, a port 6, and a process command issuing means 8. The tag copying unit 5 holds a part or all of copies in the tag region 4 arranged in the buffer memory unit 7. The port 6 holds a process request from the data processing unit 2 or an external process request. The process command issuing means 8 refers the tag copying unit 5 and then issues a predetermined process command to the buffer memory unit 7 sent to the data processing unit 2 according to a process request held in the port 6. A bit 9 is arranged in the tag copying unit 5 to set a flag showing a process under request to the buffer memory unit 7. The process command issuing means 8 includes flag setting means 10 that issues a predetermined process command to be sent to the buffer memory unit 7 to the data processing unit 2 and sets at the same time a flag showing a process under request to the bit 9 in the tag copying unit 5 corresponding to a predetermined process command. Moreover, with the buffer memory unit 7 including plural ways managed on a set-associative basis, the tag copying unit 5 has flag setting bits arranged respectively to plural ways. The process command issuing means 8 includes port releasing means which releases the port 5 which holds a process request causing an issuance of a predetermined process command at the same time when a predetermined process command sent to the buffer memory unit 7 is issued to the data processing unit 2; and flag resetting means which resets a flag of the tag copying unit 5 corresponding to the process completion report when the process completion report is received from the data processing unit 2 in response to a predetermined process command. The process command issuing means 8 can issue a predetermined process command to be sent to the buffer memory unit 7 to the data processing unit 2, on condition that all flags of the portion to be processed under a predetermined process command in the tag copying unit 5 are in a reset state. The next process of a process request starts on condition that the flag reset means resets all the flags set in the tag copying unit 5 at an issuance of a predetermined process command. The process command issuing means 8 includes a counter that sets the number of responses to be issued, as non-response number, from the data processing unit 2 according to the predetermined process command at the same time when a predetermined process command is issued to the buffer memory unit 7, and subtracting means that subtracts one from the non-response number in the counter every time when the data processing unit 2 receives a process completion report as a response to a predetermined process command. The next process of the process request can be started at the time when the counter counts non-response number of zero. According to the first and second aspects of the invention, the memory control unit 13 issues a predetermined request to the buffer memory unit 7 within the data processing unit 2 while it refers the tag copying unit 5 according to the process request held in the port 6, thus controlling the data holding state of the buffer memory unit 7 on a store-in basis. A predetermined process command to be sent to the buffer memory unit 7 is issued to the data processing unit 2 while a flag which shows being in a process request to a portion in the tag copying unit 5, the portion to be processed under the predetermined process command, is set to the bit 9 in the tag copying unit 5. Thus information on whether a block including a process request address exists in the block memory unit 7 as well as information on whether the block is now in a process request can be obtained simultaneously by retrieving the tag copying unit 5. Hence, the address comparing unit can be omitted because of no address comparison. The buffer memory unit 7, which has plural ways managed on a set-associative basis, sets a flag to the tag copying unit 5 in every way so that whether a process is being required in each way can be managed. Furthermore, since the port 6 does not need to hold the process request until a response completion, a predetermined process request is issued to the buffer memory unit 7 via the data processing unit 2 while the port releasing unit can release the port 6 which holds a process request causing an issuance of the predetermined command. When the flag resetting means receives a process completion report from the data processing unit 2 in response to a predetermined process command, it resets the flag of the tag copying unit 5 corresponding to the process completion report. The process command issuing means 8 issues a predetermined process command to the buffer memory unit 7, on condition that all the flags of the portions corresponding to the predetermined process command in the tag copying unit 5 are in a reset state. The next process of the process request starts, on condition that the flag resetting means has reset all the flags set in the tag copying unit 5 at an issuing time of the predetermined process request, in response to a process completion report. Moreover, a counter sets the number of responses, as non-response number, to be sent from the data processing unit 2 in response to a predetermined process command at the same time when the process command issuing means issues a predetermined process command to the buffer memory unit 7. The subtracting means subtracts from the non-response number counted by the counter every time the process command issuing means receives a process request in response to a predetermined process request. When the non-response number reaches zero, the process command issuing means controls to start the next process of the process request. Hence the next process can be immediately started according to the condition of the response from the data processing unit 2. According to the memory control method or the memory control device according to the present invention, since a flag showing being under a process request can be set in the tag copying unit 5, both the presence or absence of a process request address including block in the buffer memory unit 7 as well as the current process condition of a block can be grasped by retrieving only the tag copying unit 5. Hence there is an advantage in that the address comparison can be omitted, whereby the system constructing cost can be reduced. According to the memory control method or the memory control device, a predetermined process request to be sent to the buffer memory unit 7 is issued to the data processing unit 2 while the port which holds the process request causing the issuance of the predetermined process command can be released. Hence the address holding operation is not needed till the data processing unit 2 completes the response operation. Hence the improved port-use efficiency can increase the throughput without increasing the number of ports. Hence there is an advantage in that the amount of hardware can be reduced so that the system constructing cost can be largely decreased. Furthermore, according to the memory control method or the memory control device, the next process can be started according to the response condition to a process request, whereby the throughput can be realized advantageously. Fig. 2 is a block diagram showing an aspect claimed in divisional application E-A-903 669. Referring to Fig. 2, the information processing system includes a storage unit 11 for storing data, at least one of data processing units 2 that operates according to the data from the storage unit 11, an input/output control unit 15 that issues a store request to the storage unit 11, together with a memory protection checking command, and a memory control unit 14. Each data processing unit 12 includes a buffer memory unit 18 which consists of a data region 16 which holds a piece of data stored in the storage unit 11, and a tag region 17 which holds tag information including the address of data held in the data region 16. The memory control unit 14 includes a tag copying unit 19 and a port 20, and memory protection deciding means 21. The tag copying unit 19 holds a part or all of the copy of the tag region 17 arranged in the buffer memory unit 18. The port 20 holds a process request issued from the data processing unit 12 or the input/output control unit 15. The memory protection deciding means 21 performs a memory protection checking operation when it receives a store request associated with a memory protection checking command from the input/output control unit 15, to the memory unit 11. The memory control unit 14 issues a predetermined process request sent to the buffer memory unit 18 to the data processing unit 12, based on the comparison result from the tag copying unit 18 in response to the process request held in the port 20. The memory control unit 14 controls the data transfer between the storage unit 11 and the buffer memory control unit 18 on a store-in basis, and allows a store request to be transferred from the input/output control unit 15 to the storage unit 11, according to the result of the memory protection checking from the memory protection deciding means 20. As claimed in divisional application EP-A-903 669, when the input/output control unit 15 outputs a store request associated with a memory protection checking to be sent to the storage unit 11 to the memory control unit 14, the tag copying unit 19 performs a referencing process, in synchronism with the memory protection checking operation of the memory protection deciding unit 21. The memory control unit 14 issues a predetermined process command to the buffer memory unit 18 arranged in the data processing unit 12, based on the reference result from the tag copying unit 19 in response to the process request held in the port 20. The memory control unit 14 also controls the data holding state of the buffer memory unit 18 on a store-in basis and decides whether a store request is issued from the input/output deciding means 21 to the storage unit 11, based on the result of the memory protection checking operation from the memory protection deciding means 21. Where the input/output control unit 15 issues a store request to be sent to the storage unit 11 to the memory control unit 14, the store request being associated with a memory protection checking command, the referencing process of the tag copying unit 19 is performed in synchronism with the memory protection checking operation of the memory protection deciding means 21. Hence the process time during which the memory protection checking approves accessing (a store request) can be shortened. According to the memory control method, when the input/output control unit 15 issues a store request to the storage unit 11, together with a memory protection checking request, the referencing process of the tag copying unit 19 on the store request is performed in synchronism with the memory protection checking operation of the memory protection deciding means 21. Hence, where the memory protection checking operation does not inhibit accessing, a hit or erroneous hit is found in the tag copying unit 19, the storage unit 11 can perform a high speed storing operation, whereby the use efficiency of the port can be improved. Hence there is an advantage in that the above-mentioned procedure contributes largely to an improved system throughput. (b) Explanation of First Embodiment: An embodiment of the present invention will be explained below with reference to the attached drawings. Fig. 3 is a block diagram showing the first embodiment according to the present invention. Referring to Fig. 3, the information processing system includes a main storage unit (MSU) 101, two data processing units (central processing units (CPUs)) 106 and 107, and an input/output control unit (IOP) 104. The above elements have functions similarly to the corresponding elements shown in Fig. 12. The main storage unit 101 stores data. The data processing units 106 and 107 can execute concurrently a parallel data operating process. The data processing unit 106 includes a data region that holds a piece of data stored in the main storage unit 101 and a tag region 109 that holds tag information holding tag information with the address of data held in the data region 108. The data processing unit 107 includes a data region that holds a piece of data stored in the main storage unit 101 and a tag region 111 that holds tag information holding tag information with the address of data held in the data region 110. The buffer memory unit 106 in the data processing unit 102 is managed, for example, on a 4-way set-associative basis. The buffer memory unit 107 in the data processing unit 103 is managed, for example, on a 4-way set-associative basis. Furthermore, the input/output control unit 104 outputs a process request (process command) to be issued to the external processing units 102 and 103 to the memory control unit 31 (to be described later). Numeral 31 represents a memory control unit (MCU) that controls the data transfer between the main storage unit 101 and the buffer memory unit 106 or 107 on a store-in basis. Like the memory control unit 105 shown in Fig. 13, the memory control unit 31 includes acceptance ports 112 to 114 and a priority circuit 115. The acceptance port 112 stores an external process command input from the data processing unit 102. The acceptance port 113 stores an external process command input from the data processing unit 103. The acceptance port 114 stores an external process command input from the input/output control unit 104. The priority circuit 115 outputs selectively any one of the processing commands from the acceptance ports 112 to 114. Numeral 32 represents a second tag region. The second tag regions (tag copying units) 32 hold a copy of a part or all of the tag region 109 in the buffer memory unit 106 and a copy of a part or all of the tag region 111 in the buffer memory unit 107, respectively. For example, where the buffer control units 106 and 107 includes 4 ways managed on a set-associative basis, flag setting bits (refer to numeral 41 in Figs. 4 and 5) are respectively arranged to four ways in the second tag region 32. Numeral 33 represents order issuing means (or process command issuing means). The order issuing means 33 references the second tag region 32 in response to the tag retrieval result reporting signal 32-1, according to a process command held in each of the acceptance ports 112 to 114, and then issues a predetermined process command (order) 33-1 to be sent respectively to the buffer memory units 106 and 107, to the data processing units 102 and 103. As shown in Figs. 4 and 5, a bit 41 showing being under a process request to the buffer memory units 106 and 107 is set to each of the entries in the second tag region 32 (to "1" at a flag setting time). The order issuing unit 33 also includes a flag setting function unit (flag setting means) 33A which issues a process request to the buffer memory unit 106 or 107 to the corresponding data processing unit 102 or 103 while it outputs a flag setting control signal 33-2 to the second tag region 32, whereby a flag "1" showing under a process request is set to the bit 41 of the portion (entry) of interest in the second tag region 32. The order issuing unit 33 includes a port releasing unit (port releasing means) 33B that outputs the port reset signal 33-3, together with the flag setting control signal 33-2, thus releasing one of the ports 112 to 114 holding a process command. The entry of each of the second tag regions 32, as shown in Fig. 5, includes a comparison address portion 42 to be compared and a control bit 43 such as valid and exclusive, in addition to the flag 41. Numeral 37 represents a responding circuit (flag resetting means). When the responding circuit 37 receives the response 102-1 from the data processing unit 102 and the response 103-1 from the data processing unit 103 according to the process command already processed in the order issuing unit 33, it outputs a flag reset signal 37-1 to the second flag unit 32. Thus the flag of the way of interest is reset while the process completion report 37-2 is output to the counter subtracting circuit 38 (to be described later). The order issuing unit 33 issues the buffer memory unit 106 or 107 to the corresponding data processing unit 102 or 103, on condition that all the flags of the portions corresponding to a predetermined process command in the second tag region 32 have been reset. The memory control unit 31 starts the next process of a process request, on condition that the response processing circuit 37 has reset all flags set to the second tag region 32 when the previous process command is issued. Numeral 35 represents a response waiting control port (BCP). The response waiting control port 35 includes a counter 36 that sets the number of responses, as non-response number, to be issued from the data processing unit 102 or 103, or a process command issuing source, corresponding to a process command. Numeral 38 represents a counter subtracting circuit (subtracting means). The counter subtracting circuit 38 outputs a signal 38-1 to the response waiting control port 35 every time the process completion report 37-2 as a response signal from the data processing unit 102 or 103 is received from the response processing circuit 37, thus subtracting the number of responses not counted by the counter 36. The operation of the above configuration according to the first embodiment of the present invention will be described below with reference to the flow chart shown in Fig. 6 and the time chart shown in Fig. 7. When the data processing unit 102, for example, outputs a process command 102-2 (refer to Fig. 3) (refer to the step C1 in Fig. 6 and the duration t11 in Fig. 7), the memory control unit 31 stores the process command 102-2 in the acceptance port 112 (refer to the step C2 in Fig. 6 and the duration t12 in Fig. 7). When the priority circuit 115 selects a process request 102-2 (refer to YES route in the step C3 in Fig. 6 and the duration t13 in Fig. 7), it retrieves the second tag region 32 using the address corresponding to the process command (refer to the step C4 in Fig. 6 and the duration t14 in Fig. 7) to report the order issuing unit 33 of the retrieval result as a tag retrieval result reporting signal 32-1. The tag retrieval result reporting signal 32-1 includes a signal showing whether a process command address including block exists in the buffer memory units 106 and 107 and a signal showing whether a block storing way is in a process request waiting state (a signal corresponding to a flag set in the bit 41). When the process command address including block does not exist in the buffer memory units 10 and 107, a reading request is issued to the main storage unit 101 (or from the NO route in the step C5 to the step C13 in the Fig. 6) so that the acceptance port 112 is released (in the step C14 in Fig. 6). Then the next process of the process response waiting request is started (the step C12 in Fig. 6). With a process command address including block stored in the buffer memory unit 106 or 107 (refer to YES route from the step C5 in Fig. 6) and a response waiting flag in the bit 41 being in ON state, where the address corresponding to the process command is in a process request waiting state, an order is not issued so that the process command is canceled. Since the port reset signal 33-3 is not issued, the content of the port 112 is not reset. Hence till the priority circuit 115 selects again the process command, the acceptance port 112 queues by (the step C15 in Fig. 6). With a process command address including block existing in the buffer memory unit 101 or 107, a response waiting flag 41 in an OFF state, and the address corresponding to the process command being not in a process request waiting state (NO route from the step C6 in Fig. 6), the order issuing unit 33 selects the corresponding buffer memory unit 106 or 107 to issue the order 33-1 (refer to the duration t15 in Fig. 7). At the same time, the flag setting unit 33A within the order issuing unit 33 outputs the flag setting control signal 33-2 to set a flag "1" showing being under a process request to the bit 41 of a portion of interest in the second tag region 32. The port releasing unit 33B within the order issuing unit 33 issues the port reset signal 33-3 to release the port 112 holding the process request, thus setting the number of issued orders to the counter 36 within the response waiting control port 35 to set the order number information to the waiting control port 35 (step C7 in Fig. 6). The acceptance port 112 released can accept a new request. Thereafter, when the memory control unit 31 receives the responses 102-1 and 103-1 with respect to an order (YES route from the step C8 in Fig. 6), the response processing circuit 37 decides that the response has come from the data processing unit 102 or 103 to output the flag reset signal 37-1 to the second tag region 32, thus resetting a flag of a way of interest (in the step C9 in Fig. 6) while it outputs the process completion report 37-2 as a counter subtraction command to the counter subtracting circuit 38. The counter subtracting circuit 38 subtracts the count value of the counter 36 (refer to the numeral 38-1 in Fig. 3 and the step C10 in Fig. 6). The counter 36 counting "0" (refer to YES route in the step C11 in Fig. 6 and the duration t16 in Fig. 7) means the responses to all orders issued on a process command. Then the flow goes to the step C12 to continue the process in accordance with the content held in the response waiting control port 35. According to the first embodiment of the present invention, the flag setting unit 33A can set a flag showing a process request to the bit 41 in the second tag region 32. Whether a process request address including block exists in the buffer memory units 106 or 107 and whether the block now is being processed can be recognized concurrently by retrieving the second tag unit 32, whereby an exclusive address comparing circuit is not needed. Hence there is an advantage in that the system constructing cost can be reduced. A predetermined process request to the buffer memory unit 106 or 107 is issued to the data processing unit 102 or 103 while the port releasing unit 33B can release the port 114 which holds a process request causing the predetermined process command. It is unnecessary to hold the address till the data processing unit 102 and 103 issue responses. Hence the use efficiency of the acceptance ports 112 to 114 can be improved. The improved throughput can be realized without increasing the number of ports. Hence there is an advantage in that the amount of hardware as well as the system constructing cost can be largely reduced. The next process of the process request can be started according to the response state to a process request. Hence the sharply increased throughput can be realized. According to the present embodiment, two data processing units and the buffer memory unit with four ways are used. However, according to the present invention, the data processing units and the number of ways of the buffer memory unit should not be limited to a limited number, respectively. The data processing units and the buffer memory unit can be applied in a desired number, respectively. (c) Explanation of Second Embodiment: Fig. 8 is a block diagram showing the second embodiment according to the present invention. Referring to Fig. 8, the information processing system includes two data processing units (CPUs) 102 and 103, an input/output control unit (IOP) 104, a memory control unit (MCU) 51, and a main storage unit (MSU) 101. A memory protection checking (where a store request is made to the data unit smaller than the minimum move-out unit of the buffer memory unit 106 or 107 (hereinafter the process request is referred to as a request A)) can be performed to a store request with a memory protection check which is issued from the input/output control unit 104 to the main storage unit 101 via the memory control unit 51. The main storage unit 101 and two data processing units 102 and 103, and the input/output control unit 104 have functions in a manner similar to those in the first embodiment. The data processing unit 102 includes a buffer memory unit 106 which consists of the data region 108 and the tag region 109. The data processing unit 103 includes a buffer memory unit 107 which consists of the data region 110 and the tag region 111. In the memory control unit 51, the second tag region (tag copying unit) 52 holds a part or all of a copy of the tag region 109 in the buffer memory unit 106 and a part or all of a copy of the tag region 111 in the buffer memory unit 107. The second tag region 52-1 holds a copy of the tag region 109 and the second tag region 52-2 holds a copy of the tag region 111. Numeral 53 represents a memory protection key storing unit (KSU). The memory protection key storing unit 53 stores data which is used to execute a memory protection checking in response to a process request from the input/output unit 104. According to the present embodiment, the memory control unit 51 has the detail configuration shown in Fig. 9. The memory control unit 51 includes the second tag region 52 described above, the memory protection key storing unit 53 described above, acceptance ports 112 to 114 being functionally similar to that in the memory control unit 205 in Fig. 15, a priority circuit 115, a queue 216, and a priority circuit 217. A predetermined process command such as a move-out order to be sent to the buffer memory unit 106 is issued to the data processing unit 102, together with the associated order number, according to process requests respectively held the acceptance ports 112 to 114 and based on the reference result from the second tag region 52. A predetermined process command such as a move-out order to be sent to the buffer memory unit 107 is issued to the data processing unit 103, together with the associated order number, according to process requests respectively held in the acceptance ports 112 to 114 and based on the reference result from the second tag region 52. In addition, as described later with reference to Figs. 10 and 11, when the acceptance port 114 holds the request A from the input/output control unit 104 is held by the acceptance port 114 and then selected by the priority circuit 115, the retrieving process (referencing process) of the second tag region 52 can be performed in synchronism with the memory protection checking of the memory protection checking circuit 54, thus releasing the acceptance port 114. The address and the key-checking key in the data block to be subjected to the request A move together with an order issued from the memory control unit 51 or a response issued from the data processing unit 102 or 103 corresponding to the order. The memory control unit 51 also includes the memory protection checking circuit (KCHK) 54, or memory protection deciding means, and the memory protection check information holding unit 56. In order to perform a memory protection checking operation, the memory protection checking circuit 54 compares the key corresponding to the address of the request A obtained by accessing the memory protection key storing unit 53 with the key-checking key associated with the request A, thus checking whether the requested address is accessible. The memory protection checking information holding unit 56 holds information showing whether an order issuance causing request is accompanied by a memory protection checking (or showing the presence or absence of the request A), in order of the order number of an order attached by the memory control unit 51. When the acceptance port 112 or 113 outputs a response corresponding to the order, the memory protection checking information holding unit 56 references the order number attached to the response. If it is proved that the response has been made to the request A associated with the memory protection checking, the memory protection checking circuit 54 reads and accesses a key corresponding to the address associated with the response out of the memory protection key storing unit 53, and then compares the readout key with the key-checking key associated with the response, thus performing a memory protection checking operation. The information showing whether an order issuance causing request is associated with a memory protection checking is held in order of the order numbers by the memory protection checking information holding unit 56. However, the information may be associated with the order or the response to the order. In this case, the order number setting operation and the memory protection checking information holding unit 56 can be omitted. In the memory control unit 51, like the process of the request A, when the input/output control unit 104 issues a store request to the main storage unit 101, associated with a memory protection checking command, the acceptance port 114 holds the store request. The operation of the above-configuration will be described below with reference to the flowchart shown in Fig. 10 and the time chart shown in Fig. 11. The input/output control unit 104, for example, issues the request A (refer to the step D1 in Fig. 10 and the duration u1 in Fig. 11) to store the acceptance port 114 in the memory control unit 51 (refer to the step D2 in Fig. 10 and the duration u2 in Fig. 11). When the priority circuit 115 participates the priority selection (refer to the step D3 in Fig. 10 and the duration u3 in Fig. 11) and then selects the process request (request A) issued from the input/output control unit 104 to the memory control unit 51, together with a memory protection checking operation, the acceptance port 114 is released (step D4 in Fig. 10). With the flow started by the priority selection, the retrieving process of the second tag region 52 (refer to the step D5 in Fig. 10 and the duration u4 in Fig. 11) is performed in synchronism with an access to the memory protection key storing unit 53 (the step D6 in Fig. 10). The second tag region 52 is retrieved immediately. The access to the memory protection key storing unit 53 takes a relatively long processing time, compared with the retrieval process of the second tag region 52. If the second tag region 52 of the access related to the request A is erroneously retrieved (NO route in the step D5 in Fig. 10), the access to the memory protection key storing unit 53 becomes valid (the step D8 in Fig. 10) so that the memory protection checking circuit 54 performs a memory protection checking (the step D9 in Fig. 10). Where the memory protection checking circuit 54 compares the key-checking key associated with the request A with the key from the memory protection key storing unit 53 and then proves the accessible state (YES route in the step D9 in Fig. 10), the main storage unit 101 stores the store data from the input/output control unit 104 (in the step D10 shown in Fig. 10). On the other hand, where the memory protection checking circuit 54 performs a memory protection checking and then proves an inaccessible state (NO route in the step D9 in Fig. 10), the reset A is canceled (the step D11 in Fig. 10). If retrieving the second tag region 52 finds the address related to the request A (YES route in the step D7 in Fig. 10), it is regarded that an access to the memory protection key storing unit 53 is invalid (the step D8 in Fig. 10). In actual, the memory protection checking circuit 54 performs a key checking operation, according to the access result from the memory protection keying unit 53 (the step D9 in Fig. 10), and then invalidates the access by neglecting the checking result. The memory control unit 51 issues a move-out order to the data processing unit 102 or 103 which has the latest data in the address corresponding to the request A (refer to the step D12 in Fig. 10 and the duration u6 in Fig. 11). An order number is attached to the move-out order transferred to the data processing unit 102 or 103. The memory protection check information holding unit 56 holds the instruction by which a memory protection checking is performed to the order number. When the data processing unit 102 or 103 receives the move-out order, it invalidates the tag region 109 or 111 of the corresponding data and then issues the response to the memory control unit 51 to move out the corresponding data (the step D13 in Fig. 10 and the duration u7 in Fig. 11). When the acceptance port 112 or 113 in the memory control unit 51 holds the response (refer to the duration u8 in Fig. 11) and the priority circuit 115 selects the same (refer to the step D14 in Fig. 10 and the duration u9 in Fig. 11), the memory protection checking information holding unit 56 is referenced (refer to the duration u16 in Fig. 11), it is decided whether it is instructed to subject the order number associated with the response to a memory protection checking. Where a memory protection checking is instructed, an access to the memory protection key storing unit 53 is made (refer to the step D16 in Fig. 10 and the duration u10 in Fig. 11) while a move-out data from the data processing unit 102 or 103 is stored into the main storage unit 101 via the queue 216 and the priority circuit 217 (refer to the step D15 in Fig. 10 and the duration u12 in Fig. 11). Where the memory protection checking circuit 54 compares the key-checking key associated with a response with a key from the memory protection key storing unit 53 (refer to the duration u11 in Fig. 11) to permit accessing (YES route in the step D17 in Fig. 10), the move-out data from the data processing unit 102 or 103 is stored in the main storage unit 101 in the step D15. Then the store data from the input/output control unit 104 is stored in the main storage unit 101 (the step D18 in Fig. 10). Where the memory protection checking of the memory protection checking circuit 54 results in no access permission (NO route in the step D17 in Fig. 10), the move-out data from the data processing unit 102 or 103 is stored in the main storage unit 101 in the step D15 but the request A is canceled (the step D19 in Fig. 10). Where it is decided that the tag region 52 has been retrieved rightly in the step D12, the memory protection checking information holding unit 56 corresponding to the order number may hold the result on the memory protection checked in the step D9, without invalidating the checking result of the memory protection checking unit 54. In this case, the key checking can be omitted in the step D17 in the second flow. Hence the key checking result can be obtained merely by referencing the order number associated with a response which is held in the memory protection checking information holding unit 56. According to the second embodiment, when the input/output control unit 104 requests the memory control unit 51 of a storing process to the main storage unit 101, together with a memory protective checking operation, retrieving the second tag region 52 in response to the store request is performed in synchronism with the memory protection checking process of the memory protection deciding means in the first process flow. Thus where the memory protection checking is not permitted because of an erroneous hit of the second tag region 52, the request can be immediately canceled. Where the memory protection checking is permitted because of an erroneous hit of the second tag region 52, the store request can be made from the input/output control unit 104 to the main storage unit 101 in the same process flow. When the second tag region 52 is hit, a move-out order is issued to the data processing unit 102 or 103, without waiting the result of a memory protection checking so that the result of the memory protection check is invalidated. Thus the memory protection checking process is resumed in the process flow responding to the order. Where the memory protection checking in the responding flow results in an access permission, the main storage unit 101 can store the move-out data from the data processing unit 102 or 103 and then stores data from the input/output control unit 104. In the case of no access permission, the main storage unit 101 stores the move-out data from the data processing unit 102 or 103, but the store request according to the request A is canceled. If the memory protection checking does not inhibit accessing or the second tag region 52 is hit or erroneously hit, data can be stored in the main storage unit 101 at high speed. Hence the processing speed can be improved remarkably. This large effect results from the memory protection checking which rarely inhibits accessing. Moreover, the acceptance port 114 which can be released in the first flow can improve the use efficiency, thus contributing largely to the improved system throughput. The present embodiment uses two data processing units. However, according to the present invention, the number in use of data processing units should not be limited to a specific value, but is applicable to a desired value.

Claims: A memory control method suitable for an information processing system including a memory unit (1), one or more data processing units (2) each of which operates based on data stored in said memory unit (1), a memory control unit (13) operable to control data transfer between said memory unit (1) and said data processing unit (2), and a buffer memory unit (7), said buffer memory unit (7) having a data region (3) which holds a piece of data stored in said memory unit (1) for each data processing unit (2) and a tag region (4) which holds tag information including the address of data stored in said data unit (3); said memory control unit (13) including a tag copying unit (5) that holds one or more pieces of copy information stored in said tag region (4) in said buffer memory unit (7), and a port (6) which holds a process request sent from each data processing unit (2) or an external process request; said memory control method including issuing a predetermined processing command sent to said buffer memory unit (7) from said memory control unit (13) to said data processing unit (2), according to a process request held by said port (6) and with reference to said tag copying unit (5); and controlling the data holding state of said buffer memory unit (7) on a store-in basis; said memory control method being characterized by the steps of: issuing said predetermined processing command sent to said buffer memory unit (7) in said data processing unit (2); and setting at the same time a flag (9) held in said tag copying unit (5) showing a process under request for said predetermined processing command, and upon process completion, resetting said flag (9) in said tag copying unit (5) when said process completion report is received from said data processing unit (2), in response to said predetermined process command. A memory control method suitable for an information processing system according to claim 1, further comprising the step of: setting said flag in said tag copying unit (5) in a plurality of ways, with said buffer memory unit (7) having the plurality of ways managed on a set-associative basis. A memory control method suitable for an information processing system according to claim 1 or 2, further comprising the steps of: issuing said predetermined process command to be sent to said buffer memory unit (7) in said data processing unit (2); and releasing at the same time said port (6) holding said process request causing an issuance of said predetermined process command. A memory control method suitable for an information processing system according to any one of claims 1 to 3; further comprising the step of: issuing said predetermined process command to be sent to said buffer memory unit (7) in said data processing unit (2), on condition that all flags to be subjected to said predetermined process command in said tag copying unit (5) have been reset. A memory control method suitable for an information processing system according to any one of claims 1 to 4, further comprising the step of: starting the next process of said process request, on condition that all flags set in said tag copying unit (5) at an issuance of said predetermined process command have been reset in response to said process completion report. A memory control method suitable for an information processing system according to any one of claims 1 to 4, further comprising the steps of: issuing said predetermined process command to said buffer memory unit (7) while the number of responses to be sent from said data processing unit (2) is set in response to said predetermined process command; subtracting one from said number every time a process completion report is received from said data processing unit (2) as a response to said predetermined process command; and starting the next process of said process request when said number becomes zero. A memory control device suitable for an information processing system including a memory unit (1), one or more data processing units (2) each operating based on data stored in said memory unit (1), and a buffer memory unit (7), said buffer memory unit (7) having a data region (3) which holds a piece of data stored in said memory unit (1) for each of the said one or more data processing units (2) and a tag region (4) which holds tag information including the address of data stored in said data region (3); said memory control device (13) comprising: a tag copying unit (5) that holds one or more pieces of copy information stored in said tag unit (4) which is in said buffer memory unit (7); a port (6) that holds a process request sent from said data processing unit (2) or an external process request; and being characterized by: process command issuing means (8) in said memory control unit for issuing a predetermined processing command to be sent to said buffer memory unit (7) in said data processing unit (2) according to a process request held by said port and with reference to said tag copying unit; whereby the data transfer between said memory unit (1) and said buffer memory unit (7) is controlled on a store-in basis; said tag copying unit (5) including a bit (9) with which a flag is set showing a process under request to said buffer memory unit (7) ; said process command issuing means (8) including flag setting means (10) which, at the same time when said command issuing means (8) issues said predetermined processing command to be sent to said buffer memory unit (7) in said data processing unit (2), sets the flag (9) to show the data process under request for said predetermined processing command, and flag resetting means for resetting said flag (9) corresponding to a process completion report in said tag copying means (5) when said process completion report is received from said data processing unit (2) in response to said predetermined process command. A memory control device suitable for an information processing system according to claim 7, wherein said buffer memory unit (7) includes a plurality of ways which are managed on a set-associative basis, and wherein said tag copying unit (5) sets the flag (9) in accordance with the said plurality of ways. A memory control device suitable for an information processing system according to claim 7 or 8, wherein said process command issuing means (8) comprises port releasing means for issuing said predetermined process command to be sent to said buffer memory unit (7) of said data processing unit (2) and at the same time for releasing said port (6) which holds said process request causing an issuance of said predetermined process command. A memory control device suitable for an information processing system according to any one of claims 7 to 9, wherein said process command issuing means (8) issues said predetermined process command to be sent to said buffer memory unit (7) of said data processing unit (2), on condition that all flags of portions to be processed under said predetermined process command in said tag copying unit (5) are reset. A memory control device suitable for an information processing system according to claim 10, wherein the next process of said process request is started on condition that said flag resetting means resets all flags which are set in said tag copying unit (5) at an issuance of said predetermined process command. A memory control device suitable for an information processing system according to any one of claims 7 to 11, further comprising: a counter for holding the number of responses to be sent from said data processing unit (2), in response to said predetermined process command, at the same time as said process command issuing means (8) issues said predetermined process command to said buffer memory unit (7); and subtracting means for subtracting one from said number held by said counter every time a process completion report is received from said data processing unit (2) as a response to said predetermined process command; whereby the next process f said process request is started at the time when said number held by said counter is equal to zero.

Inventors: AOKI NAOZUMI, KITANO YUKIHIKO, NAGATO KENRO, SUGINO MASATOSHI, AOKI, NAOZUMI, KITANO, YUKIHIKO, NAGATO, KENRO, SUGINO, MASATOSHI, AOKI, NAOZUMI, C/O FUJITSU LIMITED, KITANO, YUKIHIKO, C/O FUJITSU LIMITED, NAGATO, KENRO, C/O FUJITSU LIMITED, SUGINO, MASATOSHI, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1995
Main classification: G06F12
IPC codes: G06F15, G06F12