Capacitance forming method

Abstract: A capacitance forming method for forming capacitances corresponding to a plurality of constant numbers within a large scale integrated circuit (LSI) comprises steps of defining a unit capacitance with a predetermined shape, defining an arrangement of a plurality of the unit capacitances of a number necessary for total capacity of capacitances to be formed in two dimension in an area of the LSI, selecting the unit capacitances of a number corresponding to the maximal capacity among capacities of the capacitances to be formed so that the selected unit capacitances are equivalently dispersed over the area, and successively selecting other of the capacitances than the capacitance of the maximal capacity in the order of capacities, and selecting the unit capacitances of a number corresponding to a capacity of each the capacitance selected so that the selected unit capacitances are equivalently dispersed over an area of the rest of the unit capacitances which have not selected yet.

Description: The present invention relates to a capacitance forming method, with a plurality of unit capacitances according to the preamble part of claim 1. A capacitance forming method is proposed a shown in Figure 8, wherein a plurality of predetermined unit capacitances are aligned, then some unit capacitances are selected for one capacitance component so that there is no adjacent pairs of the unit capacitances selected for the one capacitance component. The deviation of the capacitances is minimized in order to compensate the relative accuracy of capacities of capacitance components. By the proposed method, capacitance components consisting of a plurality of unit capacitances are of good relative accuracy when the components have capacities nearly equal to one another. However, when capacities are much different in such case that weights of digits of binary number are represented by the capacitance components. In the process of diffusion of chemical vapor during the forming of the unit capacitances, inequality of forming is caused due to flowing direction in the peripheral area of the alignment area of unit capacitances, and the relative accuracy becomes lower. JP-A-58103163 discloses a method for forming a capacitor element wherein dummy patterns are constructed in such a manner that they will be placed in a row on the circumferential part of the structure. At this location, the relative error of a weighted capacitor is less while the capacitor element occupies a small area. EP-A-0186239 discloses an integrated circuit comprising capacitances of different capacitance values having different numbers of basic capacitances connected in parallel between a first and second connection electrode. The circuit is comprised of a plurality of rows having the same number of basic capacitances and in different ones of these rows different numbers of basic capacitances form part of the said capacitances whereas all the remaining basic capacitances of the relevant rows are dummy capacitances. The present invention is invented so as to solve the conventional problems and to provide a capacitance method having the steps as set forth in claim 1. Figure 1 is a plan view of alignment of unit capacitances of the first embodiment according to the present invention, Figure 2 is a plan view of the second embodiment, Figure 3 is a plan view of the unit capacitances in the initial condition of the third embodiment, Figure 4 is a plan view of unit capacitances for the most significant and the secondly significant bit of binary number, Figure 5 is a plan view of a group newly defined after the condition in Figure 4, Figure 6 is a plan view of selection of unit capacitances for the third and fourth bits according to the order defined in Figure 5, Figure 7 is plan view showing a new order and selections of unit capacitances for fifth bit, the least significant bit and the reference capacitance according to the order defined after the selection of Figure 6, and Figure 8 is a circuit diagram showing unit capacitance arrangement proposed in the art. Hereinafter the embodiment of a capacitance forming method according to the present invention is described with referring to the attached drawings. Figure 1 is a plan view showing an arrangement of unit capacitances for obtaining a capacity ratio of 8:4:2:1:1, in the arrangement the unit capacitances are aligned in a matrix of 4 × 4 unit capacitances. Here, when a capacity of an unit capacitance is Cu, a capacity of a capacitance with the maximum capacity is defined as 8Cu and capacities of the following second capacitance are defined as 4Cu, 2Cu, Cu and Cu. In Figure 1, there are arranged the unit capacitances designated by references "a", "b", "c", "d" and "e". The reference "a" shows unit capacitances for a capacitance, or a capacitance component, of 8Cu (It is called the first capacitance.). The unit capacitances "b" are for a capacitance component of 4Cu (It is called the second capacitance.). The unit capacitances "c" are for a capacitance component of 2Cu (It is called the third capacitance.). The unit capacitances "d" are for a capacitance component of Cu (It s called the fourth capacitance.). The unit capacitances "e" are for a capacitance component of Cu (It is called the fifth or last capacitance.). The unit capacitances of the first capacitance are arranged in a checker flag. In other words, the capacitance component of the maximum capacity consists of unit capacitances arranged so that the unit capacitances are dispersed equivalently in the whole arrangement area without any adjacent pairs in the horizontal or vertical direction. Therefore, decentralization and mutual estrangement of unit capacitances are realized. Unit capacitances for the second capacitance component are positioned at four corners of a horizontal square with sides of three unit capacitances in good decentralization and estrangement similarly to the first capacitance component. For the third capacitance component, two unit capacitances are positioned at diagonal corners of a horizontal square with sides of three unit capacitances in the rest of the unit capacitances so as to be widely dispersed. There is one unit capacitance for each of fourth and fifth capacitances which are positioned at other diagonal corners than the corners of third capacitance component in the same square as that for the third capacitance. As mentioned above, even when capacitance components with large difference of capacity are formed, unit capacitances for the capacitance components are equivalent in the positioning condition, so the relative accuracy of a capacity is improved. Figure 2 is the second embodiment of an arrangement of unit capacitances for obtaining a capacity ratio of 16:8:4:2:1:1, and the unit capacitances are arranged in a matrix of 4 × 8 unit capacitances. Here, when a capacity of a unit capacitance is Cu, a capacity of an unit capacitance with the maximum capacity is defined as 16Cu, and capacities of the following capacitances are defined as 8Cu, 4Cu, 2Cu, Cu and Cu. In Figure 2, unit capacitances "a", "b", "c", "d", "e" and "f" are arranged, which are called the first, second, third, fourth, fifth and sixth capacitances, hereinafter. These capacitances are unit capacitances for capacitance components of 16Cu, 8Cu, 4Cu, 2Cu, the first Cu and the last Cu. Unit capacitances for the first capacitance are arranged in a checker flag, similar to the first embodiment. Unit capacitances for the second capacitance component are aligned along two horizontal lines on each of which four unit capacitances are positioned on every other unit capacitance position. The lines are departed by one unit capacitance position from each other. For the third capacitance component, four unit capacitances are positioned at corners of a horizontal rectangle with vertical sides of three unit capacitances and horizontal sides of five unit capacitances in the rest of the unit capacitances so as to be widely dispersed. The fourth capacitance consists of two unit capacitances diagonally positioned on the corner of a rectangle similar to the rectangle of the third capacitance. There is one unit capacitance for each of fourth and fifth capacitances which are positioned at other diagonal corners than the corners of fourth capacitance component in the same rectangle as that for the fourth capacitance. In this embodiment, the good decentralization and mutual estrangement are realized, also, for larger difference of ratio of 16:8:4:2:1:1 than that of the first embodiment. Hereinafter the third embodiment of capacitance forming method according to the present invention is described with referring to the attached drawings. Figure 3 is a plan view of an arrangement of unit capacitances for obtaining a capacity ratio of 32:16:8:4:2:1:1 in squares area of a 8 × 8 unit capacitances. Here, when a capacity of an unit capacitance is Cu, a capacity of an unit capacitance is Cu, a capacity of a capacitance with the maximum capacity is defined as 32Cu, and the capacitances following to the maximum are defined as 16Cu, 8Cu, 4Cu, 2Cu and Cu. Furthermore, a capacity is defined as a reference capacity of Cu. In order to designate unit capacitances for capacity definition, following steps are performed: [STEP 1] Figure 3 shows an arrangement of unit capacitances with coordinates 'i' of the horizontal direction and 'j' of the vertical direction 'j'. When a group G of all unit capacitances is defined as G = {xij}, four subsets can be defined, that is, g1={xij | i = even, j = even}, g2={xij | i = even, j = odd}, g3={xij | i =odd, j = even}, g4={xij | i = odd, odd}. Furthermore, a sum of subsets g1 and g4 is defined as g5, and a sum of subsets g2 and g3 is defined as g6. The subset g5 or g6 is designated as unit capacitances for the capacitance component of most significant bit (MSB). Figure 4 shows an arrangement of g5, and unit capacitances of MSB are designated by a reference 'a'. This arrangement can be called 'zigzag arrangement'. [STEP 2] In step 2, unit capacitances for the second bit from MSB is selected. Since g5 is selected in step 1, unit capacitances included in g6 are selected in step 2. The subset g2 or g3 is selected. Figure 4 shows a condition that g2 is selected and the selected unit capacitance is shown by a reference 'b'. If g6 were selected, gl or g4 would be selected. [STEP 3] In step 3, unit capacitances are shown without references which are not selected in the step 2, as shown in Figure 4. Then, new coordinates of arrangement is given to the non-selected, and processes are repeated like step 1. [STEP 4] Figure 5 shows new coordinates "i" (horizontal direction) and "j" (vertical direction) for non-selected 16 unit capacitances, and subset mentioned above is defined (selected unit capacitance is shown by x.). The total set G = {xij} , and subsets g1={xij | i even, j = even}, g2={xij | i = even, j = odd}, g3={xij | i =odd, j = even}, g4={xij | i = odd, odd}, g5=g1 ∪ g4 and g6=g2 ∪ g3, as shown in figure 3. Similar to the step 1, g5 or g6 is selected to be the third bit from MSB, which is the most significant bit among the bits undefined. Figure 6 shows an arrangement when g5 is selected, unit capacitances for the third bit is shown by 'a'. In Figure 6, selected unit capacitances are shown by ×. [STEP 5] Similar to the step 2, g2 is selected to be the the forth bit. In Figure 6, four unit capacitances for the forth bit is shown by a refernce 'b'. [STEP 6) Similar to the step 3, new coordinates are given for non-selected unit capacitances, as shown in figure 7. [STEP 7] Four unit capacitances are remained, here. Similar to the steps 1 and 4, new coordinates are defined, as follows: G = {x11, x12, x21, x22}, g1=(x22), g2={x21}, g3={x12}, g4={x11}, g5={x22,x11}, g6={x21,x12} (selected unit capacitances are shown by ×). The subset g5 is selected and two unit capacitances for the 5th bit are selected. [STEP 8] Similar to the 5, g2={x21} is selected as an unit capacitance for the sixth bit. Figure 7 shows the unit capacitances by a reference 'b'. [STEP 9) Non-selected unit capacitances exist as unit capacitances for a reference capacitance, then the total assignments are completed. As mentioned above, by applying the zigzag arrangement and rectangle arrangement of the unit capacitances one after another, unit capacitances for each capacitance are equally dispersed. Deviation of capacities due to positioning partiality is solved and high relative accuracy is obtained. The above steps are generalized by the following steps G1 to G3. [STEP G1] A subset of non-selected unit capacitances is defined as G = {xij}("i" and "j" are coordinates of horizontal and vertical directions), g1={xij | i = even, j = even}, g2={xij | i = even, j = odd}, g3={xij | i =odd, j = even}, g4={xij | i = odd, odd}, g5=g1 ∪ g4, and g6=g2 ∪ g3. The subset g5 or g6 is selected to be unit capacitances of MSB. [STEP G2] When g5 is selected in step 1, then g2 or g3 is selected to be unit capacitances for the highest bit among bits after the selection of unit capacitances for MSB. When g6 is selected, gl or g4 is selected. [STEP G3] When, in this stage, weights of LSB and the reference are not defined by the unit capacitances, the half of non-selected unit capacitances are assigned to LSB and the others are assigned to the reference. Otherwise, new coordinates are given to the all non-selected unit capacitances, such as {xij}, and the steps from G1 to G3 are repeated. In the case the total number of unit capacitance is relatively large, enough relative accuracy is obtained even if mentioned rules are not applied to LSB and the reference capacity. According to an experience, smaller than 10% of the total of 128 unit capacitances can be wired independently from the rule above without deteriorating the relative accuracy of capacities. When the total number is in the range of 256 with 10% unit capacitances out of rule, extremely high relative accuracy is guaranteed. It is advantageous that some capacitances are wired according to simplicity or efficiency than to the rule above with keeping accuracy in capacity.

Claims: A capacitance forming method for forming capacitance components representing weights of bits of a binary number within a large scale integrated circuit (LSI) comprising the steps of: defining a unit capacitance with a predetermined shape; defining a rectangle of a plurality of said unit capacitances with a number necessary to obtain a desired total capacity to be formed in a two dimensional area of said large scale integrated circuit; characterized by the following steps: STEP 1: defining coordinates (i,j) along both sides of said rectangle, a group of total unit capacitances as G = {xij} subsets of g1={xij | i : even, j : even}, g2={xij | i : even, j : odd}, g3={xij | i : odd, j : even} and g4= {xij | i : odd, j : odd}, and defining groups g5=g1 ∪ g4 and g6=g2 ∪ g3; STEP 2: selecting g5 or g6 as a group of unit capacitances for a capacitance component, representing the most significant bit among bits for which said unit capacitances have not yet been assigned; STEP 3: when g5 is selected, selecting g2 or g3 for the next most significant bit at this stage, otherwise selecting g1 or g4 for the next most significant bit at this stage; and STEP 4: when all other bits other than the least significant bit of said binary number are already defined by said unit capacitances, assigning the half of the rest of said unit capacitances not yet assigned to the least significant bit and the others to a reference capacitor, otherwise defining new coordinates (i,j) for the rest of said unit capacitances and return to said STEP 1.

Inventors: MOTOHASHI KAZUNORI, SHOU GUOLIANG, TAKATORI SUNAO, YAMAHOTO MAKOTO, MOTOHASHI, KAZUNORI, SHOU, GUOLIANG, TAKATORI, SUNAO, YAMAHOTO, MAKOTO, Motohashi, Kazunori, c/o Yozan Inc., Shou, Guoliang, c/o YOZAN Inc., TAKATORI, SUNAO, C/O YOZAN INC., Yamahoto, Makoto, c/o Yozan Inc.
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1995
Main classification: H01L27
IPC codes: H01L27