Semiconductor memory device

Abstract: A semiconductor device is constituted by a booster circuit, memory cell arrays (MCA1, MCA2), a sense amplifier circuit (S/A), transmission gate circuits (Q4, Q5; Q9, Q10), equalizing circuits (Q1, Q2, Q3; Q6, Q7, Q8) and a control circuit applying a boosted potential respectively to the gates of MOS transistors of the transmission gate circuits and the equalizing circuits when no memory cells of the memory cell arrays are selected whereby the capacitance of de-coupling capacitors connected to output terminals of the booster circuit can be reduced thereby contributing to reduction in chip area.

Description: The conventional DRAM has utilized boot-strap-type word line driving circuits, which use N channel MOS transistors as word line drivers in word line driving circuits. This technology is disclosed in IEEE ISSCC DIGEST OF TECHNICAL PAPERS PP12-13 February 16, 1977. Meanwhile, reduction of power supply voltage and advancement of micro lithography technology have realized an arrangement of P channel type MOS transistors as word line drivers on every word line. Therefore a newly developed 64M bit DRAM has word line driving circuits each of which has a P channel MOS transistor, and a booster circuit to generate a word line driving voltage, which cause no threshold voltage drop of the word line driving voltage across the P channel MOS transistor. However, if a booster circuit is formed in a chip, a capacitor which is connected to the output of the booster circuit occupies a very large area in order to stabilize the output potential. Accordingly, a conventional DRAM with built-in booster circuit has a problem of chip area increase. US-A-5,267,214 and JP06-203600 disclose dynamic random access memory arrangements including a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to a switching unit for connecting the selected memory block to the sense amplifiers up to a level higher than a power supply voltage V cc during the activation of the sense amplifiers, and a circuit for separating a memory block paired with the selected memory block from the activated sense amplifiers during the sensing operation. The memory further comprises a circuit for generating a control signal of the power supply voltage V cc and connecting all the memory blocks to the corresponding sense amplifiers in a stand-by state so as to reduce power consumption arising from the charge and discharge of the parasitic capacitance of the separating circuit. These documents do not disclose the use of stabilising capacitors at the output of the booster circuit. The present invention relates to a semiconductor memory, more particularly, to a DRAM (dynamic type random access memory) of a shared sense amplifier structure, which includes a booster circuit for generating a stationary boosted potential as a word line driving potential. It is an object of the present invention to minimize a capacitor area for potential stabilising capacitors which are connected to an output of a word line driving potential booster circuit. This object is achieved by the arrangement of claim 1. To achieve the above object, according to a further embodiment of the present invention there is provided a semiconductor memory device comprising: a booster circuit generating a boosted potential; a first memory cell array including first pairs of bit lines; a second memory cell array including second pairs of bit lines; a sense amplifier circuit; a first transmission gate circuit having pairs of transistors for connecting the first pairs of bit lines to the sense amplifier circuit; a second transmission gate circuit having pairs of transistors for connecting the second pairs of bit lines to the sense amplifier circuit; a first equalizing circuit having transistors equalizing the first pairs of bit lines; a second equalizing circuit having transistors equalizing the second pairs of bit lines; and a control circuit applying the boosted voltage respectively to gates of the transistors in the first and the second transmission gate circuits and gates of the transistors in the first and the second equalizing circuits when none of memory cells in the first and the second memory cell arrays is selected. By using the means provided by the present invention the boosted potential is applied on the gates of the transistors in the first and the second transmission gate circuits when none of the memory cells of the first and the second memory cell arrays is selected. That is, at this moment these transistors work as capacitive elements to be connected to the output of the booster circuit. Accordingly, the capacitance to be connected to the output of the booster circuit can be reduced by an amount corresponding to the parasitic capacitance of these transistors. Further, even when the memory cells in either of the first and the second memory cell arrays are selected, a half of the transistors in the transmission gate circuits are connected to the output of the booster circuit, the half work as capacitive elements and the capacitance to be connected to the booster circuit can be reduced by an amount corresponding to their parasitic capacitance. As stated above the transistors of the transmission gates and the like which have conventionally been connected to the ground potential in a nonselection time, are used as the capacitor for the booster circuit by which the area of the capacitive elements can be reduced by an amount corresponding to the parasitic capacitance. Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the scope of the invention will become apparent to those skilled in the art from this detailed description. BRIEF DESCRIPTION OF DRAWINGS A more complete appreciation of the present invention and many of its attendant advantages will be readily obtained by reference to the following detailed description considered in connection with the accompanying drawings, in which: Fig. 1 is a circuit diagram of the semiconductor memory of the present invention showing essential parts, and an operation diagram thereof; Fig. 2 is a circuit diagram of the semiconductor memory, showing more details of the essential part in Figure 1 and the control circuit thereof; Fig. 3. is an entire circuit configuration diagram of the embodiment of the present invention; Fig. 4 is a plane view of the semiconductor memory device of the embodiments of the present invention, showing details of the essential parts of Fig.3; Fig. 5 is a structural diagram of a booster circuit of a semiconductor memory device of the embodiments ; Fig. 6 is a view showing operational characteristic of the booster circuit of Fig. 5; Fig. 7 is a circuit diagram showing in details the booster circuit of Fig. 5; Fig. 8 is a circuit diagram showing in details the booster circuit of Fig. 5 ; Fig. 9 is a circuit diagram showing in details the booster circuit of Fig. 5; Fig. 10 is an operation diagram of the circuits shown in Figs. 7, 8 and 9; Fig. 11 is a plane view showing locations of de-coupling capacitors; and Fig. 12 is a circuit diagram showing in details a word line driving circuit and a row decode circuit. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the drawings. Although the present invention is naturally applicable to various semiconductor memory devices ( SRAM, EPROM, MROM etc.) the explanation will be given of a DRAM since the present invention is preferable to a DRAM. Fig. 1 shows essential parts of the present invention which are constituted by a first memory cell array MCA1, a second memory cell array MCA2, a pair of left bit lines BLL and /BLL, a pair of right bit lines BLR and /BLR, a sense amplifier S/A and the like. Further, the embodiment includes a left bit line pair equalizing circuit constituted by N-channel MOS transistors Q1, Q2 and Q3, a left transmission gate constituted by N-channel MOS transistors Q4 and Q5, a right bit line pair equalizing circuit constituted by N-channel MOS transistors Q6, Q7 and Q8 and a right transmission gate circuit constituted by N-channel MOS transistors Q9 and Q10. A plurality of dynamic type memory cells are arranged in a matrix in each of the memory cell arrays MCA1 and MCA2. The memory cells belonging to the same column are connected by the same pair of bit lines and the memory cells belonging to the same row are connected by the same word line. The left bit line pair equalizing circuit is controlled by a signal  E1. When  E1 is at a boosted potential Vpp ( for example, 4.3V in comparison with ground potential ), VBL (for example, 1.5V which is about a half of potential of VDD that is an inner power source potential ) is supplied to the left bit line pair BLL and /BLL and the both are shortcircuited. When  E1 is at a ground potential Vss (0V) all the MOS transistors in the circuit are made nonconductive. The right bit line pair equalizing circuit is controlled by a signal  E2. When  E2 is at the boosted potential Vpp, VBL is supplied to the right bit line pair BLR and /BLR and the both are shortcircuited. When  E2 is at the ground potential Vss, all the MOS transistors in the circuit are made nonconductive. The left transmission gate circuit is controlled by a signal  T2. When  T2 is at the boosted potential Vpp, the left bit line pair BLL and/BLL is connected to the sense amplifier S/A . When  T2 is at the ground potential Vss, the left bit line pair BLL and /BLL and the sense amplifier S/A are disconnected from each other. The right transmission gate circuit is controlled by a signal  T1. When  T1 is at the boosted potential Vpp, the right bit line pair BLR and /BLR are connected to the sense amplifier S/A. When  T1 is at the ground potential Vss, the right bit line pair BLR and/BLR and the sense amplifier S/A are disconnected from each other. In the above-constituted DRAM when none of the memory cells in the first and the second memory cell arrays is selected, all of  E1,  E2,  T1,  T2 are connected to Vpp. Since a word line, not shown, is in a nonselect state, data stored in the memory cells are not destructed. At this moment all the MOS transistors Q1 through Q10 in Fig. 1 are connected to Vpp and accordingly, the transistors provide a parasitic capacitance connected in parallel to capacitive elements that are to be connected to output terminals of a booster circuit, not shown, by which the capacitive elements can be made smaller by the amount of the parasitic capacitance. When the memory cells in the first memory cell array are selected, as shown in Fig. 1,  E1 is changed from Vpp to Vss,  T2 is maintained as Vpp,  T1 is changed from Vpp to Vss and  E2 is maintained as Vpp by which the sense amplifier S/A and the second memory cell array MCA2 are disconnected from each other and the equalizing operation of the left equalizing circuit is released. When the memory cells in the second memory cell array are selected, in a similar way,  E1 is maintained as Vpp,  T2 is changed from Vpp to Vss,  T1 is maintained as Vpp and  T2 is changed from Vpp to Vss by which the sense amplifier S/A and the first memory cell array MCA1 are disconnected from each other and the equalizing operation of the right equalizing circuit is released. As stated above by using the transistors of the transmission gates and the like which have conventionally been connected to the ground potential in a nonselect time as a capacitor of the booster circuit, the area of the capacitive elements can be reduced by the amount of their parasitic capacitance. Next, Fig. 2 shows essential parts of the present invention and the details of a control system. The control system is constituted by a booster circuit VPPGEN generating the boosted potential Vpp from an inner power source potential VDD, a capacitor DC (hereinafter, de-coupling capacitor), a circuit 221 for selecting and driving MCA1 which includes a first level shift circuit 201 and a first drive circuit 211, a circuit 222 for selecting and driving MCA2 which includes a second level shift circuit 202 and a second drive circuit 212, a row decode circuit 23, a word line driving circuit 24 and the like. The level shift circuits 201 and 202 respectively use Vpp as a power source and shift eMCA1 and eMCA2 which are output signals of a memory cell array select circuit, not shown, from a logic level (amplitude between Vss-VDD) to a boost level ( amplitude between Vss-Vpp). The drive circuits 211 and 222 respectively use Vpp as the power source and respectively drive  E1,  E2,  T1 and  T2 by amplifying input signals at the booster level as output signals at the same booster level. The row decode circuit 23, the predecode circuit 23' (refer to Fig. 12) and the word line driving circuit 24 use Vpp as the power source and select and drive word lines to the booster level. Fig. 12 shows the details thereof. The row decode circuit 23 is constituted by a circuit where a P-channel MOS transistor Q21 on the gate of which a signal PRE 2 at the booster level is applied is connected in series to N-channel transistors Q22, Q23 and Q24 on the gates of which a row address signal X Add at the logic level is applied and three inverter circuits 231, 232 and 233. The predecode circuit 23' is constituted by a circuit where a P-channel MOS transistor Q21' on the gate of which a signal PRE 1 at the booster level is applied is connected in series to N-channel MOS transistors Q22', Q23' and Q24' on the gates of which a row address signal X+ Add at the logic level is applied and four inverter circuits 231', 232', 233' and 234'. The word line driving circuit 24 is constituted by inverter circuits Q25 and Q26 which use Vpp as the power source. Next, an explanation will be given of the operation of the circuit shown in Fig. 2. When both of MCA1 and MCA2 are not selected, the signal eMCA1 and the signal eMCA2 are both at LOW level (Vss). At this moment the potentials of N11, N12, N21 and N22 are respectively at Vpp, Vss, Vpp and Vss. The signals are amplified by the amplifying circuits 211 and 212 and all of  E1, fE2, fT1 and  T2 are at Vpp. Here, the output terminal of the booster circuit and the respective signal lines of  E1,fE2,fT1 and  T2 are commonly connected via P-channel MOS transistors on pull-up side at the final stage of inverters (constituted by P-channel MOS transistor and N-channel MOS transistor) in the drive circuits 221 and 212. Further, these respective signal lines simultaneously drive a great number of bit line pairs (several hundreds) in the memory cell arrays and accordingly, the parasitic capacitance is very large. As a result it is possible to make comparatively small the capacitance of the de-coupling capacitor DC. Next, the operation in case where MCA2 is selected is shown as an example. The signal eMCA1 is changed from low level to high level (VDD) and the signal eMCA2 is maintained at low level. As a result, the potentials of N11, N12, N21 and N22 are respectively at Vss, Vpp, Vpp and Vss. The signals are amplified at the drive circuits 211 and 212 and  E1,fE2,fT1 and  T2 respectively become Vpp, Vss, Vpp and Vss. As a result the sense amplifier S/A and the first memory cell array MCA1 are disconnected from each other and the equalizing operation of the right equalizing circuit is released. Successively, the word line WL is driven to the booster level by the operation of the word line driving circuit 24 and the operation such as reading is performed by the operation of the sense amplifier S/A. A similar operation is performed when MCA1 is selected and accordingly,the explanation will be omitted. Fig. 3 shows an outline structural view of a DRAM of the present invention. The total memory capacity is assumed to be that of a 64M bit DRAM. Core blocks CB0, CB1, CB2 and CB3 each constituted by 16M bit memory cells and peripheral circuits within a core section such as sense amplifiers, decoders and the like accompanying the memory cells, are arranged in a semiconductor chip 9. Vpp generating circuits Vpp Pump each generating the boosted voltage Vpp of a word line, are respectively arranged between CB0 and CB1, and CB2 and CB3. Data multiplexer circuits MUX and data buffer circuits DIB are respectively arranged at data output units of the respective core blocks CB. Fuse arrays CFUSE for holding replaced data of column redundancy circuits are arranged at the vicinities of the respective core blocks. A reference voltage generating circuit VREF for generating a reference potential that is an intermediate potential of 1/2 Vcc etc. is arranged between CB0 and CB1. A power-on reset circuit PWRON for generating an initializing signal when the internal portion of the chip is initialized in case where power source is on, is arranged between CB2 and CB3. A substrate potential generation circuit SSB, a data input/output buffer I/O buffer and Pad, a IO data multiplexer circuit X1MUX for selecting Pad in accordance with data output width are successively arranged between CB0 and CB2. A self refresh control circuit'Self refresh, an address buffer Address buffer, a row series control circuit RAS series and a data control circuit DCC are successively arranged between CB1 and CB3. Further, column partial decoder circuits CPD, an address transition detection circuit ATD, a row partial decoder circuit RPD and a column address switch circuit ASD are respectively arranged at the central portion of the chip. Next, Fig. 4 shows the structure of the 16M bit core block CB. 32 sets of memory cell arrays Cell and 33 sets of peripheral circuits within a core section S/A are alternately arranged constituting the memory cell block and the column decoder circuits C/D are arranged at an end thereof. A plurality of column select lines CSL are arranged in the column direction, and are selectively driven by the column decoder circuits C/D. The column select lines CSL supply selection signals to the peripheral circuits within a core section S/A at each column belonging to the same row. More in details the column select line is used for partial activation of the sense amplifier circuits and for driving the column gate circuits. The memory cell block constitutes the 16M bits core block CB by dividing it into top and bottom groups between which respectively arranged are row decoder circuits R/D(23) each corresponding to each memory cell array, circuits WDRV for supplying drive signals to the row decoder circuits, circuits RFUSE for holding replaced data of row redundancy circuits, data line amplifying circuits DQB, a block control circuit BC and the like. P-channel type sense amplifier drive circuits PSAD each corresponding to each peripheral circuit within a core section are respectively arranged at peripheral portions of the core blocks CB. The memory cell arrays MCA1 and MCA2 shown in Fig. 1 and Fig. 2 respectively correspond to the memory cell arrays Cell in Fig. 4. As is illustrated one 16M core block CB has 64 of the memory cell arrays Cell (MCA) and a single chip has 256 of the memory cell arrays Cell (MCA). The following description indicates how much parasitic capacitance is provided by the block structure shown in Fig. 3 and Fig. 4 and how much capacity of the de-coupling capacitor can be saved as a result. First, a contribution of the transmission gate circuits will be calculated. There are 1024 pairs of bit lines in one memory cell array ( disregarding redundancy bit lines). Therefore, the number of the transmission gate circuits in a single chip is 262144. Incidently, a single transmission gate circuit is constituted by two N-channel transistors. Therefore, the number of the MOS transistors in the transmission gate circuits is 524288. For example, assuming the gate width of 0.8mm and the gate length of 0.56µm in one MOS transistor, the area of the channel regions in one MOS transistor is 0.45µm 2 . By multiplying the area to all the MOS transistors the area amounts to 234880µm 2 . Assuming the gate oxide film thickness of 12nm, it corresponds to a parasitic capacitance of 0.68nF. Secondly, a contribution of the equalizing circuits will be calculated. The number of the equalizing circuits in a single memory cell array is also 262144. A single equalizing circuit is constituted by three MOS transistors, that is, two MOS transistors each having the gate width of 0.8µm and the gate length of 0.56µm and one MOS transistor having the gate width of 2.0µm and the gate length of 0.56µm. Accordingly, when the area is multiplied to all the MOS transistors, the total area of the channel regions amounts to 528482µm 2 . This corresponds to a parasitic capacitance of 1.52nF. The parasitic capacitance calculated as above amounts to approximately 2.2nF. Normally several (4 in a refresh cycle product having 8K and 8 in a refresh cycle product having 4K) memory cell arrays are selected in reading. Therefore, substantially all of the memory cell arrays contribute to the parasitic capacitance. Further, in a 64M DRAM, a de-coupling capacitor DC having a capacitance of approximately 5nF is necessary to guarantee a stable operation. However, it is possible to approximately halve it to 2.8nF by the circuit structure of the present invention which contributes to a considerable reduction in the chip area. In this way, the memory device is divided into a number of memory cell arrays as in a DRAM having a large capacity and a ratio of the number of the memory cell arrays that are simultaneously activated to a total thereof is reduced by which the total amount of the parasitic capacitance can be increased which as a result contributes to the considerable reduction in the chip area. Further, as shown in Fig. 11 the de-coupling capacitors DC are scattered all over the tip. Next, a detailed explanation will be given of the booster circuit VPPGEN in reference to Fig. 5 through Fig. 10. Fig. 5 shows the circuit structure of the booster circuit VPPGEN. The booster circuit is constituted by a reference potential generating circuit 50, comparing circuits 51,52 and 53, ring oscillator circuits 54,55 and 56, driver circuits 57,58 and 59, charge pump circuits 60,61 and 62, voltage dividing circuits 63,64 and 65 and a power source voltage step-down transistor Q66. As shown in Fig. 5, an outer potential Vcc inputted from the outside is stepped down by the power source voltage step-down transistor Q66 whereby VDD is generated and VDD is again boosted by the charge pump circuits 60 and 61 whereby the boosted potential Vpp is generated. The power source voltage step-down transistor Q66 is driven by VPPD that is a potential boosted from VDD. Further, the generation of Vpp is performed by two kinds of systems, that is, a system exclusive for standby and a system exclusive for operation. In this way the booster circuit is constituted by three booster systems each performing the boosting operation independently by a feedback type control. Fig. 6 shows behaviors of changes of Vpp, VPPD and VDD with respect to Vcc along with those of a cell capacitor plate potential VPL, a bit line potential VBL and a substrate potential VBB. There is a nonvariational region of potentials between approximately 3V to approximately 4V. Fig. 7 shows the detail of the ring oscillator 54 and a portion of the driver circuit 57. In the ring oscillator 54 a NAND gate 541 and even number stages of inverters 542, 543, 544, 545, 546 and 547 are connected in a ring-like form. In the driver circuit inverter circuits 571,572, 573, 574, 575, 576, 578, 579, 580, 581, 582, 583 and 584 are connected in series respectively forming successively delayed signal outputs /C0, C0, /C1, C1, /C2, C2, /C3, C3, /C4, C4, /C5, C5, /C6 and C6. Fig. 8 shows the remaining portion of the driver circuit 57. A signal A1 is formed from the signals C1 and C4 by a NAND gate 585 and inverters 586, 587 and 589. A signal B1 is formed from the signals C1 and C6 by a NAND gate 590 and inverters 591, 592 and 593. A signal C11 is formed from the signals C3, /C6,C2 and /C0 by a ANDNOR gate 604 and inverters 605, 606 and 607. A signal C12 is formed from the signals C3,/C6,C2 and/C0 by an ORNAND gate 608 and inverters 609,610,611 and 612. A signal A2 is formed from the signals C1 and C4 by a NOR gate 594 and inverters 595, 596, 597 and 598. A signal B2 is formed from the signals C1 and C6 by a NOR gate 599 and inverters 600, 601, 602 and 603. Fig. 9 shows the details of the charge pump circuit. The charge pump circuit is constituted by capacitors Q31,Q32,Q33,Q34,Q41 and Q42 and N-channel MOS transistors Q35, Q36, Q37,Q38,Q39 and Q40. Fig. 10 shows the operation of the charge pump circuit. Although the charge pump circuit is constituted by vertically symmetrical circuit portions, the explanation will be given only of the upper half portion for simplicity. To simplify the explanation no parasitic capacitance is considered and the capacitor coupling ratio is assumed to be infinitive. The signals C0 through C6 are provided with waveforms as shown in Fig. 10 by the driver circuit 57. At the initial state where one cycle operation has finished, a node A and a node B are provided with the potential of VDD and a node C is provided with the potential of 2VDD. At a time point t1, the signal C1 is changed from Vss to VDD, then the potential of the node C is boosted from 2VDD to 3VDD by the capacitive connection of the capacitor Q41. At a time point t2, the signal A1 is changed from Vss to VDD, then the potential of the node A is boosted from VDD to 2VDD by the capacitive connection of the capacitor Q31. 3VDD is supplied on the gate of the MOS transistor Q39 and accordingly, the potential of 2VDD is transmitted to the node B. Successively at a time point t3, the signal B1 is changed from Vss to VDD, then the potential of the node B is boosted from 2VDD to 3VDD by the capacitive connection of the capacitor Q33. At this instance the MOS transistor Q39 is cut off. As a result the MOS transistor Q35 on the gate of which 3VDD is applied becomes conductive and 2VDD at the node A is transmitted to the Vpp node that is an output node. At a time point t4, C1 again rises, at a time point t5, the potentials of A1 and B1 change from VDD to Vss and at a time point t6, C1 falls. The potential C1 is made VDD and the potential of the node C is made 3VDD before and after the time point t5 for finishing the boosting and transmitting operation to firmly initialize the potential of the node B to VDD. As explained above theoretically 2VDD is stationarily outputted. However, actually Vpp is approximately 4.3V for 3V of VDD by a feedback control and by the parasitic capacitance. The charge pump is very efficient compared with a conventional one. However, highfrequency noises are apt to generate therein and accordingly, it is necessary to connect the de-coupling capacitor DC having a large capacitance to output terminals. Therefore, the characteristic of the charge pump shown in Fig. 9 can be maximized by positively utilizing the parasitic capacitance by using the control system shown in Fig. 2. Although detailed explanation has been given to the embodiments wherein the present invention is used in a 64M bit DRAM, the present invention is not restricted to the above-mentioned structures and various modifications can naturally be performed so far as these modifications do not deviate from the gist of the invention. Especially, with regard to the structure of the power source circuit, although the stepped-down potential VDD is further boosted in the above-mentioned embodiments, Vcc that is a power source potential inputted from the outside may directly be boosted whereby an effect of simplifying the power source circuit is achieved. According to the present invention the capacitance of the de-coupling capacitor can be reduced thereby contributing to the reduction in chip area. The capacitance of a de-coupling capacitor can further be reduced in case where a number of memory cell arrays are arranged and only a portion of the arrays are activated. While there has been illustrated and described what are presently considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for devices thereof without departing from the true scope of the invention. In addition many modifications may be made to adapt a particular situation or material to the teaching of the present invention without departing from the central scope thereof. Therefore, it is intended that this invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention include all embodiments falling within the scope of the appended claims.

Claims: A semiconductor memory device having: a booster circuit (VPPGEN) for generating a boosted potential (VPP) at an output terminal of said booster circuit; a first memory cell array (MCA 1 ) including first pairs of bit lines (BLL 1 /BLL); a second memory cell array (MCA n ) including second pairs of bit lines (BLR 1 /BLR); a sense amplifier circuit (S/A); a first transmission gate circuit (ØT 2 ) having pairs of transistors (Q4, Q5) for connecting the first pairs of bit lines (BLL 1 /BLL) to the sense amplifier circuit (S/A); a second transmission gate circuit (ØT 1 ) having pairs of transistors (Q9, Q10) for connecting the second pairs of bit lines (BLR 1 /BLR) to the sense amplifier circuit (S/A); and a control circuit (22 1 ) applying the boosted potential (VPP) respectively to gates of the transistors in the first and the second transmission gate circuits (ØT 2 , ØT 1 ) when none of memory cells in the first and the second memory cell arrays (MCA 1 , MCA 2 ) is selected, characterised in that capacitive elements (DC) are connected to the output terminal of the booster circuit. The semiconductor memory device of claim 1 further comprising: a first equalizing circuit (E 1 ) having transistors (Q 1 , Q 2 , Q 3 ) for equalizing the first pairs of bit lines (BLL 1 /BLL); a second equalizing circuit (ØE2) having transistors (Q 6 , Q 7 , Q 8 ) for equalizing the second pairs of bit lines (BLR 1 /BLR); and wherein said control circuit (221) further applies the boosted voltage (CVPP) respectively to gates of the transistors in the first and the second equalizing circuits (E1, ØE2) when none of memory cells in the first and the second memory cell arrays (MCA 1 , MCA 2 ) is selected. The semiconductor memory device according to claim 2, wherein the control circuit (22 1 ) applies a ground potential respectively to the gates of the transistors in the first equalizing circuit (ØE1) and to the gates of the transistors in the second transmission gate circuit (ØT1) and applies the boosted potential (VPP) respectively to the gates of the transistors in the second equalizing circuit (ØE2) and to the gates of the transistors in the first transmission gate circuit (ØT2) when selecting the memory cells in the first memory cell array (MCA 1 ); and wherein the control circuit (22 1 ) applies the ground potential respectively to the gates of the transistors in the second equalizing circuit (ØE2) and to the gates of the transistors in the first transmission gate circuit (ØE2) and applies the boosted potential (VPP) respectively to the gates of the transistors in the first equalizing circuit (ØE1) and to the gates of the transistors in the second transmit circuit (ØT1) when selecting the memory cells in the second memory cell array (MCA 2 ). The semiconductor memory device according to claim 1, wherein the control circuit (22 1 ) applies a ground potential to the gates of the transistors in the second transmission gate circuits (ØT1) and applies the boosted potential (VPP) to the gates of the transistors in the first transmission gate circuit (ØT2) when selecting the memory cells in the first memory cell array (MCA 1 ); and the control circuit (22) applies the ground potential to the gates of the transistors in the first transmission gate circuit (ØT2) and applies the boosted potential (VPP) to the gates of the transistors in the second transmission gate circuit (ØT1) when selecting the memory cells in the second memory cell array (MCA 2 ). The semiconductor memory device according to claim 2 or 4, wherein first and second word line driving circuits 24 are respectively connected to the first and the second memory cell arrays (MCA 1 /MCA n ) and the first and the second word line driving circuits (24) are operated by the boosted potential (VPP). The semiconductor memory device according to claim 5, wherein the first and the second word line driving circuits (24) are controlled respectively based on selection signals of first and second row decode circuits (23) and the first and the second row decode circuits are operated by the boosted potential (VPP). The semiconductor memory device according to claim 2 or 6, wherein the control circuit (22) comprises at least a first level shift circuit (20) for shifting an amplitude level of a first select signal for selecting the first memory cell array to a level of the boosted potential and a second level shift circuit (20 2 ) for shifting an amplitude level of a second select signal for selecting the second memory cell array to the level of the boosted potential (VPP) and the boosted potential (VPP) is used for a power source of the first and the second level shift circuits. The semiconductor memory device according to claim 7, wherein the control circuit is further comprising first and second drive circuits (21 1 , 21 2 ) respectively connected to the first and the second level shift circuits (20 1 , 20 2 ), said first and second drive circuits using the boosted potential (VPP) as a power source and driving the gates of the transistors in the first and the second transmission gate circuits (ØT 2 , ØT 1 ) to the boosted potential (VPP) when none of the memory cells in the first and the second memory cell arrays (MCA 1 , MCA 2 ) is selected. The semiconductor memory device according to claim 1 or 2, wherein the booster circuit (VPPGEN) generates the boosted potential (VPP) by stepping down a potential inputted from an outside and again boosting the potential. The semiconductor memory device according to claim 7, wherein the control circuit (22) is further comprising first and second drive circuits (2Ø 1 , 2Ø 2 ) respectively connected to the first and the second level shift circuits (20 1 , 20 2 ), said first and second drive circuits (21 1 , 21 2 ) using the boosted potential (VPP) as a power source and driving the gates of transistors in the first and the second transmission gate circuits (ØT 2 , ØT 1 ) and the gates of transistors in the first and the second equalizing circuits (ØE 1 , ØE 2 ) to the boosted potential (VPP) when none of the memory cells in the first and the second memory cell arrays (MCA 1 , MCA 2 ) is selected.

Inventors: KANEKO TETSUYA, KANEKO, TETSUYA, KANEKO, TETSUYA, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1995
Main classification: G11C11
IPC codes: G11C11, G11C5