ELECTRONIC SPEED GOVERNOR

Abstract: The low cost speed governor for internal combustion engines may be completely powered by the ignition coil. The governor receives a periodic signal from the primary ignition winding (W1) that is indicative of the actual speed of the engine. A pulsed speed signal is generated that is functionally related to the periodic signal. The pulsed speed signal had a pulse width that is functionally related to the actual engine speed. A pulsed reference signal is generated by a timer circuit (U4), and has a pulse width that is functionally related to a predetermined reference speed. The pulsed speed signal is then compared with the pulse reference signal by a comparator circuit (G12), and a pulsed error signal is generated that has a pulse width which is functionally related to the difference between the speed signal pulse width and the reference signal pulse width. The speed of the device is then changed by a transistor bridge network as a function of the error signal.

Description: ELECTRONIC SPEED GOVERNOR BACKGROUND OF THE INVENTION This invention relates to speed governors for power producing and absorbing devices, such as internal combustion engines. More particularly, this invention relates to electronic speed governors for small engines like those used on lawnmowers, snowblowers, generators and the like. Automatic devices that cause power producing and absorbing machines to operate near a fixed speed are well known in the art. Such automatic devices are commonly referred to as "speed governors". Typically, such speed • governors are either of the mechanical type or of the electronic type. Various types of mechanical governors are well known in the art. However, such governors are often bulky, contain numerous moving parts, and are expensive. Many types of electronic speed governors are also well known in the art. Such electronic devices permit more accurate control of engine speed, but often contain many semiconductor components that thereby increase the cost of the governor. In addition, typical prior art electronic governors require a separate DC power source such as a battery to power the governor's electronic components. This also further increases the cost and complexity of the typical prior art governor. SUMMARY OF THE INVENTION A speed governor for controlling the actual speed of a device comprises an input means for receiving a periodic signal that is indicative of the actual speed of the device, and a first means for generating a pulsed speed signal that is functionally related to the periodic signal such that the pulse width of the pulsed speed signal is also functionally related to the actual engine speed. The periodic signal may be an AC signal generated by a winding on the device's ignition coil frame, from a separate coil assembly, or from a battery-powered or alternator-powered sensor. The speed governor also includes a second means for generating a pulsed reference signal whose pulse width is functionally related to a desired device speed. The pulsed speed signal is then compared with the pulsed reference signal by a comparison means. The comparison means generates a pulsed error signal whose pulse width is functionally related to the difference between the speed signal pulse width and the reference signal pulse width. In one embodiment, a determining means then determines whether the actual speed of the device is above or below the desired speed, and generates a control signal that is indicative of the result of that determination and that is also functionally related to the error signal pulse width. In response to the control signal, a changing means changes the speed of the device such that the magnitude of the speed change is a function of the magnitude of the difference between the actual speed and the desired speed. In a preferred embodiment, the speed governor also includes a means for preventing the changing of the device speed when the width of the error signal pulse is less than a predetermined value. This feature avoids the unnecessary cycling of the device when the engine speed is near the . desired reference speed, thereby allowing the device speed to vary within a predetermined speed band, without correcting the speed of the device. The preferred embodiment also includes a means for controlling the increase of the device speed in response to the governor during warm-up of the device. It is a feature and advantage of the present invention to provide a low cost electronic governor that uses a small coil or the ignition primary winding to power all of the governor's components. It is another feature and advantage of the present invention to provide an electronic governor having a minimum number of integrated circuits and other semi¬ conductor components. It is another feature and advantage of the present invention to provide a low cost electronic governor having proportional speed control. These and other features of the present invention will be apparent to those skilled in the art from the following detailed descri p tion of the preferred embodiments and the drawings, in wh_ n: BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a first embodiment of the present invention. Fig. 2 is a schematic diagram of a second embodiment of the present invention. Figs. 3(a) through 3(f) are timing diagrams relating to the circuits of Figs. 1 and 2 when the device is in an underspeed condition. Fig. 3(a) depicts the periodic input signal. Fig. 3 (b) depicts the output signal of the optional signal conditioner circuit. Fig. 3(c) depicts the pulsed speed signal for an underspeed condition. Fig. 3(d) depicts the pulsed referenced signal. Fig. 3(e) depicts the pulsed error signal which corresponds to the difference in the pulse width between the pulsed speed signal and the pulsed reference signal. Fig. 3(f) depicts the current flowing through the motor as a function of the error signal. Fig. 4 is a schematic diagram of an integrated 555 timer which may be used in the first embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following descriptions and the drav,-.ngs assume that the governor is being used to control the throttle position of an internal combustion engine. However, the governor according to the present invention may be used to control the position of other actuators in power-producing and power-absorbing devices, such as electric motors and dynamometers, to thereby control the actual speed of such devices. Referring to Fig. 1, a rotating flywheel FW generates an alternating periodic signal in winding WI . Fig. 3(a) depicts this periodic signal. Winding WI is preferably the ignition primary winding of a gasoline-powered, internal combustion engine, although winding WI could be a small power winding attached to one leg of the engine's ignition coil frame. This arrangement significantly reduces the governor's cost since no battery, with its accompanying charging system, is required. However, the present invention may also be used with a battery. In that event, the battery would be used for system power, and the input periodic signal may be derived from winding WI or from a battery-powered sensor such as a Hall-effect sensor (not shown) . Even if a battery is available, however, it may be desirable to use winding WI to power the electronic governor since the governor may then be used regardless of the state of the battery charge. The power supply for the electronic governor depicted in Fig. 1 includes diodes Dl and D2, capacitors Cl and C2, and zener diodes D3 and D . In some applications, it may be desirable to combine zener diodes D3 and D4 into a single diode. When the governor is used on a small engine, the power supply generates a supply voltage each time a magnet MA affixed to flywheel FW passes ignition winding WI . Diode rectifiers Dl and D2 convert the input supply voltage from AC to DC. Capacitors Cl and C2 provide energy storage to maintain a more constant power supply voltage as a function of time. Zener diodes D3 and D4 limit the power supply voltage to a value that is acceptable for the sensing and control circuitry, described below. The voltage across capacitor Cl is usec o power the governor' s output motor drive circuit, while the voltage across capacitor C2 is used to power the governor's sensing and control circuitry. The governor depicted in Fig. 1 includes an optional signal conditioning circuit that receives a periodic signal from the power supply and that outputs a pulsed DC signal to the governor's sensing and control circuitry. The signal conditioning circuit includes NPN transistor Tl, a voltage divider consisting of resistors Rl and R2 that control the base-to-emitter junction of transistor Tl, a resistor R3, a NAND gate inverter Gl, and a capacitor C3. The signal conditioning circuit operates in the following manner. When a periodic signal is generated by winding WI, NPN transistor Tl is biased ON through the voltage divider consisting of resistors Rl and R2. The biasing ON of transistor Tl causes capacitor C3 to discharge through transistor Tl, thereby causing NAND gate Gl to change rapidly to a high-state output . When transistor Tl no longer conducts, capacitor C3 begins to charge through resistor R3. As long as the voltage across capacitor C3 is below the input threshold voltage of gate Gl, the inputs to gate Gl remain at a low-state and the output of gate Gl remains at a high-state. As soon as the voltage of capacitor C3 exceeds the input threshold voltage for gate Gl, the output of gate Gl returns to a low-state. Thus, the signal conditioning circuit has a timing function that is used to provide a rectangular-wave input signal to the governor's sensing and control circuitry. The timing function of the signal conditioning circuit should be longer than the time duration of the periodic signal generated by coil WI at normal engine operating speeds. The output of the signal conditioning circuit is depicted in Fig. 3 (b) . A divide-by-two circuit Ul is used to receive the periodic signal generated by a DC-powered sensor (not shown) if no signal conditioner is used, or to receive the pulsed signal generated by NAND gate Gl if a signal conditioner is used. The purpose of device Ul is to receive the periodic signal and to output a pulsed .speed signal whose pulse width is a function of the actual engine speed. The pulsed speed signal for an underspeed condition is depicted in Fig. 3(c). By comparing Figs. 3(a) and 3(c), it is apparent that the pulse width of the speed signal is equal to the time duration between the onset of successive periodic signals. The speed signal changes state at the onset of each periodic signal, so that the pulse width of both the high-states and the low-states of the speed signal are a function of the actual speed of the device. The speed of the device is readily determined from the time between the onset of successive periodic signals, since one periodic signal is generated for each revolution of the engine flywheel. Referring again to Fig. 1, the output of device Ul is conditioned by a differentiator circuit consisting of capacitor C4 and resistor R4. This conditioned signal is input to both inputs of a .second NAND gate G2, that is used to initiate a timing cycle of an integrated circuit timer U2. The integrated circuit timer is preferably a 555 timer, although other monostable multivibrators may be used. One suitable 555 timer is sold by Motorola under part no. MC1455. A circuit diagram of a typical timer U2 is depicted in Fig. 4. Timer U2 initiates a timing cycle each time the output of divide-by-two circuit Ul changes from a low-state to a high-state. The pulse width of the timer U2 output signal corresponds to the time period of one engine flywheel revolution at the desired or reference engine speed. The pulse width of this reference signal is preset by the timing circuit consisting of resistor R5 and capacitor C5, which are connected to an input of timer U2. The pulsed reference signal is depicted in Fig. 3(d) . Resistor R5 may be replaced by a variable-resistance potentiometer to provide variable speed control. The output of timer U2 is then compared with the output of divide-by-two circuit Ul by an Exclusive-OR Gate G3. As depicted in Fig. 1, pin 6 of gate G3 is connected to the pin 1 output of circuit Ul. Pin 5 of gate G3 _s connected to output pin 3 of timer U2. The purpose of the comparison by gate G3 is to determine wheth_r the actual engine speed, as indicated by the output of device Ul, is equal to the reference speed, as indicated by the output of timer U2. If these two inputs to gate G3 are substantially equal, the output of gate G3 remains at a low-state. When the actual engine speed differs from the reference speed, the output s. al generated by gate G3 goes to a high-state, with the , ..e width of this error signal being proportional to the difference between the actual engine speed and the desired speed. The error signal for an underspeed condition is depicted in Fig. 3(e). A determination is then made as to whether the actual engine speed is above or below the desired engine speed. This determination is made by a circuit consisting of two NAND gates G4 and G5 and two Exclusive-OR Gates G6 and G7, which are used as inverters. Input 9 of NAND gate G4 is connected to output pin 1 of divide-by-two device Ul. Input pin 8 of gate G4 is connected to. the output of Exclusive-OR Gate G3. Input pin 12 of NAND gate G5 is connected to the output of gate G3. Input pin 13 of gate G5 is connected to the inverted output of J evice Ul, the inverted signal being output at pin 2 of "ice Ul. In other words, the output of gate G3 is compared with the output of circuit Ul by gate G4 and the output of gate G3 is also compared with the inverted signal of device Ul by gate G5. This determination circuit operates in the following manner. In an underspeed condition, both inputs to NAND gate G4 are in their high-state simultaneously, so that the output of gate G4 is at its low-state. The low-state output of gate G4 is inverted by Exclusive-OR Gate G6, so that the output of gate G6 is a high-state control signal which turns ON transistors T2 and T3 through resistors R7 and R8 respectively. Motor current then causes the drive shaft of motor Ml to rotate in a first direction, thereby partially opening the throttle. Also in an underspeed condition, the output of gate G5 remains continuously in its high-state since the inverted output at pin 2 of device Ul and the output of gate G3 are never at a high-state simultaneously. This high-state signal output by gate G5 is inverted by gate G7, whose other input is connected to the power supply. Thus, the output of gate G7 stays low in an underspeed condition, thereby keeping transistors T4 and T5 OFF. If an overspeed condition exists, the output of device Ul goes to its low-state before the output of timer U2 goes to its low-state. In that event, the output of gate G3 is high. The output of NAND gate G4 stays high since its inputs at pins 8 and 9 are never at a high-state simultaneously in an overspeed condition. Gate G6 inverts the high-state output of gate G4, and outputs a low-state signal. Thus, transistors T2 and T3 connected to the output of gate G6 remain OFF. Also in the overspeed condition, the output of gate G3 and the inverted output of timer Ul are at high-states simultaneously. Gate G5 thus receives two high-state inputs, and the output of gate G5 goes low. When the output of gate G5 is low, the output of inverter G7 is high, thereby generating a control signal that turns ON transistors T4 and T5 through resistors R9 and RIO respectively. Motor current is thus generated through motor Ml in a second direction to at least partially close the throttle. The length of time that any of the drive circuit transistors conduct is proportional to the pulse width of the control signal, that pulse width being a function of the difference between the actual and desired engine speeds. Thus, the length of time that the transistors conduct is functionally related to the pulse width of the error signal generated by gate G3. In either the underspeed or the overspeed condition, the amount of rotation of the motor drive shaft and thus of the throttle plate is a function of the difference between the actual speed and the desired engine speed. A gear- reduction system is typically connected between the DC motor drive shaft and the engine's throttle plate to insure that throttle plate position is precisely controlled. The speed governor could also be used to control an engine fuel injection system instead of carburetor throttle plate position. The motor drive output section consisting of transistors T2 through T5 and resistors R7 through RIO may be replaced by a single integrated circuit motor drive chip, such as that sold by Cherry Semiconductor of East Greenwich, Rhode Island, Model No. CS-298. The speed governor can also be used with a push-pull amplifier drive circuit. With this drive circuitry, the output of one operational amplifier goes to a high-state while the output of the second operational amplifier goes to a low-state, and vice versa, causing the motor current to flow in a first or a second direction. The circuit depicted in Fig. 1 includes two optional circuits that may be desirable in many applications. The first optional circuit creates a "speed band" in which the engine speed is allowed to vary with only limited correction of the actual speed when the actual speed is slightly less than the reference speed, by using a time delay circuit. The speed band is preferably between 20 to 200 wide rpm, with the desired engine speed being at the high end of the speed band. Of course, this time delay could also operate when the actual speed is slightly higher than the reference speed, so that the desired speed is in the middle of the speed band. The purpose of the speed band is to limit corrections in engine speed when the engine speed differs slightly from the desired speed. Referring to Fig. 1, the speed band is achieved using capacitor C6 and resistor R8. Capacitor C6 and resistor R8 are used to reduce the throttle positioner travel when the engine speed is just slightly lower than the desired engine speed. Capacitor C6 provides a very brief time delay to the biasing of transistor T3. When the speed difference between the actual speed and the desired speed is small, the biasing signal to transistor T3 is too short to switch transistor T3 ON through the time delay circuit. In that event, current through motor Ml is provided through transistor T2 and through resistor Rll, which limits motor current to a lower value than if transistor T3 was to conduct. When the difference between the actual speed and the desired speed becomes greater, transistor T3 switches ON fully, thereby providing increased current to motor Ml. A similar capacitor and resistor circuit may be applied to transistor T5, if desired, to provide a similar time delay function when the actual engine speed only slightly exceeds the desired engine speed. Another optional feature of the present invention is to delay throttle-positioner response to the underspeed condition during initial engine starting and engine warm- up. It is desirable to delay the governor's underspeed response to allow the engine to warm up without excessive speed oscillations occurring. This optional feature is achieved by the circuit consisting of Exclusive-OR Gate G8, resistor R12, capacitor C7, transistor T6, and resistor R13. Exclusive-OR Gate G8 has two inputs: Input pin 1 is connected to the governor's power supply through the RC timing circuit consisting of resistor R12 and capacitor C7. Input pin 2 of gate G8 is directly connected to the governor's power supply. When the engine is initially started, the output of gate G8 remains at a high-state until capacitor C7 becomes charged. During this time, transistor Tβ is biased ON through resistor R13. As a result, transistor T3 is prevented from conducting. Thus, during the engine warm-up period, motor current is provided through transistor T2 and resistor Rll. The underspeed throttle-positioner response is thereby limited during engine warm-up, which in turn limits the engine speed oscillations during the warm-up period. After capacitor C7 becomes sufficiently charged, both inputs to Exclusive-OR Gate G8 are at a high-state, so that the output at pin 3 of gate G8 goes to a low-state. When the output of gate G8 goes to a low-state, transistor T6 no longer conducts, thereby allowing transistors T3 and T2 to control engine speed during an underspeed condition. Fig. 2 is a schematic diagram of a se- nd embodiπH z of the present invention. The embodiment depicted in Fig. 2 achieves essentially the same functions as the embodiment depicted in Fig. 1, except that the Fig. 2 embodiment is lower in cost due to a reduction in the number of components. More specifically, the embodiment depicted in Fig. 2 uses a dual-timer chip comprised of devices U4 and U5, in place of NAND gate Gl and 555 timer U2, to achieve signal conditioning and to yield the reference signal. In addition, the circuit depicted in Fig. 2 uses AND gates G10 and Gil in place of NAND gates G4 and G5 and the Exclusive- OR Gates G6 and G7 of the Fig. 1 embodiment, to determine which of the output transistors T2 through T5 will conduct. Components in Fig. 2 which have corresponding functions to components in Fig. 1 have been given the same part designations. In Fig. 2, the power supply consists of diodes D6 and D7, zener diode D8, and capacitors C9 and CIO. The power supply functions in a manner similar to the power supply described above with respect to Fig. 1. The periodic signal from winding WI is provided to timer U4 through resistor R14, capacitor Cll, and resistor R15. Resistor R16 and capacitor C12 together form an RC timing circuit which determines the time constant of timer U4. The receipt of a periodic signal by timer U4 starts its timing cycle. The output of timer U4 at pin 6 thereof is a rectangular-wave signal whose pulse width is greater than the length of the periodic input signal from winding WI at normal engine operating speeds. Thus, timer U4 creates a one pulse per engine revolution signal. The output of device U4 is provided to the pin 3 input of a divide-by-two circuit Ul . The function of device Ul in Fig. 2 is the same as the function of device Ul in Fig. 1. In Fig. 2, the output of divide-by-two device Ul is a rectangular-wave signal whose pulse width is functionally related to the actual engine speed. The output of device Ul at pin 1 thereof is provided to the input of device U5, which is the other half of the dual-timer IC chip no. 4538. The timing cycle of device U5 is determined by resistor R17, capacitor C13, resistor R18, and a variable resistor R19 that may be switched into the RC timing circuit consisting of resistor R17 and capacitor C13. Variable resistor R19 allows different engine reference speeds to be set by the user. The output of ti er U5 is a rectangular-wave signal whose pulse width corresponds to the desired engine speed. The output at pin 10 of device U5 is provided to Exclusive-OR Gate G12. The function of gate G12 is substantially the same as the function of gate G3 in Fig. 1. That is, gate G12 is used to compare the pulsed speed signal output by device Ul with the pulsed reference signal output by device U5. When the pulsed speed signal is not equal to the pulsed reference signal, the output of gate G12 goes to a high-state, with the pulse width of this error signal being proportional to the difference between the actual engine speed and the desired speed. The output of gate G12 is connected to an input of both AND gate G10 and AND gate Gil. Regarding AND gate G10, its input pin 12 is connected to output pin 1 of device Ul . Both inputs to gate G10 are at a high-state during an underspeed condition, so that the output of gate G10 is also at a high-state in an underspeed condition. In that event, transistors T2 and T3 are turned ON to provide motor current to motor Ml in a first direction so as to partially open the engine throttle. Again referring to gate G10, in an overspeed condition the output of gate G10 is high while the output of divide- by-two Ul is low, so that the output of AND gate G10 is low. Since no high-state control signal is output by gate G10 in overspeed condition, transistors T2 and T3 are not turned ON. Referring now to AND gate Gil, in an underspeed condition, the output of gate G12 will be high when the inverted output of device Ul provided to pin 2 of gate Gil is at its low-state, Thus, the output of AND gate Gil is at its low-state in an underspeed condition, so that no high-state control signal is provided to transistors T4 and T5. Thus, transistors T4 and T5 do not conduct in an underspeed condition. In an overspeed condition, the output of AND gate Gil is at its high-state since the output of gate G12 and the inverted output of device Ul are both in their high-state at the same time. In the overspeed condition, gate Gil outputs a control signal to turn ON transistors T4 and T5. Motor current is thus provided to motor Ml, and the engine throttle is at least partially closed to reduce the engine speed. As in the Fig. 1 embodiment, the embodiment of Fig. 2 also delays the response of the governor to an underspeed condition during engine warm-up. The circuit which achieves this function consists of AND gate G13, resistor R20, capacitor C14, and resistor R21. This circuit operates as follows. During engine warm-up, the input to pin 8 of gate G13 remains at its low-state until capacitor C14 becomes sufficiently charged through resistor R20. When pin 8 of gate G13 is low, the output of gate G13 remains low, so that transistor T3 does not conduct. However, some motor current is still provided to DC motor Ml through transistor T2 and resistor R22. Once capacitor C14 has become sufficiently charged, pin 8 of gate G13 goes high. When the input at pin 9 of gate G13 is also high, which occurs in an underspeed condition, the output of gate G13 is controlled by gate G10, so that the conduction of transistor T3 is controlled by gate G10 in the usual manner. The other optional circuit in Fig. 2 operates in the following manner. When the actual speed is slightly below the desired or reference speed, the amplitude of the control signal is limited to prevent unnecessary cycling of the engine. When the actual engine speed is slightly less than the reference speed, the output at pin 11 of AND gate G10 goes high. Capacitor C15 is then charged through resistor R23, keeping pin 9 of gate G13 low until capacitor C15 is sufficiently charged. Transistor T3 is thus prevented from conducting until capacitor C15 becomes sufficiently charged, since the output of gate G13 is in its low-state and no high-state control signal is generated to transistor T3. After a short time delay, capacitor C15 becomes sufficiently charged, so that pin 9 of gate G13 goes to its high-state. Since pin 8 of gate G13 is also at its high-state after engine warm-up, the output of AND gate G13 then goes to its high-state, thereby turning ON transistor T3. Transistor T2 is also turned ON at the same time since the output of AND gate G10 is also high. Thus, current flows through motor Ml to rotate the shaft of motor Ml, thereby partia ly opening the engine throttle. While the preferred embodiment of the present invention has been shown and described, alternate embodiments will be apparent to those skilled in the art and are within the scope of the present invention. Therefore, the invention is to be limited only by the following claims.

Claims: CLAIMS 1. A speed governor for controlling the actual speed of a device, comprising: input means for receiving a periodic signal indicative of the actual speed of the device; first means for generating a pulsed speed, signal that is functionally related to said periodic signal, said pulsed speed signal having a pulse width that is functionally related to said actual speed; second means for generating a pulsed reference signal having a pulse width that is functionally related to a desired speed; means for comparing said pulsed speed signal with said pulsed reference signal, and for generating a pulsed error signal having a pulse width that is functionally related to a difference between said speed signal pulse width and said reference signal pulse width; and means for changing the speed of the device as a function of said error signal. 2. The speed governor of claim 1, further comprising: signal conditioning means for receiving said periodic signal from said input means and for generating a pulsed DC signal to said first generating means. 3. The speed governor of claim 2, wherein said signal conditioning means includes a timer. 4. The speed governor of claim 1, further comprising: means for determining whether said actual speed is above or below said desired speed, and for generating a control signal to said speed changing means that is indicative of said determin ' .on and that is functionally related to said error signa. ulse width. 5. The speed governor of claim 1, further comprising: means for controlling the increase of the device speed during warm-up of the device. 6. The speed governor of claim 5, wherein said controlling means includes a time delay circuit. 7. The speed governor of claim 1, further comprising: means for limiting the changing of said device speed when the width of said error signal pulse is less than a predetermined value. 8. The speed governor of claim 7, wherein said limiting means includes: a time delay circuit; and a semiconductor switch. 9. The speed governor of claim 1, wherein said speed changing means includes a reversible DC motor. 10. The speed governor of claim 9, wherein said speed changing means includes a bridge network that determines the amount of rotation of said DC motor as a function of said error signal. 11. The speed governor of claim 9, wherein said reversible DC motor is interconnected with a throttle of an internal combustion engine. 12. The speed governor of claim 1, further comprising: a coil that outputs said periodic signal. 13. The speed governor of claim 1, wherein said periodic signal is an alternating signal output by said device. 14. The speed governor of claim 13, wherein said device is an internal combustion engine having a primary ignition winding, and wherein said alternating signal is output by said primary ignition winding. 15. The speed governor of claim 1, wherein said periodic signal is a pulsed DC signal. 16. The speed governor of claim 1, wherein said second generating means includes: a resistor and capacitor that determine the pulse width of said pulsed reference signal. 17. The speed governor of claim 1, wherein said first generating means includes a divide-by-two circuit. 18. The speed governor of claim 1, wherein said second generating means includes a timer. 19. The speed governor of claim 1, wherein said comparing means includes a logic gate.. 20. The speed governor of claim 1, wherein said determining means includes two logic gates.

Inventors: DYKSTRA RICHARD A, MITCHELL ROBERT K, DYKSTRA, RICHARD, A., MITCHELL, ROBERT, K.
Applicants: BRIGGS & STRATTON CORP, BRIGGS & STRATTON CORPORATION
Application year: 1995
Main classification: H02P5
IPC codes: F02D31, H02P7