Static type of semiconductor memory device having great low voltage operation margin

Abstract: A static type of semiconductor memory device includes a power supply line (VCC) for supplying a power supply voltage, a pair of bit lines (DG1, DG1*), a word line, and a memory cell (4) connected to the word line and the pair of bit lines via transfer gates of MOS transistors (Q109, Q111). The power supply voltage is boosted up to provide the boosted voltage on a boosted voltage line. A predetermined voltage is supplied to the word line using the boosted voltage and a write operation or read operation is performed to the memory cell via the pair of bit lines when the predetermined voltage is supplied on the word line. The predetermined voltage is approximately equal to a sum of the power supply voltage and a threshold voltage of the MOS transistor, resulting in a great low voltage operation margin.

Description: Background of the Invention 1. Field of the Invention The present invention relates to a static type of semiconductor memory device, and more particularly, to a static type of semiconductor memory device including a boosting circuit for boosting the voltage of a word line higher than a power supply voltage. 2. Description of Related Art Recently, a semiconductor integrated circuit shifts quickly to allow a low voltage operation, for example, 3.3V operation or 3.0V operation because of needs from users and the increase of reliability of the semiconductor integrated circuit itself. A static type of semiconductor memory device is not excluded and a manufacturing maker develops the products of the low voltage operation specification. The technique for boosting the potential of a word line higher than a power supply voltage in the static type of semiconductor memory device is reported by K. Kozuru, M. Ukita, S. Murakami, Y. Morooka, Y. Nishimura, K. Anami in "A Boost Circuit for Low Supply Voltage" (Proc. of the 1993 IEICE Spring Conference, C-622, p. 5-252). In this technique, as shown in Fig. 1, the static type of semiconductor memory device includes a word line boosting circuit 102 for boosting up the power supply voltage V CC to a voltage V BST , a word line driving circuit 103 for driving a word line WL in accordance with an input address to supply the voltage V BST to the word line WL, a pair of bit lines DG1 and DG1* (this means the inverted signal of DG1), and a memory cell circuit 104 connected to the word line WL and the pair of bit lines DG1 and DG1* via transfer gates. The boosting circuit 102 generates the boosted voltage V BST from the power supply voltage V CC to supply to the word line driving circuit 103. The circuit 103 supplies the boosted voltage V BST on the word line WL in accordance with the input address. The memory cell circuit 104 includes a memory cell and is accessed via the pair of bit lines DG1 and DG1* when the boosted voltage V BST is supplied to the word line W1. The word line boosting circuit 102 is shown in Fig. 2 in detail. Referring to Fig. 2, the circuit 102 is constituted of an inverter 121 for inputting a signal  BST , a P-channel MOS transistor Q102 connected between the power supply voltage V CC line and the boosted voltage V BST line and a P-channel Q103 connected to the boosted voltage V BST line, an N-channel MOS transistor Q104 connected between the P-channel MOS transistor Q103 and the ground potential, and a boosting up capacitor C BST between the output of the inverter 121 and the boosted voltage V BST line. Note that a parasitic capacitor C PAR is the capacitor parasitizing the boosted voltage V BST line. The signal BST is connected to the node between the gates of the MOS transistors Q103 and Q104 the gate of the MOS transistor Q102 is connected to the MOS transistors Q103 and Q104. When the signal  BST is in the high level, the output of the inverter 121 is the low level so that the capacitor C BST is charged from the power supply voltage V CC via the P-channel MOS transistor Q102. When the signal  BST is in the low level, the output of the inverter 121 is the high level, so that the potential of the capacitor C BST is arisen higher than the power supply voltage V CC . Fig. 6 shows a relation of the boosted voltage V BST , i.e., the word line voltage to the power supply voltage V CC . As seen from the figure, the boosted voltage V BST becomes greater as the power supply voltage V CC is increased. The above-mentioned word line driving circuit 103 is shown in Fig. 3 in detail. Referring to Fig. 3, the driving circuit 103 is constituted of a NAND circuit 131 for inputting an address signal and a word line activation signal  WL , an N-channel MOS transistor Q105 connected to the output of the NAND circuit 131 and having the gate always supplied with the power supply voltage V CC , a P-channel MOS transistor Q106 connected between the boosted voltage V BST line and the MOS transistor Q105 on the opposite side of the NAND circuit 131 and a P-channel MOS transistor Q107 connected to the boosted voltage V BST line and the word line WL, and an N-channel MOS transistor Q108 connected between the word line WL and the ground potential GND. The gate of the MOS transistor Q106 is connected to the word line WL and the gates of the transistor Q107 and Q108 are connected to the transistor Q105 together with the transistor Q106. When the word line WL is selected in accordance with the address signal and the activation signal  WL , i.e., when the output of the NAND circuit 131 is the low level, the N-channel MOS transistor Q108 is turned off so that the boosted voltage V BST is supplied to the word line WL through the P-channel MOS transistor Q107. On the other hand, when the word line WL is not selected, i.e., when the output of the NAND circuit 131 is the high level, the N-channel MOS transistor Q108 is turned on and the P-channel MOS transistor Q106 is also turned on. Therefore, the P-channel MOS transistor Q107 is turned off so that the word line WL is in the ground or low level. Fig. 4 is a diagram showing an equivalent circuit of a typical memory cell circuit for storing memory information in the static type of semiconductor memory device. In the figure, a load resistor R101 is connected to the drain of an N-channel MOS transistor Q110 and the gate of an N-channel MOS transistor Q112, and a load resistor R102 is connected to the drain of the N-channel MOS transistor Q112 and the gate of the N-channel MOS transistor Q110. The sources of the N-channel MOS transistors Q110 and Q112 are connected to the ground potential. As a result, a flip-flop circuit is constituted. The node N1 between the load resistor R101 and the drain of the N-channel MOS transistor Q110 and the node between the load resistor R102 and the drain of the N-channel MOS transistor Q112 are connected to the bit lines DG1 and DG1* through the N-channel MOS transistors Q109 and Q111 as transfer gates, respectively. The gates of the N-channel MOS transistors Q109 and Q111 are connected to the word line WL. By arranging as described above, data of "1" or "0" can be arbitrarily stored at the nodes N1 and N2. In this case, the write operation or read operation to or from the nodes N1 and N2 are performed by setting the word line WL in a high level and selecting the bit lines DG1 and DG1*. Whether or not the low voltage operation is allowed in the write operation in the static type of semiconductor memory device is determined based on a low voltage operation margin. For instance, in a case where data of "1" is written in the memory cell shown in Fig. 4, the power supply voltage V CC is applied to the word line WL and the bit line DG1 and a ground voltage GND is applied to the bit line DG1*, if the boosting circuit 102 is not present. In this case, the potential of the node N1 changes to a level of (V CC - V TN ) immediately after the voltage is applied, where V TN is a threshold voltage of the N-channel MOS transistor Q109 or Q111 as the transfer gate. When a sufficiently long time (of an order of ms to sec.) elapses after the write operation, the potential of the node N1 reaches the V CC level by the load resistor R101 in the memory cell. In the normal operation (shorter than 10 nS), however, the potential is kept to be in the level of about (V CC - V TN ). Therefore, in the low voltage operation, i.e., when the power supply voltage is low, the low voltage operation is further difficult, because the influence of the threshold voltage V TN to the write level becomes greater in relation to the power supply voltage V CC . Therefore, by employing the word line boosting circuit 102 as in the conventional static type of semiconductor memory device shown in Fig. 1, the voltage of word line WL can be boosted upper than the power supply voltage V CC , so that the large low voltage operation margin is allowed. As a result, the potential of the storage node N1 immediately after the write operation can be increased. The operation of the conventional static type of semiconductor memory device including the word line boosting circuit 2 will be described below with reference to Fig. 5. Fig. 5 shows the operation waveforms in the conventional static type of semiconductor memory device. Referring to Fig. 5, first, at the time 0, since the signal  BST is in the V CC level, the P-channel MOS transistor Q103 of the word line boosting circuit 102 is in the off state, and the P-channel MOS transistor Q102 and the N-channel MOS transistor Q104 are in the on state. Accordingly, the boosted power supply voltage V BST is charged up to the V CC level. Next, at the time t1, since the signal  BST starts to be inverted from the V CC level to the ground (GND) level. In response to the signal  BST , the P-channel MOS transistor Q103 gradually changes to the on state and the P-channel MOS transistor Q102 and the N-channel MOS transistor Q104 gradually changes to the off state. At the same time, the output of the inverter 121 starts to rise from the GND level toward the V CC level. That is, the potential of the boost up capacitor C BST starts to rise upwardly from the V CC level. Accordingly, the boosting up effect appears at the time t2. The boosting up operation is performed until the boosted voltage reaches the voltage of (V CC + Vα) at the time t3. Note that Vα varies based on a ratio of boost up capacitor C BST and parasitic capacitor C PAR . If C BST » C PAR , Vα is approximately equal to the power supply voltage V CC . Next, a word line activation signal  WL changes from the GND level to the V CC level at the time t4. In response to the change of the signal  WL , the P-channel transistor Q107 of the word line driving circuit 103 goes to the on state and the P-channel MOS transistor Q106 and the N-channel MOS transistor Q108 goes to the off state. The voltage of the word line WL rises from the time t5 and reaches the voltage of (V CC + Vα) at the time t6. As described above, in the conventional static type of semiconductor memory device, if the ratio of the boost up capacitor C BST and the parasitic capacitor C PAR is set out of a target range because of the variation of the manufacturing process, the boosted voltages V BST of the word lines also arises. Therefore, it is difficult to adjust the boosted voltage V BST of the word line to a predetermined target voltage. If the ratio of the boost up capacitor C BST and the parasitic capacitor C PAR is changed because of variation of the manufacturing process, there would be cases that the word line is boosted higher or lower than the predetermined voltage. In a case where the boosted voltage of the word line WL is lower than the target voltage, the voltage of storage node is lower than the power supply voltage V CC immediately after the write operation, so that the low voltage operation margin is decreased. On the other hand, in a case where the boosted voltage of the word line WL is higher than the target voltage, the voltage of storage node is approximately equal to the power supply voltage V CC immediately after the write operation. However, the low voltage operation margin would be decreased. For this reason, the manufacturing process must be determined with a great margin. Further, even if the boosted voltage V BST of the word line can be adjusted to the predetermined voltage, it is difficult to apply the semiconductor memory device to a power supply such as battery whose voltage varies, because the boosted voltage V BST of the word line is not constant over the wide range of power supply voltage. DE 43 32 452 discloses a circuitry and method for clamping a boost signal, wherein a clamping circuit clamping a boost signal supplied on a boost line includes a p-channel MOS transistor and an n-channel MOS transistor. These MOS transistors are serially connected between an internal power supply line and the boost line. P-channel MOS transistor receives a clamping level control signal from a clamp control circuit at its gate. In accordance with the clamping level control signal a clamping level given by clamping circuit is varied. Therefore, by decreasing the clamping level of the boost line during an overvoltage-applied mode such as burn-in test, deterioration of components due to an overvoltage can be prevented. Summary of the Invention Therefore, an object of the present invention is to eliminate the above problems and to provide a static type of semiconductor memory device in which the boosted voltage of the word line can be adjusted to a predetermined voltage, e.g., a voltage of about (V CC + V TN ) in the wide range of power supply voltage and a method for regulating the boosted voltage, thereby to provide a great low voltage operation margin. The present invention is defined in independent claims 1 and 6. The dependent claims define particular preferred embodiments of the invention. Brief Description of the Drawings Fig. 1 is a block diagram of the structure of a conventional static type of semiconductor memory device; Fig. 2 is a circuit diagram of a word line boosting circuit of Fig. 1; Fig. 3 is a circuit diagram of a word line driving circuit of Fig. 5; Fig. 4 is a circuit diagram of a memory cell circuit of Fig. 5; Fig. 5 is operation waveform diagrams of the conventional static type of semiconductor memory device of Fig. 1; Fig. 6 is a graph showing a relation of the word line voltage and the power supply voltage in the conventional semiconductor memory device of Fig. 1; Fig. 7 is a block diagram of a static type of semiconductor memory device according to a first embodiment of the present invention; Fig. 8 is a graph showing a relation of the word line voltage and the operation voltage lower limit in a static type of semiconductor memory device when the present invention is not applied; Fig. 9 is operation waveform diagrams of the static type of semiconductor memory device according to the first embodiment of the present invention; Fig. 10 is a graph showing a relation of the word line voltage and the power supply voltage in the semiconductor memory device according to the first embodiment of the present invention; and Fig. 11 is a block diagram of a static type of semiconductor memory device according to another embodiment of the present invention. Description of the Preferred Embodiments A static type of semiconductor memory according to the present invention will be described below with reference to the accompanying drawings. Fig. 7 is a block diagram of the static type of semiconductor memory device according to the first embodiment of the present invention. Referring to Fig. 7, the static type of semiconductor memory device includes a word line boosting circuit 2 for boosting up a power supply voltage V CC to a voltage V BST higher than the voltage V CC , a word line driving circuit 3 for driving a word line WL to supply the boosted voltage V BST to the word line WL, a suppression circuit 1 connected between the boosted voltage V BST and the power supply voltage V CC , for regulating the boosted voltage to a predetermined voltage, i.e., a voltage of (V CC + V TN ) in the embodiment, and a memory cell circuit 4 connected to the word line WL and a pair of bit lines DG1 and DG1* (the symbol "*" means the inversion). The word line boosting circuit 2, word line boosting circuit 3 and memory cell circuit 4 may have the same structures as those shown in Figs. 2, 3, 4. The structures are already described in detail and, therefore, the description is omitted here. The suppression circuit 1 is composed of an N-channel MOS transistor Q1 in this embodiment. The MOS transistor Q1 has a gate and drain connected to the boosted voltage V BST and a source connected to the power supply voltage V CC . Accordingly, when the boosted voltage V BST supplied from the word line boosting circuit 2 is too higher than the voltage of (V CC + V TN ), the N-channel MOS transistor Q1 is turned on, so that the boosted voltage V BST is suppressed or regulated to be approximately equal to the voltage (V CC + V TN ). The voltage V TN is a threshold voltage of the transfer gate Q109 or Q111 in Fig. 4. A relation between the word line voltage and an operation voltage lower limit V CCMIN is simulated. The result is shown in Fig. 8. As shown in Fig. 8 by a dashed line A, as the word line voltage is increased, the operation voltage lower limit is decreased. However, when the word line voltage exceeds the voltage of (V CC + V TN ), the effect of increase of the word line voltage saturates. On the other hand, a ratio of current flowing through the N-channel MOS transistor Q110 in Fig. 4 to current flowing through the N-channel MOS transistor Q109 is aimed to be 5 : 1, for example. However, as the word line voltage is increased, the ratio becomes small, as shown in Fig. 8 by a dashed line B. As a result, the operation voltage lower limit has an optimal value at the word line voltage of about (V CC + V TN ). In other words, at the voltage, the lower voltage operation margin is maximum. That is, the voltage of the word line WL is desirably boosted to the voltage of about (V CC + V TN ) for the above reasons. The operation of the first embodiment will be described below with reference to Fig. 9, wherein the word line boosting circuit 2, word line driving circuit 3 and memory cell circuit are the same as those shown in Figs. 2, 3 and 4. Fig. 9 is operation waveforms of the first embodiment of the present invention. Referring to Fig. 9, first, at the time 0, when the signal  BST is in the V CC level, the P-channel MOS transistor Q103 of Fig. 2 is in the off state, and the P-channel MOS transistor Q102 and the N-channel MOS transistor Q104 are in the on state. Also, the output of the inverter 121 is in the GND level. Accordingly, the boost up capacitor C BST is charged to the V CC level. Next, at the time t1, the signal  BST starts to be inverted from the V CC level to the GND level. In response to the signal  BST , the P-channel MOS transistor Q103 gradually changes to the on state and the P-channel MOS transistor Q102 and the N-channel MOS transistor Q104 gradually changes to the off state. At the same time, the output of the inverter 121 starts to rise from the GND level toward the V CC level. That is, the boost up capacitor C BST is arisen from the V CC level. Accordingly, the boosting up effect appears at the time t2 and the boosting up operation is performed until the boosted voltage V BST reaches the voltage of (V CC + Vα) at the time t3. At that time, the boosted voltage V BST is suppressed to be approximately equal to voltage of (V CC + V TN ) by the N-channel MOS transistor Q1 of Fig. 7. Next, at the time t4, the word line activation signal  WL rises from the GND level to the V CC level so that the P-channel MOS transistor Q107 of Fig. 3 goes to the on state and the P-channel MOS transistor Q106 and N-channel MOS transistor Q108 goes to the off state. The voltage of the word line WL rises from the time t5 and reaches the voltage of (V CC + V TN ) at the time t6. Fig. 10 is a diagram showing a relation between the word line voltage and the power supply voltage in the fist embodiment of the present invention. The figure shows that the voltage of the word line WL is adjusted to be in the vicinity of the voltage of (V CC + V TN ) over the wide range of power supply voltage because the boosted voltage V BST is suppressed to be approximately equal to the voltage of (V CC + V TN ) by the N-channel MOS transistor Q1. Fig. 11 is a block diagram of the static type of semiconductor memory device according to another embodiment of the present invention. In the figure, the static type of semiconductor memory device has the same structure as that of the first embodiment of the present invention shown in Fig. 7 except for a suppression circuit 5 provided between the power supply voltage V CC and the boosted voltage V BST . In the suppression circuit 5, diodes D1 and D2 are used in place of the N-channel MOS transistor Q1 in the suppression circuit 1. The same components are assigned with the same reference numerals or symbols. Also, the components operates in the same manner as the components having the same reference numerals or symbols in the static type of semiconductor memory device according to the first embodiment of the present invention. If the forward direction voltage V f of the diodes D1 and D2 in the suppression circuit 5 has the relation of V TN ≒ 2V f , the voltage of the word line WL can be set to the voltage of about (V CC + V TN ). Alternatively, the same effect can be obtained even if the a zener diode is used in place of the diodes D1 and D2. In this manner, in the static type of semiconductor memory device having the word line boosting circuit 2 for the voltage of the word line WL higher than the power supply voltage V CC , the boosted voltage V BST of word line WL can be regulated to be in the vicinity of the voltage of (V CC + V TN ) by connecting the N-channel MOS transistor Q1 or the diodes D1 and D2 to suppress the word line WL voltage to the voltage close to (V CC + V TN ), i.e., the voltage obtained by adding the threshold voltage V TN of the transfer gate Q109 or Q111 in the memory cell to the power supply voltage V CC . As a result, the low voltage operation margin can be increased. In the embodiments of the present invention, the N-channel MOS transistor Q1 or diodes D1 and D2 are used as means for suppressing the boosted voltage of the word line WL to be in the vicinity of the voltage of (V CC + V TN ). However, the present invention is not limited to these elements. Alternatively, other means such as a zener diode may be used.

Claims: A static type of semiconductor memory device comprising: a power supply line for supplying a power supply voltage (V CC ); a static type of memory cell (4) having a flip-flop which is composed of two load resistors (R101, R102) and two driving MOS transistors (Q110, Q112) respectively connected to said two load resistors, wherein said two load resistors are connected to said power supply line, transfer MOS transistors (Q109, Q111) are provided between output terminals (N1, N2) of said flip-flop and bit lines (DG1, DG1 ), respectively, and gates of said transfer MOS transistors are connected to a word line (WL); a boosting circuit (2) for boosting said power supply voltage (V CC ); a word line driving circuit (3) for driving said word line (WL) with a boosted voltage (V BST ) supplied from said boosting circuit (2); and a voltage control circuit (1) for controlling said boosted voltage to be in the neighborhood of a predetermined voltage (V CC + V TN ) such that a ratio of current flowing through one of said driving MOS transistors (Q110, Q112) in an on state to current flowing through one of said transfer MOS transistors (Q109, Q111) is set to a desired value. A static type of semiconductor memory device according to claim 1, wherein said voltage control circuit (1) is provided between said boosting circuit (2) and said power supply line (VCC). A static type of semiconductor memory device according to claim 1 or 2, wherein said predetermined voltage (V CC + V TN ) is approximately equal to a sum of said power supply voltage (V CC ) and a threshold voltage (V TN ) of one of said transfer MOS transistors (Q109, Q111). A static type of semiconductor memory device according to claim 2, wherein said voltage control circuit (1) comprises an N-channel MOS transistor (Q1) having a gate and drain connected to said boosting circuit (2) and a source connected to said power supply line (V CC ). A static type of semiconductor memory device according to claim 2, wherein said voltage control circuit (1) comprises diodes (D1, D2) connected in series, an anode of the first diode (D2) being connected to said boosting circuit (2) and a cathode of the last diode (D1) being connected to said power supply line (V CC ). A method of providing a great low voltage operation margin in a static type of semiconductor memory device, comprising the steps of: providing in a static type of memory cell (4) a flip-flop which is composed of two load resistors (R101, R102) and two driving MOS transistors (Q110, Q112) respectively connected to said two load resistors, wherein said two load resistors are connected to a power supply line, transfer MOS transistors (Q109, Q111) are provided between output terminals (N1, N2) of said flip-flop and bit lines (DG1, DG1 ), respectively, and gates of said transfer MOS transistors are connected to a word line (WL); boosting the power supply voltage (V CC ) to provide boosted voltage (V BST ) on a boosted voltage line; regulating said boosted voltage to a predetermined voltage (V CC + V TN ), supplying the predetermined voltage to the word line ; and performing a write operation or read operation to the memory cell via the pair of bit lines when the predetermined voltage is supplied on the word line, wherein the predetermined voltage supplied on the word line is such that a ratio of current flowing through one of said driving MOS transistors (Q110, Q112) in an on state to current flowing through one of said transfer MOS transistors (Q109, Q111) is set to a desired value. A method according to claim 6, wherein the predetermined voltage (V CC + V TN ) is approximately equal to a sum of the power supply voltage (V CC ) and a threshold voltage (V TN ) of one of said transfer MOS transistor (Q109, Q111). A method according to claim 6, wherein said regulating step includes flowing current from the boosted voltage line to the power supply line such that a voltage drop is approximately equal to a threshold voltage of an N-channel MOS transistor (Q1) between the boosted voltage line and the power supply line.

Inventors: YAMAGUCHI TAKASHI, YAMAGUCHI, TAKASHI, YAMAGUCHI, TAKASHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1995
Main classification: G11C11
IPC codes: G11C11, G11C8