Power amplifier

Abstract: A power amplifier comprises a first amplifier circuit (100a) connected between an input terminal (IN) and an output terminal (OUT) and comprising a first amplifier FET (A2) and a first matching circuit (M2), and a second amplifier circuit (100b) connected between the input terminal (IN) and the output terminal (OUT) and comprising a second amplifier FET (A3), a second matching circuit (OM3), and a switching circuit (SW3). In this power amplifier, the first amplifier circuit (A2) outputs an output signal of a first power level when the first amplifier FET (A2) is operated while the second amplifier FET (A3) is not operated and the switching circuit (SW3) is turned off, and the second amplifier circuit (A3) outputs an output signal of a second power level when the first amplifier FET (A2) is not operated while the second amplifier FET (A3) is operated and the switching circuit (SW3) is turned on. Therefore, impedances of the output side matching circuits (M2,OM3) of the first and second amplifier circuits (100a,100b) which output amplified signals of different power levels can be optimized with high precision. As the result, in both the high-power output operation and the low-power output operation, the efficiencies of the first and second amplifier circuits (100a,100b) are significantly improved.

Description: FIELD OF THE INVENTION The present invention relates to power amplifiers and, more particularly, to an improvement in efficiency of a power amplifier used in a transmitter of a portable telephone. BACKGROUND OF THE INVENTION In recent years, with the spread of portable telephones, mobile communication systems utilizing analog or digital modulation have been extensively developed. Since portable telephones use batteries as power source, to reduce the power consumption is very important for the long-time operation. In a portable telephone, a power amplifier amplifies a signal amplitude to an antenna output, and the power consumption of the power amplifier amounts to 70 - 80 % of the total power consumption of the portable telephone. Therefore, it is very important for the reduction in the power consumption to increase the efficiency of the power amplifier. Figure 10 is a block diagram illustrating a structure of a transmitter of an ordinary analog modulation (frequency modulation) type portable telephone. In the figure, a control circuit 1 controls a voltage-controlled crystal oscillator 2 (hereinafter referred to as a VCXO) in response to speech signal data (hereinafter referred to as IN-data). The VCXO 2 performs frequency modulation in response to the IN-data and outputs a frequency modulated signal (hereinafter referred to as FM signal) in the intermediate frequency band (hereinafter referred to as IF band) to a mixer 3. A frequency synthesizer 4 produces a carrier wave signal in the radio frequency band (hereinafter referred to as RF band) and outputs the signal to the mixer 3. The mixer 3 mixes the FM signal in the IF band with the carrier wave signal in the RF band to convert the FM signal in the IF band into an FM signal in the RF band. A band-pass filter (hereinafter referred to as BPF) 5 eliminates unnecessary waves caused by the frequency conversion from the FM signal in the RF band. A power amplifier 6 amplifies the power level of the FM signal in the RF band to a power level of an antenna output. A BPF 7 eliminates unnecessary waves caused by the amplification from the FM signal and transmits a signal in a frequency band for transmission. The signal transmitted through the BPF 7 is radiated into space from an antenna 9. On the other hand, signals received by the antenna 9 are applied to a BPF 8. The BPF 8 transmits only a signal in a frequency band to be received by a receiving circuit 10. The BPF 8 and the receiving circuit 10 are constituents of a receiver. Figure 11 is a block diagram illustrating the power amplifier 6 in more detail. An input terminal IN of the power amplifier 6 is connected through an input matching circuit M1 to an input end of a driver stage A1 for driving an output amplifier stage A2. An output end of the driver stage A1 is connected through an inter-stage matching circuit M12 and an AC coupling capacitor C1 to an input end of the output amplifier stage A2. An output end of the output amplifier stage A2 is connected through an output matching circuit M2 to an output terminal OUT. The driver stage A1 comprises an FET having a gate bias terminal Vg1 and a drain bias terminal Vd1, and the output amplifier stage A2 comprises an FET having a gate bias terminal Vg2 and a drain bias terminal Vd2. Generally, in transmitters of portable telephones, an output power exceeding 1W is required for the analog modulation (frequency modulation). In order to improve the efficiency in the high-power output operation exceeding 1W, various means, such as harmonic processing techniques, have been adopted in the design of the power amplifier. However, the transmitter of the portable telephone operates at a high power level near the maximum power level when it is used in a place far from the base station. On the other hand, when the transmitter is used in a place near the base station, it is preferable that the transmitter should be used at a low power level, for example, 10 - 20 dB reduced per 1W, to increase the lifetime of the battery. That is, it is desired to reduce the current consumption of the power amplifier of the transmitter. In order to realize the low-power output operation of the transmitter, in the prior art power amplifier 6 shown in figure 11, bias voltages applied to the gate bias terminals Vg1 and Vg2 and the drain bias terminals Vd1 and Vd2 of the driver stage A1 and the output amplifier stage A2 are controlled to reduce the current consumption of the output amplifier stage A2 which consumes most power in the low-power output operation. Although the input power applied to the input terminal IN of the power amplifier 6 is usually constant, the input power may be controlled to realize the low-power output operation of the power amplifier 6. Figure 12 is a graph illustrating a relationship between the output power and the current consumption when the gate bias voltages applied to the gate bias terminals Vg1 and Vg2 and the drain bias voltages applied to the drain bias terminals Vd1 and Vd2 are controlled in the prior art power amplifier 6. In the graph, a point A denotes the current consumption when the output power is 1W, a point B denotes the current consumption when the output power is 100mW (1W - 10dB), and a point C denotes the current consumption when the output power is 10mW (1W - 20dB). Figure 13 is a graph illustrating the input power vs. output power characteristics and the input power vs. power added efficiency characteristics of the power amplifier 6. In the graph, continuous lines X1 and X2 show the input power vs. output power characteristics in the high-power output operation and the low-power output operation of the power amplifier 6, respectively, and dotted lines Y1 and Y2 show the input power vs. power added efficiency characteristics in the high-power output operation and the low-power output operation of the power amplifier 6, respectively. Further, points a1 and a2 show the output power and the power added efficiency at the point A of figure 12, respectively, and points c1 and c2 show the output power and the power added efficiency at the point C of figure 12, respectively. The input power to a1, a2, c1, and c2 is fixed at a prescribed value Δ. As shown in figure 13, in the prior art power amplifier, a high-efficiency operation with the power added efficiency of 50 - 60 % is realized by a higher harmonic processing circuit or the like included in the matching circuit M2 during the high-power output operation (point A in figure 12). However, in the low-power output operation (point C in figure 12), the efficiency is significantly reduced to several percent. The reason of the reduction in the efficiency is described hereinafter. Even when the drain bias voltage is reduced to reduce the current consumption by the power amplifier 6, since the voltage supplied from the battery is fundamentally constant, the power consumption with respect to DC and viewed from the battery side depends on the reduction in the current only. In addition, since the gate width of the FET of the output amplifier stage A2 is increased to improve the efficiency in the high-power output operation, the control of the drain bias voltage alone is not enough for a significant reduction in the current consumption. For example, when the drain voltage is reduced while maintaining the operation of the FET, the current consumption exceeds 100 mA. As described above, although the prior art power amplifier 6 operates efficiently while the high-power, almost the maximum power, output operation, the efficiency is significantly reduced while the low-power output operation. In order to solve the above-described problem, Japanese Published Patent Application No. Hei. 3-104408 discloses a power amplifier in which a plurality of amplifier circuits providing different amplified outputs are connected in parallel between an input terminal and an output terminal and voltages applied to the amplifier circuits are controlled. Figure 14 is a block diagram illustrating the power amplifier. The power amplifier comprises three amplifier circuits connected in parallel with each other between an input terminal IN and an output terminal OUT. A first amplifier circuit comprises an amplifier FET 11a, an input side matching circuit 12a, and an output side matching circuit 13a. A second amplifier circuit comprises an amplifier FET 11b, an input side matching circuit 12b, and an output side matching circuit 13b. A third amplifier circuit comprises an amplifier FET 11c, an input side matching circuit 12c, and an output side matching circuit 13c. A control circuit 16 is connected between a power supply 15 and gate electrodes of the respective FETs 11a to 11c and controls voltages applied to the gate electrodes of the FETs. A power supply 14 is connected to drain electrodes of the respective FETs 11a to 11c. In this prior art power amplifier, the amplifier FETs 11a to 11c are selectively driven by the control circuit 16, whereby the power level of the amplified output applied to the output terminal OUT is changed. In addition, these amplifier FETs are designed so as to operate efficiently. Therefore, a plurality of amplified outputs with different power levels are obtained. In this prior art power amplifier, however; the matching circuits 13a and 13b on the output side of the amplifier FETs 11a to 11c are directly connected to the output terminal OUT as shown in figure 14. In this case, when the amplifier FET 11a is driven while the amplifier FETs 11b and 11c are not driven, not only the matching circuit 13a for the amplifier FET 11a that outputs amplified signals but also the matching circuits 13b and 13c for the amplifier FETs 11b and 11c that do not output amplified signals are electrically connected to the output terminal OUT. Therefore, in order to selectively operate those three amplifier FETs efficiently, the impedance of the output side matching circuit for the operated, i.e., selected, amplifier FET has to be controlled so as to have an optimum load curve along which the amplifier FET operates efficiently, while considering the impedances of the unselected amplifier FETs and the output side matching circuits therefor. However, it is very difficult to set the impedance of the output side matching circuit for the selected amplifier FET while considering the impedances of the output side matching circuits for the unselected amplifier FETs because the impedance of one matching circuit varies with a variation in the impedance of the other matching circuit. Actually, it is difficult to selectively operate the amplifier FETs providing different amplified outputs with high efficiency. Furthermore, since the amplifier circuit in which the amplifier FET is operated is electrically connected to the amplifier circuit in which the amplifier FET is not operated, a feedback loop is produced between these amplifier circuits, resulting in an incidental oscillation. Further information relating to the prior art can be found in US 4,598,252 which describes a power amplifier having plural parallel amplification circuits of different gains selectively actuable to zero and maximum gains, and electronic switches to select a circuit for connection to a common output junction. The power outputs of the parallel connected amplifiers vary in a binary scheme to allow the total gain to be adjusted in binary steps. One or several of the parallel connected amplifiers can be in operation and connected to the common output simultaneously. Unused amplifier output is isolated from the common output. The phase through each channel is matched for proper summing to occur without degradation. JP 4269013 A discloses transmitting equipment and its power amplification circuit for transmitting an AM signal at one power level and an FM or PM signal at another power level, both with high efficiency. In particular, said document teaches that matching networks, which match the impedance of a power amplifier with an impedance of a load, are connected to said power amplifier, and switched between different operation modes through drive control over switches, according to the kind of modulation of a modulated carrier to be transmitted. The 1 st operation mode corresponds to AM, and the 2nd operation mode corresponds to fixed amplitude modulation, such as FM and PM. The switches make a choice between the matching networks, which are different in impedance or varies the impedance of a common matching network, so as to obtain maximum efficiency in each operation mode, and then match the impedance in either operation mode. SUMMARY OF THE INVENTION It is an object of the present invention to provide a power amplifier including a plurality of amplifier circuits outputting amplified signals of different power levels, in which each amplifier circuit is selectively operated with high efficiency. It is another object of the present invention to provide a power amplifier including a plurality of amplifier circuits outputting amplified signals of different power levels, in which each amplifier circuit is selectively operated with high efficiency and no feedback loop is produced between an operated amplifier circuit and an unoperated amplifier circuit. It is still another object of the present invention to provide a power amplifier including a single amplifier circuit, in which the amplifier circuit always operates with high efficiency and the power level of the amplified output from the amplifier circuit is varied by controlling the power supply voltage. Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description. In accordance with the invention, these objects are achieved by the power amplifier defined in claim 1. Preferred embodiments of the invention are defined in the dependent claims. According to a first aspect of the present invention, a power amplifier comprises an input terminal to which an input signal to be amplified is applied; an output terminal from which an amplified signal is output; a first amplifier circuit connected between the input terminal and the output terminal and comprising a first amplifier FET and a first matching circuit, wherein the input terminal is connected to an input end of the first amplifier FET, an output end of the first amplifier FET is connected to an input end of the first matching circuit, and an output end of the first matching circuit is connected to the output terminal; and a second amplifier circuit connected between the input terminal and the output terminal and comprising a second amplifier FET, a second matching circuit, and a first switching circuit, wherein the input terminal is connected to an input end of the second amplifier FET, an output end of the second amplifier FET is connected to an input end of the second matching circuit, an output end of the second matching circuit is connected to an input end of the first switching circuit, and an output end of the first switching circuit is connected to the output terminal. In this power amplifier, the first amplifier circuit outputs an output signal of a first power level with high efficiency when the first amplifier FET is operated while the second amplifier FET is not operated and the first switching circuit is turned off, and the second amplifier circuit outputs an output signal of a second power level with high efficiency when the first amplifier FET is not operated while the second amplifier FET is operated and the first switching circuit is turned on. The impedance of the second matching circuit for the second amplifier circuit is adjusted to an optimum value that secures a high efficiency of the second amplifier circuit in consideration of the impedance of the first amplifier circuit while the impedance of the first matching circuit for the first amplifier circuit is adjusted to an optimum value that secures a high efficiency of the first amplifier circuit regardless of the impedance of the second amplifier circuit. Thereby, both the first and second amplifier circuits operate efficiently and output the amplified signal of the first power level and the amplified signal of the second power level, respectively. Accordingly, the impedances of the output side matching circuits of the first and second amplifier circuits which output amplified signals of different power levels can be optimized with high precision. As the result, in both the high-power output operation and the low-power output operation, the efficiencies of the first and second amplifier circuits are significantly improved. According to a second aspect of the present invention, in the above-described power amplifier, the first power level is larger than the second power level, and the power amplifier further comprises a third matching circuit having an input end connected to the input terminal and an output end connected to the input end of the first amplifier FET; and a second switching circuit and a fourth matching circuit, wherein an input end of the second switching circuit is connected to the input terminal, an output end of the second switching circuit is connected to the input end of the fourth matching circuit, and an output end of the fourth matching circuit is connected to the input end of the second amplifier FET. In this power amplifier, when the first and second switching circuits are turned off to operate the first amplifier FET, the first amplifier circuit outputs an amplified signal of a high power level. On the other hand, when the first and second switching circuits are turned on to operate the second amplifier FET, the second amplifier FET outputs an amplified signal of a low power level. Accordingly, when the first amplifier FET (first amplifier circuit) is in the unoperated state and the second amplifier FET (second amplifier circuit) is in the operated state to produce the amplified output of the low power level, even if the input impedance of the first amplifier circuit significantly varies and an impedance mismatch occurs between the input terminal and the second amplifier circuit, the third matching circuit compensates this mismatch. As the result, the low power level amplified output of the low power level is obtained by the stable and efficient operation. According to a third aspect of the present invention, in the above-described power amplifier, the first power level is larger than the second power level, and the power amplifier further comprises a third switching circuit for branching a gate bias applied to the first amplifier FET in a gate bias circuit of the first amplifier FET. When the input impedance of the first amplifier FET is considerably lower than that of the second amplifier FET, the input impedance of the first amplifier FET is increased by branching the gate bias applied to the first amplifier FET, whereby the signal input to the input terminal is supplied to the second amplifier FET with high reliability. As the result, the operation of the second amplifier circuit is made stable. According to a fourth aspect of the present invention, in the above-described power amplifier, the first power level is larger than the second power level, and the power amplifier further comprises a fourth switching circuit connected between the input terminal and the input end of the first amplifier FET, which fourth switching circuit is turned on when the first amplifier FET is operated and turned off when the second amplifier FET is operated. Since the first switching circuit is turned off while the operation of the first amplifier FET, no feedback loop is produced between the first amplifier circuit and the second amplifier circuit. Further, since the third switching circuit is turned off while the operation of the second amplifier FET, no feedback loop is produced between the first amplifier circuit and the second amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram illustrating a power amplifier in accordance with a first embodiment of the present invention. Figure 2 is an equivalent circuit diagram illustrating an output amplifier stage A2 (A3) included in the power amplifier shown in figure 1. Figure 3 is an equivalent circuit diagram illustrating a concrete structure of an amplifier FET shown in figure 2. Figure 4 is an equivalent circuit diagram illustrating an FET switch SW3 included in the power amplifier shown in figure 1. Figure 5 is a graph illustrating output power vs. gate width characteristics of the amplifier FET in the output amplifier stage A2 (A3) shown in figure 2. Figure 6 is a graph illustrating input power vs. output power characteristics and input power vs. power added efficiency characteristics in the high-power output operation of the output amplifier stage A2 and the low-power output operation of the output amplifier stage A3. Figure 7 is a block diagram illustrating a power amplifier in accordance with a second embodiment of the present invention. Figure 8 is a block diagram illustrating a power amplifier in accordance with a third embodiment of the present invention. Figure 9 is an equivalent circuit diagram illustrating an output amplifier stage A2 included in a power amplifier in accordance with a fourth embodiment of the invention. Figure 10 is a block diagram illustrating a transmitter of a portable telephone of a general frequency modulation system according to the prior art. Figure 11 is a block diagram illustrating a power amplifier included in the transmitter shown in figure 10. Figure 12 is a graph illustrating output power vs. current consumption characteristics when a gate bias voltage and a drain bias voltage applied to a driving stage A1 and an output amplifier stage A2 are controlled in the power amplifier shown in figure 11. Figure 13 is a graph illustrating input power vs. output power characteristics and input power vs. power added efficiency characteristics of the power amplifier shown in figure 11. Figure 14 is a block diagram illustrating a power amplifier according to the prior art. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 is a block diagram illustrating a power amplifier in accordance with a first embodiment of the present invention. In the figure, the same reference numerals as in figure 11 designate the same or corresponding parts. In the power amplifier shown in figure 11, a second amplifier circuit 100b comprising an AC coupling capacitor C2, an output amplifier stage A3, an output matching circuit OM3, and an FET switch SW3 is connected in parallel with a first amplifier 100a comprising an AC coupling capacitor C1, an output amplifier stage A2, and an output matching circuit M2. The structure of the first amplifier 100a is identical to that of the prior art power amplifier shown in figure 11. More specifically, the output amplifier stage A3 comprises an amplifier FET having a gate width narrower than the gate width of the amplifier FET of the output amplifier stage A2, and an input end of the output amplifier stage A3 is connected through the AC coupling capacitor C2 to a junction n1 of the inter-stage matching circuit M12 and the AC coupling capacitor C1 while an output end thereof is connected to an input end of the output matching circuit OM3. An output end of the output matching circuit OM3 is connected through the FET switch SW3 to the output terminal OUT. The impedance of the output matching circuit OM3 is appropriately set so that it has a load curve that secures a high-efficiency operation of the output amplifier stage A3 with considering the impedances of the output amplifier stage A2 and the output matching circuit M2. Figure 2 is an equivalent circuit diagram of the output amplifier stage A2 (A3). In figure 2, reference character F denotes an amplifier FET, Rg a gate stabilizing resistor, Cgb a gate bias capacitor, Ld a drain bias inductor, Cdb a drain bias capacitor, G a gate terminal, Vg2 a gate bias terminal, D a drain terminal, and Vd2 a drain bias terminal. A gate of the amplifier FET F is connected to the gate terminal G, and a junction of the gate and the gate terminal G is connected to an end of the gate stabilizing resistor Rg. The other end of the gate stabilizing resistor Rg is connected to the gate bias terminal Vg2. A junction of the gate stabilizing resistor Rg and the gate bias terminal Vg2 is connected through the gate bias capacitor Cgb to ground. A drain of the amplifier FET F is connected to the drain terminal D, and a junction of the drain and the drain terminal D is connected to an end of the drain bias inductor Ld. The other end of the drain bias inductor Ld is connected to the drain bias terminal Vd2, and a junction of the drain bias inductor Ld and the drain bias terminal Vd2 is connected through the gate bias capacitor Cgb to ground. Figure 3 shows a concrete structure of the amplifier FET included in the output amplifier stage shown in figure 2. In the figure, reference characters f1 to fn designate fundamental FET cells. Gates of the FETs f1 to fn are connected to a common gate terminal G and drains of the FETs are connected to a common drain terminal D. Usually, the gate width of the amplifier FET constituting the output amplifier stage A2 (A3) is significantly larger than the gate width of the FET constituting the driver stage A1. However, when the circuit design and the fabrication process are considered, the structure of the amplifier FET shown in figure 3 in which the gates and the drains of the FETs f1 to fn having the same-gate width are connected to the common gate terminal and the common drain terminal, respectively, to obtain a desired total gate width of the FETs f1 to fn is preferable to a single amplifier FET having a large gate width. Figure 4 is an equivalent circuit diagram illustrating the FET switch SW3. In the figure, reference character F1 denotes an FET, P1 an input terminal, P2 an output terminal, Csw1, Csw2, and Csw3 AC coupling capacitors, Rsw1, Rsw2, and Rsw3 resistors for applying a DC bias to the FET F1. The impedance of these resistors is sufficiently higher than the characteristic impedance of the transmission line. In addition, reference character Vsw3 designates a control terminal for controlling ON/OFF switching of the FET F1. A source (drain) of the FET F1 is connected through the AC coupling capacitor Csw1 to the input terminal P1, and a junction of the FET F1 and the AC coupling capacitor Csw1 is connected through the resistor Rsw1 to ground. A drain (source) of the FET F1 is connected through the AC coupling capacitor Csw2 to the output terminal P2, and a junction of the FET F1 and the AC coupling capacitor Csw2 is connected through the resistor Rsw2 to ground. Further, a gate of the FET F1 is connected through the resistor Rsw3 to the control terminal Vsw3, and a junction of the FET F1 and the control terminal Vsw3 is connected through the AC coupling capacitor Csw3 to ground. A description is given of the operation. While the high-power output operation, the gate bias voltage applied to the gate bias terminal Vg3 of the output amplifier stage A3 is controlled not to exceed the pinch-off voltage of the amplifier FET of the output amplifier stage A3, so that the output amplifier stage A3 is not driven. In addition, the FET switch SW3 is turned off by controlling the gate bias voltage applied to the control terminal Vsw3, so that the output side of the output amplifier stage A3, i.e., the second amplifier circuit 100b, is electrically separated from the first amplifier circuit 100b. In this state, the driver stage A1 and the output amplifier stage A2 are driven. Therefore, in the high-power output operation, the second amplifier circuit 100b does not adversely affect the operation of the first amplifier circuit 100a, whereby the first amplifier circuit 100a operates efficiently and outputs an amplified output of a high power level to the output terminal OUT. On the other hand, while the low-power output operation, the FET switch SW3 is turned on by controlling the gate bias voltage applied to the control terminal Vsw3 to electrically connect the output end of the output amplifier stage A3 with the OUT terminal. In other words, the output end of the second amplifier circuit 100b is electrically connected to the OUT terminal. In addition, the gate bias voltage applied to the gate bias terminal Vg2 of the amplifier FET constituting the output amplifier stage A2 is controlled not to exceed the pinch-off voltage of the amplifier FET so that the output amplifier stage A2 is not driven. In this state, the driver stage A1 and the output amplifier stage A3 are operated. At this time, the impedance of the output matching circuit OM3 of the output amplifier stage A3 is appropriately set so that it has a load curve that secures a high-efficiency operation of the output amplifier stage A3 considering the impedances of the output amplifier stage A2 and the output matching circuit M2. Therefore, the second amplifier circuit 100b, i.e., the output amplifier stage A3, operates efficiently and outputs a high power level amplified output to the output terminal OUT. Each of the amplifier FETs constituting the output amplifier stages A2 and A3 has a gate width that provides a desired high-power output under the bias condition in which the output amplifier stages A2 and A3 operate efficiently. When the gate width of the amplifier FET and the output power have the relationship shown in figure 5, in order to make the output amplifier stages A2 and A3 output amplified powers of 1W and 10mW, respectively, the gate widths of the FETs constituting the output amplifier stages A2 and A3 have to be set to Wa and Wc, respectively. Figure 6 is a graph illustrating input power vs. output power characteristic curves and input power vs. power added efficiency characteristic curves in the power amplifier in which the gate widths of the amplifier FETs are set as described above. In the graph, the output power and the power added efficiency at the point a in figure 5 are plotted by a3 and a4, respectively, and the output power and the power added efficiency at the point c in figure 5 are plotted by c3 and c4, respectively. The input power is fixed at a prescribed value shown by Δ. It can be seen from figure 6 that the efficiency in the low-power output operation of the power amplifier according to the invention is as high as the efficiency in the high-power output operation. In addition, when the amplifier FET constituting the output amplifier stage A3 is designed so that it operates efficiently under the bias condition for the ordinary operation, i.e., the bias condition that secures high-power output and high efficiency of the output amplifier stage A2, an efficient operation with reduced current consumption is achieved with no reduction in the drain bias voltage during the low-power output operation. As described above, in the power amplifier according to the present invention, the output end of the second amplifier circuit 100b for the low-power output operation is connected through the FET switch SW3 to the output end of the first amplifier circuit 100a for the high-power output operation. The impedance of the output matching circuit OM3 of the second amplifier circuit 100b is adjusted to an optimum value that secures high efficiency of the second amplifier circuit 100b in consideration of the impedance of the first amplifier circuit 100a comprising the output amplifier stage A2 and the output matching circuit M2. On the other hand, the impedance of the output matching circuit M2 of the first amplifier circuit 100a is adjusted to an optimum value that secures high efficiency of the first amplifier circuit 100a regardless of the impedance of the second amplifier circuit 100b comprising the output amplifier stage A3 and the output matching circuit OM3. Thereby, both the first and second amplifier circuits 100a and 100b operate efficiently and output a prescribed high-power level amplified output and a prescribed low-power level amplified output. Therefore, in the power amplifier according to the present invention, the output matching circuits M2 and OM3 of the first and second amplifier circuits 100a and 100b have precisely optimized impedances, respectively, and the efficiencies of the amplifier circuits 100a and 100b are significantly improved in both the high-power output operation and the low-power output operation. In order to transmit the amplified output to the output terminal OUT efficiently while the high-power output operation, both the output matching circuits M2 and OM3 may be connected to the output terminal OUT through a power synthesizer, such as a Wilkinson type power synthesizer, in place of the FET switch SW3. In this case, however, since such power synthesizer generally uses a 1/4 wavelength transmission line, the size of the power synthesizer unfavorably increases when it is used in a low frequency band ranging from 800 MHz to 2 GHz that is generally used for portable telephones, resulting in an increase in the size of the power amplifier. Therefore, the FET switch SW3 inserted between the output amplifier stage A3 and the output matching circuit OM3 is advantageous with respect to a reduction in the size of the power amplifier. Embodiment 2. Figure 7 is a block diagram illustrating a power amplifier in accordance with a second embodiment of the present invention. In figure 7, the same reference numerals as in figure 1 designate the same or corresponding parts. Reference character SW2 denotes an FET switch, Vsw2 a control terminal for ON/OFF switching of the FET switch SW2, INM3 an input matching circuit, and n2 a junction of a driver stage A1 and an AC coupling capacitor C1, to which a signal to be amplified in the first amplifier circuit 100a or the second amplifier circuit 100b is applied. While in the above-described first embodiment, the inter-stage matching circuit M12 corrects the mismatch between the driver stage A1 and the output amplifier stage A3 and the mismatch between the driver stage A1 and the output amplifier stage A2, i.e., the inter-stage matching circuit M12 functions as an input matching circuit between the first amplifier circuit 100a and the second amplifier circuit 100b. However, when the FET constituting the output amplifier stage A2 is pinched off in the low-power output operation, the input impedance of the FET significantly varies and the inter-stage matching circuit M12 alone cannot correct the impedance mismatch between the driver stage A1 and the output amplifier stage A3. In the power amplifier according to this second embodiment of the invention, in order to solve the above-described problem in the first embodiment, the first and second amplifier circuits 100a and 100b include different input matching circuits. More specifically, the FET switch SW2 is connected to the junction n2 between the driver stage A1 and the AC coupling capacitor C1, the input end of the output amplifier stage A3 of the second amplifier circuit 100b is connected through the input matching circuit INM3 to the FET switch SW2, and the inter-stage matching circuit M12 is used as an input matching circuit for the first amplifier circuit 100a. The input matching circuit INM3 is set so that the driver stage A1 impedance-matches to the output amplifier stage A3 while the low-power output operation in which the second amplifier circuit 100b operates efficiently. In the power amplifier according to the second embodiment of the invention, the FET switches SW2 and SW3 are turned off while the high-power output operation so that the output amplifier stage A2 of the first amplifier circuit 100a is driven, whereby a desired high-power output is obtained by the high-efficiency operation of the first amplifier circuit 100a. In the low-power output operation, the FET switches SW2 and SW3 are turned on to turn off the output amplifier stage A2 of the second amplifier circuit 100a and to turn on the output amplifier stage A3 of the second amplifier circuit 100b, whereby a desired low-power output is applied to the output terminal OUT. Accordingly, desired outputs are obtained by the highly-efficient operation of the amplifier circuits 100a and 100b in both the high-power output operation and the low-power output operation, as in the above-described first embodiment. Further, when the output amplifier stage A2 is in the off state while the low-power output operation, i.e., when the amplifier FET constituting the output amplifier stage A2 is in the pinch-off state, the input impedance of the FET significantly-varies and an impedance mismatch occurs between the driver stage A1 and the output amplifier stage A3. In this second embodiment, the input matching circuit INM3 compensates this impedance mismatch. Therefore, the low-power output operation is performed with high efficiency and high reliability. Embodiment 3. Figure 8 is a block diagram illustrating a power amplifier in accordance with a third embodiment of the present invention. In figure 8, the same reference numerals as in figure 7 designate the same or corresponding parts. Reference character SW1 denotes an FET switch, Vsw1 a control terminal for ON/OFF switching of the switch SW1, and M12 an input matching circuit. The circuit structure of the FET switch SW1 is identical to the FET switch SW3 of the first embodiment. In the above-described first and second embodiments of the invention, no feedback loop is produced between the first and second amplifier circuits 100a and 100b because the FET switch SW3 is turned off when the first amplifier circuit 100a is operated. However, since the FET switches SW2 and SW3 are turned on when the second amplifier circuit 100b is operated, a feedback loop is produced between these circuits 100a and 100b, resulting in parasitic oscillation. The power amplifier according to this third embodiment is made to solve this problem. More specifically, the AC coupling capacitor C1 of the first amplifier circuit 100a in the power amplifier shown in figure 7 is replaced with the FET switch SW1, and the FET switch SW1 is turned off while the low-power output operation of the second amplifier circuit 100b so that no feedback loop is produced between the first and second amplifier circuits 100a and 100b. In the power amplifier according to this third embodiment of the invention, the same effects as described in the second embodiment are achieved. In addition, when the FET switch SW1 is turned off during the low-power output operation of the second amplifier circuit 100b, the second amplifier circuit 100b is electrically separated from the first amplifier circuit 100a. Therefore, no feedback loop is produced between the first and second amplifier circuits neither in the operation of the first amplifier circuit 100a nor in the operation of the second amplifier circuit 100b, whereby the parasitic oscillation is avoided. Embodiment 4. In this fourth embodiment of the invention, the output amplifier stage A2 shown in figure 2 included in the power amplifier according to the first embodiment of the invention is replaced with an output amplifier stage having a circuit structure shown in figure 9. In figure 9, the same reference characters as in figure 2 designate the same or corresponding elements. An FET switch 20 comprises a switch FET GSW for branching the gate bias voltage applied to the gate terminal G (hereinafter referred to as a gate bias branching switch FET), a resistor Rgsw, a switch FET bias capacitor Cgsw, and a control terminal Vgsw for controlling the gate bias branching (hereinafter referred to as a gate bias branching control terminal). A drain of the gate bias branching switch FET GSW is connected to an end of the gate stabilizing resistor Rg. The other end of the resistor Rg is connected to a junction of the gate terminal G and the amplifier FET F. A gate of the gate bias branching switch FET GSW is connected through the high resistor Rgsw to the gate bias branching control terminal Vgsw, and a junction of the gate and the high resistor Rgsw is connected through the switch FET bias capacitor Cgsw to the gate bias terminal Vg2. A source of the gate bias branching switch FET GSW is connected to an end of the gate bias capacitor Cgb, and a junction of the source and the gate bias capacitor Cgb is connected to a junction of the switch FET bias capacitor Cgsw and the gate bias terminal Vg2. In the power amplifier including the output amplifier stage A2 shown in figure 2 according to the first embodiment of the invention, if the input impedance on the output amplifier stage A2 side is considerably low compared to the input impedance on the output amplifier stage A3 side when the resistance of the gate stabilizing resistor Rg for the amplifier FET of the output amplifier stage A2 is low and the output power is low, i.e., when the output amplifier stage A3 is operated and the amplifier FET constituting the output amplifier stage A2 is pinched off, most of the signal output from the driver stage A1 flows toward the output amplifier stage A2, so that the signal output is hardly applied to the output amplifier stage A3. As the result, an expected operation cannot be realized. The fourth embodiment of the invention is directed to solving this problem. More specifically, in the power amplifier of this fourth embodiment, since the output amplifier stage A2 has the circuit structure shown in figure 9, the input impedance on the output amplifier stage A2 side can be increased by turning off the gate bias branching switch FET 20. Therefore, while the low-power output operation, i.e., while the output amplifier stage A3 is operated and the amplifier FET constituting the output amplifier stage A2 is in the pinch-off state, by turning off the gate bias branching switch FET GSW, the signal output from the driver stage A1 is input to the output amplifier stage A3 with high reliability, resulting in a stable low-power output operation. If the voltage at the gate bias branching control terminal Vgsw is equivalent to the voltage at the gate bias terminal Vg2, the gate bias branching switch FET GSW is turned on. If the voltage at the gate bias branching control terminal Vgsw is sufficiently negative compared to the voltage at the gate bias terminal Vg2, the gate bias branching switch FET GSW is turned off. As described above, according to the fourth embodiment of the invention, since the FET switch 20 for branching the gate bias is included in the gate bias circuit for the amplifier FET (F) constituting the output amplifier stage A2, even when the input impedance is lower on the output amplifier stage A2 side than on the output amplifier stage A3 side because of the low resistance of the gate stabilizing resistor Rg of the amplifier FET, the input impedance on the output amplifier stage A2 side can be increased by turning off the gate bias branching switch FET 20, whereby the signal output from the driver stage A1 is input to the output amplifier stage A3 with high reliability, resulting in a stable low-power output operation of the output amplifier stage A3. While in the above-described first to fourth embodiments emphasis has been placed upon a power amplifier including two amplifier circuits with different output power levels, a similar power amplifier including three or more amplifier circuits with different output power levels is also within the scope of the present invention. In the above-described first to fourth embodiments of the present invention, the power amplifier comprises the first and second amplifier circuits 100a and 100b, and the first amplifier circuit 100a includes the output amplifier stage A2 comprising the first amplifier FET and outputs a high-power level output by the high-efficiency operation thereof while the second amplifier circuit 100b includes the output amplifier stage A3 comprising the second amplifier FET having a gate width narrower than that of the first amplifier FET and outputs a low-power level output by the high-efficiency operation thereof. These first and second amplifier circuits 100a and 100b are selectively operated to improve the efficiencies in both the high-power output operation and the low-power output operation. A description is given of the operation. An input signal applied to the input terminal IN is transmitted through the matching circuit M5 to the output amplifier stage A4. The output amplifier stage A4 has a circuit structure as shown in figure 2 in which the gate bias terminal Vg4 corresponds to the gate bias terminal Vg2 and the drain bias terminal Vd4 corresponds to the drain bias terminal Vd2. By controlling power supply voltages applied to the gate bias terminal Vg4 and the drain bias terminal Vd4, the output amplifier stage A4 output amplified outputs of different power levels. It is assumed that the power level of the amplified output is changed from P1 to P2 (P1 > P2). When the power level of the amplified output is P1, the matching circuit M6 is selected by the FET switches SW4 and SW5 and the amplified output is transmitted through the matching circuit M6 whose impedance is adjusted so that the optimum impedance match is made when the output power level is P1, to the output terminal OUT. On the other hand, when the power level of the amplified output is P2, the matching circuit M7 is selected by the FET switches SW4 and SW5 and the amplified output is transmitted through the matching circuit M7 whose impedance is adjusted so that the optimum impedance match is made when the output power level is P2, to the output terminal OUT. In the FET switch SW4, the input terminal IN1 is connected to the output end of the amplifier stage A4, and the output terminals OUT1, and OUT2 are connected to the matching circuit M6 and the matching circuit M7, respectively. In the FET switch SW5, the input terminals IN2 and IN3 are connected to the matching circuit M6 and the matching circuit M7, respectively, and the output terminal OUT3 is connected to the output terminal OUT. When the FETs F2 and F5 are turned on and the FETs F3 and F4 are turned off by controlling voltages applied to the control terminals Vsw4a and Vsw4b, a signal output from the amplifier stage A4 and input to the input terminal IN1 is transmitted through the matching circuit M6 to the output terminal OUT. On the other hand, when the FETs F2 and F5 are turned off and the FETs F3 and F4 are turned on, the signal input to the input terminal IN1 is transmitted through the matching circuit M7 to the output terminal OUT.

Claims: A power amplifier (Fig. 1) comprising: an input terminal (IN) to which an input signal to be amplified is applied; an output terminal (OUT) from which an amplified signal is output; a first amplifier circuit (100a) connected between the input terminal (IN) and the output terminal (OUT) and comprising a first amplifier FET (A2) having an input end and an output end and a first matching circuit (M2) having an input end and an output end, wherein the input terminal (IN) is connected to the input end of the first amplifier FET (A2), the output end of the first amplifier FET (A2) is connected to the input end of the first matching circuit (M2), and the output end of the first matching circuit (M2) is directly connected to the output terminal (OUT); and a second amplifier circuit (100b) connected between the input terminal (IN) and the output terminal (OUT) and comprising a second amplifier FET (A3) having an input end and an output end, a second matching circuit (OM3) having an input end and an output end, and a first switching circuit (SW3) having an input end and an output end, wherein the input terminal (IN) is connected to the input end of the second amplifier FET (A3), the output end of the second amplifier FET (A3) is connected to the input end of the second matching circuit (OM3), the output end of the second matching circuit (OM3) is connected to the input end of the first switching circuit (SW3), and the output end of the first switching circuit (SW3) is connected to the output terminal (OUT); wherein said first switching circuit (SW3) is turned off when said first amplifier circuit (100a) is turned on; and wherein said first amplifier circuit (100a) outputs an output signal of a first power level when the first amplifier FET (A2) is operated while the second amplifier FET (A3) is not operated and the first switching circuit (SW3) is turned off, and said second amplifier circuit (100b) outputs an output signal of a second power level when the first amplifier FET (A2) is not operated while the second amplifier FET (A3) is operated and the first switching circuit (SW3) is turned on. The power amplifier of claim 1 (Fig. 7) wherein the first power level is larger than the second power level, said power amplifier further comprising: a third matching circuit (M12) having an input end connected to the input terminal (IN) and an output end connected to the input end of the first amplifier FET (A2); and a second switching circuit (SW2) having an input end and an output end and a fourth matching circuit (INM3) having an input end and an output end, the input end of the second switching circuit (SW2) being connected to the input terminal (IN), the output end of the second switching circuit (SW2) being connected to the input end of the fourth matching circuit (INM3), and the output end of the fourth matching circuit (INM3) being connected to the input end of the second amplifier FET (A3), wherein the second switching circuit (SW2) is turned off when the first amplifier FET (A2) is operated and turned on when the second amplifier FET (A3) is operated. The power amplifier of claim 1 (Fig. 8) wherein the first power level is larger than the second power level, said power amplifier further comprising: a third switching circuit (SW1) for electrically separating said first amplifier circuit (100a) from said second amplifier circuit (100b) between said input terminal (IN) and said input end of said first amplifier FET (A2). The power amplifier of claim 1 (Fig. 9) further comprising: a fourth switching circuit (20) connected between the input terminal (IN) and the input end of the first amplifier FET (A2), said fourth switching circuit being turned on when the first amplifier FET (A2) is operated and turned off when the second amplifier FET (A3) is operated. The power amplifier of claim 1, wherein said first amplifier FET (A2) has a gate width different from that of said second amplifier FET (A3). The power amplifier of claim 5 (Fig. 3) wherein, said first amplifier FET (A2) has FET cells (f1 to Fn) whose gates are commonly connected to the input end of said first amplifier FET, whose drains are commonly connected to the output end of said first amplifier FET, and which have same gate widths, and said second amplifier FET (A3) has FET cells (f1 to Fn) whose gates are commonly connected to the input end of said second amplifier FET, whose drains are commonly connected to the output end of said second amplifier FET, and which have same gate widths.

Inventors: TANINO NORIYUKI, UMEMOTO TETSUYA, YAMAMOTO KAZUYA, TANINO, NORIYUKI, UMEMOTO, TETSUYA, YAMAMOTO, KAZUYA, TANINO, NORIYUKI, C/O MITSUBISHI DENKI K.K., UMEMOTO, TETSUYA, C/O MITSUBISHI DENKI K.K., YAMAMOTO, KAZUYA, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1995
Main classification: H03F1
IPC codes: H03F3, H03F1, H04B1