Pulse generator, circuit and method for driving electronic devices, and corresponding applications

Abstract: The present invention relates primarily to a pulse generator (GEN) having an input (ID) and two outputs (OR,OS) at which to generate respectively a pulse in relation to a edge of a different type at input. The generator provides two distinct logic circuit blocks of the sequential type hence mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses. In addition, if two blocks are connected with appropriate and simple logic networks (G3,G4) it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

Description: The present invention relates to a pulse generator in accordance with the preamble of claim 1 and to a circuit and method of driving the electronic devices wherein the generator finds advantageously application. For electronic devices and in particular if they are the type designed to operate at high voltages much care should be dedicated to the study of their drive circuits since these circuits see on one side very low voltages, e.g. 5V coming from a logic circuit, and on the other very high voltages, e.g. 500V. This problem becomes still more important when the logic circuit, the drive circuit and the high-voltage electronic device are integrated in the same chip. A conventional architecture is shown in the annexed FIG. 1. The drive circuit has a control input IN and a drive output OUT and comprises a pulse generator GEN having an input ID connected to the input IN and a first output OR and a second output OS at which it generates respectively a pulse in relation to a edge of a different type at the input ID. It also comprises a first transistor MR and a second transistor MS both of the n-channel MOS type and having control terminals respectively connected to the output OR and the output OS and source terminals connected to ground GND. It also comprises a level shifter network LS having two inputs respectively connected to the drain terminals of the transistors MR and MS and two corresponding outputs. It also comprises a flip-flop FFD sensitive to the pulses at its inputs or better at the levels and having a reset input IR connected to the output of the network LS corresponding to the transistor MR and a setting input IS connected to the output of the network LS corresponding to the transistor MS and a state output OQ connected to the output OUT. Often between the output OQ and the output OUT is placed an output amplifier or buffer. It is noted that in FIG. 1 are shown the intrinsic diodes DR and DS which are respectively transistors MR and MS. The network LS is often merely made up of a pair of equal resistors of appropriate value connected between the drain terminals of the MOS transistors and a reference voltage and the inputs IR and IS are connected respectively and directly to the drain terminals of the transistors MR and MS. A possible, simple and widespread electrical diagram for the generator GEN is shown in FIG. 2. It comprises a resistor RES having a first terminal connected to the input ID and a capacitor CAP having a first terminal connected to ground GND and a second terminal connected to a second terminal of the resistor RES and an inverter INV having its input connected to the second terminals of the resistor RES and of the capacitor CAP and a logic gate G2 of the NAND type having a first input connected to the output of the inverter INV and a second input connected to the input ID and an output connected to the output OS and a logic gate G1 of the OR type having a first input connected to the input ID and a second input connected to the output of the inverter INV and an output connected to the output OR. This circuit is level sensitive and has a single element corresponding to the assembly of the resistor RES and the capacitor CAP to generate a delay corresponding to the duration of an output pulse. It ensues that with increase of signal frequency at the input ID and/or the appearance of spurious pulses of extended duration at the input ID the pulses at the outputs OR and OS no longer have characteristics, in particular concerning the duration and mutual position in time, such as to correctly drive the downstream circuits. In limit cases there may occur failure to recognize commands at the input ID with very serious consequences in the case of commands for turning-off the driven electronic device. In the Patent Abstract of Japan No. 60010913 to Fujitsu K.K. it is described a noise eliminating circuit comprising D flip-flops multi-stage circuits, connected in cascade to each other. In particular, the input signal is branched in two signals: one signal enters a positive noise eliminating circuit, consisting of two stages of D flip-flops, and the other signal is inverted and enters a negative noise eliminating circuit, consisting of two stages of D flip-flops too. Such a noise eliminating circuit is actually a digital synchronous filter and it needs a synchronous clock signal CL. Moreover, the Patent Abstract of Japan No. 60100820 also to Fujitsu K.K. illustrates a monostable multivibrator comprising a delay circuit between the reset terminal and an output terminal OUT. In such a way, the output OUT is used to obtain an output signal having a desired pulse width. Also these known circuits do not assure that with the increase of input signal's frequency and/or the appearance of spurious pulses of extended duration at the input, the output pulses maintain the required characteristics, in particular concerning the duration and mutual position in time, to correctly drive the downstream circuits. The purpose of the present invention is to overcome the shortcomings of the prior art. This purpose is achieved by means of the generator having the characteristics set forth in claim 1 and the drive circuit having the characteristics set forth in claim 4 and by means of the drive method having the functions set forth in claim 6. Other advantageous aspects of the present invention are set forth in the dependent claims. The present invention also relates to an integrated circuit and an electric motor control system and a power supply, according to claims 8-10, in which the drive circuit in accordance with the present invention finds advantageous application. The invention is clarified by the following description considered together with the annexed drawings wherein: FIG. 1 shows a block diagram of a drive circuit in accordance with the prior art, FIG. 2 shows a circuit diagram of a pulse generator in accordance with the prior art, FIG. 3 shows a circuit diagram of a possible implementation of the pulse generator in accordance with the present invention, FIG. 4 shows a time chart of the input and output signals of the generator of FIG. 3, FIG. 5 shows a circuit diagram of the delay network included in the generator of FIG. 3, and FIG. 6 shows a circuit diagram of a drive stage usable in a drive circuit in accordance with the present invention. The generator of FIG. 3 has an input ID designed to receive digital signals and a first output OR and a second output OS at which to generate respectively pulses in relation to edges in the digital signal at the input ID. For example in FIG. 3 the outputs OR and OS are normally at high logic state and a negative pulse is generated at the output OR if the signal at the input ID goes from the high logic state to the low logic state while a negative pulse is generated at the output OS if the signal at the input ID goes from low logic state to high logic state. This behavior is illustrated in the time chart of FIG. 4 which represents the simultaneous behavior in time of the signals at the input ID and the outputs OS and OR. The generator of FIG. 3 consists of two distinct sequential logic circuit blocks having each its own input and output. The inputs are both connected to the input ID through an AND logic gate G3 whose function is explained below and whose outputs are connected respectively to the outputs OR and OS. The two blocks being independent of each other it is easy to control the characteristics of the generated pulses. The two blocks are essentially equal. The first block comprises a first, type D, flip-flop FF1 sensitive to the edges and having a data input D1 receiving at input a predetermined logic value, high or "1" in the example, and a clock input CK1 connected to the block input, an asynchronous reset input R1 which is active "high" in the example, a first state output Q1 in normal form and a second state output QN1 in negated form connected to the output of the block, a first asymmetrical delay network DT1 for two types of edge having an input connected to the first output Q1 and an output connected to the reset input R1. Similarly the second block comprises a second, type D, flip-flop FF2 sensitive to the edges and having a data input D2 receiving at input a predetermined logic value, 'high' or '1' in the example, a clock input CK2 connected to the block input, an asynchronous reset input R2, active 'high' in the example, a first state output Q2 in normal form and a second state output QN2 in negated form connected to the block output, a second asymmetrical delay network DT2 for two types of edge having input connected to the first output Q2 and output coupled with the reset input R2. The fact that the two flip-flops are the edge-sensitive type permits signals at the input ID of frequency limited in a first approximation only by the characteristic delay of the networks DT1 and DT2. As may be seen in FIG. 3 the flip-flop FF1 and the flip-flop FF2 are different since the former has a clock input CK1 sensitive to falling edges while the latter has an input CK2 sensitive to rising edges. In addition, in the second block the output of the network DT2 is connected to the input R2 through a logic gate G4 of the OR type whose function is explained below. Two identical blocks can be employed and an inverter connected upstream of one of them. In the example of FIG. 3 the delay networks DT1 and DT2 are such that a rising edge at input is brought back at output with a predetermined delay while a falling edge at input is brought back at output practically instantaneously except for delays in propagation of the signals in the network. This is important so that the generator will be ready to process a new edge at the input as soon as a pulse is generated at the output. If the two blocks are connected by appropriate and simple logical networks it is possible in the generation to impose phase conditions between the pulses at the two outputs OR and OS simply and with a certain freedom. For electronic device drive circuits a first requirement which appeared was that no more pulses be generated at the outputs if there is already a pulse at the output OR. This was achieved by means of a first logic network G3 connected at input to the input ID and to the output OR and connected at output to both the inputs of the two blocks. In the example of FIG. 3 the network G3 consists merely of an AND logical gate preventing arrival of edges at the inputs of the two blocks if the output OR is at the low logic state. For the drive circuits there appeared a second requirement that there be no pulse at the output OS if a pulse is generated at the output OR. This was achieved by means of a second logical network G4 connected at input to the output Q1 and to the output of the network DT2 and connected at output to the input R2. In the example of FIG. 3 the network G4 consists merely of an OR-type logical gate which keeps the flip-flop FF2 reset if the output OR is in the low logic state. A possible embodiment of the delay networks DT1 and DT2 is shown in FIG. 5. It exhibits an input A and an output B and comprises a capacitor C having a first terminal coupled to the output B and a second terminal connected to ground GND and a p-channel MOS transistor P1 having its control terminal connected to the input A and its drain terminal connected to a first terminal of the capacitor C, an n-channel MOS transistor N1 having its control terminal connected to the input A, its source terminal connected to ground GND and its drain terminal connected to the first terminal of the capacitor C and a current generator I1 having its input connected to a potential reference and in particular to the power supply VDD and its output connected to the source terminal of the transistor P1. In this manner, when the input A is in the low logic state the capacitor C is charged with constant current by the generator I1 through the transistor P1 which is turned-on while when the input A is in high logic state the capacitor C is discharged to ground GND by the transistor N1 which is turned-on. While the charge phase lasts a finite time determined by the ratio of the current of the generator I1 to the capacitance of the capacitor C the discharge phase is almost instantaneous. The first terminal of the capacitor C is connected to the output terminal B through a CMOS inverter fulfilling the functions of bufferization and logical inversion and comprising another p-channel MOS transistor P2 and another n-channel MOS transistor N2 connected between the power supply VDD and ground GND in the usual manner. The characteristic delay of the networks DT1 and DT2 in case of particular requirements can be made different to achieve a turn-on pulse for the electronic device of a duration different from that of turn-off. In dimensioning the delay networks it is necessary to allow for the dynamics of the electronic device to be driven, the minimum duration of the pulses for correct switching of the successive stages and the type and duration of the spurious pulses at the input. A generator in accordance with the present invention, e.g. the one just described, could be inserted advantageously in a drive circuit for electronic devices like that of the prior art shown in FIG. 1 with the advantages set forth above. In comparison with the circuit of the prior art of FIG. 1 the driving of the transistors MR and MS takes place differently as follows. The pulses are never overlapped in time and are of fixed and predetermined duration, the pulses to the transistor MR cannot be interrupted in any case and they are thus all strictly of the predetermined duration, and the pulses to the transistor MS are interruptible if there is a requirement to send a pulse to the transistor MR. Even if the flip-flop FFD were the JK type the presence of two pulses simultaneously at the outputs OR and OS would give no advantage but rather instability in operation. In FIG. 4 can be seen how spurious pulses following a falling edge on the input ID have no effect on the outputs OR and OS. It may also be seen that the spurious pulses isolated have the effect of taking the electronic device to the off state in a manner not causing damage. Lastly it may be seen that two rapidly succeeding edges are correctly read by the generator and give rise to a pulse at the output OR and a pulse at the output OS. It might be advantageous to drive the transistors MR and MS in current instead of voltage as illustrated in FIG. 1 in order to limit the dissipation of power to the level shifter. Indeed, a voltage pulse acting on the control terminal of the transistor MR or MS would give rise in case of voltage drive to a high current peak which, in addition to increasing the dissipation, would involve a higher discharge of the bootstrap capacitance normally used in this type of control system. For this purpose, downstream of the outputs OR and OS can be connected a drive stage like the one illustrated in FIG. 6. It exhibits an input E which can be connected to the output OR or OS and an output F which can be coupled to the input IR or IS of the flip-flop FFD. It is noted that the n-channel MOS transistor M3 corresponds functionally to the transistor MR or MS of FIG. 1. The stage of FIG. 6 comprises conceptually a current generator and a current mirror. The input E permits activation or deactivation of the stage in the example of FIG. 6 through two MOS transistors. In greater detail it comprises a p-channel MOS transistor M1 having its control terminal connected to the input E and its source terminal connected to a potential reference V1, a resistor R having a first terminal connected to the drain terminal of the transistor M1 and a second terminal connected to an input terminal of the current mirror. An output terminal of the mirror is connected to the source terminal of the transistor M3. The control terminal of the transistor M3 is connected to a potential reference V2. The reference values V1 and V2 must be chosen appropriately in relation to the rest of the drive circuit. In particular, as a digital signal is supplied to the input E, the value of V1 must be chosen such that when the input signal has high potential the transistor M1 is off while when the input signal has low potential the transistor M1 is turned-on. The current mirror is implemented in a simple manner e.g. as in FIG. 6 by means of an npn junction transistor T1 having its collector terminal connected to the mirror input, its emitter terminal connected to ground GND and its base terminal connected to the collector terminal; and by means of an npn junction transistor T2 having its emitter terminal connected to ground GND, its base terminal connected to the base terminal of the transistor T1 and its collector terminal connected to the current mirror output. Lastly the stage of FIG. 6 comprises a protection network comprising two diodes D1 and D2 connected in series between the collector of the transistor T2 and the reference V2. The function of the diodes is to protect the transistor T2 during the turn-off transients. Indeed, when the transistor T2 is off, the potential of its collector could reach very high values and the voltage VCE could exceed the breakdown threshold. The presence of the two diodes limits the collector potential to slightly higher than V2. To ensure that the transistor T2 is off and thus does not supply current to the output of the mirror when the transistor M1 is off, it is appropriate to insert an n-channel MOS transistor M2 between the base terminal of the transistor T2 and ground GND and connect the control terminal to the input E. In this manner when the input signal has low potential the transistor M1 is energized and the transistor M2 is off and thus it is as though it were not there, neither for the transistor T2 nor consequently for the mirror. When the input signal has low potential the transistor M1 is off and the transistor M2 is turned-on and thus short-circuits the base and emitter of the transistor T2 which is kept off. The drive circuit discussed above can be advantageously integrated in a chip through the use of manufacturing processes which ensure adequate insulation. It could also be though to insert in the chip at least one high-voltage electronic device having its control terminal coupled to the output of the drive circuit. In this manner can be achieved a new high-voltage electronic device which can be driven without problems by a low-voltage logic signal. It could also be thought to insert in the chip additional logic circuitry which would in turn drive the drive circuit. Typical advantageous applications of the present invention are control systems for electric motors and switching voltage regulators. The ability to operate on very highfrequency input signals up to 500kHz and change the duty cycle between limit values permits achieving high efficiency in both applications.

Claims: Pulse generator having an input (ID) receiving digital signals and a first output (OR) and a second output (OS) at which to generate respectively a pulse in response to a rising edge and a falling edge at its input (ID) and comprising: a. a first and a second sequential logical circuit blocks each comprising a data input, a clock input, a reset input and state outputs; each sequential logic circuit blocks generating a pulse of a predetermined duration at its output when triggered by the rising and falling edges on its input and immediately terminating said output pulse in response to activation of said reset input, said clock inputs being mutually inverted; characterized in that it further comprises: b. a first logical network (G3) coupled at input at least to said input (ID) of the pulse generator and to said first output (OR) of the pulse generator and coupled at output to both the clock inputs of said sequential logical circuit blocks, such a first logical network (G3) terminating said output pulse at the outputs (OR, OS) of the pulse generator in response to a pulse at said first output (OR) of the pulse generator; and c. a second logical network (G4) coupled at input at least to a state output of said first sequential logic circuit block and coupled at output to the reset input of the second sequential logic circuit block, such a second logical network (G4) terminating said output pulse at the second output (OS) of the pulse generator in response to a pulse at said first output (OR) of the pulse generator, said reset input of the second sequential logic circuit block returning its logic state to a predetermined value. Generator in accordance with claim 1 and characterized in that at least one of said sequential logic circuit blocks comprises: a. a type D flip-flop (FF1,FF2) sensitive to the edges and having a data input (D1,D2) receiving at input a predetermined logical value and a clock input (CK1,CK2) coupled to the sequential logic circuit block clock input and an asynchronous reset input (R1,R2) and at least one state output (Q1,QN1,Q2,QN2) coupled to the sequential logic circuit block state output, and b. an asymmetrical delay network (DT1,DT2) for two types of edge and having an input coupled to an output (Q1,Q2) of said flip-flop (FF1,FF2) and an output coupled to said asynchronous reset input (R1,R2). Generator in accordance with claim 2 and characterized in that said asymmetrical delay network (DT1,DT2) comprises: a. a capacitor (C) coupled to an output (B) of the asymmetrical delay network (DT1, DT2), b. a first switch (P1) having a control terminal coupled to an asymmetrical delay network input (A) and having a first conduction terminal coupled to said capacitor (C), c. a second switch (N1) having a control terminal coupled to the asymmetrical delay network input (A) and having a first conduction terminal coupled to said capacitor (C) and a second conduction terminal coupled to a potential reference (GND), and d. a current generator (I1) coupled to a second conduction terminal of said first switch (P1) so that said capacitor (C) is charged & discharged by said generator (I1) through said first switch (P1) and is discharged & charged from said potential reference (GND) through said second switch (N1). Electronic device drive circuit having a control input (IN) and a drive output (OUT) and comprising: a. a pulse generator (GEN) having an input (ID) coupled to said control input (IN) of the electronic device drive circuit and a first output (OR) and a second output (OS) at which to generate respectively a pulse in response to a rising edge and a falling edge at its input (ID), b. a first transistor (MR) and a second transistor (MS) driven respectively by signals present at said first output (OR) and second output (OS) of the pulse generator (GEN), c. a flip-flop (FFD) having a reset input (IR) coupled to one of the main conduction terminals of said first transistor (MR) and an reset input (IS) coupled to one of the main conduction terminals of said second transistor (MS) and a state output (OQ) coupled to the drive output (OUT) of the electronic device drive circuit and characterized in that said pulse generator (GEN) is a pulse generator in accordance with one of the claims 1 to 3. Electronic device drive circuit in accordance with claim 4 characterized in that it further comprises a first and a second drive stages connected respectively at input to said first output (OR) and second output (OS) to control their activation and at output to said first transistor (MR) and second transistor (MS) to drive them, each of said drive stages comprising: a. a current generator having an output, and b. a current mirror having its input coupled to the output of said current generator and at least one output coupled to a main conduction terminal of a corresponding transistor of said two transistors (MR,MS). Driving method for at least one electronic device comprising a first transistor (MR) and a second transistor (MS) and a flip-flop (FFD) of the type having a reset input (IR) coupled to one of the main conduction terminals of said first transistor (MR) and a setting input (IS) coupled to one of the main conduction terminals of said second transistor (MS) and a state output (OQ) for driving said electronic device, said method comprising the steps of: driving said transistors (MR,MS) by means of a first and a second driving pulse signals of predetermined duration generated by a pulse generator (GEN) according to one of the claims 1 to 3. Method in accordance with claim 6 characterized in that the driving of said transistors (MR,MS) is performed in current. Integrated circuit comprising a drive circuit in accordance with one of claims 4 or 5 and at least one high-voltage electronic device having its control terminal coupled to the output of said drive circuit. Electric motor control system comprising at least one drive circuit in accordance with one of claims 4 or 5 and at least one electronic device having its control terminal coupled to the output of said drive circuit and designed to power at least one winding of said electric motor. Power supply of the switching type and comprising a drive circuit in accordance with one of claims 4 or 5 and at least one electronic device and having its control terminal coupled to the output of said drive circuit and designed to operate as a regulating element.

Inventors: CANTONE GIUSEPPE, NOVELLI ALDO, CANTONE, GIUSEPPE, NOVELLI, ALDO
Applicants: CONS RIC MICROELETTRONICA, ST MICROELECTRONICS SRL, CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: H03K5
IPC codes: H03K5