Acquisition of carrier phase and symbol timing through joint estimation of phase and timing adjustments

Abstract: A signal acquisition system rapidly acquires carrier phase and symbol timing of a received PSK-modulated communication signal (24) having a 110-symbol pattern through joint estimation of carrier-phase adjustment and symbol-timing adjustment by processing a common set of sampled data. A reference signal (22) at a local oscillator frequency is mixed with a received communication signal (24) to provide the communication signal (26) at an intermediate frequency. The intermediate-frequency communication signal (26) is converted into a digital communication signal (28), which is formatted into in-phase (I) and quadrature-phase (Q) components. A sampling circuit (18) samples the I components at twice a predetermined symbol rate to provide a first series of I-component samples at the predetermined symbol rate and a second series of I-component samples that are intermediate to the first series of I-component samples and at the predetermined symbol rate, and for sampling the Q components at twice the predetermined symbol rate to provide a first series of Q-component samples at the predetermined symbol rate and a second series of Q-component samples that are intermediate to the first series of Q-component samples and at the predetermined symbol rate. A processor (20) processes the samples to estimate a phase-adjustment value  A and a symbol-timing-adjustment value ST A . The phase of the reference signal (22) is adjusted in accordance with the phase-adjustment value  A and the timing of the sampling is adjusted in accordance with the symbol-timing-adjustment value ST A .

Description: BACKGROUND OF THE INVENTION The present invention generally pertains to communication signal acquisition and is particularly directed to a system for acquiring carrier phase and symbol timing of a received communication signal. Various techniques for acquiring carrier phase and/or symbol timing of received communications signals are described by C. Heegard, J. A. Heller and A. J. Viterbi, "A Microprocessor-Based PSK Modem for Packet Transmission Over Satellite Channels", IEEE Transactions on Communications, Vol. COMM-26, No. 5, pp. 552-564, May, 1978; L. E. Franks, "Carrier and Bit Synchronization in Data Communication - A Tutorial Review", IEEE Transactions on Communications, Vol. COMM-28, No. 8, pp. 1107-1120, August, 1980; A. J. Viterbi and A. M. Viterbi, "Nonlinear Estimation of PSK-Modulated Carrier Phase with Application to Burst Digital Transmission, IEEE Transactions on Information Theory, Vol. IT-29, No. 4, pp. 543-551, July, 1983; United States Patent No. 5,282,227 to James A. Crawford for "Communication Signal Detection and Acquisition"; and James, N D: "A Digitally Implemented QPSK Modem Operating At Up To 10 Mbit/s", GEC Journal of Research, Vol. 7, No. 1, 1989, pages 8-15, the latter of which discloses a system for acquiring carrier phase and symbol timing of a received communication system by processing a common set of sampled data. SUMMARY OF THE INVENTION The present invention provides a system for rapidly acquiring carrier phase and symbol timing of a received communication signal through joint estimation of carrier-phase adjustment and symbol-timing adjustment by processing a common set of sampled data. The system of the present invention comprises a local oscillator for providing a reference signal at a local oscillator frequency; a mixer for mixing a received communication signal with the reference signal to provide the communication signal at an intermediate frequency; an analog-to-digital converter for converting the intermediate-frequency communication signal to a digital communication signal; a circuit for formatting the digital communication signal into in-phase (I) and quadrature-phase (Q) components; a sampling circuit for sampling the I components at twice a predetermined symbol rate to provide a first series of I-component samples at the predetermined symbol rate and a second series of I-component samples that are intermediate to the first series of I-component samples and at the predetermined symbol rate, and for sampling the Q components at twice the predetermined symbol rate to provide a first series of Q-component samples at the predetermined symbol rate and a second series of Q-component samples that are intermediate to the first series of Q-component samples and at the predetermined symbol rate; and a processor for processing the samples to estimate a phase-adjustment value and a symbol-timing-adjustment value; wherein the processor is coupled to the sampling circuit for adjusting the timing of said sampling in accordance with the symbol-timing-adjustment value; characterised by the processor being coupled to the local oscillator for adjusting the phase of the reference signal in accordance with the phase-adjustment value. The system of the present invention is particularly useful in rapidly acquiring carrier phase and symbol timing of a received communication signal that is characterized by message-bursts, such as utilized in the multiple-user DAMA communication system described in United States Patent No. 5,197,125 to Gernot M. Engel, Dwight R. Bean and Edward F. Smith. Additional features of the present invention are described with reference to the detailed description of the preferred embodiments. The sole figure is a block diagram of a preferred embodiment of the system of the present invention. The Drawing illustrates a preferred embodiment of the system of the present invention that is designed for rapidly acquiring carrier phase and symbol timing of a received PSK-modulated communication signal having a 110-symbol pattern. The system includes a local oscillator embodied in a direct digital synthesizer (DDS) 10, a mixer 12, an analog-to-digital (A/D) converter 14, a down-converter circuit 16, a rate reduction circuit 18 and a digital signal processor 20. The local oscillator 10 provides a reference signal 22 at a local oscillator frequency. The mixer 12 mixes a received communication signal 24 with the reference signal 22 to provide the communication signal 26 at an intermediate frequency. The analog-to-digital converter 14 converts the intermediate-frequency communication signal 26 to a digital communication signal 28. The down-converter circuit 16 formats the digital communication signal 28 into in-phase components I and quadrature-phase components Q. The rate reduction circuit 18 samples the I components at twice a predetermined symbol rate to provide a first series of I-component samples I1 at the predetermined symbol rate and a second series of I-component samples I2 that are half-way intermediate to the first series of I-component samples and at the predetermined symbol rate. The rate reduction circuit 18 also samples the Q components at twice the predetermined symbol rate to provide a first series of Q-component samples Q1 at the predetermined symbol rate and a second series of Q-component samples Q2 that are half-way intermediate to the first series of Q-component samples and at the predetermined symbol rate. The processor 20 processes the samples I1, Q1, I2, Q2 to estimate a phase-adjustment value  A and a symbol-timing-adjustment value ST A . The processor 20 is coupled to the local oscillator 10 for adjusting the phase of the reference signal 22 in accordance with the phase-adjustment value  A and to the rate reduction circuit 18 for adjusting the timing of the sampling a number of samples indicated by the symbol-timing-adjustment value ST A . The processor 20 is adapted for estimating an amplitude component "y" of the symbol-timing-adjustment value ST A by computing: y = (BB2 - BB1)/(BB2 + BB1), wherein B1 (1) = W1 1 + W1 4 + W1 7 + W1 10 + ..., B1 (2) = W1 2 + W1 5 + W1 8 + W1 11 + ..., B1 (3) = W1 3 + W1 6 + W1 9 + W1 12 + ..., B2 (1) = W2 1 + W2 4 + W2 7 + W2 10 + ..., B2 (2) = W2 2 + W2 5 + W2 8 + W2 11 + ..., B2 (3) = W2 3 + W2 6 + W2 9 + W2 12 + ..., W1 n is a complex sample consisting of a first-series I-component sample and a coincident first-series Q-component sample; and W2 n is a complex sample consisting of a second-series I-component sample and a coincident second-series Q-component sample, for n = 1, 2, 3, ... . The processor 20 is adapted for estimating the sign of the symbol-timing-adjustment value ST A by computing: and wherein, the sign is positive when CC1 < CC2, and the sign is negative when CC1 ≥ CC2, C1 (k) = B1 (k) + B2 (k) for k = 1, 2, 3, C2 (1) = B1 (1) + B2 (3), C2 (2) = B1 (2) + B2 (1), and C2 (3) = B1 (3) + B2 (2). In a preferred embodiment, in which there are 40 complex samples per symbol, the symbol-timing adjustment ST A is estimated in accordance with the following equations: ST A = [(6y/0.3077) + 10]/40, for |y| ≤ 0.3077 ST A = 4{[min(y, 0.5) - 0.3077]/[0.5 - 0.3077]}/40 + 16/40, for y > 0.3077 and ST A = 4{[max(y, - 0.5) + 0.5]/[0.5 - 0.3077]}/40, for y <-0.3077 The value 0.3077 defines a transition between a linear mid range and non-linear outer ranges. The symbol timing adjustment ST A simulates an S-curve adjustment characteristic that is commonly used in phase-locked loops. The processor 20 is adapted for estimating a phase-adjustment value  A by computing:  A = ( 1 +  2 +  3 )/6, wherein if BB1 ≥ BB2,  k is the phase angle Φ B of B1 (k) after removing the modulation for k = 1, 2, 3, and otherwise,  k is the phase angle Φ B of B2 (k) after removing the modulation for k = 1, 2, 3; and wherein for B = a + jb, Φ B = tan -1 (a/b). In computing the phase-adjustment value  A , modulo 2π should be considered. While the above description contains many specificities, these should not be construed as limitations on the scope of the present invention, but rather as exemplifications of the preferred embodiments described herein. Other variations are possible and the scope of the present invention should be determined not by the embodiments described herein but rather by the claims

Claims: A system for acquiring carrier phase and symbol timing of a received communication signal (24), comprising a local oscillator (10) for providing a reference signal (22) at a local oscillator frequency; a mixer (12) for mixing a received communication signal (24) with the reference signal to provide the communication signal (26) at an intermediate frequency; an analog-to-digital converter (14) for converting the intermediate-frequency communication signal (26) to a digital communication signal (28); a circuit (16) for formatting the digital communication signal (28) into in-phase (I) and quadrature-phase (Q) components; a sampling circuit (18) for sampling the I components at twice a predetermined symbol rate to provide a first series of I-component samples at the predetermined symbol rate and a second series of I-component samples that are intermediate to the first series of I-component samples and at the predetermined symbol rate, and for sampling the Q components at twice the predetermined symbol rate to provide a first series of Q-component samples at the predetermined symbol rate and a second series of Q-component samples that are intermediate to the first series of Q-component samples and at the predetermined symbol rate; and a processor (20) for processing the samples to estimate a phase-adjustment value Φ A and a symbol-timing-adjustment value ST A ; wherein the processor (20) is coupled to the sampling circuit (18) for adjusting the timing of said sampling in accordance with the symbol-timing-adjustment value ST A ; characterised by the processor (20) being coupled to the local oscillator for adjusting the phase of the reference signal (22) in accordance with the phase-adjustment value Φ A . A system according to Claim 1, wherein the timing of said sampling is adjusted by a number of samples indicated by the symbol-timing-adjustment value. A system according to Claim 2, wherein the processor is adapted for estimating an amplitude component "y" of the symbol-timing-adjustment value by computing: y = (BB2 - BB1)/(BB2 + BB1), wherein B1 (1) = W1 1 + W1 4 + W1 7 +W1 10 + ... , B1 (2) = W1 2 + W1 5 + W1 8 + W1 11 + ... , B1 (3) = W1 3 + W1 6 + W1 9 + W1 12 + ... , B2 (1) = W2 1 + W2 4 + W2 7 + W2 10 + ... , B2 (2) = W2 2 + W2 5 + W2 8 + W2 11 + ... , B2 (3) = W2 3 + W2 6 + W2 9 + W2 12 + ... , W1 n is a complex sample consisting of a first-series I-component sample and a coincident first-series Q-component sample; and W2 n is a complex sample consisting of a second-series I-component sample and a coincident second-series Q-component sample, for n = 1, 2, 3, ... . A system according to Claim 3, wherein the processor is adapted for estimating a phase-adjustment value "  A " by computing:  A = ( 1 +  2 +  3 )/6, wherein if BB1 ≥ BB2,  k is the phase angle Φ B of B1 (k) after removing the modulation for k = 1, 2, 3, and otherwise,  k is the phase angle Φ B of B2 (k) after removing the modulation for k = 1, 2, 3; and wherein for B = a + jb, Φ B = tan -1 (a/b). A system according to Claim 3, wherein the processor is adapted for estimating the sign of the symbol-timing-adjustment value by computing: and wherein, the sign is positive when CC1 < CC2, and the sign is negative when CC1 ≥ CC2, C1 (k) = B1 (k) + B2 (k) for k = 1, 2, 3, C2 (1) = B1 (1) + B2 (3), C2 (2) = B1 (2) + B2 (1), and C2 (3) = B1 (3) + B2 (2). A system according to Claim 5, wherein the processor is adapted for estimating a phase-adjustment value " A " by computing:  A = ( 1 +  2 +  3 )/6, wherein if BB1 ≥ BB2,  k is the phase angle Φ B of B1 (k) after removing the modulation for k = 1, 2, 3, and otherwise,  k is the phase angle Φ B of B2 (k) after removing the modulation for k = 1, 2, 3; and wherein for B = a + jb, Φ B = tan -1 (a/b). A system according to Claim 1, wherein the processor is adapted for estimating a phase-adjustment value " A " by computing:  A =( 1+  2+  3 )/6, wherein if BB1 ≥ BB2,  k is the phase angle Φ B of B1 (k) after removing the modulation for k = 1, 2, 3, and otherwise,  k is the phase angle Φ B of B2 (k) after removing the modulation for k = 1, 2, 3; wherein for B = a + jb, Φ B = tan -1 (a/b); and wherein B1 (1) = W1 1 + W1 4 + W1 7 + W1 10 + ..., B1 (2) = W1 2 + W1 5 + W1 8 + W1 11 + ..., B1 (3) = W1 3 + W1 6 + W1 9 + W1 12 + ..., B2 (1) = W2 1 + W2 4 + W2 7 + W2 10 + ..., B2 (2) = W2 2 + W2 5 + W2 8 + W2 11 + ..., B2 (3) = W2 3 + W2 6 + W2 9 + W2 12 + ... , W1 n is a complex sample consisting of a first-series I-component sample and a coincident first-series Q-component sample; and W2 n is a complex sample consisting of a second-series I-component sample and a coincident second-series Q-component sample, for n = 1, 2, 3, ... .

Inventors: AN SONG HOWARD, AN, SONG HOWARD
Applicants: LINKABIT WIRELESS INC, LINKABIT WIRELESS, INC.
Application year: 1995
Main classification: H04L27
IPC codes: H04L7, H04L27