Process for realizing trench isolation structures

Abstract: A novel process for forming, on a semiconductor substrate, a dielectric isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of: defining an isolation region (45) on a layer of silicon oxide (42) overlying a silicon layer (41); selectively etching the silicon (41) to provide the isolation region (45); growing thermal oxide (43) over the interior surfaces of the isolation structure (45); depositing dielectric (46) conformingly; and oxidizing the deposited dielectric (46).

Description: Field of the Invention The present invention relates to a process for forming, on a semiconductor substrate, a dielectric isolation structure between two zones of an integrated circuit wherein active regions of electronic components have already been defined. The invention relates, in particular but not solely, to electronic devices having a driver circuit and one or more power transistors integrated monolithically thereto, and concerns the formation of a trench isolation structure. Reference will be made hereinafter to this specific application for convenience of illustration. Prior Art As is well known, to form an isolation region between two zones of an integrated circuit is to establish electrical separation therebetween, and this is usually achieved by the interposition of an isolation structure. One possible isolation structure of a known type is depicted in Figure 1a, and is described in Patent Application EP-A-0 509 183, filed on April 17, 1991 by this Applicant. For simplicity, Figure 1a shows a circuit including a single low-voltage driver transistor of the npn type and single power transistor, also of the npn type. This known structure, as described in detail in the above-mentioned patent, uses a diffused zone 4 of the n type, called the junction isolation zone, which separates regions 30 and 31 of the p type to isolate the power stage from the driver circuit. While being advantageous from several aspects, this solution has a drawback in that it is limiting of the breakdown voltage for the resultant components due to inherent features of the method used, which provides for different concentrations of the various dopants. Also directed to isolate the power stage from the driver circuit is a second solution, illustrated in Figure 1b of the aforementioned document, wherein a dielectric isolation region 14' is provided instead of the diffused region 4. While achieving its objective, not even this second solution is devoid of drawbacks. Most serious of such drawbacks is one inherent to the processing sequence used, on account of the isolation region being defined directly after growing the last epitaxial layer, and in any case before forming either the power or the control components. Due to the materials used to form the dielectric isolation region 14' having different expansion coefficients, during the high-temperature, typically above 800°C, thermal cycles required to form the active regions of the components, the monocrystalline silicon lattice is subjected to considerable stresses which may later be relieved in an unelastic manner by dislocations and other crystal defects likely to impair the circuit performance and functionality. In general, the man skilled in the art would regard a temperature below 700 degrees Celsius as being a low one. The same man skilled in the art may find that a temperature above 800 degrees Celsius is a high one. This allows some processing steps which entail deposition of materials to be classified as low-temperature steps, whereas the oxidation and diffusion steps would be steps carried out at high temperatures. However, this is but one example of an isolation scheme known as Deep Trench Isolation (DTI). Comprehensive reviews of known technological approaches are to be found in the references listed here below: [1] H: Goto and K. Inayoshi, "Trench Isolation Schemes for Bipolar Devices: Benefits and Limiting Aspects", Proceedings of the 17th ESSDERC (Bologna, September 1987), 369-372; [2] C. Rapisarda, R. Zambrano, F. Baroetto and P.J. Ward, "Reliable Deep Trench Isolation Scheme for High Density, High Performance Bipolar Applications", Isolation and Trench Technology Symposium (Seattle, October 1990), Proceedings of the 178th Electromechanical Society Meeting, 412-413; and [3] F. Y. Robb et al., "High Voltage Deep Trench Isolation Process Options", Isolation and Trench Technology Symposium (Seattle, October 1990), Proceedings of the 178th Electromechanical Society Meeting, 408-409. References [1] and [2] above deal with the application of the technique to high-performance bipolar devices. To provide effective isolation, the trench should be extended through the n-type epitaxial layer, approximately 1 micron thick. The depth attained by the isolation, with this approach, does not exceed 5 microns. Also known is that, to achieve good planarization, the trench width should not exceed 2 microns, for otherwise, very thick layers of polycrystalline silicon, or polySi, would have to be deposited, resulting in decreased productivity and increased cost of the process. Some problems connected with the extension of this technique to devices which are to operate at higher voltages are discussed in Reference (3) above. It is emphasized there, for example, that the trench depth should be increased, because the epitaxial layers to be etched are thicker, being on the order of 15 to 25 microns thick; on the other hand, trenches with higher aspect ratii (ratio of trench depth to width) than 10 are difficult to make. Other known methods for forming an isolation region are also described in the EP 0 166 141, JP 2030161, EP 0 245 622, EP 0 181 188 and US 4,264,382 documents. The underlying technical problem of the present invention is to provide a method of making a structure for isolating two zones of an integrated circuit, which can overcome the aforementioned limitations and/or drawbacks of prior art methods. Summary of the Invention The technical problem is solved by a process according to claim 1. In this way, a dielectric isolation structure is obtained which can also be applied, in quite a straightforward manner, to devices intended for operation at voltages in excess of a few tens Volts. More particularly, the invention provides for the isolation structure to be formed after the formation of the active zones of the components. Advantageously, this sequential processing scheme allows the stresses built into the silicon, on account of the materials which enter the making of the isolation by high-temperature processes having different coefficients of thermal expansion, to be minimized. Additional advantages come from the possibility of using, for the purpose of planarization, different materials ranging from polycrystalline silicon to deposited oxide layers and perhaps organic materials. All this by virtue of the active zones of the components having been formed earlier, and the only steps left to complete the device being the definition of the contact areas and the steps of metallization and passivation. It should be further noted that the isolation forming technique of this invention affords high productivity. In fact, from information reported in Reference (3) above, it can be appreciated that productivity is a variable of the utmost importance. With the method of this invention, productivity can be kept high at uniquely reduced costs. Table 1 of Reference (3) can be altered by the addition of the following column to encompass information about our own solution, namely: etch equipment wet etch chemistry KOH etch rate >1 micron/minute throughput/cost (wafer/hour/$) 100 wafers/hr/30K$ si ox selectivity 50:1 trench shape isotropic comments easily deeper than 25 microns As can be gathered from the Table, the method of this invention allows isolation regions to be formed to a depth of upwards of 25 microns. This value is essential to the operation of circuits which contain one or more power transistors and a driver circuit operated at higher voltages than a few tens Volts. The features and advantages of the device according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 shows an embodiment of a device with a junction type of isolation according to the prior art. Figure 1b shows an embodiment of a device with a dielectric type of isolation according to the prior art. Figures 2a to 2d show successive steps in the making of the dielectric isolation structure according to the invention. Figures 3a to 3c show successive steps in the making of another modified embodiment of the dielectric isolation structure according to the invention. Detailed Description of the Invention The process sequence which results in a first embodiment of the inventive structure being implemented, is illustrated schematically in Figures 2a-2d, not drawn to scale. Figure 2a is a vertical section view, enlarged but out of scale, of a semiconductor electronic device which has been formed with the active regions and an opening 40, through the oxide 42 provided on the device surface, within the region where the dielectric isolation structure 45 is to be formed. Figure 2b is a view showing schematically the same device as in Figure 2a, after the steps of wet etching the silicon underlying the oxide 41 by means of potassium hydroxide, KOH, and then growing the thermal oxide 43 have been completed. Figure 2c is a schematic view of the device shown in Figure 2b, having a layer of polycrystalline silicon, or polySi, 46 deposited thereon whose thickness is approximately one half the size of the opening 40 formed through the oxide 42. Figure 2d is a schematic view of the device shown in Figure 2c after the polySi 46 oxidation step. The operations which lead to the formation of active regions of the device, namely the emitters and bases of power transistors, the emitters, bases and collectors of low-voltage transistors, isolation regions of the p type, and the collectors of power transistors, are quite the same as described in the aforementioned European Patent Application EP-A-0 509 183. In relation to the sequence that will produce the structure shown in Figure 1a, the operations for defining the diffused region 4 are omitted here; an opening 40 is instead provided through the silicon oxide 42. The silicon 41 area not covered with silicon oxide 42 is then etched to produce a trench which extends down to the epitaxial layer 2 of N - type in contact with the substrate 1 of N + type. The etching can be performed using a wet solution of potassium hydroxide (KOH) or by plasma etching. Alternatively to KOH, an aqueous solution of hydrofluoric acid and nitric acid (HNO 3 ) has been successfully employed at preferred percent concentrations in the ratio of 83:2:205. A high ratio of the etch rates of the silicon 41 and the silicon oxide 42, i.e. a high etch selectivity, is preferred, but the etchant does not need to be anisotropic. Once the etching step is completed, an oxidation is performed whereby a layer of thermal oxide 43 is grown over the walls of the trench 45. Thermal oxide 43 is also grown on the bottom of the trench 45. The process sequence includes, at this point, the deposition of a polySi layer 46. The thickness of this layer is equal to one half the spacing between the two portions of the oxide 42 which are present on the device surface, i.e. one half the size of the opening 40. In this way, since the deposition is a conforming one, that is, the layer is grown evenly in a manner unaffected by topography, the portions of the polySi 46 grown on either sides of the isolation region 42, will merge together at the surface, as shown in Figure 2c, until they cover the opening 40. As a consequence of this, upon such merge, any increase in the thickness of the polySi 47 within the trench will be disallowed, and further depositions of polySi can only lead to surfacial increase of the layer 46 thickness. Since the polySi deposition is carried out at low pressures of a few mTorrs, (one mTorr being equal to 0.13 Pascal) under controlled atmosphere, no air can be trapped inside the trench. Thus, a potentially dangerous condition is avoided where the structure is to undergo subsequent thermal processing at a high temperature. Thereafter, a further oxidation step is carried out in which the surface polySi, 46, is turned into an oxide which bonds to the underlying region 42 to form the surface oxide layer 48, as shown in Figure 2d. The resultant structure is fully planarized. The process is completed by the definition of the contact areas, the metallization required for interconnecting the various components, and the coating of the metallization with glass or some other passivating materials in accordance with conventional methods of processing integrated electronic circuits. A metallization of the underside 49 of the substrate is also contemplated for contacting the collector of the power transistor Cp, as shown in Figure 1a. It should be understood that many changes may be made unto the sequence just described without departing from the scope of the invention. For example: Figure 3a is a schematic view of the same device as shown in Figure 2c, where a layer of silicon nitride (Si 3 N 4 ) has been deposited onto the initial oxide which covers the silicon in Figure 2a before opening the isolation zone, followed by deposition of the polySi after the wet etching step. Figure 3b is a schematic view of the same device as shown in Figure 4a, after the etch-back of the polySi has been carried out. Figure 3c is a schematic view of the same device as shown in Figure 3b, after the oxidation of the remaining polySi. Referring in particular to the example shown in Figure 3a, another modified embodiment will now be described. Over the surface oxide layer 42, a thin layer of silicon nitride (Si 3 N 4 ) 54 may be deposited on which the polySi 55 will then be deposited. This procedure is eminently useful where, in order to avoid increasing the thickness of the surface oxide during the subsequent oxidation step, one wishes to remove the polySi layer 55 to expose the layer 54 of silicon nitride (Si 3 N 4 ). The outcome of this operation is clearly visible in Figure 3c. In fact, the formation of the oxide layer 58 in the zone of the opening 40 will only be obtained, as is due to oxidation of the residual polySi 57 following removal of 55 by etch-back, as shown in Figure 3b. The structure of this invention mainly distinguishes itself from the prior art structures by that it utilizes the two portions of surface oxide for the subsequent planarization step. In the instance of devices which contain one or more power transistors with monolithically integrated control logic, the device dimensions are such that the size of the isolation zone can be regarded as negligible. In fact, no definition of trenches with near-vertical walls, having high aspect ratii and no recesses, is required, and the presence of two "projecting" oxide portions from the silicon etching step is utilized instead as the start point for the dielectric deposition. In the previously discussed Figures 2 and 3, the trench walls have been intentionally drawn at an angle of about 55 degrees from the normal to the surface, just as would be the case if an aqueous solution of potassium hydroxide (KOH) is used for etching the silicon. Finally, it should be emphasized that the invention distinguishes itself from known solutions by a further essential aspect: the trench is defined subsequently to forming the active regions, that is after the heaviest thermal cycles have been completed. Accordingly, the active zones of the components have already been formed and the only steps left to complete the device processing are the definition of the contact area and the metallization and passivation steps.

Claims: A process for forming, on a semiconductor substrate that includes a layer (41) of silicon semiconductor material and a first layer (42, 54) comprising a silicon oxide layer formed thereon, a trench isolation structure (45) between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been formed, characterized in that the process comprises the following steps of: providing an opening (40) having a predetermined size through the first layer (42, 54) comprising a silicon oxide layer to expose a portion of said semiconductor layer (41); selectively etching said semiconductor layer (41) through said opening (40) to form said trench isolation structure (45) having walls and a bottom and produce oxide portions projecting from the walls of said trench isolation structure (45); growing thermal oxide (43) on the walls and the bottom of said trench isolation structure (45); conformally depositing polysilicon (46, 55) on said first layer (42, 54) and on the walls and a bottom of said trench isolation structure (45) said polysilicon having a thickness of one half the predetermined size of the opening (40), such that a void remains in said trench isolation structure (45) then oxidising at least a portion of said polysilicon (46, 55) thus providing the electrical isolation of said two zones of the integrated circuit. A process according to Claim 1, wherein said first layer (42, 54) also comprises a silicon nitride layer (54). A process according to Claim 2, further comprising a step of etching-back the polysilicon (55) down to said silicon nitride layer before the step of oxidising.

Inventors: ZAMBRANO RAFFAELE, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, CO.RI.M.ME.CONSORZIO PER LA RICERCA SULLAMICROELETTRONICA NEL MEZZOGIORNO
Application year: 1995
Main classification: H01L21
IPC codes: H01L27, H01L29, H01L21