Method of forming a damascene structure with WGe polishing stop

Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH 4 gas followed by WF 6 can be used to produce an in-situ hard cap of W x Ge y . Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450 °C) without degrading the underlying metals.

Description: Field of the Invention The present invention generally relates to a method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), and more particularly to a method for producing the metallization for interconnecting wiring in an integrated circuit. A W x Ge y hard cap is employed for wearresistance. GeH 4 gas followed by WF 6 can be used to produce the in-situ hard cap of W x Ge y . Description of the Related Art Low resistivity metals such as aluminum and copper and their binary and ternary alloys have been widely explored as fine line interconnects in semiconductor manufacturing. Typical examples of fine line interconnect metals include Al x Cu y ,where the sum of x and y is equal to one and both x and y are greater than or equal to zero and less than or equal to one, ternary alloys such as Al-Pd-Cu and Al-Pd-Nb, Al-Cu-Si, and other similar low resistivity metal-based alloys. Emphasis on scaling down line width dimensions in very large scale integrated (VLSI) circuitry manufacture has led to reliability problems including inadequate isolation, electromigration, and planarization. Damascene processes using metal filling vias and lines followed by chemical/mechanical polishing (CMP) with various Al, Cu and Cu-based alloys as are a key element of future wiring technologies for very large-scale system integration (VLSI). A key problem is filling high aspect ratio vias and lines without voids or seams, and creating homogeneous structures. Metallo-organic chemical vapor deposition (MOCVD) appears to be a promising method but only in the beginning stages of fabrication, and the deposition rates are very slow and the in-situ deposition of thin lines is very difficult. Additionally, laser melting appears promising but many issues remain in applying such a fabrication method. Furthermore, high temperature bias sputtering (i.e., above 450 °C) technique has been attempted but this technique has limitations below 1 µm geometries. Additionally, such high temperatures would degrade the underlying metals. Additionally, conventional techniques such as chemical vapor deposition (CVD) or plating appear promising but as yet have not been applied to fabrication of such a structure. Currently, there is no method which allows the use of physical vapor deposition (PVD) techniques or which improves the quality of CVD or plating films if required for filling high aspect ratio vias and lines. Further, low resistivity Cu or Al lines are being evaluated for back-end metallization and packaging applications. However, good fill of these alloys in submicrometer lines is still challenging as the existing techniques mentioned above lack adequate filling properties. The exotic and expensive CVD methods to deposit Cu or Al-Cu (e.g., metallo-organic chemical vapor deposition (MOCVD), laser melting, high-temperature bias sputtering, Al-Ge on poly substrate, etc.) are being explored, but have drawbacks as mentioned above. Another alternative would be formation of low eutectic Al-Ge by sputtering, but this technique requires different targets and a fixed composition degrades the lines' electromigration properties. Plating is an inexpensive technique, but it cannot deposit any combination of alloys (e.g., Al-Cu, Al-Nb-Pd, etc). Additionally, pure Cu from Al-Cu alloy is known for its poor corrosion resistance. Further, any selective technique is prone to loss of selectivity and therefore the capping of dense Al-Cu lines, without affecting the yield, remains a great challenge. Presently, 4Mb and 16Mb memories typically employ Al-Cu lines and W via interconnects. CVD is used to conformally deposit W into the vias. However, as dimensions decrease and current densities increase, W will have to be replaced with a different metal similar to the ones used for the first metal layer (M1) or second metal layer (M2) interconnect structure to form the hard layer. A suitable choice would be Al-Cu or Cu. However, these metals are very difficult to deposit by CVD, because of very slow deposition rates, the lack of a good precursor, and because deposition occurs at temperatures, such as above 450 °C, that are believed too high for back-end-of-line (BEOL) applications. In one example of the conventional techniques, (as disclosed for example, in Kikuta et al. PROC. OF 1991 VMIC CONFERENCE, pp.163-170 and Kikuta et al., "0.25 µm Contact Hole Filling by Al-Ge Reflow Sputtering", Proceedings of the 1991 Symposium on VLSI Technology, pp. 35-36), sputtered Al-Ge material was used for via fill. However, this structure exhibited high line and via resistance and also required a polysilicon underlayer. Further, only a binary alloy is described and in a technique in which alloying is homogeneous, a high Ge content is required and thermal stability is degraded. It is well-known to deposit low resistivity metals such as Al-Cu by increasing the temperature close to its melting point (e.g., 580 °C) and reflowing it by using substrate biasing. Such high temperatures as well as bias degrades the already deposited metal layers and causes diffusion as well. Normally, these temperatures in the conventional methods are above 475 °C. Other problems of the conventional structures and methods have been that damascene of soft metals (e.g., metals such as Al-Cu, Cu, alloys of Al, etc.) shows scratching and smearing using harder suspension particles in the slurry and that conventional sputtering techniques are unable to fill lines including high temperature, bias sputtering. Significant challenges exist in filling and forming scratch-free, soft metal lines and the conventional methods have been unable to provide a practical and effective solution thereto. EP-A-0 558 004 discloses creating electrically conductive vias and lines by a three step process. First, a controlled amount of a soft, low resistive metal is deposited in a trench or hole to a point below the top surface of the dielectric in which the trench or hole is formed. Subsequently, the low resistive metal is overcoated with a hard metal such as CVD tungsten. Finally, chemical mechanical polishing is used to planarize the structure. Summary of the Invention It is therefore an object of the present invention to provide a low resistivity line or via with a wear resistant, hard cap which reduces electromigration. The invention provides a method according to claim 1. As discussed below, GeH 4 gas followed by WF 6 can be used to produce an in-situ hard cap of W x Ge y . A good polish stop is provided in the form of W x Ge y . The hard capped W x Ge y can be formed in one step and, with the invention, there is no degradation of line resistance and the electromigration of Al-Cu-Ge system can be improved in relation to the conventional systems. Brief Description of the Drawings The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of the preferred embodiments of the invention with reference to the drawings, in which: Figures 1(a)-1(b) are cross-sectional views of a semiconductor substrate; Figures 2(a)-2(b) are cross-sectional views of a semiconductor substrate; Figures 3(a)-3(b) are cross-sectional views of a semiconductor substrate in which voids encountered during a sputtering process are closed by a reaction of GeH 4 ; Figure 4 is a cross-sectional view of a semiconductor substrate which may be formed by the method of the present invention in which a W-Ge layer is deposited on top as a hard polishing stop; Figure 5 is a cross-sectional view of a semiconductor substrate in which the lines or vias formed are etched-back or polished to form interconnect lines. Figure 6 is an SEM photograph of the CMP resultant of Al-Cu + GeH 4 . Figure 7(a) and 7(b) are photographs illustrating GeH 4 being reacted to fill aspect ratios close to 4-5. Figure 8 illustrates a multilevel structure by Example 1. Figures 9(a)-9(c) illustrate a dual damascene structure process flow and Figure 9(d) illustrates a multilevel structure produced by Example 2. Figure 10 illustrates via chain yield as a function of via resistance. Figure 11(a) illustrates electromigration performance of Al-Cu studs/lines by Example 1 and Figure 11(b) illustrates electromigration performance of Al-Cu studs/lines by Example 2. Figure 12 is a graph illustrating the relationship of step coverage to atomic weight (or melting point) of the material at room temperature for holes/lines with an aspect ratio of 4. Detailed Description of a Preferred Embodiment of the Invention Referring now to the drawings, and more particularly to Figure 1, there is shown a general process not forming part of the present invention. The invention is particularly useful in fabricating circuits using FETs, bipolars, or BiCMOS, and is especially useful for lithographic structures less than 0.5 micrometer , (e.g., those commonly encountered with the 64Mb and 256Mb DRAM structures). Of course, the invention is not limited to such applications and it is envisioned that the invention could be easily tailored to other applications by one ordinarily skilled in the art reading this application. In a process described below but not corresponding to that of the invention low temperature germanium gas flow is used to affect metals and alloys deposited in high aspect ratio structures including lines and vias. The metals and alloys preferably include a first element which preferably is an element from the group of aluminum, gold and silver, and a second element of germanium. The metal alloy preferably has first regions of germanium in a range of from 0 to 40 at. percent and second regions of germanium in the range of from 60 to 100 at. percent. The metal alloy preferably includes a third region of Al-Ge and Cu 3 Ge. The second region of the metal alloy advantageously includes a ternary metal alloy and the metallization preferably includes a layer of W x Ge y over the metal alloy. By using a germanium gas flow, Ge will be introduced in a surface reaction that will prevent the appearance of voids and side seams. The surface reaction is also useful in that it also provides a passivating layer of CuGe. Additionally, the germanium gas flow with WF 6 produces a hard cap layer of W x Ge y . More specifically, the method fills high aspect ratio lines/vias using surface reactions of GeH 4 and WF 6 , in which a low resistivity alloy (e.g., Al x Cu y , x + y = 1, 0 < x < 1 ) can be deposited either by chemical vapor deposition (CVD), plating or physical vapor deposition (PVD) techniques. The gradual flows of GeH 4 at elevated temperatures on these alloys result in filling up voids or gaps present at the seams or at the sides by forming in-situ low eutectic Al-M-Ge or Cu-Ge alloy. By slowly introducing WF 6 , a hard, wear-resistant coating (W x Ge y ) is deposited on top of an Al-Cu-Ge layer as a polish stop for soft alloys. After forming the lines/vias, the W alloy cap can be removed by an SF 6 reactive ion etching (RIE) process or the like. The resulting structure formed by the reaction of GeH 4 is unique and improves electromigration of the structure. It should be understood that the techniques and resulting structures are not limited to using any specific substrates and dielectric overlays. Moreover, the invention is not restricted to any particular metal combinations; rather, an objective of the invention is to overlay a metal or metal alloy with a W-Ge hard cap which can withstand wear, corrosion and electromigration. The invention has particular relevance to electrical systems which use aluminum and copper alloys, but can also be equally used to advantage with other metal alloys. A structure and process for filling high aspect ratio vias/lines with low resistivity metal by forming its low melting point eutectic alloy will now be disclosed. Also, the formation of the hard cap of W-Ge as a polishing stop will also be described. Generally, as shown in Figures 1-5, first GeH 4 is introduced and then WF 6 is introduced gradually to form a bilayer structure of Al-Cu-Ge/W x Ge y . Here, the GeH 4 gas is employed for filling of the low resistivity alloys deposited practically by any method. For example, any PVD, plating or CVD technique can be used in combination with GeH 4 . Examples of such fillings are shown in Figs. 1-5 and as described below. In a first example, as shown in Figures 1(a) and 1(b), a substrate (not illustrated) is first overcoated with a dielectric 10 which is subsequently patterned. The substrate is preferably silicon, silicon germanium, germanium, gallium arsenide, or some other material which is suitable for making integrated circuits. However, the substrate may be a ceramic, glass, or composite material commonly used for packaging semiconductors and for making thin film interconnections. The substrate preferably has a plurality of semiconductor devices formed therein which may include field effect transistors (FETs), bipolar transistors, BiCMOS, resistors, Schottky diodes, or the like. Of course, the substrate can have any of the attributes discussed above plus many other attributes known within the art. The dielectric (a single layer, as shown in the drawings, or a composite having a plurality of layers) may be formed of organic and/or inorganic materials. The inorganic materials may be silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or the like. The dielectric 10 is preferably deposited using plasma-enhanced chemical vapor deposition (PECVD). An organic dielectric layer, such as a polyimide or diamond-like carbon (DLC), may be deposited on top or between one or more inorganic layers of the dielectric. Alternative to a dielectric composite created by a plurality of layers, a single layer of an inorganic dielectric, such as SiO 2 , PSG, or BPSG, or an organic dielectric, such as polyimide, may also be employed and may be deposited by any of a number of well-known techniques such as by growing in an oxidative atmosphere, sputtering, or PECVD. While Figs. 1(a) and 1(b) show the use of a single dielectric layer, it is understood that the dielectric layer 10 is not limited and that any dielectric (e.g., inorganic or organic) used by itself or in combination could be employed. An opening 11 is formed in the dielectric composite, and this opening may be a via or a trench for a conductive line. In VLSI applications, the substrate is likely to have several hundred to thousands of openings 11 like that shown in Figure 1(a) where the resulting dense, complex pattern will ultimately interconnect circuits on or in the substrate. The openings 11 are preferably formed using contrast-enhanced lithography (CEL) followed by trench or hole etching with a multiwafer tool using CHF 3 and O 2 with an optimum overetch to ensure that the opening 14 has the desired dimensions and extends to a contact on the surface of the substrate for a via stud pattern. For line patterns, the dielectric layers are preferably partially etched to a depth about 10% higher than the metal thickness to be employed. When etching polyimide, O 2 RIE at low temperatures is preferred. It should be understood that the formation of the opening 11 is well understood within the art and can be created by many different techniques. Thereafter, a suitable material 12 such as Ti followed by Al-Cu or Cu, is deposited by PVD (e.g., evaporated, collimated sputtering or sputtering without collimation, etc.) in the openings 11 (e.g., trenches/vias) and over the dielectric 10. Instead of Al, gold or silver can be advantageously used. Then, a refractory metal layer 13 is deposited on top of the Al-Cu or Cu on the dielectric and in the trenches. Due to shadowing effects, PVD (e.g., evaporation) exhibits seams at the sides of the structure. Seams are problematic in such structures since they pose reliability problems. Thereafter, a GeH 4 gas is flowed across the top surface of the Al-Cu or Cu layer 12, and the vias are filled. Preferably, the GeH 4 is flowed at a pressure of 1 mT to 760 Torr, and more preferably 1 Torr, and at a temperature of 300 °C to 450 °C, and more preferably 380 °C to 400 °C. Using GeH 4 in combination with Al-Cu lowers the eutectic point of Al-Cu and fills the vias. As mentioned above, the top of the Al-Cu or Cu is preferably capped as shown in Fig. 1(a) with the refractory metal. The refractory metal layer can be titanium (Ti), titanium alloys or compounds such as Ti/TiN, tungsten (W), titanium/tungsten (Ti/W) alloys, or chromium (Cr) or tantalum (Ta) and their alloys, or some other suitable material. Such a refractory metal cap prevents the surface reaction from progressing and promotes the side reaction. Preferably, the metalization 14, as shown in Figs. 1(a)-1(b) is Al x Cu y , where the sum of x and y is equal to one and both x and y are greater than or equal to zero and less than or equal to one. However, ternary alloys such as Al-Pd-Cu and multicomponent alloys such as Al-Pd-Nb-Au are also be suitable. The principal characteristic of the metalization 14 is that it is a low resistivity and soft material compared to the refractory metal cap 13. Preferably, the opening 11, which represents the line pattern or interlevel via pattern, is filled with the metalization 14 to a depth of 100 to 400 nm below the surface of the line or via. After reacting this structure with GeH 4 as shown in Equation 1, the side seams are filled with its low melting point eutectic alloy 15 which is Al-Cu-Ge, as shown in Fig. 1(b). Al x Cu y + (x+y) GeH 4 → xAl-Ge + y(Cu-Ge) + 2(x+y) H 2 Referring to Figures 2(a)-2(b), this illustrates the closing of the metal gaps during PVD processing (e.g., evaporation, collimation sputtering, etc.) due to the shadowing effects mentioned above. Specifically, by reacting the Al-Cu alloy with GeH 4 in a temperature range of between 300-450°C and preferably between 350 °C to 400 °C, and even more preferably between 380 °C to 400 °C, and a pressure range of 26.66 to 133.32 N/m 2 (0.2 to 1 Torr) in an ultrahigh velocity (UHV) reactor, voids 20 are advantageously closed, as shown in Fig. 2(b). As shown in Figs. 3(a)-3(b), similar voids encountered during standard sputtering processes are closed by the reaction of GeH 4 and the formation of the low melting point eutectic material. Thus, without any complicated technologies, this process can be used for manufacturing to fill vias and lines. The reaction forms the low melting point (m.p.) eutectic alloy and flows the material to the center of the void, to thereby fill the void. In an alternative process, once the material flow is achieved, a W-Ge layer 30 or the like is preferably deposited over the refractory material layer and the metalization, as shown in Fig. 4. The W-Ge layer 30 is advantageously used as a hard, wear-resistant polishing stop (e.g., it will be more resistant to an alumina slurry or the like in ferric nitrate used in chemical-mechanical polishing or the like). Thereafter, the lines or vias are formed and they are preferably etched-back or polished to form interconnect lines, as shown in Fig. 5. The structure is planarized after the application of the W x Ge y to yield a structure having a conductive via or line, which includes a central, soft, low resistivity metalization 14 having a hard, wear-resistant cap made of W x Ge y or the like. The top surface of the via or line is even with the top surface of the dielectric material on the substrate. Planarization can be accomplished within one or two steps by chemical-mechanical polishing with a slurry such as alumina in dilute ferric nitrate or by RIE in the presence of SF 6 or Cl 2 based chemistry. Alternatively to the technique described above, the lines and vias can be formed in one step by depositing the material into vias in combination with GeH 4 reaction and then patterning and etching the lines to form the interconnect structure. Experiments have shown that, with the aforementioned process, a low temperature eutectic of Al-Cu-Ge (Cu 3 Ge) can be formed with a GeH 4 reaction at temperatures below 400 °C and furthermore, that a low temperature Ge material containing a hard W cap can be deposited on top of the Al-Cu alloy. Using such a process (i.e., surface diffusing GeH4 with Al-Cu) aspect ratios of 4 to 5 are filled without voids as shown in the photographs of Figs. 6 and Figures 7(a) and 7(b). The additional experiments performed using GeH 4 reactions are listed in Table 1 below. The data clearly shows that voids may be filled using the above-described process. Metal Pressure (N/m 2 (mT)) Step Coverage Aspect Ratio Al-Cu 2.67 x 10 -2 (0.2) 100 % 3.0 6.67 x 10 -2 (0.5) 100 % 2.5 1.07 x 10 -1 (0.8) 100 % 2.0 The above-described technique provides a simple and inexpensive solution to problems which become worse as the lithographic ground rules decrease below 0.5 micrometer. Further, the above technique is advantageous in that it has many applications and the process relies on surface reactions. Hence, it selectively forms a low melting point eutectic alloy in the vias only, thereby to prevent voids and seams. The process can be used as a batch or single wafer reactor (SWR) deposition if desired. Further, the process provides a low-cost technique which can use any PVD technique (e.g., evaporation, standard sputtering, etc.). Further, regarding the hard cap of W x Ge y , W 3 Ge 5 -20-30µΩCm has a polish rate 1/5 of that of pure W. Further, large pads/lines and small pads/lines are protected as well in that resistances of large and small pads remain unchanged. Experiments were conducted with the above structure and the following results were found: Material Holder temperature Resistivity Al-Cu-Ge As-Dep 3.6µΩ Cm 400, 15 min 3.2µΩ Cm 400, 30 min 4.2µΩ Cm 400, 40 min 5.9µΩ Cm 400, 60 min 8.9µΩ Cm In silicon back-end metallization for CMOS as well as bipolar applications to fill high aspect ratio contacts and vias with conventional techniques in combination with GeH 4 and WF 6 (if this is desired) and further the electromigration performance of the Al-Cu alloys using the aforementioned technique and structure can be improved in relation to that of the conventional structures and methods. Further, expensive and complex apparatus are not required, and the use of low melting-point alloys as via fill materials is possible. These alloys can be matched with the Al-Cu lines and interconnects so as to prevent electromigration and limited lifetimes. Further, the technique is particularly useful when the lithography ground rules are less than 0.5 micrometer, as in, for example, fabrication of 64Mb and 256Mb dynamic random access memory (DRAM) structures. Additionally, the Al-Cu lines and W can be used for via interconnects between wiring layers. In cases in which high aspect ratio vias/lines are filled by surface diffusion, a low pressure sputtering process is used along with temperatures below 450 °C. The directionality is improved at low pressure (e.g., below 1.33 x 10 -1 M/m 2 (1 mT), with the preferred range being from 1.07 x 10 -1 N/m 2 (0.2mT to 0.8mT)) although the cosine distribution from the target prevails. If the deposition is performed at low pressure at room temperature (see Table 2 below), an aspect ratio of close to 4 can be filled without voids (see Table 2). The aspect ratio generally refers to the ratio of the height of a trench or via relative to its width (in the case of a trench) or its diameter (in the case of a via). Trenches and vias with aspect ratios greater than two are generally considered to have a high aspect ratio. By increasing the pressure at room temperature, the fill is adversely affected as shown in Table 3 below. Thus, to fill higher aspect ratio (e.g., higher than 4) moderate temperatures below 450 °C are needed. The results in Figure 4 show that at moderately low pressures and low temperatures, higher aspect ratios (4 and above) can be filled. One possible explanation for this behavior may be due to the increase of kinetic energy of the sputtered atoms emitted at low pressures. Such atoms with high energy have a low sticking coefficient (.1 to 0.3) compared to sputtered atoms generated at higher pressure (1.07 x 10 -1 N/m 2 to 1.33 x 10 -1 N/m 2 (0.8 mT to 1 mT)). Since they have high energy (greater than 1 eV), they do not stick to a vertical wall, but instead bounce off or diffuse until a stable configuration is reached. Further, large mean free paths at lower pressure may assist in minimal collision with other atoms and thus retain the kinetic energy. Additionally, moderate temperatures (e.g., lower than 450 °C) may increase the surface diffusion characteristics of the sputtered atoms yielding a void-free fill. Thus, at low pressures such as 2.67 x 10 -2 N/m 2 (0.2 to 0.8 mT), high aspect ratio (aspect ratio of 4 or more) vias may be filled with a low resistivity metal completely as shown in Tables 2, 3 and 4. STEP COVERAGE PRESSURE ASPECT RATIO Al Al-Cu (2%) 2.67 x 10 -2 N/m 2 (0.2 mT) 1.5 100 100 2.0 100 100 3.0 100 98 3.5 100 97 4.0 98 95 POOR FILL AT HIGH PRESSURES ASPECT RATIO PRESSURE Al Al-Cu (2%) 4 5.33 x 10 -2 N/m 2 (0.4 mT) 96 97 1.07 x 10 -1 N/m 2 (0.8 mT) 55 52 2.67 x 10 -1 N/m 2 (2.0 mT) 32 30 GOOD FILL AT LOW PRESSURES AND HIGH TEMPERATURES ASPECT RATIO PRESSURE Al Al-Cu (2%) 4 5.33 x 10 -2 N/m 2 (0.4 mT) 100 100 1.07 x 10 -1 N/m 2 (0.8 mT) 100 100 2.67 x 10 -1 N/m 2 (2.0 mT) 80 70 Formation of Multilevel Structure Example 1 - Combination of RIE and Damascene Process (Fig. 8) The two-level structure shown in Figure 8 is formed by first depositing sputtered layer (0.8 micrometer) as a stack and then patterning to form a line. A dielectric layer, as known in the art, was deposited thereon by a deposition/etching/deposition etch process flow. Then, the dielectric was planarized by chemical and mechanical polishing. Planarization can be accomplished within one or two steps by chemical-mechanical polishing with a slurry such as alumina in dilute ferric nitrate or by RIE in the presence of SF 6 or Cl 2 based chemistry. If chemical-mechanical polishing is employed, slurries can be selected to remove different metal layers on the stack depending on hardnesses of the metal layer. Thereafter, vias were opened up and filled with an Al-Cu stud (having, for example, between 0 to 4 % of Cu) using these two processes (e.g., the GeH 4 reaction with Al-Cu and/or the other process of using sputtering at low pressures and high temperatures). The metal was left in the via by an etchback process employing either chemical and mechanical polishing (using an alumina and ferric nitrate slurry and low polishing pressures) and separately using RIE techniques (using BCl 3 + Cl 2 + CHCl 3 /N 2 ). If chemical and mechanical polishing is employed, slurries can be selected to provide scratch-free surfaces. Once again, the Ti/Al-Cu/Ti/TiN layer was deposited on top of these vias and then patterned by lithography and formed by RIE to form an interconnect. Such a structure has been electrically tested by the present inventors. Example 2 - Dual Damascene Process (Figure 9(a)-9(d)) In a further example, as shown in Figs . 9 (a)-9(d), a first level metal line (Ti/Al-Cu (0.5%)/Ti was formed by forming a trench in a patterned oxide, then polishing the excess metal using softer slurry (e.g., colloidal silica with a low pH compared to alumina and ferric nitrate). Thereafter, an oxide having a thickness of substantially 2 micrometer was deposited thereon. Patterning with metal level 2 (M2) was performed, and then the oxide was etched to 1 micrometer and the resist was removed. Once again, using lithography, the oxide was patterned with vias which were opened down to metal level 1 (M1) with RIE. After removing the resist, metal (e.g., Al-Cu(0.5%)) was sputter deposited at low pressures and at 400 °C. Using the surface diffusion, the high aspect ratios were filled without voids. Using the above-mentioned polishing process, Al-Cu was removed from the field oxide and thus a dual damascene structure was created, as shown in Figure 9(d). Thus, a method of creating one of a dual damascene and a damascene structure in combination with reactive ion etching, on a substrate on which a stack including a metal layer (e.g., Al-Cu, Al, Al-Cu-Ge, or the like) having a predetermined hardness, is fabricated, is also provided. The method includes removing the metal layer having the predetermined hardness, by chemical and mechanical polishing using slurries having a hardness two to three times that of the material to be removed (e.g., colloidal silica in the case of Al-Cu, etc.). Furthermore, if a hard cap such as, for example, W x Ge y , is employed, then harder suspension particles in the slurry can be employed (e.g., alumina or the like). Electrical Results were obtained via chain resistance of the obtained multilevel structure using these different examples as shown in Figure 10. The distribution is normal with a mean resistance of 0.5kΩ Ohms for a chain (500 vias/chain, via size of 0.7 µm, and 38 chains tested). The yield on the chain is 100%. The via resistance is comparable to CVD W studs. Electromigration testing of the two level structure (shown in Fig. 9(d)) using a 1.4 µm-wide and 300 µm long Al-2%Cu line connected by Al-Cu studs having a 1 µm diameter was performed at a current density of 1.22 MA/cm 2 at a temperature of 250 °C. The 20% shift in resistance was used as a criterion of failure. The electromigration performance was compared against CVD W studs. An electromigration normal logarithmic plot for Al-Cu formed GeH 4 reaction and Al-Cu alone by low pressure sputtering at 440 °C alone is shown in Figs. 11(a) and 11(b), respectively. W via samples (not illustrated) shift to higher resistance values than Al-Cu via samples before electrical opening (i.e., complete failure). A 20% change in the resistance as the failure criterion, the Al-Cu via sample exhibits a higher mean-time-to-fail t 50 (for Al-Cu-Ge sample: 116 hours, and for low pressure 440 °C sputtered Al-Cu: 6161 hours as opposed to 86 hours for CVD W) and a higher σ than the W via samples compared with them. Hence, the Al-Cu via electromigration results show significant improvement in t 50 over CVD W via samples. As pointed out above, several factors affect the fill for low resistivity metal including pressure and temperature which the present inventors have studied to explore the surface diffusion effects. Figure 12 illustrates the relationship of step coverage to atomic weight (or melting point) of the material at room temperature for holes/lines with an aspect ratio of 4. Figure 12 readily illustrates that with lower atomic weight or melting point material, it is easier to fill the vias at room temperatures and low pressures for aspect ratios below 4. To fill higher aspect ratios, other sputtering parameters play a key role. To achieve such material fill, a relationship between step coverages and sputtering parameters for material fill has been found by the present inventors. The relationship is as shown in Equation 2. SC = K · M p -a · M W -a · P -b · A R -c ·  -d · T e In Equation 2, SC is the step coverage of the material to be filled; M p is the melting point of the material; M W is the atomic weight of the material; A R is the aspect ratio of the trench or hole; P is the operating pressure (mT); T is the substrate temperature (°C);  is a dimensionless quantity = tan() = D1-D2/2H; and K = material dependent constant. Constants and coefficients are as follows: a = 0.2 b = 0.25 (high weight) - 0.51 (low weight) c = 0.21 - 0.27 ≤ 0.03 (for low weight) (e.g. Al, Al-Cu) d ≤ 0.1 e = 0.6 - 0.7 K = 3-5 (≈ 4.0 - 4.5) D1 = diameter of target D2 = diameter of substrate H = distance between target and substrate Hence, as illustrated in Figure 12, the relationship of step coverage to atomic weight, or the melting point, of the material at room temperature for holes/lines with an aspect ratio of 4 is shown and it can clearly be seen that, with lower atomic weight or melting point material, filling of the vias at room temperatures and low pressures for aspect ratios below 4, can be performed more easily. Further, the above equation amply illustrates the relationship between step coverages and sputtering parameters for material fill and the fill being dependent on the atomic weight is clearly shown. Thus, as described above, a metallization for interconnecting wiring in an integrated circuit is provided. The metallization includes a metal alloy for forming at least one of a line and via within a dielectric structure having sidewalls. The metal alloy includes a first element selected from the group consisting of aluminum, gold and silver and a second element of germanium. The metal alloy having first regions of germanium in a range of from 0 to 40 at. percent and second regions of germanium in the range of from 60 to 100 at. percent. The metal alloy preferably includes a third region of Al-Ge and Cu 3 Ge. The second region of the metal alloy preferably includes a ternary metal alloy and the metallization preferably includes a layer of W x Ge y over the metal alloy. Further, the method described above for forming a metal alloy on a substrate having an upper surface, includes heating the upper surface of the substrate to a temperature in the range from 300 to 450°C, and flowing a gas containing germanium over the upper surface of the substrate, the upper surface having regions containing exposed aluminum, or Cu alloys, whereby the germanium in the gas reacts with the Al-Cu to form an aluminum alloy for flowing into adjacent openings due to surface tension of the aluminum alloy. The step of flowing a gas preferably includes selecting GeH 4 . Preferably, the method also includes a step of flowing a gas containing W after the step of flowing a gas containing germanium to form a hard cap.

Claims: A method of creating one of a dual damascene and a damascene structure on a substrate on which a stack is fabricated, said stack including a metal layer having a hardness, said method comprising the steps of: removing said metal layer having said hardness, by chemical and mechanical polishing using slurries having a hardness at least twice that of said metal layer to be removed, said step of removing including chemical and mechanical polishing employing a slurry including alumina; characterized in that said metal layer has a hard cap consisting of a tungsten-germanium alloy functioning as a chemical mechanical polishing stop layer. A method according to claim 1, wherein said slurry hardness is two to three times as hard as said metal layer to be removed.

Inventors: JOSHI RAJIV VASANT, SRIKRISHNAN KRIS VENKATRAMAN, TEJWANI MANU JAMNADAS, JOSHI, RAJIV VASANT, SRIKRISHNAN, KRIS VENKATRAMAN, TEJWANI, MANU JAMNADAS
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1995
Main classification: H01L21
IPC codes: H01L23, H01L21