Junction field effect transistor and method of producing the same

Abstract: For suppressing generation of leakage current and side-gate effect in a junction field effect transistor, a gate extension (43A) is formed on a semi-insulative compound semiconductor substrate (40) in a manner to extend from a gate (43) and to protrude outward beyond a channel (41) transversely thereto, and an insulating layer (44) is formed on the semi-insulative compound semiconductor substrate (40) under the gate extension (43A). A method of producing this transistor comprises the steps of first forming a channel (41) and a source-drain (42) on a substrate (40), then forming a gate (43) on the channel (41) together with a gate extension (43A) which extends from the gate and protrudes outward beyond the channel (41) transversely thereto, and forming an insulating layer (44) adjacently to the channel (41) and the source-drain (42) in such a manner that no gap is existent between the insulating layer (44) and at least the channel (41).

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a junction field effect transistor formed on a semi-insulative compound semiconductor substrate, and also to a method of producing such a transistor. Description of Related Art Remarkable development is currently in progress with regard to an integrated circuit which is formed on a semi-insulative compound semiconductor substrate composed of GaAs and is adapted for high-speed operation in a gigahertz band of microwave or millimetric wave region. Furthermore, it is presently observed that such integrated circuit begins to be employed as an amplifier circuit for a portable telephone or the like using a frequency band of 1 GHz or so. This integrated circuit usually consists of MES field effect transistors or junction field effect transistors. A conventional n-type junction field effect transistor formed on a semi-insulative compound semiconductor substrate is shown in Fig. 1. Fig. 1A is a typical plan view, and Figs. 1B and 1C are typical partial sectional views taken along lines B-B and C-C in Fig. 1A, respectively. It is to be understood that, in some cases hereinafter, such a semi-insulative compound semiconductor substrate will be referred to simply as a substrate, and an ordinary n-type junction field effect transistor will be referred to simply as a field effect transistor in the following description. A brief summary will now be given explaining a method for production of a conventional n-type junction field effect transistor according to the related art. Although a gate electrode and a source-drain electrode are formed in the field effect transistor, these electrodes are omitted in the diagrams. Further, in a diode and a resistance element, there are formed electrodes and terminals as well. However, these are also omitted in the diagrams. First a source-drain 12 composed of an n ++ -type conductive region is formed by implanting silicon ions into a substrate 10 of GaAs where a photo mask is formed. Thereafter a channel 11 composed of an n + -type conductive region is formed by removing the above photo mask, then forming another photo mask, and implanting silicon ions again into the substrate 10. Subsequently, annealing is executed to activate the ion-implanted silicon which is an n-type impurity. Next, an insulating film of, e.g., SiN (silicon nitride) is formed by CVD or the like on the entire surface including the channel 11 and the source-drain 12, and then an opening is formed in the insulating film above the channel 11 by the techniques of photolithography and etching. Thereafter a gate 13 composed of a p ++ -type conductive region is formed by diffusing zinc into the channel 11 through a heating process while causing a gas, which includes diethyl zinc (DEZ), to flow into the opening formed in the insulating film. In this step, the gate 13 is so formed as to protrude outward beyond the channel 11. More specifically, there is formed a gate extension 13A which protrudes beyond the channel 11 transversely thereto. When the width of the gate 13 is changed with respect to the channel 11, a current flowing in the field effect transistor is also changed. Accordingly, in order to attain a sufficient margin in the process of producing a field effect transistor, the structure thereof is so contrived that the gate 13 protrudes outward beyond the channel 11. Subsequently, an element isolating region 20 is formed for the purpose of ensuring a required electric insulation between mutually adjacent field effect transistors. The element isolating region 20 is formed by implanting boron ions into a substrate region where any field effect transistor is not existent, hence obtaining the structure of Fig. 1. In the method of producing such a conventional n-type junction field effect transistor, when boron ions are implanted at the above processing step, the element isolating region 20 is spaced apart by 0.3 µm to 1.0 µm from the channel 11 and the source-drain 12, as shown in Figs. 1A, 1B and 1C. Reference numeral 41 denotes a region formed between the element isolating region 20 and both of the channel 11 and the source-drain 12. A portion 13B of the gate extension 13A of the gate 13 protruding outward beyond the channel 11 is in a state not overlapping the element isolating region 20. The distance from the channel 11 to the element isolating region 20 is dependent solely on the positioning precision of the photo mask at the time of forming the element isolating region 20 by ion implantation. Due to the existence of such portion 13B of the gate extension 13A, there arises a problem that one field effect transistor is adversely affected by another field effect transistor adjacent thereto. More specifically, as shown in a typical partial sectional view, Fig. 2, when a positive voltage is applied to a gate 13 of an adjacent field effect transistor while a negative voltage is applied to a source-drain 12 of one field effect transistor, a non-negligible current comes to flow between said one field effect transistor and the adjacent transistor. Hereinafter this current will be referred to as a leakage current. Such a phenomenon is usually termed side-gate effect or back-gate effect. Concretely, a leakage current flows from a portion 13B of the gate extension 13A of the adjacent field effect transistor via the region 21 and an area under the element isolating region 20 to the source-drain 12 of said one field effect transistor. In Fig. 6, a dotted line represents exemplary currcnt-to-voltage characteristic between the source-drain 12 of said one field effect transistor and the gate 13 of the adjacent field effect transistor in an example where the element isolating region 20 is spaced apart by 0.3 µm from the channel 11 (i.e., where the region 21 has a width of 0.3 µm). In Fig. 6, the ordinate signifies the current I (unit: nanoampere) flowing between the source-drain 12 of one field effect transistor and the gate 13 of the adjacent field effect transistor; while the abscissa signifies the voltage difference V (unit: volt) obtained by subtracting the voltage, which is applied to the source-drain 12 of the adjacent field effect transistor, from the voltage applied to the gate 13 of said one field effect transistor. Thus, when a leakage current flows between one field effect transistor and the adjacent field effect transistor, the performance characteristics thereof are adversely affected. It is therefore necessary to minimize such leakage current. In the case where a diode is adjacent to a field effect transistor, a leakage current flows from a portion 13B of a gate extension 13A of the field effect transistor via a region 21 and an area under an element isolating region 20 to an n-type conductive region 23 of the adjacent diode (as shown in a typical diagram, Fig. 3A). Denoted by reference numeral 24 in Fig. 3A is a p-type conductive region. In another case, where a resistance element composed of an n-type conductive region 25 is adjacent to a field effect transistor, a leakage current flows from a portion 13B of a gate extension 13A of the field effect transistor via a region 21 and an area under an element isolating region 20 to an n-type conductive region 25 of the adjacent resistance element (as shown in a typical diagram, Fig. 3B). Generation of such leakage current is not desired either in view of the operation stability of the junction field effect transistor. In EP-A-158752 (corresponding to the preamble of claim 1) a GaAs JFET with a self-aligned p-type gate region is disclosed. The Japanese patent application published under no. 2 119 265 (and summarised in the journal Patent Abstracts of Japan, vol. 14, no. 346 (E-0956) July 26, 1990) describes a MESFET in which a ring-shaped isolation region is formed surrounding the active region. An elongate gate electrode extends across and beyond the active region and terminal portions thereof overshoot the outer periphery of the isolation region, thus being in contact with the underlying substrate. SUMMARY OF THE INVENTION It is an object of the present invention to provide a junction field effect transistor formed on a semi-insulative compound semiconductor substrate, and also a method of producing such a transistor, wherein generation of a leakage current and side-gate effect can be suppressed with a further advantage that harmful influence from any adjacent junction field effect transistor, diode or resistance element is minimized. In a junction field effect transistor formed in the surface of a semi-insulative compound semiconductor substrate and having a channel, a gate region and a source-drain, the object mentioned above can be attained by contriving an improvement where a gate extension protruding outward beyond the channel transversely thereto extends from the gate region, and an insulating layer is formed on the semi-insulative compound semiconductor substrate so as to prevent any part of the gate extension from being in contact with said substrate. In the junction field effect transistor of the present invention, there is embraced an aspect where the insulating layer overlaps at least the channel. The semi-insulative compound semiconductor substrate may be composed of GaAs, and boron may be included as an impurity in the insulating layer. A method of producing the junction field effect transistor of the present invention for attaining the above object comprises the steps of: (a) forming a channel and a source-drain on a semi-insulative compound semiconductor substrate; (b) forming a gate region on the channel together with a gate extension which extends from the gate and protrudes outward beyond the channel transversely thereto; and (c) forming an insulating layer in the surface of the semi-insulative compound semiconductor substrate adjacently to both of the channel and the source-drain in such a manner that there is no gap between the insulating layer and at least the channel and no part of the gate extension is in contact with the substrate. In the method of producing the junction field effect transistor of the present invention, the step (c) mentioned above may embrace an aspect where the insulating layer is formed adjacently to both of the channel and the source-drain in such a manner as to overlap at least the channel. The semi-insulative compound semiconductor substrate may be composed of GaAs, and the insulating layer may be formed by implanting boron ions. In the present invention, the gate extension protrudes outward beyond the channel transversely thereto, and the insulating layer is formed in the surface of the semi-insulative compound semiconductor substrate under the gate extension. Therefore a flow of the leakage current from the gate extension to an adjacent junction field effect transistor, diode or resistance element is prevented by the insulating layer, hence effectively suppressing generation of the side-gate effect. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1C are a typical plan view and typical partial sectional views of a substrate and so forth for explaining a method of producing a conventional n-type junction field effect transistor according to the related art; Fig. 2 is a typical partial sectional view for explaining the problems observed in the conventional n-type junction field effect transistor; Figs. 3A and 3B are diagrams for explaining the problems observed in a combination of a conventional junction field effect transistor and a diode, and also in a combination of a conventional junction field effect transistor and a resistance element; Figs. 4A to 4C are a typical plan view and typical partial sectional views of a junction field effect transistor according to a first embodiment of the present invention; Figs. 5A to 5C are typical partial sectional views of a semi-insulative compound semiconductor substrate and so forth for explaining an example method for production of the junction field effect transistor of the first embodiment; Fig. 6 graphically shows exemplary current-to-voltage characteristics of the junction field effect transistor in the first embodiment of the invention and of the conventional transistor of the related art, respectively; Figs. 7A and 7B are a typical plan view and a typical sectional view of a junction field effect transistor according to a second embodiment of the invention; Figs. 8A and 8B are typical partial sectional views showing structures of third and fourth embodiments of the present invention; Figs. 9A and 9B are a typical plan view and typical partial sectional views of a fifth embodiment of the invention which is a modification of the first embodiment; and Fig. 10 is a typical plan view of a sixth embodiment- of the invention which is a modification of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter some preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Fig. 4A is a typical plan view of a junction field effect transistor in a first embodiment of the present invention. And Figs. 4B and 4C are typical partial sectional views taken along lines B-B and C-C in Fig. 4A showing the junction field effect transistor of the first embodiment. The junction field effect transistor of the first embodiment is formed on an n-type or p-type semi-insulative compound semiconductor substrate 40. This transistor has a channel 41 composed of an n + -type conductive region, a gate 43 of a p ++ -type conductive region and a source-drain 42 of an n ++ -type conductive region. A gate extension 43A protruding outward beyond the channel 41 extends transversely thereto from the gate 43. Practically, however, the gate extension 43A has no function as a gate. And an insulating layer 44 is formed in the surface of the semi-insulative compound semiconductor substrate 40 under the gate extension 43A which is a protruding portion of the gate. This insulating layer 44 functions also as an element isolating region. In the junction field effect transistor of the present invention, no gap is formed, differing from the conventional junction field effect transistor, between the insulating layer 44, which corresponds to an element isolating region, and each of the channel 41 and the source-drain 42. Consequently, it becomes possible to prevent a flow of any great leakage current from the gate extension 43A of the gate 43 to the source-drain of an adjacent junction field effect transistor. A method of producing the junction field effect transistor of the first embodiment will be described below with reference to Fig. 5, which is a typical partial sectional view taken in the direction along line C-C in Fig. 4A. [Step 100] First a channel 41 and a source-drain 42 are formed on a semi-insulative compound semiconductor substrate 40 composed of GaAs. More specifically, a source-drain 42 of an n ++ -type conductive region in the field effect transistor is formed by implanting silicon ions into a semi-insulative compound semiconductor substrate 40 of GaAs on which a photo mask 50 is formed (as shown in Fig. 5A). Subsequently the photo mask 50 is removed and, after another photo mask 51 is formed, silicon ions are again implanted into the semi-insulative compound semiconductor substrate 40, whereby the channel 41 of an n + -type conductive region is formed (as shown in Fig. 5B). Thereafter the photo mask 51 is removed, and then an annealing process is executed to activate the ion-implanted silicon which is an n-type impurity. [Step 110] Subsequently a gate 43 is formed on the channel 41 together with a gate extension 43A which extends from the gate and protrudes outward beyond the channel 41 transversely thereto. For this purpose, first an insulating film (not shown) composed of SiN (silicon nitride) for example is formed by CVD or the like on the entire surface including the channel 41 and the source-drain 42, and then an opening is formed in the insulating film above the channel 41 by the techniques of photolithography and etching. Thereafter a gate 43 of a p ++ -type conductive region is formed by diffusing zinc into the channel 41 through a heating process while causing a gas, which includes diethyl zinc (DEZ), to flow into the opening formed in the insulating film (as shown in Fig. 5C). [Step 120] Next an insulating layer 44 corresponding to an element isolating region is formed for the purpose of ensuring required electric insulation between mutually adjacent field effect transistors. The insulating layer 44 can be formed by first providing a photo mask which covers both of the channel 41 and the source-drain 42, and then implanting boron ions into a region of the semi-insulative compound semiconductor substrate 40 where neither the channel 41 nor the source-drain 42 is existent. When producing a junction field effect transistor according to the first embodiment, the insulating layer 44 is formed in the surface of the semi-insulative compound semiconductor substrate 40 adjacently to the channel 41 and the source-drain in such a manner that no gap is formed between the insulating layer 44 and each of the channel 41 and the source-drain 42. Formation of such insulating layer 44 is dependent much on enhancement of the photo-mask positioning precision in the mass production line of semiconductor devices. The junction field effect transistor of Fig. 4 can thus be produced. [Step 130] Thereafter an insulating film composed of SiO 2 for example is formed by CVD or the like on the entire surface including the gate 43 and the source-drain 42, and an opening is formed in the insulating film above the gate and the source-drain by the techniques of photolithography and etching. Subsequently a metallic wiring material layer is deposited by sputtering or the like on the insulating film inclusive of such opening, and then wires are formed by patterning the metallic wiring material layer on the insulating film. As for suitable metallic wiring materials, Pt/Au may be used for the gate, and Au-Ge/Ni for the source-drain. In Fig. 6, a solid line represents an exemplary current-to-voltage characteristic obtained by applying a positive voltage to the gate 43 of one junction field effect transistor, produced as mentioned above, while applying a negative voltage to the source-drain 42 of an adjacent junction field effect transistor. It is obvious therefrom that, in comparison with the other current-to-voltage characteristic represented by a dotted line and obtained in the conventional junction field effect transistor known heretofore, the leakage current is reduced remarkably in the junction field effect transistor of the first embodiment. Hereinafter a second embodiment of the present invention will be described. In the first embodiment mentioned above, an insulating layer 44 is formed in the surface of a semi-insulative compound semiconductor substrate 40 adjacently to a channel 41 and a source-drain 42 in such a manner that no gap is existent between the insulating layer 44 and each of the channel 41 and the source-drain 42. As contrasted therewith, in the second embodiment shown in a typical plan view, Fig. 7A, and a typical partial sectional view, Fig. 7B, a portion 44A of an insulating layer 44 overlaps a channel 41 and a source-drain 42. With the exception of this- point, the junction field effect transistor of the second embodiment is structurally the same as that of the first embodiment. In the junction field effect transistor of the second embodiment, the channel width and so forth are designed with advance estimation of the overlap (invasion) of the insulating layer 44. In a method of producing the junction field effect transistor of the second embodiment, an insulating layer 44 is formed adjacently to a channel 41 and a source-drain 42, at [step 120] relative to the first embodiment, in such a manner as to partially overlap the channel 41 and the source-drain 42. With the exception of this point, the junction field effect transistor of the second embodiment can be produced by the same method as that described above for production of the junction field effect transistor of the first embodiment. A third embodiment of the present invention will be described below. The third embodiment shown in a typical partial sectional view of Fig. 8A represents an example where the junction field effect transistor explained with regard to the first embodiment and a diode are formed adjacently to each other. The diode consists of an n-type conductive region 60 and a p-type conductive region 61. Fundamentally, such diode can be formed simultaneously with the source-drain and the gate of the junction field effect transistor in the production process thereof. Next a fourth embodiment of the present invention will be described below. The fourth embodiment shown in a typical partial sectional view of Fig. 8B represents an example where the junction field effect transistor explained with regard to the first embodiment and a resistance element are formed adjacently to each other. The resistance element consists of an n-type conductive region 62. Fundamentally, such resistance element can be formed simultaneously with the source-drain of the junction field effect transistor in the production process thereof. Although the present invention has been described above with reference to some preferred embodiments, it is to be understood that the present invention is not limited thereto alone. At [step 120] relative to the first embodiment, the insulating layer 44 is formed in the surface of the semi-insulative compound semiconductor substrate 40 adjacently to the channel 41 and the source-drain 42 in such a manner that no gap is existent between the insulating layer 44 and each of the channel 41 and the source-drain 42. However, the process may be so modified, at [step 120], as to form the insulating layer 44 in the surface of the semi-insulative compound semiconductor substrate 40 adjacently to the channel 41 and the source-drain 42 in a manner that no gap is existent between the insulating layer 44 and at least the channel 41. Such an example is shown in a typical plan view of Fig. 9A and a typical partial sectional view of Fig. 9B. In the example of Fig. 9, the insulating layer 44 is formed in the surface of the semi-insulative compound semiconductor substrate adjacently to the channel 41 and the source-drain 42 in a manner that no gap is existent between the insulating layer 44 and a portion of the channel 41. In other words, the requisite is satisfied if, as illustrated in Fig. 4B, the insulating layer 44 is formed exactly in the surface of the semi-insulative compound semiconductor substrate under the gate extension 43A which is a protruding portion of the gate. Reference numeral 45 denotes a gap formed between the other portion of the channel 41 and the insulating layer 44, and also between the source-drain 42 and the insulating layer 44. Fig. 9B is a typical partial sectional view taken along a line B-B in Fig. 9A. Similarly in the second embodiment also, the requisite is satisfied if the insulating layer 44 exactly overlaps at least the channel 41, as shown in a typical plan view of Fig. 10. In this example, the insulating layer 44 is formed in the surface of the semi-insulative compound semiconductor substrate adjacently to the channel 41 and the source-drain 42 in a manner that the insulating layer 44 overlaps the channel 41 and a portion of the source drain 42. Reference numeral 45 denotes a gap formed between the other portion of the source-drain 42 and the insulating layer 44. In each of the above embodiments, Si ions implanted to form a source-drain of an n ++ -type conductive region may be replaced with Se ions. Further, diffusion of Zn for forming a gate of a p ++ -type conductive region may be replaced with diffusion of C, Mg or Be, or with implantation of ions thereof. The insulating layer 44 can be formed by implantation of oxygen or hydrogen ions instead of implanting boron ions. Although an n-type junction field effect transistor has been described above as an example in each of the embodiments, the junction field effect transistor of the present invention may be a p-type one as well. In the junction field effect transistor of the present invention, remarkable enhancement is achievable in the electric insulation and voltage-withstanding characteristics between a gate of a p-type conductive region in this transistor and a source-drain of an n-type conductive region in an adjacent junction field effect transistor or an adjacent diode or resistance element. Therefore, the side-gate effect between this junction field effect transistor and the adjacent one is reduced to consequently decrease the leakage current flowing between the junction field effect transistor and the diode or the resistance element. As a result, it becomes possible to stabilize the operation of the junction field effect transistor with another advantage of raising the integration density of junction field effect transistors.

Claims: A junction field effect transistor comprising: a semi-insulative compound semiconductor substrate (40); a channel (41); a source-drain (42); a gate region (43); characterised in that: the gate region has a gate extension (43A) which extends from said gate region and protrudes outward beyond said channel (41) transvcrsely thereto; and an insulating region (44) is formed in the surface of said semi-insulative compound semiconductor substrate (40) so that no part of said gate extension (43A) is in contact with said substrate (40). The junction field effect transistor according to claim 1, wherein said insulating region (44) is formed to overlap at least a part of the channel (41). The junction field effect transistor according to claim 1 or 2, wherein said semi-insulative compound semiconductor substrate (40) is composed of GaAs, and said insulating region (44) includes boron as an impurity. The junction field effect transistor according to claim 1 or 2, wherein said insulating region (44) is so formed as to surround said source-drain (42) and channel (41) in a manner that no gap exists between the insulating region (44) and at least a portion of the channel (41). The junction field effect transistor according to claim 4, wherein said insulating region (44) is so formed that a gap exists between said insulating region (44) and the source-drain (42). The junction field effect transistor according to claim 5, wherein said insulating region (44) has an inner periphery surrounding said source-drain (42) and channel (41), the distance separating portions of said inner periphery which oppose each other across the source or drain being greater than the distance separating portions of said inner periphery which oppose each other across the channel (41). The junction field effect transistor according to claim 1 or 2, wherein said insulating region (44) is so formed as to surround said source-drain (42) and channel (41) in a manner that no gap exists between the insulating region (44) and each of the source-drain (42) and channel (41). A method of producing a junction field effect transistor, comprising the steps of: forming a channel (41) and a source-drain (42) in the surface of a semi-insulative compound semiconductor substrate (40); forming a gate region (43) on said channel (41) together with a gate extension (43A) which extends from said gate and protrudes outward beyond said channel (41) transversely thereto; and forming an insulating region (44) in the surface of said semi-insulative compound semiconductor substrate (40) adjacently to said channel (41) and said source-drain (42) in such a manner that no gap is existent between said insulating layer (44) and at least said channel (41) and no part of the gate extension (43A) is in contact with the substrate (40). The method of producing a junction field effect transistor according to claim 8, wherein the step of forming said insulating region (44) comprises formation thereof adjacently to said channel (41) and said source-drain (42) in such a manner as to overlap at least the previously-formed channel (41). The method of producing a junction field effect transistor according to claim 8 or 9, wherein said semi-insulative compound semiconductor substrate (40) is composed of GaAs, and said insulating layer (44) is formed by implanting boron ions. The method of producing a junction field effect transistor according to claim 8, wherein a diode (60,61) is formed at the time of forming said gate region (43) simultaneously with the step of forming said source-drain (42). The method of producing a junction field effect transistor according to claim 8, wherein a resistance element (62) is formed at the time of forming said source-drain (42).

Inventors: KAWASAKI HIDETOSHI, TAKANO CHIAKI, WADA MASARU, KAWASAKI, HIDETOSHI, TAKANO, CHIAKI, WADA, MASARU, KAWASAKI, HIDETOSHI, C/O SONY CORPORATION, TAKANO, CHIAKI, C/O SONY CORPORATION, WADA, MASARU, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1995
Main classification: H01L29
IPC codes: H01L21, H01L29, H01L27