Modulated slope signal generation circuit, particularly for latch data sensing arrangements

Abstract: A modulated slope signal generation circuit, particularly for latch data sensing arrangements, having the particularity of comprising: a line (V mod ) for the equalization of a latch arrangement; a branch (13, 14) for following the current of a base cell applied to one of the loads of the latch arrangement; a branch (6, 7) for the slow discharge of the equalization line; a branch (11) for the fast discharge of the equalization line; a branch (2, 3) for evaluating the ratio between a current (I CELLA ) that is a function of the conductivity of the cell and a reference current (I REF ) that is present on the evaluation branch; and a control signal (PC n ) that is sent to the slow discharge branch (6, 7) and to the current follower branch (13, 14); the slow discharge branch (6, 7) being adapted to control a first slope of the signal of the equalization line; the evaluation branch being adapted to control the modulation of the signal of the equalization line, determining its slope change point; the fast discharge branch being adapted to determine a second slope of the signal of the equalization line after the first slope; the first slope of the equalization signal corresponding to a step for the evaluation of a datum and the second slope corresponding to a step for the capture of the datum in the cell.

Description: The present invention relates to a modulated slope signal generation circuit, particularly adapted for applications in circuits using latch sensing arrangements as known from EP-A-0 205 294 or DE-A-3 710 821. It is important to achieve two basic goals in circuits using latch arrangements for data sensing, that is to say, for capturing and storing data. Consider figure 1, which is a diagram of a latch sensing arrangement with two nodes M and R. The result to be obtained, starting from a substantial equalization of the two nodes M and R of the latch, is the generation, with an appropriate timing, of a small signal that can be sensed reliably and stored correctly. Figure 1a plots, as a function of time, the voltage of the signal to be obtained on the two branches of the latch that correspond to the nodes M and R. This chart shows that the signal created after the equalization step, which corresponds to the straight portion of the curve, is a weak signal, and that the divergence that is obtained, which corresponds to the different voltage levels on the two branches, is initially small and then increases. In other words, the voltage level produced on each one of the two branches must be different enough to determine a binary representation that defines a datum. It is therefore necessary to create a signal having an initially low level but which can be sensed and stored correctly, and then reaches a high voltage level, which corresponds to a logic 1, on one branch, and a low voltage level, which corresponds to a logic zero, on the other branch. The drawbacks observed with latch arrangements of this kind relate to the choice of the timings with which data reading and storage are to be performed. Since two different currents are produced in the two branches of the latch, which are initially intentionally shorted, and since this difference is highly variable because there are weak signals and strong signals and there are matrix cells, which constitute the load of the latch, having high conductivity and low conductivity, it is not possible to be certain of the reading. Accordingly, it is necessary to read or "capture" the datum in a controlled and therefore slow manner, but not too slowly, in order to avoid increasing the reading times excessively. If instead the datum is captured too quickly, there is the drawback that a capacitive effect, known as Miller effect, is produced and is superimposed on the datum, surpassing it in terms of intensity and thus preventing its reliable capture. As an alternative, it may also happen that if the datum capture times become too fast, not enough time is left to allow the currents present in the circuit to set the nodes adequately and therefore the latch arrangement does not operate correctly. In all these cases, the result is an incorrect reading of the datum, its loss, or an inadequate utilization, in terms of time, of a latch sensing arrangement. The principal aim of the present invention is therefore to provide a modulated slope signal generation circuit to control data capture in a latch data sensing arrangement. Within the scope of this aim, an object of the present invention is to provide a circuit for generating, with an appropriate timing, a modulated slope signal that can be sensed reliably and stored correctly. Another object of the present invention is to provide a modulated slope signal generation circuit allowing to identify the instant in which the capture of a datum must be completed slowly but progressively. Another object of the present invention is to provide a modulated slope signal generation circuit allowing to reduce the capacitive effects associated with the equalization line during the generation of said signal. Another object of the present invention is to provide a modulated slope signal generation circuit in which slope change occurs in reliably determined conditions and in the shortest possible time. Another object of the present invention is to provide a modulated slope signal generation circuit in which the value of the modulated slope is linked to the value of the current of the cells. Another object of the present invention is to provide a modulated slope signal generation circuit the timing whereof is a function of the conductivity of the base cell of a cell matrix. Another object of the present invention is to provide a modulated slope signal generation circuit that is capable of controlling the duration of the sloping part of the signal. Another object of the present invention is to provide a device that is highly reliable, relatively easy to manufacture, and at competitive costs. This aim and these objects are achieved by a modulated slope signal generation circuit according to claim 1. Further characteristics and advantages of the invention will become apparent from a preferred but not exclusive embodiment of the device according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a diagram of a typical latch arrangement; figure 1a is a plot of the signal present in the latch arrangement of figure 1; figure 2 is a diagram of the circuit according to the invention, applied to a latch sensing arrangement; and figure 3 is a plot of the voltages present at the various nodes of the circuit shown in figure 2. With reference to figures 2 and 3, the circuit according to the invention comprises a line for the equalization of the loads of a latch circuit. A signal V mod is created on the equalization line and supplies the base terminal of a first equalization transistor 1 the drain terminal whereof is connected to V DD . The latch arrangement of figure 2 is similar to that of figure 1, and in particular the transistor on the right branch of the latch arrangement of figure 1 corresponds to a second transistor, designated by the reference numeral 2 in figure 2, whereas the block designated by the letter A in figure 1 corresponds to the first equalization transistor, designated by the reference numeral 1 in figure 2. Advantageously, the transistor 1 is of the native type, whereas the transistor 2 is of the P-channel type. The transistor provided on the left branch of the latch of figure 1 is not present, since said transistor can be seen as being always off and the branch can therefore be seen as being connected to the supply voltage V DD . In summary, in the equalization transistor 1 the drain terminal is connected to the supply voltage V DD , the source terminal is connected to the gate terminal of the transistor 2, and the gate terminal is connected to a latch load equalization line, where a signal V mod is present. In the transistor 2, the drain terminal is also connected to the supply voltage V DD and the source terminal is connected to the drain terminal of a third current ratio evaluation transistor 3 that is part of a line for the evaluation of a current ratio. The gate terminal of the transistor 3 is also connected to the source terminal of the equalization transistor 1. The transistor 3 is conveniently of the N-channel type. The current ratio evaluation line comprising the transistor 3 is supplied by a first voltage source, which is external to the circuit, is not shown, and is capable of supplying a voltage stable enough to set a reference current on the current ratio evaluation line. Said reference current, which is constant, is a function of the conductivity of a generic specimen matrix cell. The current ratio evaluation line has the purpose of evaluating the ratio between the current of a cell that is identical to the matrix cell and the reference current. One or more mirroring transistors 5, generally designated by the reference numeral 4 in figure 2, are associated with the current ratio evaluation line; the source terminal of each one of said transistors 5 is connected to the ground (GND), and each one of said transistors 5 is adapted to determine the profile of the curve of the equalization signal V mod . The current set by the reference voltage V ref is therefore a function of the conductivity of the cell, which varies according to the number of transistors 5 composing it. Hereinafter, the voltage generated by the first voltage source is designated by V ref and "k" designates the number of transistors 5. The circuit according to the invention furthermore comprises a branch for the constant discharge of the equalization line V mod that comprises a fourth pre-charge transistor 6 of the P-channel type, in which the drain terminal is connected to the supply voltage V DD , the gate terminal receives a control signal PC n originating outside the circuit, and the source terminal is connected to the drain terminal of a fifth pre-charge transistor 7 advantageously of the N-channel type. The gate terminal of the fifth transistor 7 also receives the control signal PC n in input. A second voltage source, lying outside the circuit and not shown, generates a voltage that is a function of the conductivity of a generic reference cell 8 constituted by one or more transistors, the number whereof is "m". The source terminal of the transistor 7 is connected to the cell 8, which is in turn connected to the ground by means of the source terminals of the transistors 5 that compose it. The discharge of the slow discharge branch is a function of the conductivity of the cell, that is to say, of the number "m" of transistors 5. A capacitor 10 is parallel-connected to the slow discharge branch and is connected to the ground. The circuit according to the invention furthermore comprises a fast discharge branch parallel-connected to the capacitor 10 and constituted by a sixth transistor 11 in which the gate terminal is connected to the current ratio evaluation branch. The drain terminal of the transistor 11 is connected to the equalization line V mod and its source terminal is connected to the ground. The circuit according to the invention furthermore comprises a branch that follows the current of a generic matrix cell 12 applied to one of the two loads of the latch circuit and constituted by one or more transistors, whose number is "n" and the source terminals whereof are connected to the ground. Said current follower branch comprises a seventh transistor 13 advantageously of the N-channel type and an eighth transistor 14 of the P-channel type. The source terminal of the transistor 14 is connected to the drain terminal of the transistor 13, whereas the gate terminal of the transistor 14 is connected to the gate terminal of the transistor 13, which in turn receives the signal PC n . With reference to figures 2 and 3, the operation of the circuit according to the invention is as follows. In the initial inactive condition, the signal PC n is at the high level (V DD ), the equalization line V mod is at the high level, the node 15 on which the voltage V set is present is at the low level, the node 16 on which the voltage V dis is present is at the high level, the voltage set by the second voltage source is high, and the reference voltage generated by the first source is low. Upon activation, which is termed standby or pre-charge step, PC n switches to zero and the slow discharge branch, the current ratio branch, and the voltage follower branch are switched off. At this time, the equalization line V mod is high, the voltage V dis on the node 16 is low (GND), the voltage V ref generated by the first voltage source is constant, and the voltage V generated by the second voltage source is a function of the conductivity of the cell. The voltage on the node 15 of the voltage follower branch is V DD , since the transistor 2 switches off. The capacitor 10 is charged during this pre-charge step. At the end of the pre-charge step, the signal PC n switches back to the high level (V DD ) and therefore the slow discharge branch, the current ratio branch, and the voltage follower branch are activated; the current ratio branch, however, is activated later than the other two branches. The slow discharge branch discharges the capacitor 10, producing the first part of the slope of V mod , that is to say, the less steep part. The capacitor 10 does not discharge quickly because a fast transistor is not provided on the slow discharge branch. The line V mod therefore discharges slowly, with a constant discharge current I dis ; at the same time, the conductivity of the transistor 2 decreases. The slope of the line V mod is determined by the "m" transistors 5, which conduct a current that is a function of the conductivity of the base cell. At the same time, a cell current is generated on the voltage follower branch, said current being supplied by the set of transistors 4. When the transistor 13 reaches 1, the transistor 14 switches off and the node 15, which is V set , follows from below the dynamics of V mod , that is to say, V set = V mod -threshold voltage V Tnat of the transistor 1. Therefore V set modulates the conductivity of the transistor 2, which in turn controls V dis . The transistor 2 approaches its threshold, but the node 16, which is V dis , remains low because the transistor 2 is unable to deliver the set reference current I ref . As V mod decreases, the conductivity of the transistor 2 increases, and so does V dis , and increasingly approaches the current value of I ref . When the conductivity of the transistor 2 reaches a current level that is set with the ratio between the cell current and the reference current, V dis gradually increases until it reaches the activation threshold of the transistor 11, which is 1 volt. The transistor 11 is therefore activated exactly when the ratio between the cell current and the reference current is greater than 1. In this manner, the voltage V dis drives the switching-on of the transistor 11, which is responsible for the fast discharge of V mod and therefore for the steeper slope part of V mod . At this point, therefore, the progression become very fast: V mod drops to the ground value, V set quickly degrades to the ground, and V dis rises quickly to V DD , and the initial inactive condition is regained. In this manner, the signal V mod has a behavior including two slopes: a less steep one, which allows to evaluate the datum with the appropriate caution, and a much steeper slope, which occurs at the end of the reliable evaluation, to capture the datum and store it. It should be noted that the second slope, that is to say, the steeper one of V mod , is triggered only when the equalization signal V mod , by virtue of its slow decrease, has reduced the equalization action on the latch to the point that the current produced on the transistor 2 is greater than the reference current set externally to the circuit by means of the first voltage source. Therefore, switching to the steeply sloping part can be linked to a reference current, which in turn is a function of the conductivity of the cell. It is therefore evident that if a cell is highly conductive, the cell current is high and therefore the ratio between the cell current and the reference current reaches and exceeds 1 much faster than would occur if the cell were scarcely conductive and therefore the cell current were small. In this regard, the operating context in which the cell is used, that is to say, the voltage values used, are also important. This effect is clearly visible in the chart of figure 3, where the dashed lines indicate the variations that the curves of V set and V mod assume in case of a large number of transistors 5 in the cell 8, that is to say, if "m" is large and "n" is also large. Therefore, the slope of V mod is controlled by means of "m" and the separation of V set from V mod is instead controlled by means of "n"; in practice, one determines the instant when triggering must occur, that is to say, when the quick change in slope after the datum evaluation step must occur. In practice it has been observed that the circuit according to the invention fully achieves the intended aim and objects, since it allows to pass very gradually from the equalization (inactive) step to the evaluation step, providing maximum circuit sensitivity so that the datum is sensed reliably. Furthermore, the capacitive noise (Miller effect) associated with the switching of the equalization line during the creation of the signal V mod is reduced. Another advantage of the circuit according to the invention is that it is possible to drastically reduce the datum evaluation time, allowing faster capture. Transition from the slow step (shallow slope) to the fast step (steep slope) is achieved by means of a circuit that allows to quantize the signal produced therein and to change the slope in certain datum acquisition conditions and, at the same time, in the shortest possible time interval. The timing for the creation of the signal V mod thus becomes dependent on the conductivity of a given base cell, linking the operating dynamics to the actual geometric features of the cell and to the voltages being used. The device thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept. For example, the signal V mod obtained as described above can be used to directly drive a latch amplifier. Finally, all the details may be replaced with other technically equivalent elements. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and to the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: Modulated slope signal generation circuit, particularly for latch data sensing arrangements, comprising: a line (V mod ) for carrying said modulated slope signal and for the equalization of a latch arrangement (1, 2); a branch for following (14, 15, 13, 12) the current of a base memory cell applied to one of the loads of said latch arrangement (1, 2); a branch for the slow discharge (7, 8) of said equalization line; a branch for the fast discharge (11) of said equalization line; a branch for evaluating the ratio (2, 16, 3, 4) between a current that is a function of the conductivity of said base memory cell and a reference current that is present on said evaluation branch (2, 16, 3, 4); and a control signal (PC n ) that is sent to said slow discharge branch (7, 8) and to said current follower branch (14, 15, 13, 12); said slow discharge branch (7, 8) being adapted to control a first slope of the signal of said equalization line (V mod ); said evaluation branch (2, 16, 3, 4) being adapted to control the modulation of the signal of said equalization line (V mod ), determining its slope change point; said fast discharge branch (11) being controlled by said evaluation branch (14, 15, 13, 12) to determine a second slope of the signal of said equalization line (V mod ) after said first slope; said first slope of the equalization signal corresponding to a step for the evaluation of a datum and said second slope corresponding to a step for the capture of the datum in said cell. Circuit according to claim 1, characterized in that one or more mirroring transistors (4; 5) are connected to said current ratio evaluation branch (2, 16, 3, 4), said transistors being supplied by a first voltage source (V REF ) adapted to set a constant reference current. Circuit according to claim 1, characterized in that one or more mirroring transistors (8; 5) are connected to said slow discharge branch (7, 8) of said equalization line (V mod ) and are supplied by a second voltage source (V) adapted to set a current that is a function of the conductivity of said cell, the slope of the signal of said equalization line (V mod ) being determined by the number (m) of said transistors. Circuit according to claim 3, characterized in that one or more mirroring transistors (12; 5) are connected to said voltage follower branch (14, 15, 13, 12) and are supplied by said second voltage source (V), the number (n) of said transistors determining the ability of the voltage follower branch to follow the current of said cell. Circuit according to claim 1, characterized in that said equalization line (V mod ) supplies the gate terminal of a first transistor (1), the drain terminal of said first transistor being connected to the supply voltage. Circuit according to claim 2, characterized in that said current ratio evaluation branch (2, 16, 3, 4) comprises a second (2) and a third (3) transistors, the source terminal of said second transistor (2) being connected to the drain terminal of said third transistor (3), the drain terminal of said second transistor (2) being connected to the supply voltage, and the source terminal of said third transistor (3) being connected to the drain terminals of said one or more mirroring transistors (4; 5). Circuit according to claim 6, characterized in that said second transistor (2) is of a first polarity and said third transistor (3) is of a second polarity. Circuit according to claim 3, characterized in that said slow discharge branch (7, 8) comprises a fourth (6) and a fifth (7) transistors, the source terminal of said fourth (6) transistor being connected to the drain terminal of said fifth transistor (7), the drain terminal of said fourth transistor (6) being connected to the supply voltage, the gate terminals of said fourth (6) and fifth (7) transistors being supplied by said control signal (PC n ), the source terminal of said fifth transistor (7) being connected to the drain terminals of said one or more mirroring transistors (8; 5). Circuit according to claim 8, characterized in that said fourth transistor (6) is of a first polarity and said fifth transistor (7) is of a second polarity. Circuit according to claim 1, characterized in that a capacitor (10) is parallel-connected to said slow discharge branch and is connected between said equalization line (V mod ) and the ground. Circuit according to claim 1, characterized in that said fast discharge branch comprises a sixth transistor (11) of a second polarity, in which the drain terminal is connected to said equalization line (V mod ), the source terminal is connected to the ground, and the gate terminal is connected to the connection (16) between the source terminal of a second transistor (2) and the drain terminal of a third transistor (3). Circuit according to claim 4, characterized in that said voltage follower branch comprises a seventh (13) and an eighth transistors (14), the drain terminal of said eighth transistor (14) being connected to the supply voltage, the gate terminal and the source terminal of said eighth (14) transistor being connected respectively to the gate terminal and to the drain terminal of said seventh transistor (13), the source terminal of said seventh transistor (13) being connected to the drain terminals of said one or more mirroring transistors (12; 5), and the gate terminal of said seventh transistor (13) being furthermore connected to said control signal (PC n ). Circuit according to claim 12, characterized in that said eighth transistor (14) is of a first polarity and said seventh transistor (13) is of a second polarity. Circuit according to claim 4, characterized in that the respective source terminals of said one or more mirroring transistors (12; 5) are connected to the ground.

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: G11C11
IPC codes: G11C11