Transistor current generator stage for integrated analog circuits

Abstract: The present invention relates to a current generator stage for integrated analog circuits of the type comprising a current source (2) inserted between a first reference supply voltage (Vdd) and a second fixed reference voltage (GND). The stage 1 comprises also at least one current mirror circuit (5) operationally connected to the current source (2) to generate at least one output current and a bias circuit (10) operationally connected to the current source (2) to supply to this source a bias voltage. The stage 1 is also characterized in that the bias circuit (10) comprises an energy storage circuit (11) which in a first circuit configuration is a combination of a first reactance (X1) and a second reactance (X2) when the current source (2) is in a first operational mode. The energy storage circuit (11) is in a second circuit configuration to supply to the current source (2) a predetermined bias voltage when said current source (2) is in a second operating mode.

Description: The present invention relates to current generator stages with transistors particularly suited to being used in integrated analog circuits either as biasing elements or as load devices in the amplifier stages. As known, current generator stages used in integrated electronic circuits are implemented with circuit structures of which an example is shown in FIG. 1. With reference to this FIG. the stage 1 current generator comprises a current generator 2 provided essentially by a first circuit branch 3 and a second circuit branch 4 both inserted between a first reference supply voltage Vdd and a second fixed reference voltage and more in particular a ground GND. More specifically the first circuit branch 3 comprises a fixed reference current Ir and a first bipolar transistor Q1 and a first resistor R1 connected in series together. The second circuit branch 4 comprises the series between a second bipolar transistor Q2 and a second resistor R2. The two circuit branches 3 and 4 are connected together by means of a first circuit node A and a second circuit node B. The first circuit node A is inserted between the fixed reference current Ir and the first transistor Q1 while the second circuit node B is inserted between the second transistor Q2 and the second resistor R2. The current generator stage 1 also comprises a current mirror circuit 5 operationally connected to the current generator 2 by means of the second circuit node B. This current mirror circuit 5 is provided by a multiplicity of output branches (6,7,8,...) each of which is capable of generating an output current (I1out,I2out,I3out,...) to drive circuit structures not shown in FIG. 1 and incorporated in a user stage 9. Each output branch (6,7,8,...) comprises the series between a bipolar transistor (Q3,Q4,Q5,...) and a resistor (R3,R4,R5,...). The current generator stage 1 also comprises a bias circuit 10 operationally connected to the current generator 2 by means of the first circuit node A to supply to the above generator a bias voltage. More particularly the bias circuit 10 comprises a capacitor Ccomp inserted with a first and a second terminal between the first circuit node A and ground GND. The above mentioned capacitor Ccomp is also connected in parallel with a switch T1 driven by means of a control logic external to the stage 1 and not shown in FIG. 1. As concerns operation of the above mentioned circuit structure the power down phase of the stage 1 is relatively fast because it takes place by means of the discharge of the capacitor Ccomp to ground GND through the switch T1. Contrariwise the power up phase of the stage 1 is rather slow because the capacitor Ccomp has to be charged by means of the current Ir. The charge time τ on of the capacitor Ccomp is with good approximation: τ on ∼ V A *Ccomp/Ir which for some applications and in particular those at high frequency is not tolerable. Usually, to decrease this charge time a second circuit structure of which an example is shown in FIG. 2 is used. In this second circuit structure the bias circuit 10 is provided only by the capacitor Ccomp. From FIG. 2 it is also seen that the first output branch 6 and the second output branch 7 of the current mirror circuit 5 are separated by means of a first switch T1 and a second switch T2 with the latter connected in parallel with the output branch 7. As concerns operation of the circuit structure described above the power down phase of stage 1 takes place by opening the switch T1 and closing the switch T2. Contrariwise the power up phase of stage 1 takes place by closing the switch T1 and opening the switch T2. With this second structure there is reduction both of power down time and power up time of the current generator stage. However, the presence of a voltage drop ΔV on the switch T1 due to the intrinsic resistance Ron of this switch causes an error on the output currents (I1out,I2out,I3out,...). Consequently this second circuit structure is ineffective in all those applications which require high accuracy. The technical problem underlying the present invention is to provide a current generator stage for integrated analog circuits exhibiting significantly reduced power down and power up times. The technical problem is solved by a current generator stage for integrated analog circuits of the type indicated above and defined in the characterizing part of the annexed claims. The characteristics and advantages of the stage in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of non-limiting example with reference to the annexed drawings. In the drawings: FIG. 1 shows a circuit diagram of a current generator stage in accordance with the prior art, FIG. 2 shows another circuit diagram of a current generator stage in accordance with the prior art, FIG. 3 shows a circuit diagram of a current generator stage in accordance with the present invention, FIG. 4 shows a circuit embodiment of the diagram shown in FIG. 3, FIGS. 5 and 6 show respective charts with the same time base of electrical signals present in the current generator stage in accordance with the present invention. With reference to the FIGS. and in particular to FIG. 3 reference number 1 indicates as a whole and diagrammatically a current generator stage for integrated analog circuits provided in accordance with the present invention. The current generator stage 1 comprises a current generator 2 provided by means of a first circuit branch 3 and a second circuit branch 4. More specifically the first circuit branch 3 comprises a first bipolar transistor Q1 and a first resistor R1 connected in series together and inserted between a first circuit node A and a second fixed reference voltage and in particular a ground GND. The second circuit branch 4 comprises a second bipolar transistor Q2 and a second resistor R2 connected in series together and inserted between a first reference supply voltage Vdd and ground GND. The second circuit branch 4 is connected to the first circuit branch 3 by means of both the circuit node A and the circuit node B inserted between the second transistor Q2 and the second resistor R2. The current generator stage 1 also comprises a current mirror circuit 5 operationally connected to the current generator 2 by means of the second circuit node B. This current mirror circuit 5 is provided by a multiplicity of output branches (6,7,8,...) each of which is capable of generating an output current (I1out,I2out,I3out,...) to drive circuit structures not shown in FIG. 1 and included in a user stage 9. Each output branch (6,7,8,...) of the current mirror circuit 5 comprises the series between a bipolar transistor (Q3,Q4,Q5,...) and a resistor (R3,R4,R5,...). The current generator stage 1 also includes a bias circuit 10 operationally connected to the current generator 2 by means of the first circuit node A to supply to the above mentioned generator a bias voltage. This bias circuit comprises an energy storage circuit 11 provided by means of a first reactance X1 and a second reactance X2. The two reactances X1 and X2 are separated by means of a first switch T1 and a second switch T2 with the latter connected in parallel to the second reactance X2. Specifically the first reactance X1 is inserted between a fixed reference current Ir and ground GND while the second reactance X2 is inserted between the first circuit node A and ground GND. The first switch T1 is inserted between the first circuit node A and a third circuit node C for connection between the fixed reference current Ir and the first reactance X1. It is also noted that the two switches T1 and T2 are driven by means of a control logic external to the stage 1 and not shown in FIG. 3 and capable of generating a digital signal S1 of the type shown in FIG. 6. FIG. 4 also shows a first circuit embodiment of stage 1 in which the first reactance X1 and the second reactance X2 comprise respectively a first capacitor C1 and a second capacitor C2. There is now described operation of the stage 1 in accordance with the present invention with particular reference to an initial state in which the above mentioned stage is in operating condition. In the example considered the first reactance X1 and the second reactance X2 are provided respectively by means of the first capacitor C1 and second capacitor C2. In operating condition the first switch T1 is closed while the second switch T2 is open. In this condition the circuit nodes A and C are at the same voltage Vf while the drop in potential of the switch T1 is disregarded. The power down phase of stage 1 takes place by opening the switch T1 and closing the switch T2. In this phase the third circuit node C goes to the supply voltage Vdd while the first circuit node A is connected to ground GND. Consequently power down of the stage 1 is relatively fast because it depends only on the discharge to ground GND of the second capacitor C2 through the switch T2. In addition the power down phase of the stage 1 provided in accordance with the present invention is faster than that of the stage shown in FIG. 1 because the capacitor C2 is smaller than the capacitor Ccomp. The power up phase of the stage 1 takes place by closing the switch T1 and opening the switch T2. In this phase the charge accumulated on the first capacitor C1 during the power down phase is distributed between the same capacitor C1 and the second capacitor C2. Indeed, at the beginning of the power up phase on the first capacitor C1 there is an accumulated charge equal to: Q1= C1*Vdd. When the charge is distributed between the two capacitors C1 and C2 there is: Q1= (C1+C2)*V' where V' is the voltage present on the second capacitor C2 at the end of the charge transitory. This voltage V' is: V' = Vdd (C1/C1+C2). If V' is made equal to Vf the power up phase of stage 1 is very fast because the second capacitor C2 is charged by the first capacitor C1 through the first switch T1 which has a very low intrinsic resistance Ron. In conclusion, this charge distribution mechanism allows obtaining a considerably reduced power up time in comparison with the prior art while keeping circuit complexity low. In addition, the current generator stage in accordance with the present invention exhibits a significant reduction of dissipated power during the power down phase. Indeed, during this phase the current Ir is accumulated on the first capacitor C1 and not eliminated through the ground GND as takes place in the prior art. In addition, with reference to FIG. 7 showing the behavior in time of the current I(Vdd) absorbed by the supply during the power up phase, it is noted that for the proposed solution there is considerable improvement in power up time.

Claims: Current generator stage for integrated analog circuits of the type comprising: a current source (2) inserted between a first reference supply voltage (Vdd) and a second fixed reference voltage (GND), at least one current mirror circuit (5) operationally connected to the current source (2) to generate at least one output current, a bias circuit (10) operationally connected to the current source (2) to supply to said current source (2) a bias voltage, and characterized in that said bias circuit (10) comprises an energy storage circuit (11) which is a combination of a first reactance (X1) and a second reactance (X2) connected in parallel and separated by means of a first (T1), and a second switch (T2) connected in parallel with the second reactance (X2). Current generator stage in accordance with claim 1 and characterized in that the first (X1) and the second (X2) reactances comprise respectively a first capacitor (C1) and a second capacitor (C2). Current generator stage in accordance with claim 2 and characterized in that the first capacitor (C1) is inserted between a fixed reference current (Ir) and the second fixed reference voltage (GND).

Inventors: BRUCCOLTRI MELCHIORRE, COSENTINO GAETANO, DEMICHELI MARCO, PATTI GIUSEPPE, BRUCCOLTRI, MELCHIORRE, COSENTINO, GAETANO, DEMICHELI, MARCO, PATTI, GIUSEPPE
Applicants: CONS RIC MICROELETTRONICA, ST MICROELECTRONICS SRL, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO - CORIMME, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: G05F1
IPC codes: H03K17, H03F3, G05F3