Electrostatic discharge protection device for MOS integrated circuits

Abstract: The protection device forms an output buffer comprising a MOS transistor (41) formed on the substrate of the integrated circuit and connected between a circuit output pad (40) and a reference terminal (9) of the integrated circuit. A thyristor (54) formed on the substrate is connected between the output pad and the reference terminal. The control electrode (60) of this thyristor consists of a region of the substrate in such a way that the thyristor (54) can be triggerred by a current of charge carriers produced in the substrate by avalanche when a voltage rise occurs between the substrate and the drain (42) of the MOS transistor.

Description: The present invention relates to the protection of the outputs of integrated circuits against electrostatic discharges (ESD) which may appear when they are handled. The integrated circuits to be protected are MOS circuits, i.e. including a substrate made of doped semiconductor on which MOS (metal-oxide-semiconductor) transistors are formed. The invention applies especially to CMOS (complementary MOS) - type circuits. When the circuit is handled, electrostatic charges may appear on the circuit pads and risk causing a discharge (typically a few thousand volts for a few nanoseconds) capable of irreversibly damaging the circuit. The MOS transistor uses the effect of the electric field through a thin oxide to bring about a conversion into current of the voltage present on the gate. The growing integration of technology leads to this oxide thickness being reduced in order to obtain a better amplifying power for the transistor, to the detriment of its capacity to withstand high voltages. The inputs of CMOS integrated circuits generally consist of control gates of MOS transistors and exhibit both high impedance and great sensitivity to electrostatic discharges. In order to satisfy the laws of integration, thinner and thinner gate oxides are produced nowadays, in which the breakdown voltages from now on are less than 20 volts for the most advanced technology. The first protection devices used the avalanche regime of diodes mounted in reverse mode between the input pads and the Vss and Vcc power supply terminals. As long as the avalanche voltage of these diodes remains lower than the breakdown voltage of the gate oxide of the MOS transistors, the energy of the electrostatic discharge was able to be dissipated in the diodes. Unfortunately, with technical evolution, the avalanche voltages of these diodes have not fallen as much as the breakdown voltages of the gate oxides of the transistors. One solution frequently adopted is then the addition, in series between the input pad and the gate of the transistor, of a resistor which will form a time constant with the capacitance of the MOS transistor. The use of turned-off MOS transistors in parallel with the input also constitutes an interesting alternative. During the electrostatic discharge, the voltage rises on the drain, up to the avalanche regime of the junction. In the case of a N+ diffusion for the drain, the holes thus created by avalanche diffuse into the substrate. The emission of these holes causes a potential drop in the region of the source diffusion which then behaves like the emitter of a bipolar transistor which has become conducting. This effect corresponds to the conduction regime of the MOS transistor by "snap-back". The transistor becomes conducting and removes the energy. The advantage of this solution with transistors is that the removal of the energy can be done for voltages which are lower than in the case of diodes. However, when the avalanche current becomes too high, there is a risk of destroying the protection transistor. It is known (see US Patent No. 4,896,243 or the article "A synthesis of ESD input protection scheme" by C. Duvvury et al, which appeared in Journal of Electronics, Vol.29, No.1, Dec.1992, pp.1-19) to provide a protection thyristor in parallel with the turned-off MOS transistor. However, according to these documents, the thyristor triggers only under the effect of the voltage rise to which it is subjected. The relatively high value of the threshold voltage to be reached in order to trigger the thyristor constitutes a limitation of this known device. ESD problems may also affect the output pads. An output pad of a CMOS circuit is normally connected to the drains of two complementary MOS transistors constituting an output buffer. An ESD event causes the voltage to rise on the drains of the buffer, up to the avalanche regime of the junctions. When the avalanche current becomes too high, the buffer transistors may be destroyed. An object ot the invention is to enhance the known protection devices in the case of output pads, in order to allow more effective removal of the electrostatic discharges, while reducing the risks of damaging the device. According to the invention, there is provided an electrostatic discharge protection device for an integrated circuit, the integrated circuit including a substrate made of semiconductor and doped with impurities of a first type, said protection device comprising: at least one MOS transistor having a source consisting of a diffusion of a second type of impurities formed in the substrate and connected to a reference terminal of the integrated circuit, and a drain consisting of a diffusion of the second type of impurities formed in the substrate and connected to a pad of the integrated circuit; and a thyristor having a well formed in the substrate and doped with the second type of impurities, a first electrode consisting of a diffusion of the first type of impurities formed in the well and connected to said pad, a second electrode consisting of a diffusion of the second type of impurities formed in the substrate between the well and the drain of said MOS transistor and connected to said reference terminal, and a control electrode consisting of a region of the substrate situated between the well and the second electrode of the thyristor. When the voltage on the pad rises, the voltage across the thyristor rises at the same time as that across the MOS transistor. When this voltage becomes sufficient to create, by avalanche, electron-hole pairs within the drain junction of the MOS transistor, charge carriers migrate towards the region of the substrate which constitutes the control electrode of the thyristor. The latter then becomes conducting in order to remove the energy of the discharge. The triggering of the thyristor can be done for a relatively weak current of charge carriers, so that the risks of damage to the MOS transistor are substantially reduced. Furthermore, the removal of the energy of the discharge by a triggered thyristor is more effective than in the prior devices in which it results principally from an avalanche current. Such a device used for protecting of the outputs of an integrated circuit, is disclosed in US-A-5 290 724. More specifically, the present invention proposes an integrated circuit as set forth in claim 1. Preferably, the output buffer further includes an insulating layer portion deposited on the substrate between the drain of the MOS transistor and the second electrode of the thyristor, and a conductive layer portion deposited on said insulating layer portion and connected to said reference terminal. Such disposition of a layer portion, e.g. of polycrystalline silicon, promotes migration of the charge carriers created at the drain junction during an ESD event towards the control electrode of the thyristor rather than towards the source of the MOS transistor, thereby preventing a lateral bipolar transistor from becoming conducting prior to triggering of the thyristor. When the output buffer includes complementary MOS transistors, a thyristor may be provided in parallel with any one or both of the complementary transistors. However, it will generally be sufficient to associate a thyristor with the NMOS transistor, since NMOS transistors are usually more sensitive to ESD. Other features and advantages of the present invention will become apparent from the following description of preferred embodiments. In the accompanying drawings : Figure 1 is an electrical diagram of an output buffer according to the invention ; Figure 2 is schematic sectional view of an output buffer according to the invention ; and Figures 3 and 4 are schematic top views of portions of an output buffer according to the invention. Figure 1 illustrates an output pad 40 of an integrated circuit associated with an output buffer constituting an embodiment of the invention. The integrated circuit, produced on a common substrate 20 (silicon), includes conventional CMOS circuits comprising MOS transistors supplied with power between a reference terminal 9 at a potential Vss and a reference terminal 11 at a potential Vcc. The terminal 9 is typically a ground terminal (Vss = 0 V) and the terminal 11 is a positive power supply terminal (Vcc = + 5 V). In a conventional manner, the output buffer includes a NMOS transistor 41 and a PMOS transistor 46 having respective drains 42, 47 connected together to the output pad 40. The source 43 of NMOS transistor 41 is connected to the ground terminal 9, and the source 48 of PMOS transistor 46 is connected to the positive reference terminal 11. The gate 44 of NMOS transistor 41 is connected to a node 51 of the integrated circuit, and the gate 49 of PMOS transistor 46 is connected to a node 52 of the integrated circuit, which may be the same as or different from node 51. The NMOS transistor 41 is shown in the cross-sectional view of Figure 2. The substrate 20 of the circuit being of the P- type in the illustrated example (e.g. silicon with 10 15 atoms of boron per cm 3 ), the drain 42 and the source 43 each consist of a N+ type diffusion formed in the substrate (e.g. silicon with 10 20 atoms of phosphorus per cm 3 ), and the gate 44 is made of polycrystalline silicon. The output buffer further includes a thyristor 54 connected in parallel with NMOS transistor 41. The thyristor 54 comprises a well 56 formed in the substrate and doped N-with impurities of electron donor type (for example silicon with 10 16 atoms of phosphorus per cm 3 ), in which the anode 57 of the thyristor is formed, which consists of a P+ type diffusion (for example silicon with 10 20 atoms of boron per cm 3 ). Anode 57 is connected to the output pad 40. The cathode 58 of the thyristor 54, connected to the ground terminal 9, consists of a N+ type diffusion formed in the substrate 20 between the well 56 and the drain 42 of the NMOS transistor 41. Another N+ type diffusion 59 is formed in the well 56 beside the anode 57 and connected to the pad 40 in order to bias the well of the thyristor. The control electrode 60 of the thyristor 54 consists of the region of the substrate 20 situated between the well 56 and the cathode 58 of the thyristor. The substrate 20 is held at the potential Vss in the vicinity of the output buffer by a connection 61 consisting of a P+ type diffusion formed in the substrate 20. The well 56 of the thyristor 54 is situated between this diffusion 61 and the NMOS transistor 41. In Figure 2 the resistors and the bipolar transistors have been represented symbolically, forming the equivalent diagram of the thyristor 54. When manufacturing the circuit, the substrate 20 is first P- doped and the N- well 56 is formed therein. A first oxide layer is conventionally formed on the substrate, with thick oxide layer portions 63 and thin oxide layer portions 64. The thin oxide layer portions 64 correspond to the active regions of the circuit and have contact apertures 65-69 etched therein for providing electrical connections with the diffusions to be formed. Then, polycrystalline silicon is deposited to form, inter alia, the gate 44 of the NMOS transistor 41. Such polycrystalline silicon also includes a portion 71 situated above the region between drain 42 of transistor 41 and cathode 58 of thyristor 54. Then, the N+ and P+ diffusions are formed by a conventional self-aligned process. Then, a first metallization layer is deposited on the substrate. The first metallization layer includes different portions on the thin oxide layer portions : a portion 75 contacting source 43 through apertures 65 ; a portion 76 contacting drain 42 through apertures 66 ; a portion 77 contacting cathode 58 of thyristor 54 through apertures 67 ; a portion 78 contacting both diffusions 57 and 59 through apertures 68 ; and a portion 79 contacting diffusion 61 through apertures 69. A second thick oxide layer 81 is then deposited on the circuit. The second oxide layer 81 is provided with vias 82. A second metallization layer is deposited on the second oxide layer 81 and contacts the first metallization layer through the vias 82. The second metallization layer includes : a first portion 84 connected to the ground terminal 9 and in contact with portions 75, 77 and 79 of the first metallization layer and with the polycrystalline silicon portion 71 for providing the Vss connection of source 43, polysilicon 71, cathode 58 and diffusion 61 ; a second portion 85 connected to the output pad 40 and in contact with portions 76 and 78 of the first metallization layer for providing the pad connection of drain 42 and anode 57 ; and a third portion 86 connected to the circuit node 51 and in contact with the polycrystalline silicon gate 44. It has been found that the best ESD protection properties are obtained when the vias 82 formed in the second oxide layer portions are in alignment above respective contact apertures 65-69 of the underlying thin oxide layer portions. Figure 3 shows a diagrammatic top view of the output buffer after formation of the first metallization layer. It is seen that the thyristor 54 has a general ring configuration on the substrate, and surrounds the NMOS transistor 41 and the polycrystalline silicon portion 71. The N+ type diffusions 42, 43, 58, 59 are represented by contours in dashes (for clarity, the shape of the implantation mask is represented rather than the actual self-aligned N+ diffusion shape). The P+ type diffusions 57, 61 are represented by contours in solid lines. The N- well 56 is represented by a contour in dots and dashes. The polycrystalline silicon 44, 71 is represented by hatched areas. Finally, portions 75-79 of the first metallization layer are represented by regions with broken hatching. The illustrated NMOS transistor 41 is composed of a plurality of ring-shaped gates in a parallel arrangement, each surrounding a source region 43, and separated from each other by drain regions 42. Thus, the outer part of the NMOS transistor consists of the drain 42, whereby drain 42 is located as close as possible to the thyristor 54. The polycrystalline silicon portion 71 interposed between the drain 42 and the thyristor 54 surrounds the MOS transistor, except in the top region of Figure 3 where the gates are connected to the node 51. Figure 4 is a top view similar to Figure 3, showing the shapes of the portions 84-86 of the second metallization layer. Figures 3 and 4 can be superimposed to display the circuit. In both Figures , the little squares denote the locations of the vias 82 aligned above respective contact apertures 65-69 of the first metallization layer. It will be understood that the contact apertures 67-69 relating to thyristor 54 and diffusion 61 will generally be distributed all along their ring-shaped configuration, only those having vias 82 thereabove being shown in Figure 3. When electrostatic charges appear on the output pad 40, a rise in voltage occurs between the substrate 20, at the potential Vss, and the drain 42 of the NMOS transistor 41. From a certain voltage threshold, electron-hole pairs are created by avalanche within the PN junction between the drain and the substrate. This results in a current of holes which diffuse into the substrate. Due to the resistivity of the substrate and to the fact that the connection 61 is further from the drain 42 than the region 60 forming the trigger electrode of the thyristor 54, the holes arrive in this region 60 before being removed by the connection 61 (arrow G in Figures 1 and 2). This local de-biasing of the substrate in the region 60 causes triggering of the thyristor 54 which becomes conducting with a very low resistivity so as to remove the energy of the discharge. The removal of the energy is particularly effective when the ring configuration is adopted. The polycrystalline silicon portion 71 further improves the ESD performance by preferentially drawing the hole current towards region 60 due to the electric field that it generates. The device according to the invention is particularly suitable for CMOS-type integrated circuits, as this technology already presupposes the formation of N- wells in a P- substrate in order to produce the complementary MOS transistors. Accordingly, the production of the thyristor 54 does not need an additional process step for producing the well 56. Needless to say, if the circuit includes several output pads, a protection device will be provided for any or each output pad.

Claims: An integrated circuit comprising an output buffer, the integrated circuit including a substrate (20) made of semiconductor and doped with impurities of a first type, said output buffer comprising at least one MOS transistor (41) having a gate (44) connected to a node (51) of the integrated circuit, a source (43) consisting of a diffusion of a second type of impurities formed in the substrate and connected to a reference terminal (9) of the integrated circuit, and a drain (42) consisting of a diffusion of the second type of impurities formed in the substrate and connected to an output pad (40) of the integrated circuit, a thyristor (54) having a well (56) formed in the substrate and doped with the second type of impurities, a first electrode (57) consisting of a diffusion of the first type of impurities formed in the well and connected to said output pad, a second electrode (58) consisting of a diffusion of the second type of impurities formed in the substrate between the well (56) and the drain (42) of said MOS transistor and connected to said reference terminal (9), and a control electrode (60) consisting of a region of the substrate (20) situated between the well (56) and the second electrode (58) of the thyristor, characterized in that a diffusion (61) of the first type of impurities is formed in the substrate (20) and connected to the reference terminal (9), the well (56) of the thyristor being situated between said diffusion of the first type of impurities and said MOS transistor (41). An integrated circuit according to claim 1, wherein a diffusion (59) of the second type of impurities is formed in the well (56) of the thyristor and connected to the output pad (40). An integrated circuit according to claim 1 or 2, wherein the thyristor (54) has a general ring configuration on the substrate (20) about said MOS transistor (41). An integrated circuit according to any one of claims 1 to 3, further comprising an insulating layer portion deposited on the substrate (20) between the drain (42) of the MOS transistor and the second electrode (58) of the thyristor, and a conductive layer portion (71) deposited on said insulating layer portion and connected to said reference terminal (9). An integrated circuit according to claim 4, wherein said conductive layer portion (71) surrounds said MOS transistor (41), except in a region provided for connection of the transistor gate (44) to the circuit node (51). An integrated circuit according to claim 5, wherein the thyristor (54) has a general ring configuration on the substrate (20) about said MOS transistor (41) and said conductive layer portion (71). An integrated circuit according to any one of claims 4 to 6, wherein said conductive layer portion (71) is made of polycrystalline silicon. An integrated circuit according to any one of claims 1 to 7, wherein each of said diffusions (42, 43, 57, 58, 59, 61) is covered by a respective thin oxide layer portion (64) having contact apertures (66, 65, 68, 67, 69) formed therein, wherein respective portions (76, 75, 78, 77, 79) of a first metallization layer are deposited on said thin oxide layer portions (64) and electrically connected to the respective underlying diffusions through said contact apertures, wherein said first metallization layer is covered by another oxide layer (81) having vias (82) formed therein in alignment above respective contact apertures of said thin oxide layer portion, and wherein respective portions (85, 84) of a second metallization layer are deposited on said other oxide layer (81) and electrically connected to respective underlying portions of said first metallization layer through said vias (82) for providing the connection of the drain (42) of said MOS transistor and the first electrode (57) of the thyristor to the output pad (40) and the connection of the source (43) of said MOS transistor and the second electrode (58) of the thyristor to said reference terminal (9).

Inventors: CREVEL PHILIPPE, QUERO ALAIN, CREVEL, PHILIPPE, QUERO, ALAIN
Applicants: ATMEL NANTES SA
Application year: 1995
Main classification: H01L27
IPC codes: H01L27