Insulated gate thyristor

Abstract: To improve the maximum controllable current of the insulated gate thyristors by optimising the length and sheet resistance of the poly-silicon constituting the gate electrodes. The device has an n - base layer (3) with high resistivity, on the first surface of which is selectively formed a p type base region (4). The first source region (71), the second source region (72), and an n + emitter region (8) are selectively formed in the surface layer of the p type base region (4). The first gate electrode (11) is formed above the exposed area of the n - base layer (3), and the portion of the p type base region (4) extending between the n - base layer (3) and the first source region (71). The second gate electrode (12) is formed above the second source region (72), and the portion of the p type base region (4) extending between the second source region (72) and the emitter region (8). The length of the poly-silicon constituting the gate electrodes is set at 4 mm or less. Additionally or alternatively, the sheet resistance of the poly-silicon is set at 70Ω or less.

Description: The present invention relates to insulated gate thyristors, and particularly concerns insulated gate thyristors used as power switching devices. Thyristors have been used by virtue of their low on-voltage characteristics as indispensable devices for large capacity power conversion. Currently, GTO (gate turn-off) thyristors are used very often in the high-voltage large-current range. However, drawbacks of the GTO thyristors have also become clear. The drawbacks include: (1) the GTO thyristors require a large gate current for turning-off, that is a turn-off gain of the GTO thyristors is small, and (2) the GTO thyristors require large snubber circuits to turn them off safely. Furthermore, since the switching speed of the GTO is low, their use has been limited to the low frequency range. In 1984, V. A.K. Temple (cf. IEEE IEDM Tech. Dig., 1984, p282) disclosed a MOS control thyristor (hereinafter referred to as "MCT") which may be classified as a voltage driven type thyristor. Since then, analysis and improvement of the MCT have been done world wide. This is because the MCT is a voltage driven type thyristor which can be driven with a much simpler gate circuit than the previously known GTO thyristors, and since the MCT turns on at low on-voltage. Recently, new device structures have been proposed which have two insulated gate structures and operate in a thyristor mode when the devices are turned on and in an IGBT mode when the devices are turned off (cf. S. Momota et al., Proceedings of IEEE ISPSD, '92(1992), p28, and Y. Seki et al., Proceedings of IEEE ISPSD, '93(1993), p159). Figure 8 of the accompanying drawings is a cross-section of a double insulated gate MOS device (DGMOS) disclosed in 1992. In Figure 8, the device has a p+ collector layer 21 on which is formed an n - layer 23 via an n + buffer layer 22. A p type base region 24 is selectively formed in the surface layer of the n - layer 23. The surface layer of the p type base region 24, has n type base regions 25, 25 selectively formed therein. In the surface layer of each n type base region 25, p type emitter regions 26, 26 are selectively formed. An emitter electrode 27 is fixed in common to the p type emitter regions 26, 26 and to the n type base region 25. The emitter electrodes 27, 27 are connected to the emitter terminals E, E. The first gate electrode 31 is fixed via a gate oxide film 28 to the exposed area of the n - layer 23, to the portion of the p type base region 24 extending between the n - layer 23 and the n type base region 25, and to the portion of the n type base region 25 extending between the p type base region 24 and the emitter region 26. The first gate electrode 31 is covered with an insulation film 29, and connected to the first gate terminal G1 through an opening in the insulation film 29. The second gate electrode 32 is fixed via the gate oxide film 28 to the portion of the p base region 24 extending between the n type base regions 25, 25, and to the portions of the n type base regions 25, 25 extending between the p type base region 24 and the p type emitter region 26. The second gate electrode 32 is covered by the insulation film 29, and connected to the second gate terminal G2 through an opening in the insulation film 29. A collector electrode 30 is fixed to the p + collector layer 21, and connected with a collector terminal C. Voltages are applied to the first and second gate electrodes 31 and 32 in a manner as shown in Figure 9. When a voltage which exceeds the threshold value is applied to the terminal G1, an inversion layer is formed in the surface region of the p type base region 24 below the first gate electrode 31. As electrons pass through the inversion layer, an electron current flows into the n - layer 23 and the n + buffer layer 22. Since a positive voltage is applied to the collector electrode 30, the current which has flowed into the n - layer 23 and the n + buffer layer 22 generates a base current of a built-in PNP transistor composed of the p + collector layer 21, the n + buffer layer 22 and the n - layer 23, and the p type base region 24. The base current modulates the conductivity of the n - layer 23 and turns on the PNP transistor. A hole current caused by the conductivity modulation generates a base current of a built-in NPN transistor composed of the n + buffer layer 22 and the n - layer 23, the p type base region 24, and the n type base region 25. The base current drives the NPN transistor to finally operate a PNPN transistor composed of the p + collector layer 21, the n + buffer layer 22 and the n - layer 23, the p type base region 24, and the n type base region 25. Thus, the DGMOS of Figure 8 is turned on through the terminal G1. The DGMOS of Figure 8 is turned off by removing the gate voltages applied to the gate electrodes 31 and 32 with a time lag as shown in Figure 9. The voltage of the second gate electrode 32 grounded at the time t1 becomes negative with respect to the voltage of the gate electrode 31. As a result, an inversion layer is formed in the surface layer of the n type region 25 below the second gate electrode 32, and a p-channel MOSFET is turned on. Since the turning-on of the p-channel MOSFET causes a short-circuit of the p type base region 24 and the n type base region 25, the basic structure becomes equivalent to an IGBT. Therefore, in the steady state operation, the DGMOS operates at first in the thyristor mode through the first gate electrode 31. The DGMOS shifts to the on-state of the IGBT operation mode at the time t1 at the start of turning-off in response to negatively biassing the second gate electrode 32 with respect to the first gate electrode 31. At the time t2, 3 to 4µsec after the IGBT operation mode started, the DGMOS is turned off by removing the voltage applied to the first gate electrode 31 to stop the electron supply. The device disclosed in 1993 (DGMOT) has lowered its on-resistance by converting the p-channel device of Figure 8 to an n-channel one. These devices are featured by the mode switching which realises in one single device the low on-resistance of the thyristor and high speed switching of the IGBT. However, the uneven operations inside the MCTs and the devices having two insulated gate structures reduce the maximum controllable current to such small values that these devices cannot be used practically. In view of the foregoing, it is an object of the present invention to provide an insulated gate thyristor which facilitates the control of a large current. The objects of the present invention are achieved, according to a first aspect, by an insulated gate thyristor comprising: a high resistivity base layer of a first conductivity type; a base region of a second conductivity type selectively formed on a first surface of said base layer; two first source regions of the first conductivity type selectively formed on the surface of said base region; two second source regions of the first conductivity type formed on the surface of said base region between said two first source regions; an emitter region of the first conductivity type formed on the surface of said base region between said two second source regions; said two first source regions, two second source regions and emitter region being in sequence, laterally spaced apart and substantially rectangular; an emitter layer of the second conductivity type formed on a second surface of said base layer; first gate electrodes, each of which is fixed via an insulation film to a portion of said base region extending between one of said two first source regions and said base layer; second gate electrodes , each of which is fixed via an insulation film to a portion of said base region extending between one of said two second source regions and said emitter region; a first main electrode contacting with said emitter layer; and a second main electrode contacting with said emitter region and said two first source regions; said first and second gate electrodes being connected to wiring metal layers over only part of their lengths to leave exposed areas, the length (L) of each exposed area being 4 mm or less. A buffer layer of the first conductivity type and of low resistivity maybe formed between the base layer and the emitter layer. It is also preferable to set the sheet resistance of the first gate electrode and the sheet resistance of the second gate electrode at 70Ω/□ or less. The gate electrodes are preferably formed of polycrystalline silicon. By applying a voltage to the first gate electrode, an inversion layer is formed in the surface layer of the base region. In association with this, the first carriers are supplied from the second main electrode contacting with the first source regions. The first carriers function as a base current of a bipolar transistor and drive the bipolar transistor. The base layer, sandwiched between the emitter layer and the base region, constitutes with the buffer layer a base of the bipolar transistor. Then, the second carriers are injected from the emitter layer. Since the injected second carriers promote electron injection from the emitter region, the main thyristor operates to electrically connect the first and second main electrodes under a low on-voltage. The main thyristor is composed of the emitter layer, buffer layer and the base layer, base region, and the emitter region. In turning off the insulated gate thyristor, a voltage is applied at first to the second gate electrode to form a channel between the emitter region and the second source region. As the channel is formed, the second carriers injected from the emitter layer flow to the emitter region via the base region, the auxiliary electrode, the second source region, and the channel. As a result, the operation of the insulated gate thyristor shifts to the IGBT mode. By lowering the potential of the first gate electrode below the threshold value at this instant, the insulated gate thyristor is quickly turned off. The potential of the first gate electrode is lowered with a time lag after the voltage higher than the threshold value is applied to the second gate electrode. However, as the time lag is made shorter, the more parts of the device remain in the thyristor operation mode. As a result, the current controllable by the device is reduced. The voltage applied to the second gate electrode is expressed by the following equations. Vg2 = V0.(1-exp(-t/CR)) R = ρ .L/W Here, V0 is 1.5V for example; C the capacitance of the poly-silicon of the second gate electrode; R the resistance of the poly-silicon of the second gate electrode; ρ the sheet resistance of the poly-silicon (Ω); L the length of the poly-silicon; W the width of the poly-silicon; and t the time. The above equations indicate that as the capacitance and resistance of the poly-silicon increase, the rise time of the voltage applied to the second gate electrode becomes longer to switch the device more slowly to the IGBT operation mode. As a result, the device remains in the thyristor operation mode to cause current localization even when the potential of the first gate electrode is lowered below the threshold value. The capacitance, sheet resistance and width of the poly-silicon do not distribute within a semiconductor chip once the manufacturing conditions of the poly-silicon are fixed. The resistance of the poly-silicon depends on the length of that part of the poly-silicon not covered with the wiring metal layer. The resistance of the poly-silicon becomes large in the area remote from the current collecting wiring metal layer. The voltage applied to the gate electrode rises slowly in the remote area. Thus, the more remote the area is, that is the poly-silicon length is longer, the higher becomes the poly-silicon resistance, and the voltage applied to the gate electrode rises more slowly. Therefore, a rise time difference of the voltage applied to the second gate electrode is caused between the areas near to and remote from the wiring metal layer. The remote area in which the applied voltage rises slowly does not shift to the IGBT mode of operation, and current localises in the remote area. The current localisation may break down the device, and reduce the controllable current of the device. With an increase of the sheet resistance of the poly-silicon, the poly-silicon resistance increases. When the sheet resistance of the poly-silicon is high, the resistance difference along the length of the poly-silicon is increased to reduce the controllable current. On the contrary, as the poly-silicon length is shorter and the sheet resistance of the poly-silicon is lower, the poly-silicon resistance is reduced. As the poly-silicon resistance is lower, the resistance difference of the poly-silicon is reduced between the areas near to and remote from the wiring metal layer. As the resistance difference is reduced, the local rise time difference of the applied voltage is reduced. A smaller local rise time difference facilitates preventing the current localisation from occurring, and enables the controllable current of the insulated gate thyristor to be increased. Embodiments of the present invention will now be described in detail with reference to the accompanying drawings, in which: Figure 1 is a cross section of an embodiment of an insulated gate thyristor according to the present invention; Figure 2 is an isometric view showing the cell pattern of the insulated gate thyristor of Figure 1; Figure 3 shows the relation between the poly-silicon length of the second gate electrode and the controllable current of the 900V class device of the present invention; Figure 4 shows the relation between the poly-silicon length L of the second gate electrode and the controllable current of the 2500V class device of the present invention; Figure 5 shows the relation between the poly-silicon length L of the first gate electrode and the controllable current of the 900V class device of the present invention; Figure 6 shows the relation between the poly-silicon length of the first gate electrode and the controllable current of the 2500V class device of the present invention; Figure 7 shows the relation between the sheet resistance of the poly-silicon and the controllable current of the 900V class device of the present invention; Figure 8 is a cross section of a conventional DGMOS; and Figure 9 is a wave chart showing the voltage for driving the insulated gate thyristor of Figure 8. Referring no to the Figures, Figure 1 is a cross-section of an embodiment of an insulated gate thyristor according to the present invention, and Figure 2 is an isometric view showing the cell pattern of the insulated gate thyristor of Figure 1. Referring now to Figure 1, the device has an n - base layer 3 with high resistivity, on a first surface of which is selectively formed a p type base region 4. In the p type base region 4, p + base regions 5, 5 are formed. A p + emitter layer 1 is formed on the exposed face of an n + buffer layer 2 laminated onto the second surface of the n - base layer 3. In an alternative embodiment, the buffer layer 2 may be omitted. A p ++ contact region 6 overlaps with the surface region of each p + base region 5. An n type first source region 71 and an n type second source region 72 overlap with the surface region of each p ++ contact region 6 and extend to the surface region of the p + base region 4. An n + emitter region 8 is formed in the portion of the p type base region 4 extending between a pair of the second base regions 72. The first gate electrode 11 is fixed via a gate oxide film 91 to the exposed area of the n - base layer 3, to the portion of the p type base region 4 extending between the n - base layer 3 and the first source region 71, and to the first source region 71. The second gate electrode 12 is fixed via a gate oxide film 92 to second source region 72, to the portion of the p type base region 4 extending between the second source region 72 and the emitter region 8, and to the emitter region 8. An auxiliary electrode 10 contacts in common with the second source region 72 and the p ++ contact region 6. An anode 13 as the first main electrode is fixed to the p + emitter layer 1, and is connected with an anode terminal A. A cathode 14 as the second main electrode contacts with the first source regions 71, and with the emitter region 8, and is connected with a cathode terminal C. An insulation film 92 of phosphorus glass (PSG), silicon oxide, or the like isolates the first and second gate electrodes 11 and 12 from one another. The insulation film 92 also isolates each gate electrode from the second main electrode 14. The gate electrodes are made for example of poly-silicon. Referring now to Figure 2, each gate electrode is connected with a wiring metal layer 15 as shown in the Figure. The wiring metal layer 15 is connected with a gate pad (not shown) which is further connected with the gate terminal G1 or G2 of Figure 1. Here, the poly-silicon length L indicates the length between the edge of the wiring metal layer and the edge of the poly-silicon film. The operation of the thus configured insulated gate thyristor is explained below. By applying a positive voltage to the gate electrode 11 while the cathode 14 is grounded and a positive voltage is applied to the anode 13, an inversion layer (partial storage layer) is formed beneath the gate oxide film 91 to turn on the lateral MOSFET. In association with this, electrons are supplied, at first, to the n - base region 3 from the cathode 14 via the first n + source region 71 and the channel of the MOSFET. The electrons function as a base current of a PNP transistor and drive the PNP transistor. The PNP transistor has a structure comprising the p + emitter layer 1, the n + buffer layer 2 and the n - base layer 3, and the p type base layer 4 (p + base region 5). Holes are injected from the p + emitter layer 1. The holes partly flow to the p type base region 4 via the n + buffer layer 2 and the n - base layer 3. Then, by boosting the potential of the p type base region 4 to promote electron injection from the n + emitter region 8, the main thyristor 41 starts operating. During the operation, the second gate electrode is held at zero potential. In turning off the insulated gate thyristor, the lateral MOSFET is turned on at first by boosting the potential of the second gate electrode 12 above the threshold value of the MOSFET. Then, the p type base region 4 is biassed to an equi-potential with the cathode 14 through the MOSFET. The holes injected from the p + emitter layer 1 flow into the cathode 14 via the p type base region 4, the p ++ contact region 6, the auxiliary electrode 10, the second n + source region 72, the n channel, and the n + emitter region 8. As a result, the operation of the insulated gate thyristor shifts to that of the IGBT 42. By lowering the potential of the first gate electrode 11 below the threshold value at this instant, the insulated gate thyristor is turned off through a switching process similar to that of the IGBT. Since all the currents pass through the above described MOSFET in this operation mode, a transistor structure is left in which a part of the first n + source region 71 is not formed so that the contact region 6 may contact directly with the cathode 14 as shown in Figure 2. Figure 3 shows the relation between the poly-silicon length L and the controllable current of an experimental insulated gate thyristor of the present invention. The experimental device was designed and manufactured as the 900V class device. The 900V class experimental device has a p + silicon substrate with resistivity of 0.02Ωcm, and thickness of 450µm as the p + emitter layer 1 or as the p + collector layer 21. An n + layer with resistivity of 0.1Ωcm, and thickness of 10µm is formed as the n + buffer layer 2 or 22. An n - layer with resistivity of 70Ωcm, and thickness of 80µm is formed as the n - base layer 3 or 23. The p type base region 4 is formed by implanting ions at the doping amount of 1.10 14 cm -2 and by thermally driving the implanted ions for 5 hours. The active region of the device has an area of 0.16cm 2 . The poly-silicon width of the first gate electrode is 20µm. The poly-silicon width of the second gate electrode is 3µm. The poly-silicon length of the first gate electrode 11 is 4 mm. Figure 3 shows the relation between the poly-silicon length of the second gate electrode 12 and the controllable current measured by setting the time lag from feeding the on-signal to the second gate electrode until feeding the off-signal to the first gate electrode at 500nsec. Other experimental parameters include the poly-silicon length of 4 mm of the first gate electrode 11, the sheet resistance of 70Ω/□ of the first gate electrode 11, and the device temperature of 125 °C. The controllable current saturates at the poly-silicon length of 4 mm or less of the second gate electrode. At the poly-silicon length of 4 mm or less, the local rise time difference of the voltage applied to the gate electrode is shortened to several hundreds of nsecs or less. The rise time difference is caused by the difference of the poly-silicon resistance values (resistance value difference between the poly-silicon in the vicinity of the gate pad and the poly-silicon remote from the gate pad). Because of the short rise time difference, the device is turned off almost simultaneously over the entire active region. Since the breakdown mode is replaced by the so-called latch-up mode in which the parasitic thyristor is turned on, the controllable current saturates. Figure 4 shows the relationship between the poly-silicon length L of the second gate electrode 12 and the controllable current of an experimental insulated gate thyristor of the 2500V class. The 2500V class experimental device was manufactured on a bulk silicon wafer. Similarly to Figure 3, the controllable current saturates at a poly-silicon length of 4 mm or less. Figure 5 shows the relationship between the poly-silicon length L of the first gate electrode 11 and the controllable current of an experimental insulated gate thyristor of the 900V class with the poly-silicon length of the second gate electrode 12 fixed at 4 mm. Figure 6 shows the relation between the poly-silicon length of the first gate electrode 11 and the controllable current of an experimental insulated gate thyristor of the 2500V class with the poly-silicon length of the second gate electrode 12 fixed at 4 mm. In Figures 5 and 6, the controllable current saturates at the poly-silicon length of 4 mm or less. Figure 7 shows the relationship between the sheet resistance of the poly-silicon and the controllable current of an experimental insulated gate thyristor of the 900V class with the poly-silicon length of the first and second gate electrodes 11 and 12 fixed at 4 mm. The controllable current saturates at the sheet resistance of 70Ω/□ or less. At sheet resistances of 70Ω/□ or less, the local rise time difference of the voltage applied to the gate electrode, caused by the poly-silicon resistance difference, is shortened to several hundreds of nsecs or less. Because of the short rise time difference, the device is turned off almost simultaneously over the entire active region. Since the breakdown mode is replaced by the so-called latch-up mode in which the parasitic thyristor is turned on, the controllable current saturates. According to the present invention, by setting the length of the first and second gate electrodes on which the wiring metal layer is not disposed at 4 mm or less, and selecting the sheet resistance of the first and second gate electrodes to be 70Ω/□ or less, insulated gate thyristors are obtained which cope with large maximum controllable currents.

Claims: An insulated gate thyristor comprising : a high resistivity base layer (3) of a first conductivity type; a base region (4,6) of a second conductivity type selectively formed on a first surface of said base layer (3); two first source regions (71) of the first conductivity type selectively formed on the surface of said base region; two second source regions (72) of the first conductivity type formed on the surface of said base region (4,6) between said two first source regions (71); an emitter region (8) of the first conductivity type formed on the surface of said base region (4) between said two second source regions (72); said two first source regions (71), two second source regions (72) and emitter region (8) being in sequence, laterally spaced apart and substantially rectangular; an emitter layer (1) of the second conductivity type formed on a second surface of said base layer (3); first gate electrodes (11), each of which is fixed via an insulation film to a portion of said base region extending between one of said two first source regions (71) and said base layer (3); second gate electrodes (12), each of which is fixed via an insulation film (92) to a portion of said base region extending between one of said two second source regions (72) and said emitter region (8); a first main electrode (13) contacting with said emitter layer (1); and a second main electrode (14) contacting with said emitter region (8) and said two first source regions (71); said first (11) and second (12) gate electrodes being connected to wiring metal layers (15) over only part of their lengths to leave exposed areas, the length (L) of each exposed area being 4 mm or less. The insulated gate thyristor as claimed in claim 1 characterised by a buffer layer (2) of the first conductivity type and of low resistivity formed between said base layer (3) and said emitter layer (1). The insulated gate thyristor as claimed in claim 1 or claim 2 characterised in that the sheet resistance of each of said first gate electrodes (11) and said second gate electrodes (12) is 70Ω/□ or less. The insulated gate thyristor as claimed in any preceding claim characterised in that said first gate electrodes (1) and said second gate electrodes (12) comprise polycrystalline silicon.

Inventors: IWAMURO NORIYUKI, IWAMURO, NORIYUKI, Iwamuro, Noriyuki, c/o Fuji Electric Co Ltd
Applicants: FUJI ELECTRIC CO LTD, FUJI ELECTRIC CO. LTD.
Application year: 1995
Main classification: H01L29
IPC codes: H01L29