MOTION ESTIMATION USING A HIERARCHAL SEARCH

Abstract: A hierarchal search for moving image encoding determines a motion vector by comparing a target block to sets of blocks selected according to the results of previous comparisons. Typically, each set of blocks includes a central block and four blocks offset on x and y axes. Blocks most similar to the target block provide co-ordinates of a center block in a next stage of the search. The hierarchal search searches regions indicated by previous comparisons to be similar to the target block and thereby reduces the number of comparisons and the search time required to find a motion vector. A motion estimation circuit for the hierarchal search includes: five processing elements which compare the target block to five blocks; a first memory that asserts a target block pixel value to the processing elements; a second memory that asserts five search window pixel values to the processing elements. The processing elements operate in parallel, and an address generator selects the five search window pixel values according to output from the processing elements. The second memory contains three parts. One part is loaded with new data while the processing elements search data from the other two parts. Each part contains nine memory modules, each having an independently addressable data port, to reduce the memory size required to supply five pixel values.

Description: MOTION ESTIMATION USING A HIERARCHIA SEARCH CROSS REFERENCE TO RELATED APPLICATION This application is related to and incorporates by reference in its entirety cofiled U.S. patent application Serial No. unknown, entitled "Motion Estimation with Bit Rate Criterions." BACKGROUND OF THE INVENTION Field of the Invention This invention relates to circuits and processes for motion estimation in digital encoding of moving images. Description of Related Art A moving image can be created by displaying a succession of frames (or still pictures) where each frame differs slightly from a previous frame, and the succession of frames provides the illusion of a continuously moving image. For a typical digital display, each frame is a two-dimensional array of pixels which have colors or intensities indicated by pixel values. The pixel values can be written to memory to store a moving image or transmitted to broadcast a moving image. However, in a typical digital application, the large amount of data that must be transmitted or stored for a high quality moving image makes transmitting or storing every pixel value for every frame of a moving picture impractical. Many known moving image encoding techniques reduce the amount of data needed to represent a moving image. In difference-frame coding, a coder determines the difference between a predicted frame and a current frame of a moving image. The predicted frame may be, for example, the frame immediately before the current frame. The coder transmits a representation of the difference to a decoder. Since successive frames tend to be similar, the description of the difference typically requires less data than a description of the entire frame. The decoder having previously decoded the predicted frame combines the transmitted difference with the predicted frame to reconstruct the current frame. In motion compensated coding, motion estimation modifies the previous frame to provide a predicted frame that is more similar to the current frame. Typically, the current frame is partitioned into blocks, which are for example 16-by-16 pixels; and for each block in the current frame, the coder searches the previous frame to locate a block which is similar to the block in the current frame. A motion vector indicates the position of the block in the previous frame which is similar to the block in the current frame. For each block in the current frame, the coder transmits, to the decoder, a motion vector and a representation of the difference between the block in the current frame and the block indicated by the motion vector. The decoder constructs the current frame from the blocks at the locations indicated by the motion vectors. Determination of the motion vectors typically requires comparing a target block in the current frame to every block of the same size in a search window of the previous frame. The size of the search window depends on the range of motion vectors. Motion vectors having x and y components which range from -7 to 7 can indicate 225 different blocks in the previous frame, and a typical prior art encoder performs 225 comparisons of blocks to determine one motion vector with components that range from -7 to 7. Accordingly, determination of motion vectors can be a considerable calculational burden on a coder, and efficient search processes and circuits are needed to increase the speed and reduce the cost of coders which determine motion vectors. SUMMARY OF THE INVENTION A motion estimation circuit in accordance with an embodiment of this invention performs hierarchial searches to determine motion vectors for moving image encoding. The hierarchial search rather than comparing a target block in a current frame to fixed set of blocks in a search window, compares the target block to dynamically determined sets of blocks in the search window. The results of each comparison (or stage) of the search determines a next set of blocks to be compared to the target block in a next stage of the search. The hierarchial search reduces the total number of comparisons required to find a good match to the target block because the hierarchial search locates regions of the previous frame which are similar to the target block. Fewer location are searched, which allows a motion vector to be found more quickly than is possible in the prior art. The hierarchial search may use two one-dimensional searches on perpendicular axes to locate a region which best matches the target block. For example, a one- dimensional search of locations on a first line through a search center indicates a direction along the first line toward blocks which provides a better fit to the target block. A second one-dimensional search of locations on a second line, perpendicular to the first line, indicates a direction along the second line toward blocks which provides a better fit to the target block. A new search center is selected according to directions determined by the two one-dimensional searches, and searches along two more lines are repeated in a second stage of the search. One embodiment of the invention provides a search method for finding a motion vector for a target block in a current frame of a moving image. The method includes: selecting a first set of blocks of pixels from a previous frame in the moving image; comparing the target block to each block in the first set of blocks; selecting a second set of blocks from the previous frame, wherein the blocks in the second set are selected according to the results of comparing the target block to the first set of blocks; comparing the target block to each block in the second set of blocks; and generating a motion vector for the target block using results of comparing the target block to each block in the second set. Selecting a set of blocks marks a stage in a hierarchial search. The generation of the motion vector may include one or more further stages after selection of the first and second sets. Typically, five blocks are selected at each stage, a central block and four blocks offset, by a step size, along a pair of perpendicular lines, from the central block. The step size is typically decreased with successive stages to provide a coarse search when there is less information about the regions of the search window and a fine search when the region most like the target block has been found. A motion estimation circuit in accordance with an embodiment of this invention includes: parallel processing elements which generate parallel signals indicating differences between a target block and a set of blocks; a first memory that stores the target block and simultaneously asserts a pixel value from the target block to all of the processing elements; a second memory which stores a search window and asserts different search window pixel values to each of the processing elements; and an address generator that selects the pixel values that the second memory asserts to the processing elements. Typically, the motion estimation circuit contains five parallel processing elements. One compares the target block to a central block, and four compare the target block to four block offset from the central block by a step size. The processing elements perform the parallel comparisons for each stage of a hierarchial search, and the address generator generates address signals which depend on results from a previous stage of the search. The second memory is divided into three parts. The size of the parts of the second memory are such that two of the parts contain a current search window used by the processing elements, and a third of the parts is loaded with pixel values for a next search window while the processing elements perform a search on the current search window. The second memory can also be divided into nine memory modules, each module having an independently addressable output data port. Interleaving the data from a search window among the nine modules assures that for an even step size between the locations searched, no two processing elements ever simultaneously require pixel values from the same module. Interleaving pixel values among nine memory modules reduces the amount of memory required to simultaneously supply five parallel processors with five different pixel values from the current search window. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates an example hierarchial search in accordance with this invention. Fig. 2 shows a block diagram of a motion estimation circuit in accordance with an embodiment of this invention. Fig. 3A, 3B, 3C, and 3D illustrate the relationships among target blocks in a current frame, search windows in a previous frame, and a three-part memory used in accordance with this invention to store the search windows. Fig. 4 shows a block diagram of a processing element usable in the embodiment of Fig. 2. Fig. 5 illustrates interleaving of search window pixel values in nine memory modules of a memory in accordance with an embodiment of this invention. Fig. 6 shows a block diagram of a moving image coder and a moving image decoder in accordance with and embodiment of this invention. Use of the same reference symbols in different figures indicates similar or identical items. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A motion estimation circuit in accordance with an embodiment of this invention preforms hierarchial searches to determine motion vectors for moving image encoding. A hierarchial search rather than comparing a target block in a current frame to every block in a search window, compares the target block to iteratively determined sets of selected blocks in the search window, and each iteration (or stage) of the search indicates a next set of blocks selected for comparison. The hierarchial search reduces the total number of comparisons required to find the a good match to the target block. Accordingly, a motion vector may be found more quickly than is possible in the prior art. Each target block in a current frame has a corresponding block which is at the same relative position in a previous frame. Typically, a motion vector indicates a displacement in the previous frame from the top-left corner pixel of the corresponding block to the top-left corner pixel of a closely matching block. For example, if the current frame and the previous frame are identical, each blocks of the current frame is identical to a corresponding block in the previous frame, and each block in the current frame may be assigned a motion vector with x and y components equal to zero. If the current frame and the previous frame differ, a non-zero motion vector can indicate a block in the previous frame that provides a closer match to the target block in the current frame. Fig. 1 illustrates a Hierarchical One-Dimensional Search (HODS) of a search window in a previous frame, conducted to find a block which is similar to a target block in a current frame. Similarity is determined by a cost criterion such as the sum of the absolute differences between corresponding pixel values in the blocks compared. In Fig. 1, each cross point of the horizontal and the vertical lines represents the location of a top-left corner pixel of a block in the search window of the previous frame. The block having a location corresponding to the location of the target block has a top-left corner pixel at co-ordinates (0,0). The size of the search window depends on the range of the motion vector components and the size of the blocks being compared. Tn Fig. 1, x and y components of motion vectors are restricted to a range between -7 and 7 (a 4-bit binary value for each component) , but other ranges may be employed. In the first stage of the HODS, five locations IN, 1 , 1C, IS, and IE are searched by comparing the target -l- block to blocks having top-left pixels at locations IN, 1W, 1C, IS, and IE. The blocks are located along two axes, a horizontal (or y) axis and a vertical (or x) axis; and the blocks are separate from each other by a step size which is more half of the largest possible absolute value of a motion vector component. In Fig. 1 where the largest motion vector component is 7, the initial step size is 4, and locations IN, 1 , 1C, IS, and IE are (-4,0), (0,-4), (0,0), (4,0) and (0,4) respectively. A cost criterion is calculated for each of the five blocks to determine a measure of the difference between the target block and each of the five blocks searched. A commonly used cost criterion is the Sum of Absolute Differences (SAD) , but other cost criterion such as the Euclidean distance can be also used. In the following, p(i,j) denotes the pixel value of the pixel in row i and column j of the target block of the current frame, where i, j = 0, 1, ..., 15, for 16-by-16 pixel block. The target block and compared blocks are 16-by-16 for this example, but sizes other than 16-by-16 can be used. s(m,n) denotes a pixel value in row m and column n of the search window in the previous frame. For 16-by-16 blocks and motion vectors having components in the range between -7 and 7, the search window is a 30-by-30 pixel block, and m and n range from -7 to 22. The SAD for a block having has a top- right corner pixel at co-ordinates (r,t) in the search window, is defined as follows. B(t-r) = ∑ ∑ |p(i,j) " s(i-t,j-r) 1-0 j-0 After costs for the five blocks having top-right corners at locations IN, IW, 1C, IS, and IE are calculated, a minimum cost is determine from costs of the blocks having top-left corners IW, 1C, and IE on the horizontal axis, and a minimum cost is determine from costs of the blocks having top-left corners IN, 1C, and IS on the vertical axis. A center block for a second stage of the HODS has a top-right corner 2C having a y co-ordinate equal to the y co-ordinate of the location IW, 1C, or IE having minimum cost and has an x co-ordinate equal to the x co-ordinate of the location IN, 1C, or IS having minimum cost. For example, if the cost criterion is the SAD and the minimum SAD along the horizontal axis, i.e. among B(0,-4), B(0,0), B(0,4), is B(0,4), then the y co¬ ordinate of search center 2C for the second stage of HODS is 4. If the minimum SAD along the vertical direction, i.e. among B(-4,0), B(0,0), B(4,0), is B(4,0), then the x co-ordinate of search center^20 for the second stage is also 4. Thus, in the second stage, search center 2C is at (4,4), and five search locations 2N, 2W, 2C, 2S, and 2E are arranged along the horizontal and vertical lines through location 2C in a pattern similar to the arrangement of locations IN, IW, 1C, IS, and IE used in the first stage, but locations 2N, 2W, 2C, 2S, and 2E are separated by half of the step size of the first stage. In Fig. 1, search locations 2N, 2W, 2C, 2S, and 2E are at (2,4), (4,2), (4,4), (4,6) and (6,4), separated by a step size of 2. The costs for locations 2N, 2W, 2C, 2S, and 2E of the second stage are computed, and a center 3C for a third stage of the search is determined from the minimum of the costs along a horizontal line and a vertical line. For the example shown in Fig. 1, B(4,4) is the minimum of B(4,2), B(4,4), or B(4,6), and B(6,4) is the minimum of B(2,4), B(4,4), or B(6,4). Search center 3C is at (4,6) which also happens to be location 2E. In stage three of the HODS, five search locations 3N, 3W, 3C, 3S, and 3E are arranged at points (3,6), (4,5), (4,6), (4,7) and (5,6) in Fig. 1. The step size between search locations 3N, 3W, 3C, 3S, and 3E for third stage is one (half the step size used in second stage). Since location (4,6) has been searched in the second stage, the cost calculation for location (4,6) does not need to be repeated, but costs for the remaining four locations 3N, 3W, 3S, and 3E are computed. For the last stage of the HODS which is the third stage in the example of Fig. 1, determination of the minimum costs indicate the x and y components of a motion vector 100. In the example of Fig. 1, the horizontal minimum cost location is location 3W, (4,5), and the y-component of motion vector 100 is 5. The vertical minimum SAD location is 3S, (5,6), and the x-component of the motion vector is 5. Thus, motion vector 100 of the example in Fig. 1 has x and y components (5,5). The example HODS illustrated by Fig. 1 is a search involving a target block which is away from an edge of the current frame. For target blocks on the edge of the current frame, the edge of the previous frame limits the search window and reduces the number of locations that can be searched. Accordingly, the number searches preformed for a target block at an edge of the current frame is reduced because at least one of locations IN, IW, IS or IE is not in the previous frame. The example HOD of Fig. 1 searches 14 locations to determine motion vector 100. This is significantly less than the 225 which would be searched if every block in the search window was compared to the target block in the current frame. In some cases, motion vector 100 does not indicate the block in the search window which is most similar to the target block in the current frame, and motion vector 100 not being the best can result in a decrease in the amount of compression or a decrease in the image quality. However, HODS tends to guide the locations searched toward the region of a search window where the most similar block is, and motion vector 100 found by HODS provides good fit suitable for moving image coding. For one exemplary moving image, coded transmission of the moving image using motion vectors found by HODS had an increase in peak signal-to-noise ratio (PSNR) of less than about 0.5 Db when compared to coded transmission at the same bit rate using motion vectors found by a full search of every block in a search window. In most applications, the small degradation of image quality is offset by the significant decrease in hardware required for real time motion coding. Table 1 illustrates a schematic program structure for implementing a HODS. TABLE 1 1 Initialize a step size k and the components Δx and Δy of an estimated motion vector; 2 While (k > 1) 3 For (x,y) equal to (Δx,Δy) , (Δx+k,Δy) , (Δx- k,Δy), (Δx,Δy+k) , and (Δx,Δy-k) , 4 if the location (x,y) has not been searched, compute cost criterion B(x,y) ; 5 end of for; 6 set Δx equal to the x-coordinate of minimum of {B(Δx-k,Δy), B(Δx,Δy), B(Δx+k,Δy)}; 7 set Δy equal to the y-coordinate of minimum of {B(Δx,Δy-k), B(Δx,Δy), B(Δx,Δy+k)}; 8 set k equal to k/2; 9 end of while; 10 motion vector = (Δx, Δy) . In the program of Table 1, the initial estimated motion vector Δx, Δy will typically be zero (or a vector which indicates the block at a position in the previous frame corresponding to the position of the target block) because typically the corresponding block will be similar to the target block. The window searched for a better match depends on initial step size k. If initial step size k is 2" (e.g. 2, 4, or 8) then the search covers a range of motion vectors having components from -(2 B+1 -1) to 2° +1 -l (e.g. -3 to 3, -7 to 7, or -15 to 15). Steps sizes which are not powers of 2 may also be used. If desired, a different steps size could be used for the horizontal and vertical directions, for example to search a rectangular search window. Additionally, the HODS may be terminated before the step size k is reduced to one. Other variations of the program of Table 1 will be apparent to those skilled in the art. Fig. 2 shows a block diagram of a motion estimation circuit 200. Motion estimation circuit 200 is described for an embodiment which handles 16-by-16 pixel target blocks and a maximum possible motion vector component of 7, but the architecture shown in Fig. 2 also works for other searches. Motion estimation circuit 200 contains an on-chip three-part memory 210 for storing search windows and an on-chip memory 220 for the target block. Fig. 3A shows the relative locations of a target block 301 in a current frame and a search window 311 in the previous frame. Fig. 3A also shows the positions of the next two target blocks 302 and 303 for which motion vectors are determined. Figs. 3B and 3C show the relative positions of search windows 312 and 313 for blocks 302 and 303 respectively. Search windows 311, 312, and 313 of the consecutive target blocks 301, 302, and 303 overlap. For example, search windows 311 and 312 overlap by about half of their width. Memory 210 (Fig. 2) is partitioned into three parts Ml, M2, and M3. Each part Ml, M2, or M3 stores 480 (16 x 30) pixel values, for the case where 16 is width of each target block and 30 is the height (and width) of each search window. For target block 301, search window 311 is stored in memory parts Ml and M2 as shown in Fig. 3D. Memory part Ml holds the left part (16 columns) of search window 311. Memory part M2 holds the right part (14 columns) of search window 311. The left part (16 columns) of search window 312 overlaps the right part of search window 311 and is also stored in memory part M2. During motion estimation for target block 301, the right part of search window 312 (which is also the left part of search window 313) is read into M3 from -an external memory (not shown) . Accordingly, search window 312 for target block 302 is in parts M2 and M3 before motion estimation for target block 302 begins. The motion vector for target block 302 is determined from the data in memory parts M2 and M3, and the right part of search window 313 for target block 303 is loaded into Ml while doing motion estimation for block 302. In this way, search window 313 will be ready in memory parts M3 and Ml before motion estimation for block 302 ends and motion estimation for block 303 begins. Three-part on-chip memory 210 reduces the bandwidth requirement for access to external memory because overlapping portions of two search windows are read from the external memory once and fewer new pixel values are read for each search. Target blocks 301, 302, and 303 shown in Figs. 3A to 3C are away from the edge of current frame. Target blocks which are at an edge of the current frame do not require a full 30-by-30 search window for a HODS. Accordingly, in memory 210, the values which are at addresses indicating a location outside a frame are irrelevant to the HODS. For a block at the right edge of the current frame, one part Ml, M2, or M3 holds all the relevant search window pixel values, and no right part of the search window is required. During the time when the right part would be loaded, the left part of the search window for a following target block is loaded in to the next memory part M2, M3, or Ml. Typically, the target block following a block on the right edge is a block at the left edge of a next row of blocks in the frame. Returning to Fig. 2, five parallel processing elements 231 to 235 receive search window pixel values from memory 210 and target block pixel values from memory 220, and calculate five costs for each stage in a HODS. Circuit block 240 determines a vertical minimum of costs from processing elements 231 to 233 and a horizontal minimum of costs from processing elements 233 to 235 and provides to an address generator 250 x and y components of a search center aligned with the blocks having the vertical and horizontal minimum costs. Address generator 250 generates an address signal which indicates the locations to be searched in a stage, and following the last stage, generates a signal indicating the motion vector found in the HODS. Motion estimation circuit 200 executes a HODS process indicated in Table 1 as the follow. Address generator 250 initializes and changes the step size k and the estimated motion vector (Δx,Δy) as required for the HODS and for generation of address signals selecting the search location from memory 210. The "while" loop between line 2 and line 9 is executed as PCMJS95/15524 sequential stages. In each stage, the computation of the costs as described by the "for" loop between line 3 and line 5 of Table 1 is executed in parallel by the five processing elements 231 to 235. Processing elements 231, 232, 233, 234, and 235 calculate costs for the locations (Δx-k,Δy) , (Δx+k,Δy) , (Δx,Δy) , (Δx,Δy+k) , and (Δx,Δy-k) respectively. Circuit block 240 determines x and y components of a search center for the " next stage based on the costs from processing elements 231 to 235. Fig. 4 shows a processing element 400 for an embodiment of this invention where the cost criterion is the SAD. Processing element 400 contains a math block 410 which determines the absolute value of the difference between a pixel value p from a target block in the current frame and a pixel value s from a search window in the previous frame. In 256 clock cycles (one for each pixel value in the target block) , pixel values p and s are asserted to math block 410, and an accumulator 420 accumulates a sum of the absolute values of the differences. After the difference between the last pixel values p and s are accumulate, a latch 430 stores the total SAD while accumulator 420 is reset for a next stage of the HODS or for a next HODS. In one embodiment of motion estimation circuit 200 of Fig. 2, each of processing elements 231 to 235 is identical to processing element 400. Memory 220 broadcasts target block pixel values p(i,j) to all processing elements, so that each processing element simultaneously receives the same pixel value p(i,j). An index i or j which indicates the row or column of the pixel value p(i,j) changes by one each clock cycle. Memory 210 asserts a different pixel value to each of the blocks 231 to 235. During each clock cycle, processing elements 231, 232, 233, 234, and 235 receive pixel values s(Δx-k+i,Δy+j) , s(Δx+k+i,Δy+j) , s(Δx+i,Δy+j) , s(Δx+i,Δy-k+j) , and s(Δx+i,Δy+k+j) from memory 210. Typically, memory 210 has at least five independently addressable output data ports. In one embodiment of this invention, each part of Ml, M2, and M3 of memory 210 is divided into nine memory modules ml to m.9. Each module ml to m9 has an independently addressable output data port for providing a search window pixel value to one of the five processing elements 231 to 235. The search window pixel values are interleaved in the nine memory modules ml to m9 of memory part Ml as shown in Fig. 5. For each row of pixel values, three consecutive memory modules are used cyclically. Modules ml, m2, and m.3 store the first row of pixel values. Modules m4, m5, and m6 store the second row, and modules m7, ro8, and m.9 store the third row. The next three rows, the fourth, fifth and sixth, are stored in the same pattern as the first three rows. This three-row pattern for storage is repeated for the rest of rows stored in memory part Ml. Memory parts M2 and M3 are structured in the same way, so that memory 210 includes a total of 27 modules (nine modules for each part Ml, M2, and M3) . The interleaved storage pattern of modules ml to m9 in Fig. 5 assures that if the step size between search locations is not a multiple of three, no two of processing elements 231 to 235 simultaneously require data rom the same one of modules ml to m.9. During each clock cycle, processing element 233 compares a pixel value p(i,j) from the target block to a search window pixel value s(Δx+i,Δy+j) , and processing elements 231, 232, 234, and 235 compare search window pixel values s(Δx-k+i,Δy+j) , s(Δx+k+i,Δy+j) , s(Δx+i,Δy-k+j)„ and s(Δx+i,Δy+k+j) to the pixel value p(i,j). For example, during a particular clock cycle, the search window pixel value s(Δx+i,Δy+j) for processing element 223 is pixel value 503 from module ml of memory 210. The other search window pixel values are offset from pixel value 503 by the step size. If the step size is two, processing element 231 compares p(i,j) to pixel value 521 which is from memory module m4, processing element 232 compares p(i,j) to pixel value 522 which is from memory module m7, processing element 234 compares p(i,j) to pixel value 524 which is from memory module m3, and processing element 235 compares p(i,j) to pixel value 525 which is from memory module m.2. For a step size of one, processing elements 231, 232, 234, and 235, uses pixel values 511, 512, 514, and 515 in modules m.7, ra.4, m.2, and m3, respectively. More generally, since the interleaving pattern of Fig. 5 repeats after three pixel values either horizontally or vertically, the same module is used twice only if the step size is a multiple of three. Fig. 6 shows a moving image coder 610 in accordance with an embodiment of this invention. Coder 610 receives a series of frames of a moving image from an external source (not shown) which may be for example a memory or a video camera. Coder 610 transmits a coded representation of moving image, over a channel 620 to a moving image decoder 630. Channel 620 may for example be an integrated services digital network (ISDN) line or a local area network (LAN) line or modems and a phone line. Decoder 630 decodes the coded representation and generates a series of frames which represent the moving image. Each frame received by coder 610 is represented by one or more two-dimensional arrays of pixel values. For a typical black-and-white or gray scale image, the pixel values represent the intensity of a pixel in a two-dimensional display. Pixel values for color images typically represent either a color index which identifies a color from a pallet of colors or represents the magnitude of one or more color components in conventional color representations such as RGB or YUV. For conventional color components, each frame is represented either by three two-dimensional arrays (color planes) or by a single two-dimensional array containing (chunky) pixel values which are a combination of the three component values. The following example considers the case of a gray scale moving image. Other application will be apparent to those skilled in the art. A two-dimensional array representing the current frame is applied via a bus 614 to a subtractor 611 and to motion estimation circuit 200, a target block at a time. Motion estimation circuit 200 determines a motion vector for each target block, and supplies the motion vector to a predictor 616. Predictor 616 selects from a decoded previous frame a predicted block indicated by the motion vector, and asserts pixel values from the predicted block to subtractor 611. Subtractor 611 determines the difference between the target block and the predicted block. The difference generated by subtractor 611 is a data block which is the difference between the pixel values in the target block and the corresponding pixel values in the predicted block. If the predicted block is sufficiently similar to the target block, most of the values in the difference are small or zero. A quantizer 612 converts the difference between the target block and the predicted block from a standard two-dimensional array representation to a compressed representation which on average reduces the amount of data required to represent the difference. The representation can either be exact or can be an approximation. U.S. patent application serial No. 08/153,322, filed November 15, 1993, entitled "QUADTREE-STRUCTURED WALSH TRANSFORM VIDEO/IMAGE CODING" describes a quantizer that uses a quadtree structured Walsh transformation, linear quantization, and Huffman coding to represent a difference and is incorporated by reference herein in its entirety. A source coder 613 formats and encodes the quantized representation from quantizer 612 for transmission on channel 620. Motion vectors corresponding to the quantized representation are also transmitted through channel 620 to decoder 630. A source decoder 633 in decoder 630 receives the coded signal from channel 620 and decodes the quantized representation of the difference to a dequantizer 637. Dequantizer 637 preforms the inverse operation of quantizer 612 and generates a two-dimensional array representing the difference between the target block and the predicted block. The two-dimensional array typically differs from the difference generated by subtractor 611 for a variety of reasons. For example, the quantized representation from quantizer 612 nay be an approximation to reduce the amount of data transmitted or may contain round off error. An adder 638 adds difference blocks from dequantizer 637 to blocks from a predictor circuit 636. Predictor 636 provides the blocks from the previous frame, indicated by the motion vectors from coder 610. Typically, while dequantizer 637 is decoding a difference for a block, predictor circuit 636 uses a motion vector from channel 620 to retrieve from the previous decoded frame a block indicated by the motion vector. The previous decoded frame is typically stored in an external memory (not shown) which is accessible by predictor circuit 636, but alternatively may be stored in predictor circuit 636. The result of the addition performed by adder 638 is a two-dimensional array which is approximately equal to the two- dimensional array representing the current frame. Coder 610 contains a dequantizer 617 and an adder 618 which are identical to dequantizer 637 and adder 638 respectively. Dequantizer 617 receives the quantized representation of the differences from quantizer 612 which adder 618 combines with the predicted blocks from predictor circuit 616 to generate a decoded current frame which is identical to the decoded current frame produced by adder 638 in decoder 630. The decoded current frame may be saved to an external memory (not shown) and used by predictor 616 to generate a predicted blocks for the next frame in series. Although the present invention has been described with reference, to particular embodiments, the description is only an example of the invention's application and should not be taken as a limitation. Various adaptations and combinations of features of the embodiments disclosed will be apparent to those skilled in the art and are within the scope of the present invention as defined by the following claims.

Claims: We claim: 1. A method for generating a motion vector for moving image encoding, comprising: selecting a target block of pixels from a first two-dimensional array representing a current frame in a moving image; selecting a first set of blocks of pixels from a second two-dimensional array representing a previous frame in the moving image; comparing the target block to each block in the first set of blocks; selecting a second set of blocks of pixels from the second two-dimensional array, wherein the blocks in the second set are selected according to the results of comparing the target block to each block in the first set; comparing the target block to each block in the second set of blocks; and generating a motion vector for the target block using results from comparing the target block to each block in the second set. 2. The method of claim 1, wherein selecting the first set of blocks comprises: selecting a first block, a second block, and a third block in the previous frame, wherein the first, second, and third blocks have top-left corner pixels which are on a first axis in the previous frame; and selecting a fourth block and a fifth block in the previous frame, wherein the first, fourth and fifth blocks have top-left corner pixels which are on a second axis of the previous frame. 3. The method of claim 2, wherein comparing the target block to each block in the first set comprises determining a cost for each block in the first set, the cost for each block indicating differences between pixel values in the target block and pixel values in that block. 4. The method of claim 3, wherein selecting the second set of blocks comprises: selecting a sixth block in the previous frame, the sixth block having a top-left corner pixel which is aligned with the top-left corner pixel of one of the first, second, and third blocks and aligned with the top-left corner pixel of one of the first, fourth, and fifth blocks, wherein the one of the first, second, and third blocks with which the sixth block is aligned has a cost that is less than or equal to the costs of the first, second, and third blocks, and wherein the one of the first, fourth, and fifth blocks with which the sixth block is aligned has a cost that is less than or equal to the costs of the first, fourth, and fifth blocks; selecting a seventh block and an eighth block in the previous frame, wherein the sixth, seventh, and eighth blocks have a top-left corner pixel on a line parallel to the first axis; and selecting a ninth block and a tenth block in the previous frame, wherein the sixth, ninth, and tenth blocks have a top-left corner pixel on a line parallel to the second axis. 5. The method of claim 4, wherein: the top-left corner pixels of the second and third blocks are each a first distance from the top-left corner pixel of the first block; the top-left corner pixels of the seventh and eighth blocks are each a second distance from the top-left corner pixel of the sixth block; and the second distance is about half of the first distance. 6. The method of claim 5, wherein generating a motion vector further comprises: selecting a third set of blocks of pixels from the second two-dimensional array, wherein the blocks in the third set are selected according to the results of comparing the target block to each block in the second set; comparing the target block to each block in the third set of blocks; and generating a motion vector for the target block using results from comparing the target block to each block in the third set. 7. The method of claim 2, wherein: selecting the target block comprises storing pixel values of the target block in a first memory; selecting the first set of blocks comprises: storing pixel values of a search window of the second two-dimensional array, in a second memory; and generating address signals for the second memory, which select pixel values of the first set of blocks; comparing the target block to each block in the first set further comprises: asserting a pixel value from the first memory to five processing elements simultaneously; asserting five different pixel values from the second memory to the five processing elements; repeating asserting values from the first and second memory; and accumulating five costs indicating differences between the pixel value from the first memory and the pixel values from the second memory. 8. A process for generating a motion vector corresponding to a target block in a current frame of a moving image, the process comprising: (a) storing a step size in a memory; (b) storing a first component and a second component of an estimated motion vector in the memory, the estimated motion vector identifying a first block in a previous frame of the moving image; (c) determining a first cost which indicates a difference between the target block and the first block; (d) determining second, third, fourth, and fifth costs which indicate differences between the target block and second, third, fourth, and fifth blocks in the previous frame, wherein a vector formed by adding the step size to the first component of the estimated motion vector identifies the second block, a vector formed by subtracting the step size from the first component of the estimated motion vector identifies the third block, a vector formed by adding the step size to the second component of the estimated motion vector identifies the fourth block, and a vector formed by subtracting the step size from the second component of the estimated motion vector identifies the fifth block; (e) increasing the first component of estimated motion vector by the step size, if the second costs is less than the first and third costs; (f) reducing the first component of estimated motion vector by the step size, if the third costs is less than the first and second costs; (g) increasing the second component of estimated motion vector by the step size, if the fourth costs is less than the first and fifth costs; (h) reducing the second component of estimated motion vector by the step size, if the fifth costs is less than the first and fourth costs; (i) reducing the step size by about half; (j) repeating steps (c) through (i) one or more times; and (k) generating a motion vector which equals the estimated motion vector. 9. The method of claim 8, wherein repeating steps (c) through (i) one or more times comprises repeating steps (c) through (i) until the step size is less than one. 10. The method of claim 8, wherein the first, second, third, fourth, and fifth costs are determined simultaneously. 11. The method of claim 8, wherein determining a cost comprises calculating the cost if the cost was not previously determine, and using a previously determined cost if the cost was previously determined. 12. A motion estimation circuit comprising: a plurality of processing elements, wherein each processing element provides a signal which depends on a difference between a first and a second data signals asserted to the processing element; a first memory being operably coupled to simultaneously assert identical data signals to each of the processing elements; a second memory operably coupled to simultaneously assert data signals to the processing elements, wherein the second memory asserts to each processing element a data signal which is independent of the data signals asserted to the other processing elements; and an address generator operably coupled to the processing elements and to the second memory, the address generator providing to the second memory an address signal which selects the data signals that the second memory asserts to the processing elements. 13. The motion estimation circuit of claim 12, wherein the second memory comprises a three parts, such that data can be written into any one of the parts of the memory while data is read from the other two parts of the memory. 14. The motion estimation circuit of claim 13, wherein each part of the second memory comprises nine modules each module having an independently addressable data port. 15. The motion estimation circuit of claim 12, wherein the second memory comprises a memory having nine independently addressable modules. 16. The motion estimation circuit of claim 12, wherein the address generator generates address signals which depend on the output signals of the processing elements. 17. The motion estimation circuit of claim 12, wherein the plurality of processing elements comprises five processing elements. 18. A method for generating a motion vector for moving image encoding, comprising: reading pixel values for a first part of a first search window, from a first memory and writing the pixel values into a first part of a second memory; reading pixel values for a second part of the first search window from the first memory and writing the pixel values into a second part of the second memory, wherein the pixel values of the second part of the first search window are also pixel values in a first part of a second search window; comparing a first target block to the pixel values in the first and second parts of the second memory; /, reading pixel values for a second part of the second search window, from the first memory and writing the pixel values into a third part of a second memory; and comparing a second target block to the pixel values in the second and third parts of the second memory. 19. The method of claim 18, wherein comparing a first target block to the pixel values in the first and second part of the second memory and reading pixel values for the second part of the second search window are performed simultaneously. 20. The method of claim 18, wherein the pixel values of the second part of the second search window are also pixel values in a first part of a third search window, and the method further comprises: reading pixel values for a second part of the third search window, from the first memory and writing the pixel values into the first part of the second memory; and comparing a third target block to the pixel values in the third and first parts of the second memory. 21. The method of claim 18, wherein the writing pixel values into the first, second, and third parts of the second memory respectively comprises writing to a first, second, and third data ports of the second memory. 22. A motion estimation circuit comprising: a first memory; a second memory, the second memory having a first, a second, and a third parts, each part having a data port for writing pixel values to that part; and a processing element operably connected to read pixel values from the first and second memory and generate a motion vector from the pixel values, wherein the processing element is able to read pixel values from two of the first, second, and third parts of the second memory, while pixel values are written to a remaining one of the first, second, and third parts of the second memory. 23. The motion estimation circuit of claim 22, wherein: the processing element, and the first and second memories are integrated together on a die; the circuit further comprises a third memory external to the die; and pixel values from the third memory are written into the second memory while the processing element reads pixel values from the first and second memory.

Inventors: RAN XIAONONG, VAN SCHERRENBURG MICHAEL, RAN, XIAONONG, VAN SCHERRENBURG, MICHAEL
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1995
Main classification: G06T7
IPC codes: G06T7, H04N7