COUPLING OF SDH SIGNALS IN A TS'S'TS'S'T COUPLING NETWORK

Abstract: The invention relates to a method of switching STM-N signals in a TS'S'TS'S'T switching network in which the number of input and output ports of the centre stage (STS) is, for example, double that of the ports of the input or output stages, whereby the doubled portion is called extra blocks. In the method in accordance with the invention, first a switching solution is obtained for the signals that travel through the time and space switches (TS) of the input side in such a way that in the same time slot of the outputs of the time switches (T) there is not more than one signal that goes to the same output port of the switching network. Thereafter a solution is obtained for the outputs of the space switches (S) of the input side in such a way that to the same centre block (STS) of the centre stage there does not go more than one signal that is to be routed to the same output block (ST). Finally, it is a simple matter to obtain a solution through the centre stage (STS) and the output side (TS).

Description: Coupling of SDH signals in a TS'S'TS'S'T 1 coupling network The invention relates to the use of a TS'S'TS'S'T switching network and especially to a method of switching SDH STM-N signals. Synchronous digital hierarchy (SDH) comprises an extensive facility for the transmission of time-divided signals in a telecommunications network. Mention can be made of the recommendation ITU-T G.707, which defines the STM-1 signal of the SDH signals, ie, the signal of the Synchronous Transport Module of the first level. Other defined levels are STM-4, STM-16 and STM-64. The STM-N frame structure (in which N = 1, 4, 16, 64) is defined in the recommendations ITU-T G.708. The STM-1 basic frame is composed of bytes (8 bits). In an STM-1 frame it is possible to transmit units of a subsystem, for example, 63 TU-12 signals, in each of which 2,048 kbit/s signals can be transported. The STM-N frames are assembled into logical multiframes. The SDH signals are formed from signals of the subsystems by the interleaving of bytes. Thus each signal can be separated into its own time slot in the main signal. Digital Cross Connect systems have been defined for SDH (ITU-T Draft Resolutions G.sdcx-l...-3). SDH DXC is capable of connecting, in the manner desired, traffic from different SDH levels. Use of cross connect equipment provides the possibility of forming remote-controlled routings, connecting traffi to reserve routes, connecting traffic from one signal to many signals (broadcasting or copying), etc. Ordinarily, connections through a cross connect device are bidirectional. There exist a variety of different cross connect architectures. A structure that fulfils well the conditions of non-blocking and implementability is a quadratic time switch structure, a TxT S structure (Time x Time - Space). Because this time switch structure expands quadratically, in large cross connect units the equipment becomes very large in size. In principle, time switches are memory elements and the space switch is composed of switch elements. A double capacity TST structure, ie, a time - space - time cross connect structure also fulfils well the requirement of non-blocking properties and implementability. The TST structure is better suited to large cross connect units than is the TxT S structure because in a TST arrangement only the size of the space switch increases quadratically. Depending on how the space switch is implemented, its size may nevertheless pose problems in larger cross connect equipment. This kind of problem can be solved by means of a modified space switch stage arrangement in which plain space switches are replaced by a switch network. Since time switching connections are also possible in a switching network, the capacity of the outermost space switches can be one-fold. The centre switch block of the system is generally marked T&S. The T&S switch block can be, for example, of the form space-time-space, STS, or time x time - space, TxT-S. In a structure that is considered advantageous, which uses the STS structure of the centre stage, the entire switching network is then of the form TS'S'TS'S'T. In this case the STS structure of the centre port can advantageously have twice the number of inputs and outputs compared with the number of inputs and outputs of the entire switching network. Each switching element must be capable of switching signals in a byte mode. The problem addressed by the invention is now to indicate, in connection with TS'S'TS'S'T switching network for switching SDH signals, a method by which non-blocking switching can be implemented. This problem is solved by means of the method in accordance with claim 1. Other advantageous embodiments of the invention are disclosed in the dependen claims. The problem presented is solved by means of the method according to the invention in which the signals to be switched can be packed such that new signals can be formed simply and fast via the parts of the switching network th are free. When new switching connections have been made, the connections are packed in such a way that at least the same number of free parts is again available. It is essential for the invention that signals are arranged efficiently in the time- space switch blocks of the input side. In this case, a solution is provided for th signals that travel via the time and space switches of the input side in such a way that at the outputs of the time switches in the same time slots there is not more than one signal going to the same output port of the switching network, and that at the outputs of the space switches not more than one signal that is to be routed to the same output block goes to the same centre block of the active centre stage, whereby in the time switches and space switches the signals that remained without a desired solution in the previous phases are routed via the extra blocks of the centre stage to the space-time switches of the output side. The method according to the invention and a cross connect architecture can be used at all SDH levels, ie, for the cross connection of the defined signals STM- 1...STM-64 and other corresponding signals. Although in the accompanying figures the situation depicted is that of a traditional space switch module having 16 input and 16 output interfaces of the AU-4 signals (= STM-1 capacity), it is natural that smaller and, especially, larger numbers of signal lines can be used within the purview of the invention. In a cross connect network the essential point is that the switching connections can be made in a byte mode. Accordingly, the signals of the upper level, such as AU-4, TU-3 and TU-2, are "splittable" into as many small parts as there are TU-12 signals. The method according to the invention offers an advantageous way of processing first the AU-4 signals in the ports of the input stages, which signals are routed via the switch stages in such a way that in each given case they are primarily routed via the STS block (space-time-space) of the same centre stage. The switching algorithm does not try to pack, in an optimal manner, signals via the blocks of the other half of the centre stage - ie, the active half because it ha been observed in practice that when using a suitable algorithm, and when seeking a solution for the first time switch, in general only a very few signals do not fit within the framework of the solution. The same holds for the first space switch stage. Several solution algorithms can be found for the first space and time switch. In the solution to be worked out for the space switch, the idea is to arrange the time slots in such a way that after the switching arrangement, in one column - ie, in one time slot - there is not more than one signal that goes to the same port. If a solution of this kind is not found, the signals that contravene the correct solution are connected via extra blocks of the centre stage. A corresponding algorithm, which is used in seeking a solution for the time switches can also be used for the first space switch stage. Here the object is to resolve the situation by columns, ie, time slots, in such a way that not more than one signal that is routed to the same output block goes to the same centre block. As in the time switch solution, when a solution is not found, the signals that contravene the correct solution are connected to extra blocks. If it is desired to enhance the packing, the algorithm can be improved after the fetches for the first solutions in such a way that the arrangement for the signals is repeated in the first TS block. In this case the object is to see to it that the number of signals going to the centremost STS stage, which signals go to an S block of the output side, cannot exceed the number of time slots, which is 63. In addition, the number of signals going from the TS block of the input side to the STS block cannot exceed the capacity of the AU-4 signals. If it is desired t enhance the packing capacity in the above-mentioned manner, the STS algorith will have to be solved in the blocks of the centre stage so that the signals can b got out and brought to the final stages in the correct sequence. In practice, when solutions are obtained separately for the time and space switches, packing is sufficient so that there is enough space for new signals in the extra centre blocks before repacking. In this case, the final part of the switching algorithm to be implemented for the method is also very simple. In the centre blocks per se it is necessary to make only a space switching connection, which can be done in only one specific way. In the last ST blocks the signals can be switched also only in one specific way in order for the signal to be routed correctly. For AU-4 and TU-3 signals, the first 18 columns of the STM-1 frame must be processed separately. In making the switching connectio the same principles as have been mentioned above can be observed. The invention is discussed in the following by means of examples with referenc to the accompanying drawing in which Figure 1 shows a 128 port digital cross connect unit that is implemented with TS'S'TS'S'T architecture; and Figure 2 shows a simplified view of the markings of the signals of the switching network. Shown in Figure 1 is a TS'S'TS'ST switching network for AU-4 signals, in which there are 128 inputs and 128 outputs and in which an algorithm in accordance with the invention is used. In the figure TSW means a Time S Witch and SSW means a Space SWitch. In Figure 1 the sidemost switch arrangements are essentially mirror images of each other. The analysis will focus on the input side (at the left in the figure) in which there are 16 time switches TSW, comprising 8 inputs and 8 outputs at any given time and which are connected to the first space switch stage SSW. Each space switch has 8 inputs and 16 outputs, at least one of which is routed to a space stage of the centre block. In the centre blocks the structure of the other space switch is 16*16, and its outputs are connected to a time stage 16*16. (Regarding this centremost time switch, the cross connect is symmetrical so that a total of 128 outputs are obtained from the 16 time switches in the output.) The outputs of the space switches of the centre block's output side are routed in each given case to each space switch of the output side. It is to be noted that in the example in Figure 1 the summed capacity of the centre blocks is double that of the capacity of the sidemost blocks. Accordingly, in the centre blocks, ie, in respect of the space- time-space switch blocks, it can be said that switch blocks 1-8 are active and blocks 9-16 are extra blocks that are used to handle blocking situations as well as for the formation of new signals, which is examined in greater detail in the example given below. This TS'S'TS'ST architecture shown in Figure 1 is a modified reconfigurable Clos structure. In this case "modified" means that the conventional TST architecture has been extended: a) by placing time and space stages in the middle of the switch and b) by adding 8 blocks to the centremost stage. The first modification (a) enables blocking to be eliminated, or to be more exact, in this manner blocking is theoretically made highly improbable already without the second modification. This small probability is completely eliminated by means of the second modification (b). The second modification is needed primarily to speed up the operation of the TS'S'TS'ST switch, because in especially difficult cases, solution of the TS'S'TS'ST algorithm may require a very long time, in practice 2-30 s with state-of-the-art equipment. In normal cases the extra blocks guarantee that free channels are also available for new bidirectional signals. When the signals have been configured, the TS'S'TS'ST algorithm is solved so that there again remain 8 empty blocks. Figure 2 shows, for purposes of illustration, a simplified example of the markings of the signals to be processed when the switching network has 3 input blocks, in each of which there are 3 input ports. There are thus nine input signals and they have two time slots in use in the example shown in Figure 2. I the figure, two numbers are marked for each input signal, the first of the numbers indicating the desired port number for the input signal and the second indicating the desired time slot of the signal leaving the output port. If two signals are going to the same time slot, these signals are copied to the outputs as a broadcast. Signal selections are required for the purpose of route backup, ie, protection; in Figure 2 the marking signal selection (6.1; 3.2) is used. This means that two input signals can be going to a time slot of the same output port. In this case, one of these signals is selected in the space switch. The signals selected should be located in the same input block. In the following, the method in accordance with the invention is analysed in greater detail. In a manner that is essential for the invention, in the time and space switches of the input side, the signals are arranged in such a way that the SSW-TSW-SSW signals in the output, which come to an STS block of the centre stage, obey the rules: the number of signals coming to the STS block, which go to an STS block of the output side (SSW-TSW), must not exceed the number of the time slots, which is 63. In addition, the number of signals going from the TS block of the input side to the STS block cannot exceed the capacity of the AU-4 signal. For this reason, the plain AU-4 signals in the input ports must be routed first through the switch stages so that fast switching connections of the AU-4 signals are obtained. This means that in each given case it is most advantageous to route them via the same STS block. In addition, the following conditions are imposed upon the signals coming from the output ports of the space switches of the input side: the signals must be brought to a block of the centre stage such that they can reach the output side's ST block that has the correct TS'S'TS'ST structure; and only one time slot can be directed to the same output port simultaneously. These conditions are very simple and obvious. With them, it is possible to find quite many different alternatives for the outgoing signals. If it is not possible to find, by means of th switching algorithm that implements the method, a suitable solution for a given signal via the active half of the centre stage, extra STS blocks of the central SSW-TSW-SSW stage must be utilized to form the connection. This means that in the architecture in accordance with the invention and using the algorithm according to the invention, difficult backtracking phases that eat up computational capacity are not required. If in a column, ie, in a time slot, there are several signals going to the same port, one or several of the signals can be routed via the extra blocks. According to the invention, the idea is to organize the signals in such a way that into the same STS block there cannot come more signals that belong to the same group than there are time slots in the block. The idea of the row numbering of the tables below is thus that the signals to be routed to the same STS block of the centre stage have the same row numbers. The signals going out from the TS blocks of the input side are organized first such that the above-mentioned conditions are fulfilled. Broadcasting, ie, copyin of the signals, is not done in the TS blocks of the input side having this TS'S'TS'ST structure, and accordingly broadcasting cannot cause blocking in these blocks. Copying operations are done most advantageously in the centre stage. Due to protections, selection of VC-12 signals could cause blocking, an this can be prevented, for example, by reorganizing the outgoing signals (repeating the arrangement several times) in the TS blocks of the input side if blocking appears to occur. A fan-out to the blocks of the centre stage is effected from the TS blocks of th input port. According to Figure 1 , the outputs of the state switches of the inpu stage are in each given case connected such that the uppermost output of the block is connected to the uppermost block of the centre stage, the second highest output to the second block of the centre stage, etc. Each block of the centre stage receives outputs of the previous state switch such that the uppermost input port of the uppermost block receives the uppermost output of the previous block, the second input port receives the second output of the previous block, etc. Since most broadcasts should be made in the STS blocks of the centre stage, i them should be found such solutions for outgoing signals as well assure switching without blocking. A simple rule for avoiding blocking could be that the same broadcast signal should go out from the STS blocks at the same time - ie, in the corresponding time slots. If blocking occurs in spite of this, the outgoing signals must be rearranged and this is repeated until unblocked switching is achieved. The switching solutions of the central stage are now relatively simple and straightforward because the arrangements of the signals according to the invention have been made in the time and space switches of the input side. Accordingly, in practice time switching is not required at all in the centre stage, but instead plain space switching is carried out in the blocks, as is shown by means of Tables 1-8 in the signal arrangement example given below. In the switch blocks SSW-TSW of the output side, first in the space switches SSW the signals at any given time are connected to the correct, ie, the desired output port TSW, which signals then arrange the time slots into the correct order to be sent out from the cross connect as the AU-4 signal required at any given time. In the following the basic concept of the TS'S'TS'ST algorithm and its application in practice are explained in greater detail in the light of the examples in Tables 1-8. Accordingly, in the situation in the example, the markings are those explained in connection with Figure 2, but now on the input side there are three switch blocks (TSW-SSW) which, for the sake of simplicity, have only three input ports and thus there are a total of 9 input ports. For purposes of illustration, there are only 6 time slots to be switched. In Tables 1-8 the rows correspond to ports and the columns to time slots. Extra switch blocks of the centre block (cf. blocks 1-16 in Figure 1) are not shown in the tables in order t make the discussion simpler. Table 1 shows, in simplified form, the signals coming to the switching networ According to the explanation in Figure 2, the signal in time slot one of port on (6,1) should be connected to output port 6 of the TS'S'TS'S'T switch and to time slot one in the output port. In can be seen that the incoming signals invol a number of cases in which the signal must be copied to several output ports. For example, the incoming signal in time slot one of port four (fourth row, fir column: 8.2/3,1/1,2) must be copied to the outputs 8/2, 3,1 and 1,2. The organization of the signals of the TS'S'TS'S'T switching arrangement in t input blocks forms the most difficult part of the algorithm according to the invention. The object of this invention is to give a more precise picture of the implementation of the algorithm in the input blocks and, more generally, also i the other blocks. The idea of the algorithm implementing the method according to the invention to move signals in the table below in the vertical direction, ie, in the same tim slot between the ports and/or blocks in such a way that no switch block gets more signals than there are time slots. The number of signals in a specific row of a specific input group must similarly be equal to or smaller than the number of time slots. Moves in the vertical direction can be continued in order to improve the situation until the conditions have been fulfilled. As a general guideline, the algorithm can be allowed to examine the situation block by bloc and to find out which of the signals to be moved give the most benefit. For example, a broadcast signal, ie, first arranging the signal that is to be copied t many output ports may give the most benefit. Subsequently, there are less signals to be moved in order to solve the problem. The analysis starts with the example situation in Table 1, in which signals are coming to the switching network. Table 1 6,1 6,2 6,3 6,4 6,5 6,6 4,1 1,1 2,1 5,1 8,1 4,2 / 2,2 7,1 7,2 7,3 7,4 7,5 7,6 8,2/3,1/1,2 9,1 / 4,3 8,3 1,3 1,4 1,5 / 3,2 8,4 3,3 / 8,5 2,3 1,6 5,2 4,4 / 5,3 9,2 2,4 / 9,3 2,5 9,4 4,5 9,5 5,4 2,6 8,6 9,6 3,4 / 5,5 5,6 3,5 3,6 / 4,6 The signals in Table 1 are organized in the first block, ie, the block of the input side, in which the idea is to organize the signals as far as possible in such a wa that one column does not contain two signals going to the same output port. When the problem of the TS block of the input side has been solved, the output of each signal is solved. Thereafter, routes can be sought separately inside each TS block. The problem to be solved is simple. The signals in the time switches must be organized in such a way that the column contains no more than one signal going to the same output port. Table 2 shows the arrangement of the signals after the first time switch. The signals in the space switch can then be switched to the desired port. In this case, selections are made only in the space switch. First, an example will illustrate the arrangement of the signals that takes place in the space switches. Table 2 6,1 6,2 6,3 6,4 6,5 6,6 2,1 1,1 4,1 5,1 8,1 4,2 / 2,2 7,1 7,2 7,3 7,4 7,5 7,6 8,2/3,1/1,2 9,1 / 4,3 1,3 8,3 (*) 1,4 1,5 / 3,2 3,3 / 8,5 8,4 2,3 1,6 5,2 2,5 2,4 / 9,3 9,2 4,4 / 5,3 9,4 4,5 9,5 5,4 2,6 9,6 8,6 5,6 3,5 3,6 / 4,6 3,4 / 5,5 Arranging of the signals must now be continued in the first space switch of the input side according to the same principle as in the time switch, ie, such that one column does not contain two signals going to the same port. Here, for each column a solution must be obtained separately for a situation such that to a given centre block there does not go more than one signal that goes to the same final block. If this cannot be accomplished completely, the unsolved signals are moved to the extra blocks. It can be seen that the signal in row 4, column 2 (*) cannot be processed by means of the active basic blocks of the centre stage according to the required conditions, whereby it is channelled into extra blocks, ie, into the doubled part of the centre block; this signal thus does not occur in the following Tables 3-5. Table 3 shows the situation after the first space switch, from which fan-out to the centre stage takes place. Table 3 6,1 6,2 6,3 6,4 6,5 6,6 2,1 1,1 7,3 5,1 8,1 4,2 / 2,2 7,1 7,2 4,1 7,4 7,5 7,6 8,2/3,1/1,2 1,4 1,6 8,3 1,5 / 3,2 3,3 / 8,5 (*) 8,4 2,3 9,5 2,4 / 9,3 9,2 9,6 9,4 ■ 4,5 5,6 5,4 2,6 8,6 5,2 2,5 3,5 3,6 / 4,6 4,4 / 5,3 3,4 / 5,5 In Table 3 it can be seen in row 6, column 2 that also this signal (*) must be routed to the extra centre blocks because via the basic blocks the conditions presented cannot be fulfilled; this signal thus does not occur in the following Tables 4-8. On the basis of Figure 1 we see that the outputs of the space switches have been switched in each given case in such a way that the uppermost output of the block (row 1 , row 4, row 7) in each given case is switched to the first block of the centre stage, the second highest output (row 2 row 5, row 8) in each given case to the second block of the centre stage etc. Each block of the centre stage receives outputs of the space switch in such a way that the highest row (input ports 1 , 4, 7) receives the highest output of the previous block, the second row (input ports 2, 5, 8) receives the second output of the previous block, etc. In this way the situation in the input ports of the centre blocks is made like that shown in Table 4, ie, the situation after fan-out. Table 4 6,1 6,2 6,3 6,4 6,5 6,6 8,2/3,1/1,2 2,1 1,4 1,6 9,5 2,4 / 9,3 9,2 9,6 9,4 2,1 1,1 7,3 5,1 8,1 4,1 / 2,2 1,3 8.3 1,5 / 3,2 4,5 5,6 5,4 2,6 8,6 7,1 7,2 4,1 7,4 7,5 7,6 8,4 2,3 5,2 2,5 3,5 3,6 / 4,6 4,4 / 5,3 3,4 / 5,5 Let us examine, by means of Table 4, the switching connections that are to be made in the first space stage of the centre block. Signal 6/1 (row 1 , column 1) is moved one row down because it is about to go to the centremost block (of which the output ports are 4-6) of the sidemost switches of the output side. Signal 8,2/3,1/1,2 (row 2, column 1) is first divided in two: first signal 8,2 is copied one row down on the same basis as signal 6/1 was above (the output por of signal 8,2 is in the third output block). A signal is also copied one row up, ie, 3,1/1,2 should come from the output ports that are located in the first output block (output ports 1-3). The same principle is applied to the other signals. The initial situation of the space switching connections made here is not presented separately. In the following time switch stage, no switching connections are made in this example. In the space switches of the output side of the centre blocks, some more space switching connections are made, so that Table 5 shows the situation after the centre blocks. Table 5 3,1 / 1,2 2,4 1,4 1,6 6,1 6,2 6,3 6,4 6,5 6,6 8,2 9,5 7,3 9,2 9,6 9,4 2,1 1,1 1,3 2,6 1,5 / 3,2 2,2 4,5 5,6 5,4 5,1 4,2 . 7,3 8,3 8,1 8,6 2,5 3,5 3,6 2,3 3,4 5,2 4,1 4,6 4,4 / 5,3 5,5 7,1 7,2 8,4 7,4 7,5 7,6 From the centre blocks the signals are fanned out in a fixed manner to the sidemost switches of the output side on the same principle as was explained in connection with the processing of the signals in Table 3. Table 6 presents the situation before the last two settings for the output side. Now, it must be recalled that the signals marked with an asterisk (*) were removed from Tables 2 and 3 and placed in extra blocks. They were processed there in the same way as was explained above in respect of the active blocks. I this way, the signals marked with an arrow (- > ) can also be processed, and time switching connections are still needed for them because they are located in the wrong time slots in this phase. Table 6 > 3,3 3,1 / 1,2 2,4 1,4 1,6 2,1 1,1 1,3 2,6 1,5 / 3,2 2,2 2,5 3,5 3,6 2,3 3,4 - > 4,3 6,1 6,2 6,3 6,4 6,5 6,6 4,5 5,6 5,4 5,1 4,2 5,2 4,1 4,6 4,4 / 5,3 5,5 ->9,1 -> 8,5 8,2 9,5 9,3 9,2 9,6 9,4 7,3 8,3 8,1 8,6 7,1 7,2 8,4 7,4 7,5 7,6 Table 7 shows the situation after the last space switches. Table 7 1,2 1,1 1,3 1,4 1,5 1,6 2,1 2,5 2,4 2,6 2,3 2,2 3,1 3,3 3,5 3,6 3,2 3,4 4,5 4,3 4,1 4,6 4,4 4,2 5,2 5,6 5,4 5,1 5,3 5,5 6,1 6,2 6,3 6,4 6,5 6,6 7,1 7,2 7,3 7,4 7,5 7,6 8,2 8,5 8,4 8,3 8,1 8,6 9,1 9,5 9,3 9,2 9,6 9,4 Table 8 finally shows the situation after the last time switches, ie, the output signals of the entire switching network in the example selected here. Table 8 1,1 1,2 1,3 1,4 1,5 1,6 2,1 2,2 2,3 2,4 2,5 2,6 3,1 3,2 3,3 3,4 3,5 3,6 4,1 4,2 4,3 4,4 4,5 4,6 5,1 5,2 5,3 5,4 5,5 5,6 6,1 6,2 6,3 6,4 6,5 6,6 7,1 7,2 7,3 7,4 7,5 7,6 8,1 8,2 8,3 8,4 8,5 8,6 9,1 9,2 9,3 9,4 9,5 9,6 In this context it should further be noted that the example shown in Tables 1-8 is greatly simplified for purposes of illustration. In practice, for example, in the case of the switching network shown in Figure 1, in which there are 128 inputs and outputs and 63 time slots, the switchings of the signals would have to be illustrated with tables having, in a corresponding fashion, 128 rows and 63 columns, ie, 8,064 signal cells. An illustrative representation of the real-life situation furthermore will grow significantly in size if, additionally, it is desired to show the switching situations of the "extra" blocks of the centre stages by means of corresponding tables. Although in the example above a situation was examined in which the number of input and output ports of the centre stage is double that of the input and output stages, it is known that a non-blocking network can be achieved in a general case in which the input stage has m TS blocks, the centre stage 2n-l STS blocks and the output stage n ST blocks if copyings are not made. It should be noted furthermore that the method and cross connect architecture presented do not limit the implementation to the model presented in the example, but instead the invention can be employed at all SDH levels. In addition, the switching mode can be used for the cross connect of both STM and other corresponding signals. Although the modular structure of the exampl is advantageous at the present moment, it does not of course limit the use of th invention with smaller of, especially, with larger modules. In this application no detailed discussion has been given of the algorithm implementing the method, which algorithm can be implemented with many methods known to one versed in the art. The algorithm can be employed advantageously in the computer controller of the cross connect equipment, whereby the algorithm related to the invention is characterized by what is state in the claims.

Claims: Claims 1. A method of switching SDH STM-N signals in a TS'S'TS'S'T switching network in which the capacity of the centre stage (SSW-TSW-SSW) is greater than the capacity of the input and output stages, whereby the centre blocks corresponding to the capacity of the input or output stages of the centre stage are called the active blocks and the other blocks are called extra blocks, characterized in that, a) a solution is obtained for the signals that travel via the time and space switches of the input side (TSW-SSW, on the left hand side in Figure 1) in such a way that al) in the same time slot of the outputs of the time switches (TSW) there is not more than one signal going to the same output port of the switching network; and a2) in the outputs of the space switches (SSW) there does not go to the same centre block of the centre stage more than one signal that is to be routed to the same output block (SSW-TSW); a3) whereby in the time switches and space switches, the signals that remained without a desired solution in phases al and a2 are routed via extra blocks of the centre stage to space-time switches of the output side, b) a solution is obtained for the signals that travel through the STS switch blocks (SSW-TSW-SSW) of the centre stage; and c) a solution is obtained for the signals that travel through the space and time switches of the output side (SSW-TSW, on the right hand side in Figure 1). 2. A method in accordance with claim 1, characterized in that phases al and a2 are repeated for the signals that are to be switched through the time-space switches of the input side (TSW-SSW) before carrying out phase a3, whereby when repeating phases al and a2 the number of the signals going to the same centre block of the centre stage and to the same space-time switch block of the output side must not exceed the number of time slots. 3. A method in accordance with claims 1 or 2, characterized in that in phases al and a2 the limitation set is that the number of signals coming from the same time-space block of the input side must not exceed the capacity of the AU-4 signal. 4. A method in accordance with any of the above claims, characterized in that in the method the processing is first done on the AU-4 signals in the ports of th input stages, which signals are routed through the switch stages in such a way that at any given time they are primarily routed via the space-time-space block of the centre stage (SSW-TSW-SSW1, 2, ...16). 5. A method in accordance with any of the above claims, characterized in that the switching operations of the broadcast signals are done in the space-time- space blocks of the centre stage (SSW-TSW-SSW) whereby the switching rule i that the broadcast signals are routed out from the space-time-space blocks (SSW-TSW-SSW) at the same instant, ie, in the corresponding time slots. 6. A method in accordance with any of the above claims, characterized in that the signals in the centre stages (SSW-TSW-SSW) are organized solely by means of the space switches (SSW).

Inventors: KASURINEN TIMO, OESTERGAARD PATRIC, KASURINEN, TIMO, OESTERGAARD, PATRIC
Applicants: KASURINEN TIMO, NOKIA TELECOMMUNICATIONS OY, OESTERGAARD PATRIC, KASURINEN, TIMO, OESTERGAARD, PATRIC
Application year: 1995
Main classification: H04Q11
IPC codes: H04Q3, H04Q11