Electrically programmable and erasable non-volatile memory cell and memory devices of FLASH and EEPROM type

Abstract: The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and missing from the second source diffusion. In addition to possessing the known advantages of p-channel EPROM cells such as low consumption and which are still more important in view of the typical applications of FLASH and EEPROM memories they are easier to integrate with MOS transistors of traditional logic circuits because their structure is more similar thereto.

Description: The present invention relates to a memory cell in accordance with the preamble of claim 1 and to FLASH and EEPROM memory devices in which this cell finds advantageous application. A very serious problem in the area of semiconductor memories is power consumption. The article of D. Cantarelli, A. Maurelli and L. Baldi, "A high-performance p-channel EPROM cell", ESSDERC 1987, Proceedings, pages 769-771, proposes a p-channel cell instead of an n-channel cell as in the well-established tradition for the manufacture of EPROM memory devices. This article underscores the various advantages of inversion of the type of conductivity of the elements making up the traditional structure of the EPROM memory cell among which that of low power consumption in the writing phase. In recent years electrically programmable and erasable non-volatile memories such as FLASH and EEPROM memories have spread widely and in particular for applications where low power consumption is a very important requisite. Applying the lesson of the above mentioned article to these types of memories, what is obtained is a new type of electrically programmable and erasable non-volatile memory cell whose cross section is shown in the annexed FIG. 1. But the gate oxide in this case is thinner to allow conduction by tunnel effect and can be 8nm to 9nm for EEPROM memories and 10nm to 12nm for FLASH memories. The memory cell of FIG. 1 consists of a double-gate MOS transistor and comprises a type-n zone 1, two p-type regions 2 and 3 implemented in the zone 1 and separated from each other by a spacing, and a double gate structure implemented over the zone 1 opposite the spacing. The double-gate structure comprises an insulated gate 5 and a connected gate 4 superimposed on and insulated from each other and inserted in a layer 6 of insulating material. The region 2 extends beneath the insulated gate 5. The space 9 of the region 2 bordering on the zone 1 is normally doped more lightly than the remaining space. FIG. 1 also shows two layers 7 and 8 of insulating material which leave two openings over the regions 2 and 3 respectively for optional contacts. This structure corresponds to one of traditional type such as, e.g. that illustrated in FIG. 7 of US patent no. 4,142,926 except for the type of conductivity of the constituting elements. As known, the space 9 is very important in the erasing phase of the cell to permit passage of charges from the insulated gate 5 to the region 2 corresponding to the source region of the MOS transistor. From US patent 4,203,158 is known a more sophisticated solution to this problem and which however implies again superimposing (more generally an approach) between the insulated gate and the source region. Implementation of this superimposition involves considerable complication in the production process in terms both of number of masks required and production time. Furthermore, at high integration levels, e.g. 0.5-1.0u technologies, the space 9 (which can be an extension of e.g. 0.15-0.3u beneath the insulated gate) considerably affects the minimal size of the cell. A process of this type and which also allows simultaneous manufacture of FLASH and EEPROM memory cells is illustrated in US patent 4,957,877. In laboratory tests it was noticed that unexpectedly in the case of an electrically programmable and erasable non-volatile memory cell this superimposition is superfluous because the channel formed during erasing of the cell underneath the insulated gate 5 ensures passage of sufficient charges between the insulated gate 5 and the region 2. A memory cell of known structure is disclosed in EP 0255489 which related to a non-volatile EPROM cell formed using a P-Channel MOS device. However, this kind of cell doesn't allow electrically erasing. A similar memory cell structure is also disclosed in the German patent application No. DE-A-2039955, which however required two different dielectric layers, and in another German patent No. DE-B-2636350, which relates to an N-Channel cell with no electrical erasing possibility. A further memory cell is disclosed in the Proceedings of the 3rd Conference on Solid State Devices, Tokyo 1971, at pages 155-162. This document relates to a read-write memory cell using avalanche breackdown at just one junction. A further prior art solution is disclosed in the US patent No. 4,267,558 which relates to an N-Channel Flash memory cell. The present invention therefore concerns an electrically programmable and erasable non-volatile memory cell having the characteristics set forth in claim 1. Further advantages are set forth in the dependent claims. In the light of the results of the tests performed it was sought to use a traditional cell structure and invert the type of conductivity of the constituting elements and to avoid the second source diffusion. In addition to possessing the known advantages of p-channel EPROM cells such as low consumption and which are still more important in view of the typical applications of FLASH and EEPROM memories they are easier to integrate with the MOS transistors of the traditional logic circuits because their structure is more similar thereto. Furthermore many of the known provisions of the manufacturing techniques for MOS transistors to reduce the intensity of the electrical field in the channel region and consequently the harmful effect of the "hot" electrons are advantageously applicable, e.g. the lightly doped drain (LDD) technique. Advantageously for manufacturing, the use of these provisions maintains the similarity of the cells and the transistors. In the case of the cells, a low intensity of the electrical field permits reduction of writing parasites from the drain region. A discussion of these problems and their possible solutions both as to structure and as to process is found in US patent no. 5,102,815. In accordance with another aspect the present invention concerns also FLASH and EPROM semiconductor memory devices having the characteristics set forth in claims 8 and 9 respectively. The invention is clarified by the description given below considered together with the annexed drawings wherein: FIG. 1 shows a cross section of a structure of a flash memory cell in accordance with the prior art, and FIG. 2 shows cross sections of a FLASH memory cell structure in accordance with the present invention. As shown in Fig. 1, one of the regions 2 and 3 exhibits internally an essentially uniform doping. In order to reduce the intensity of the electrical field in the channel region the regions 2 and 3 can have different doping profiles. A first possibility consists of providing that spaces of regions 2 and 3 bordering on the channel region which separates the regions 2 and 3 be doped more lightly. A second possibility corresponds to the invention and is shown in FIG. 2 and consists of providing that all the spaces 12 and 13 bordering on the zone 1 be doped more lightly. In the embodiment shown in FIG. 2 the regions 2 and 3 do not extend essentially beneath the insulated gate 5 since this would have no advantage. However, the extension of the regions 2 and 3 must be such that the channel formed under the insulated gate 5 connects these two regions. The p-channel transistors are characterized by the presence of a completely different mechanism for injection of electrons into the insulated gate and not requiring avalanche multiplication in the drain region and hence high electrical fields. The mechanism is linked to the fact that under strong saturation conditions the electrical field is very favorable to the injection of electrons into the gate and it is several orders of magnitude more efficient than that operating in the n-channel transistors and produces huge gate currents even at low drain currents. In particular, optimal injection conditions are had with the drain region at relatively high potential (less than-6V) and with the gate just over the threshold. It is then possible to obtain the same charge injected into the insulated gate with a much lower total drain charge and this involves small charge pump voltage raiser circuits and facilitates the implementation of integrated devices powered at low voltages. Furthermore, given the characteristics of the p-channel transistors, at no time during writing is there firing of an avalanche multiplication and therefore the substrate currents generated are negligible with considerable advantages for reliability and design flexibility because it is not necessary to ensure frequent substrate contacts and it is possible to operate the cell even in a process having n-type conductivity. Implantation of the source and drain regions is not necessarily self-aligning with the gate since it is not necessary to accentuate the avalanche multiplication. As it is not necessary to implement excessively high gate voltages the capacitive coupling between insulated gate and connected gate can be less that that of the n-channel cells and hence the extension of the so-called "tabs" in the "field" can be reduced. The "virgin" cell in accordance with the present invention has an intrinsically high threshold between approximately-1.2V and -1.4V with no need of additional implantation and especially if n-doped gates are used as in the standard CMOS technology. Writing is achieved by applying a high enough negative voltage on the drain (from -6V to -8V depending on the thickness of the tunnel oxide) and a voltage above the threshold of the connected gate. As the effectiveness of injection decreases rapidly for gate voltages much higher than the threshold the choice of the voltage applied to the connected gate is dictated only by reasons of consumption and noise. Erasing is achieved by applying to the connected gate a negative voltage between approximately -9V and -11V depending on the thickness of the tunnel oxide and keeping the source terminal grounded. This voltage sends the channel into conduction and hence the tunnel effect takes place towards all of the channel region and without voltage differences between the latter and the substrate and thus avoiding the band-to-band tunnelling phenomenon between the source region and the substrate typical of n-channel memory cells which is responsible for nearly all the erasing current and good reliability is ensured. Erasing takes the threshold voltage towards high positive values originating closing of the channel and is thus self-limiting and thus the over-erasing problems typical of n-channel memory cells are avoided. An EEPROM cell can be easily derived from the cell described by means of mere addition of a p-channel single-gate MOS transistor implemented in the zone 1 beside one of the regions 2 and 3. Normally it is arranged beside the drain region. As mentioned above, the cells described can be used arranged in a matrix, in FLASH EPROM and/or EEPROM memory devices. The present invention finds particular application in memory integrated devices powered with low voltage, e.g. 3V, for the above mentioned advantages of low consumption and ease of programming and erasing at low voltage. It is also noted that in addition to being an advantage in itself low consumption has a beneficial effect on the dimensions of voltage-raising circuits which are necessary for achieving writing and erasing voltages well above e.g. 3V and especially when it is necessary to raise voltage by a high factor, e.g. 3 to 4.

Claims: Electrically programmable and erasable memory cell consisting of a double-gate MOS transistor and comprising a zone (1) of n-type conductivity and two regions (2,3) of p-type conductivity implemented in said zone (1) and separated from each other by a spacing and a structure (4,5,6), said transistor comprising a double gate (4, 5) implemented over said zone (1) opposite said spacing, characterized in that both said two regions (2,3) are doped more lightly in the spaces (12, 13) bordering said zone (1). Cell in accordance with one of the above claims and characterized in that said structure (4,5,6) comprises at least one isolated gate (5) and that said two regions (2,3) essentially do not extend beneath said isolated gate (5). Cell in accordance with claim 1 and characterized in that said zone (1) belongs to a well having n-type conductivity. Cell in accordance with one of the above claims and comprising further another transistor of the p-channel single-gate MOS type and implemented in said zone (1) beside one of said two regions (2,3). Flash memory device comprising a cell matrix with memory cells in accordance with one of claims 1 to 4. EEPROM memory device comprising a cell matrix with memory cells in accordance with claim 5.

Inventors: BALDI LIVIO, PARUZZI PAOLA, BALDI, LIVIO, PARUZZI, PAOLA
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1995
Main classification: H01L29
IPC codes: H01L21, H01L29, H01L27