Spread spectrum receiving apparatus

Abstract: A receiving apparatus includes a base-band conversion circuit, a synchronizing circuit/code generator and a demodulator. The base-band conversion circuit converts a received signal into a base-band signal. The synchronizing circuit/code generator detects a spread code included in the received signal to generate a plurality of spread codes in synchronization with the spread code included in the received signal. The demodulator uses the plurality of spread codes supplied by the synchronizing circuit/code generator to demodulate the base-band signal.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a receiving apparatus for receiving a spread spectrum signal, specifically a multi-code spread spectrum signal. Related Background Art A spread spectrum communication system employing a direct sequence spread method is a method of generating, from a base-band signal of a digital signal to be transmitted, a base-band signal having a significantly wide band width with respect to original data. This is accomplished by using a spread code sequence, such as a pseudo noise code (a PN code). Furthermore, modulation, such as PSK (Phase Shift Keying) or FSK (Frequency Shift Keying), is performed to convert the base-band signal into an RF (Radio Frequency) signal so as to transmit the RF signal. A receiver unit uses the same spread code as that used in a transmitter unit to perform a despread operation to perform correlation with the received signal so as to convert the received signal into a narrow-band signal having a band width that corresponds to the original data. Then, a normal data demodulation is performed so that the original data is reproduced. Since the spread spectrum communication system employs a significantly wide transmission band width with respect to the information band width as described above, the foregoing system cannot realize an unsatisfactorily low transmission speed as compared with a typical narrow band width modulation system if the transmission band width is within a certain condition. To overcome the foregoing problem, a multi-code method has been employed. The foregoing method includes the steps of converting a high-speed information signal into low-speed parallel data, spread- modulating the parallel data in different spread code sequences so as to add data, and converting the data into an RF signal that is then transmitted, so that high speed data transmission is realized under a predetermined condition of the transmission band width without deterioration in the spread rate in the spread modulation. Fig. 24 shows the structure of a transmission mechanism adapted to the foregoing method. Supplied data is converted into n parallel data items by a serial-parallel converter 301. Each converted data is, by a multiplier group consisting of n multipliers 302-1 to 302-n, multiplied by n different spread code outputs from a spread-code generator 303 so as to be converted into wide band spread signals over n channels. Then, the outputs from the respective multipliers are added by an adder 304 so as to be provided to a high-frequency transmitter stage 305. The added wide spread base-band signals are, by the high-frequency transmitter stage 305, converted into a transmission frequency signal having an appropriate central frequency so as to be transmitted by a transmission antenna 306. Fig. 25 shows the structure of a receiver. The signal received by an antenna 401 is appropriately filtered and amplified by a high-frequency signal processor 402 so as to be converted into a signal having an intermediate frequency. The intermediate-frequency signal is distributed to n channels connected in parallel to correspond to the spread codes. In each channel, the correlation of the input signal with outputs from spread code generator group 404-1 to 404-n is detected in correlator group 403-1 to 403-n so as to be despread, the spread code generator group 404-1 to 404-n corresponding to the channels of the correlator group 403-1 to 403-n. Synchronization of the despread signal is established at each channel in synchronizing circuit group 405-1 to 405-n so that the code phases and clocks of the spread code generators are made to coincide with one another. The despread signals are also demodulated in demodulator group 406-1 to 406-n so that data is reproduced. Then, reproduced data is converted into serial data in serializer 407 so that the original information is reproduced. However, since the correlator at each demodulation channel acts as the intermediate frequency stage, the conventional structure suffers from a problem in that the size of the circuit cannot be reduced. SUMMARY OF THE INVENTION An object of the present invention is to reduce the size of a structure required for receiving a multi-code spread spectrum signal. Another object of the present invention is to accurately receive a multi-code spread spectrum signal. Another object of the present invention is to accurately synchronize a multi-code spread spectrum signal. Another object of the present invention is to realize high-speed communication. Another object of the present invention is to provide a spread spectrum signal receiving apparatus for, and a method of converting a received signal into a base-band signal, detecting a spread code from the base-band signal, and demodulating the base-band signal on the basis of a plurality of spread codes in synchronization with the detection of the spread code. The invention proposes a receiving apparatus for receiving a multi-code spread spectrum signal, said receiving apparatus comprising first conversion means for converting a first received signal into a second received signal in a base-band frequency; detection means for detecting a spread code included in the second received signal in the base-band frequency; and demodulating means for demodulating the second received signal modulated by a plurality of spread codes, characterized by second conversion means for converting the second received signal into a first digital signal at a first sampling frequency, and third conversion means for converting the first digital signal into a second digital signal corresponding to a second sampling frequency lower than the first sampling frequency, and said detection means is operable to detect the spread code from the first digital signal sampled at the first sampling frequency, and said demodulating means is operable to demodulate the second digital signal sampled at the second sampling frequency. The detection means may comprise control means for controlling a sampling clock having the first sampling frequency, and the second conversion means may be operable to convert the second received signal into the first digital signal by the sampling clock. According to a possible embodiment, the first conversion means is operable to convert the first received signal into the second received signal and a third received signal having different phases and in the base-band frequency, the second conversion means is operable to convert the second received signal into the first digital signal and the third received signal into a third digital signal at the first sampling frequency, the detection means comprises first correlation means for correlating the first digital signal and the spread code; second correlation means for correlating the third digital signal and the spread code; synthesis means for synthesizing a first output from said first correlation means and a second output from said second correlation means; and control means, which inputs an output from said synthesis means, for controlling a sampling clock having the first sampling frequency, and the second conversion means is operable to convert the second received signal into the first digital signal and the third received signal into the third digital signal by the sampling clock. The first conversion means may comprise reproduction means for reproducing a carrier of the first received signal. In a corresponding manner, the invention proposes a method of receiving a multi-code spread spectrum signal, said method comprising: a first conversion step of converting a first received signal into a second received signal in a base-band frequency; a detection step of detecting a spread code included in the second received signal in the base-band frequency; and a demodulating step of demodulating the second received signal modulated by a plurality of spread codes, characterized by a second conversion step of converting the second received signal into a first digital signal at a first sampling frequency, and a third conversion step of converting the first digital signal into a second digital signal corresponding to a second sampling frequency lower than the first sampling frequency, and said detection step detects the spread code from the first digital signal sampled at the first sampling frequency, and said demodulating step demodulates the second digital signal sampled at the second sampling frequency. The detection step may comprise a control step of controlling a sampling clock having the first sampling frequency, and the second conversion step may convert the second received signal into the first digital signal by the sampling clock. According to a possible embodiment, the first conversion step converts the first received signal into the second received signal and a third received signal having different phases and in the base-band frequency, the second conversion step converts the second received signal into the first digital signal and the third received signal into a third digital signal at the first sampling frequency, the detection step comprises a first correlation step of correlating the first digital signal and the spread code; a second correlation step of correlating the third digital signal and the spread code; a synthesis step of synthesizing a first output from said first correlation step and a second output from said second correlation step; and a control step, which inputs and output from said synthesis means, of controlling a sampling clock having the first sampling frequency, and the second conversion step converts the second received signal into the first digital signal and the third received signal into the third digital signal by the sampling clock. The first conversion step may comprise a reproduction step of reproducing a carrier of the first received signal. Other and further objects, features and advantages of the invention will be evident from the following detailed description of the preferred embodiments taken in conjunction with the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram for understanding the invention showing the structure of a receiving apparatus in which synchronization with a quasi-base-band signal is established; Fig. 2 is a circuit diagram of the quasi-base-band conversion circuit 6A of Fig. 1; Figs. 3A and 3B are circuit diagrams of synchronizing circuits comprising a sliding correlator and a delay locked loop circuit; Fig. 4 is a circuit diagram of the demodulator 7A of Fig. 1, formed by an analog circuit; Fig. 5 is another circuit diagram of the demodulator 7A of Fig. 1 formed by a digital circuit; Fig. 6 is a circuit diagram of a correlator 713-1 through 713-n of Fig. 5; Fig. 7 is a further circuit diagram of the demodulator 7A of Fig. 1, which is adapted to a case where despreading is performed after phase correction; Figs. 8A and 8B, when taken together as shown in Fig. 8 show the structure of a first embodiment of the present invention in which synchronization with a quasi-base-band signal is established; Figs. 9A-9D are respective circuit diagrams of circuits which may be used as the synthesizing circuit 17 of Fig. 8B; Figs. 10A-10C are waveform graphs showing the outputs from the synthesizing circuit 17, the delay circuit 18 and the subtraction circuit 19 shown in Fig. 8B; Figs. 11A and 11B are circuit diagrams of circuits which may be used as the clock control circuit 20 of Fig. 8B; Fig. 12 is a circuit diagram of the correlators 15 and 16 of Fig. 8B; Fig. 13 is a circuit diagram of a correlator which may be used as the correlators 23-1 through 23-n of Fig. 8B; Fig. 14 is a circuit diagram showing a modification of the clock output circuit 200 of Fig. 8B; Fig. 15 is a waveform graph showing the output from the synthesizing circuit 17 shown in Fig. 14; Fig. 16 is a circuit diagram of the phase shifting circuit 20H of Fig. 14; Fig. 17 is a diagram for understanding the invention showing the structure of a receiving apparatus in which synchronization with a base-band signal is established; Fig. 18 is a circuit diagram of the carrier reproducing circuit 5 of Fig. 17; Fig. 19 is a diagram for understanding the invention showing the structure of a receiving apparatus which includes a costas loop; Fig. 20 is a circuit diagram of the costas loop 51 of Fig. 19; Fig. 21 is a diagram for understanding the invention showing the structure of a receiving apparatus which is adapted to orthogonal modulation; Fig. 22 is a diagram showing the structure of the base-band conversion circuit 6B of Fig. 21; Figs. 23A and 23B when taken together as shown in Fig. 23 are diagrams showing the structure of a second embodiment of the present invention in which synchronization with a base-band signal is established; Fig. 24 is a diagram showing the structure of a transmission system of the related art; and Fig. 25 is a diagram showing the structure of a transmission system of the related art. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 is a diagram showing the structure of a receiving apparatus which eases understanding of the present invention. Referring to Fig. 1, reference numeral 1 represents an antenna, 2 represents a high-frequency signal processor for processing, at a high frequency stage thereof, the signal received by the antenna 1, 4B represents a synchronizing circuit for capturing and maintaining synchronization with the code and clock for the transmission unit; and a code generator for generating n spread codes for demodulating data and spread codes for synchronization from a code synchronizing signal and a clock signal, 6A represents a quasi-base-band conversion circuit for converting the received signal into a quasi-base-band signal, 7A represents a demodulator that uses the quasi-base-band signal transmitted from the quasi-base-band conversion circuit 6A and n spread codes transmitted from the code generator 4B to demodulate data, and 8 represents a parallel/serial conversion circuit for converting n parallel data items into serial data. Referring to Fig. 1, the signal received by the antenna 1 is supplied to the high-frequency signal processor 2. The high-frequency signal processor 2 comprises, for example, an amplifier, a filter and a frequency conversion circuit. Thus, the received signal is, in the high-frequency signal processor 2, appropriately amplified and filtered so that the high frequency component of the received signal is maintained as it is, or the same is converted into an intermediate frequency. The output from the high-frequency signal processor 2 is converted into a quasi-base-band signal by the quasi-base-band conversion circuit 6A. Fig. 2 shows an example of the quasi-base-band conversion circuit 6A. The signal supplied from the high-frequency signal processor 2 is branched into two sections that are then received by multipliers 202 and 203. The multiplier 202 is also supplied with the output from a local oscillator 201 which generates a signal having a frequency that is substantially the same as the central frequency of the signal transmitted from the high-frequency signal processor 2, so that the in-phase component (Ich) is extracted by a low-pass filter 205. The multiplier 203 is also supplied with the output from the local oscillator 201, the phase of the output being converted by an angular degree of 90° by a phase converter 204 before the output is supplied to the multiplier 203 so that the orthogonal component (Qch) is extracted by a low-pass filter 206. The quasi-base-band signal transmitted from the quasi-base-band conversion circuit 6A is supplied to the synchronizing circuit/code generator 4B and the demodulator 7A. The synchronizing circuit/code generator 4B uses a spread code PNr for synchronization to establish the synchronization of the code and clock with respect to those of the transmitted signal so as to transmit a code synchronizing signal and a clock signal. As the spread code PNr for synchronization, it is preferable that a code corresponding to one of a plurality of multiplex codes PN 1 to PNn is used. A code for only synchronization may be employed. The synchronizing circuit/code generator 4B can be formed by using a sliding correlator and a delay locked loop circuit, as shown in Figs. 3A and 3B. Referring to Fig. 3A, multipliers 2431I and 2431Q multiply a synchronizing spread code PNr supplied from a code generator 2436 with data in the channels Ich and Qch. The code generator 2436 generates a spread code PNr in accordance with the clock having substantially the same frequency as that of the transmission-side spread code. Integrators 2432I and 2432Q integrate the outputs from multipliers 2431I and 2431Q for one period of the spread code PNr. A synthesizing circuit 2433 synthesizes the outputs from the integrators 2432I and 2432Q. The synthesizing circuit 2433 squares the outputs from the integrators 2432I and 2432Q to add the foregoing outputs or obtain the square root of the result of the addition. As an alternative to this, the absolute values of the outputs from the integrators 2432I and 2432Q may be added, or either of the outputs from the integrators 2432I or 2432Q may be selected. A peak detection circuit 2434 detects the peak of the output from the synthesizing circuit 2433. A discriminator 2435 instructs the code generator 2436 to shift the code if no peak has been detected by the peak detection circuit 2434. Referring to Fig. 3B, reference numeral 2455 represents a shift register type code generator. When a clock is supplied from a VCO 2454, data in a leading bit (the m-th bit) is transmitted to a delay circuit 2456 and multipliers 2449I and 2449Q, and is also transferred to a final bit (the first bit) of the shift register. Data in the (m-1)th bit of the shift register is transmitted to multipliers 2448I and 2448Q, and is also shifted to the m-th bit of the shift register. Data in the m-2 th bit, that in the m-3 th bit,..., data in the first bit of the shift register are respectively shifted to the left by one. The multipliers 2448I and 2448Q multiply data in the m-1 th bit and data in the channels Ich and Qch, while the multipliers 2449I and 2449Q multiply data in the m-th bit and data in the channels Ich and Qch. Integrators 2450I, 2450Q, 2451I and 2451Q integrate the outputs from the multipliers 2448I, 2448Q, 2449I and 2449Q for one period of the spread code PNr. A synthesizing circuit 2452A synthesizes the outputs from the integrators 2450I and 2450Q, while the synthesizing circuit 2452B synthesizes the outputs from the integrators 2451I and 2451Q. A subtractor/amplifier 2453 transmits a signal that corresponds to the difference between the output from the synthesizing circuit 2452A and that from the synthesizing circuit 2452B. A voltage control oscillator (VCO) 2454 oscillates at a frequency that corresponds to the output from the subtractor/amplifier 2453. The delay circuit 2456 delays the output of the m-th bit from the code generator 2455 by a half clock for transmission. The code generator 4B transmits, to the demodulator 7A, n spread codes PN 1 to PN n for demodulation in synchronization with the output from the delay circuit 2456. Quasi-base-band signals in the channels Ich and Qch transmitted from the quasi-base-band conversion circuit 6A are, together with the n spread codes PN1,..., PNn for demodulating data transmitted from the code generator 4B, supplied to the demodulator 7A so as to be correlated with each spread code for demodulating data so that n data items are demodulated. Fig. 4 shows a first example of the demodulator 7A. Signals in the channels Ich and Qch are respectively branched into n pieces so as to be supplied to multipliers 701-1 to 701-n and multipliers 702-1 to 702-n. The multipliers 701-1 to 701-n and multipliers 702-1 to 702-n are respectively supplied with the spread codes PN1,..., PNn so that the signals in the respective channels and the spread codes are multiplied. The outputs from the multipliers 701-1 to 701-n are respectively filtered by low-pass filters 703-1 to 703-n so that the correlation is detected by the respective spread codes so as to be despread. Similarly, the outputs from the multipliers 702-1 to 702-n are respectively filtered by low-pass filters 704-1 to 704-n so that the correlation is detected by the respective spread codes so as to be despread. Both signals in the channels Ich and Qch, which are despread by the same spread code, are supplied to discriminators 705-1 to 705-n so that data is discriminated and, thus, parallel demodulated data is obtained. As the discriminators, delay wave-detectors or the like may be employed that perform the discrimination by performing a comparison of the phase of a given signal with the phase of the immediately prior signal. N parallel outputs from the demodulator 7A are, by the parallel/serial conversion circuit 8, converted into serial data for transmission. Fig. 5 shows a second example of the demodulator 7A. The apparatus shown in Fig. 5 has a structure such that a reproducing clock and a code phase synchronizing signal are supplied to the demodulator 7A from the synchronizing circuit/code generator 4B. The reproducing clock is in a form delayed by a half clock from the output of the VCO 2454 shown in Fig. 3B. The code phase synchronizing signal is a signal that is transmitted at every period after a half clock from the code start in the code generator 2455. Referring to Fig. 5, the supplied signals in the channels Ich and Qch are converted into digital signals, each having a resolving power of a single bit or a plurality of bits, by A/D converters 711 and 712, the basic period of which is the same as the reproducing clock. The digital signal is distributed into n branches so as to be supplied, together with a plurality of spread codes transmitted by the code generator 4B, to the correlators 713-1 to 713-n and correlators 714-1 to 714-n so that their correlations are calculated. Fig. 6 shows an example of the structure of the correlators 713 and 714. Referring to Fig. 6, the uppermost bit MSB (code bit) of a single bit or multiple-bit digital signal transmitted by the A/D converter 711 or 712 is, in an exclusive OR circuit 901, subjected to a calculation for obtaining an exclusive OR with a plurality of spread codes transmitted from the code generator 4B, and is supplied to an adder 902 together with the other bits. In the adder 902, the supplied signal and the output from a register 903 are added at each reproducing clock so as to be respectively transmitted to the register 903. The register 903 is reset simultaneously with the input of each spread signal, and the results of the addition of the received signals and the spread codes are stored for one period of the spread code. Therefore, when the final bit in one period of the spread code has been supplied, the correlation value of the spread code for one period and the received signal are stored. Data of the foregoing correlation value is discriminated by ensuing discrimination circuits 715-1 to 715-n (Fig. 7) so that n demodulated data items are obtained. N demodulated parallel data items are converted into serial data by a serializer 8. Fig. 7 shows a third example of the demodulator 7A. Referring to Fig. 7, the supplied signals in the channels Ich and Qch are, in the A/D converters 711 and 712 the basic period of which is the reproducing clock, converted into digital signals each having a resolving power of a single bit or multiple bits. The quantity of the phase shift of the digital signal from the phase of zero degrees is detected by a phase detection circuit 717, and is then supplied to a phase correction circuit 716. In accordance with the quantity of the phase shift, data in the channels Ich and Qch is converted into data modulated by zero degrees to 180 degrees. The output from the phase correction circuit 716 is distributed into n branches so as to be supplied to the correlators 713-1 to 713-n together with a plurality of spread codes transmitted from the code generator 4B so that their correlations are calculated.Data of the correlation values is discriminated in the ensuing discrimination circuits 715-1 to 715-n so that n demodulated data items are obtained. In the foregoing first example, the output from the demodulation circuit is converted into series data by the parallel/serial conversion circuit. However, the parallel/serial conversion circuit may be omitted and the output may therefore be transmitted as a plurality of parallel data items. In the first example, signals in the channels Ich and Qch that have been orthogonally converted are synthesized to discriminate one received data item. Therefore, received data can accurately be discriminated even if the conversion into the quasi-base-band signal has not been performed accurately. The foregoing effect is similar to the following embodiments. Figs. 8A and 8B show the structure of a first embodiment of the receiving apparatus according to the present invention. Referring to Figs. 8A and 8B, reference numeral 1 represents an antenna, and 2 represents a high-frequency signal processor. Reference numeral 6A represents a conversion circuit for converting the received signal into a quasi-base-band signal, the conversion circuit 6A having the same structure as that shown in Fig. 2. Reference numeral 7B represents a demodulator. Reference numerals 13 and 14 represent A/D converters, 200 represents a clock output circuit, 15 and 16 represent correlators for establishing the correlations with desired spread code PNr, 17 represents a synthesizing circuit for synthesizing the correlated outputs from the two correlators 15 and 16, 18 represents a delay circuit for delaying, by a predetermined time (the time corresponding to about one to two chips (bits) of the spread code), the output from the synthesizing circuit 17, 19 represents a subtraction circuit for subtracting the output from the synthesizing circuit 17 and that from the delay circuit 18, and 20 represents a clock control circuit that receives the output from the subtraction circuit 19 to control the phases of sampling clocks to be supplied to the A/D converters 13 and 14. Reference numerals 23-1 to 23-n represent correlators for establishing the correlation among the input signal and the spread codes PN1 to PNn. Reference numeral 24-1 to 24-n represent data discrimination circuits, and 25 represents a peak detection circuit for detecting the peak of the output from the synthesizing circuit 17. Referring to Figs. 8A and 8B, the operation of the apparatus according to this embodiment will now be described. Received signal r(t)·exp(iωt) is subjected to amplification and filtering in the high-frequency signal processor 2, and therefore has the input frequency converted into an intermediate frequency which is branched into two pieces so as to be respectively supplied to a first frequency converter 202 and a second frequency converter 203 so that signals r 1 (t) and r Q (t) in the base band region and orthogonal to each other are transmitted. Assuming that the phase difference between the received signal and the output signal from the oscillator 201 is α, the two signals are expressed as follows: r 1 (t) = r(t) cos α r Q (t) = r(t) sin α Then, the signals r 1 (t) and r Q (t) in the base band region are sampled at a frequency that is two times or higher than the chip speed of the spread code by the A/D converters 13 and 14 so as to be supplied to the correlators 15 and 16, in which correlation-calculations with a desired spread code PNr are performed. The desired spread code PNr is usually the same as the spread code for use in the spread modulation in the transmission unit, that is, the same as any one of PN1 to PNn or the code for only synchronization. Assuming that the outputs from the correlators 15 and 16 are respectively c 1 (t) and c Q (t), the outputs are expressed as follows: c 1 (t) = c(t)cos α c Q (t) = c(t)sin α where c(t) is the output when signal r(t) is supplied to the correlators 15 and 16. The outputs c 1 (t) and c Q (t) from the two correlators 15 and 16 are synthesized in the synthesizing circuit 17. One example of the synthesizing circuit 17 is shown in Fig. 9A. Referring to Fig. 9A, the outputs c 1 (t) and c Q (t) from the two correlators 15 and 16 are respectively squared, added and then the square root is taken. As a result of the calculation for obtaining the square root, the absolute value of c(t) can be obtained. Other examples of the synthesizing circuit 17 are shown in Figs. 9B, 9C and 9D. In Fig. 9B, the calculation for obtaining the square root shown in Fig. 9A is omitted to reduce the number of calculations. In Fig. 9C, calculations for obtaining the absolute value are performed in place of the calculations for obtaining the square root so that the number of calculations are further reduced as compared with the structure shown in Fig. 9B. In Fig. 9D, a selector for selecting either of the two signals is provided in place of performing the addition so that the number of calculations is still further reduced as compared with the structure shown in Fig. 9C. The output from the synthesizing circuit 17 is branched into two pieces so that subtraction of the signal allowed to pass through the delay circuit 18 from the signal that is not allowed to pass through the delay circuit 18 is performed in the subtraction circuit 19. Referring to Figs. 10A-10C, the operation will now be described in detail. Figs. 10A-10C show an example in which 2 samples per chip (bit) is performed and the quantity of delay of the delay circuit 18 is 1 chip, that is, 2 samples, and black dots show the sampling points. Dashed lines indicate the analog quantities, that is, the case where the sampling frequency is infinite. In a case where the phase of the sampling clock is delayed as shown in Fig. 10A, the quantity of delay from point t 0 , at which the output from the synthesizing circuit 17 is made maximum in one period to the half of the delay circuit 18, that is, the output from the subtraction circuit 19 at point t 1 after 1/2 bit (1 sampling) is negative. In a case where the phase of the sampling clock is ahead as shown in Fig. 10B, the output from the subtraction circuit 19 at point t 1 is positive. Furthermore, since the level of the output indicates the degree of the shift, control is performed so that the output from the subtraction circuit 19 at point t 1 approaches zero, which enables the clock phase to be synchronized. Accordingly, the output from the subtraction circuit 19 is received at point t 1 (that is, the time (detected by a peak detection circuit 25) at which the maximum value in one period of the output from the synthesizing circuit 19 is given to the time after the half of the quantity of delay of the delay circuit 18), and the phase of the sampling clock is controlled by the clock control circuit 20 so that the clocks are synchronized. The clock control circuit 20, as shown in Fig. 11A, comprises, for example, a delay circuit 20A, a latch 20B, a filter 20C, a digital/analog (D/A) converter 20D and a voltage control oscillator (VCO) 20E. The order of the filter 20C and the digital/analog (D/A) converter 20D may be changed. Another example of the clock control circuit 20 may be employed, as shown in Fig. 11B, in which the phase of the signal transmitted from a reference signal generator 20F is shifted by the output from the subtraction circuit 19 so as to transmit it as clocks. The delay time realized by the delay circuit 20A is half of the delay time realized by the delay circuit 18. The latch 20B latches the output from the subtraction circuit 19 when the delay time realized by the delay circuit 20A has passed from the peak of the output from the synthesizing circuit 17. The clock control circuit 20 controls the clocks so as to reduce the output from the latch 20B. In this embodiment, if synchronization has been established, the outputs from the two A/D converters 13 and 14 (Fig. 8A) are thinned ( i . e . decimated) to 1 sample per chip (bit) by a thinning/synthesizing circuit 22 so that the phase difference α between the received signal and the output signal from the oscillator is corrected. The synthesis is performed similarly to that performed by the phase correction circuit 716 shown in Fig. 7 such that calculation r 1 (t)cos α + r Q (t)sin α is performed. The output from the thinning/synthesizing circuit 22 is branched into n pieces so that correlation with n different spread codes PN1 to PNn used in the spread demodulation in the transmission unit is established in n correlators 23-1 to 23-n, followed by being respectively demodulated by data discrimination circuits 24-1 and 24-n so that n demodulated data items are obtained. The data discrimination circuits 24-1 to 24-n discriminate data for each period of the spread code in synchronization with the peak detected by the peak detection circuit 25. As a result of the structure according to this embodiment, the shift of the sampling clock can be corrected by a small-size structure. Furthermore, since the thinning/synthesizing circuit 22 thins ( i.e. decimates) data to 1 sample per chip (bit), the size of each of the ensuing n correlators 23-1 to 23-n can be reduced. In this embodiment, the serial-parallel converter for converting high-speed data into a plurality of parallel data items is added to the transmission unit, and the serializer for converting a plurality of demodulated parallel data items into serial data is added to the receiving unit. Thus, data can be transmitted at high speed. In this embodiment, information can be transmitted by orthogonal modulation. If orthogonal modulation is performed, information is converted into an orthogonal signal, the phase difference α of which has been corrected by the thinning/synthesizing circuit 22, so as to establish the correlation in the n correlators so that the data is discriminated. Fig. 12 shows the structure of the correlators 15 and 16 for use in the case of 2 samples per chip (bit). If the spread code is m bits long, a shift register 15A is a 2 x m bits long shift register that shifts, by each bit, the outputs from the A/D converters 13 and 14 in synchronization with the clock CLK supplied from the clock control circuit 20. The correlators 15 and 16 further comprise 2 x m multipliers 15B for multiplying data stored in the shift register 15A and each bit of the spread code (a 1 , a 2 , a 3 , ..., a m ); and an adder 15C for adding the outputs from the multipliers 15B so as to transmit the added outputs as correlated values. Fig. 13 shows the structure of the correlators 23-1 to 23-n (Fig. 8B). Reference numeral 23A represents a m-bit shift register, 23B represents m multipliers for multiplying data stored in the shift register 23A and each bit of the spread codes (a 1 , a 2 , a 3 ,..., a m ), and 23C represents an adder for adding the outputs from the multiplier 23B to transmit the result as a correlated value. The adder 23C, at each period of the spread code, transmits the result of the addition in accordance with the peak detection performed by the peak detection circuit 25. The correlators 23-1 to 23-n respectively receive different spread codes, whereas the correlators 15 and 16 receive the same spread code. The structure of the correlators 23-1 to 23-n may be structured as shown in Fig. 6. Note that the correlators 15 and 16 use the output clock CLK supplied from the clock control circuit 20 to perform calculations for establishing the correlation. That is, assuming that the frequency of the output clock from the clock control circuit 20 is f c , the correlators 15 and 16 perform the calculations for establishing the correlations in synchronization with the clock CLK having the frequency f c . The correlators 23-1 to 23-n use clocks obtained by halving the frequency of the output clock CLK from the clock control circuit 20 to perform the calculations for establishing the correlations. That is, the correlators 23-1 to 23-n perform the calculations for establishing the correlations in synchronization with the clock whose frequency is half (if l samples per chip (bit) are employed, 1/ℓ) of the frequency f c . Note that the clocks to be supplied to the correlators 23-1 to 23-n are generated by dividing the output clock frequencies from the clock control circuit 20 so that the correlation calculation is performed when the peak is generated in the output from the synthesizing circuit 17 (at time t 0 shown in Fig. 10C). The thinning/synthesizing circuit 22 thins (i.e. decimates) and synthesizes the outputs from the A/D converters 13 and 14 to 1 sample/clock period so as to cause the outputs from the A/D converters 13 and 14 to be transmitted while being synthesized when the peak is generated in the output from the synthesizing circuit 17. As described above, since the clock frequencies of the despreading correlators 23-1 to 23-n are made lower than the clock frequencies of the correlators 15 and 16 for correctly sampling the received signal, sampling can be performed accurately and despreading can be realized by a small-size structure. It is preferable that the quantity of delay realized by the delay circuit 18 is the time that corresponds to about 1 to 2 chips of the spread code, as described above. Although the quantity of delay may be one chip in a state where a 2 samples/chip (bit) structure is employed, it is preferable that the quantity of delay be 2 chips if the sampling frequency is high. Fig. 14 shows another example of the clock output circuit 200 (see Fig. 8B). Referring to Fig. 14, the same elements as those shown in Fig. 8B are given the same reference numerals. Reference numeral 20I represents a peak shift detection circuit for detecting the quantity of the peak shift from the output from the synthesizing circuit 17, 20F represents a reference signal generating circuit, and 20H represents a phase shifting circuit that receives the output from the peak shift detection circuit 20I to generate a sampling clock that shifts the phase of the output signal from the reference signal generating circuit 20F to supply the phase-shifted clock to the A/D converters 13 and 14 (Fig. 8A). The output from the synthesizing circuit 17 is supplied to the peak shift detection circuit 20I so that the quantity of the peak shift is transmitted. The operation will now be described in detail with reference to Fig. 15. Fig. 15 shows an example in which a 2 samples/chip (bit) method is employed, and sampling points near the peak output are indicated by black dots. Dashed lines show the case of a continuous-time signal. In the continuous-time signal, the correlation peak is in the form of an isosceles triangle as indicated by a dashed line. Since discrete time sampling takes place due to A/D conversion, a discrete value having a sampling period Ts as indicated by the black dots is realized. Accordingly, maximum value α 0 in one period of the output from the synthesizing circuit 17 is detected, and a shift ΔT between the time, at which the maximum value α 0 is taken, and the true peak position is obtained from values α- and α+ at the sampling points before and after the time at which the maximum value α 0 is taken by using the following equation: ΔT/Ts = (α - - α + )/(2 · Δα) where Δα is the larger of (α 0 - α - ) or (α 0 - α + ). The phase shifting circuit 20H (Fig. 14) shifts the phase of the output from the reference signal generator 20F in accordance with the quantity of the shift transmitted by the peak shift detection circuit 20I to transmit the sampling clock, that has been synchronized, to the A/D converters 13 and 14. An example of the phase shifting circuit 20H is shown in Fig. 16. In Fig. 16, the delay circuits are continuously connected to generate a plurality of signals having different amounts of delay which are selected by a selector. If a highly-stable oscillator, such as a TCXO (Temperature Compensation Crystal Oscillator), is used as the reference signal generator 20F and a clock is selected from 8 to 16 signals having different amounts of delay, synchronization can be established accurately. In particular, a significant effect can be obtained in the transmission, such as packet transmission, in which the data length is limited. When the clock synchronization has been established, the synthesizing circuit 17 extracts the output from the two correlators 15 and 16 at point tl so as to obtain the amplitude and/or phase from the two signals so that demodulation of data is performed. By detecting the shift of the peak by the peak shift detection circuit 20I multiple times to detect the average value, a central value or the most probable frequency, influence of noise can be determined. Fig. 17 shows the structure of a receiving apparatus useful for understanding the present invention. Referring to Fig. 17, reference numeral 1 represents an antenna, 2 represents a high-frequency signal processor for processing, at a high frequency stage thereof, the signal received by the antenna 1, 4 represents a synchronizing circuit for capturing and maintaining the synchronization with the code and clock in the transmission side; and a code generator for generating n spread codes for demodulating data and spread codes for synchronization from a code synchronizing signal and a clock signal, 5 represents a carrier reproduced circuit for extracting a carrier from the received signal, 6 represents a base-band conversion circuit for converting the received signal into a base-band signal by using the reproducing carrier, 7 represents a demodulator that uses the base-band signal transmitted from the base-band conversion circuit 6 and n spread codes transmitted from the code generator 4 to demodulate data, and 8 represents a parallel/serial conversion circuit for converting n parallel data items into serial data. Referring to Fig. 17, the signal received by the antenna 1 is supplied to the high-frequency signal processor 2. The received signal is then converted into an intermediate frequency by the high-frequency signal processor 2. The output from the high-frequency signal processor 2 is supplied to the carrier reproducing circuit 5 and the base band conversion circuit 6. The carrier reproducing circuit 5 extracts the carrier from the output from the high-frequency signal processor 2. Fig. 18 shows a structure of the carrier reproducing circuit 5. The input signal is squared by a squaring circuit 261, a filter 262 extracts the carrier having the doubled frequency, and a PLL 263 halves the same, so that the carrier is reproduced. The reproduced carrier is supplied to the base-band conversion circuit 6 so that the output from the high-frequency signal processor 2 is converted into a base-band signal. The base-band conversion circuit 6 comprises, for example, a mixer for multiplying the output from the high-frequency signal processor 2 and the output from the carrier reproducing circuit 5, and a low-pass filter for removing unnecessary components from the output from the mixer. The carrier reproducing circuit 5 will be described later with reference to Fig. 18. The base-band signal transmitted from the base-band conversion circuit 6 is supplied to a synchronizing circuit/code generator 4 and a demodulator 7. The synchronizing circuit/code generator 4 uses the spread code PNr for synchronization to establish the synchronization of the code and the clock with respect to those of the transmitted signal. It is preferable that spread code PNr for synchronization be a selected code that corresponds to one of a plurality of multiplexed codes. The synchronizing circuit/code generator 4 has a similar structure to that according to the first embodiment shown in Fig. 3. Since no orthogonal component exists, the circuit corresponding to Qch and the synthesizing circuits 2433, 2452A and 2452B are not required. After the synchronization has been established, the code generator 4 generates n spread codes PN1,..., PNn for demodulating data, the clock and code phase of which coincide with those of the received signal. The n spread codes PN1,..., PNn for demodulating data transmitted by the code generator 4 are, together with the base-band signal transmitted by the base-band conversion circuit 6, supplied to the demodulator 7 so that the correlations with the base-band signals are calculated. Thus, n data items are demodulated. The demodulator 7 may have a structure similar to that shown in Fig. 4. Since no orthogonal component exists, the circuits 702-1 through 702-n and 704-1 through 704-n corresponding to Qch are not required. The demodulator 7 may have a structure similar to that shown in Figs. 5 and 6. Since no orthogonal component exists, the circuits 712 and 714-1 through 714-n corresponding to Qch are not required. Fig. 19 shows the structure of another example useful for understanding the invention in which a costas loop 51 is provided in place of the carrier reproducing circuit 5 and the base-band conversion circuit 6. Referring to Fig. 19, the same elements as those according to the apparatus shown in Fig. 17 are given the same reference numerals. Fig. 20 shows the structure of the costas loop. Referring to Fig. 20, the input signal is branched into two pieces so as to be respectively transmitted to mixers 461 and 462. The mixer 461 is also supplied with the output from a voltage-control oscillator 465, while the mixer 462 is supplied with the output from the voltage-control oscillator 465 after the output has been allowed to pass through a phase shifter 464. The mixer 461 transmits the same phase component (Ich) as that of the input signal, while the mixer 462 transmits the orthogonal component (Qch). The foregoing output signals are respectively supplied to low-pass filters 463 and 464, followed by a mixer 468. The output from the mixer 468 is allowed to pass through a loop filter 467 so as to be fed back to the voltage-control oscillator 465. As a result of the foregoing structure, the carrier of the input signal is reproduced by the voltage-control oscillator 465, while the base-band signal is transmitted from the low-pass filter 463. The foregoing base-band signal is supplied to the demodulator 7. Fig. 21 shows the structure of another example of a receiving apparatus useful for understanding the present invention. In this example, the same elements as those according to the example of Fig. 17 are given the same reference numerals. The present example is adapted to a case where the transmission signal is an orthogonal modulation signal. The orthogonal modulation signal can be obtained by modulating the signals in the two channels, that is, the channels Ich and Qch, by carrier waves that are orthogonal to each other and by synthesizing the modulated signals. Referring to Fig. 21, since the antenna 1, the high-frequency signal processor 2, and the synchronizing circuit/code generator 4 are the same as those according to the example of Fig. 17, their descriptions are omitted. A carrier reproducing circuit 5A has a structure in which it multiplexes the input signal by, for example, four, followed by causing the same to pass through the filter, and then the same is divided by four. The reproducing carrier transmitted from the carrier reproducing circuit 5A is supplied to the base-band conversion circuit 6B so that the input signal from the high-frequency signal processor 2 is converted into base-band signals in the two channels, that is, the channels Ich and Qch. Fig. 22 shows an example of the structure of the base-band conversion circuit 6B. The input signal is branched into two pieces so as to be respectively transmitted to mixers 361 and 362. In the mixer 361, the reproducing carrier from the carrier reproducing circuit 5A is multiplied with the input signal and the result is sent through a low-pass filter 364. Thus, the signal having the same phase (Ich) as the input signal is extracted. The mixer 362 is supplied with the reproducing carrier through a 90°-phase converter 363 so as to be multiplied by the input signal, followed by being sent through a low-pass filter 365. Thus, the orthogonal component (Qch) of the input signal is extracted. The base-band signals in the channels Ich and Qch are, together with n spread codes PN1,..., PNn for demodulating data transmitted by the code generator 4, supplied to demodulators 7I and 7Q so as to be correlated with the respective spread codes for demodulating data. Thus, n data items are demodulated. The demodulators 7I and 7Q have the same structures as those according to the example shown in Fig. 17. N parallel data items demodulated by the demodulators 7I and 7Q are supplied to the serializer 8 so as to be converted into serial data that is then transmitted. According to this example, information is carried on the two channels, that is, the channels Ich and Qch. Therefore, information transmission capacity that is twice that realized in the example of Fig.17 can be obtained. The channel Qch may be used for establishing synchronization in place of transmitting data information. In the foregoing case, the demodulator 7Q is not required. The foregoing structure eliminates the influence of data information on the synchronizing information, and stable synchronization can be realized. Figs. 23A and 23B show the structure of a second embodiment of the receiving apparatus according to the present invention. In this embodiment, the same elements as those according to the first embodiment shown in Fig. 8 are given the same reference numerals. In this embodiment, a base-band conversion circuit 6 and a carrier reproducing circuit 5 are provided in place of the quasi-base-band conversion circuit 6A. In this embodiment, the peak detection circuit 25 detects the peak of the correlator 15. The delay circuit 18 delays the output from the correlator 15, while the subtraction circuit 19 subtracts the output from the delay circuit 18 from the output from the correlator 15. A thinning (i.e. decimating) circuit 22A halves the output from the A/D converter 13. The thinning circuit 22A thins ( i . e . decimates) the output from the A/D converter so that the output from the A/D converter 13 is transmitted to the correlators 23-1 to 23-n when the output from the correlator 15 generates a peak. The structure of the carrier reproducing circuit 5 is the same as that shown in Fig. 18. The operations of the A/D converter 13, the clock control circuit 20, the correlators 23-1 to 23-n and the data discrimination circuits 24-1 to 24-n are the same as those according to the first embodiment shown in Fig. 8. In Figs. 23A and 23B, a clock output circuit 200A may have the structure similar to that shown in Fig. 14. In the foregoing case, since the Qch is omitted, the correlator 16 and the synthesizing circuit 17 are not required. In this embodiment, the peak shift detection circuit 20I obtains a shift ΔT between the maximum value α0 (see Fig. 15) of the output from the correlator 15 and the true peak value. The phase shifting circuit 20H shifts the output clock from the reference signal generator 20F in accordance with the shift ΔT.

Claims: A receiving apparatus for receiving a multi-code spread spectrum signal, said receiving apparatus comprising: first conversion means (6A, 6) for converting a first received signal into a second received signal at a base-band frequency; detection means (200, 200A) for detecting a spreading code included in the second received signal at the base-band frequency; and demodulating means (7B) for demodulating the second received signal modulated by a plurality of spreading codes, characterized in that it comprises second conversion means (13, 14) for converting the second received signal into a first digital signal at a first sampling frequency, and third conversion means (22, 22A) for converting the first digital signal into a second digital signal corresponding to a second sampling frequency lower than the first sampling frequency, and in that said detection means is operable to detect the spreading code from the first digital signal sampled at the first sampling frequency, and said demodulating means is operable to demodulate the second digital signal sampled at the second sampling frequency. A receiving apparatus according to Claim 1, wherein said detection means comprises control means (20) for controlling a sampling clock having the first sampling frequency, and wherein said second conversion means is operable to convert the second received signal into the first digital signal by means of the sampling clock. A receiving apparatus according to Claim 1, wherein said first conversion means is operable to convert the first received signal into the second received signal and a third received signal having different phases and in the base-band frequency; said second conversion means is operable to convert the second received signal into the first digital signal and the third received signal into a third digital signal at the first sampling frequency, said detection means comprises first correlation means (15) for correlating the first digital signal and the spreading code; second correlation means (16) for correlating the third digital signal and the spreading code; synthesis means (17) for synthesizing a first output from said first correlation means and a second output from said second correlation means; and control means (20, 20I, 20H), operable to receiving as input an output from said synthesis means, for controlling a sampling clock having the first sampling frequency; and said second conversion means is operable to convert the second received signal into the first digital signal and the third received signal into the third digital signal by means of the sampling clock. A receiving apparatus according to Claim 1, wherein said first conversion means comprises reproduction means (5) for reproducing a carrier of the first received signal. A method of receiving a multi-code spread spectrum signal, said method comprising the steps of: a first conversion step of converting a first received signal into a second received signal in a base-band frequency; a detection step of detecting a spreading code included in the second received signal in the base-band frequency; and a demodulating step of demodulating the second received signal modulated by a plurality of spread codes, characterized in that it comprises a second conversion step of converting the second received signal into a first digital signal at a first sampling frequency, and a third conversion step of converting the first digital signal into a second digital signal corresponding to a second sampling frequency lower than the first sampling frequency, in that and said detection step detects the spread code from the first digital signal sampled at the first sampling frequency, and said demodulating step demodulates the second digital signal sampled at the second sampling frequency. A receiving method according to Claim 5, wherein said detection step comprises a control step of controlling a sampling clock having the first sampling frequency, and wherein said second conversion step converts the second received signal into the first digital signal by means of the sampling clock. A receiving method according to Claim 5, wherein said first conversion step converts the first received signal into the second received signal and a third received signal having different phases and in the base-band frequency; said second conversion step converts the second received signal into the first digital signal and the third received signal into a third digital signal at the first sampling frequency; said detection step comprises a first correlation step of correlating the first digital signal and the spreading code; a second correlation step of correlating the third digital signal and the spread code; a synthesis step of synthesizing a first output from said first correlation step and a second output from said second correlation step; and a control step of controlling a sampling clock having the first sampling frequency using an output from said synthesis step ; and said second conversion step converts the second received signal into the first digital signal and the third received signal into the third digital signal by means of the sampling clock. A receiving apparatus according to Claim 5, wherein said first conversion step comprises a reproduction step of reproducing a carrier of the first received signal.

Inventors: KANDA TETSUO, KATO ICHIRO, MOCHIZUKI NORIHIRO, MORITOMO KAZUO, MYOJO TOSHIHIKO, SAITO KATSUO, SUZUKI RIE, TAKASAKI ATSUSHI, TORISAWA AKIRA, KANDA, TETSUO, KATO, ICHIRO, MOCHIZUKI, NORIHIRO, MORITOMO, KAZUO, MYOJO, TOSHIHIKO, SAITO, KATSUO, SUZUKI, RIE, TAKASAKI, ATSUSHI, TORISAWA, AKIRA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1995
Main classification: H04B1
IPC codes: H04B1, H04J13