Digital signal processing apparatus

Abstract: A specific pattern in an inputted digital signal is detected (13) and the input digital signal is sampled and held (14) in accordance with such a detection output. A clock (15-17) whose phase is synchronized with the input digital signal is generated on the basis of the sampling output. With such a construction as mentioned above, the phase of the clock can be optimally controlled by a simple construction. The clock can be precisely extracted from the input digital signal, so that the operation of a circuit is also stable.

Description: The present invention relates to a digital signal processing apparatus and, more particularly, to an apparatus for generating a signal whose phase is synchronized with a digital signal inputted. Hitherto, as such a kind of apparatus, there has been known a digital VTR for converting a video signal to a digital signal and for recording or reproducing the signal onto/from a magnetic tape. Fig. 1 is a block diagram showing a construction of a reproducing system in such a digital VTR. In Fig. 1, reference numeral 1 denotes a magnetic tape; 2 a magnetic head for recording or reproducing a signal to/from the magnetic tape 1; 3 a head amplifier for amplifying a reproduced signal of the magnetic head 1; 4 a reproduction equalizer which has predetermined frequency characteristics to equalize an output of the head amplifier 3 and is constructed by an LC network and the like; 18 a data detection circuit for converting an output signal of the reproduction equalizer 4, namely, a signal whose amplitude is changed in an analog manner to a digital signal again; 20 a PLL circuit for generating a clock synchronized with an output of the data detection circuit 18; 19 a sample-hold circuit for sampling and holding an output of the data detection circuit 18 by the clock that is generated from the PLL circuit 20; 9 a demodulator for demodulating the data which was sampled and held; 10 an error correction decoding circuit for correcting errors by detecting errors included in the demodulated reproduced data by using parity data added upon recording; 11 a reproduced signal processing circuit for performing a signal process which is almost opposite to a signal process at the time of the recording to the error corrected data, thereby decoding an encoded video signal and extending an information amount; and 12 a D/A converter for converting the signal processed data to the analog signal. The operation will now be described. The micro reproduced signal obtained from the magnetic head 2 by reproducing the magnetic tape 1 on which video image data has been recorded is amplified to 50 to 60 dB by the head amplifier 3. The frequency characteristics of the reproduced signal amplitude of the magnetic head 2 frequency characteristics of a magnetic recording and reproducing system as shown in Fig. 2, they are differentiating characteristics in a low frequency band and are attenuating characteristics in a high frequency band due to various losses. In the reproduction equalizer 4, the characteristics of the magnetic recording and reproducing system are compensated by using characteristics shown in Fig. 3 which are opposite to those in Fig. 2, thereby correcting the above reproduced signal amplitude. Such a method is an equalizing method called an integrating method. An output waveform of the reproduction equalizer 4 of the foregoing integrating method becomes an eye-pattern waveform as shown in Fig. 4. A waveform of such an eye-pattern is converted by using a comparator or the like in which a threshold level is selected at a position near the center by the data detection circuit 18, thereby deriving reproduced digital data. The PLL circuit 20 generates a clock synchronized with the reproduced digital data. The sample-hold circuit 19 samples and holds the above reproduced digital data by using such a clock. The sampled and held data is demodulated by the demodulator 9. Further, errors of such demodulated data are corrected by the error correction decoding circuit 10 by using an error correction parity added at the time of the recording. In the reproduced signal processing circuit 11, a signal process which is almost opposite to the signal process upon recording of the data is executed. The processed signal is D/A converted by the D/A converter 12, thereby obtaining a reproduced video image signal. In recent years, as an equalizing method of a reproduction equalizer which is used in a VTR for recording at a high density, a system using an intercode interference of a reproduced waveform called a partial response system (PR method) is being developed. In order to reduce reproduction errors, a technique in which such a system is combined with the Viterbi decoding method for detecting data by using a correlation of a reproduced signal in the direction of a time base is becoming a main stream nowadays. Fig. 5 is a block diagram of a reproducing system of a digital VTR using a PR(1, -1) method and a Viterbi decoder among the above partial response methods. In Fig. 5, reference numeral 5 denotes a delay circuit for delaying the output of the reproduction equalizer 4 by a time corresponding to one bit; 6 a subtracter for subtracting a delay output from the output of the reproduction equalizer 4; 7 an A/D converter for converting a subtraction output to digital data of a plurality of bits per one sample by the A/D conversion clock from the PLL circuit 20; and 8 a Viterbi decoder for converting the A/D conversion output to the digital data of one bit per one sample by using a Viterbi algorithm. In this instance, an equalizer of the PR(1, -1) method is constructed by the 1-bit delay circuit 5 and subtracter 6. Transmission characteristics of a transmission path are characteristics for suppressing a low frequency component as shown in Fig. 6. In recent years, a metal evaporation deposited tape (ME tape) has been being developed in order to record at a high density. According to the characteristics of the ME tape, a high frequency output is higher than that of a conventional metal painting type tape (MP tape) by a few dB, however, what is called a vertical component of residual magnetization is strong depending on a convenience in a manufacturing procedure. The low frequency component especially becomes a cause of a waveform distortion. To prevent such a distortion, the partial response method is used. Subsequently, an output of the subtracter 6 is A/D converted by the A/D conversion clock obtained from the PLL circuit 20 by the A/D converter 7, thereby detecting data having few errors by using a correlation in the direction of the time base of the reproduced signal by the Viterbi decoder 8. The detected data is added to the demodulator 9 and subsequent processes are executed in a manner similar to those in Fig. 1. A detailed description with respect to the operation of the Viterbi decoder 8 is omitted here. The partial response system as mentioned above is not limited to the PR(1, -1) method, but a PR(1, 0, -1) method is also considered. A reproducing system of a digital VTR using the PR(1, 0, -1) method will now be described hereinbelow. Fig. 7 is a block diagram showing a construction of the reproducing system of such a digital VTR. The construction up to the equalization of the reproduced signal by the reproduction equalizer 4 is substantially the same as that in Fig. 5. In Fig. 7, the delay circuit 5 delays the digital signal from the A/D converter 7 a time corresponding to two bits. Reference numeral 20a denotes a phase comparator for detecting a phase difference between the output signal of the reproduction equalizer 4 and an output clock of a VCO (voltage controlled oscillator) 20c, which will be described hereinlater; 20b a loop filter for amplifying an output of the phase comparator 20a, for returning the amplified output to the VCO 20c, and for obtaining predetermined PLL loop response characteristics; 20c the VCO for supplying a sampling clock to Viterbi decode a PR(1, 0, -1) signal and an operation clock of another circuit to the A/D converter 7. The above phase comparator 20a, loop filter 20b, and VCO 20c construct the PLL circuit 20. The operation will now be described. The signal which was reproduced and was equalized by the reproduction equalizer 4 as mentioned above is outputted to the A/D converter 7 and phase comparator 20a. In the PLL circuit 20, a phase difference between a clock generated by the VCO 20c and the output signal of the reproduction equalizer 4 is detected by the phase comparator 20a. The phase difference signal is inputted to the VCO 20c through the loop filter 20b, thereby performing a phase lock so that the phase difference is almost equal to 0. Frequency characteristics and a gain of the loop filter 20b, a sensitivity of the VCO 20c, and the like are set so that phase response characteristics of the PLL circuit can sufficiently absorb jitters which occur by a head tape system of the VTR and become less responsive to various noises. The PLL circuit is constructed as mentioned above and the phase of the lock of the PLL circuit is adjusted by, for example, adjusting the operation point of the phase comparator 20a or the like, so that a point at which an eye aperture becomes maximum can be sampled. The equalized signal is sampled and digitized by the A/D converter 7 which is controlled by the clock generated by the PLL circuit. The digitized reproduced signal is delayed by the delay circuit 5 and is subtracted from the original signal by the subtracter 6. The integrated equalized waveform is converted to a waveform having PR(1, 0, -1) characteristics by the above operation and its eye-pattern has three values as shown in Fig. 8. Such a PR(1, 0, -1) signal is maximum likelihood decoded by the Viterbi decoder 8. The combination of the PR(1, 0, -1) method and the Viterbi decoding is often used for a digital VTR using a high density magnetic recording or the like and can avoid bad low frequency band characteristics (S/N ratio, waveform distortion, and the like) of the magnetic recording system and can hold transmission errors minimum. Errors which occurred in the transmission path in the reproduced data decoded by the Viterbi decoder 8 are corrected by the error correction decoding circuit 10. The error corrected data is converted to the image signal of the original format by the reproduced signal processing circuit 11 and is converted to the analog image signal by the D/A converter 12 and is outputted as a reproduced image signal of the VTR. An output of the VCO 20c is also used as an operation clock of the circuits other than the A/D converter 7. The conventional digital VTR is constructed as mentioned above. The reproduced eye-pattern of the equalizer output of the PR(1, -1) method shown in Fig. 5 has a waveform as shown in Fig. 9A. In such an eye-pattern, as shown in the diagram, a window width in the direction of the time base is narrower as compared with that of the integrating method in Fig. 4. In case of A/D converting, therefore, when the phase of the A/D conversion clock added to the A/D converter 7 from the PLL circuit 20 is deviated from the optimum position in Fig. 9B to a position as shown in Fig. 9C or 9D, there is a problem such that the reproduced errors rapidly increase. In the conventional example, the apparatus is constructed in a manner such that a clock such as a sampling clock or the like of the A/D converter 7 is extracted from the analog signal which is generated from the reproduction equalizer 4 by the PLL circuit and the reproduced signal equalized by the reproduction equalizer 4 is sampled by the extracted clock. Generally, however, in the PLL circuit constructed in an analog manner, especially, in the case where a quality of the reproduced signal is low and the signal is reproduced at a high speed as in the digital VTR, there are problems such that it is difficult to hold a stability, it is necessary to adjust a sampling phase, and the like. It is known from EP-A-0415108 for a video tape recorder to extract a clock signal from an analogue playback signal using a phase locked loop. A variable phase correction is applied to the clock signal to adjust the timing of sampling for analogue to digital conversion to coincide with the timing of the maximum eye opening for the video signal. Coincidence with the maximum eye is determined by comparing digitised original levels against thresholds and accumulating count values of comparison results to allow the phase correction to be adjusted after each counting period of several seconds. It is also known from FR-A-2606575 to recover binary data from a received analogue signal using duobinary encoding by taking multiple digital samples at different phases. The number of code violations is observed for each of the resulting samples and an optimum sample is selected on the basis of minimum number of code violations. A clock signal is also recovered but using non optimum binary data. It is also known from EP-A-0586236 to detect a partial response coded signal using a phase locked loop in which a partial response phase comparator compares sampled signal levels for successive pulses and computes a phase error. during an acquisition phase, a zero crossing detector is used to extract a clock signal from a training signal before switching the phase comparator into operation. It is also an object of the invention to provide an improved digital signal processing apparatus. According to the present invention there is disclosed a digital signal processing apparatus, comprising: (a) input means for inputting a digital signal; (b) detecting means for detecting a specific pattern in said input digital signal; (c) sampling means for sampling a portion of the input digital signal, corresponding to said specific pattern in the input digital signal in response to an output of said detecting means; and (d) generating means for generating a clock signal whose phase is synchronized with that of said input digital signal in accordance with an output of said sampling means. A preferred embodiment provides an apparatus which can optimally control a phase of a clock to be generated by using an input digital signal. According to particular embodiments of the invention, there is provided a digital signal processing apparatus characterized by comprising input means for inputting a digital signal, detecting means for detecting a specific pattern in the input digital signal, sampling means for sampling and holding the input digital signal in accordance with an output of the detecting means, and generating means for generating a clock whose phase is synchronized with the input digital signal in accordance with an output of said sampling means. Another advantage of the embodiment is to provide an apparatus which extracts a clock from an input signal at a high precision and in which the operation is stable. The above and other objects and features of the present invention will become more apparent from the following detailed description and the appended claims with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing a construction of a conventional digital VTR; Fig. 2 is a diagram showing characteristics of a magnetic recording and reproducing system; Fig. 3 is a diagram showing reproduction equalizing characteristics; Fig. 4 is a diagram showing a waveform of a reproduced signal after completion of the equalization; Fig. 5 is a diagram showing another construction of a convectional digital VTR; Fig. 6. is a diagram showing transmitting characteristics of an equalizer of a PR(1, -1) method; Fig. 7 is a diagram showing further another construction of the conventional digital VTR; Fig. 8 is a diagram showing a waveform of a signal after completion of the PR(1, 0, -1) process; Figs. 9A to 9D are diagrams showing states of phases between a waveform of a reproduced signal and reproduced clocks; Fig. 10 is a diagram showing a construction of a digital VTR as an embodiment of the invention; Figs. 11A to 11E are diagrams showing states of signals of sections in Fig. 10; Figs. 12A to 12C are diagrams showing states of the signals of the sections in Fig. 10; Figs. 13A to 13C are diagrams showing states of the signals of the sections in Fig. 10; Figs. 14A to 14E are diagrams showing states of the signals of the sections in Fig. 10; Fig. 15 is a diagram showing another construction of a digital VTR as an embodiment of the invention; Fig. 16 is a diagram showing a construction of a digital phase detection circuit in Fig. 15; Fig. 17 is a diagram for explaining the operation of the circuit in Fig. 16; Fig. 18 is a diagram for explaining the operation of a PLL circuit in Fig. 16; Fig. 19 is a diagram showing another construction of the digital phase detection circuit in Fig. 15; and Fig. 20 is a diagram showing further another construction of the digital phase detection circuit in Fig. 15. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the invention will now be described. First, a case where the invention is applied to an apparatus which performs a process of PR(1, -1) to a reproduced signal and A/D converts the processed signal, thereby obtaining a reproduced video signal in a manner similar to the apparatus shown in Fig. 5. Fig. 10 is a block diagram showing a construction of a reproducing system of a digital VTR as an embodiment of the invention. The same portions as those in Fig. 5 are designated by the same reference numerals and their explanations are omitted. In Fig. 10, reference numeral 13 denotes a pattern detection circuit for detecting a specific data pattern which output data of the A/D converter 7 obtains on a time series; 14 a sample-hold circuit for sampling and holding the output data of the A/D converter 7 by a detection output of the pattern detection circuit 13; 15 a loop filter comprising a low pass filter for performing a filter process to an output of the sample-hold circuit 14; 16 a D/A converter for D/A converting an output of the loop filter 15; and 17 an oscillator comprising a VCO (voltage controlled oscillator) whose oscillating frequency is controlled by an output voltage of the D/A converter 16. An oscillation output of the oscillator 17 is supplied to the A/D converter 7 as an A/D conversion clock. A center frequency of the oscillator 17 is selected so as to be almost equal to a data transmission rate. The operation by the above construction will now be described. It is now assumed that a recording signal has a data pattern of (..., 0110, ...) as shown in Fig. 11A. When the signal is recording and reproduced to/from the magnetic tape 1 by the magnetic head 2, an output of the reproduction equalizer 4 of the integrating type at the time of the reproduction has a waveform as shown in Fig. 11B. When the output of the reproduction equalizer 4 is transmitted through an equalizer of the PR(1, -1) method comprising the delay circuit 5 and subtracter 6, as shown in Fig. 11C, an output signal of the equalizer has values such as +A, 0, and -A at three time points t 0 , t 1 , and t 2 , respectively, so as to decrease in one direction. Such a waveform is sampled at a leading edge of the A/D conversion clock from the oscillator 17 and is A/D converted by the A/D converter 7. When the data after completion of the A/D conversion is expressed in an analog manner, in the case where a phase of the A/D conversion clock is optimum, it has values of +A, 0, and -A as shown in Fig. 11E and is equal to 0 at the center time point t 1. When the phase of the A/D conversion clock advances, the A/D conversion data has values as shown in Fig. 12C. In this instance, it will be understood that the value of the center time point t 1 among three time points is not equal to 0 but is changed to +α. Similarly, when the phase of the A/D conversion clock lags, the value at the time point t 1 is changed to -α as shown in Fig. 13C. This means that in the case where a signal of a specific data pattern such as (..., 0110, ...) was recorded and reproduced, the pattern detection circuit 13 detects that the equalizer output of the PR(1, -1) method has a pattern which decreases in one direction at three points on the time series. When a value corresponding to the time point t 1 is sampled and held by the sample-hold circuit 14 in accordance with the detection, phase detection data indicative of the phase of the A/D conversion clock is directly obtained as a sampling output. When a specific data pattern is detected, the pattern detection circuit 13 generates a latch pulse to latch the value at the center time point t 1 . After the output of the sample-hold circuit 14 as phase detection data was subjected to the filter process by the loop filter 15, the processed output signal is D/A converted by the D/A converter 16 and the output voltage is negatively returned to the oscillator 17 of the VCO and the oscillating frequency is controlled, so that a PLL circuit in which a phase of the A/D conversion clock is optimized. In the above embodiment, although the example using a pattern in which a reproduction waveform decreases in one direction has been explained by using the pattern (..., 0110, ...) as a specific data pattern to be recorded, a signal such as (..., 1001, ...) is recorded as shown in Fig. 14A and a data pattern increasing in one direction at the time of the reproduction as shown in Fig. 14C is used, or the like, various data patterns can be used. For example, when the apparatus is constructed in a manner such that a pattern of a high appearance probability such as a sync pattern is used in accordance with a modulating method upon recording and such a pattern is detected, a further large effect can be obtained. Although the above embodiment has been described above with respect to the example in which the equalizer of the PR(1, -1) method has been constructed by the analog circuit, when the equalizer is constructed by a digital circuit and is provided at the post stage of the A/D converter 7, the operation similar to that of the above embodiment can be expected. Such a construction will be described hereinlater. Although the example in which the invention was applied to the digital VTR has been explained in the above embodiment, even when the invention is applied to a data processing apparatus using another transmission path such as satellite communication, optical fiber communication, or the like, the operation similar to that of the above embodiment can be expected. In the embodiment, although the input digital signal itself has been latched in accordance with the output of the pattern detection circuit 13, the invention is not limited to such a construction but can be also applied to a construction such that, in accordance with the detection of the pattern, differences between values at time points t1 in Figs. 12A and 13A and the 0 level, namely, +α and -α are obtained and outputted to the loop filter. Further, in the embodiment, although the output of the oscillator 17 has been used by only the A/D converter 7, the invention is not limited to the above construction. Since the output of the oscillator 17 is synchronized with the output digital signal of the A/D converter 7, it can be also used as an operation clock of another circuit in the apparatus. Since the phase detection output is directly obtained from the input digital signal, a stability of the PLL circuit to form the clock can be improved and a non-adjustment can be realized. As described above, in the embodiment, since the specific pattern in the input digital signal is detected and the clock is generated on the basis of the control signal formed by using the digital signal extracted in response to the detection timing, there is an effect such that the clock synchronized with the phase of the input digital signal can be formed. By using the clock formed as mentioned above as a clock at the time of, for example, the A/D conversion, even in the case where a window width in the direction of the time base of the eye-pattern is narrow as in the partial response system, since the phase of the A/D conversion clock can be optimized, there is an effect such that reproduction errors can be reduced. Subsequently, a case where the invention is applied to an apparatus in which, after a reproduced signal was A/D converted, the converted signal is subjected to a process of PR(1, 0, -1), thereby obtaining a reproduced video signal will now be explained. Fig. 15 is a block diagram showing a construction of a digital VTR as another embodiment of the invention. The same portions as those in Figs. 5 and 7 are designated by the same reference numerals and their explanations are omitted. An apparatus of Fig. 15 differs with respect to a point that a digital phase detection circuit 30 is provided in place of the phase comparator 20a in Fig. 7. The digital phase detection circuit 30 comprises a pattern detection circuit 31 and a sample-hold circuit 32. The digital data digitized by the A/D converter 7 is supplied to the pattern detection circuit 31 and a signal corresponding to the pattern of the data is generated. A PR(1, 0, -1) signal as an output of the subtracter 6 is supplied to the sample-hold circuit 32. The sample-hold circuit 32 samples and holds the PR(1, 0, -1) signal by being controlled by an output of the pattern detection circuit 31. By selecting a method of the pattern detection circuit 31, a signal corresponding to the phase difference between the reproduced data and the A/D conversion clock is obtained as an output of the sample-hold circuit 32. Fig. 16 shows a specific constructional example of the digital phase detection circuit 30 and is constructed by including the delay circuit 5 and subtracter 6 in Fig. 15. In Fig. 16, reference numerals 311 to 314 denote delay circuits for delaying A/D converted reproduced data 301 by a clock cycle; 315 a decoder as logical arithmetic operating means for extracting a specific pattern from outputs of the delay circuits 311 to 314; 321 a code inversion circuit for inverting a code of the output of the subtracter 6 in Fig. 15; 322 a switch for switching the output of the subtracter 6 and an output of the code inversion circuit 321 by a signal (s) generated from the decoder 315; 323 a latch for sampling and holding an output of the switch 322 by a signal (h) generated from the decoder 315, thereby generating a phase detection output 302. Arithmetic operating means is constructed by the subtracter 6 and code inversion circuit 321. In Fig. 16, the A/D converted reproduced data 301 is sequentially delayed by the delay circuits 311 to 314. The delay circuits 312 and 313 construct the delay circuit 5 and an output of the delay circuit 5 is subtracted by the subtracter 6 and becomes the PR(1, 0, -1) signal. In this instance, it is assumed that MSBs of input data and output data of the delay circuits 311 to 314 are set to (a), (b), (c), (d), and (e). When the reproduced data is A/D converted, if a mean value of those reproduced data is set so as to be located at the center of an A/D conversion range, then that (a), (b), (c), (d), and (e) become a binary data train obtained by integration detecting a reproduced data train. Such a data train is decoded by a specific logic by the decoder 315, thereby obtaining the signals (s) and (h). The signal (s) controls the switch 322 so as to switch the output of the subtracter 6 and an output obtained by inverting the output of the subtracter 6 by the code inversion circuit 321. The signal (h) controls the latches 323 and allows an output of the switch 322 to be sampled and held. A selecting method of the signals (s) and (h) will now be described. Fig. 8 shows the eye-pattern of the PR(1, 0, -1) signal. Such an eye-pattern has three values at data detection points. When paying an attention to a zero-crossing point of the eye-pattern, it is known that a signal which passes through the zero-crossing point has an inclination proportional to a phase difference between the data and the detection point. Such an inclination has values of both of positive and negative. By performing predetermined logical arithmetic operations by the decoder 315 so that the signal (s) judges about the positive or negative of the inclination and that the signal (h) locates at the zero-crossing point, the phase detection output 302 of the digital phase detection circuit 30 is set to a value in which the average level is proportional to the phase difference between the data and the detection point. As will be understood from the above eye-pattern, the inclination at the zero-crossing point has various values depending on the patterns of data and an inclination of phase comparison characteristics (phase detection sensitivity) is also fluctuated depending on the data patterns. In case of using in the loop of the PLL circuit, however, such an inclination causes only the fluctuation of the mean value of the loop gain, so that there is no problem. As a method of obtaining the signals (s) and (h), according to the invention, the signals are obtained by performing the logical arithmetic operations from the integration detected data train. Fig. 17 shows an example of a truth table of (s) and (h). In Fig. 17, (b-d), namely, an output of the subtracter 6 and logics of the signals (s) and (h) are shown for the integration detection data (a), (b), (c), (d), and (e). (s) denotes whether the inclination of (b-d) indicates positive or negative and (h) denotes whether (b-d) locates at the zero-crossing point or not. It will be understood that (s) and (h) can be expressed by simple logical arithmetic operations from the truth table. For example, they can be expressed as follows. h = (b ⊕ d) + a c e + a c e s = c Where, ⊕ denotes EXOR. The above logics are satisfied in the case where no error exists in the integration detected data (a), (b), (c), (d), and (e). As the phase between the data and the clock is deviated, errors occur in data of the detection output 302. In this case, although the output of the digital phase detection circuit 30 is erroneously sampled, when paying an attention to the mean value, the mean value approaches 0 with an increase in errors. Thus, phase comparison characteristics as shown in Fig. 18 are obtained. In Fig. 18, linear comparison characteristics are obtained for a range of almost ± 100°, so that a sufficient phase locked range is obtained as a PLL. When the PLL circuit to extract the clock is constructed by using the digital phase detection circuit 30 like the embodiment, since the PR(1, 0, -1) data itself sampled by the clock is controlled so as to be settled to the zero-crossing point, there is no fluctuating factor of the locked phase, so that the adjustment is unnecessary. When the loop filter 20b is also realized by a digital arithmetic operation, there is no DC offset or the like which causes a problem in an analog circuit, so that the adjustment of the PLL portion is almost unnecessary. The output of the VCO 20c is supplied as an operation clock to another predetermined circuit. As mentioned above, according to the embodiment, since the phase detection output is directly obtained from the A/D converted data, the stability of the PLL circuit to extract the clock can be raised, a non-adjustment can be realized, and errors can be reduced. In the above explanation, although the precision (the number of bits) of the arithmetic operation of the data, namely, by which number of bits per one sample the data is quantized by the A/D converter 7 has not been mentioned, generally, satisfactory characteristics (S/N ratio) are obtained by five bits or less. The number of bits can be decreased to about two bits in consideration of a performance, so that a circuit scale is also small. According to the embodiments, although the case where the invention is applied to the digital VTR has been described as an example, the invention is not limited to those embodiments but can be also applied to a system for transmitting and reproducing binary data, for example, a communication (radio wave, optical, etc.) optical disc or the like. In this case, in accordance with a nature of each transmission path, for example, the detection of three values such as PR(1, -1), PR(1, 1), and the like other than PR(1, 0, -1) is selected and a digital phase detection circuit similar to that of the invention can be constructed. As examples, constructional examples of the digital phase detection circuit in case of PR(1, -1) are shown in Figs. 19 and 20. Figs. 19 and 20 are different with respect to a point that the subtracter 6 obtains a difference between the data and the data which was delayed by one clock and also they differ from the case where the logics of the decoder 315 are equal to PR(1, 0, -1) shown in Fig. 16. That is, in Fig. 19, one delay circuit 311 is used, an EXOR (exclusive OR) gate is used as a decoder 315, the signal (h) is obtained by the MSBs (b) and (c) of an input and an output of the EXOR gate, and (c) is set to the signal (s). In Fig. 20, three delay circuits 311 to 313 are used and the delay outputs and the MSB of the reproduced data 301 are added as (a), (b), (c), and (d) to the decoder 315, so that the signals (s) and (h) are obtained by the logical expression shown in the diagram. As described above, according to the foregoing embodiments, since the specific pattern in the input digital signal is detected and the clock is generated on the basis of the control signal which was formed on the basis of the difference between the digital signals extracted in response to the detection timings, there is an effect that the clock synchronized with the phase of the input digital signal can be formed. By using the clock formed as mentioned above as a clock at the time of, for example, the A/D conversion, even in the case where the window width in the direction of the time base of the eye-pattern is narrow like the partial response system, since the phase of the A/D conversion clock can be optimized, there is an effect that the reproduced errors can be reduced. According to the above embodiments, the apparatus is constructed in a manner such that the input digital signal is sequentially delayed every stage of each of the delay circuits by the clock, the (N) data of the delayed data and the input digital signal are judged in a binary manner, predetermined logical arithmetic operations are performed by using the N-bit data obtained by the result of the above judgment, a difference or sum of two data among the (N) data is obtained, a value of the difference or sum is latched in accordance with the result of the logical arithmetic operations, the oscillator is controlled by the latched value, and such an oscillation output is used as a clock in the signal processes. Therefore, since the phase detection output is directly obtained from the input digital signal, the clock can be stably extracted. Thus, there are effects that the non-adjustment can be realized and errors in the signal processes can be reduced.

Claims: A digital signal processing apparatus, comprising: (a) input means (1 to 7) including converting means (7) for inputting a signal whose amplitude changes in an analog manner and for converting it into an input digital signal; (b) detecting means (13;31) for detecting a specific pattern in said input digital signal; (c) sampling means (14;32) for sampling a portion of the input digital signal corresponding to said specific pattern in the input digital signal in response to an output of said detecting means; and (d) generating means (15, 16, 17) for generating a clock signal whose phase is synchronized with that of said input digital signal in accordance with an output of said sampling means, and wherein said converting means is operable to perform a converting operation in accordance with the clock signal generated by said generating means. An apparatus according to any preceding claim, wherein said detecting means is operable to detect a plurality of different patterns as said specific pattern. An apparatus according to any preceding claim, wherein said generating means comprises means for extracting parts (b;d) of said input digital signal in accordance with an output (h) of said detecting means and said sampling means (323) is operable to sample and hold a difference of said extracted parts of said digital signal. An apparatus according to claim 3, wherein said generating means comprises delay means (5) for delaying the input digital signal from said input means and subtracting means (6) for subtracting the digital signal outputted by said delay means from the input digital signal outputted by said input means, and wherein said sampling means is operable to sample and hold an output of said subtracting means. An apparatus according to claim 4, wherein said detecting means is operable to detect said specific pattern such that zero-crossing points occur among a plurality of samples of the portion of the input digital signal which are successively outputted from said subtracting means corresponding to said specific pattern. An apparatus according to claim 3, wherein said detecting means is operable to detect the specific pattern in said digital signal by using data of N successive samples where N ≥ 3 in said input digital signal. An apparatus according to claim 1, wherein said generating means includes a loop filter (15;20b) to which the output of said sampling means is supplied and oscillating means (17) for generating said clock signal at a frequency corresponding to an output of said loop filter. An apparatus according to claim 1, wherein said input digital signal has characteristics corresponding to a partial response (1, 0, -1). An apparatus according to claim 8, wherein said detecting means is operable to detect whether or not a zero-crossing point exists between two successive samples in said input digital signal. An apparatus according to claim 1, wherein said input digital signal is a digital signal of a plurality of bits per one sample, and that said apparatus further has Viterbi decoding means (8) for detecting the digital signal of one bit per one sample from said input digital signal by using a Viterbi algorithm. An apparatus according to claim 1, wherein said input means includes reproducing means (3) for reproducing a recorded signal from a magnetic recording medium and equalizing means (4) for equalizing the signal reproduced by said reproducing means, and wherein said equalizing means has equalizing characteristics to compensate characteristics of a magnetic recording and reproducing system. An apparatus according to claim 8, wherein said input means has receiving means for receiving the digital signal and processing means for executing a process corresponding to a partial response (1, 0, -1) for the digital signal from said receiving means. An apparatus according to claim 1, wherein said detecting means includes: delay means (311, 312, 313, 314), connected at N - 1 stages for delaying said input digital signal by N clocks where N ≥ 2; logical arithmetic operating means (315) for binary-judging the digital signals of N - 1 samples of said input digital signal and the digital signals of N + 1 samples obtained from each stage of said delay means, respectively, and for performing predetermined logical arithmetic operations by using data of N + 1 bits obtained as judgment results; arithmetic operating means (6) for obtaining a sum or difference between two samples among said digital signals of (N) samples, and also wherein said sampling means is operable to sample and hold an output of said arithmetic operating means on the basis of an output of said logical arithmetic operating means. An apparatus according to claim 13, wherein said logical arithmetic operating means is operable to judge whether or not zero-crossing points exist among a plurality of successive samples in said input digital signal on the basis of said digital signals of N samples and also to judge positive or negative inclination among a plurality of samples which pass said zero-crossing points. An apparatus according to claim 13, wherein said arithmetic operating means is operable such that, in accordance with a judgment result about positive or negative inclination of said plurality of samples by said logical arithmetic operating means, a polarity of the inclination can be inverted, and said latch means is operable to perform said latch operation in accordance with the judgment result of the zero-crossing point by said logical arithmetic operating means. An apparatus according to claim 13, wherein said input digital signal is a signal of a plurality of bits per one sample and said data of N bits is constructed by the most significant bits of said digital signals of N samples. A method of extracting a clock signal for analogue to digital conversion and decoding of data from a received signal whose waveform comprises portions having a predetermined pattern which is a characteristic of the encoded data; the method comprising (a) generating a clock signal by operation of a phase locked loop (14, 15, 16, 17); (b) analogue to digital converting the received signal to obtain a digital signal by sampling the received signal according to the clock signal; (c) detecting in the digital signal the occurrence of the predetermined pattern; (d) selecting, in response to detection of each occurrence of the predetermined pattern, a respective value of the digital signal corresponding to the waveform portion in which the pattern occurs; and (e) inputting only the selected values of the digital signal to the phase locked loop as a phase detection signal for generating the clock signal.

Inventors: SASAKI YOSHIYUKI, YAMASHITA SHINICHI, SASAKI, YOSHIYUKI, YAMASHITA, SHINICHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1995
Main classification: H04N5
IPC codes: H04N5, H03L7