Sample hold circuit

Abstract: A sample hold circuit comprises a first transistor having its base connected to an input terminal and its collector connected to a voltage supply terminal, series-connected first and second diodes having a cathode of the first diode connected to an emitter of the first transistor, a first constant current source having its one end connected to an anode of the second diode circuit and its other end connected to the voltage supply terminal, a first differential circuit including a first branch connected to the emitter of the first transistor and a second branch connected to the anode of the second diode, a third diode having its cathode connected to the anode of the second diode, a second transistor having its base connected to a connection node between the second diode and the third diode and its collector connected to the voltage supply terminal, a second differential circuit including a first branch connected to the voltage supply terminal and a second branch connected to an emitter of the second transistor, a hold capacitor having its one end connected to the emitter of the second transistor, and a buffer having its input connected to the hold capacitor and its output connected to an output terminal and an anode of the third diode.

Description: Background of the Invention Field of the invention The present invention relates to a sample hold circuit for sampling and holding an instantaneous value of an analog signal, and more specifically to a sample hold circuit which is suitable to an integrated circuit and which can sample and hold a high speed analog signal. Description of related art One typical example of this type sample hold circuit is disclosed in, for example, US Patent 4,806,790. Referring to Figure 1, there is shown a conventional sample hold circuit shown in Figure 2 of US Patent 4,806,790. The shown sample hold circuit includes a transistor Q 11 having its base connected to an input terminal 11 and its collector connected to a high voltage supply terminal 15, series-connected diodes (D 11 to D 13 ) having its cathode side connected to an emitter of the transistor Q 11 , a constant current source I 14 having its one end connected to an anode of the diode D 13 and its other end connected to the high voltage supply terminal 15, and a differential circuit 31 including a differential pair of composed of one transistor Q 14 having its collector connected to the emitter of the transistor Q 11 and another transistor Q 15 having its collector connected to the anode of the diode D 13 , and a constant current source I 11 . The shown circuit also comprises a diode D 14 having its cathode connected to the anode of the diode D 13 , and its anode connected to a bias voltage terminal 17, a transistor Q 12 having its base connected to a connection node between the diodes D 13 and D 14 and its collector connected to the high voltage supply terminal 15, and a differential circuit 32 including a differential pair of composed of one transistor Q 16 having its collector connected to the high voltage supply terminal 15 and another transistor Q 17 having its collector connected to an emitter of the transistor Q 12 , and a constant current source I 12 . Furthermore, the shown circuit comprises a hold capacitor C H having its one end connected to the emitter of the transistor Q 12 and its other end connected to ground, and an emitter follower 33 composed of a transistor Q 13 having its base connected to the hold capacitor C H and its emitter connected to an output terminal 12 and a constant current source I 13 . Now, operation of this conventional sample hold circuit will be described. In a sample mode in which an input voltage Sin on a control input terminal 13 is at a high level ("H") and an input voltage Hin on a complementary control input terminal 14 is a low level ("L"), the transistors Q 14 and Q 17 of the differential transistor pairs (Q 14 and Q 15 ) and (Q 16 and Q 17 ) are rendered conductive, and the transistors Q 15 and Q 16 are rendered non-conductive. At this time, the analog signal Vin on the input terminal 11 is applied to the base of the transistor Q 11 , so that the transistor Q 11 operates as an emitter follower. The series-connected diodes (D 11 to D 13 ) connected to the emitter of the transistor Q 11 , acts as a level shift circuit supplied with a current from the constant current source I 14 Incidentally, a current of the constant current source I 11 is a sum of the current of the constant current source I 14 and an operating current of the transistor Q 11 . The transistor Q 12 operates as an emitter follower, so that the hold capacitor C H is charged or discharged. The transistor Q13 receiving the voltage of the hold capacitor C H as an input, operates as an emitter follower, so that an output voltage Vo is outputted from the output terminal 12. Now, assuming that a base-emitter voltage of the transistor Q 11 is V BE11 , a base-emitter voltage of the transistor Q 12 is V BE12 , a base-emitter voltage of the transistor Q 13 is V BE13 , and a forward direction voltage drop V F11 of the diode D 11 , a forward direction voltage drop V F12 of the diode D 12 , and a forward direction voltage drop V F13 of the diode D 13 , are the same voltage "V D ", the output voltage Vo can be expressed as follows: Vo = Vin - (V BE11 +V BE12 +V BE13 ) + 3V D Here, if it is set that all current densities of the transistors Q 11 , Q 12 and Q 13 and the diodes D 11 , D 12 and D 13 are equal, the following equation holds: V BE11 +V BE12 +V BE13 ≈ 3V D In this case, therefore, the relation becomes Vo = Vin, and accordingly, the output voltage Vo follows the input voltage Vin. In a hold mode in which the input voltage Sin and the input voltage Hin are brought to the low level ("L") and the high level ("H"), respectively, the transistors Q 14 and Q 17 are rendered off, and the transistors Q 15 and Q 16 are rendered on. In this condition, the transistor Q 12 which had operated in the emitter follower fashion in the sample mode so as to cause to charge or discharge the hold capacitor C H , is rendered non-conductive as a result of the conducting of the diode D 14 , so that the charge/discharge operation is stopped and an instantaneous value of the voltage Vin+V D is held in the hold capacitor C H . Thus, an instantaneous value of the input voltage Vin is held and outputted from the output terminal 12. Incidentally, a condition of cutting off the transistor Q 12 is sufficient if a sum of the potential of the hold capacitor C H and the base-emitter voltage V BE12 of the transistor Q 12 , namely, the base potential (Vin+2V D ) of the transistor Q 12 is larger than a voltage obtained by subtracting the forward direction voltage drop V F14 of the diode D 14 from the voltage of the bias voltage terminal 17. Here, assuming that the voltage of the bias voltage terminal 17 is V B , and the forward direction voltage drop V F14 of the diode D 14 is equal to V D , the above condition can be expressed as V B - V D < Vin + 2V D As one example, assuming that the analog input voltage Vin takes a value in the range of -2V to 0C, since V D is generally on the order of 0.7V to 0.8V, it is sufficient if the bias voltage V B is on the order of 0V (ground potential). On the other hand, the above condition can be satisfied by connecting the terminal 17 in common to the high voltage supply terminal 15, and replacing the diode D 14 by a plurality of diodes. However, the above mentioned sample hold circuit is disadvantageous in that the condition for holding the input voltage depends upon the input voltage, and a non-linear characteristics of the circuit becomes large. In other words, the cut-off condition " V B - V D < Vin + 2V D " of the emitter follower transistors Q 12 can be modified as follows: V B - 3V D < Vin Accordingly, it is disadvantageous in that the range of the input voltage that can be held in the sample hold circuit, is limited, and the cut-off condition of the transistors Q 12 depends upon the input voltage. Summary of the Invention Accordingly, it is an object of the present invention to provide a sample hold circuit which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a sample hold circuit so configured that the range of the input voltage is not limited by the condition for holding the input voltage, so that even if the voltage supply voltage is small, a wide operational range can be obtained. Still another object of the present invention is to provide a sample hold circuit so configured that when an input voltage is held, a cutoff transistor is always fixed to a constant operation condition, so that the cutoff condition become constant and therefore, a factor causing the non-linearity can be eliminated. The above and other objects of the present invention are achieved in accordance with the present invention by a sample hold circuit comprising: a first transistor having its base connected to an input terminal and its collector connected to a voltage supply terminal; a diode circuit having its cathode side connected to an emitter of the first transistor; a first constant current source having its one end connected to an anode side of the diode circuit and its other end connected to the voltage supply terminal; a first differential circuit including one transistor having its collector connected to the emitter of the first transistor and its base connected to a first control input and another transistor having its collector connected to the anode side of the diode circuit and its base connected to a second control input complementary to the first control input, and a constant current source having its one end connected in common to emitters of the one transistor and the another transistor; a second diode circuit having its cathode side connected to the anode side of the first diode circuit; a second transistor having its base connected to a connection node between the first diode circuit and the second diode circuit and its collector connected to the voltage supply terminal; a second differential circuit one transistor having its collector connected to the voltage supply terminal and its base connected to the second control input and another transistor having its collector connected to an emitter of the second transistor and its base connected to the first control input, and a constant current source having its one end connected in common to emitters of the one transistor and the another transistor of the second differential circuit; a hold capacitor having its one end connected to the emitter of the second transistor; and a buffer having its input connected to the hold capacitor and its output connected to an output terminal and an anode side of the second diode circuit. In an embodiment, each of said first and second diode circuits can be composed of a single diode, a plurality of diodes series-connected in the same direction, a single transistor connected in the form of a diode, or a plurality of transistors which are series-connected in the same direction and each of which is connected in the form of a diode. In one embodiment, the buffer includes an operational amplifier having its non-inverting input connected to the hold capacitor and its output connected to the output terminal and the anode side of the second diode circuit, the output of the operational amplifier being connected to an inverting input of the operational amplifier itself so that a closed loop full feedback is constituted. In another embodiment, the buffer is constituted of an emitter follower. Alternatively, the buffer is constituted of a source follower. According to another aspect of the present invention, there is provided a sample hold circuit comprising: a first transistor having its base connected to an input terminal and its collector connected to a voltage supply terminal; a diode circuit having its cathode side connected to an emitter of the first transistor; a first constant current source having its one end connected to an anode side of the diode circuit and its other end connected to the voltage supply terminal; a first differential circuit including one transistor having its collector connected to the emitter of the first transistor and its base connected to a first control input and another transistor having its collector connected to the anode side of the diode circuit and its base connected to a second control input complementary to the first control input, and a constant current source having its one end connected in common to emitters of the one transistor and the another transistor; a second diode circuit having its cathode side connected to the anode side of the first diode circuit; a second transistor having its base connected to a connection node between the first diode circuit and the second diode circuit and its collector connected to the voltage supply terminal; a second differential circuit including one transistor having its collector connected to the voltage supply terminal and its base connected to the second control input and another transistor having its collector connected to an emitter of the second transistor and its base connected to the first control input, and a constant current source having its one end connected in common to emitters of the one transistor and the another transistor of the second differential circuit; a hold capacitor having its one end connected to the emitter of the second transistor; and a buffer having its input connected to the hold capacitor, its first output connected to an anode side of the second diode circuit, and its second output connected to an output terminal. In an embodiment, each of said first and second diode circuits can be composed of a single diode, a plurality of diodes series-connected in the same direction, a single transistor connected in the form of a diode, or a plurality of transistors which are series-connected in the same direction and each of which is connected in the form of a diode. In one embodiment, the buffer includes an emitter follower and a source follower, an output of the source follower being connected to the anode side of the second diode circuit, an output of the emitter follower being connected to the output terminal. In another embodiment, the buffer includes two emitter followers, an output of one of the two emitter followers being connected to the anode side of the second diode circuit, an output of the other of the two emitter followers being connected to the output terminal. Alternatively, the buffer includes two source followers, an output of one of the two source followers being connected to the anode side of the second diode circuit, an output of the other of the two source followers being connected to the output terminal. According to a further aspect of the present invention there is provided a sample hold circuit as defined in claim 9. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a circuit diagram of a conventional sample hold circuit; Figure 2 is a circuit diagram of a first embodiment of the sample hold circuit in accordance with the present invention; Figure 3 is a circuit diagram of a second embodiment of the sample hold circuit in accordance with the present invention; Figure 4 is a circuit diagram of a third embodiment of the sample hold circuit in accordance with the present invention; Figure 5 is a circuit diagram of a fourth embodiment of the sample hold circuit in accordance with the present invention; Figure 6 is a circuit diagram of a fifth embodiment of the sample hold circuit in accordance with the present invention; Figure 7 is a circuit diagram of a sixth embodiment of the sample hold circuit in accordance with the present invention; and Figure 8 is a circuit diagram of a seventh embodiment of the sample hold circuit in accordance with the present invention. Description of the Preferred embodiments Referring to Figure 2, there is shown a circuit diagram of a first embodiment of the sample hold circuit in accordance with the present invention. As shown in Figure 2, the first embodiment of the sample hold circuit in accordance with the present invention includes a transistor Q 1 having its base connected to an input terminal 1 and its collector connected to a high voltage supply terminal 5, a pair of series-connected diodes D 1 and D 2 having its cathode of the diode D 1 connected to an emitter of the transistor Q 1 , a constant current source I 4 having its one end connected to an anode of the diode D 2 and its other end connected to the high voltage supply terminal 5, and a differential circuit 21 including a differential pair of composed of a pair of transistors Q 4 and Q 5 and a constant current source I 1 having its one end connected in common to emitters of the transistors Q 4 and Q 5 and its other end connected to a low voltage supply terminal 6. The transistors Q 4 has its collector connected to the emitter of the transistor Q 1 and its base connected to a sample control input terminal 3, and the transistor Q 5 has its collector connected to the anode of the diode D 2 and its base connected to a hold control input terminal 4. The shown circuit also comprises a diode D 4 having its cathode connected to the anode of the diode D 2 , a transistor Q 2 having its base connected to a connection node between the diodes D 2 and D 4 and its collector connected to the high voltage supply terminal 5, and a differential circuit 22 including a differential pair of composed of a pair of transistors Q 6 and Q 7 and a constant current source I 2 having its one end connected in common to emitters of the transistors Q 6 and Q 7 and its other end connected to the low voltage supply terminal 6. The transistor Q 6 has its collector connected to the high voltage supply terminal 5 and its base connected to the hold control input terminal 4, and the transistor Q 7 has its collector connected to an emitter of the transistor Q 2 and its base connected to the sample control input terminal 3. Furthermore, the shown circuit comprises a hold capacitor C H having its one end connected to the emitter of the transistor Q 2 and its other end connected to ground, and a buffer 7 having its input connected to the hold capacitor C H and its output connected to an output terminal 2 and an anode of the diode D 4 . Now, operation of this first embodiment of the sample hold circuit will be described. In a sample mode in which an input voltage Sin on the sample control input terminal 3 is at a high level ("H") and an input voltage Hin on the hold control input terminal 4 complementary to the sample control input terminal 3 is a low level ("L"), the transistors Q 4 and Q 7 of the differential transistor pairs (Q 4 and Q 5 ) and (Q 6 and Q 7 ) are rendered conductive, and the transistors Q 5 and Q 6 are rendered non-conductive. At this time, the analog signal Vin on the input terminal 1 is applied to the base of the transistor Q 1 , so that the transistor Q 1 operates as an emitter follower. The series-connected diodes D 1 and D 2 connected to the emitter of the transistor Q 1 , acts as a level shift circuit supplied with a current from the constant current source I 4 Incidentally, a current of the constant current source I 1 is a sum of the current of the constant current source I 4 and an operating current of the transistor Q 1 . The transistor Q 2 operates as an emitter follower, so that the hold capacitor C H is charged or discharged. The buffer 7 receives a voltage V CH on the hold capacitor C H as an input, and amplifies the received voltage with a gain of 1 (one), so that an output voltage Vo is outputted from the output terminal 2. Here, by using a DC level shift voltage V LS of the buffer 7, the output voltage Vo can be expressed: Vo = V CH - V LS Now, assuming that a base-emitter voltage of the transistor Q 1 is V BE1 and a base-emitter voltage of the transistor Q 2 is V BE2 and a forward direction voltage drop V F1 of the diode D 1 and a forward direction voltage drop V F2 of the diode D 2 are the same voltage "V D ", the voltage V CH on the hold capacitor C H can be expressed as follows: V CH = Vin - (V BE1 +V BE2 ) + 2V D Here, if it is set that all current densities of the transistors Q 1 and Q 2 and and the diodes D 1 and D 2 are equal, the following equation holds: V BE1 +V BE2 ≈ 2V D In this case, therefore, the relation becomes V CH = Vin, and accordingly, the voltage V CH on the hold capacitor C H follows the input voltage Vin. In a hold mode in which the input voltage Sin and the input voltage Hin are brought to the low level ("L") and the high level ("H"), respectively, the transistors Q 4 and Q 7 are rendered off, and the transistors Q 5 and Q 6 are rendered conductive. In this condition, the transistor Q 2 which had operated in the emitter follower fashion in the sample mode so as to cause to charge or discharge the hold capacitor C H , is rendered non-conductive as a result of the conducting of the diode D 4 , so that the charge/discharge operation is stopped and an instantaneous value of the analog input voltage Vin is held in the hold capacitor C H . In the buffer 7, the instantaneous value of the analog input voltage Vin is level-shifted by the voltage V LS , so that the output expressed by the following equation is outputted: Vo = Vin - V LS Here, assuming that the forward direction voltage drop V F4 of the diode D 4 is equal to V D , the base potential of the transistor Q 2 can be expressed as Vo - V D = Vin - V LS - V D The emitter voltage of the transistor Q2 is the voltage of the hold capacitor C H , and therefore, it is equal to the analog input voltage Vin. Namely, the base-emitter voltage V BE2 of the transistor Q 2 can be expressed as follows: V BE2 = -{V LS + V D } Accordingly, the base-emitter of the transistor Q 2 is applied with a constant reverse-bias voltage of {V LS + V D }. Thus, the sample hold circuit of the first embodiment of the present invention is so configured that, the transistor Q2 can take a cutoff condition without subjecting to restriction of the range of the analog input voltage Vin, and the cutoff voltage is the reverse-bias voltage of {V LS + V D }, which is always at a constant. Therefore, the non-linearity of the circuit caused by a varying cutoff degree of the transistor Q 2 can be substantially eliminated. Referring to Figure 3, there is shown a second embodiment of the sample hold circuit in accordance with the present invention. In Figure 3, elements corresponding or similar to those shown in Figure 2 are given the same Reference Numerals, and explanation thereof will be omitted. As seen from comparison between Figures 2 and 3, the second embodiment is the same as the first embodiment, excepting that the buffer 7 of the first embodiment is replaced with an operation amplifier 71 having its non-inverting input connected to the hold capacitor C H and its output connected not only to the output terminal 2 and the anode of the diode D 4 , but also to an inverting input of the operational amplifier 71 itself so that a closed loop full feedback is constituted. In this circuit construction, the analog input voltage Vin is not level-shifted by the voltage V LS , and therefore, the base-emitter voltage V BE2 of the transistor Q 2 becomes {-V D }. Accordingly, the base-emitter of the transistor Q 2 is applied with a constant reverse-bias voltage of {V D }. In this second embodiment, thus, the non-linearity of the circuit can be substantially eliminated, similarly to the first embodiment. Referring to Figure 4, there is shown a third embodiment of the sample hold circuit in accordance with the present invention. In Figure 4, elements corresponding or similar to those shown in Figure 2 are given the same Reference Numerals, and explanation thereof will be omitted. As seen from comparison between Figures 2 and 4, the third embodiment is the same as the first embodiment, excepting that the buffer 7 of the first embodiment is replaced with an emitter follower 23 having a bipolar transistor Q 3 having its base connected to the hold capacitor C H , its collector connected to the high voltage supply terminal 5 and its emitter connected to the output terminal 2 and the anode of the diode D 4 , and a current source I 3 having its one end of the emitter of the transistor Q 3 and its other end connected to the low voltage supply terminal 6. In this third embodiment, the level shift voltage V LS becomes a base-emitter voltage V BE3 of the transistor Q 3 , and therefore, by equalizing the current densities of various elements similarly to the first embodiment, the following relation can be obtained: V BE3 = V D If V BE3 = V D , the base-emitter voltage V BE2 of the transistor Q 2 becomes {-2V D }. Accordingly, the base-emitter of the transistor Q 2 is applied with a constant reverse-bias voltage of {2V D }. In this third embodiment, thus, the non-linearity of the circuit can be substantially eliminated, similarly to the first and second embodiments. Referring to Figure 5, there is shown a fourth embodiment of the sample hold circuit in accordance with the present invention. In Figure 5, elements corresponding or similar to those shown in Figure 2 are given the same Reference Numerals, and explanation thereof will be omitted. As seen from comparison between Figures 2 and 5, the fourth embodiment is the same as the first embodiment, excepting that the buffer 7 of the first embodiment is replaced with a source follower 24 having a field effect transistor Q 33 having its gate connected to the hold capacitor C H , its drain connected to the high voltage supply terminal 5 and its source connected to the output terminal 2 and the anode of the diode D 4 , and a current source I 33 having its one end connected to the source of the field effect transistor Q 33 and its other end connected to the low voltage supply terminal 6. In this fourth embodiment, the level shift voltage V LS becomes a gate-source voltage V GS3 of the transistor Q 3 , and therefore, the base-emitter of the transistor Q 2 is applied with a constant reverse-bias voltage of {V GS3 +V D }. This would be readily understood from the explanation of the third embodiment. Referring to Figure 6, there is shown a fifth embodiment of the sample hold circuit in accordance with the present invention. In Figure 6, elements corresponding or similar to those shown in Figure 2 are given the same Reference Numerals, and explanation thereof will be omitted. As seen from comparison between Figures 2 and 6, the fifth embodiment is the same as the first embodiment, excepting that the buffer 7 of the first embodiment is replaced with an emitter follower 25 having a bipolar transistor Q 31 having its base connected to the hold capacitor C H , its collector connected to the high voltage supply terminal 5 and its emitter connected to the output terminal 2 and a current source I 31 having its one end of the emitter of the transistor Q 31 and its other end connected to the low voltage supply terminal 6, and a source follower 26 having a field effect transistor Q 8 having its gate connected to the hold capacitor C H , its drain connected to the high voltage supply terminal 5 and its source connected to the anode of the diode D 4 , and a current source I 5 having its one end connected to the source of the field effect transistor Q 8 and its other end connected to the low voltage supply terminal 6. In this fifth embodiment, the base-emitter of the transistor Q 2 is applied with a constant reverse-bias voltage of {V GS8 +V D }, similarly to the fourth embodiment shown in Figure 5. In this fifth embodiment, on the other hand, since the output terminal 2 of the sample hold circuit is connected with the output of the emitter follower 25 and the anode of the diode D 4 is connected with the output of the source follower 26, the output voltage Vo is not subjected to noise occurring when the transistor Q 5 and the diode D 4 are rendered conductive, in comparison with the third and fourth embodiments. Referring to Figure 7, there is shown a sixth embodiment of the sample hold circuit in accordance with the present invention. In Figure 7, elements corresponding or similar to those shown in Figure 6 are given the same Reference Numerals, and explanation thereof will be omitted. As seen from comparison between Figures 6 and 7, the sixth embodiment is the same as the fifth embodiment, excepting that the source follower 26 of the fifth embodiment is replaced with an emitter follower 27 having a bipolar transistor Q 88 having its base connected to the hold capacitor C H , its collector connected to the high voltage supply terminal 5 and its emitter connected to the anode of the diode D 4 and a current source I 55 having its one end of the emitter of the transistor Q 88 and its other end connected to the low voltage supply terminal 6. In this sixth embodiment, the base-emitter of the transistor Q 2 is applied with a constant reverse-bias voltage of {2V D }, similarly to the third embodiment shown in Figure 4. Accordingly, similarly to the fifth embodiment, it is possible to reduce the noise occurring when the transistor Q 5 and the diode D 4 are rendered conductive. Referring to Figure 8, there is shown a seventh embodiment of the sample hold circuit in accordance with the present invention. In Figure 8, elements corresponding or similar to those shown in Figure 6 are given the same Reference Numerals, and explanation thereof will be omitted. As seen from comparison between Figures 6 and 8, the seventh embodiment is the same as the fifth embodiment, excepting that the emitter follower 25 of the fifth embodiment is replaced with a source follower 28 having a field effect transistor Q 34 having its gate connected to the hold capacitor C H , its drain connected to the high voltage supply terminal 5 and its source connected to the output terminal 2 and a current source I 34 having its one end of the source of the field effect transistor Q 34 and its other end connected to the low voltage supply terminal 6. In this seventh embodiment, the base-emitter of the transistor Q 2 is applied with a constant reverse-bias voltage of {V GS8 +V D }, similarly to the fifth embodiment shown in Figure 6. Accordingly, similarly to the fifth embodiment, it is possible to reduce the noise occurring when the transistor Q 5 and the diode D 4 are rendered conductive. In the above mentioned third to seventh embodiments, the emitter follower and the source follower of the buffer in the sample hold circuit have been described to be of an N-channel input type. However, it would be apparent to persons skilled in the art that the emitter follower and the source follower can be of a P-channel input type or can be formed of a combination of an N-channel transistor and a P-channel transistor. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A sample hold circuit comprising: a first transistor (Q1) having its base connected to an input terminal (1) and its collector connected to a voltage supply terminal (5); a diode circuit (D1, D2) having its cathode side connected to an emitter of said first transistor (Q1); a first constant current source (I4) having its one end connected to an anode side of said diode circuit (D1, D2) and its other end connected to said voltage supply terminal (5); a first differential circuit (21) including one transistor (Q4) having its collector connected to the emitter of said first transistor (Q1) and its base connected to a first control input (3) and another transistor (Q5) having its collector connected to said anode side of said diode circuit (D1, D2) and its base connected to a second control input (4) complementary to said first control input (3), and a constant current source (I1) having its one end connected in common to emitters of said one transistor (Q4) and said another transistor (Q5); a second diode circuit (D4) having its cathode side connected to said anode side of said first diode circuit (D1, D2); a second transistor (Q2) having its base connected to a connection node between said first diode circuit (D1, D2) and said second diode circuit (D4) and its collector connected to said voltage supply terminal (5); a second differential circuit (22) including one transistor (Q6) having its collector connected to said voltage supply terminal (5) and its base connected to said second control input (4) and another transistor (Q2) having its collector connected to an emitter of said second transistor (Q2) and its base connected to said first control input (3), and a constant current source (I2) having its one end connected in common to emitters of said one transistor (Q6) and said another transistor (Q7) of said second differential circuit (22); a hold capacitor (CH) having its one end connected to said emitter of said second transistor (Q2); and a buffer (7) having its input connected to said hold capacitor (CH) and its output connected to an output terminal (2), characterised in that said buffer (7) further has its output connected to an anode side of said second diode circuit (D4). A sample hold circuit claimed in Claim 1 wherein said buffer (7) includes an operational amplifier (71) having its non-inverting input connected to said hold capacitor (CH) and its output connected to said output terminal (2) and said anode side of said second diode circuit (D4), said output of said operational amplifier (71) being connected to an inverting input of said operational amplifier (71) itself so that a closed loop full feedback is constituted. A sample hold circuit claimed in Claim 1 wherein said buffer (7) is constituted of an emitter follower (Q3, I3). A sample hold circuit claimed in Claim 1 wherein said buffer (7) is constituted of a source follower (Q33, I33). A sample hold circuit comprising: a first transistor (Q1) having its base connected to an input terminal (1) and its collector connected to a voltage supply terminal (5); a diode circuit (D1, D2) having its cathode side connected to an emitter of said first transistor (Q1); a first constant current source (I4) having its one end connected to an anode side of said diode circuit (D1, D2) and its other end connected to said voltage supply terminal (5); a first differential circuit (21) including one transistor (Q4) having its collector connected to the emitter of said first transistor (Q1) and its base connected to a first control input (3) and another transistor (Q5) having its collector connected to said anode side of said diode circuit (D1, D2) and its base connected to a second control input (4) complementary to said first control input (3), and a constant current source (I1) having its one end connected in common to emitters of said one transistor (Q4) and said another transistor (Q5); a second diode circuit (D4) having its cathode side connected to said anode side of said first diode circuit (D1, D2); a second transistor (Q2) having its base connected to a connection node between said first diode circuit (D1, D2) and said second diode circuit (D4) and its collector connected to said voltage supply terminal (5); a second differential circuit (22) including one transistor (Q6) having its collector connected to said voltage supply terminal (5) and its base connected to said second control input (4) and another transistor (Q7) having its collector connected to an emitter of said second transistor (Q2) and its base connected to said first control input (3), and a constant current source (I2) having its one end connected in common to emitters of said one transistor (Q6) and said another transistor (Q7) of said second differential circuit (22); a hold capacitor (CH) having its one end connected to said emitter of said second transistor (Q2); and second a buffer (25-28) having its input connected to said hold capacitor (CH) and its first output connected to an output terminal (2), characterised in that said buffer (25-28) has its second output connected to an anode side of said second diode circuit (D4). A sample hold circuit claimed in Claim 5 wherein said buffer includes an emitter follower (25) and a source follower (26), an output of said source follower (26) being connected to said anode side of said second diode circuit (D4), an output of said emitter follower (25) being connected to said output terminal (2). A sample hold circuit claimed in Claim 5 wherein said buffer includes two emitter followers (Q31, I31; 27), an output of one (27) of said two emitter followers being connected to said anode side of said second diode circuit, an output of the other (Q31, I31) of said two emitter followers being connected to said output terminal (2). A sample hold circuit claimed in Claim 5 wherein said buffer includes two source followers (28; Q8, I5), an output of one (Q8, I5) of said two source followers being connected to said anode side of said second diode circuit (D4), an output of the other (28) of said two source followers being connected to said output terminal (2). A sample hold circuit comprising: a first transistor (Q1) having its control electrode connected to an input terminal (1), one end of its current path of said first transistor (Q1) being connected to a voltage supply terminal (5); a diode circuit (D1, D2) having its cathode side connected to an emitter of said first transistor (Q1); a first constant current source (I4) having its one end connected to an anode side of said diode circuit (D1, D2) and its other end connected to said voltage supply terminal (5); a first differential circuit (21) including a first input connected to a first control input (3) and a second input connected to a second control input (4) complementary to said first control input (3), said first differential circuit also including a first branch (Q4) connected to the other end of the current path of said first transistor (Q1) and a second branch (Q5) connected to said anode side of said first diode circuit (D1, D2); a second diode circuit (D4) having its cathode side connected to said anode side of said first diode circuit (D1, D2); a second transistor (Q2) having its control electrode connected to a connection node between said first diode circuit (D1, D2) and said second diode circuit (D4), one end of a current path of said second transistor (Q2) being connected to said voltage supply terminal (5); a second differential circuit (22) including a first input connected to said second control input (4) and a second input connected to said first control input (3), said second differential circuit (22) also including a first branch (Q6) connected to said voltage supply terminal (5) and a second branch (Q7) connected to the other end of said current path of said second transistor (Q2); a hold capacitor (CH) having its one end connected to the other end of said current path of said second transistor (Q2); and a buffer (7) having its input connected to said hold capacitor (CH) and its output connected to an output terminal (2), characterised in that said buffer (7) further has its output connected to an anode side of said second diode circuit (D4).

Inventors: SONE KAZUYA, SONE, KAZUYA
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1995
Main classification: G11C27
IPC codes: H03K17, G11C27, H03M1