Semiconductor memory device

Abstract: A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.

Description: BACKGROUND OF THE INVENTION Field of the Invention: This invention relates to a semiconductor memory device. Description of the Related Art: In the conventional semiconductor memory device, a plurality of memory cells arranged in matrix form have been divided into a plurality of blocks (hereinafter called "arrays"). In this type of semiconductor memory device, various operations such as a data reading operation, etc. have been carried out in array units. The semiconductor memory device has output circuits each of which supplies data corresponding to data supplied from a memory cell to its corresponding bit line to a data line in response to a column address signal sent to one of the column address lines. The output circuit comprises two transistors series-connected between a terminal supplied with a ground potential and the data line. A control electrode of one of the two transistors is electrically connected to its corresponding bit line. A control electrode of the other thereof is electrically connected to its corresponding column address line. When data stored in a memory cell, which has been supplied to a bit line, is of "1", for example, a transistor connected to the bit line is turned ON and a transistor supplied with a column address signal is turned ON in response to the column address signal. Thus, the data line is reduced in potential. As a result, data corresponding to the data "1" supplied to the bit line, is supplied to the data line. On the other hand, when the data referred to above is of "0", the transistor connected to the bit line is turned OFF. Thus, the potential of the data line is maintained as it is. As a result, data corresponding to the data "0" of the memory cell, which has been supplied to the bit line, is sent to the data line. According to the conventional semiconductor memory device as described above, the above operations are performed by the selected array alone. It is therefore possible to reduce power consumption of the whole semiconductor memory device. EP-A-0490652 discloses a static random access memory array divided into sub-arrays according to the pre-characterised portion of claim 1. To reduce the power consumed during active operation, only one of the sub-arrays remains energised during each active cycle, the energised sub-array being selected according to the three most significant column address bits. EP-A-0449282 discloses further details of a sense amplifier and its power supply in a memory circuit. According to the present invention, there is provided a semiconductor memory device comprising a plurality of memory arrays selectable by a selection signal, each array including a plurality of memory cells, a plurality of row address lines connected to said memory cells, a plurality of pairs of bit lines connected to said memory cells, a pair of data buses and a plurality of sense amplifier means each of which is connected to one of said bit line pairs, said sense amplifier means being selectable by a column address signal, characterised in that said semiconductor memory device further comprises a data bus pre-charge circuit connected to said data bus pair for charging the data bus pair to a first potential, and each of said amplifier means includes an output circuit connected to said data bus pair and one of said bit line pairs, said output circuit including data transfer transistors having gates connected to one of the bit line pairs, first terminals connected to supply a second potential different to the first potential, and second terminals connected to said data bus pair, wherein the output circuit included in a selected one of the sense amplifier means within a selected memory array is arranged to selectively supply the second potential to one data bus of said data bus pair in response to a potential appearing on the connected bit line pair, and the output circuit included in each of the non-selected sense amplifier means within the selected memory array and the output circuits within the non-selected memory arrays are arranged to maintain the status of said data bus pair. Embodiments of the present invention will now be described, by way of example with reference to the accompanying drawings, in which: Figure 1 is a fragmentary circuit diagram showing a sense amplifier array employed in a first embodiment of the present invention; Figure 2 is a view schematically illustrating a configuration of a semiconductor memory device according to the present invention; Figure 3 is a view schematically depicting a configuration of an array ARm; Figure 4 is a fragmentary circuit diagram showing a sense amplifier array employed in a second embodiment of the present invention; Figure 5 is a fragmentary circuit diagram illustrating a sense amplifier array employed in a third embodiment of the present invention; Figure 6 is a fragmentary circuit diagram depicting a sense amplifier array employed in a fourth embodiment of the present invention; Figure 7 is a fragmentary circuit diagram showing a sense amplifier array employed in a fifth embodiment of the present invention; Figure 8 is a timing chart for describing the operation of the sense amplifier array shown in Figure 1; and Fig. 9 is a timing chart for describing the operation of the sense amplifier array shown in Fig. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings. Fig. 2 is a view schematically showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. The semiconductor memory device comprises a plurality of arrays AR 0 through AR m and decoder circuits D1 and D2. Column address lines CL 0 , ∼, CL i are respectively connected to the decoder circuit D1 and the arrays AR 0 through AR m . The decoder circuit D1 serves as a circuit for selecting a desired column address line from the column address lines CL 0 , ∼, CL i . Each of array selection signal lines AS 0 , ∼, AS m electrically connected to the decoder circuit D2 is electrically connected to its corresponding array of the arrays AR 0 through AR m . The decoder circuit D2 serves as a circuit for selecting a desired array selection signal line from the array selection signal lines AS 0 , ∼, AS m so as to select a desired array. A plurality of data lines DB are electrically connected to their corresponding arrays AR 0 , ∼, AR m . Fig. 3 is a view schematically showing a configuration of the array AR m . The AR m will be described below with reference to Fig. 3. The array ARm comprises a decoder circuit D3, a memory cell array MAR having a plurality of memory cells arranged in matrix form, a sense amplifier array SAR composed of a plurality of sense amplifiers and a sense amplifier control circuit, and a switching circuit SW electrically connected between the sense amplifier array SAR and a data line DB. The decoder circuit D3 is electrically connected to the memory cell array MAR through a plurality of row address lines WL 0 , ∼, WL m . The decoder circuit D3 is electrically connected to the decoder circuit D2 through the array selection signal line AS m . Further, the decoder circuit D3 serves as a circuit for selecting a row address line corresponding to an input row address when the array selection signal line AS m is selected. The memory cell array MAR is electrically connected to the sense amplifier array SAR through a plurality of bit lines BL 0 , ∼, BL i . A brief description will now be made of a circuit operation of the memory cell array MAR. When the decoder circuit D3 selects one row address line, a plurality of data stored in a plurality of memory cells connected to the selected row address line are supplied to their corresponding bit lines. Since the individual bit lines are electrically connected to the sense amplifier array SAR, the data stored in the respective memory cells connected to the selected row address line are transferred to the sense amplifier array SAR. The sense amplifier array SAR is electrically connected to the decoder circuit D1 through the column address lines CL 0 , ∼, CL i . Further, the sense amplifier array SAR is electrically connected to the decoder circuit D2 through the array selection signal line AS m . Furthermore, the sense amplifier array SAR is electrically connected to the switching circuit SW through data lines SDB and SDB . The sense amplifier array SAR comprises a plurality of sense amplifiers composed of sense latch circuits and output circuits and connected to their corresponding bit line pairs, and a sense amplifier control circuit. Each of the sense latch circuits amplifies data stored in a memory cell, which has been supplied to its corresponding bit line. Each of the output circuits outputs data corresponding data stored in a memory cell, which has been supplied to a bit line corresponding to a column address line selected by the decoder circuit D1, to the data lines SDB and SDB . The switching circuit SW is electrically connected to the sense amplifier array SAR through the data lines SDB and SDB . The switching circuit SW controls the transfer of data corresponding to the data sent to the data lines SDB or SDB to the data line DB. The sense amplifier array SAR and the decoder D3 included in each of the arrays AR 0 through AR m are electrically connected to their corresponding array selection signal line of the array selection signal lines AS 0 through AS m . Since inner circuit configurations of the respective arrays AR 0 through ARm are substantially identical to one another, the arrays other than the array AR m which has been described above, will not be described. Fig. 1 is a fragmentary circuit diagram showing a sense amplifier array employed in the first embodiment of the present invention. The first embodiment will be described below with reference to Fig. 1. Fig. 1 is a fragmentary circuit diagram of a sense amplifier array SAR which comprises a plurality of sense amplifiers SA 0 , ∼, SA i and a sense amplifier control circuit SAC. Incidentally, a memory cell array MAR is also described to provide easy understanding of the relationship of correspondence between memory cells and sense amplifiers. The memory cell array MAR includes a plurality of memory cells MC 00 through MC im-1 electrically connected to their corresponding bit lines of bit lines BL 0 , ∼, BL j , ∼, BL i provided on an alternate basis counting from the bit line BL 0 and electrically connected to their corresponding row address lines of row address lines WL 0 , WL 2 , ∼, WL m-1 provided on an alternate basis counting from the row address line WL 0 . Further, the memory cell array MAR includes a plurality of memory cells MC 01 , ∼, MC im electrically connected to their corresponding bit lines of bit lines BL 0 , ∼, BL j , ∼, BL i provided on an alternate basis counting from the bit line BL 0 and electrically connected to their corresponding row address lines of row address lines WL 1 , WL 3 , ∼, WL m provided on an alternate basis counting from the row address line WL 1 . The bit line pair (BL 0 and BL 0 ) is electrically connected to its corresponding sense amplifier SA 0 . Similarly, the bit lines of the bit line pairs (BL 1 and BL 1 ) ∼ (BL i and BL i ) are electrically connected to their corresponding sense amplifiers SA 1 , ∼, SA i . The sense amplifiers SA 0 through SA i are electrically connected to their corresponding column address lines CL 0 , ∼, CL i . The sense amplifier SA j will now be described. The sense amplifier SA j comprises a sense latch circuit and an output circuit. The sense latch circuit comprises N-channel type Metal Oxide Semiconductor transistors (hereinafter called "NMOS transistors") MN 1 and MN 2 used for detection and amplification, P-channel type MOS transistors (hereinafter called "PMOS transistors") MP 1 and MP 2 , and NMOS transistors MN 3 and MN 4 used for equalization of bit lines. The source of the NMOS transistor MN 1 is electrically connected to a sense latch terminal SLNT. The drain of the NMOS transistor MN 1 is electrically connected to the bit line BL j and the gate thereof is electrically connected to the bit line BL j . The source of the NMOS transistor MN 2 is electrically connected to the sense latch terminal SLNT. The drain of the NMOS transistor MN 2 is electrically connected to the bit line BL j and the gate thereof is electrically connected to the bit line BL j . The source of the PMOS transistor MP 1 is electrically connected to a sense latch terminal SLPT. The drain of the PMOS transistor MP 1 is electrically connected to the bit line BL j and the gate thereof is electrically connected to the bit line BL j . The source of the PMOS transistor MP 2 is electrically connected to the sense latch terminal SLPT. The drain of the PMOS transistor MP 2 is electrically connected to the bit line BL j and the gate thereof is electrically connected to the bit line BL j . The source of the NMOS transistor MN 3 is supplied with a potential of 1/2V CC . The drain of the NMOS transistor MN3 is electrically connected to the bit line BLj and the gate thereof is electrically connected to a sense latch circuit equalize EQT. The source of the NMOS transistor MN4 is supplied with the potential of 1/2V CC . The drain of the NMOS transistor MN4 is electrically connected to the bit line BL j and the gate thereof is electrically connected to the sense latch circuit equalize terminal EQT. The output circuit comprises N-channel type MOS transistors MN 5 , MN 6 , MN7 and MN 8 . The NMOS transistors NM 5 and MN 6 are series-connected between a data line SDB and a date transfer enable line DTEA. Further, the NMOS transistors MN 7 and MN 8 are series-connected between a data line SDB and the data transfer enable line DTEA. The column address line CL j is electrically connected to the gate of the NMOS transistor MN 6 and the gate of the NMOS transistor MN 8 . The gate of the NMOS transistor MN 5 is electrically connected to the bit line BLj and the gate of the NMOS transistor MN7 is electrically connected to the bit line BLj. Each of the sense amplifiers SA 0 , ∼, SA i electrically connected to their corresponding bit lines of the bit line pairs (BL 0 and BL 0 )∼ (BL i and BL i ) is composed of NMOS transistors MN 1 , MN 2 , MN 3 , MN 4 , MN 5 , MN 6 , MN7 and MN 8 and PMOS transistors MP 1 and MP 2 in a manner similar to the sense amplifier SA j . The drain of the transistor MN 1 of each of the sense amplifiers SA 0 , ∼ SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The gate of the transistor MN 1 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The drain of the transistor MN 2 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The gate of the transistor MN 2 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines( BL 0 , ∼, BL i ). The drain of the transistor MP1 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The gate of the transistor MP 1 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The drain of the transistor MP 2 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The gate of the transistor MP 2 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The gate of the transistor MN 5 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The gate of the transistor MN 7 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The drain of the transistor MN 3 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The drain of the transistor MN4 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i . The gate of the transistor MN 6 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding column address line of the column address lines CL 0 , ∼, CL i . The gate of the transistor MN 8 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding column address line of the column address lines CL 0 , ∼, CL i . Since electrical connections of the individual sense amplifiers SA 0 , ∼, SA i , which are other than the electrical connections referred to above, are similar to those made by the sense amplifier SA j , their description will be omitted. A sense amplifier control circuit SAC will now be described. The sense amplifier control circuit SAC comprises NMOS transistors MN 9 , MN 10 , MN 11 , MN 12 , MN 13 , a PMOS transistor MP 3 and generating circuits SPG, EQG, SNG and DTEG. The drain and gate of the NMOS transistor MN 9 are supplied with a power source potential V CC . The source of the NMOS transistor MN 9 is electrically connected to the data line SDB. The drain and gate of the NMOS transistor MN 10 are supplied with the power source potential V CC . The source of the NMOS transistor NM 10 is electrically connected to the data line SDB . The generating circuit DTEG is of a circuit for supplying a data transfer enable signal DTE to a data transfer enable terminal DTET to which the data transfer enable line DTEA is connected. The generating circuit SNG is of a circuit for supplying an N-channel sense latch enable signal SN to an N-channel sense latch enable terminal SNT. The generating circuit EQG is of a circuit for supplying a sense latch circuit equalizing signal EQ to the sense latch circuit equalize terminal EQT. The generating circuit SPG is of a circuit for supplying a P-channel sense latch enable signal SP to a P-channel sense latch activation or enable terminal SPT. The source of the PMOS transistor MP 3 is supplied with the power source potential V CC . The drain of the PMOS transistor MP3 is electrically connected to the sense latch terminal SLPT. The gate of the PMOS transistor MP3 is electrically connected to the P-channel sense latch enable terminal SPT. The source of the NMOS transistor MN 11 is supplied with the potential of 1/2V CC . The drain of the NMOS transistor NM 11 is electrically connected to the sense latch terminal SLPT. The gate of the NMOS transistor NM 11 is electrically connected to the sense latch circuit equalize terminal EQT. The source of the NMOS transistor MN 12 is supplied with the potential of 1/2V CC . The drain of the NMOS transistor MN 12 is electrically connected to the sense latch terminal SLNT. The gate of the NMOS transistor MN 12 is electrically connected to the sense latch circuit equalize terminal EQT. The source of the NMOS transistor MN 13 is supplied with a ground potential V SS . The drain of the NMOS transistor MN 13 is electrically connected to the sense latch terminal SLNT. The gate of the NMOS transistor MN 13 is electrically connected to the N-channel sense latch enable terminal SNT. A reading operation of the semiconductor memory device shown in Figs. 1, 2 and 3 will now be described with reference to a timing chart shown in Fig. 8, for describing the operation of the sense amplifier array employed in the first embodiment of the present invention. Prior to the reading operation, the potential of each of the column address lines CL 0 , ∼, CL i is set to the ground potential V SS . The potential of each of the row address lines WL 0 , ∼, WL m is set to the ground potential. The potential of the sense latch circuit equalizing signal EQ is set to the power source potential V CC . The potential of the sense latch circuit equalize terminal EQT is set to the power source potential V CC . The potential of the P-channel sense latch enable signal SP is set to the power source potential V CC . The potential of the P-channel sense latch enable terminal SPT is set to the power source potential V CC . The potential of the N-channel sense latch enable signal SN is set to the ground potential V SS . The potential of the N-channel sense latch enable terminal SNT is set to the ground potential V SS . The transistor MN 11 is turned ON so that the potential of sense latch terminal SLPT is set to the potential of 1/2V CC . The transistor MN 12 is turned ON so that the potential of the sense latch terminal SLNT is set to the potential of 1/2V CC . The transistor MN4 of the corresponding sense amplifier of the sense amplifiers SA 0 , ∼, SA i is turned ON so that the potential of each of the bit lines BL 0 , ∼, BL i is set to the potential of 1/2V CC . The transistor MN3 of the corresponding sense amplifier of the sense amplifiers SA 0 , ∼, SA i is turned ON so that the potential of each of the bit lines BL 0 , ∼, BL i is set to the potential of 1/2V CC . The potential of the data transfer enable signal DTE is set to the power source potential V CC . The potential of the data transfer enable terminal DTET is set to the power source potential V CC . The data line SDB is set to a potential lowered by a threshold voltage V t of the NMOS transistor MN 9 from the power source potential V CC . The data line SDB is set to a potential reduced by a threshold voltage V t of the NMOS transistor MN 10 from the power source potential V CC . This state is called an "equalized state". A circuit operation for reading data of "1" stored in a memory cell MC j1 of the array AR m will now be described as an example. An array selection signal line ASm is first selected by the decoder circuit D2. Correspondingly, the potential of the sense latch circuit equalizing signal EQ developed in the array AR m is changed to the ground potential V SS . In doing so, the transistors MN 3 and MN4 of each of the sense amplifiers SA 0 , ∼, SA i are turned OFF so that the potential of the row address line WL1 selected by the decoder circuit D3 is changed to a potential increased by a threshold voltage V t of the NMOS transistor in the memory cell MC j1 from the power source potential V CC . With the change of the potential of the row address line WL 1 to the increased potential, data stored in the individual memory cells MC 01 , ∼, MC j1 , ∼, MC i1 connected to the row address line WL1 are supplied to their corresponding bit lines BL 0 , ∼, BL j , ∼, BL i . Thus, small differences in potential are developed between the respective bit line pairs (BL 0 and BL O ), ∼, (BL i and BL i ). Next, the potential of the data transfer enable signal DTE is changed to the ground potential V SS . Further, the potential of the P-channel sense latch enable signal SP is changed to the ground potential V SS . Furthermore, the N-channel sense latch enable signal SN is changed to the V CC potential. Thus, the PMOS transistor MP 3 is turned ON so that the potential of the sense latch terminal SLPT is changed to the power source potential V CC . Further, the NMOS transistor MN 13 is turned ON so that the potential of the sense latch terminal SLNT is changed to the ground potential V SS . With the change of the sense latch terminals SLPT and SLNT to the power source potential V CC and the ground potential V SS , the individual sense latch circuits of the sense amplifiers SA 0 , ∼, SA i are driven. Thus, the difference in potential between each of the bit line pairs (BL 0 and BL 0 ), ∼, (BL i and BL i ) is amplified. As a result, the potential of the BL j supplied with a high level potential is brought to the power source potential V CC and the potential of the bit line BL j is brought to the ground potential V SS . Next, the column address line CL j is selected by the decoder circuit D1. The potential of the selected column address line CL j is changed to the power source potential V CC . With the change of the potentials of the bit line BL j and the column address line CL j to the power source potential V CC , the NMOS transistors MN 5 and MN 6 of the sense amplifier SA j are turned ON. Thus, the potential of the data line SDB is reduced. With the change of the potential of the bit line BL j to the ground potential V SS on the other hand, the transistor MN 7 is turned OFF. As a result, the data line SDB is maintained at the power source potential V CC . Thus, data corresponding to the data stored in the memory cell MC j1 is supplied to the data line SDB . The state of each of the arrays, which have not been selected through the corresponding array selection signal lines, will now be described. The potential of a sense latch circuit equalizing signal EQ is set to the power source potential V CC . The potential of each of the row lines WL 0 , ∼, WL i is set to the ground potential V SS . The potential of a P-channel sense latch enable signal SP is set to the power source potential V CC . The potential of an N-channel sense latch enable signal SN is set to the ground potential V SS . A transistor MN 11 is turned ON so that the potential of a sense latch terminal SLPT is set to a potential of 1/2V CC . A transistor MN 12 is turned ON so that the potential of a sense latch terminal SLNT is set to the potential of 1/2V CC . A transistor MN 4 of a corresponding sense amplifier of the sense amplifiers SA 0 , ∼, SA i is turned ON so that the potential of each of the bit lines BL 0 , ∼, BL i is set to the potential of 1/2V CC . A transistor MN 3 of a corresponding sense amplifier of the sense amplifiers SA 0 , ∼, SAj is turned ON so that the potential of each of the bit lines BL 0 , ∼, BL i is set to the potential of 1/2V CC . The potential of a data transfer enable signal DTE is set to the power source potential V CC . A data line SDB is set to a potential reduced by a threshold voltage V t of an NMOS transistor MN 9 from the power source potential V CC . A data line SDB is set to a potential reduced by a threshold voltage V t of an NMOS transistor MN 10 from the power source potential V CC . Even if a column address line CL j is selected in each array held in the non-selected state, an NMOS transistor MN 5 and an NMOS transistor MN 7 of a sense amplifier SA j connected to the column address line CL j are not turned ON. This is because the potential of the data transfer enable signal DTE is set to the power source potential V CC and the potential of the bit line pair BL j and BL j connected to the sense amplifier SAj is set to the potential of 1/2V CC . Namely, each of the transistors MN 5 and MN 7 is in an OFF state. Thus, no current flows through the transistor MN 5 . Similarly, no current flows through the transistor MN 7 . As a result, power consumption is reduced. Here, the level of the potential of the data transfer enable signal DTE employed in the non-selected array, i.e., the potential of the data transfer enable terminal DTET may be a potential that does not allow the transistors MN 5 and MN 7 to turn ON. Namely, since the potential of the bit line pair being in the equalized state is of the 1/2V CC , the potential of the data transfer enable terminal DTET may be a potential higher than 1/2V CC - threshold voltage V t (where V t : threshold voltage of each of transistors MN 5 and MN 7 ). Fig. 4 is a fragmentary circuit diagram showing a sense amplifier array employed in a second embodiment of the present invention. The second embodiment will be described below with reference to Fig. 4. The same elements of structure as those shown in Fig. 1 or the elements of structure similar to those shown in Fig. 1 are identified by like reference numerals and their description will therefore be omitted. In the first embodiment, the sources of the transistors MN 5 and MN 7 of each of the sense amplifiers SA 0 , ∼, SA i have been connected to the data transfer enable terminal DTET through the data transfer enable line DTEA. In the second embodiment to the contrary, the sources of transistors MN 5 and MN 7 of each of sense amplifiers SA 0 , ∼, SA i are electrically connected to a sense latch terminal SLNT. No generating circuit DTEG is provided in the second embodiment. A reading operation of the second embodiment will now be described. In a selected array, the potential of a sense latch terminal SLNT is reduced in a manner similar to the data transfer enable terminal DTET employed in the first embodiment. Thus, each output circuit is activated in the same manner as that employed in the first embodiment. In non-selected each array, the potential of a sense latch terminal SLNT is set to a potential of 1/2V CC . Thus, the potentials of the sources of the transistors MN 5 and MN 7 of each of the sense amplifiers SA 0 , ∼, SA j are respectively set to the potential of 1/2V CC . Further, the potential of each of bit lines BL 0 , ∼, BL j , BL j , ∼, BL i is set to the potential of 1/2V CC . Therefore, the transistors MN 5 and MN 7 of each of the sense amplifiers SA 0 , ∼, SA i are brought into an OFF state. Thus, even if a column address line CL j is selected, no current flows through the transistor MN 5 of the sense amplifier SA j . Further, no current flows through the transistor MN 7 of the sense amplifier SA j . Since the sources of the transistors MN 5 and MN 7 of each of the sense amplifiers SA 0 , ∼, SA i are electrically connected to the sense latch terminal SLNT, the generating circuit DTEG becomes unnecessary in the second embodiment. Accordingly, the second embodiment can bring about advantageous effects that logic and layout designs become easy as well as advantageous effects obtained in the first embodiment. Fig. 5 is a fragmentary circuit diagram showing a sense amplifier array employed in a third embodiment of the present invention. The third embodiment will be described below with reference to Fig. 5. The same elements of structure as those shown in Fig. 1 or the elements of structure similar to those shown in Fig. 1 are identified by like reference numerals and their description will therefore be omitted. A generating circuit DTEG is not provided in the third embodiment. An inverter INV0 and a pair of NMOS transistors MN 9 and MN 10 are provided at plural places within a sense amplifier array SAR. The placement and connections of the inverters INV0 and the NMOS transistors MN 9 and MN 10 will now be described in detail. The inverters INV0 are disposed in the neighborhood of their corresponding sense amplifier groups of sense amplifier groups each comprised of an appropriate number of sense amplifiers. The output of each inverter INV0 is electrically connected to a data transfer enable line DTEA provided in the vicinity of its corresponding sense amplifier group. The input of each inverter INV0 is electrically connected to an N-channel sense latch enable terminal SNT. The NMOS transistors MN 10 are provided in the neighborhood of their corresponding sense amplifier groups of the sense amplifier groups. One ends of the individual NMOS transistors MN 10 are electrically connected to their corresponding data lines SDB provided in the neighborhood of the corresponding sense amplifier groups. The NMOS transistors MN 9 are provided in the neighborhood of their corresponding sense amplifier groups of the sense amplifier groups. One end of each NMOS transistor MN 9 is electrically connected to its corresponding data line SDB in the vicinity of the corresponding sense amplifier group. In the third embodiment, a signal obtained by inverting an N-channel sense latch enable signal SN is supplied to the data transfer enable line DTEA through the plurality of inverters INV0. Thus, each output circuit performs an output operation substantially similar to the first embodiment. Comparisons will now be made between advantageous effects brought about by the third embodiment and those obtained in the first embodiment. In the semiconductor memory device according to the first embodiment, the number of the sense amplifiers SA 0 through SA i is regarded as being provided in plural form. In the first embodiment, junction points between the sense amplifier SA 0 and the data lines are provided close to junction point between the NMOS transistors MN 9 and the data lines SDB and junction point between NMOS transistors MN 10 and the data lines SDB than junction points between the sense amplifier SA i and the data lines SDB and SDB . Thus, if a comparison is made between the case where the NMOS transistors MN 5 and MN 6 of the sense amplifier SA 0 are turned ON and the potential of the data line SDB is reduced, for example, and the case where the NMOS transistors MN 5 and MN 6 of the sense amplifier SA i are turned ON and the potential of the data line SDB is reduced, then the latter makes a path over which the current flows along the data line SDB longer. Wiring resistances are included in the data lines. Thus, when the sense amplifier SA i is driven and the potential of the data line SDB is reduced, the potential of a portion near the junction point at which the sense amplifier SA i is connected to the data line SDB is greatly reduced as compared with the case where the sense amplifier SA 0 is driven and the potential of the data line SDB is lowered. In the third embodiment on the other hand, the transistors MN 9 and MN 10 are disposed at plural places within the sense amplifier array SAR. Thus, if a comparison is made between the case where a sense amplifier SA i is driven and the potential of a data line is reduced in the third embodiment, for example, and the case where the sense amplifier SA i is driven and the potential of the data line is reduced in the first embodiment, then the former can bring about a less reduction in the potential of the neighboring data line connected to the sense amplifier SA i . Thus, since the potential on the data line is not greatly reduced in the third embodiment, the semiconductor memory device can be activated at high speed upon reading the next data. In the first embodiment, the data transfer enable line DTEA is electrically connected to the data transfer enable terminal DTET supplied with the data transfer enable signal DTE. The sense amplifier SA 0 is electrically connected to the data transfer enable line DTEA at junction points relatively near the data transfer enable terminal DTET. Further, the sense amplifier SA i is electrically connected to the data transfer enable line DTEA at junction points spaced away from the data transfer enable terminal DTET. Therefore, if a comparison is made between the case where the transistors MN 5 and MN 6 of the sense amplifier SA 0 disposed relatively close to the data transfer enable terminal DTET are turned ON and the potential of the data line SDB is reduced and the case where the transistors MN 5 and MN 6 of the sense amplifier SA i disposed away from the data transfer enable terminal DTET are turned ON and the potential of the data line SDB is reduced, then the latter makes longer a path over which the current flows along the data transfer enable line DTEA. Since wiring resistances are included in the data transfer enable line DTEA here, the potential of the source of the transistor MN 5 in the sense amplifier SA i is raised when the sense amplifier SA i is driven and the data line SDB is reduced in potential. Therefore, the transistor MN 5 is hard to turn ON and the operation of reducing the potential on the data line SDB becomes slow. Since the inverters are located in the plural places of the sense amplifier array so as to correspond to the appropriate number of sense amplifier groups in the third embodiment, a path over which the current flows along the data transfer enable line DTEA, is shortened when the potential of the data line SDB or SDB is lowered. Thus, the potentials of the sources of NMOS transistors MN 5 and MN 7 are respectively reduced to a potential enough to turn ON the NMOS transistors MN 5 and MN 7 . As a result, the potential on each data line can be lowered at high speed. Further, since each inverter INV0 is electrically connected between the data transfer enable line DTEA and the N-channel sense latch enable terminal SNT, it is unnecessary to provide a generating circuit DTEG. Therefore, logic and layout designs can be easily carried out. Fig. 6 is a fragmentary circuit diagram showing a sense amplifier array employed in a fourth embodiment of the present invention. The fourth embodiment will be described below with reference to Fig. 6. The same elements of structure as those shown in Fig. 1 or the elements of structure similar to those shown in Fig. 1 are identified by like reference numerals and their description will therefore be omitted. Referring to Fig. 6, the drain of a data line pull-down transistor MN 14 is electrically connected to a data line SDB and the source thereof is supplied with a ground potential V SS . The gate of the transistor MN 14 is supplied with a data transfer enable signal DTE. The drain of a data line pull-down transistor MN 15 is electrically connected to a data line SDB and the source thereof is supplied with the ground potential V SS . The gate of the transistor MN 15 is supplied with the data transfer enable signal DTE. In the first embodiment, the gates of the transistors MN 9 and MN 10 are supplied with the power source potential V CC . In the fourth embodiment, however, the gates of transistors MN 9 and MN 10 are electrically connected to an output terminal of an inverter INV0. Further, an input terminal of the inverter INV0 is electrically connected to a generating circuit DTEG and is supplied with the data transfer enable signal DTE. Further, a data transfer enable line DTEA is electrically connected to the ground potential V SS . A reading operation of the sense amplifier array employed in the fourth embodiment of the present invention will now be described with reference to a timing chart shown in Fig. 9. Prior to the reading operation, the potential of each of column address lines CL 0 , ∼, CL i is set to the ground potential V SS . The potential of a sense latch circuit equalizing signal EQ is set to the power source potential V CC and the potential of a sense latch circuit equalize terminal EQT is set to the power source potential V CC . The potential of a P-channel sense latch enable signal SP is se to the power source potential V CC and the potential of a P-channel sense latch enable terminal SPT is set to the power source potential V CC . The potential of an N-channel sense latch enable signal SN is set to the ground potential V SS and the potential of an N-channel sense latch enable terminal SNT is set to the ground potential V SS . NMOS transistors MN 11 and MN 12 are turned ON so that the potentials of the sense latch terminals SLPT and SLNT are respectively set to a potential of 1/2V CC . A transistor MN 4 of each of sense amplifiers SA 0 through SA i is turned ON so that the potential of each of bit lines BL 0 through BL i is set to the potential of 1/2V CC . A transistor MN 3 of each of sense amplifiers SA 0 through SAj is turned ON so that the potential of each of bit lines BL 0 through BL i is set to the potential of 1/2V CC . The potential of the data transfer enable signal DTE is set to the power source potential V CC . Thus, the potentials of the data lines SDB and SDB are set to the ground potential V SS . This state is called an "equalized state". A circuit operation for reading data of "1" stored in a memory cell MC j1 of an array AR m will now be described. The circuit operation of the selected array ARm will be described below. When an array selection signal line AS m is first selected by a decoder circuit D2, the potential of the sense latch circuit equalizing signal EQ developed in the array AR m is changed to the ground potential V SS . Further, the potential of a row address line WL 1 selected by a decoder circuit D3 is changed to a potential increased by a threshold voltage V t of each NMOS transistor from the power source potential V CC . With the change of the potential of the data transfer enable signal DTE to the ground potential V SS , the data line pull-down NMOS transistors MN 14 and MN 15 are turned OFF and the data line pull-up transistors MN 9 and MN 10 are turned ON to thereby change the potential of the data line pair SDB and SDB to a potential reduced by a threshold voltage V t of each NMOS transistor from the power source potential V CC . With the transition from the present potential of the row address line WL 1 to the increased potential, data stored in individual memory cells MC 01 , ∼, MC j1 , ∼ MC i1 connected to the row address line WL 1 are supplied to their corresponding bit lines BL 0 , ∼, BL j , ∼, BL i . Thus, small differences in potential are developed between the respective bit line pairs (BL 0 and BL O ), ∼, (BLj and BL j ), ∼, (BL i and BL i ). Next, the potential of the P-channel sense latch enable signal SP is changed to the ground potential V SS . Further, the potential of the N-channel sense latch enable signal SN is changed to the ground potential V CC . Thus, a PMOS transistor MP 3 is turned ON and the potential of the sense latch terminal SLPT is changed to the power source potential V CC . Further, an NMOS transistor MN 13 is turned ON so that the potential of the sense latch terminal SLNT is changed to the ground potential V SS . The sense latch terminals SLPT and SLNT are respectively changed to the power source potential V CC and the ground potential V SS so that individual sense latch circuits of the sense amplifiers SA 0 , ∼, SA j , ∼, SA i are driven. As a result, the difference in potential between each of the bit line pairs (BL 0 and BL 0 ), ∼, (BL j and BL j ), ∼, (BL i and BL i ) is amplified. Thus, the potential of the bit line BL j supplied with the data of "1" is brought to the power source potential V CC and the potential of the bit line BL j is brought to the ground potential V SS . When a column address line CL j is next selected by a decoder circuit D1, the potential of the selected column address line CL j is changed to the power source potential V CC . With the transition from the present potentials of the bit line BL j and the column address line CL j to the power source potential V CC , NMOS transistors MN 5 and MN 6 of the sense amplifier SA j are turned ON and hence the potential of the data line SDB is reduced to the ground potential V SS . On the other hand, since the potential of the bit line BL j is changed to the ground potential V SS , the corresponding transistor MN 7 is turned OFF. As a result, the potential of the data line SDB remains unchanged. Thus, data corresponding to the data stored in the memory cell MC j1 is supplied to the data line SDB . The state of each of the arrays, which are not selected through the corresponding array selection signal lines, will now be described. The potential of a sense latch circuit equalizing signal EQ is set to the power source potential V CC level. The potential of a P-channel sense latch enable signal SP is set to the power potential V CC . The potential of an N-channel sense latch enable signal SN is set to the ground potential V SS . Transistors MN 11 and MN 12 are turned ON so that the potentials of sense latch terminals SLPT and SLNT are respectively set to a potential of 1/2V CC . A transistor MN 4 of a corresponding sense amplifier of sense amplifiers SA 0 , ∼, SA i is turned ON so that the potential of each of bit lines BL 0 , ∼, BL i is set to the potential of 1/2V CC . A transistor MN3 of a corresponding sense amplifier of the sense amplifiers SA 0 , ∼, SA i is turned ON so that the potential of each of bit lines BL 0 , ∼, BL i is set to the potential of 1/2V CC . The potential of a data transfer enable signal DTE is set to the power source potential V CC . The potential of a data line SDB is set to the ground potential VSS. The potential of a data line SDB is set to the ground potential V SS . The potential of each of row address lines WL 0 through WL i is set to the ground potential V SS . The potential of a data transfer enable line DTEA is set to the ground potential V SS . Now, consider that a column address line CL j is selected and transistors MN 6 and MN 8 of a sense amplifier SA j are turned ON in this condition. Since the data lines SDB and SDB and the data transfer enable line DTEA are maintained at the ground potential V SS , no current flows between the NMOS transistors MN 5 and MN 6 of the sense amplifier SA j . Further, the current does not flow between the NMOS transistors MN 7 and MN 8 of the sense amplifier SA j . In the fourth embodiment, the data can be supplied to the data line pair at high speed as compared with the first embodiment. The reason will be described as follows: In the first embodiment, the potential of each of the bit lines BL 0 , ∼, BL i is set substantially to the potential of 1/2V CC when the potential of the data transfer enable signal DTE is changed to the ground potential V SS . Thus, when the potential of the data transfer enable line DTEA is reduced by Vt from the potential of 1/2V CC , the transistors MN 5 and MN7 of each of the sense amplifiers SA 0 through SA i are turned ON. Therefore, capacitances between the source and gates of the transistors MN 5 and MN7 of each of the sense amplifiers SA 0 through SA i are added to the data transfer enable line DTEA. Let's now consider where the gate of the transistor MN 6 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL O , ∼, BL i , the gate of the transistor MN 8 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding bit line of the bit lines BL 0 , ∼, BL i , the transistor MN 5 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding column address line of the column address lines CL 0 , ∼, CL i , and the transistor MN 7 of each of the sense amplifiers SA 0 , ∼, SA i is electrically connected to its corresponding column address line of the column address lines CL 0 , ∼, CL i . When the potential of the SDB is lowered, the potential of one bit line of each of the bit line pairs (BL 0 and BL 0 ), ∼, (BL i and BL i ) is brought to the power source potential V CC . Therefore, either one of the transistors MN 6 and MN 8 of each of the sense amplifiers SA 0 , ∼, SA i is turned ON. As a result, a capacitance is added to the data line SDB . In the fourth embodiment to the contrary, the potentials of the sources of the transistors MN 5 and MN7 of each of the sense amplifiers SA 0 , ∼, SA i are fixed to the ground potential V SS . The gates of the transistors MN 6 and MN 8 of each of the sense amplifiers SA 0 , ∼, SA i are electrically connected to their corresponding column address line of the column address lines CL 0 , ∼, CL i . Since the potential of each of the column address lines CL 0 , ∼, CL i is of the ground potential V SS when the potential of the data line SDB or SDB is changed to the potential reduced by V t from the power source potential V CC , the transistors MN 6 and MN 8 of each of the sense amplifiers SA 0 , ∼, SA i are not turned ON. Thus, no capacitance is added to the data line SDB or SDB at this time. Further, when the potential of the data line SDB is lowered, the potential of each column address line other than the column address line CL j is set to the ground potential V SS . Thus, since the transistors MN 6 and MN 8 of each of the sense amplifiers SA 0 , ∼, SA i other than the sense amplifier SAj are turned OFF, the capacitances of these transistors are not added to the data line SDB . As a result, the potential of the data line SDB is rapidly reduced. Fig. 7 is a fragmentary circuit diagram showing a sense amplifier array employed in a fifth embodiment of the present invention. The fifth embodiment will be described below with reference to Fig. 7. The same elements of structure as those shown in Fig. 6 or the elements of structure similar to those shown in Fig. 6 are identified by like reference numerals and their description will therefore be omitted. In the fifth embodiment, bit line pull-up transistors MN 9 and MN 10 are disposed at plural places within a sense amplifier array so as to correspond to an appropriate number of sense amplifier groups. Thus, when the potential of a data line SDB or SDB is lowered, a path over which the current flows along the data line, is shortened. The resistance is reduced by the shortened path. As a result, the potential of the data line SDB or SDB is not reduced to a potential than required. The semiconductor memory device according to the fifth embodiment can bring about an advantageous effect that it can be activated at high speed, as well as that obtained in the fourth embodiment. In the first through fifth embodiments, the sense amplifier control circuit SAC is provided on the sense amplifier SA 0 side so that the sense amplifier SA 0 be opposed to the sense amplifier SA i . However, the sense amplifier control circuit SAC may be provided on the sense amplifier SA i side. In the first, second and third embodiments, the gates of the NMOS transistors MN 6 of the sense amplifiers SA 0 , ∼, SA i may be connected to their corresponding bit lines BL 0 , ∼, BL i . Further, the gates of the NMOS transistors MN 8 of the sense amplifiers SA 0 , ∼, SA i may be connected to their corresponding bit lines BL 0 , ∼ BL i . Furthermore, the gates of the NMOS transistors MN 5 and MN 7 of the sense amplifiers SA 0 , ∼, SA i may be connected to their corresponding column address lines CL 0 , ∼, CL i . In the second embodiment, the sources of the NMOS transistors MN 5 and MN 7 of the sense amplifiers SA 0 , ∼, SA i are electrically connected to their corresponding sense latch terminal SLNT. However, the sources of the NMOS transistors MN 5 and MN 7 may be connected to the P-channel sense latch enable terminal SPT or the sense latch circuit equalize terminal EQT. In the fourth and fifth embodiments, the drains of the NMOS transistors MN 9 are respectively supplied with the power source potential V CC . The gates of the NMOS transistors MN 9 are electrically connected to the cource potential Vcc and the sources thereof are electrically connected to their corresponding data line SDB. Further, the drains of the NMOS transistors MN 10 are respectively supplied with the power source potential V CC . The gates of the NMOS transistors MN 10 are electrically connected to source potential and the source thereof are electrically connected to their corresponding data line SDB . However, the gates of the NMOS transistors MN 9 and the gates of the NMOS transistors MN 10 may be connected to the power source V CC . Further, the sources of the NMOS transistors MN 9 and the drains of the NMOS transistors MN 10 may be connected to the N-channel sense latch enable terminal SNT. Although the input of the inverter INVO has been connected to the sense latch circuit equalize terminal EQT in the fifth embodiment, the input thereof may be connected to the P-channel sense latch enable terminal SPT. While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description.

Claims: A semiconductor memory device comprising a plurality of memory arrays (AR0, ... , ARm) selectable by a selection signal (AS0, ... , ASm), each array including a plurality of memory cells (MC00, ... , MCim), a plurality of row address lines (WL0, ..., WLm) connected to said memory cells (MC00, ... , MCim), a plurality of pairs of bit lines (BL0, ... , BLi, /Bt0, ..., /BLi) connected to said memory cells (MC00, ... , MCim), a pair of data buses (SDB, /SDB) and a plurality of sense amplifier means (SA0, ..., SAi) each of which is connected to one of said bit line pairs (BL0, ... , BLi, /BL0, ... , /BLi), said sense amplifier means being selectable by a column address signal (CL0, ... , CLi), characterised in that said semiconductor memory device further comprises a data bus pre-charge circuit (MN9, MN10) connected to said data bus pair (SDB, /SDB) for charging the data bus pair (SDB, /SDB) to a first potential, and each of said amplifier means (SA0, ... ,SAi) includes an output circuit (MN5, MN6, MN7, MN8) connected to said data bus pair (SDB, /SDB) and one of said bit line pairs (BL0, ... , BLi, /BL0, ... , /BLi), said output circuit including data transfer transistors (MN5, MN7) having gates connected to one of the bit line pairs (BL0, ... , BLi, /BLi), first terminals connected to supply a second potential different to the first potential, and second terminals connected to said data bus pair (SDB, /SDB), wherein the output circuit included in a selected one of the sense amplifier means within a selected memory array is arranged to selectively supply the second potential to one data bus (SDB or /SDB) of said data bus pair in response to a potential appearing on the connected bit line pair (BL0, /BL0 or BL1, /BL1 or ... , BLi, /BLi), and the output circuit included in each of the non-selected sense amplifier means within the selected memory array and the output circuits within the non-selected memory arrays are arranged so that they do not affect the potential level on said data bus pair (SDB, /SDB). A semiconductor memory device according to claim 1, wherein said first potential is a power supply potential and said second potential is ground potential. A semiconductor memory device according to claim 1 or 2, further comprising a sense amplifier control circuit (SAC) connected to said sense amplifier means (SA0, ... , SAi) for activating said sense amplifier means (SA0, ... , SAi) in response to a sense latch enable signal (SP, SN) and for equalizing said pair of bit lines in response to a sense larch equalizing signal (EQ). A semiconductor memory device according to any one of claims 1 to 3, further comprising a plurality of prie-charge circuits (MN9, MN10) connected to said data bus pair (SDB, /SDB) and disposed at plural places. A semiconductor memory device according to claim 1, further comprising a generating circuit (DTEG) for supplying a data transfer enable signal (DTE) to said output circuit (MN5, MN6, MN7, MN8), wherein the data transfer enable signal (DTE) has the second potential and said output circuit (MN5, MN6, MN7, MN8) supplies the data transfer enable signal (DTE) to one data bus pair (SDB or /SDB) of said data bus pair. A semiconductor memory device according to claim 5, wherein said pre-charge circuit (MN9, MN10) charges said data bus pair (SDB, /SDB) in response to an inverted signal of the data transfer enable signal (DTE). A semiconductor memory device according to claim 6, further comprising a discharge circuit (MN14, MN15) connected to said data bus pair(SDB, /SDB) for charging said data bus pair (SDB, /SDB) to the second potential in response to the data transfer enable signal (DTE). A semiconductor memory dievice according to claim 3, wherein said pre-charge circuit (MN9, MN10) charges said data bus pair (SDB, /SDB) in response to an inverted signal of the sense latch circuit equalizing signal (EQ). A semiconductor memory device according to claim 8, further comprising a discharge circuit (MN14, MN15) connected to said data bus pair (SDB, /SDB) for charging said data bus pair (SDB, /SDB) to the second potential in response to the sense latch circuit equalizing signal (EQ).

Inventors: ISHIMURA TAMIHIRO, MATSUI KATSUAKI, MIYAMOTO SAMPEI, ISHIMURA, TAMIHIRO, MATSUI, KATSUAKI, MIYAMOTO, SAMPEI, Ishimura, Tamihiro, c/o Oki Electric Ind. Co., Ltd, Matsui, Katsuaki, c/o Oki Electric Ind. Co., Ltd., Miyamoto, Sampei, c/o Oki Electric Ind. Co., Ltd.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1995
Main classification: G11C7
IPC codes: G11C11, G11C7