Signal processing circuit

Abstract: A signal processing circuit includes a signal selecting device operative for selecting and outputting one of plural input signals. A filter connected to the signal selecting device filters the signal selected by the signal selecting device with a changeable center frequency of a pass band of the filtering. A frequency changing device is operative for temporarily changing the center frequency when the signal selected by the signal selecting device is changed from one to another. The filter includes, for example, a switched-capacitor filter.

Description: This invention relates to a signal processing circuit according to the preamble of claims 1, 2 and 16 usable in, for example, engine knock control. In a typical knock control of an automotive engine, a knock sensor attached to an engine cylinder block detects vibrations of the engine. The output signal of the knock sensor is processed by a filter to extract signal components which represent engine vibrations in a given frequency band. The peak level of the engine vibrations in the given frequency band is compared with a reference level. The result of this comparison is used in detecting whether or not a knock is present in the engine. A spark timing in the engine is adjusted in response to the result of the knock detection. Generally, in the case of a multi-cylinder engine of a V configuration, plural knock sensors are provided, and the output signals of the knock sensors are processed by plural filters respectively. The total area occupied by the plural filters tends to be large. The plural filters generally cause a complicated structure of an electric circuit for processing the output signals of the knock sensors. A signal processing circuit according to the preamble of claim 1 is known from DE-A-4 201 567 . This document discloses a filter for filtering a respectively selected signal with a changeable center frequency of a pass band of the filtering. Furthermore, the signal processing circuit known from this documents comprises a frequency changing means which is adapted to change the center frequency in proportion to a value which is outputted from the filter and which is calculated by the frequency changing means. A drawback of this known signal processing circuit, however, has to be seen in that each switching from one input signal to another input signal negatively influences the filter characteristics of the newly selected signal due to the settings of the previously selected signal. Therefore, the switching from one input signal to another input signal is delayed in a certain amount. It is the object of the present invention to improve a signal processing circuit according to the preamble of claims 1, 2 and 16, respectively, in such a way that the response time during the selection of another input signal can be shortened without any negative influence to the newly selected input signal. This object, according to the invention, is solved by the advantageous features indicated in the characterizing part of claims 1 , 2 and 16, respectively. By temporarily changing - in response to the selection of another input signal - the center frequency from a first value to a second value which is different from the first value for a predetermined period, the signal processing circuit of the present invention provides a very fast response to the newly selected signal; moreover, any negative influence which goes back to the previously selected signal can be damped so that the newly selected signal is not at all affected thereby. Thus, the present invention provides a signal processing circuit having a fast and optimal switching between successive input signals. Further advantageous measures of the present invention are indicated in the subclaims thereof. In the following, the invention will be described in more detail with reference to the drawings, in which: Fig. 1 is a block diagram of a signal processing circuit according to a first embodiment of this invention. Fig. 2 is a schematic diagram of multiplexers in Fig. 1. Fig. 3 is a schematic diagram of a switched-capacitor filter in Fig. 1. Fig. 4 is a schematic diagram of a signal amplifying circuit in Fig. 1. Fig. 5 is a schematic diagram of a peak hold circuit in Fig. 1. Fig. 6 is a time-domain diagram of response characteristics of the switched-capacitor filter in Figs. 1 and 3. Fig. 7 is a time-domain diagram of a timing of peak detection by the peak hold circuit and a timing of fail detection by a voltage follower circuit in Fig. 1. Fig. 8 is a schematic diagram of a switched-capacitor filter in a signal processing circuit according to a second embodiment of this invention. Fig. 9 is a block diagram of a part of a signal processing circuit according to a third embodiment of this invention. Fig. 10 is a time-domain diagram of a peak hold timing and a reset timing in the signal processing circuit of Fig. 9. DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment With reference to Fig. 1, knock sensors 11 and 12 are followed by a signal processing circuit 13 at least partially formed in an LSI (a large-scale integrated circuit) 14. The output signals of the knock sensors 11 and 12 are processed by the signal processing circuit 13. Multiplexers 15 and 16 (MPX0, MPX1) are provided in a front stage of the signal processing circuit 13. The multiplexer 15 (MPX0) serves as a signal selector. Three adjustment signals (three calibration signals) are fed to the multiplexer 15 (MPX0) via input terminals A/D IN0, A/D IN1, and A/D IN2 of the LSI 14. As shown in Fig. 2, the multiplexer 15 (MPX0) includes switching elements 17 for selecting one of the three adjustment signals. The output terminal of the multiplexer 15 is connected via an analog switch 65 to the input terminal of an 8-bit A/D converter 18 provided in a final stage of the signal processing circuit 13. The adjustment signal selected by the multiplexer 15 can be fed to the A/D converter 18 via the analog switch 65. The switching elements 17 in the multiplexer 15 are controlled by control signals outputted from a control register 62. Also, the analog switch 65 is controlled by a control signal outputted from the control register 62. The multiplexer 16 (MPX1) serves as a signal selector. The multiplexer 16 (MPX1) receives the output signals of the knock sensors 11 and 12 via input terminals A/D IN3 and A/D IN4 of the LSI 14. The multiplexer 16 (MPX1) also receives a predetermined reference voltage AVref- equal to, for example, 2.5 V. As shown in Fig. 2, the multiplexer 16 (MPX1) includes switching elements 24 for selecting one of the sensor output signals and the reference voltage AVref-. During the execution of knock control, one of the sensor output signals is sequentially and cyclically selected by the multiplexer 16 (MPX1) in response to the result of a decision regarding an engine cylinder to be subjected to an igniting process. The signal or the voltage selected by the multiplexer 16 (MPX1) is transmitted to an output terminal SIG OUT of the LSI 14 via a buffer amplifier 19 before being outputted from the LSI 14 via the output terminal SIG OUT. The buffer amplifier 19 prevents the impedance of the multiplexer 16 (MPX1) from adversely affecting a stage following the buffer amplifier 19. The switching elements 24 in the multiplexer 16 are controlled by control signals outputted from the control register 62. A pre-filter 22 including a series combination of a resistor 20 and a capacitor 21 is connected to the output terminal SIG OUT of the LSI 14. The pre-filter 22 is of a low pass type. A signal which has passed through the pre-filter 22 is fed to a switched-capacitor filter (an SCF) 23 in the LSI 14 via an input terminal SIG IN of the LSI 14. Thus, the output signal of the multiplexer 16 (MPX1) is transmitted to the SCF 23 via the pre-filter 22. The pre-filter is an external device with respect to the LSI 14. The SCF 23 executes a sampling process. Accordingly, to avoid foldover or antialiasing distortion (noise) in the SCF 23, it is preferable to band-limit an incoming signal to one-half the sampling clock frequency. The pre-filter 22 executes a desired band limiting process. In the case of knock detection, the cut-off frequency of the pre-filter 22 is preferably set to about 100 kHz. As shown in Fig. 3, the SCF 23 includes an operational amplifier 26 and switched-capacitor integrators 27 and 28. The inverting input terminal of the operational amplifier 26 receives a signal transmitted via the input terminal SIG IN of the LSI 14. The non-inverting input terminal of the operational amplifier 26 receives the reference voltage AVref-. The output side of the operational amplifier 26 is successively followed by the switched-capacitor integrators 27 and 28. As will be made clear later, the SCF 23 is used as a band pass filter. Each of the switched-capacitor integrators 27 and 28 includes capacitors C1 and C2, switching elements SW1 and SW2, and an operational amplifier 29. The switching elements SW1 and SW2 are formed by, for example, C-MOS analog switches. In each of the switched-capacitor integrators 27 and 28, the switching elements SW1 and SW2 are alternately turned on and off in synchronism with a sampling clock signal so that an incoming signal undergoes a filtering process. As shown in Fig. 1, the sampling clock signal used in the SCF 23 is fed from a variable frequency divider 32 in the LSI 14. Specifically, a microcomputer 30 within the LSI 14 has an oscillator 31 which generates and outputs a basic clock signal having a predetermined fixed frequency. The variable frequency divider 32 receives the basic clock signal from the oscillator 31, and converts the basic clock signal to the sampling clock signal through a frequency dividing process. The frequency of the sampling clock signal depends on a frequency division factor in the variable frequency divider 32. The frequency division factor in the variable frequency divider 32 is adjusted by a control signal outputted from the control register 62. Accordingly, the frequency of the sampling clock signal is adjusted in response to the control signal outputted from the control register 62 to the variable frequency divider 32. As shown in Fig. 3, the output terminal of the operational amplifiers 26 leads to a high-pass-filter output terminal HP OUT of the LSI 14. The output terminal of the operational amplifier 29 in the switched-capacitor integrator 27 leads to a band-pass-filter output terminal BP OUT of the LSI 14. The output terminal of the operational amplifier 29 in the switched-capacitor integrator 28 leads to a low-pass-filter output terminal LP OUT of the LSI 14 respectively. A signal resulting from a filtering process by the SCF 23, that is, a filtering-resultant signal, is transmitted via the band-pass-filter output terminal BP OUT. Resistors R1, R2, R3, and R4 for setting filter constants or filter factors are connected to the terminals SIG IN, HP OUT, BP OUT, and LP OUT of the LSI 14 respectively. The resistors R1, R2, R3, and R4 are external with respect to the LSI 14. The characteristics of the band pass filter formed by the SCF 23 are determined as follows. The center frequency "fo" of a pass band of the band pass filter is given by: fo = fclk 2π•C2/C1 • R2 R4 where "fclk" denotes the sampling clock frequency; R2 and R4 denote the resistances of the resistors R2 and R4 respectively; and C2 and C1 denote the capacitances of the capacitors C2 and C1 respectively. The Q factor and the gain H of the band pass filter are given by: Q = R2 R4 • R3 R2 H = R3 R1 where R1 and R3 denote the resistances of the resistors R1 and R3 respectively. It is known that the frequencies of engine vibrations caused by a knock in an engine (that is, the frequencies of an output signal of a knock sensor) have a fundamental frequency and harmonic frequencies. Accordingly, the center frequency "fo" of the pass band of the band pass filter can be made into agreement with the fundamental frequency of the engine vibrations by suitably setting the resistances of the resistors R2 and R4. Further, multiplying the sampling clock frequency "fclk" by an integer can make the center frequency "fo" of the pass band of the band pass filter into agreement with one of the harmonic frequencies of the engine vibrations. The multiplication of the sampling clock frequency "fclk" by an integer can be executed by the variable frequency divider 32. In general, the amplitudes of the engine vibrations at the fundamental frequency and the harmonic frequencies (the amplitudes of the corresponding-frequency components of the output signal of the knock sensor) depend on which of engine cylinders is currently subjected to an igniting process. Accordingly, it is preferable that the center frequency "fo" of the band pass filter is adjusted, in response to which of the engine cylinders is currently subjected to an igniting process, into agreement with one of the fundamental frequency and the harmonic frequencies at which the engine-vibration amplitude is maximized. This designing enables a good signal-to-noise (S/N) ratio of the filtering-resultant signal. The output signal from the SCF 23 follows the input signal to the SCF 23 by a time lag which determines the speed of the response of the SCF 23 to the input signal. The time lag shortens as the center frequency "fo" of the band pass filter rises. As previously described, one of the sensor output signals is sequentially and cyclically selected by the multiplexer 16 (MPX1). Each time the selected sensor output signal is changed from one to the other, the response of the SCF 23 to an incoming signal is temporarily quickened by maximizing (or increasing) the sampling clock frequency "fclk" and thereby increasing the center frequency "fo" of the band pass filter. Specifically, as shown in Fig. 6, during a given short interval "A" immediately after the change of the sensor output signals from one to the other, the response of the SCF 23 to an incoming signal is quickened so that the affection by the previously-selected sensor output signal can be promptly damped. When the given short interval "A" terminates, the sampling clock frequency "fclk" is changed to a given value corresponding to the newly-selected sensor output signal. These processes are reiterated so that the sensor output signals are sequentially and cyclically filtered by the single SCF 23 while preventing the previously-selected sensor output signal from interfering with the filtering of the newly-selected sensor output signal. It should be noted that maximizing (or increasing) the sampling clock frequency "fclk" is executed by the control of the variable frequency divider 32. The filtering-resultant signal is transmitted from the SCF 23 to a signal amplifying circuit 36 within the LSI 14 via the output terminal BP OUT of the LSI 14, a coupling capacitor 35, and an input terminal GIN of the LSI 14. The coupling capacitor 35 is connected between the output terminal BP OUT and the input terminal GIN of the LSI 14, forming an external device with respect to the LSI 14. As shown in Fig. 4, the signal amplifying circuit 36 includes an operational amplifier 37, resistors R1, R2, R3, R4, R5, and R6, and C-MOS analog switches AS1, AS2, AS3, AS4, AS5, and AS6. The inverting input terminal of the operational amplifier 37 is connected to the input terminal GIN of the LSI 14 via an input resistor Rin and a C-MOS analog switch ASin which is continuously closed. The resistors R1-R6 are connected in parallel with each other. The resistors R1-R6 are connected via the analog switches AS1-AS6 to the operational amplifier 37 as feedback resistors respectively. The gain of the signal amplifying circuit 36 can be changed by selectively turning on and off the analog switches AS1-AS6. The resistances of the input resistor Rin and the feedback resistors R1-R6 are set as follows. The resistance of the input resistor Rin is set to a given value R while the resistances of the feedback resistors R1, R2, R3, R4, R5, and R6 are set to given values R, 2R, 4R, 8R, 16R, and 32R respectively. Accordingly, the gain of the signal amplifying circuit 36 can be changed among a factor of 1, a factor of 2, a factor of 4, a factor of 8, a factor of 16, and a factor of 32. Generally, the amplitudes of the sensor output signals vary in the range of several millivolts to several hundreds of millivolts. A wide dynamic range of the signal processing circuit 13 can be attained by selectively turning on and off the analog switches AS1-AS6 in response to the amplitudes of the sensor output signals. It should be noted that the gain of the signal amplifying circuit 36 can be changed by selectively turning on and off the analog switches AS1-AS6. The analog switches AS1-AS6 have certain resistances (on-resistances) when assuming on states, that is, when being closed. Such on-resistances of the analog switches AS1-AS6 are prevented from adversely affecting the values of the gain of the signal amplifying circuit 36 as described below. The on-resistance of the analog switch AS6 is set to a given value Ron while the on-resistances of the analog switches AS1, AS2, AS3, AS4, and AS5 are set to values Ron/32, Ron/16, Ron/8, Ron/4, and Ron/2 respectively. The analog switch ASin connected in series with the input resistor Rin forms a dummy. The on-resistance of the analog switch ASin is set to a value Ron/32. As previously described. the analog switch ASin is held in an on state. When the analog switch AS1 is in its on state and the analog switches AS2-AS6 are in their off states, the gain of the signal amplifying circuit 36 is given as (R+Ron/32)/(R+Ron/32) and is thus equal to a factor of 1. When the analog switch AS2 is in its on state and the analog switches AS1 and AS3-AS6 are in their off states, the gain of the signal amplifying circuit 36 is given as (2R+Ron/16)/(R+Ron/32) and is thus equal to a factor of 2. When the analog switch AS3 is in its on state and the analog switches AS1-AS2 and AS4-AS6 are in their off states, the gain of the signal amplifying circuit 36 is given as (4R+Ron/8)/(R+Ron/32) and is thus equal to a factor of 4. When the analog switch AS4 is in its on state and the analog switches AS1-AS3 and AS5-AS6 are in their off states, the gain of the signal amplifying circuit 36 is given as (8R+Ron/4)/(R+Ron/32) and is thus equal to a factor of 8. When the analog switch AS5 is in its on state and the analog switches AS1-AS4 and AS6 are in their off states, the gain of the signal amplifying circuit 36 is given as (16R+Ron/2)/(R+Ron/32) and is thus equal to a factor of 16. When the analog switch AS6 is in its on state and the analog switches AS1-AS5 are in their off states, the gain of the signal amplifying circuit 36 is given as (32R+Ron)/(R+Ron/32)and is thus equal to a factor of 32. The analog switches AS1-AS6 are connected to the virtual grounding point side, that is, the inverting input terminal, of the operational amplifier 37. Accordingly, the analog switches AS1-AS6 are continuously subjected to a same voltage. Thus, the voltage characteristics of the analog switches AS1-AS6 are prevented from adversely affecting the setting values of the gain of the signal amplifying circuit 36. The amplitudes of the sensor output signals vary in accordance with dynamical conditions such as the rotational speed of the engine. Also, the amplitudes of the sensor output signals vary in accordance with which of the engine cylinders is currently subjected to an igniting process. To compensate for such variations in the amplitudes of the sensor output signals and to attain a wide dynamic range of the signal processing circuit 13, changes of the analog switches AS1-AS6 between the on states and the off states are controlled and hence the gain of the signal amplifying circuit 36 is automatically changed in response to dynamical conditions such as the rotational speed of the engine or in response to which of the engine cylinders is currently subjected to an igniting process. The analog switches AS1-AS6 in the signal amplifying circuit 36 are controlled by control signals outputted from the control register 62. The coupling capacitor 35 is connected between the SCF 23 and the signal amplifying circuit 36. Normally, voltages at the opposite ends of the coupling capacitor 35 are in an equilibrium since they are equal to the voltage at the virtual grounding point of the SCF 23 and the voltage at the virtual grounding point of the signal amplifying circuit 36 respectively. When the center frequency "fo" of the SCF 23 is changed, the voltage at the virtual grounding point of the SCF 23 varies so that the voltages at the opposite ends of the coupling capacitor 35 move out of the equilibrium. To regain the equilibrium, the coupling capacitor 35 is charged (or discharged) as follows. The virtual grounding point (that is, the inverting input terminal) of the operational amplifier 37 is connected to the end of the capacitor 35 via an analog switch 40. The output terminal of the operational amplifier 37 is connected to the virtual grounding point (that is, the inverting input terminal) of the operational amplifier 37 via an analog switch 41. The analog switches 40 and 41 compose a charging (discharging) circuit 42 which acts on the coupling capacitor 35. The analog switches 40 and 41 are normally open. When the center frequency "fo" of the SCF 23 is changed, the analog switches 40 and 41 are closed so that the coupling capacitor 35 is quickly charged (or discharged). Accordingly, it is possible to complete a charging process (or a discharging process) in a short time immediately after the change of the center frequency "fo" of the SCF 23. This designing enables different incoming signals to be successively processed while preventing the coupling capacitor 35 from causing a considerable time lag. The analog switches 40 and 41 in the signal amplifying circuit 36 are controlled by control signals outputted from the control register 62. The output side of the signal amplifying circuit 36 (that is, the output terminal of the operational amplifier 37) is connected to the input terminals of a peak hold circuit (P/H) 45 and a voltage follower circuit 46 for sample hold (S/H). An external hold capacitor 47 is connected to the peak hold circuit 45 via a terminal HOLD of the LSI 14. As shown in Fig. 5, the peak hold circuit 45 includes an operational amplifier 48 serving as a voltage comparator. The peak hold circuit 45 also includes a P-MOS transistor 49 following the operational amplifier 48 and serving as a switch for selectively connecting and disconnecting the hold capacitor 45 to and from a charging power source. A first input terminal of the operational amplifier 48 receives the output signal of the signal amplifying circuit 36 via an analog switch 81. A second input terminal of the operational amplifier 48 receives the voltage across the hold capacitor 47 via an analog switch 85, a resistor 50, and an analog switch 51. When the voltage of the output signal of the signal amplifying circuit 36 is higher than the voltage across the hold capacitor 47, the operational amplifier 48 turns on the transistor 49 so that the hold capacitor 47 is charged. Otherwise, the operational amplifier 48 turns off the transistor 49 to inhibit the hold capacitor 47 from being charged. As a result, the hold capacitor 47 is enabled to hold the peak voltage of the output signal of the signal amplifying circuit 36. The resistor 50 and the analog switch 51 are connected in series, and are provided between the hold capacitor 47 and the transistor 49. The resistor 50 and the hold capacitor 47 compose a post-filter 52 with respect to the SCF 23. The post-filter 52 has a given time constant and serves as a low pass filter which prevents high-frequency noise to be held by the hold capacitor 47. In the case where the time constant of the post-filter 52 is set to a value corresponding to a frequency between an incoming signal frequency and a foldover noise frequency, the signal peak holding function and the signal post-filtering function can be implemented by a single circuit. The peak hold circuit 45 includes analog switches 81, 82, 83, 84, 85, and 86 composing a reset circuit 90. After each A/D conversion process is completed, this circuit 90 resets the voltage across the hold capacitor 47 to a given level by changing the analog switches 81-86 between on states and off states. When the peak voltage is held by the hold capacitor 47, the analog switches 81-86 are in the states of Fig. 5. When the voltage across the hold capacitor 47 is required to be reset, the reset circuit 90 changes the states of the analog switches 81-86 so that the hold capacitor 47 is discharged. Generally, the resetting of the voltage across the hold capacitor 47 can be quickly executed. The analog switches 81-86 in the peak hold circuit 45 are controlled by control signals outputted from the control register 62. As shown in Fig. 5, the voltage follower circuit 46 includes an operational amplifier 53 and an analog switch 54. The operational amplifier 53 receives the output signal of the signal amplifying circuit 36. The operational amplifier 53 is followed by the analog switch 54. The analog switch 54 is controlled by a control signal outputted from the control register 62 (see Fig. 1). The operational amplifier 53 serves as a buffer with respect to the output signal of the signal amplifying circuit 36. A fail judgment (a fail detection) can be made by referring to the output signal of the voltage follower circuit 46. Further, a check of dynamical conditions such as distortion and frequency conditions of an incoming signal can be made by referring to the output signal of the voltage follower circuit 46. As shown in Fig. 1, the hold capacitor 47 is connected to the input terminal of the A/D converter 18 via an analog switch 66. The output side of the voltage follower circuit 46, that is, the analog switch 54 (see Fig. 5), is connected to the input terminal of the A/D converter 18 via the analog switch 66. The analog switch 66 is controlled by a control signal outputted from the control register 62. During the execution of knock control, the peak voltage held by the hold capacitor 47 is transmitted to the A/D converter 18 via the analog switch 66 before being converted into a corresponding digital signal by the A/D converter 18. In the LSI 14, the digital signal representing the peak voltage is transmitted from the A/D converter 18 to the microcomputer 30 via the control register 62 and a data bus 61. By statistically processing the digital signal of the peak voltage, the microcomputer 30 executes a judgment as to whether or not a knock is present in the engine. During the execution of detection of a failure such as a break of electric wires to or in the knock sensors 11 and 12, the analog switch 54 at the output side of the voltage follower circuit 46 is set in an on state so that the output signal of the signal amplifying circuit 36 is transmitted to the A/D converter 18 via the voltage follower circuit 46 and the analog switch 66. The A/D converter 18 is provided with a first section for comparing the output signal of the signal amplifying circuit 36 with a given reference voltage, and a second section for digitally integrating the output signal of the signal amplifying circuit 36 in response to the result of the comparison. A fail detection (a fail judgment) is executed by referring to the result of the integration in a given time. Further, a check on the signal amplifying circuit 36 or a check on the operational amplifier 53 can be executed by setting the analog switch 54 to its on state. Accordingly, it is possible to shorten a check time and enhance a check quality. When the analog switch 54 is in its on state, the output side of the voltage follower circuit 46 is directly connected with the hold capacitor 47. In this case, the resistor provided by the analog switch 54 and the hold capacitor 47 compose a low-pass-type post-filter with respect to the SCF 23. It is preferable that an incoming signal frequency "f", the cut-off frequency "fc(P/H)" of the low pass filter provided by the peak hold circuit 45, the cut-off frequency "fc(S/H)" of the low pass filter provided by the voltage follower circuit 46, and the sampling clock frequency "fclk" related to the SCF 23 have the following relation. fc(P/H) < f < fc(S/H) < fclk As shown in Fig. 7, the peak detection by the peak hold circuit 45 is periodically executed at a timing 1 ○ while the fail detection via the voltage follower circuit 46 is periodically executed at a timing 2 ○ different from the timing 1 ○. The peak detection and the fail detection are alternately executed. As shown in Fig. 1, the signal processing circuit 13 except the pre-filter 22, the resistors R1-R4, the coupling capacitor 35, and the hold capacitor 47 is provided in the LSI 14. Further, the microcomputer 30 is provided in the LSI 14. The microcomputer 30 feeds control signals to the control register 62 via the data bus 61. The operation and the characteristics of the signal processing circuit 13 are controlled in response to the control signals in the control register 62 on a real-time basis. The microcomputer 30 is connected to an engine crank angle sensor (not shown). The microcomputer 30 receives an engine-cylinder discrimination signal and a reference crank angle signal from the engine crank angle sensor. The microcomputer 30 analyzes the engine-cylinder discrimination signal and the reference crank angle signal, thereby generating information of which of the engine cylinders is currently subjected to an igniting process and also information of the rotational engine speed. The microcomputer 30 generates control signals for the multiplexers 15 and 16, the SCF 23, the signal processing circuit 36, the peak hold circuit 45, the voltage follower circuit 46, the A/D converter 18, the frequency divider 32, and the analog switches 65 and 66 in response to the engine cylinder information and the engine speed information. The control signals generated by the microcomputer 30 are transmitted to the control register 62 via the data bus 61 before being stored into the control register 62. The control signals are outputted from the control register 62 to the multiplexers 15 and 16, the SCF 23, the signal processing circuit 36, the peak hold circuit 45, the voltage follower circuit 46, the A/D converter 18, the frequency divider 32, and the analog switches 65 and 66. Accordingly, the signal selection by the multiplexer 15 and the signal selection by the multiplexer 16 are controlled in response to the engine cylinder information and the engine speed information. The variable frequency divider 32 is controlled in response to the engine cylinder information and the engine speed information. Thus, the center frequency "fo" of the pass band of the band pass filter provided by the SCF 23 is controlled in response to the engine cylinder information and the engine speed information. The gain of the signal amplifying circuit 36 is controlled in response to the engine cylinder information and the engine speed information. The quickly charging process by the signal amplifying circuit 36 is enabled and disabled in response to the engine cylinder information and the engine speed information. The selection of one of the peak detection by the peak hold circuit 45 and the fail detection by the voltage follower circuit 46 is controlled in response to the engine cylinder information and the engine speed information. A start and an end of the A/D conversion by the A/D converter 18 are controlled in response to the engine cylinder information and the engine speed information. A start and an end of the comparator conversion for the digital integration by the A/D converter 18 are controlled in response to the engine cylinder information and the engine speed information. Thus, it is possible to implement fine signal processing. As shown in Fig. 1, the LSI 14 includes an I/O port 63 for communication with an external device such as an external microcomputer (not shown). As previously described, the signal processing circuit 13 includes operational amplifiers. In general, the output signal from an operational amplifier has a component corresponding to an offset voltage. Accordingly, offset voltages related to the operational amplifiers in the signal amplifying circuit 36 and the peak hold circuit 45 are superimposed on the peak voltage held by the hold capacitor 47. The offset voltages are compensated or cancelled as follows. During a period different from a time of the execution of the peak detection, the multiplexer 16 is controlled to select the reference voltage AVref-. The reference voltage AVref- is successively processed by the SCF 23, the signal amplifying circuit 36, and the peak hold circuit 45. Thus, in this case, the peak voltage held by the hold capacitor 47 corresponds to the reference voltage AVref-. The peak voltage is transmitted from the hold capacitor 47 to the A/D converter 18 via the analog switch 66, and is then converted into a corresponding digital signal by the A/D converter 18. In this way, the digital signal representing the reference voltage AVref- is generated. Generally, the reference voltage AVref- is chosen to correspond to a null state of a sensor output signal, and hence the generated digital signal represents an offset voltage. The offset-representing digital signal is transmitted from the A/D converter 18 to the microcomputer 30 via the control register 62 and the data bus 61 before being stored into a memory within the microcomputer 30. During the execution of the peak detection, the multiplexer 16 is controlled to select one of the output signals of the knock sensors 11 and 12. The selected sensor output signal is successively processed by the SCF 23, the signal amplifying circuit 36, and the peak hold circuit 45. Thus, in this case, the peak voltage held by the hold capacitor 47 corresponds to the selected sensor output signal. The peak voltage is transmitted from the hold capacitor 47 to the A/D converter 18 via the analog switch 66, and is then converted into a corresponding digital signal by the A/D converter 18. In this way, the digital signal representing the peak voltage of the selected sensor output signal is generated. The peak-representing digital signal related to the selected sensor output signal is transmitted from the A/D converter 18 to the microcomputer 30 via the control register 62 and the data bus 61. The microcomputer 30 subtracts the value indicated by the offset-representing digital signal from the value indicated by the peak-representing digital signal, thereby detecting an accurate peak voltage of the selected sensor output signal which is free from the offset voltage. With reference to Fig. 1, the analog switches 65 and 66 are controlled so that one of the output signal of the multiplexer 15 and the output signal of the peak hold circuit 45 (or the output signal of the voltage follower circuit 46) can be selected and fed to the A/D converter 18. During a check on the A/D converter 18, the analog switches 65 and 66 are set to an on state and an off state respectively so that the output signal of the multiplexer 15 is fed to the A/D converter 18. In the case where the microcomputer 30 requires the feed of engine-type information or other adjustment information (calibration information), the analog switches 65 and 66 are set to the on state and the off state respectively so that the output signal of the multiplexer 15 is fed to the A/D converter 18. During a check on the A/D converter 18, a check signal can be fed to the A/D converter 18 via the multiplexer 15 and the analog switch 65 while being enabled to bypass the SCF 23, the signal amplifying circuit 36, and the peak hold circuit 45. Therefore, the check on the A/D converter 18 can be executed independent of the operation of the SCF 23, the signal amplifying circuit 36, and the peak hold circuit 45. Thus, it is possible to shorten a check time and enhance a check quality. Further, the microcomputer 30 can receive engine-type information or other adjustment information (calibration information) via the multiplexer 15 and the A/D converter 18, and the contents of control by the microcomputer 30 can be automatically adjusted in response to the received information. As previously described, each time the selected sensor output signal is changed from one to the other, the response of the SCF 23 to an incoming signal is temporarily quickened by maximizing (or increasing) the sampling clock frequency "fclk" and thereby increasing the center frequency "fo" of the pass band of the band pass filter provided by the SCF 23. It is understood from the previously-indicated equation (1) that the center frequency "fo" of the pass band of the band pass filter increases as the ratio "C2/C1" between the capacitances of the capacitors C1 and C2 in the SCF 23 decreases. For a finer adjustment of the center frequency "fo" of the band pass filter, the capacitance ratio "C2/C1" may be changed in addition to a change of the sampling clock frequency "fclk". It should be noted that only one of the change of the capacitance ratio "C2/C1" and the change of the sampling clock frequency "fclk" may be executed to adjust the center frequency "fo" of the pass band of the band pass filter. As previously described, after each A/D conversion process is completed by the A/D converter 18, the reset circuit 90 in the peak hold circuit 45 (see Fig. 5) resets the voltage across the hold capacitor 47 to a given level by changing the analog switches 81-86 between on states and off states. Specifically, the microcomputer 30 monitors each A/D conversion process by the A/D converter 18. When the microcomputer 30 detects and confirms an end of each A/D conversion process, the microcomputer 30 outputs an active reset control signal to the control register 62. The control register 62 feeds the active reset control signal to the reset circuit 90 in the peak hold circuit 45. The analog switches 81-86 in the reset circuit 90 are changed in response to the active reset control signal so that the voltage across the hold capacitor 47 is reset to the given level. It should be noted that the signal processing circuit 13 may be applied to various systems other than a knock control system. Further, the multiplexer 16 may select one of three or more sensor output signals. Second Embodiment A second embodiment of this invention is similar to the previously-indicated first embodiment thereof except for design changes described later. The second embodiment includes an SCF 70 which replaces the SCF 23 in the first embodiment. As shown in Fig. 8, the SCF 70 includes an operational amplifier 26 and switched-capacitor integrators 27 and 28. The inverting input terminal of the operational amplifier 26 receives a signal transmitted via an input terminal SIG IN of an LSI 14. The non-inverting input terminal of the operational amplifier 26 receives a reference voltage AVref-. The output side of the operational amplifier 26 is successively followed by the switched-capacitor integrators 27 and 28. As will be made clear later, the SCF 70 is used as a band pass filter. Each of the switched-capacitor integrators 27 and 28 includes capacitors C1, C2a, and C2b, switching elements SW1 and SW2, an operational amplifier 29, and switching elements 71 and 72. The switching elements SW1 and SW2, and the switching elements 71 and 72 are formed by, for example, C-MOS analog switches. In each of the switched-capacitor integrators 27 and 28, the operational amplifier 29 is provided with a feedback circuit having a parallel combination of the capacitors C2a and C2b. Specifically, the capacitor C2b is connected between the inverting input terminal and the output terminal of the operational amplifier 29. One end of the capacitor C2a is connected via the switching element 71 to the inverting input terminal of the operational amplifier 29 while the other end of the capacitor C2a is connected to the output terminal of the operational amplifier 29. The junction between the capacitor C2a and the switching element 71 is connected via the switching element 72 to a line subjected to the reference voltage AVref-. When the switching element 71 is changed to an off state, the switching element 72 is changed to an on state so that the potential at the capacitor C2a will be fixed to the reference voltage AVref-. The switching elements 71 and 72 cooperate to change a capacitance ratio. The switching elements 71 and 72 are changed by control signals outputted from a control register 62 (see Fig. 1). In each of the switched-capacitor integrators 27 and 28, the switching elements SW1 and SW2 are alternately turned on and off in synchronism with a sampling clock signal so that an incoming signal undergoes a filtering process. As shown in Fig. 8, the output terminal of the operational amplifiers 26 leads to a high-pass-filter output terminal HP OUT of the LSI 14. The output terminal of the operational amplifier 29 in the switched-capacitor integrator 27 leads to a band-pass-filter output terminal BP OUT of the LSI 14. The output terminal of the operational amplifier 29 in the switched-capacitor integrator 28 leads to a low-pass-filter output terminal LP OUT of the LSI 14 respectively. A signal resulting from a filtering process by the SCF 70, that is, a filtering-resultant signal, is transmitted via the band-pass-filter output terminal BP OUT. Resistors R1, R2, R3, and R4 for setting filter constants or filter factors are connected to the terminals SIG IN, HP OUT, BP OUT, and LP OUT of the LSI 14 respectively. The resistors R1, R2, R3, and R4 are external with respect to the LSI 14. The characteristics of the band pass filter formed by the SCF 70 are determined as follows. Normally, the switching elements 71 and 72 in each of the switched-capacitor integrators 27 and 28 are in an on state and an off state respectively. Accordingly, in the normal case, both the capacitors C2a and C2b are operatively connected to the related operational amplifier 29, and the center frequency "fo" of the pass band of the band pass filter is given by: fo = fclk 2π•(C2a + C2b)/C1 • R2 R4 where "fclk" denotes the sampling clock frequency; R2 and R4 denote the resistances of the resistors R2 and R4 respectively; and C2a, C2b, and C1 denote the capacitances of the capacitors C2a, C2b, and C1 respectively. In the normal case, the capacitance ratio is given as "(C2a + C2b)/C1". When a selected sensor output signal is changed from one to the other, the switching elements 71 and 72 are changed to an off state and an on state respectively. Accordingly, in this case, only the capacitor C2b is operatively connected to the related operational amplifier 29 and the potential at the capacitor C2a is fixed to the reference voltage AVref-, and the center frequency "fo" of the pass band of the band pass filter is given by: fo = fclk 2π•C2b/C1 • R2 R4 Under these conditions, the capacitance ratio is given as "C2b/C1". Each time the selected sensor output signal is changed from one to the other, the response of the SCF 70 to an incoming signal is temporarily quickened by reducing the capacitance ratio in the SCF 70 from "(C2a + C2b)/C1" to "C2b/C1" and thereby increasing the center frequency "fo" of the pass band of the band pass filter provided by the SCF 70. It should be noted that the sampling clock frequency "fclk" may be increased simultaneously with the reduction of the capacitance ratio in the SCF 70. Third Embodiment Fig. 9 shows a third embodiment of this invention which is similar to the previously-indicated first embodiment thereof except for design changes described later. In the embodiment of Fig. 9, an A/D converter 18 is designed to output a peak hold control signal to a peak hold circuit 45. Specifically, the peak hold control signal is fed to analog switches 81-86 in a reset circuit 90 within the peak hold circuit 45 (see Fig. 5). The reset circuit 90 in the peak hold circuit 45 (see Fig. 5) resets the voltage across a hold capacitor 47 to a given level in response to the peak hold control signal. The A/D converter 18 outputs the peak hold control signal to the peak hold circuit 45 simultaneously with the completion of each A/D conversion process. Accordingly, the voltage across the hold capacitor 47 is promptly reset to the given level upon the completion of each A/D conversion process. After a given reset interval for which the voltage across the hold capacitor 47 is successfully decreased to the given level, the peak hold control signal is removed so that a peak holding process is restarted (see Fig. 10). As understood from the above description, a microcomputer 30 and a control register 62 (see Fig. 1) are excluded from sequence control of an A/D conversion process, a process of resetting the held peak voltage, and a process of starting peak detection. Accordingly, it is possible to sequentially execute an A/D conversion process, a process of resetting the held peak voltage, and a process of starting peak detection without appreciable time lags therebetween.

Claims: A signal processing circuit comprising: signal selecting means (16) for selecting and outputting one of plural input signals (IN3, IN4); a filter (23) connected to the signal selecting means and filtering the signal selected by the signal selecting means with a changeable center frequency of a pass band of the filtering; and frequency changing means (30, 32) for changing the center frequency, characterized in that the frequency changing means is adapted to (30, 32) temporally change the center frequency from a first value to a second value different from the first value for a predetermined period (A) to promptly damp affection by the first signal in response to a selection of the plural input signals by the signal, selecting means, and the frequency changing means is adapted to change the center frequency to a given value different from the second value and corresponding to the signal newly selected by the signal selecting means after the predetermined period. A signal processing circuit comprising: a filter (23) filtering an input signal with a changeable center frequency of a pass band of the filtering; input signal state detecting means (18, 30) for detecting whether or not the input signal changes to a given state in response to a condition change including at least one of an engine speed change and an engine cylinder change; and frequency changing means (30, 32) for changing the center frequency, characterized in that the frequency changing means is adapted to (30', 32) change the center frequency from a first value to a second value different from the first value to promptly damp affection by the first signal when the input signal state detecting means detects that the input signal changes to the given state, and the frequency changing means is adapted to maintain said changing of the center frequency for a predetermined period (A), and the frequency changing means is adapted to change the center frequency to a given value different from the second value after the predetermined period. The signal processing circuit of claim 1, wherein the filter comprises a switched-capacitor filter (23). The signal processing circuit of claim 3, wherein the frequency changing means comprises means (30, 32) for temporarily increasing a sampling clock frequency of the switched-capacitor filter to temporarily change the center frequency in response to the selection of the plural input signals by the signal selecting means (16). The signal processing circuit of claim 3 or 4, wherein the frequency changing means comprises means (30, 32) for temporarily reducing a capacitance ratio in the switched-capacitor filter to temporarily change the center frequency in response to the selection of the plural input signals by the signal selecting means (16). The signal processing circuit of claim 1 or 2, wherein the filter comprises a switched-capacitor filter (23), and further comprising a coupling capacitor (35), and filter signal processing means (36) connected via the coupling capacitor to an output side of the switched-capacitor filter, the filter signal processing means including a circuit (40, 41) for drawing changes from the coupling capacitor. The signal processing circuit of claim 3, further comprising a pre-filter (22) connected between the signal selecting means and the switched-capacitor filter. The signal processing circuit of claim 6, further comprising a peak hold circuit (45) connected to a rear end of the filter signal processing means for holding a peak level of a filter signal, and a post-filter (47, 50) including a combination of a capacitor (47) and a resistor (50), the capacitor including a hold capacitor (47) in the peak hold circuit. The signal processing circuit of claim 8, further comprising a voltage follower circuit (46) connected in parallel with the peak hold circuit, and switch means (54) for selecting one of an output signal from the peak hold circuit and an output signal from the voltage follower circuit, wherein a time constant occurring in selection of the output signal from the peak hold circuit is greater than a time constant occurring in selection of the output signal from the voltage follower circuit. The signal processing circuit of claim 6, wherein the filter signal processing means comprises a signal amplifying circuit (36) including a parallel combination of plural feedback resistors (R1-R6), analog switches (AS1-AS6) connected in series with the feedback resistors respectively, and means (30, 61, 62) for changing a gain by selectively turning on and off the analog switches, and wherein a ratio among on-resistances of the analog switches is inverse with respect to a ratio in gain among resistances of the feedback resistors, and an analog switch (ASin) serving as a dummy is connected in series with an input resistor (Rin) of the signal amplifying circuit. The signal processing circuit of claim 2, further comprising gain changing means (30, 61, 62) for changing the gain of the signal amplifying circuit in response to a result of the detection by the input signal state detecting means. The signal processing circuit of claim 3, wherein the signal selecting means is operative for also selecting a reference voltage as an input signal in addition to the plural signals, and a signal value occurring during selection of the reference voltage is detected as an offset voltage, and wherein the offset voltage is subtracted from a signal value occurring during selection of one of the plural input signals. The signal processing circuit of claim 1 or 2, wherein the filter comprises a switched-capacitor filter (23), the signal processing circuit comprises a coupling capacitor (35) and filter signal processing means (36) connected via the coupling capacitor to an output side of the switched-capacitor filter, the filter signal processing means including a circuit (40, 41) for drawing changes from the coupling capacitor, and a final stage of the filter signal processing means comprises an A/D converter (18), and a signal selector (65, 66) is provided in addition to the signal selecting means, and wherein the signal selector is operative for selecting one of the plural input signals and directly feeding the selected input signal to the A/D converter while enabling the selected input signal to bypass the switched-capacitor filter, the signal amplifying circuit, the peak hold circuit, and the voltage follower circuit. The signal processing circuit of claim 8, wherein the peak hold circuit comprises a reset circuit (90) for discharging the hold capacitor to reset the held peak level. The signal processing circuit of claim 6, further comprising means (30) for controlling a characteristic of the filter signal processing means on a real-time basis in response to conditions including engine cylinder discrimination, an engine speed, and sensor discrimination. A signal processing circuit comprising: a switched-capacitor filter (23) having a variable response time; first means (16) connected to the switched-capacitor filter for changing an input signal fed to the switched-capacitor filter from a first signal to a second signal different from the first signal; and second means (30, 32) connected to the switched-capacitor filter and the first means for changing the response time of the switched-capacitor filter, characterized in that the second means (30, 32) is adapted to shorten the response time of the switched-capacitor filter to promptly damp affection by the first signal when the first means changes the input signal from the first signal to the second signal, and the second means is adapted to maintain the shortened response time for a predetermined period (A), and the second means is adapted to lengthens the shortened response time of the switched-capacitor filter when the predetermined period terminates. The signal processing circuit of claim 16, wherein the second means comprises means (30, 32) for temporarily increasing a sampling clock frequency of the switched-capacitor filter to temporarily change the center frequency in response to the selection of the plural input signals by the first means (16). The signal processing circuit of claim 16 or 17, wherein the second means comprises means (30, 32) for temporarily reducing a capacitance ratio in the switched-capacitor filter to temporarily change the center frequency in response to the selection of the plural input signals by the first means (16). The signal processing circuit of claim 16, further comprising a coupling capacitor (35), and filter signal processing means (36) connected via the coupling capacitor to an output side of the switched-capacitor filter, the filter signal processing means including a circuit (40, 41) for drawing changes from the coupling capacitor. The signal processing circuit of claim 16, further comprising a pre-filter (22) connected between the first means and the switched-capacitor filter. The signal processing circuit of claim 19, further comprising a peak hold circuit (45) connected to a rear end of the filter signal processing means for holding a peak level of a filter signal, and a post-filter (47, 50) including a combination of a capacitor (47) and a resistor (50), the capacitor including a hold capacitor (47) in the peak hold circuit. The signal processing circuit of claim 21, further comprising a voltage follower circuit (46) connected in parallel with the peak hold circuit, and switch means (54) for selecting one of an output signal from the peak hold circuit and an output signal from the voltage follower circuit, wherein a time constant occurring in selection of the output signal from the peak hold circuit is greater than a time constant occurring in selection of the output signal from the voltage follower circuit. The signal processing circuit of claim 19, wherein the filter signal processing means comprises a signal amplifying circuit (36) including a parallel combination of plural feedback resistors (R1-R6), analog switches (AS1-AS6) connected in series with the feedback resistors respectively, and means (30, 61, 62) for changing a gain by selectively turning on and off the analog switches, and wherein a ratio among on-resistances of the analog switches is inverse with respect to a ratio in gain among resistances of the feedback resistors, and an analog switch (ASin) serving as a dummy is connected in series with an input resistor (Rin) of the signal amplifying circuit. The signal processing circuit of claim 16, wherein the first means is operative for also selecting a reference voltage as an input signal in addition to the plural signals, and a signal value occurring during selection of the reference voltage is detected as an offset voltage, and wherein the offset voltage is subtracted from a signal value occurring during selection of one of the plural input signals. The signal processing circuit of claim 19, further comprising a coupling capacitor (35) and filter signal processing means (36) connected via the coupling capacitor to an output side of the switched-capacitor filter, the filter signal processing means including a circuit (40, 41) for drawing changes from the coupling capacitor, and a final stage of the filter signal processing means comprises an A/D converter (18), and a signal selector (65, 66) is provided in addition to the first means, and wherein the signal selector is operative for selecting one of the plural input signals and directly feeding the selected input signal to the A/D converter while enabling the selected input signal to bypass the switched-capacitor filter, the signal amplifying circuit, the peak hold circuit, and the voltage follower circuit. The signal processing circuit of claim 21, wherein the peak hold circuit comprises a reset circuit (90) for discharging the hold capacitor to reset the held peak level. The signal processing circuit of claim 19, further comprising means (30) for controlling a characteristic of the filter signal processing means on a real-time basis in response to conditions including engine cylinder discrimination, an engine speed, and sensor discrimination.

Inventors: ISHIHARA HIDEAKI, SAKISHITA HARUYASU, YAMADA HIROHIKO, ISHIHARA, HIDEAKI, SAKISHITA, HARUYASU, YAMADA, HIROHIKO
Applicants: DENSO CORP, DENSO CORPORATION
Application year: 1995
Main classification: G01L23
IPC codes: H03H19, F02D45, G01L23