Digital signal processing suitable for a non-standard analogue video signal

Abstract: The digital processing apparatus (P1) includes a high speed response PLL (13) that produces a first clock signal (Sc1) locked on the horizontal synchronization signal (H. sync.) included in the video signal (Sv) input thereto. A analog to digital converter (19) converts the input video signal (Sv) with respect to the first clock signal (Sc1) into a digitized video signal (Svc). A write controller (7) controls a video memory (6) to store the digitized video signal (Svc) based on the first clock signal (Sc1). A low speed response PLL (15) produces a second clock signal (Sc2) based on the vertical synchronization signal (V. sync.) included in the video signal (Sv). A read controller (8) controls the video memory (6) to read out the stored digitized video signal (Svc) therefrom based on the second control signal (Sc2). In thus constructed digital processing apparatus (P1) can store and read the digitized video signal (Svc) to and from the video memory (6) stably, enabling to process the video signal (Svc) read out from the video memory (6) effectively and securely.

Description: The present invention relates to a digital processing apparatus for digitizing a source signal for digital recording and, more particularly, to a digital processing apparatus for use in a digital recording apparatus such as a digital video cassette recorder and a digital video disk recorder digital that can digitally record a non-standard video signal. In recent years, various kinds of digital video tape recorders such as called as D1, D2, D3, and D5 types have been developed for the business use. Also for the commercial use, such video cassette recorders (VCR) incorporate a digital circuit for enabling a time axial compensation, and utilize an image compression technology for enabling a digital animation recording. Some of these VCR's have functions for converting a non-standard signal such as a video signal including jitter or pseudo-synchronization signal to a standard signal. In Fig. 12, an example of a time axis compensation apparatus for removing jitter which is disclosed in "Time Base Corrector for Consumer VTR", ITEJ Technical Report Vol. 13, pp. 17-22, VIR '89-8, CE'89-4, August 1989 is shown. This type of signal processing apparatus is popularly referred to as "TBC." A video signal Sv input to a video signal processing (TBC) apparatus Pc through an input terminal 1 is fed to both an analog to digital (A/D) converter 5 and a synchronization signal extractor 2. The extractor 2 extracts a horizontal synchronization signal (H. sync.) and a vertical synchronization signal (V. sync.) to produce a composite synchronization signal Ss. A control signal generator 3 generates a first reference signal Sf1 based on the H. sync. components in the composite signal Ss. This reference signal Sf1 is transferred to a phase locked loop unit (PLL) 4, a write controller 70, and a read controller 80. With respect to the reference signal Sf1, the phase locked loop unit (PLL) 4 produces a clock signal Sc in synchronization with the input video signal Sv. The write controller 70 produces a write control signal Sw based on the clock signal Sc and the reference signal Sf1. The read controller 80 produces a read control signal Sr based on the reference signal Sf1. On the other hand, the A/D converter 5 converts the video signal Sv into a digital format with respect to the clock signal Sc from the PLL 4. Thus digitized video signal Sv is transferred to a video memory 6, and is stored therein based on the control signal Sc from the PLL 4 and the write control signal Sw from the write controller 70. Thus stored data is read out from the video memory 6 based on the read control signal Sr. The data read from the video memory 6 is sequentially transferred to a digital signal processor 9, and is applied with various digital processing such as shuffling, compression, error correction, and modulation. Thus, digital processed video signal is transferred to the externals through an output terminal 10. The control signal generator 3 further generates a second reference signal Sf2 for a servo circuit (not shown) with respect to the vertical synchronization components in the composite synchronization signal Ss. This second reference signal Sf2 is transferred to the externals through an output terminal 11. According to a video signal recording apparatus incorporated with such conventional digital signal processing apparatus Pc, the video signal is encoded with high efficiency, and is recorded or reproduced, as follows. The servo circuit controls the reading and writing head on a predetermined position with respect to the recording medium. Thus, the digitized video signal Sv from the terminal 10 can be recorded in the predetermined area or position of the recording medium such as a magnetic tape, a magnetic disk, or an optical disk. US-A-5 218 449 discloses generating two clock signals both locked on the horizontal sync signal and used for respectively controlling read and write operations from/into a memory. Also, Japanese Patent Application (unexamined) No. H62-249744 (1987) published April 12, 1989 under JP-A-1 093 286 proposes one example of a non-standard video signal conversion apparatus. According to this example, a clock signal having a frequency 4fsc supplied by an oscillator is used for writing a video data to a video memory. Note that "fsc" represents the frequency of a color burst signal. Also a clock signal synchronized with the color burst signal, having a frequency 4fsc, is used for reading the video data from the video memory. Furthermore, a sequential scanning conversion television receiver, for example, is proposed in Japanese Patent Application (unexamined) No. H62-263700 (1987) published April 26, 1989 under JP-A-1 108 895. According to this example, a clock signal having phase locked on the horizontal synchronization signal is used for writing the video data to a video memory. Another clock signal having the phase synchronized with the color burst of the input video signal is used for reading the data from the video memory. Thus, the writing clock signal has the phases locked on the horizontal synchronization signal. In this example, the phase locked clock signal is obtained by a feed forward clock generation circuit that selects a clock every horizontal period, most close to the horizontal synchronization signal, out of a group of delayed clocks. Due to these characteristics of making a real-time response in every horizontal period, the feed forward clock generation circuit can follow even a high frequency jitter, and is widely used for a time base corrector of the video cassette recorder. However, thus constructed conventional digital processing apparatuses described above will be troubled when a non-standard video signal is input thereto. The non-standard video signal means a signal which does not satisfy the requirements of International Radio Consultative Committee (CCIR) for the standard signal, and typically includes: (a) a video signal having a pseudo-synchronization signal; (b) a video signal having a greater jittering; (c) a video signal having horizontal and vertical frequencies having irregular relation to each other; (d) a video signal having a skew in its horizontal signal such as that reproduced by a home use video cassette recorder; and (e) a video signal which is demodulated from a signal having a weak electromagnetic field by a tuner. In case that the reading clock Sr is fixedly locked or synchronized with the color burst signal, it is impossible to match the timing to the vertical frequency of the input video signal Sv. This because that the color burst frequency is strictly controlled in the commercial use field, but the frequencies of horizontal and vertical synchronization signals are not controlled. In other words, there is no correlation between the color burst frequency and the frequency of the vertical synchronization signal. As a result, the number of clocks within one frame is unstable, too much complicated operations are required for controlling the timing to writing the data to the recording media and the timing to applying various processing to the video signal read out from the video memory. Furthermore in the case that either one of reading clock and writing clock is fixedly locked, it is impossible to match the timing between the horizontal frequency and vertical frequency of the input video signal Sv and the frequency of the reading clock signal. Therefore, the variation of data read out from the video memory in relative to the input video signal is too great to execute the signal processing stably. Still further, however, the feed forward clock generation circuit also malfunctions under the weak electromagnetic field. The clock signal thus selected every horizontal period has skews therein. According to this skewed clock signal, it is very difficult to execute the signal processing over plural fields such as a filtering process between the A/D converter and the video memory. This is because each of signal processing should be quitted, and the processed value at that time should be escaped to the register. The present invention has been developed with a view to substantially solving the above described disadvantages. In order to achieve the aforementioned objective, a digital processing apparatus is provided for processing an analog source signal including a first synchronization signal having a first predetermined frequency and a second synchronization signal having a second predetermined frequency smaller than said first predetermined frequency, said apparatus comprises a first reference signal generation means for generating a first reference signal based on said first synchronization signal; a second reference signal generation means for generating a second reference signal based on said second synchronization signal; a first clock signal generation means for generating a first clock signal whose phase is locked on said first reference signal; an analog to digital convertor means for sampling said analog source signal with respect to said first clock signal to generate a digitized source signal; a memory means for storing at least one field of the digitized source signal; a write control means for controlling said memory means to store effective dates of said digitized source signal based on said first and second reference signals and said first clock signal; a third reference signal generation means for generating third and fourth reference signals based on a second clock signal, said third and fourth reference signals each having a predetermined frequency that is a submultiple of that of said second clock signal; a second clock signal generation means for generating said second clock signal synchronized with said second and third reference signals; and a read control means for controlling said memory means to read out said stored digitized source signal therefrom based on said fourth reference signal and said second clock signal. These and other objects and features of the present invention will become clear from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings throughout which like parts are designated by like reference numerals, and in which: Fig. 1 is a block diagram showing a digital processing apparatus according to a first embodiment of the present invention, incorporated in a video signal processing apparatus; Fig. 2 is a graph showing various signals appeared in the digital processing apparatus of Fig. 1; Fig. 3 is an illustration in assistance of explaining the effective data in the video data from the video memory by the digital processing apparatus of Fig. 1; Fig. 4 is a block diagram showing a digital processing apparatus according to a second embodiment of the present invention; Fig. 5 is a block diagram showing a phase converter used in the digital processing apparatus of Fig. 4; Fig. 6 is a graph showing waves appeared in the phase converter of Fig. 5; Fig. 7 is a block diagram showing a digital processing apparatus according a third embodiment of the present invention; Fig. 8 is a block diagram showing a digital processing apparatus according to a fourth embodiment of the present invention; Fig. 9 is a graph showing the composite synchronization signal Ss, the horizontal reference signal Sf1, and the vertical reference signal Sf2 appeared in the digital processing apparatus of Fig. 8; Fig. 10 is a graph showing the signals appeared in the lock detector 158b of Fig. 8; Fig. 11 is a graph showing the signals appeared in the skew detector 158a of Fig. 8; and Fig. 12 is a block diagram showing a conventional digital processing apparatus incorporated in a video signal processing apparatus. First embodiment Referring to Fig. 1, a digital processing apparatus according to a first embodiment of the present invention incorporated in a video signal processing apparatus for digital recording the video signal is shown. The video signal processing apparatus P1 includes an input terminal 1 for receiving a video signal Sv from a signal source separately provided outside. It is needless to say that the video signal Sv can include an audio signal therein. A synchronization signal extractor 2 is connected to the input terminal 1 for receiving the video signal Sv therefrom. The synchronization signal extractor 2 extracts a horizontal synchronization signal (H. sync.) and a vertical synchronization signal (V. sync.) from the video signal Sv to produce a composite synchronization signal Ss. A first control signal generator 12 is connected to the extractor 2 for receiving the composite synchronization signal Ss therefrom. The first control signal generator 12 extracts the horizontal synchronization components H. sync. from the composite sync. signal Ss to produce a first reference signal Sf1 as a horizontal reference signal. The control signal generator 12 further extracts the vertical synchronization components V. sync. from the composite signal Ss to produce a second reference signal Sf2 as a first vertical reference signal. A high speed phase locked loop unit (PLL) 13 is connected to the first control signal generator 12 for receiving the first reference signal Sf1 therefrom. The PLL 13 is constructed by a voltage control oscillator, a frequency divider, a phase comparator, and a low pass filter that are incorporated therein. The frequency divider is used to deliver an output wave whose frequency is a submultiple of a clock signal inputted thereto. The phase comparator compares the phase of the reference signal with that of the output from the frequency divider. The low pass filter extracts the low frequency components in the output from the phase comparator to supply it to the voltage control oscillator. The high speed PLL 13 responds to the high frequency of the horizontal reference signal Sf1, and produces a high speed clock signal Scl as a first clock signal. Thus, the high speed clock signal Scl has the phases synchronized with the horizontal synchronization signal in the input video signal Sv, and can rapidly follow the variation of the horizontal reference signal Sf1. A write controller 7 is connected to the high speed PLL 13 for receiving the high speed clock signal Sc1 therefrom, and is further connected to the first control signal generator 12 for receiving the both reference signals Sf1 and Sf2 therefrom. The write controller 7 calculates an effective data in the video signal Sv based on the vertical and horizontal reference signals Sf1 and Sf2 with respect to the clock signal Sc1. For example, when the video signal Sv conforms to the NTSC system, the effective data corresponds to the range starting from 23 to 262 line, and from 285 to 524 line, and the range from 123 to 842 samples counted from the trailing edge of the horizontal reference signal Sf1. Then, the write controller 7 produces the write signal Sw, indicative of thus calculated effected data. An analog to digital (A/D) converter 5 is connected to the input terminal 1 and the high speed PLL 13 for receiving the video signal Sv and the high speed clock signal Sc1 therefrom, respectively. The A/D converter 5 samples the video signal Sv with respect to the clock signal Sc1 to produce a digitized video signal Svc. A video memory 6 for storing a video data for more than one field is connected to the A/D converter 5 and the write controller 7 for receiving the digitized video signal Svc and the writing signal Sw therefrom, respectively. The video memory 6 stores the video data Svc therein based on the writing signal Sw. A low speed phase locked loop unit (PLL) 15 is connected to the first control signal generator 12 for receiving the vertical reference signal Sf2 to produce a low speed clock signal Sc2 as a second clock signal. The low speed PLL 15 is constructed by a voltage control oscillator for producing a clock signal, a phase comparator for comparing the phases of two signals, and a low pass filter for extracting a low frequency components in the output from the phase comparator to supply thus extracted low frequency components to the voltage control oscillator. A second control signal generator 14 is connected to the low speed PLL 15 for receiving the low speed clock signal Sc2 therefrom. Based on this signal Sc2, the signal generator 14 produces a third reference signal Sf3 as a second vertical reference signal. The signal generator 14 further delays this third reference signal Sf3 by a predetermined period Pd with respect to the second clock signal Sc2 to produce a fourth reference signal Sf4 as a third vertical reference signal. This delaying period Pd is determined according to the capacity of the video memory 6, and is measured by the second clock signal Sc2. The frequencies of these signals Sf3 and Sf4 are submultiples of that of the low speed clock signal Sc2. The signal generator 14 further generates a fifth reference signal Sf5 as a servo reference signal for the servo control with respect to the vertical synchronization signal Sc2. When the digital processing apparatus P1 is incorporated in a digital tape recorder, for example, a servo circuit in the control unit controls the position of reading/writing head relative to the recording medium for recording the digitized video signal Sv to a predetermined area of the medium. The low speed PLL 15 is further connected to the second control signal generator 14 for receiving the third reference signal Sf3 therefrom. The PLL 15 compares the phase of second (vertical) reference signal Sf2 with that of the third (vertical) reference signal Sf3. The PLL narrows the band of these compared signals sufficiently, and constructs a phase locked loop that responds to an error variation slow enough to produce the fourth reference signal Sf4. A read controller 8 is connected to the low speed PLL 15 and the second control signal generator 14 for receiving the low speed clock signal Sc2 and the fourth reference signal Sf4 therefrom, respectively. Based on these signals Sf4 and Sc2, the read controller 8 produces a reading signal Sr. The video memory 6 is further connected to the read controller 8 for receiving the reading signal Sr therefrom. Based on this reading signal Sr, the data is read out from the video memory 6. A digital signal processor 9 is connected to the video memory 6 for sequentially receiving the video data that is read out therefrom. The processor 9 applies various digital processing such as shuffling, compression, error correction, and modulation. Thus, a digitally processed video signal Sv' is produced. A first output terminal 10 is connected to the digital signal processor 9 for transferring thus digital processed video signal Sv' to the externals therethrough. A second output terminal 11 is connected to the second control signal generator 14 for transferring the fifth reference signal Sf5 to a control unit such as a servo circuit on the externals therethrough. In operation, the analog video signal Sv input to the digital processing apparatus 1 through the terminal 1 is supplied to the synchronization signal generator 2 and the A/D converter 5. The generator 2 produces the composite synchronization signal Ss including the horizontal and vertical synchronization components. The first control signal generator 12 applies to the composite signal Ss various processing such as noise removal and timing adjustment, and produces the horizontal and vertical referential signals Sf1 and Sf2. Based on the horizontal reference signal Sf1, the high speed PLL 13 produces the high speed clock signal Sc1 catching up with the variation of the horizontal synchronization signal in the input video signal Sv. On the other hand, the A/D convertor 5 converts the video signal Sv from an analog format into the digital format with respect to the high speed clock signal Sc1 from the high speed PLL 13. The write controller 7 produces the writing signal Sw for the control of data writing operation by the video memory 6 based on the high speed clock signal Sc1 and reference signals Sf1 and Sf2. Based on the writing signal Sw, the video memory 6 stores the digitized video signal Sv as an image data. The low speed PLL 15 and the second control signal generator 14 construct a phase locked loop system, and operate as follows. The second control signal generator 14 produces the third reference signal Sf3 by frequency dividing the low speed clock signal Sc2 outputted from the low speed PLL 15. The phase comparator incorporated in the low speed PLL 15 compares the phases of the signal Sf3 with that of the first vertical reference signal Sf2 outputted from the first control signal generator 12. The output signal from the comparator is further passed though the low pass filter having a sufficiently narrowed band, so that the low speed PLL 15 which can respond to the error variations slow enough to produce the fourth reference signal Sf4. As a result, the low speed clock signal Sc2 that is synchronized with the vertical synchronization signal and well stable with respect to the error variation can be obtained. Based on the fourth reference signal Sf4, the read controller 8 produces the reading signal Sr with respect to the low speed clock signal Sc2. Based on the reading signal Sr, the video memory 6 operates to read out the video data Svc therefrom to the digital signal processor 9. The digital signal processor 9 applies to the video data Svc read out from the memory 6 various digital processes, and then outputs thus processed video data through the first output terminal 10. Note that the fourth reference signal Sf4 is also a reference for the memory 6 to read out the data therefrom, and has an optionally determined period such as one field, one frame, or other. Also, the phase of fourth reference signal Sf4 is different from those of the first vertical reference signal Sf2 or the second vertical reference signal Sf3 by a required amount. When the digital video signal Sv' is output through the first output terminal 10, the servo reference signal Sf5 is output through the second output terminal 11. Based on this servo reference signal Sf5, the positional relationship between the recording head and the recording medium is controlled by a servo control circuit. That servo control circuit is incorporated in a digital signal recording apparatus that encodes the image information data with a high efficiency and records the encoded data to a recording medium, for example, a digital video cassette recorder and a digital video disk recorder. According to this kind of digital signal recording apparatus, the data recording operation is performed as follows. The video data or signal Sv' is fed to the recording head from the video signal processing block based on the information indicative of the current position of the recording head in relative to the medium. As a result, the predetermined portion of image data Sv' through the terminal 10 is recorded to the predetermined area of the recording medium such as tape or disk. Referring to Fig. 2, wave forms of signals Ss, Sf1, Sf2, Sf3, and Sf4 when the digital processing apparatus of the present invention is used for the NTSC system are shown. In this example, although each of signals is shown with respect to the video signal Sv for one frame, the wave forms are substantially the same even when the video signal Sv for one field is used. An shaded area De appeared between the signals Sf2 and Sf3 indicates the effective data area ranges from 23 to 262 line and from 285 to 524 line, wherein the area for the lines 25 to 523 is omitted for the sake of brevity. As apparently shown in Fig. 2, the first vertical reference signal Sf2 has a trailing edge within the equalizing pulses area between the lines 1 to 9. In this example, the trailing edge falls in the line 4. According to this trailing edge of the first vertical signal Sf2, the second vertical reference signal Sf3 also changes from HIGH to LOW. Note that the number pluses in the low speed clock signal Sc2 until the signal Sf3 returns to HIGH is constant regardless of the error variations of the input video signal Sv. The third vertical reference signal Sf4 is delayed by the predetermined delaying period Pd from the second vertical reference signal Sf3, and turns to LOW in the line 9 in this example. This delaying period Pd is usually 20 lines of a frame under the NTSC system. According to the trailing edge of the signal Sf4, the writing signal Sw (not shown in Fig. 2) causes the memory 6 to read out the data therefrom. Referring to Fig. 3, the relationship between the horizontal reference signal Sf1, the high speed clock signal Sc1, and the writing signal Sw around the effective data area, lines 23 and 24 for example, is depicted on a enlarged scale. As described in the above, since input video signal Sv is a non-standard signal, the pulse periods T1 and T2 in the lines 23 and 24, respectively, are not the same. In this example, the high speed clock signal Scl counts 858 clocks for the period T1. Within this period T1, the writing signal Sw controls the video memory 6 to write the data from the A/D converter 5 therein as follows. After passing first 122 clocks, the writing signal Sw controls the memory 6 to store the data for next 720 clocks. Thereafter, the memory 6 is release for the rested 16 clocks. For example, the frequencies of high speed clock signal Sc1 and the low speed clock signal Sc2 are 13.5 MHz and 18 MHz, respectively. As apparent from the above description, the digital processing apparatus P1 according to this embodiment includes the high speed PLL 13 and the low speed PLL 15. The high speed PLL 13 produces the high speed clock signal Scl synchronized with the H. Sync. signal of the input the video signal Sv. The low speed PLL 15 produces the low speed clock signal Sc2 synchronized with the V. sync. signal of the signal Sv. By using the high speed clock signal Sc1, the input analog video signal Sv is converted into the digital signal Svc, and is stored into the video memory 6. By using the low speed clock signal Sc2, thus stored data is read out from the memory 6. As a result, various digital processing of the video signal can be performed securely with a high efficiency, even if the input video signal Sv deviates much from the standard signal as specified by International Radio Consultative Committee (CCIR). Specifically, the clock in the digital signal processor 9 is synchronized with the V. Sync. signal of the input video signal Sv. Therefore, the number of clocks for one field or one frame of the input video signal Sv is kept constant. Usually the number of data in the input video signal Sv is constant for one horizontal scanning period, and for one vertical scanning period. As a result, there is no margin space such as for the blanking period necessary even when digital signal processing such as data compression, error correction coding, and modulation are applied over some fields or frames. Thus, the apparatus' circuits can be used effectively in time-division multiplexing. Furthermore, even when such a non-standard video signal having vertical and horizontal synchronization signals whose rate is beyond the allowable range, or whose vertical synchronization frequency or phases vary strongly, the video memory 6 can absorb such non-standard varying components. The memory 6 cancels such non-standard components by absorption thereof, and stably outputs the image data therefrom. Thus, the processes at the following stations can be securely performed. Note that this memory 6 is also applicable for re-arranging the sequence of video data Sv, and such re-arranging operation is usually referred to as "Shuffling". The shuffling operation can be easily realized as described follows, for example. The high speed PLL 13 is set to produce the first clock signal Scl having the frequency of 13.5 MHz. The luminance signal and color difference signal (Cr, Cb) of video signal Sv are sampled with thus obtained frequency 13.5 MHz and its half frequency 6.75 MHz, respectively. Then, the low speed PLL 15 is set to produce the low speed clock signal Sc2 having the frequency of 18 MHz. The color difference signal multiplexed with respect to the time axis and the luminance signal are respectively written to the video memory 6 based on the high speed clock signal Sc1. By alternately reading the luminance signal and the color difference signal from the memory 6 based on the low speed clock signal Sc2, the data shuffling and the frequency conversion can be performed at the same time. Usually the shuffling operation is applied for one field or one frame of data. However the capacity required for the video memory is less than one field for one field data shuffling and less than one frame for one frame data shuffling. When general-purpose memories available in the current commercial market are used for the video memory 6, it is substantially impossible to use the entire capacity thereof. This is because such general-purpose memories have predetermined capacities such as 1M bits and 4M bits, and are not just what is necessary for the video memory 6. Therefore, a memory having a greater capacity is used for the memory 6, resulting in an excessive margin of unused memory capacity. However, when using the present invention, even such extra or rested margin capacity can be used for absorbing the jitter components in the video signal Sv. Experiments tell that margin capacities sufficient for absorbing jitter components for some tens of horizontal scanning periods are usable. Note that some tens of horizontal scanning period is good enough for a usual time axis compensating apparatus. Herebelow, the jitter absorption enabled by the present invention is described. The digital processing apparatus P1 is a kind of time axis compensating apparatus. The high speed PLL 13 corresponds to the jitters in the input video signal Sv, and the signal free from the jitter components is read out from the memory 6. In a video tape recorder under the analog recording system, the time axis compensation is performed at the time of signal reproduction. However, in the apparatus which records the data in the condition of digital format, the jitter components should be absorbed at the time of analog to digital conversion. Otherwise, the phase information of the horizontal synchronization signal is discarded. Note this phase information is the reference for the jigger detection during the high efficiently encoding operation. Therefore, there will be no measure to detect the jitters at the time of signal reproduction. Furthermore, by making the timing to reading out the video memory 6 being synchronized with the servo control circuit, the variation of timing for reading the video memory 6 and for sending the video data to the recording head can be limited only to the timing of the recording head. Due to this limitation, the margin of the buffer memory can be reduced. When the input video signal Sv is switched to another one, there will be a discontinuity in the phase of vertical synchronization signal thereof. When such discontinued video signal Sv is fed to the servo control circuit, the recording head is incorrectly controlled, and is located at a non-target position. In this case, the data can not be recorded on the recording media. For preventing such mis-operation of the servo control circuit, the response of low speed PLL 15 is set at a reduced rate but at a rate not affecting the response of the servo control circuit. Second embodiment Referring to Fig. 4, a digital processing apparatus according to the second embodiment of the present invention is shown. In this embodiment, the digital processing apparatus P2 has a construction similar to that shown in Fig. 1. However, the digital processing apparatus P2 additionally includes a phase converter 19 inserted between the A/D converter 5 and the video memory 6. Also, a recording unit Ru is additionally connected between the first and second output terminals 10 and 11. Furthermore, the high speed PLL 13 is replaced by a third clock signal generator 52. The third clock signal generator 52 includes a clock oscillator 17 for producing a third clock signal Sc3 having a predetermined frequency and a clock selector 18 connected to the clock oscillator 17 for receiving the signal Sc3 therefrom. The clock selector 18 is further connected to the first control signal generator 12 for receiving the first reference signal generator Sf1 therefrom. Based on the third clock signal Sc3 and the first (horizontal) reference signal Sf1, the clock selector 18 locks the phase of the third clock signal Sc3 on that of the horizontal reference signal Sf1, and produces a phase locked signal as a sixth reference signal Sf6. This six reference signal Sf6 is supplied to the A/D converter 5 instead of the high speed clock signal Scl which is produced by the high speed PLL 13 of Fig. 1. Specifically, a delaying device incorporated in the clock selector 18 delays the third clock signal Sc3 by 50 steps by 2 ns for each step. In other words, fifty pulses of clock signals 50 having phases each preceding to or following the neighboring phases by 2 ns. The clock selector 18 selects one of those fifty pulses whose trailing edge is closest to that of the horizontal reference signal Sf1, and outputs as the third clock signal Sc3. The clock selector 18 continually outputs this selected signal Sc3 for a single horizontal signal that terminates when the next trailing edge of the reference signal Sf1 is inputted thereto. In this sense, the reference signal Sf1 is a skewed horizontal signal. Thus, by the clock oscillator 17 and the clock selector 18 without the voltage control oscillator used in the high speed PLL 13 of Fig. 1, a high speed response PLL which can produce a clock signal Sc3 whose phase locked on the horizontal reference signal can be realized. The phase converter 19 is further connected to the first control signal generator 12, the clock oscillator 17, and the clock selector 18, as best shown in fig. 4, for receiving the signals Sf2, Sf1, Sc3, and Sf6 therefrom, respectively. The phase convertor 19 latches the digitized video signal Svc with respect to the signals Sf1, Sf6, and Sc3 and outputs this latched signal as a latched video signal Svc' to the video memory 6 through the line. Similarly, the phase converter 19 latches the horizontal and vertical reference signals Sf1 and Sf2 with respect to the signals Sf1, Sf6, and Sc3 and outputs these latched signals as latched horizontal and vertical reference Sf1' and Sf2' to the write controller 7, respectively. Referring to Fig. 5, a details of the phase converter 19 is shown. As described above with reference to Fig. 4, the phase convertor 19 converts three signals Svc, Sf1, and Sf2 into the latched signals Svc', Sf1', and Sf2'. For the phase conversion of the video signal Sv, the phase converter 19 has four input terminals 30, 33, 35, and 38 connected to the first control signal generator 12, the signal selector 18, the A/D converter 5, and the clock oscillator 17, respectively. A first phase control signal generator 31 is connected to the terminal 30 for receiving the horizontal reference signal Sf1 therefrom. Based on the signal Sf1, the first phase control signal generator 31 generates a first set (reset) signal St1. Similarly, a second phase control signal generator 32 is connected to the terminal 30, and produces a second set (reset) signal St2. A first frequency divider 34 for halving the frequency of the input signal into halves is connected to the terminal 33 for receiving the sixth reference signal Sf6 therefrom. The divider 34 is further connected to the first phase control signal generator 31 for receiving the set signal Stl therefrom, respectively. The frequency divider 34 divides the frequency of the sixth reference signal Sf6 with respect to the set signal St1 from the first phase control signal generator 31, and produces a seventh reference signal Sf7. A first register 36 is connected to the input terminal 35 and the first frequency divider 34 for receiving the digitized video signal Svc and the seventh reference signal Sf7 therefrom, respectively. The first register 36 latches the digitized video signal Svc with respect to the seventh reference signal Sf7, and produces a first latched video signal Sv1. A second resister 37 is connected to the terminal 35, but is connected to first frequency divider 34 in a reversed manner. Similarly, the second register 37 latches the digitized video signal Svc with respect to the reversed seventh reference signal Sf7, and produces a second latched video signal Sv2. A second frequency divider 39 for halving the frequency of the input signal is connected to the terminal 38 and the second phase control signal generator 32 for receiving the third clock signal Sc3 and the second set signal St2 therefrom, respectively. The frequency divider 39 divides the frequency of the third control signal Sf6 with respect to the set signal St2 from the second phase control signal generator 32, and produces a eighth reference signal Sf8. A selector 40 is connected to the second frequency divider 39, the first register 36, and the second register 37 for receiving the signals Sf8, Sv1, and Sv2, respectively. Based on the eighth reference signal Sf8, the selector 40 selects either one of the first and second latched signals Sv1 and Sv2 to produces a combined latched signal Svs. A third register is connected to the selector 40 and the terminal 38 for receiving the combined video signal Svs and the third control signal Sc3 therefrom, respectively. Based on the control signal Sc3, the selector 41 latches the video signal Svs to produce a latched video signal Svc'. This latched video signal Svc' is transferred to the video memory 6 through an output terminal 42. For the phase conversion of the horizontal reference signal Sf1, the phase converter 19 further includes an input terminal 43, a delay circuit 44, a fourth register 45, and a fifth register 46, and an output terminal 47. The input terminal 43 is connected to the first control signal generator 12 for receiving the horizontal reference signal Sf1 therefrom. The delay circuit 44 is connected to the terminal 43 for receiving to delay the reference signal Sf1 by a predetermined period Td to produce a delayed horizontal reference signal Sf1d. The fourth register 45 is connected to the second frequency divider 39 and the delay circuit 44 for receiving the reversed eight reference signal Sf8 and the delayed signal Sf1d therefrom, respectively. The fourth register 45 latches the delayed signal Sf1d with respect to the reversed reference signal Sf8, and produces a latched signal Sf1r. The fifth register 46 is connected to the terminal 38 and the fourth register 45 for receiving the control signal Sc3 and the latched signal Sf1r therefrom, respectively. The fifth register 46 latches the signal Sf1r with respect to the control signal Sc3, and produces a latched horizontal reference signal Sf1'. This latched signal Sf1' is transferred to the write controller 7 through the output terminal 47. For the phase conversion of the vertical reference signal Sf2, the phase converter 19 further includes an input terminal 47, a delay circuit 48, a sixth register 49, and a seventh register 50, and an output terminal 51 that are substantially the same as an input terminal 43, a delay circuit 44, a fourth register 45, and a fifth register 46, and an output terminal 47. For the sake of brevity, these members 47, 48, 49, 50, and 51 are shown after members 43, 44, 45, 46, and 47, respectively in Fig. 5. Similarly, the delay circuit 48 delays the vertical reference signal Sf2, coming from the first control signal generator 12 through the input terminal 47, by the predetermined period Td, and produces a delayed vertical reference signal Sf2d. The sixth register 49 latches the delayed signal Sf2d with respect to the reversed reference signal Sf8, and produces a latched signal Sf2r. The seventh register 50 latches the signal Sf2r with respect to the control signal Sc3, and produces a latched vertical reference signal Sf2'. This latched signal Sf2' is transferred to the write controller 7 through the output terminal 51. Referring to Fig. 6, various wave forms appeared in the phase converter 19 used for the phase conversion of the video signal Svc are shown. The first phase control signal generator 31 produces the first set signal St1 that changes to "LOW" level at the leading edge of the horizontal reference signal Sf1 and stays thereat for a predetermined period. The first frequency divider 34 produces the seventh reference signal Sf7 by halving the frequency of the sixth reference signal Sf6, but forcibly changes the reference signal Sf7 to "LOW" when the first set signal St1 is "LOW". As a result, the phase of the seventh signal Sf7 is always the same as that of the horizontal reference signal Sf1. The first register 36 latches the digitized video signal Svc, at time t1, with respect to the leading edges of the seventh reference signal Sf7, and produces the first latched video signal Sv1. The second register 37 latches the digitized video signal Svc, at time t1, with respect to the trailing edges of the seventh reference signal Sf7, and produces the second latched video signal Sv2. The second phase control signal generator 32 produces the second set signal St2 that changes to "LOW" level at the leading edge of the horizontal reference signal Sf1 and stays thereat for a predetermined period. The second frequency divider 39 produces the eighth reference signal Sf8 by halving the frequency of the third control signal Sc3, but forcibly changes the reference signal Sf8 to "HIGH" when the second set signal St2 is "LOW". The selector 40 produces the combined video signal Svc by outputting the first latched video signal Sv1 when the eighth reference signal Sf8 is "LOW", and the second latched video signal Sv2 when the signal Sf8 is "HIGH". The third register 41 produces the latched video Svc' by latching the combined video signal Svs with respect to the leading edges of the third clock signal Sc3. When the horizontal reference signal Sf1 is input to the terminal 43, the delay circuit 44 delays the horizontal reference signal Sf1 by the predetermined period Td. Note that this period Td is shorter than the "LOW" level period of the signals St1 and St2. Thus, the delay circuit 44 produces the delayed horizontal reference signal Sf1d. The fourth register 45 latches the signal Sf1d with respect to the trailing edge of the eighth reference signal Sf8, and outputs as the latched signal Sf1r. The fifth register 46 further latches this latched signal Sf1r with respect to the clock signal Sc3, and outputs as the latched horizontal reference signal Sf1' to the terminal 47. As a result, the signal Sf1' output from the terminal 47 has the same chronological relationship with the latched video signal Svc' outputted from the terminal 42. In other words, the block S3 of the video signal Svc' corresponds to the first data after each leading edge of the signal Sf1'. Note that the phase converting operation of the vertical reference signal Sf2 is substantially the same as that for the horizontal reference signal Sf1. Referring back to Fig. 4, the recording unit Ru, for example a digital tape recorder, includes a cylinder 20 mounted with a pair of magnetic heads 21a and 21b. The magnetic heads 21a and 21b of the cylinder 20 is connected to the first output terminal 10 for receiving the final digital video signal Sv' therethrough and to record the signal Sv' on a recording tape 22. The recording tape 22 is guided by a pair of pins 24a and 24b to wind half around the cylinder 20. A driver 23 is connected to the second output terminal 11 for receiving the servo control signal Sf5 therethrough to drive the cylinder 20 and a recording tape 22 so that the magnetic heads 21a and 21b is located on the proper portion of the tape 22. It is needless to say that any other recording apparatus such as a digital video disk that suitable for digital recording can be used as the recording unit Ru. In operation, the composite synchronization signal Ss is transferred to the first control signal generator 12. The first control signal generator generates the horizontal reference signal Sf1 and the first vertical reference signal Sf2. The horizontal reference signal Sf1 is transferred to the third clock signal generator 52 and the phase converter 19. In the third clock signal generator 52, the clock oscillator 17 produces the third clock signal Svc' having the predetermined frequency free from the frequency variation. The clock selector 18 shifts the phase of clock signal Sc3 in synchronization with the phase of the horizontal reference signal Sf1, and produces the sixth reference signal Sf6 following the horizontal varying components in the input video signal Sv. It is to be noted that the signal Sf6 is continual for a single horizontal scanning period, but has a skew therein every time when the horizontal reference signal Sf1 is input to the clock selector 18. This is because the phase shift amount of the signal Sf6 varies on receipt of the signal Sf1, as described in the above. The A/D converter 5 digitizes the video signal Sv with respect to the sixth reference signal Sf6. The phase converter 19 performs the clock conversion for converting the output signal from the A/D convertor 5 that drives based on the signal Sf6 into the continual video signal Svc'. In other words, the clock signal Sf6 is converted into the clock signal Scv' while the timing between the horizontal reference signal Sf1 and the digitized video signal Svc from the A/D converter 5 is kept. Then, the phase converter 19 produces the latched signals Svc', Sf1', and Sf2'. As apparent from the above described, by providing the third clock signal generator 52, and the phase converter 19, the following effect can be obtained, and the digital processing apparatus P2 according to this embodiment is very effective for the following cases. In the case that there is delay between the A/D convertor 5 and the video memory 6 when signal processing such as a digital filtering of band limitation is performed thereto, it may be impossible to transfer the video data. This is caused when the delay of the video data is greater than the blanking period, and the effective video data area overlaps with the skewed point of the sixth reference signal Sf6. However, according to this embodiment of the present invention, the clock of the video signal is converted into the continuous clock signal Svc', resulting in the solution of such overlap with the skewed point. Additionally, the clock signal for the write controller 7 is also converted into a continual signal, enabling the controller 7 to operate more stably. In the case that the input video signal Sv is comprised of a luminance signal (Y signal), color difference signals (R-Y signal, B-Y signal), and/or RGB signal, it is sometimes necessary to monitor the encoded composite signal. For encoding the color signal, a sub-carrier signal having an extremely high frequency stability is required. However, according to this embodiment, by constructing the clock oscillator 17 with a quartz oscillating circuits, a reference signal for generating such sub-carrier signal can be easily obtained. Furthermore, the clocks signal for an encoder's circuit is a continual signal. As a result, a processing block (not shown in Fig. 4) arranged down stream of the phase converter 19 can perform all the required encoding processes. In other words, the analog video image signal can be easily obtained by utilizing the continual clock signal. It is needless to say that all the effects that the first embodiment of the present invention provides are available in this embodiment. Third embodiment Referring to Fig. 7, a digital processing apparatus according to the third embodiment of the present invention is shown. In this embodiment, the digital processing apparatus P3 has a construction similar to that shown in Fig. 4. However, the third clock signal generator 52 is replaced by a fourth clock signal generator 62. The fourth clock signal generator 62 includes the High speed PLL 13 and the clock selector 18. The high speed PLL 13 is connected to the first control signal generator 12, and produces the signal Sc3. The clock selector 18 is connected to the protector 16 and the high speed PLL 13, and produces the signal Sf6. The phase converter 19 is connected to the clock selector 18, the high speed PLL 13, the A/D converter 5, and the first control signal generator 12 for receiving the signals Sf6, Sc3, Svc, and Sf1 therefrom, respectively. According to this embodiment, a feed forward clock type generator is constructed by the clock oscillator 17 and the clock selector 18, and has the following advantage over the conventional PLL that is constructed by using voltage control oscillator: Even when non-standard components such as noises, data lack, skews, and out of phase occurs in the processing signal, the phase disturbance can be limited within a single horizontal period. As a result, the variation of timing for writing the data to the video memory can be minimized. In operation, the first control signal generator 12 compensates the composite synchronization signal Ss for the horizontal and vertical synchronization components when these components are lacking in the signal Ss, and generates the horizontal and vertical reference signals Sf1 and Sf2. The horizontal reference signal Sf1 is transferred to the fourth clock signal generator 62 and the phase converter 19. The vertical reference signal Sf2 is transferred to the low speed PLL 15 and the phase converter 19. The high speed PLL 13 produces the signal Sc3 whose frequency and phase are locked on those of the horizontal reference signal Sf1. The clock selector 18 shifts the phase of signal Sc3 as being synchronized with the phase of horizontal reference signal Sf1, and produces the clock signal Sf6 following the variation of the horizontal synchronization components in the input video signal Sv. Note that the signal Sf6 is continual for a single horizontal scanning period, but has the skew therein every time when the horizontal reference signal Sf1 is input to the clock selector 18. This is because that the phase shift amount of the signal Sf6 varies on receipt of the signal Sf1, as described in the above. The A/D converter 5 digitizes the video signal Sv with respect to the signal Sf6. The phase converter 19 functions the clock conversion for converting the output signal from the A/D convertor 5 that drives based on the signal Sf6 into the continual signal Sc3. In other words, the clock signal Sf6 is converted into the clock signal Sc3 while the timing among the vertical reference signal Sf2, the horizontal reference signal Sf1, and the digitized video signal Svc from the A/D converter 5 is kept. Then, the phase converter 19 produces the second vertical reference signal Sf2', the second horizontal reference signal Sf1', and the video data Svc. The operation of the phase convert 19 is the same as that described with reference to Fig. 4. The second vertical reference signal Sf2 and the second horizontal reference signal Sf1' are supplied to the write controller 7. Then, the write controller 7 produces the control signal Sw for controlling the operation of video memory 6 to write the data therein. This control signal Sw is supplied to the video memory 6. The operations after reading the data from the video memory 6 is performed in the same manner as in the second embodiment. As apparent from the above descriptions, by providing the high speed PLL 13 incorporated with the voltage control oscillator, the clock selector 18, and the phase converter 19, the following effects in addition to the effects of the previously described apparatus P2 can be obtained in this embodiment. For example, when a video tape recorder is set to produce a greater jitter, there will be the following two problems. One is an impact error happening at the time when the tape contacts with the recording/reproducing head. This means a high frequency jitter. The other is a swing in the lateral direction due to the mechanism of the recorder. This means a low frequency jitter, such as 30 Hz, which is a high frequency component occurring during the cylinder of the VCR is rotating at the speed of 1800 rpm according to the VHS. According to the second embodiment, the high frequency jitter can be absorbed by the use of the feed forward clock generation circuit, but the low frequency jitter can not be absorbed. However, according to this embodiment, both these high and low frequency jitter problems can be solved. Fourth embodiment Referring to Fig. 8, a digital processing apparatus according to the fourth embodiment of the present invention is shown. In this embodiment, the digital processing apparatus P4 includes the input terminal 1, synchronization signal extractor 2, A/D converter 5, video memory 6, write controller 7, read controller 8, digital signal processor 9, terminals 10 and 11, first control signal generator 12, second control signal generator 14, low speed PLL 15, phase converter 19, driver 23, and recording unit Ru that are connected to each other to function, as described with reference to Fig. 7. The digital processing apparatus P4 further includes a PLL 150, a signal selector 151, a high speed response locked loop unit 152, a synchronization detector 158 that are connected to the first control signal generator 12 for receiving the horizontal reference signal Sf1 therefrom. The clock signal generator 152 includes the clock oscillator 17 and the clock selector 18. The clock oscillator 17 generates a clock signal Clk3 having a predetermined frequency. The clock selector 18 is connected to the oscillator 17 and the first control signal generator 12 for receiving the clock signal Clk3 and the horizontal reference signal Sf1 therefrom, respectively. The clock selector 18 delays the phase of the clock signal Clk3 with reference to the horizontal reference signal Sf1, and produces a clock signal Clk1. In this sense, the clock signal generator 152 constructs a high speed response PLL. The PLL 150 generates a clock signal Clk2 whose frequency and phase are locked on the horizontal reference signal Sf1. For this purpose, the PLL 150 incorporates a voltage control oscillator, a low pass filter, a phase comparator, and a frequency divider therein. The incorporated phase comparator compares the phase of the horizontal reference signal Sf1 with a signal Vcodiv (Fig. 10) having a frequency of approximately 15.7 KHz, for example, that is a submultiple of the frequency 13.5 Mhz of the clock signal Clk2. Then, the PLL 150 generates a horizontal reference signal Hd2 synchronized with the horizontal reference signal Sf1. Thus generated signals Clk2 and Hd2 are transferred to the signal selector 151 separately. The synchronization detector 158 includes a skew detector 158a and a lock detector 158b. The skew detector 158a detects the presence of skew in a single field of the input video signal Sv based on the horizontal reference signal Sf1. The lock detector 158b is further connected to the PLL 150 for receiving the horizontal signal Hd2 therefrom. Based on the horizontal reference signals Sf1 and Hd2, the lock detector 158b detects that the PLL 150 is locked on the input video signal Sv, or not. Based on the detection results by these detectors 158a and 158b, the synchronization detector 158 produces a synchronization error signal having two levels. This synchronization error signal shows HIGH when unlock or skew is detected by the detectors 158a or 158b. The synchronization detector 158 is connected to the signal selector 151 for supplying the synchronization error detection signal thereto. The signal selector 151 includes a first select switch Sw1 having a first output port O1 connected to the A/D converter 5 and the phase converter 19. The first select switch Sw1 has first and second input ports P1 and F1 connected to the clock selector 18 and the PLL 150 for receiving the signals Clk1 and Clk2 therefrom, respectively. Based on the synchronization error detection signal from the synchronization detector 158, the select switch Sw1 selectively connects the output port O1 to either one of input ports P1 and F1 which are currently receiving the signals Clk1 and Clk2, respectively. Thus a clock signal Sclk1 combining the signals Clk1 and Clk2 is transferred to the A/D converter 5 and the phase converter 19 through the output port O1. The signal selector 151 includes a second select switch Sw2 and a third select switch Sw3 similar to the first select switch Sw1. The second switch Sw2 has a second output port O2 connected to the phase converter 19 and the write controller 7. The switch Sw2 further has third and fourth input ports P2 and F2 connected to the clock oscillator 17 and the PLL 150, respectively. Similarly, the second select switch Sw2 selectively outputs either of the clock signals Clk3 and Clk2, based on the synchronization error detection signal from the synchronization detector 158, as a clock signal Sclk2 to the write controller 7 and the phase converter 19. The third switch Sw3 has a third output port O3 connected to the phase converter 19. The switch Sw3 further has fifth and sixth input ports P3 and F3 connected to the first control signal generator 12 and the PLL 150, respectively. Similarly, the third select switch Sw3 selectively outputs either of the horizontal signals Sf1 and Hd2, based on the synchronization error detection signal from the synchronization detector 158, as a horizontal reference signal Shd to the phase converter 19. The A/D converter 5 converts the inputted video signal Sv into the digitized video signal Svc with respect to the clock signal Sclk1 from the switch Sw1. The phase converter 19 converts the signals Svc, Shd, and Sf2 to the signals Svc', Sf1', and Sf2', respectively, that are synchronized with the clock signal Sclk2. Note that the A/D converter 5, phase converter 19, and the write controller 7 operate in substantially the same manner as previously described with reference to the digital processing apparatus P3 shown in Fig. 7. With reference to Figs. 9, 10, and 11, the operation of the synchronization detector 158 is briefly bellow. In Fig. 9, the wave forms of composite synchronization signal Ss, the horizontal reference signal Sf1, and the vertical reference signal Sf2 are shown. In Fig. 10, the wave forms of signals appeared in the lock detector 158b are shown. In Fig. 11, the wave forms of signals appeared in the skew detector 158a are shown. In operation, the composite synchronization signal Ss is transferred to the first control signal generator 12, and the horizontal and vertical reference signals Sf1 and Sf2 are generated thereby. These three signals Ss, Sf1, and Sf2 have the wave forms, as best shown in Fig. 9. The horizontal reference signal Sf1 having the predetermined frequency, for example 15.7 KHz, is supplied to the PLL 150, the clock signal generator 152, and the synchronization detector 158. As best shown in Fig. 10, the PLL 150 feeds the signal Sf1 to the incorporated phase comparator so as to compare the phase of horizontal reference signal Sf1 having the frequency of approximately 15.7 KHz for example, with the clock signal Vcodiv having 1/858 of the frequency (approximately 13.5 MHz) of the clock signal Clk2. The phase comparator outputs a result signal Pcout. The low pass filter removes the frequency components beyond the responding band from the result signal Pcout, and sends the thus filtered result signal Pcout to the voltage control oscillator. Thus, the PLL 150 generates the clock signal Clk2 that will be supplied to the input ports F1 and F2 of the select switches Sw1 and Sw2, respectively, of the signal selector 151. The PLL 150 further divides the frequency of the clock signal Clk2, and generates the horizontal reference signal Hd2 that will be supplied to the lock detector 158b of the synchronization detector 158, and to the input port F3 of the select switch Sw3 of the signal selector 151. In the clock signal generator 152 constructing the high speed response PLL, the clock oscillator stably generates the clock signal Clk3 having the frequency of 13.5 MHz. The clock selector 18 shift the clock signal Clk3 in synchronization of the leading edge of the horizontal reference signal Sf1, and generates the clock signal Clk1. The clock signal Clk1 is supplied to the input port P1 of the switch Sw1 of the signal selector 151. Herebelow, the operation of the synchronization detector 158 is described. The skew detector 158a detects whether the skewed period in on field of the horizontal reference signal Sf1 is within a predetermined period. When the deviation of detected skewed period for one line ( approximately for the period of 858 clocks of the clock signal having the frequency of 13.5 MHz under the NTSC system) is over ± 3 clocks, the skew detector 158a determines that the signal is skewed. In Fig. 11, when the horizontal reference signal Sf1 input to the skew detector 158a shows the "LOW" level for the successive fifty clocks period in the line no. 518, a signal Hdpoinf turns "HIGH" level. At this time, the skew detector 158a makes an internal counter therein to count up. The internal counter increments the counted value Count within the range from 0 to 857. When the horizontal reference signal is in the line no. 20 and the counted value Count is within the range from 855 to 2, a signal Lockwd is turned to "HIGH" level. The skew detector 158a determines that the horizontal reference signal Sf1 is not skewed in the case that the signal Hdpoint shows "HIGH" while the signal Lockwd is showing "HIGH". The skew detector 158a determines that the horizontal reference signal Sf1 is skewed in the case that the signal Hdpoint shows "HIGH" while the signal Lockwd is showing "LOW". In the left half portion of Fig. 10, the signals when the PLL 150 is locked on the horizontal reference signal Sf1 are shown. The signal Vcodiv is a clock signal produced by the voltage control oscillator to have a submultiple frequency of the clock signal Clk2. The signal Vcodiv has a trailing edge falling within a period when the horizontal reference signal Sf1 shows "LOW" level, as shown in Fig. 10. The internal phase comparator produces the result signal Pcout that shows "HIGH" when the signal Vcodiv shows "HIGH" during the "LOW" level period of the signal Sf1. The result signal Pcout shows "LOW" when the signal Vcodiv shows "LOW" during the "LOW" level period of the signal Sf1. The result signal Pcout that shows an intermediate level between "HIGH" and "LOW" when during the "HIGH" level period of the signal Sf1. In the right half portion of Fig. 10, the signals are shown when the horizontal reference signal Sf1 have a frequency beyond the pull-in range of the PLL 150. In this case, the trailing edge of the signal Vcodiv is almost falling beyond "LOW" level period of the horizontal reference signal Sf1, as shown in Fig. 10. In consideration of the above described conditions, the lock detector 158b determines that the PLL 150 is locked to the input signal Sf1, or not, based on the presence of the trailing edge of signal Vcodiv with respect to the level of the horizontal reference signal Sf1. Note that at the trailing edge of the signal Vcodiv, the signal Lockinf shows "HIGH". In the case that the signal Lockinf shows "HIGH" at a predetermined rate, for example more than 80%, for a unit period of the horizontal reference signal Sf1, the lock detector 158b detects that the PLL 150 is locked. Otherwise, the lock detector 158b detects that the PLL 150 is un-locked. When the detectors 158a and 158b detect both the skewed and un-locked conditions at the same time, the synchronization detector 158 transfers the synchronization error detection signal that showing "HIGH" level to the signal selector 151. On receipt of this "HIGH" signal, three select switches Swl, Sw2, and Sw3 select the input ports P1, P2, and P3, respectively. When the detectors 158a and 158b detect non skew and lock, the synchronization detector 158 transfers the synchronization error detection signal that showing "LOW" level to the signal selector 151. On receipt of this "LOW" signal, three select switches Sw1, Sw2, and Sw3 select the input ports F1, F2, and F3, respectively. The A/D converter 5 digitizes the video signal Sv with respect to the clock signal Sclk1 from the switch Sw1. The phase converter 19 is supplied with the signals Shd, Sclk1, Svc, Sclk2, Shd, and Sf2 to the input terminals 30, 33, 35, 38, 43, and 47, respectively. The operation by other members of the digital processing apparatus P4 is substantially the same as that according to the third embodiment of the present invention. As apparent from the above descriptions, by providing the synchronization detector 152 and the signal selector 151, the following effects in addition to the effects of the apparatus P3 can be obtained in this embodiment. For example, when the horizontal reference signal Sf1 is extracted from the video signal Sv outputted by a tuner working under a weak electromagnetic field, this signal Sf1 is very sensitive to the noise components contained in the video signal Sv. Due to these noise components, the clock selector shifts the phase of clock signals to an incorrect position. As a result, the horizontal reference signal also deviates from the correct position, causing a greater degradation in the image reproduced from the video signal Sv. When the clock selector is used on a reproducing side of a video tape recorder, the user can recognize the influence of the noise on the clock selector according the quality of reproduced image. In such a case that the reproduce image is so degraded, the user can cancel the function of the clock selector for better image reproduction. However, when the clock selector is used on the recording side of the video tape recorder, the user can not cancel the function of the clock selector even when employing the digital processing apparatus P3 according to the third embodiment of the present invention. To solve these problems, the digital processing apparatus P4 according to this embodiment can be used. Accordingly, when the video signal (Sf1) is free from the skew and frequency variation, the horizontal reference signal and clock signal generated by a PLL having a crystal incorporated voltage control oscillator to have an extremely stable frequency are used for the following digital processing of the video signal. As a result, an image having a very improved quality can be reproduced even if it was acquired under the weak electromagnetic field conditions. Furthermore, when a video signal having greater skews is inputted to the digital processing apparatus, the response time of the PLL becomes greater than the vertical blanking period of the television signal. In this case, the PLL can not follow the skews in the video signal. For processing even such skewed video signal, the clock signal generated by the clock selector is more suitable and enabling to prevent the reproduced image from distorting in the horizontal direction. According to the fourth embodiment, a video signal acquired under the weak electromagnetic field conditions or a non-standard video signal having jitter can be recorded and reproduced under very stable conditions. It is to be noted that by providing the synchronization detector 158 constructed by both the skew detector 158a and the lock detector 158b, it is possible to design the PLL 150 in more consideration of the jitter suppression, resulting in an enhancement of the anti-weak electromagnetic field characteristics. In other words, the response time to skewed video signal can be negligible. In this sense, only the lock detector 158b without the skew detector 158a is effective. Furthermore, the voltage control oscillator incorporated in the PLL 150 can be constructed by utilizing various components such as crystal and LC resonant units. The clock selector 18 can select the clock signal with respect to the leading edge instead of the trailing edge. The skew detector 158b can detect the presence of skew in the horizontal reference signal Hd2 instead of the first horizontal reference signal Sf1. The lock detector 158a can be constructed to detect the locked condition of the signal in a manner other than described in the above. The clock signal Clk2 instead of the output signal from the clock oscillator 17 can be supplied to the clock selector 18, as performed in the third embodiment.

Claims: A digital processing apparatus (P1) for processing an analog source signal (Sv) including a first synchronization signal (H. sync.) having a first predetermined frequency and a second synchronization signal (V. sync.) having a second predetermined frequency smaller than said first predetermined frequency, said apparatus comprising: a first reference signal generation means (2 and 12) for generating a first reference signal (Sf1) based on said first synchronization signal (H. sync.); a second reference signal generation means (2 and 12) for generating a second reference signal (Sf2) based on said second synchronization signal (V. sync.); a first clock signal generation means (13) for generating a first clock signal (Sc1) whose phase is locked on said first reference signal (Sf1) ; an analog to digital convertor means (5) for sampling said analog source signal (Sv) with respect to said first clock signal (Sc1) to generates a digitized source signal (Svc); a memory means (6) for storing at least one field of the digitized source signal (Svc); a write control means (7) for controlling said memory means (6) to store effective data of said digitized source signal (Svc) based on said first and second reference signals (Sf1, Sf2) and said first clock signal (Sc1); a third reference signal generation means (14) for generating third and fourth reference signals (Sf3 and Sf4) based on a second clock signal (Sc2), said third and fourth reference signals (Sf3 and Sf4) each having a predetermined frequency that is a submultiple of that of said second clock signal (Sc2) ; a second clock signal generation means (15) for generating said second clock signal (Sc2) synchronized with said second and third reference signals (Sf2 and Sf3); and a read control means (8) for controlling said memory means (6) to read out said stored digitized source signal (Sv') therefrom based on said fourth reference signal (Sf4) and said second clock signal (Sc2). A digital processing apparatus (P2) as claimed in Claim 1, further comprising a recording means (9, Ru, 23) for recording said read digitized source signal (Sv') to a recording medium (22). A digital processing apparatus (P1) as claimed in Claim 1, wherein said memory means (6) can rearrange the order of said digitized data stored therein. A digital processing apparatus (P1) as claimed in claim 1, wherein when said analog source signal comprises a luminance signal and a color difference signal said memory means (6) can convert the frequency of luminance signal data and color difference signal data by changing the frequency of signals on which said memory means (6) stores and reads out said digitized data (Svc). A digital processing apparatus (P1) as claimed in Claim 2, wherein said second control signal generator (14) produces a servo signal (Sf5) for controlling said recording unit (Ru) with respect to said recording medium (22).

Inventors: HASHIMOTO KIYOKAZU, HIDAKA IWAO, KASHIRO TAKAO, OKA HIDEMI, YAMAMOTO YOSHIKI, YAMAUCHI EIJI, HASHIMOTO, KIYOKAZU, HIDAKA, IWAO, KASHIRO, TAKAO, OKA, HIDEMI, YAMAMOTO, YOSHIKI, YAMAUCHI, EIJI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1995
Main classification: H04N5
IPC codes: H04N5