Method and apparatus for programming memory devices

Abstract: A method for programming an integrated memory circuit and an integrated memory circuit structure for storing information are disclosed. The method of programming includes the steps of providing a program mode for programming the memory cells in accordance with a number of the bits of the input data pattern; and programming the memory cells in accordance with the program mode. The integrated memory circuit includes a program mode determining circuit, and a programming circuit operatively coupled to the program mode determining circuit for programming each of a plurality of block of memory cells according to its respective program mode. The program mode determining circuit comprises a circuit for determining the total number of memory cells that is required to be programmed in each block and a control circuit operatively coupled to the memory cells determining circuit for providing a first program mode control signal, a plurality of second program mode control signals and a third program mode control signal, if the total number of memory cells that are required to be programmed in a block is greater than zero but is less than or equal to a threshold number N, greater than the threshold number N, and equal to zero, respectively. Through the use of the programming method and the integrated memory circuit design, the requirement of additional number or increased current capacities of drain pumps associated with programming the integrated circuit is eliminated which reduces design complexity and minimizes the size of the integrated circuit.

Description: The present invention is generally related to an electrically programmable memory device and more specifically, to a method and apparatus for programming flash EPROMs. Flash EPROMs (erasable programmable read only memories) are a growing class of non-volatile storage integrated circuits. These flash EPROMs have integrated memory cells which can be electrically erasable, programmable or readable. The entire array can be simultaneously erased electrically. The flash EPROM can also be randomly read or written. The cells themselves use only a single device per cell and are formed using so-called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide or other insulating material, and insulated from the control gate word line of the transistor by a second layer of insulating material. The act of charging the floating gate is termed the "program" step for a flash EPROM. This is accomplished through a so-called hot-electron injection by establishing a large positive voltage between the gate and source, as much as 12 volts, and a positive voltage between the drain and source, for instance, 6 volts. A drain pump supplies the current needed to program the memory cells. The act of discharging the floating gate is called the "erase" function for a flash EPROM. This erasure function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase). For instance, a source erase operation is induced by establishing a large positive voltage from the source to gate, while floating the drain of the respective memory cell. This positive voltage may be as much as 12 volts. A problem encountered with the conventional way in which flash EPROM cells are programmed is the large amount of current required for programming a high density flash EPROM memory device. A typical flash EPROM memory device has 1 million bits (megabits or Mbit) of memory cells organized as 128 thousand (K) bytes of 8 bits each. Typically, all 8 bits are programmed at the same time. When the voltage supplied to the integrated circuit is at 12 volts, it will be high enough to provide the current needed to program the memory cells. As the personal computer industry is progressing towards size reduction and mobile computing, notebook and subnotebook computer applications become very popular. In these applications, power consumption is a concern since batteries are typically used to supply electrical power to notebook and subnotebook computers. It is known that an integrated circuit which uses a lower supply voltage consumes less power. Therefore, most of the integrated circuits used for these applications are designed to work with a lower supply voltage. Accordingly, there is a growing demand for memory devices that have supply voltage lower than the 12 volts previously used. Nowadays, the supply voltage is being reduced to 5 volts and is expected to be further reduced to 3.3 volts in the near future. When the supply voltage is at 5 volts or below, a drain pump is required to pump up the supply voltage so that there is sufficient current to program up to 8 bits of memory cells simultaneously. Further, as the microprocessor technology advances, higher density flash EPROM memory devices are required. The industry's demand is towards requiring flash EPROMs having storage capacity of 4Mbit and 16Mbit, organized as 256K words of 16 bits each and 1 million words of 16 bits each respectively. In these flash EPROMs, 16 bits of memory cells may have to be programmed at one time thus doubling the current requirement as compared to the programming of only 8 bits of memory cells simultaneously in previous devices. There has been an attempt to solve the problem of delivering more current to 4Mbit or 16Mbit devices by doubling the number of drain pumps or increasing the size of the existing drain pumps so as to increase their current capacities. While using more drain pumps or increasing the current capacity of drain pump will be able to supply adequate current to 4Mbit or 16Mbit memory devices, it undesirably adds complexity to the design of the integrated circuits. Besides, increasing the number of drain pumps or increasing the size of the drain pump increases the overall size of the integrated circuit where the flash EPROM resided. Further, as the demand for higher density flash EPROM memory device grows, there is an expectation that the number of bits to be programmed will continue to increase and a better way of providing the current needed for such high density devices is necessary. Hence, there is a need to have a method and an apparatus for programming high density flash EPROM memory devices with low supply voltage without undesirably increasing the complexity of the design and the size of the integrated circuit. The present invention addresses such a need. US-A-4,763,305 discloses a programmable memory having a byte program mode in which a new byte is written into the memory only after comparing the new data with the existing data in the byte. If the new data is the same as the old data, the conventional erase/program cycle is omitted. According to a first aspect of the present invention there is provided a method for controlling the programming of an integrated memory circuit, the method being as defined in claim 1 of the appended claims. In a preferred embodiment of the invention the number of cells that is required to be programmed in a selected block is determined by comparing the logic level of each bit of the input data pattern addressed to the selected block with the logic level of each corresponding bit stored in the memory cells in the selected block, and then summing the total number of bits of the input data pattern addressed to the selected block that are at the first logic level. The means for supplying a selected group of memory cells with a programming voltage preferably comprises at least one drain pump. Advantageously, programming is achieved without unnecessarily increasing the size of the integrated circuit and/or the size of the drain pump when the number of memory cells that is required to be programmed increases. According to a second aspect of the invention there is provided an integrated memory circuit as defined in claim 8 of the appended claims. Through this programming method or circuit design, a high density integrated memory circuit can be efficiently programmed without having to increase the number and/or the size of the drain pumps formed on the integrated circuit, thus keeping the size of the integrated circuit to a minimum. This method or system adds minimal additional hardware and does not appreciably affect the programming time of the memory circuit. In the accompanying drawings, by way of example only: Figure 1 is a simplified block diagram of an integrated memory circuit constructed in accordance with the present invention. Figure 2 is a schematic circuit diagram of an analog adding circuit used to implement the summing circuit of Figure 1. Figure 3 is a flow chart showing a preprogram verification operation in accordance with the present invention. Figure 4A is a flow chart showing a two-cycle or low byte programming operation. Figure 4B is a flow chart showing one-cycle or word programming operation. Figure 5 is a flow chart showing a postprogram verification operation. The present invention relates to a method and an integrated memory circuit for programming high density memory cells without undesirably increasing the number or the size of drain pumps formed on the integrated circuit. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the generic principles which are accompanied in this embodiment may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the scope of the appended claims. Figure 1 illustrates an integrated memory circuit 100 constructed in accordance with the present invention. The integrated memory circuit 100 is responsive to an input data pattern DQ n (DQ 0 to DQ 15 ) which has 16 bits of information. Each bit is either at a first logic level or a second logic level. For the purpose of illustration, the first logic level is assumed to be a logic 0, while the second logic level is assumed to be a logic 1. The input data pattern DQ n is separated into two bytes, a low byte DQ na (DQ oa to DQ 7a ) which represents the 0th to 7th bits and a high byte DQ nb (DQ 8b to DQ 15b ), which represents the 8th to 15th bits. The integrated memory circuit 100 includes a matrix of programmable memory cells. Each memory cell is used for storing 1 bit of information. The matrix of memory cells are organized into a plurality of blocks, and each block includes 2 groups of memory cells and each group includes 8 memory cells. In the case of a 4 Mbit flash EPROMS organized as 256 K words of 16 bits each, each word is equivalent to one block; i.e., there are 256 K blocks. Each block is further divided into 2 groups of 8 bits each. Each bit is represented by 1 memory cell. For the purpose of illustration, Figure 1 only shows 1 block of memory cells 110. Memory cells block 110 includes 2 groups of memory cells 110a and 110b. Memory cells 110a and 110b each includes 8 memory cells. For the purpose of this embodiment, when a memory cell is erased, it will be at logic 1. When a memory cell is programmed, it will be at logic 0. The integrated memory circuit 100 further includes a program mode determining circuit 112 for determining a program mode for programming block 110 in accordance with a number of the bits of the input data pattern DQ n and a programming circuit 113 operatively coupled to the program mode determining circuit 112 for programming block 110 according to its respective program mode. In this embodiment, the number of the bits of the input data pattern DQ n chosen for the purpose of program mode determination is 8, which is the number of memory cells a typical drain pump residing on the integrated memory circuit is able to supply simultaneously during programming. The program mode determining circuit 112 includes a memory cell determining circuit 114 for determining the total number of memory cells that is required to be programmed in block 110 and a control circuit 116 operatively coupled to the memory cell determining circuit 114 for providing a first program mode control signal if the total number of memory cells that is to be programmed in block 110 is greater than zero but is less than or equal to 8, a second program mode if the total number of memory cells that is required to be programmed in block 110 is more than 8, and a third program mode control signal if the total number of memory cells that is required to be programmed in block 110 is equal to zero. The memory cell determining circuit 114 includes a first comparator circuit 118, a second comparator circuit 120 and a summing circuit 122. The first comparator circuit 118 is used for comparing the logic level of each bit of the input data pattern DQ n addressed to block 110 with the logic level of each of the memory cell in block 110. The second comparator circuit 120 is used for comparing the logic level of each bit of the input data pattern DQ n with the logic level of each corresponding bit stored in the memory cells, 110a and 110b, and providing a modified input data pattern DIM na (DIM 0a to DIM 7a ) and DIM nb (DIM 8b to DIM 15b ). When a bit of the memory cells 110a (or 110b) and the corresponding bit of the input data pattern DQ na (or DQ nb ) are both at logic 1, the corresponding bit of the modified input data pattern DIM na (or DIM nb ) will be at logic 1. This indicates no programming is required for that bit. When a bit of the memory cells 110a (or 110b) and the corresponding bit of the input data pattern DQ na (or DQ nb ) are both at logic 0, the corresponding bit of the modified input data pattern DIM na (or DIM nb ) will be at logic 1. Again, this indicates no programming is required for that bit. When a bit of the memory cells 110a (or 110b) is at logic 1 and the corresponding bit of the input data pattern DQ na (or DQ nb ) is at logic 0, the corresponding bit of the modified input data pattern DIM na (or DIM nb ) will be at logic 0. This indicates that programming is required for that bit. Input data patterns DQ na and DQ nb are being applied to the second comparator 120. The second comparator 120 then generates data patterns DI na and DIM na . DI na is identical to DQ na and will be indicated as input data pattern in this embodiment. DIM na is a modified input data pattern as explained above. The second comparator 120 also provides data patterns DI nb and DIM nb . Similarly, DI nb is identical to DQ nb and will be indicated as input data pattern in this embodiment. DIM nb is a modified input data pattern as explained above. DI na is coupled to the first comparator circuit 118 through line 124a. DI na or DIM na is selectively coupled to the summing circuit 122 through a selective switch 126a in the second comparator 120 across line 128a. Similarly, DI nb is coupled to the first comparator circuit 118 through line 124b and DI nb or DIM nb is selectively coupled by switch 126b on line 128b to the summing circuit 122. Summing circuit 122 can be implemented by a digital adding circuit or an analog adding circuit. A typical digital adding circuit comprises a plurality of half and full digital adders to provide logical addition by summing the bits of the input data patterns DI na and DI nb or the modified input data patterns DIM na and DIM nb that are at logic 0. In this embodiment, 7 half digital adders and 19 full digital adders are used to accomplish the logic addition. A discussion on the implementation of digital adding circuit may be found in a book entitled "Circuit Design for CMOS VLSI," 1992, Pages 322-328, by John Uyemura. In contrast, a typical analog adding circuit sums the current through a plurality of transistors. In this embodiment, analog adding circuits are preferred because it is found that implementation of analog adding circuits here takes up less area on the integrated memory circuit than digital adding circuits. The summing circuit 122 computes the total number of bits of memory cells 110a and 110b that is required to be programmed by selectively summing the total number of bits of the input data patterns DQ na and DQ nb or the corresponding modified input data patterns DIM na and DIM nb addressed to block 110 that are at logic 0 and then produces output signal X16PGM. The X16PGM signal will be at logic 1 when the number of memory cells that is required to be programmed is greater than zero but is less or equal to 8 and logic 0 when the total number of memory cells that is required to be programmed is greater than 8. Signal X16PGM couples to control circuit 116 on line 130. The first comparator circuit 118 outputs signals LBMATCHP and HBMATCHP to control circuit 116 across lines 132a and 132b respectively. Control circuit 116 provides signal LBPGM and signal HBPGM to the second comparator circuit 120 across lines 134a and 134b respectively. Control circuit 116 provides a MATCH signal when the content of the memory cells 110a and 110b matches the contents of the input data pattern DQ n . The programming circuit 113 couples to drain pump 136. Drain pump 136 is coupled to a power supply VCC, typically at 5 volts. Memory cells 110a and 110b couple to a plurality of decoders 138a and 138b respectively. Decoders 138a and 138b couple to the programming circuit 113 via lines 140a and 140b respectively. Decoders 138a couple memory cells 110a through a first plurality of sense amplifiers 142a to the first comparator circuit 118. Similarly, decoders 138b couple memory cells 110b through a second plurality of sense amplifiers 142 b to the first comparator circuit 118. Sense amplifiers 142a and 142b provide data pattern DSI na and DSI nb respectively. Data pattern DSI na and DSI nb represent the contents of memory cells 110a and 110b respectively. Data pattern DSI na and DSI nb are being coupled to the second comparator circuit 120 on lines 144a and 144b respectively. The programming of integrated memory circuit 100 comprises three operations, namely a preprogram verification operation, a programming operation, and postprogramming verification operation. Immediately prior to the preprogram verification operation, memory cells 110a and 110b are assumed to have been fully erased, that is, they are all at logic 1. Referring to Figure 2, which is a detailed circuit diagram of an analog adding circuit used to implement summing circuit 122. Summing circuit 122 uses the principle of a differential comparator circuits to provide for current summation. Summing circuit 122 comprises a plurality of transistors 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, 232, 234, 236, 238 and 240 coupled in parallel. The drain terminal of the plurality of transistors 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, 232, 234, 236, 238 and 240 is coupled to a node 244 and a driver/buffer circuit 241. The gate terminal of each of the plurality of transistors 210, 212, 214, 216, 218, 220, 222 and 224 is respectively coupled to bit 0, 1, 2, 3, 4, 5, 6 and 7 of the input data patterns DI na or the modified input data pattern DIM na . Similarly, the gate terminal of each of the plurality of transistors 226, 228, 230, 232, 234, 236, 238 and 240 is respectively coupled to bit 8, 9, 10, 11, 12, 13, 14 and 15 of the input data pattern DI nb or the modified input data patterns DIM nb . The source terminal of each of the plurality of transistors 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, 232, 234, 236, 238 and 240 is coupled to the drain terminal of a current source transistor 247. Current source transistor 247 has its gate terminal coupled to a voltage VBIAS and its source terminal coupled to power supply voltage VCC. Current source transistor 247 acts as a constant current source for the summing circuit 122. Each one of the plurality of transistors is turned on to allow current through the transistor when the corresponding bit coupled to the gate of that transistor is at logic 0. The total current through the plurality of transistors, which is dependent on the total number of transistors being turned on, is then summed at point 244. Next, the corresponding total voltage drop due to the total current is compared with a reference voltage V1 generated by a reference voltage generator 246 and an output signal 248 is provided via node 244 and driver/buffer circuit 241. In this embodiment, the reference voltage V1 is selected such that the output signal 248 will be at logic 0 and logic 1 when the total number of logic 0 bits of the input data patterns DI na and DI nb (or the modified input data patterns DIM na and DIM nb ) is greater than 8 and less than or equal to 8 respectively. Referring now to Figure 3, what is depicted is the preprogram verification operation of the integrated memory circuit 100 as illustrated in Figure 1. Initially, a program address and input data patterns DQ na and DQ nb are provided to the second comparator 120 via step 310. DQ na and DQ nb are being latched by second comparator circuit 120 to provide signals DI na and DI nb respectively. The first comparator circuit 118 compares the input data patterns DI na and DI nb with the contents of the memory cells 110a and 110b respectively, and then output LBMATCHP signal and an HBMATCHP signal respectively via step 312. LBMATCHP will be at logic 0 whenever there is at least one bit in memory cells 110a that does not match with the corresponding bit of the input data pattern DQ na ; otherwise, LBMATCHP will be at logic 1. Similarly, HBMATCHP will be at logic 0 whenever there is at least one bit in memory cells 110b that does not match with the corresponding bits of the input data pattern DQ nb ; otherwise, HBMATCHP will be at logic 1. Next, it must be determined whether the contents of the memory cells 110a and 110b match the corresponding bit of the input data pattern DQ na and DQ nb via step 314. If each of the bits in the memory cells 110a and 110b matches with the corresponding bits of the input data pattern DQ na and DQ nb , the signals LBMATCHP and HBMATCHP will both be at logic 1. In response, a MATCH signal which is at logic 1 will be provided by the control circuit 116 indicating that no programming is required via step 316. When the MATCH signal is at logic 1, it is also known as the third program mode control signal. In case the contents of the memory cells 110a or 110b do not match with the input data pattern DQ na or DQ nb , the total number of bits that is required to be programmed must be determined via step 318. The summing circuit sums the number of bits of the input data patterns DQ na and DQ nb that are at logic 0 and generates signal X16PGM. When a bit of the input data pattern DQ na or DQ nb is at logic 0, it indicates that programming of the corresponding bit in memory cells 110a or 110b is required, since all the bits in the memory cells 110a and 110b are presumed to have been erased, that is, they were all at logic 1, immediately prior to the preprogram verification operation. Next, it must be determined whether the total number of bits required to be programmed is greater than 8 via step 320. If the total number of bits that is required to be programmed is greater than 8, which is indicated by X16PGM being at logic 0, a low byte or two-cycle programming will be performed via step 322. In case the total number of bits that is required to be programmed is greater than zero but is less than or equal to 8, then a word programming must be performed via step 324. In that case, both the high byte and the low byte will be programmed at the same time using one-cycle programming. Referring now to Figure 4A, what is shown is a flow chart showing the operation of the two-cycle or low byte programming in accordance with the present invention as illustrated in Figure 1 above. After the preprogram verification operation has determined that the total number of bits that is required to be programmed is greater than 8, the control circuit 116 will provide an LBPGM signal which is at logic 1 and an HBPGM signal which is at logic 0 via step 410. Next, both the LBPGM signal and the HBPGM signal are being fed back to the second comparator circuit 120 across lines 134a and 134b respectively. In response to the LBPGM signal being at logic 1, the second comparator circuit 120 will trigger the programming circuit 113 so that it couples the drain pump 136 to memory cells 110a via step 412. When the HBPGM signal is at logic 0, the second comparator 120 will not trigger the programming circuit 113 to couple the drain pump 136 to memory cells 110b. Accordingly, only memory cells 110a will be programmed. Next, the drain pump 136 will be turned on for a fixed amount of time, for example, 15 microseconds, to allow for adequate programming of the memory cells 110a. The amount of time for programming is determined through software or hardware (for example, by using a timer). Next, the LBPGM signal will be switched from being at logic 1 to logic 0 after the amount of time set for programming has elapsed and programming can be stopped by allowing the programming circuit 113 to disconnect the drain pump 136 from the memory cells 110a via step 414. Thereafter, a postprogram verification operation will be performed via step 416 which will be further explained in Figure 5. Turning now to Figure 4B, what is shown is a flow chart for one-cycle or word programming where all 16 bits are programmed simultaneously. When the number of bits that are required to be programmed is less than 8, then drain pump 136 will be able to couple to all 16 bits simultaneously and provide the current needed since only those bits that require programming (bits that are at logic 0) draw current. In this case, the control circuit 116 will provide LBPGM and HBPGM signals which are at logic 1 via step 440. Then, the second comparator circuit 120 triggers the programming circuit 113 to couple drain pump 136 to both memory cells 110a and 110b so that both memory cells 110a and 110b can be programmed at the same time via step 442. Again, the programming of memory cells 110a and 110b will last for a certain amount of time, which can be determined through software or hardware (for example, by using a timer). After the desired time has elapsed, then LBPGM and HBPGM signals will be reset to logic 0 and programming can be stopped by allowing the programming circuit 113 to disconnect the drain pump 136 from the memory cells 110a and 110b via step 444. Thereafter, a postprogram verification operation 416 will be performed which will be further explained in Figure 5. Turning now to Figure 5, what is shown is a postprogram verification operation of the integrated memory circuit 100 as illustrated in Figure 1. Initially, the second comparator 120 provides modified input data pattern DIM na and DIM nb via step 510. As stated earlier, immediately prior to the preprogram verification operation, memory cells 110a and 110b are assumed to have been fully erased, that is, they are all at logic 1. After the preprogram verification and programming operations, the number of bits that is still required to be programmed must be determined. A comparison between each corresponding bit of the memory cells 110a (or 110b) and the input data patterns DQ na are made to provide DIM na (or DIM nb ). As explained earlier, DIM na (or DIM nb ) has bits of information identical to the input pattern DQ na (or DQ nb ) except that if a bit in the input data pattern DQ na (or DQ nb ) and the corresponding bit in the memory cells 110a (or 110b), represented by DSI na (or DSI nb ) are both at logic 0, then the corresponding bit in the DIM na (or DIM nb ) will be at logic 1. When DIM na (or DIM nb ) is at logic 1, it indicates that no further programming is required for that bit. When a bit of the memory cells 110a (or 110b) is at logic 1 and the corresponding bit of the input data pattern DQ na (or DQ nb ) is at logic 0, the corresponding bit of the modified input data pattern DIM na (or DIM nb ) will be at logic 0. This indicates that programming is required for that bit. Accordingly, the number of memory cells that is required to be programmed after the preprogram verification and programming operation can be determined by summing the total number of bits of the modified input data patterns DIM na and DIM nb that are at logic 0. Next, it must be determined whether all the bits in memory cells 110a and 110b matches with the input data patterns DQ na and DQ nb via step 512. If they match, the control circuit 116 will output the third program mode control signal, represented by the MATCH signal which is at logic 1, via step 514. In this case, no further programming is required. If case step 512 determines that the contents of some of the memory cells, as represented by DSI na or DSI nb , do not match with the corresponding bits of the input data patterns DQ na or DQ nb , the total number of bits that is required to be programmed must be determined. The summing circuit 122 computes the number of bits that is still required to be programmed by summing the number of bits of the modified input data pattern DIM na and DIM nb that are at logic 0 via step 516. Thereafter, it must be determined whether the total number of bits to be programmed is greater than 8 via step 518. If it is determined that the total number of bits to be programmed is greater than 8, then a low byte programming can be performed via step 520 which is similar to what is illustrated in the flow chart of Figure 4A. On the other hand, if the total number of bits to be programmed is greater than zero, but less than or equal to 8, then a word programming can be performed via step 522 which is similar to what is illustrated in the flow chart of Figure 4B. The programming and postprogram verification operation can be repeated until it is determined that each of the bit in the memory cells 110a and 110b matches those in the input data pattern DQ n . When that happens, the memory cells 110a and 110b are said to have been programmed according to the input data pattern DQ n . With random input data patterns during a normal operation, it is likely that not all 16 bits of memory cells 110a and 110b need to be programmed. Therefore memory cells 110a and 110b may go through many one-cycle programming before a two-cycle programming is required. Hence, the programming time associated with this invention will not be appreciably higher than that of a circuit which always programs all 16 bits at one time by undesirabling doubling the number or the capacity of the drain pumps. Accordingly, an integrated memory circuit which has a plurality of memory cells can be programmed effectively by providing a program mode for programming the memory cells in accordance with a number of bits of the input data pattern and then programming the memory cells in accordance with the program mode so provided. In so doing, it avoids the undesirable increase in the number or the current capacity of drain pumps formed on such memory circuits thus reducing the complexity of the design and minimizing the size of the memory circuit. It should be understood that the above described embodiment is merely illustrative. For example, the number of bits to be programmed in a one-cycle programming can be adjusted to other values, such as 4. Similarly, the total number of cycles for the programming operation can be varied as required, for example, depending on the density of the integrated memory circuit. For instance, a 32 Mbit flash EPROM organized as 1 million blocks of 32 bits each may be programmed using a one-cycle, two-cycle, three-cycle and four-cycle programming. In that case, a conventional drain pump with current capacity to program 8 bits simultaneously may be used. Although an example of the present invention has been described and shown in the figures, one of ordinary skill in the art recognizes that there can be variations to the embodiments and those variations will be within the scope of the appended claims.

Claims: A method for controlling the programming of an integrated memory circuit (100) according to an input data pattern having a plurality of bits of information, each bit being either at a first logic level or at a second logic level, the circuit having a matrix of programmable memory cells, each memory cell storing one bit of information, the matrix of memory cells being organized into a plurality of blocks (110), each block including a plurality of groups (110a, 110b), and each group including a plurality of memory cells, the memory circuit further comprising means (136) for supplying a selected group with a programming voltage, the method comprising the steps of: (a) determining the total number of memory cells that is required to be programmed in a selected block; (b) providing a first program mode control signal if the total number of memory cells that is required to be programmed in a block is greater than zero but is less than or equal to a threshold number N indicative of the current capacity of the means supplying the programming voltage, providing a second program mode control signal if the total number of memory cells that is required to be programmed in a block is more than said threshold number N, and providing a third program mode control signal if the total number of memory cells that is required to be programmed in a block is equal to zero; (c) programming said plurality of groups of said selected block simultaneously if said first program mode control signal is provided, programming said plurality groups of said selected block sequentially if said second program mode control signal is provided, and not programming any of the memory cells of said selected block if said third program mode control signal is provided. A method according to claim 1 wherein the number of cells that is required to be programmed in a selected block is determined by: (i) comparing the logic level of each bit of the input data pattern addressed to said selected block with the logic level of each corresponding bit stored in the memory cells in said selected block, and (ii) computing the total number of memory cells in said selected block that is required to be programmed by summing the total number of bits of said input data pattern addressed to said selected block that are at the first logic level. A method as claimed in claim 2 further including a post program verification operation, said post program verification operation comprising the steps of: (a) determining the total number of memory cells that is required to be programmed in said selected block including: (i) comparing the logic level of each bit of the input data pattern addressed to said selected block with the logic level of each corresponding bit stored in the memory cells in said selected block, (ii) providing a modified input data pattern which has bits of information identical to the corresponding input data pattern, except that bits of said modified input data pattern are at the second logic level if the corresponding bits in the input data pattern and the memory cells are at the first logic level, and (iii) computing the total number of memory cells in said selected block that is required to be programmed by summing the total number of bits of the modified input data pattern addressed to said selected block that are at the first logic level; (b) providing said first program mode control signal if the total number of memory cells that is required to be programmed in a block is greater than zero but is less than or equal to a threshold number N indicative of the current capacity of the means supplying the programming voltage, providing said second program mode control signal if the total number of memory cells that is required to be programmed in a block is more than the threshold number N, and providing said third program mode control signal if the total number of memory cells that is required to be programmed in a block is equal to zero; (c) programming the plurality of groups of said selected block simultaneously if said first program mode control signal is provided, programming the plurality groups of said selected block sequentially if said second program mode control signal is provided, and not programming any of the memory cells of said selected block if said third program mode control signal is provided; and (d) repeating steps (a) to (c) until said third program mode control signal is provided. A method as claimed in any one of the claims 1-3 wherein the means supplying the programming voltage comprises at least one drain pump. A method as claimed in claim 2, wherein said step of computing the total number of memory cells in said selected block that is required to be programmed, comprises logically adding the number of bits of the input data pattern that are at the first logic level. A method as claimed in claim 2, wherein said step of computing the total number of memory cells in said selected block that is required to be programmed, comprises adding currents through a transistor circuit operatively coupled to the plurality of bits of the input data pattern. A method according to any one of the preceding claims, wherein N=8, the blocks comprise words, each word includes a first group and a second group, and each group includes 8 memory cells. An integrated memory circuit (100) responsive to an input data pattern having a plurality of bits of information, each bit being either at a first logic level or at a second logic level, the circuit having a matrix of programmable memory cells, each memory cell storing one bit of information, the matrix of memory cells being organised into a plurality of blocks (110), each block including a plurality of groups (110a, 110b) and each group includes a plurality of memory cells, and the circuit further comprising means (136) for supplying a selected group with a programming voltage, the circuit further comprising: a program mode determining circuit (112) for determining a program mode for programming the memory cells; and a programming means (113) operatively coupled to the program mode determining means for programming the memory cells in accordance with the program mode; wherein the program mode determining circuit (112) comprises a memory cell determining means (114) for determining the total number of memory cells that is required to be programmed; and a control means (116) providing: a first program mode control signal if the total number of memory cells that is required to be programmed is greater than zero but is less that or equal to a threshold number N, the threshold number N being indicative of the current capacity of the means supplying the programming voltage, and a second program mode control signal if the total number of memory cells that is required to be programmed is more than the said threshold number N, a third program mode control signal if the total number of memory cells that is required to be programmed in a block is equal to zero, and wherein the programming means programs the plurality of groups of said selected block simultaneously if said first program mode control signal is provided, programs said plurality of groups of said selected block sequentially if said second program mode control signal is provided, and programs none of the memory cells of said selected block if said third program mode control signal is provided. An integrated memory circuit according to claim 8 wherein the memory cell determining means comprises: comparator means (118) for comparing the logic level of each bit of the input data pattern addressed to a selected block with the logic level of each corresponding bit stored in the memory cells in the selected block, and means (122) for computing the total number of memory cells in the said selected block that is required to be programmed by summing the total number of bits of said input data pattern addressed to said selected block that are at the first logic level. An integrated memory circuit as claimed in claim 9, wherein said memory cell determining means further comprises: a second comparator means (120) for comparing the logic level of each bit of the input data pattern addressed to said selected block with the logic level of each corresponding bit stored in the memory cells, and providing a modified input data pattern which has bits of information identical to the input data pattern, except that bits of said modified input data pattern are at the second logic level if the corresponding bits in the input data pattern and the memory cells are at the first logic level, and a summing means (122) operatively coupled to said second comparator means for computing the total number of memory cells that is required to be programmed by summing the total number of bits of the modified input data pattern addressed to said selected block that are at the first logic level. An integrated memory circuit as claimed in claim 10, wherein said summing means comprises a logic adder or an analog adder. An integrated memory circuit as claimed in any one of the claims 8-11, wherein the means for supplying the programming voltage comprises at least one drain pump. An integrated memory circuit as claimed in claim 12 comprising a plurality of said drain pumps coupled by said programming circuit to said plurality of groups of memory cells for programming said plurality of groups of memory cells simultaneously in response to said first program mode control signal, and programming said plurality of groups of memory cells sequentially in response to said second program mode signal. An integrated memory circuit according to any one of the claims 8-13, wherein N=8, each block includes 2 groups and each group includes 8 memory cells.

Inventors: CHANG GEORGE, CHENG PEARL, CHANG, GEORGE, CHENG, PEARL
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES INC.
Application year: 1995
Main classification: G11C16
IPC codes: G11C17, G11C16, G11C7